rtl81x9var.h revision 1.21
1 /* $NetBSD: rtl81x9var.h,v 1.21 2006/06/18 21:29:48 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp 35 */ 36 37 #include "rnd.h" 38 39 #if NRND > 0 40 #include <sys/rnd.h> 41 #endif 42 43 #if defined(__i386__) || defined(__x86_64__) 44 #define RTK_ETHER_ALIGN 0 45 #else 46 #define RTK_ETHER_ALIGN 2 47 #endif 48 #define RTK_RXSTAT_LEN 4 49 50 struct rtk_type { 51 u_int16_t rtk_vid; 52 u_int16_t rtk_did; 53 int rtk_basetype; 54 const char *rtk_name; 55 }; 56 57 struct rtk_hwrev { 58 uint32_t rtk_rev; 59 int rtk_type; 60 const char *rtk_desc; 61 }; 62 63 struct rtk_mii_frame { 64 u_int8_t mii_stdelim; 65 u_int8_t mii_opcode; 66 u_int8_t mii_phyaddr; 67 u_int8_t mii_regaddr; 68 u_int8_t mii_turnaround; 69 u_int16_t mii_data; 70 }; 71 72 /* 73 * MII constants 74 */ 75 #define RTK_MII_STARTDELIM 0x01 76 #define RTK_MII_READOP 0x02 77 #define RTK_MII_WRITEOP 0x01 78 #define RTK_MII_TURNAROUND 0x02 79 80 #define RTK_8129 1 81 #define RTK_8139 2 82 #define RTK_8139CPLUS 3 83 #define RTK_8169 4 84 85 #define RTK_ISCPLUS(x) ((x)->rtk_type == RTK_8139CPLUS || \ 86 (x)->rtk_type == RTK_8169) 87 88 #define RTK_TX_QLEN 64 89 90 /* 91 * The 8139C+ and 8160 gigE chips support descriptor-based TX 92 * and RX. In fact, they even support TCP large send. Descriptors 93 * must be allocated in contiguous blocks that are aligned on a 94 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 95 */ 96 97 struct rtk_list_data { 98 struct rtk_txq { 99 struct mbuf *txq_mbuf; 100 bus_dmamap_t txq_dmamap; 101 int txq_descidx; 102 } rtk_txq[RTK_TX_QLEN]; 103 int rtk_txq_considx; 104 int rtk_txq_prodidx; 105 bus_dmamap_t rtk_tx_list_map; 106 struct rtk_desc *rtk_tx_list; 107 bus_dma_segment_t rtk_tx_listseg; 108 int rtk_tx_free; /* # of free descriptors */ 109 int rtk_tx_nextfree; /* next descriptor to use */ 110 int rtk_tx_desc_cnt; /* # of descriptors */ 111 int rtk_tx_listnseg; 112 113 struct mbuf *rtk_rx_mbuf[RTK_RX_DESC_CNT]; 114 bus_dmamap_t rtk_rx_dmamap[RTK_RX_DESC_CNT]; 115 bus_dmamap_t rtk_rx_list_map; 116 struct rtk_desc *rtk_rx_list; 117 bus_dma_segment_t rtk_rx_listseg; 118 int rtk_rx_prodidx; 119 int rtk_rx_listnseg; 120 }; 121 struct rtk_tx_desc { 122 SIMPLEQ_ENTRY(rtk_tx_desc) txd_q; 123 struct mbuf *txd_mbuf; 124 bus_dmamap_t txd_dmamap; 125 bus_addr_t txd_txaddr; 126 bus_addr_t txd_txstat; 127 }; 128 129 struct rtk_softc { 130 struct device sc_dev; /* generic device structures */ 131 struct ethercom ethercom; /* interface info */ 132 struct mii_data mii; 133 struct callout rtk_tick_ch; /* tick callout */ 134 bus_space_handle_t rtk_bhandle; /* bus space handle */ 135 bus_space_tag_t rtk_btag; /* bus space tag */ 136 int rtk_type; 137 bus_dma_tag_t sc_dmat; 138 bus_dma_segment_t sc_dmaseg; 139 int sc_dmanseg; 140 141 bus_dmamap_t recv_dmamap; 142 caddr_t rtk_rx_buf; 143 144 struct rtk_tx_desc rtk_tx_descs[RTK_TX_LIST_CNT]; 145 SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_free; 146 SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_dirty; 147 struct rtk_list_data rtk_ldata; 148 struct mbuf *rtk_head; 149 struct mbuf *rtk_tail; 150 u_int32_t rtk_rxlenmask; 151 int rtk_testmode; 152 153 int sc_flags; /* misc flags */ 154 int sc_txthresh; /* Early tx threshold */ 155 int sc_rev; /* revision within rtk_type */ 156 157 void *sc_sdhook; /* shutdown hook */ 158 void *sc_powerhook; /* power management hook */ 159 160 /* Power management hooks. */ 161 int (*sc_enable) (struct rtk_softc *); 162 void (*sc_disable) (struct rtk_softc *); 163 void (*sc_power) (struct rtk_softc *, int); 164 #if NRND > 0 165 rndsource_element_t rnd_source; 166 #endif 167 }; 168 169 #define RTK_TX_DESC_CNT(sc) \ 170 ((sc)->rtk_ldata.rtk_tx_desc_cnt) 171 #define RTK_TX_LIST_SZ(sc) \ 172 (RTK_TX_DESC_CNT(sc) * sizeof(struct rtk_desc)) 173 #define RTK_TX_DESC_INC(sc, x) \ 174 ((x) = ((x) + 1) % RTK_TX_DESC_CNT(sc)) 175 #define RTK_RX_DESC_INC(sc, x) \ 176 ((x) = ((x) + 1) % RTK_RX_DESC_CNT) 177 178 #define RTK_ATTACHED 0x00000001 /* attach has succeeded */ 179 #define RTK_ENABLED 0x00000002 /* chip is enabled */ 180 181 #define RTK_IS_ENABLED(sc) ((sc)->sc_flags & RTK_ENABLED) 182 #define RTK_TX_THRESH(sc) (((sc)->sc_txthresh << 16) & 0x003F0000) 183 184 #define TXTH_256 8 185 #define TXTH_MAX 48 186 187 /* 188 * register space access macros 189 */ 190 #define CSR_WRITE_4(sc, reg, val) \ 191 bus_space_write_4(sc->rtk_btag, sc->rtk_bhandle, reg, val) 192 #define CSR_WRITE_2(sc, reg, val) \ 193 bus_space_write_2(sc->rtk_btag, sc->rtk_bhandle, reg, val) 194 #define CSR_WRITE_1(sc, reg, val) \ 195 bus_space_write_1(sc->rtk_btag, sc->rtk_bhandle, reg, val) 196 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 197 bus_space_write_stream_4(sc->rtk_btag, sc->rtk_bhandle, reg, val) 198 199 200 #define CSR_READ_4(sc, reg) \ 201 bus_space_read_4(sc->rtk_btag, sc->rtk_bhandle, reg) 202 #define CSR_READ_2(sc, reg) \ 203 bus_space_read_2(sc->rtk_btag, sc->rtk_bhandle, reg) 204 #define CSR_READ_1(sc, reg) \ 205 bus_space_read_1(sc->rtk_btag, sc->rtk_bhandle, reg) 206 207 #define RTK_TIMEOUT 1000 208 209 /* 210 * PCI low memory base and low I/O base register, and 211 * other PCI registers. 212 */ 213 214 #define RTK_PCI_LOIO 0x10 215 #define RTK_PCI_LOMEM 0x14 216 217 #define RTK_PSTATE_MASK 0x0003 218 #define RTK_PSTATE_D0 0x0000 219 #define RTK_PSTATE_D1 0x0002 220 #define RTK_PSTATE_D2 0x0002 221 #define RTK_PSTATE_D3 0x0003 222 #define RTK_PME_EN 0x0010 223 #define RTK_PME_STATUS 0x8000 224 225 #ifdef _KERNEL 226 u_int16_t rtk_read_eeprom(struct rtk_softc *, int, int); 227 void rtk_setmulti(struct rtk_softc *); 228 void rtk_attach(struct rtk_softc *); 229 int rtk_detach(struct rtk_softc *); 230 int rtk_activate(struct device *, enum devact); 231 int rtk_intr(void *); 232 #endif /* _KERNEL */ 233
Indexes created Fri Sep 26 20:09:58 GMT 2025