rtl81x9var.h revision 1.37
1 /* $NetBSD: rtl81x9var.h,v 1.37 2006/11/25 02:42:18 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp 35 */ 36 37 #include "rnd.h" 38 39 #if NRND > 0 40 #include <sys/rnd.h> 41 #endif 42 43 #define RTK_ETHER_ALIGN 2 44 #define RTK_RXSTAT_LEN 4 45 46 #ifdef __NO_STRICT_ALIGNMENT 47 /* 48 * XXX According to PR kern/33763, some 8168 and variants can't DMA 49 * XXX RX packet data into unaligned buffer. This means such chips will 50 * XXX never work on !__NO_STRICT_ALIGNMENT hosts without copying buffer. 51 */ 52 #define RE_ETHER_ALIGN 0 53 #else 54 #define RE_ETHER_ALIGN 2 55 #endif 56 57 struct rtk_type { 58 uint16_t rtk_vid; 59 uint16_t rtk_did; 60 int rtk_basetype; 61 const char *rtk_name; 62 }; 63 64 struct rtk_hwrev { 65 uint32_t rtk_rev; 66 int rtk_type; 67 const char *rtk_desc; 68 }; 69 70 #define RTK_8129 1 71 #define RTK_8139 2 72 #define RTK_8139CPLUS 3 73 #define RTK_8169 4 74 75 #define RTK_ISCPLUS(x) ((x)->rtk_type == RTK_8139CPLUS || \ 76 (x)->rtk_type == RTK_8169) 77 78 79 struct rtk_mii_frame { 80 uint8_t mii_stdelim; 81 uint8_t mii_opcode; 82 uint8_t mii_phyaddr; 83 uint8_t mii_regaddr; 84 uint8_t mii_turnaround; 85 uint16_t mii_data; 86 }; 87 88 /* 89 * MII constants 90 */ 91 #define RTK_MII_STARTDELIM 0x01 92 #define RTK_MII_READOP 0x02 93 #define RTK_MII_WRITEOP 0x01 94 #define RTK_MII_TURNAROUND 0x02 95 96 97 /* 98 * The RealTek doesn't use a fragment-based descriptor mechanism. 99 * Instead, there are only four register sets, each or which represents 100 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 101 * packet buffer (32-bit aligned!) and we place the buffer addresses in 102 * the registers so the chip knows where they are. 103 * 104 * We can sort of kludge together the same kind of buffer management 105 * used in previous drivers, but we have to do buffer copies almost all 106 * the time, so it doesn't really buy us much. 107 * 108 * For reception, there's just one large buffer where the chip stores 109 * all received packets. 110 */ 111 112 #ifdef dreamcast 113 /* 114 * XXX dreamcast has only 32KB DMA'able memory on its PCI bridge. 115 * XXX Maybe this should be handled by prop_dictionary, or 116 * XXX some other new API which returns available DMA resources. 117 */ 118 #define RTK_RX_BUF_SZ RTK_RXBUF_16 119 #else 120 #define RTK_RX_BUF_SZ RTK_RXBUF_64 121 #endif 122 #define RTK_RXBUFLEN RTK_RXBUF_LEN(RTK_RX_BUF_SZ) 123 #define RTK_TX_LIST_CNT 4 124 125 /* 126 * The 8139C+ and 8169 gigE chips support descriptor-based TX 127 * and RX. In fact, they even support TCP large send. Descriptors 128 * must be allocated in contiguous blocks that are aligned on a 129 * 256-byte boundary. The RX rings can hold a maximum of 64 descriptors. 130 * The TX rings can hold upto 64 descriptors on 8139C+, and 131 * 1024 descriptors on 8169 gigE chips. 132 */ 133 #define RE_RING_ALIGN 256 134 135 /* 136 * Size of descriptors and TX queue. 137 * These numbers must be power of two to simplify RE_NEXT_*() macro. 138 */ 139 #define RE_RX_DESC_CNT 64 140 #define RE_TX_DESC_CNT_8139 64 141 #define RE_TX_DESC_CNT_8169 1024 142 #define RE_TX_QLEN 64 143 144 #define RE_NTXDESC_RSVD 4 145 146 struct re_rxsoft { 147 struct mbuf *rxs_mbuf; 148 bus_dmamap_t rxs_dmamap; 149 }; 150 151 struct re_txq { 152 struct mbuf *txq_mbuf; 153 bus_dmamap_t txq_dmamap; 154 int txq_descidx; 155 int txq_nsegs; 156 }; 157 158 struct re_list_data { 159 struct re_txq re_txq[RE_TX_QLEN]; 160 int re_txq_considx; 161 int re_txq_prodidx; 162 int re_txq_free; 163 164 bus_dmamap_t re_tx_list_map; 165 struct re_desc *re_tx_list; 166 int re_tx_free; /* # of free descriptors */ 167 int re_tx_nextfree; /* next descriptor to use */ 168 int re_tx_desc_cnt; /* # of descriptors */ 169 bus_dma_segment_t re_tx_listseg; 170 int re_tx_listnseg; 171 172 struct re_rxsoft re_rxsoft[RE_RX_DESC_CNT]; 173 bus_dmamap_t re_rx_list_map; 174 struct re_desc *re_rx_list; 175 int re_rx_prodidx; 176 bus_dma_segment_t re_rx_listseg; 177 int re_rx_listnseg; 178 }; 179 180 struct rtk_tx_desc { 181 SIMPLEQ_ENTRY(rtk_tx_desc) txd_q; 182 struct mbuf *txd_mbuf; 183 bus_dmamap_t txd_dmamap; 184 bus_addr_t txd_txaddr; 185 bus_addr_t txd_txstat; 186 }; 187 188 struct rtk_softc { 189 struct device sc_dev; /* generic device structures */ 190 struct ethercom ethercom; /* interface info */ 191 struct mii_data mii; 192 struct callout rtk_tick_ch; /* tick callout */ 193 bus_space_handle_t rtk_bhandle; /* bus space handle */ 194 bus_space_tag_t rtk_btag; /* bus space tag */ 195 int rtk_type; 196 bus_dma_tag_t sc_dmat; 197 198 bus_dma_segment_t sc_dmaseg; /* for rtk(4) */ 199 int sc_dmanseg; /* for rtk(4) */ 200 201 bus_dmamap_t recv_dmamap; /* for rtk(4) */ 202 caddr_t rtk_rx_buf; 203 204 struct rtk_tx_desc rtk_tx_descs[RTK_TX_LIST_CNT]; 205 SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_free; 206 SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_dirty; 207 208 struct re_list_data re_ldata; 209 struct mbuf *re_head; 210 struct mbuf *re_tail; 211 uint32_t re_rxlenmask; 212 int re_testmode; 213 214 int sc_flags; /* misc flags */ 215 int sc_txthresh; /* Early tx threshold */ 216 int sc_rev; /* revision within rtk_type */ 217 218 void *sc_sdhook; /* shutdown hook */ 219 void *sc_powerhook; /* power management hook */ 220 221 /* Power management hooks. */ 222 int (*sc_enable) (struct rtk_softc *); 223 void (*sc_disable) (struct rtk_softc *); 224 void (*sc_power) (struct rtk_softc *, int); 225 #if NRND > 0 226 rndsource_element_t rnd_source; 227 #endif 228 }; 229 230 #define RE_TX_DESC_CNT(sc) ((sc)->re_ldata.re_tx_desc_cnt) 231 #define RE_TX_LIST_SZ(sc) (RE_TX_DESC_CNT(sc) * sizeof(struct re_desc)) 232 #define RE_NEXT_TX_DESC(sc, x) (((x) + 1) & (RE_TX_DESC_CNT(sc) - 1)) 233 234 #define RE_RX_LIST_SZ (RE_RX_DESC_CNT * sizeof(struct re_desc)) 235 #define RE_NEXT_RX_DESC(sc, x) (((x) + 1) & (RE_RX_DESC_CNT - 1)) 236 237 #define RE_NEXT_TXQ(sc, x) (((x) + 1) & (RE_TX_QLEN - 1)) 238 239 #define RE_TXDESCSYNC(sc, idx, ops) \ 240 bus_dmamap_sync((sc)->sc_dmat, \ 241 (sc)->re_ldata.re_tx_list_map, \ 242 sizeof(struct re_desc) * (idx), \ 243 sizeof(struct re_desc), \ 244 (ops)) 245 #define RE_RXDESCSYNC(sc, idx, ops) \ 246 bus_dmamap_sync((sc)->sc_dmat, \ 247 (sc)->re_ldata.re_rx_list_map, \ 248 sizeof(struct re_desc) * (idx), \ 249 sizeof(struct re_desc), \ 250 (ops)) 251 252 /* 253 * re(4) hardware ip4csum-tx could be mangled with 28 byte or less IP packets 254 */ 255 #define RE_IP4CSUMTX_MINLEN 28 256 #define RE_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RE_IP4CSUMTX_MINLEN) 257 /* 258 * XXX 259 * We are allocating pad DMA buffer after RX DMA descs for now 260 * because RE_TX_LIST_SZ(sc) always occupies whole page but 261 * RE_RX_LIST_SZ is less than PAGE_SIZE so there is some unused region. 262 */ 263 #define RE_RX_DMAMEM_SZ (RE_RX_LIST_SZ + RE_IP4CSUMTX_PADLEN) 264 #define RE_TXPADOFF RE_RX_LIST_SZ 265 #define RE_TXPADDADDR(sc) \ 266 ((sc)->re_ldata.re_rx_list_map->dm_segs[0].ds_addr + RE_TXPADOFF) 267 268 269 #define RTK_ATTACHED 0x00000001 /* attach has succeeded */ 270 #define RTK_ENABLED 0x00000002 /* chip is enabled */ 271 272 #define RTK_IS_ENABLED(sc) ((sc)->sc_flags & RTK_ENABLED) 273 274 #define RTK_TXTH_MAX RTK_TXTH_1536 275 276 /* 277 * register space access macros 278 */ 279 #define CSR_WRITE_4(sc, reg, val) \ 280 bus_space_write_4(sc->rtk_btag, sc->rtk_bhandle, reg, val) 281 #define CSR_WRITE_2(sc, reg, val) \ 282 bus_space_write_2(sc->rtk_btag, sc->rtk_bhandle, reg, val) 283 #define CSR_WRITE_1(sc, reg, val) \ 284 bus_space_write_1(sc->rtk_btag, sc->rtk_bhandle, reg, val) 285 286 #define CSR_READ_4(sc, reg) \ 287 bus_space_read_4(sc->rtk_btag, sc->rtk_bhandle, reg) 288 #define CSR_READ_2(sc, reg) \ 289 bus_space_read_2(sc->rtk_btag, sc->rtk_bhandle, reg) 290 #define CSR_READ_1(sc, reg) \ 291 bus_space_read_1(sc->rtk_btag, sc->rtk_bhandle, reg) 292 293 #define RTK_TIMEOUT 1000 294 295 /* 296 * PCI low memory base and low I/O base registers 297 */ 298 299 #define RTK_PCI_LOIO 0x10 300 #define RTK_PCI_LOMEM 0x14 301 302 #ifdef _KERNEL 303 uint16_t rtk_read_eeprom(struct rtk_softc *, int, int); 304 void rtk_setmulti(struct rtk_softc *); 305 void rtk_attach(struct rtk_softc *); 306 int rtk_detach(struct rtk_softc *); 307 int rtk_activate(struct device *, enum devact); 308 int rtk_intr(void *); 309 #endif /* _KERNEL */ 310
Indexes created Sat Sep 27 14:09:57 GMT 2025