rtsx.c revision 1.1.6.2
1 /* $NetBSD: rtsx.c,v 1.1.6.2 2014/05/22 11:40:22 yamt Exp $ */ 2 /* $OpenBSD: rtsx.c,v 1.7 2013/12/08 18:31:03 stsp Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * Copyright (c) 2012 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Realtek RTS5209/RTS5229 Card Reader driver. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: rtsx.c,v 1.1.6.2 2014/05/22 11:40:22 yamt Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/systm.h> 32 #include <sys/proc.h> 33 #include <sys/mutex.h> 34 35 #include <dev/ic/rtsxreg.h> 36 #include <dev/ic/rtsxvar.h> 37 38 #include <dev/sdmmc/sdmmcvar.h> 39 #include <dev/sdmmc/sdmmc_ioreg.h> 40 41 /* 42 * We use two DMA buffers, a command buffer and a data buffer. 43 * 44 * The command buffer contains a command queue for the host controller, 45 * which describes SD/MMC commands to run, and other parameters. The chip 46 * runs the command queue when a special bit in the RTSX_HCBAR register is set 47 * and signals completion with the TRANS_OK interrupt. 48 * Each command is encoded as a 4 byte sequence containing command number 49 * (read, write, or check a host controller register), a register address, 50 * and a data bit-mask and value. 51 * 52 * The data buffer is used to transfer data sectors to or from the SD card. 53 * Data transfer is controlled via the RTSX_HDBAR register. Completion is 54 * also signalled by the TRANS_OK interrupt. 55 * 56 * The chip is unable to perform DMA above 4GB. 57 * 58 * SD/MMC commands which do not transfer any data from/to the card only use 59 * the command buffer. 60 */ 61 62 #define RTSX_DMA_MAX_SEGSIZE 0x80000 63 #define RTSX_HOSTCMD_MAX 256 64 #define RTSX_HOSTCMD_BUFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX) 65 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 66 67 #define READ4(sc, reg) \ 68 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 69 #define WRITE4(sc, reg, val) \ 70 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 71 72 #define RTSX_READ(sc, reg, val) \ 73 do { \ 74 int err = rtsx_read((sc), (reg), (val)); \ 75 if (err) \ 76 return err; \ 77 } while (/*CONSTCOND*/0) 78 79 #define RTSX_WRITE(sc, reg, val) \ 80 do { \ 81 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 82 if (err) \ 83 return err; \ 84 } while (/*CONSTCOND*/0) 85 86 #define RTSX_CLR(sc, reg, bits) \ 87 do { \ 88 int err = rtsx_write((sc), (reg), (bits), 0); \ 89 if (err) \ 90 return err; \ 91 } while (/*CONSTCOND*/0) 92 93 #define RTSX_SET(sc, reg, bits) \ 94 do { \ 95 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 96 if (err) \ 97 return err; \ 98 } while (/*CONSTCOND*/0) 99 100 static int rtsx_host_reset(sdmmc_chipset_handle_t); 101 static uint32_t rtsx_host_ocr(sdmmc_chipset_handle_t); 102 static int rtsx_host_maxblklen(sdmmc_chipset_handle_t); 103 static int rtsx_card_detect(sdmmc_chipset_handle_t); 104 static int rtsx_write_protect(sdmmc_chipset_handle_t); 105 static int rtsx_bus_power(sdmmc_chipset_handle_t, uint32_t); 106 static int rtsx_bus_clock(sdmmc_chipset_handle_t, int); 107 static int rtsx_bus_width(sdmmc_chipset_handle_t, int); 108 static int rtsx_bus_rod(sdmmc_chipset_handle_t, int); 109 static void rtsx_exec_command(sdmmc_chipset_handle_t, 110 struct sdmmc_command *); 111 static int rtsx_init(struct rtsx_softc *, int); 112 static void rtsx_soft_reset(struct rtsx_softc *); 113 static int rtsx_bus_power_off(struct rtsx_softc *); 114 static int rtsx_bus_power_on(struct rtsx_softc *); 115 static int rtsx_set_bus_width(struct rtsx_softc *, int); 116 static int rtsx_stop_sd_clock(struct rtsx_softc *); 117 static int rtsx_switch_sd_clock(struct rtsx_softc *, uint8_t, int, int); 118 static int rtsx_wait_intr(struct rtsx_softc *, int, int); 119 static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *); 120 static int rtsx_write(struct rtsx_softc *, uint16_t, uint8_t, uint8_t); 121 #ifdef notyet 122 static int rtsx_read_phy(struct rtsx_softc *, uint8_t, uint16_t *); 123 #endif 124 static int rtsx_write_phy(struct rtsx_softc *, uint8_t, uint16_t); 125 static int rtsx_read_cfg(struct rtsx_softc *, uint8_t, uint16_t, 126 uint32_t *); 127 #ifdef notyet 128 static int rtsx_write_cfg(struct rtsx_softc *, uint8_t, uint16_t, uint32_t, 129 uint32_t); 130 #endif 131 static void rtsx_hostcmd(uint32_t *, int *, uint8_t, uint16_t, uint8_t, 132 uint8_t); 133 static int rtsx_hostcmd_send(struct rtsx_softc *, int); 134 static uint8_t rtsx_response_type(uint16_t); 135 static int rtsx_read_ppbuf(struct rtsx_softc *, struct sdmmc_command *, 136 uint32_t *); 137 static int rtsx_write_ppbuf(struct rtsx_softc *, struct sdmmc_command *, 138 uint32_t *); 139 static int rtsx_exec_short_xfer(struct rtsx_softc *, 140 struct sdmmc_command *, uint32_t *, uint8_t); 141 static int rtsx_xfer(struct rtsx_softc *, struct sdmmc_command *, 142 uint32_t *); 143 static void rtsx_card_insert(struct rtsx_softc *); 144 static void rtsx_card_eject(struct rtsx_softc *); 145 static int rtsx_led_enable(struct rtsx_softc *); 146 static int rtsx_led_disable(struct rtsx_softc *); 147 static void rtsx_save_regs(struct rtsx_softc *); 148 static void rtsx_restore_regs(struct rtsx_softc *); 149 150 #ifdef RTSX_DEBUG 151 int rtsxdebug = 0; 152 #define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0) 153 #else 154 #define DPRINTF(n,s) /**/ 155 #endif 156 157 #define DEVNAME(sc) SDMMCDEVNAME(sc) 158 159 static struct sdmmc_chip_functions rtsx_chip_functions = { 160 /* host controller reset */ 161 .host_reset = rtsx_host_reset, 162 163 /* host controller capabilities */ 164 .host_ocr = rtsx_host_ocr, 165 .host_maxblklen = rtsx_host_maxblklen, 166 167 /* card detection */ 168 .card_detect = rtsx_card_detect, 169 170 /* write protect */ 171 .write_protect = rtsx_write_protect, 172 173 /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */ 174 .bus_power = rtsx_bus_power, 175 .bus_clock = rtsx_bus_clock, 176 .bus_width = rtsx_bus_width, 177 .bus_rod = rtsx_bus_rod, 178 179 /* command execution */ 180 .exec_command = rtsx_exec_command, 181 182 /* card interrupt */ 183 .card_enable_intr = NULL, 184 .card_intr_ack = NULL, 185 }; 186 187 /* 188 * Called by attachment driver. 189 */ 190 int 191 rtsx_attach(struct rtsx_softc *sc, bus_space_tag_t iot, 192 bus_space_handle_t ioh, bus_size_t iosize, bus_dma_tag_t dmat, int flags) 193 { 194 struct sdmmcbus_attach_args saa; 195 uint32_t sdio_cfg; 196 197 sc->sc_iot = iot; 198 sc->sc_ioh = ioh; 199 sc->sc_iosize = iosize; 200 sc->sc_dmat = dmat; 201 sc->sc_flags = flags; 202 203 mutex_init(&sc->sc_host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 204 mutex_init(&sc->sc_intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 205 cv_init(&sc->sc_intr_cv, "rtsxintr"); 206 207 if (rtsx_init(sc, 1)) 208 goto error; 209 210 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 211 if (sdio_cfg & (RTSX_SDIOCFG_SDIO_ONLY|RTSX_SDIOCFG_HAVE_SDIO)){ 212 sc->sc_flags |= RTSX_F_SDIO_SUPPORT; 213 } 214 } 215 216 if (bus_dmamap_create(sc->sc_dmat, RTSX_HOSTCMD_BUFSIZE, 1, 217 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, &sc->sc_dmap_cmd) != 0) 218 goto error; 219 220 /* 221 * Attach the generic SD/MMC bus driver. (The bus driver must 222 * not invoke any chipset functions before it is attached.) 223 */ 224 memset(&saa, 0, sizeof(saa)); 225 saa.saa_busname = "sdmmc"; 226 saa.saa_sct = &rtsx_chip_functions; 227 saa.saa_spi_sct = NULL; 228 saa.saa_sch = sc; 229 saa.saa_dmat = sc->sc_dmat; 230 saa.saa_clkmin = SDMMC_SDCLK_400K; 231 saa.saa_clkmax = 25000; 232 saa.saa_caps = SMC_CAPS_DMA|SMC_CAPS_4BIT_MODE; 233 234 sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); 235 if (sc->sc_sdmmc == NULL) 236 goto destroy_dmamap_cmd; 237 238 /* Now handle cards discovered during attachment. */ 239 if (ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT)) 240 rtsx_card_insert(sc); 241 242 return 0; 243 244 destroy_dmamap_cmd: 245 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmap_cmd); 246 error: 247 cv_destroy(&sc->sc_intr_cv); 248 mutex_destroy(&sc->sc_intr_mtx); 249 mutex_destroy(&sc->sc_host_mtx); 250 return 1; 251 } 252 253 int 254 rtsx_detach(struct rtsx_softc *sc, int flags) 255 { 256 int rv; 257 258 if (sc->sc_sdmmc != NULL) { 259 rv = config_detach(sc->sc_sdmmc, flags); 260 if (rv != 0) 261 return rv; 262 sc->sc_sdmmc = NULL; 263 } 264 265 /* disable interrupts */ 266 if ((flags & DETACH_FORCE) == 0) { 267 WRITE4(sc, RTSX_BIER, 0); 268 rtsx_soft_reset(sc); 269 } 270 271 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmap_cmd); 272 cv_destroy(&sc->sc_intr_cv); 273 mutex_destroy(&sc->sc_intr_mtx); 274 mutex_destroy(&sc->sc_host_mtx); 275 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 276 277 return 0; 278 } 279 280 bool 281 rtsx_suspend(device_t dev, const pmf_qual_t *qual) 282 { 283 struct rtsx_softc *sc = device_private(dev); 284 285 /* Save the host controller state. */ 286 rtsx_save_regs(sc); 287 288 return true; 289 } 290 291 bool 292 rtsx_resume(device_t dev, const pmf_qual_t *qual) 293 { 294 struct rtsx_softc *sc = device_private(dev); 295 296 /* Restore the host controller state. */ 297 rtsx_restore_regs(sc); 298 299 if (READ4(sc, RTSX_BIPR) & RTSX_SD_EXIST) 300 rtsx_card_insert(sc); 301 else 302 rtsx_card_eject(sc); 303 304 return true; 305 } 306 307 bool 308 rtsx_shutdown(device_t dev, int flags) 309 { 310 struct rtsx_softc *sc = device_private(dev); 311 312 /* XXX chip locks up if we don't disable it before reboot. */ 313 (void)rtsx_host_reset(sc); 314 315 return true; 316 } 317 318 static int 319 rtsx_init(struct rtsx_softc *sc, int attaching) 320 { 321 uint32_t status; 322 uint8_t ver; 323 int error; 324 325 /* Read IC version from dummy register. */ 326 if (sc->sc_flags & RTSX_F_5229) { 327 RTSX_READ(sc, RTSX_DUMMY_REG, &ver); 328 switch (ver & 0x0f) { 329 case RTSX_IC_VERSION_A: 330 case RTSX_IC_VERSION_B: 331 case RTSX_IC_VERSION_D: 332 break; 333 case RTSX_IC_VERSION_C: 334 sc->sc_flags |= RTSX_F_5229_TYPE_C; 335 break; 336 default: 337 aprint_error_dev(sc->sc_dev, "unknown ic %02x\n", ver); 338 return 1; 339 } 340 } 341 342 /* Enable interrupt write-clear (default is read-clear). */ 343 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 344 345 /* Clear any pending interrupts. */ 346 status = READ4(sc, RTSX_BIPR); 347 WRITE4(sc, RTSX_BIPR, status); 348 349 /* Check for cards already inserted at attach time. */ 350 if (attaching && (status & RTSX_SD_EXIST)) 351 sc->sc_flags |= RTSX_F_CARD_PRESENT; 352 353 /* Enable interrupts. */ 354 WRITE4(sc, RTSX_BIER, 355 RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN); 356 357 /* Power on SSC clock. */ 358 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 359 delay(200); 360 361 /* XXX magic numbers from linux driver */ 362 if (sc->sc_flags & RTSX_F_5209) 363 error = rtsx_write_phy(sc, 0x00, 0xB966); 364 else 365 error = rtsx_write_phy(sc, 0x00, 0xBA42); 366 if (error) { 367 aprint_error_dev(sc->sc_dev, "couldn't write phy register\n"); 368 return 1; 369 } 370 371 RTSX_SET(sc, RTSX_CLK_DIV, 0x07); 372 373 /* Disable sleep mode. */ 374 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 375 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 376 377 /* Disable card clock. */ 378 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 379 380 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 381 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG | 0x04); 382 RTSX_WRITE(sc, RTSX_SD30_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_3V3); 383 384 /* Enable SSC clock. */ 385 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 386 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 387 388 RTSX_SET(sc, RTSX_CHANGE_LINK_STATE, RTSX_MAC_PHY_RST_N_DBG); 389 RTSX_SET(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT); 390 391 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 392 393 /* Set RC oscillator to 400K. */ 394 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 395 396 /* Request clock by driving CLKREQ pin to zero. */ 397 RTSX_SET(sc, RTSX_PETXCFG, RTSX_PETXCFG_CLKREQ_PIN); 398 399 /* Set up LED GPIO. */ 400 if (sc->sc_flags & RTSX_F_5209) { 401 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 402 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 403 } else { 404 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 405 /* Switch LDO3318 source from DV33 to 3V3. */ 406 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 407 RTSX_SET(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_3V3); 408 /* Set default OLT blink period. */ 409 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_PERIOD); 410 } 411 412 return 0; 413 } 414 415 int 416 rtsx_led_enable(struct rtsx_softc *sc) 417 { 418 419 if (sc->sc_flags & RTSX_F_5209) { 420 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 421 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 422 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 423 } else { 424 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 425 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 426 } 427 428 return 0; 429 } 430 431 int 432 rtsx_led_disable(struct rtsx_softc *sc) 433 { 434 435 if (sc->sc_flags & RTSX_F_5209) { 436 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 437 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 438 } else { 439 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 440 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 441 } 442 443 return 0; 444 } 445 446 /* 447 * Reset the host controller. Called during initialization, when 448 * cards are removed, upon resume, and during error recovery. 449 */ 450 int 451 rtsx_host_reset(sdmmc_chipset_handle_t sch) 452 { 453 struct rtsx_softc *sc = sch; 454 int error; 455 456 DPRINTF(1,("%s: host reset\n", DEVNAME(sc))); 457 458 mutex_enter(&sc->sc_host_mtx); 459 460 if (ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT)) 461 rtsx_soft_reset(sc); 462 463 error = rtsx_init(sc, 0); 464 465 mutex_exit(&sc->sc_host_mtx); 466 467 return error; 468 } 469 470 static uint32_t 471 rtsx_host_ocr(sdmmc_chipset_handle_t sch) 472 { 473 474 return RTSX_SUPPORT_VOLTAGE; 475 } 476 477 static int 478 rtsx_host_maxblklen(sdmmc_chipset_handle_t sch) 479 { 480 481 return 512; 482 } 483 484 /* 485 * Return non-zero if the card is currently inserted. 486 */ 487 static int 488 rtsx_card_detect(sdmmc_chipset_handle_t sch) 489 { 490 struct rtsx_softc *sc = sch; 491 492 return ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT); 493 } 494 495 static int 496 rtsx_write_protect(sdmmc_chipset_handle_t sch) 497 { 498 499 return 0; /* XXX */ 500 } 501 502 /* 503 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 504 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 505 * it is a mask of *enabled* gates. 506 */ 507 508 static int 509 rtsx_bus_power_off(struct rtsx_softc *sc) 510 { 511 int error; 512 uint8_t disable3; 513 514 error = rtsx_stop_sd_clock(sc); 515 if (error) 516 return error; 517 518 /* Disable SD output. */ 519 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_CARD_OUTPUT_EN); 520 521 /* Turn off power. */ 522 disable3 = RTSX_PULL_CTL_DISABLE3; 523 if (sc->sc_flags & RTSX_F_5209) 524 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 525 else { 526 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1 | 527 RTSX_LDO3318_VCC2); 528 if (sc->sc_flags & RTSX_F_5229_TYPE_C) 529 disable3 = RTSX_PULL_CTL_DISABLE3_TYPE_C; 530 } 531 532 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 533 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 534 535 /* Disable pull control. */ 536 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 537 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 538 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, disable3); 539 540 return 0; 541 } 542 543 static int 544 rtsx_bus_power_on(struct rtsx_softc *sc) 545 { 546 uint8_t enable3; 547 548 /* Select SD card. */ 549 RTSX_WRITE(sc, RTSX_CARD_SELECT, RTSX_SD_MOD_SEL); 550 RTSX_WRITE(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_48_SD); 551 RTSX_SET(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 552 553 /* Enable pull control. */ 554 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 555 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 556 if (sc->sc_flags & RTSX_F_5229_TYPE_C) 557 enable3 = RTSX_PULL_CTL_ENABLE3_TYPE_C; 558 else 559 enable3 = RTSX_PULL_CTL_ENABLE3; 560 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, enable3); 561 562 /* 563 * To avoid a current peak, enable card power in two phases with a 564 * delay in between. 565 */ 566 567 /* Partial power. */ 568 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PARTIAL_PWR_ON); 569 if (sc->sc_flags & RTSX_F_5209) 570 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_SUSPEND); 571 else 572 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1); 573 574 delay(200); 575 576 /* Full power. */ 577 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 578 if (sc->sc_flags & RTSX_F_5209) 579 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 580 else 581 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC2); 582 583 /* Enable SD card output. */ 584 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 585 586 return 0; 587 } 588 589 static int 590 rtsx_set_bus_width(struct rtsx_softc *sc, int width) 591 { 592 uint32_t bus_width; 593 594 DPRINTF(1,("%s: bus width=%d\n", DEVNAME(sc), width)); 595 596 switch (width) { 597 case 8: 598 bus_width = RTSX_BUS_WIDTH_8; 599 break; 600 case 4: 601 bus_width = RTSX_BUS_WIDTH_4; 602 break; 603 case 1: 604 bus_width = RTSX_BUS_WIDTH_1; 605 break; 606 default: 607 return EINVAL; 608 } 609 610 if (bus_width == RTSX_BUS_WIDTH_1) 611 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK); 612 else 613 RTSX_SET(sc, RTSX_SD_CFG1, bus_width); 614 615 return 0; 616 } 617 618 static int 619 rtsx_stop_sd_clock(struct rtsx_softc *sc) 620 { 621 622 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 623 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 624 625 return 0; 626 } 627 628 static int 629 rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t n, int div, int mcu) 630 { 631 632 /* Enable SD 2.0 mode. */ 633 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK); 634 635 RTSX_SET(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 636 637 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 638 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 639 RTSX_CLR(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_SEL_MASK); 640 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 641 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 642 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 643 RTSX_CLR(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK); 644 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 645 RTSX_SET(sc, RTSX_SSC_CTL1, RTSX_RSTB); 646 delay(100); 647 648 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 649 650 return 0; 651 } 652 653 /* 654 * Set or change SD bus voltage and enable or disable SD bus power. 655 * Return zero on success. 656 */ 657 static int 658 rtsx_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 659 { 660 struct rtsx_softc *sc = sch; 661 int error = 0; 662 663 DPRINTF(1,("%s: voltage change ocr=0x%x\n", DEVNAME(sc), ocr)); 664 665 mutex_enter(&sc->sc_host_mtx); 666 667 /* 668 * Disable bus power before voltage change. 669 */ 670 error = rtsx_bus_power_off(sc); 671 if (error) 672 goto ret; 673 674 delay(200); 675 676 /* If power is disabled, reset the host and return now. */ 677 if (ocr == 0) { 678 mutex_exit(&sc->sc_host_mtx); 679 (void)rtsx_host_reset(sc); 680 return 0; 681 } 682 683 if (!ISSET(ocr, RTSX_SUPPORT_VOLTAGE)) { 684 /* Unsupported voltage level requested. */ 685 DPRINTF(1,("%s: unsupported voltage ocr=0x%x\n", 686 DEVNAME(sc), ocr)); 687 error = EINVAL; 688 goto ret; 689 } 690 691 error = rtsx_set_bus_width(sc, 1); 692 if (error) 693 goto ret; 694 695 error = rtsx_bus_power_on(sc); 696 ret: 697 mutex_exit(&sc->sc_host_mtx); 698 699 return error; 700 } 701 702 /* 703 * Set or change SDCLK frequency or disable the SD clock. 704 * Return zero on success. 705 */ 706 static int 707 rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq) 708 { 709 struct rtsx_softc *sc = sch; 710 uint8_t n; 711 int div; 712 int mcu; 713 int error = 0; 714 715 DPRINTF(1,("%s: bus clock change freq=%d\n", DEVNAME(sc), freq)); 716 717 mutex_enter(&sc->sc_host_mtx); 718 719 if (freq == SDMMC_SDCLK_OFF) { 720 error = rtsx_stop_sd_clock(sc); 721 goto ret; 722 } 723 724 /* 725 * Configure the clock frequency. 726 */ 727 switch (freq) { 728 case SDMMC_SDCLK_400K: 729 n = 80; /* minimum */ 730 div = RTSX_CLK_DIV_8; 731 mcu = 7; 732 RTSX_SET(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128); 733 break; 734 case 20000: 735 n = 80; 736 div = RTSX_CLK_DIV_4; 737 mcu = 7; 738 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 739 break; 740 case 25000: 741 n = 100; 742 div = RTSX_CLK_DIV_4; 743 mcu = 7; 744 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 745 break; 746 case 30000: 747 n = 120; 748 div = RTSX_CLK_DIV_4; 749 mcu = 7; 750 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 751 break; 752 case 40000: 753 n = 80; 754 div = RTSX_CLK_DIV_2; 755 mcu = 7; 756 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 757 break; 758 case 50000: 759 n = 100; 760 div = RTSX_CLK_DIV_2; 761 mcu = 6; 762 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 763 break; 764 default: 765 error = EINVAL; 766 goto ret; 767 } 768 769 /* 770 * Enable SD clock. 771 */ 772 error = rtsx_switch_sd_clock(sc, n, div, mcu); 773 ret: 774 mutex_exit(&sc->sc_host_mtx); 775 776 return error; 777 } 778 779 static int 780 rtsx_bus_width(sdmmc_chipset_handle_t sch, int width) 781 { 782 struct rtsx_softc *sc = sch; 783 784 return rtsx_set_bus_width(sc, width); 785 } 786 787 static int 788 rtsx_bus_rod(sdmmc_chipset_handle_t sch, int on) 789 { 790 791 /* Not support */ 792 return -1; 793 } 794 795 static int 796 rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val) 797 { 798 int tries = 1024; 799 uint32_t reg; 800 801 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY | 802 (uint32_t)((addr & 0x3FFF) << 16)); 803 804 while (tries--) { 805 reg = READ4(sc, RTSX_HAIMR); 806 if (!(reg & RTSX_HAIMR_BUSY)) 807 break; 808 } 809 810 *val = (reg & 0xff); 811 return (tries == 0) ? ETIMEDOUT : 0; 812 } 813 814 static int 815 rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val) 816 { 817 int tries = 1024; 818 uint32_t reg; 819 820 WRITE4(sc, RTSX_HAIMR, 821 RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 822 (uint32_t)(((addr & 0x3FFF) << 16) | 823 (mask << 8) | val)); 824 825 while (tries--) { 826 reg = READ4(sc, RTSX_HAIMR); 827 if (!(reg & RTSX_HAIMR_BUSY)) { 828 if (val != (reg & 0xff)) 829 return EIO; 830 return 0; 831 } 832 } 833 return ETIMEDOUT; 834 } 835 836 #ifdef notyet 837 static int 838 rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val) 839 { 840 int timeout = 100000; 841 uint8_t data0; 842 uint8_t data1; 843 uint8_t rwctl; 844 845 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 846 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_READ); 847 848 while (timeout--) { 849 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 850 if (!(rwctl & RTSX_PHY_BUSY)) 851 break; 852 } 853 if (timeout == 0) 854 return ETIMEDOUT; 855 856 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 857 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 858 *val = data0 | (data1 << 8); 859 860 return 0; 861 } 862 #endif 863 864 static int 865 rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val) 866 { 867 int timeout = 100000; 868 uint8_t rwctl; 869 870 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 871 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 872 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 873 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_WRITE); 874 875 while (timeout--) { 876 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 877 if (!(rwctl & RTSX_PHY_BUSY)) 878 break; 879 } 880 if (timeout == 0) 881 return ETIMEDOUT; 882 883 return 0; 884 } 885 886 static int 887 rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val) 888 { 889 int tries = 1024; 890 uint8_t data0, data1, data2, data3, rwctl; 891 892 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 893 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 894 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 895 896 while (tries--) { 897 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 898 if (!(rwctl & RTSX_CFG_BUSY)) 899 break; 900 } 901 if (tries == 0) 902 return EIO; 903 904 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 905 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 906 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 907 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 908 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 909 910 return 0; 911 } 912 913 #ifdef notyet 914 static int 915 rtsx_write_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, 916 uint32_t mask, uint32_t val) 917 { 918 uint32_t writemask = 0; 919 int i, tries = 1024; 920 uint8_t rwctl; 921 922 for (i = 0; i < 4; i++) { 923 if (mask & 0xff) { 924 RTSX_WRITE(sc, RTSX_CFGDATA0 + i, val & mask & 0xff); 925 writemask |= (1 << i); 926 } 927 mask >>= 8; 928 val >>= 8; 929 } 930 931 if (writemask) { 932 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 933 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 934 RTSX_WRITE(sc, RTSX_CFGRWCTL, 935 RTSX_CFG_BUSY | writemask | (func & 0x03 << 4)); 936 } 937 938 while (tries--) { 939 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 940 if (!(rwctl & RTSX_CFG_BUSY)) 941 break; 942 } 943 if (tries == 0) 944 return EIO; 945 946 return 0; 947 } 948 #endif 949 950 /* Append a properly encoded host command to the host command buffer. */ 951 static void 952 rtsx_hostcmd(uint32_t *cmdbuf, int *n, uint8_t cmd, uint16_t reg, 953 uint8_t mask, uint8_t data) 954 { 955 956 KASSERT(*n < RTSX_HOSTCMD_MAX); 957 958 cmdbuf[(*n)++] = htole32((uint32_t)(cmd & 0x3) << 30) | 959 ((uint32_t)(reg & 0x3fff) << 16) | 960 ((uint32_t)(mask) << 8) | 961 ((uint32_t)data); 962 } 963 964 static void 965 rtsx_save_regs(struct rtsx_softc *sc) 966 { 967 int i; 968 uint16_t reg; 969 970 mutex_enter(&sc->sc_host_mtx); 971 972 i = 0; 973 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 974 (void)rtsx_read(sc, reg, &sc->sc_regs[i++]); 975 for (reg = 0xFD52; reg < 0xFD69; reg++) 976 (void)rtsx_read(sc, reg, &sc->sc_regs[i++]); 977 for (reg = 0xFE20; reg < 0xFE34; reg++) 978 (void)rtsx_read(sc, reg, &sc->sc_regs[i++]); 979 980 sc->sc_regs4[0] = READ4(sc, RTSX_HCBAR); 981 sc->sc_regs4[1] = READ4(sc, RTSX_HCBCTLR); 982 sc->sc_regs4[2] = READ4(sc, RTSX_HDBAR); 983 sc->sc_regs4[3] = READ4(sc, RTSX_HDBCTLR); 984 sc->sc_regs4[4] = READ4(sc, RTSX_HAIMR); 985 sc->sc_regs4[5] = READ4(sc, RTSX_BIER); 986 /* Not saving RTSX_BIPR. */ 987 988 mutex_exit(&sc->sc_host_mtx); 989 } 990 991 static void 992 rtsx_restore_regs(struct rtsx_softc *sc) 993 { 994 int i; 995 uint16_t reg; 996 997 mutex_enter(&sc->sc_host_mtx); 998 999 WRITE4(sc, RTSX_HCBAR, sc->sc_regs4[0]); 1000 WRITE4(sc, RTSX_HCBCTLR, sc->sc_regs4[1]); 1001 WRITE4(sc, RTSX_HDBAR, sc->sc_regs4[2]); 1002 WRITE4(sc, RTSX_HDBCTLR, sc->sc_regs4[3]); 1003 WRITE4(sc, RTSX_HAIMR, sc->sc_regs4[4]); 1004 WRITE4(sc, RTSX_BIER, sc->sc_regs4[5]); 1005 /* Not writing RTSX_BIPR since doing so would clear it. */ 1006 1007 i = 0; 1008 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 1009 (void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]); 1010 for (reg = 0xFD52; reg < 0xFD69; reg++) 1011 (void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]); 1012 for (reg = 0xFE20; reg < 0xFE34; reg++) 1013 (void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]); 1014 1015 mutex_exit(&sc->sc_host_mtx); 1016 } 1017 1018 static uint8_t 1019 rtsx_response_type(uint16_t sdmmc_rsp) 1020 { 1021 static const struct rsp_type { 1022 uint16_t sdmmc_rsp; 1023 uint8_t rtsx_rsp; 1024 } rsp_types[] = { 1025 { SCF_RSP_R0, RTSX_SD_RSP_TYPE_R0 }, 1026 { SCF_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 1027 { SCF_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 1028 { SCF_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 1029 { SCF_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 1030 { SCF_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 1031 { SCF_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 1032 { SCF_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 1033 { SCF_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 1034 }; 1035 size_t i; 1036 1037 for (i = 0; i < __arraycount(rsp_types); i++) { 1038 if (sdmmc_rsp == rsp_types[i].sdmmc_rsp) 1039 return rsp_types[i].rtsx_rsp; 1040 } 1041 return 0; 1042 } 1043 1044 static int 1045 rtsx_hostcmd_send(struct rtsx_softc *sc, int ncmd) 1046 { 1047 1048 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1049 BUS_DMASYNC_PREWRITE); 1050 1051 mutex_enter(&sc->sc_host_mtx); 1052 1053 /* Tell the chip where the command buffer is and run the commands. */ 1054 WRITE4(sc, RTSX_HCBAR, sc->sc_dmap_cmd->dm_segs[0].ds_addr); 1055 WRITE4(sc, RTSX_HCBCTLR, 1056 ((ncmd * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 1057 1058 mutex_exit(&sc->sc_host_mtx); 1059 1060 return 0; 1061 } 1062 1063 static int 1064 rtsx_read_ppbuf(struct rtsx_softc *sc, struct sdmmc_command *cmd, 1065 uint32_t *cmdbuf) 1066 { 1067 uint8_t *ptr; 1068 int ncmd, remain; 1069 uint16_t reg; 1070 int error; 1071 int i, j; 1072 1073 DPRINTF(3,("%s: read %d bytes from ppbuf2\n", DEVNAME(sc), 1074 cmd->c_datalen)); 1075 1076 reg = RTSX_PPBUF_BASE2; 1077 ptr = cmd->c_data; 1078 remain = cmd->c_datalen; 1079 for (j = 0; j < cmd->c_datalen / RTSX_HOSTCMD_MAX; j++) { 1080 ncmd = 0; 1081 for (i = 0; i < RTSX_HOSTCMD_MAX; i++) { 1082 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, reg++, 1083 0, 0); 1084 } 1085 error = rtsx_hostcmd_send(sc, ncmd); 1086 if (error == 0) 1087 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4); 1088 if (error) 1089 goto ret; 1090 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0, 1091 RTSX_HOSTCMD_BUFSIZE, BUS_DMASYNC_POSTREAD); 1092 memcpy(ptr, cmdbuf, RTSX_HOSTCMD_MAX); 1093 ptr += RTSX_HOSTCMD_MAX; 1094 remain -= RTSX_HOSTCMD_MAX; 1095 } 1096 if (remain > 0) { 1097 ncmd = 0; 1098 for (i = 0; i < remain; i++) { 1099 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, reg++, 1100 0, 0); 1101 } 1102 error = rtsx_hostcmd_send(sc, ncmd); 1103 if (error == 0) 1104 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4); 1105 if (error) 1106 goto ret; 1107 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0, 1108 RTSX_HOSTCMD_BUFSIZE, BUS_DMASYNC_POSTREAD); 1109 memcpy(ptr, cmdbuf, remain); 1110 } 1111 ret: 1112 return error; 1113 } 1114 1115 static int 1116 rtsx_write_ppbuf(struct rtsx_softc *sc, struct sdmmc_command *cmd, 1117 uint32_t *cmdbuf) 1118 { 1119 const uint8_t *ptr; 1120 int ncmd, remain; 1121 uint16_t reg; 1122 int error; 1123 int i, j; 1124 1125 DPRINTF(3,("%s: write %d bytes to ppbuf2\n", DEVNAME(sc), 1126 cmd->c_datalen)); 1127 1128 reg = RTSX_PPBUF_BASE2; 1129 ptr = cmd->c_data; 1130 remain = cmd->c_datalen; 1131 for (j = 0; j < cmd->c_datalen / RTSX_HOSTCMD_MAX; j++) { 1132 ncmd = 0; 1133 for (i = 0; i < RTSX_HOSTCMD_MAX; i++) { 1134 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, reg++, 1135 0xff, *ptr++); 1136 } 1137 error = rtsx_hostcmd_send(sc, ncmd); 1138 if (error == 0) 1139 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4); 1140 if (error) 1141 goto ret; 1142 remain -= RTSX_HOSTCMD_MAX; 1143 } 1144 if (remain > 0) { 1145 ncmd = 0; 1146 for (i = 0; i < remain; i++) { 1147 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, reg++, 1148 0xff, *ptr++); 1149 } 1150 error = rtsx_hostcmd_send(sc, ncmd); 1151 if (error == 0) 1152 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4); 1153 if (error) 1154 goto ret; 1155 } 1156 ret: 1157 return error; 1158 } 1159 1160 static int 1161 rtsx_exec_short_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, 1162 uint32_t *cmdbuf, uint8_t rsp_type) 1163 { 1164 int read = ISSET(cmd->c_flags, SCF_CMD_READ); 1165 int ncmd; 1166 uint8_t tmode = read ? RTSX_TM_NORMAL_READ : RTSX_TM_AUTO_WRITE2; 1167 int error; 1168 1169 DPRINTF(3,("%s: %s short xfer: %d bytes with block size %d\n", 1170 DEVNAME(sc), read ? "read" : "write", cmd->c_datalen, 1171 cmd->c_blklen)); 1172 1173 if (cmd->c_datalen > 512) { 1174 DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n", 1175 DEVNAME(sc), cmd->c_datalen, 512)); 1176 return ENOMEM; 1177 } 1178 1179 if (!read && cmd->c_data != NULL && cmd->c_datalen > 0) { 1180 error = rtsx_write_ppbuf(sc, cmd, cmdbuf); 1181 if (error) 1182 goto ret; 1183 } 1184 1185 /* The command buffer queues commands the host controller will 1186 * run asynchronously. */ 1187 ncmd = 0; 1188 1189 /* Queue commands to set SD command index and argument. */ 1190 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 1191 0xff, 0x40 | cmd->c_opcode); 1192 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 1193 0xff, cmd->c_arg >> 24); 1194 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 1195 0xff, cmd->c_arg >> 16); 1196 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 1197 0xff, cmd->c_arg >> 8); 1198 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 1199 0xff, cmd->c_arg); 1200 1201 /* Queue commands to configure data transfer size. */ 1202 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 1203 0xff, cmd->c_datalen); 1204 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 1205 0xff, cmd->c_datalen >> 8); 1206 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 1207 0xff, 0x01); 1208 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 1209 0xff, 0x00); 1210 1211 /* Queue command to set response type. */ 1212 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 1213 0xff, rsp_type); 1214 1215 if (tmode == RTSX_TM_NORMAL_READ) { 1216 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, 1217 RTSX_CARD_DATA_SOURCE, 0x01, RTSX_PINGPONG_BUFFER); 1218 } 1219 1220 /* Queue commands to perform SD transfer. */ 1221 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1222 0xff, tmode | RTSX_SD_TRANSFER_START); 1223 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1224 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 1225 1226 /* Run the command queue and wait for completion. */ 1227 error = rtsx_hostcmd_send(sc, ncmd); 1228 if (error == 0) 1229 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 2 * hz); 1230 if (error) 1231 goto ret; 1232 1233 if (read && cmd->c_data != NULL && cmd->c_datalen > 0) 1234 error = rtsx_read_ppbuf(sc, cmd, cmdbuf); 1235 ret: 1236 DPRINTF(3,("%s: short xfer done, error=%d\n", DEVNAME(sc), error)); 1237 return error; 1238 } 1239 1240 static int 1241 rtsx_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, uint32_t *cmdbuf) 1242 { 1243 int ncmd, dma_dir, error, tmode; 1244 int read = ISSET(cmd->c_flags, SCF_CMD_READ); 1245 uint8_t cfg2; 1246 1247 DPRINTF(3,("%s: %s xfer: %d bytes with block size %d\n", DEVNAME(sc), 1248 read ? "read" : "write", cmd->c_datalen, cmd->c_blklen)); 1249 1250 if (cmd->c_datalen > RTSX_DMA_DATA_BUFSIZE) { 1251 DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n", 1252 DEVNAME(sc), cmd->c_datalen, RTSX_DMA_DATA_BUFSIZE)); 1253 return ENOMEM; 1254 } 1255 1256 /* Configure DMA transfer mode parameters. */ 1257 cfg2 = RTSX_SD_NO_CHECK_WAIT_CRC_TO | RTSX_SD_CHECK_CRC16 | 1258 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 1259 if (read) { 1260 dma_dir = RTSX_DMA_DIR_FROM_CARD; 1261 /* Use transfer mode AUTO_READ3, which assumes we've already 1262 * sent the read command and gotten the response, and will 1263 * send CMD 12 manually after reading multiple blocks. */ 1264 tmode = RTSX_TM_AUTO_READ3; 1265 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 1266 } else { 1267 dma_dir = RTSX_DMA_DIR_TO_CARD; 1268 /* Use transfer mode AUTO_WRITE3, which assumes we've already 1269 * sent the write command and gotten the response, and will 1270 * send CMD 12 manually after writing multiple blocks. */ 1271 tmode = RTSX_TM_AUTO_WRITE3; 1272 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 1273 } 1274 1275 /* The command buffer queues commands the host controller will 1276 * run asynchronously. */ 1277 ncmd = 0; 1278 1279 /* Queue command to set response type. */ 1280 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 1281 0xff, cfg2); 1282 1283 /* Queue commands to configure data transfer size. */ 1284 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 1285 0xff, 0x00); 1286 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 1287 0xff, 0x02); 1288 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 1289 0xff, cmd->c_datalen / cmd->c_blklen); 1290 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 1291 0xff, (cmd->c_datalen / cmd->c_blklen) >> 8); 1292 1293 /* Use the DMA ring buffer for commands which transfer data. */ 1294 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 1295 0x01, RTSX_RING_BUFFER); 1296 1297 /* Configure DMA controller. */ 1298 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 1299 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 1300 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC3, 1301 0xff, cmd->c_datalen >> 24); 1302 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC2, 1303 0xff, cmd->c_datalen >> 16); 1304 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC1, 1305 0xff, cmd->c_datalen >> 8); 1306 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC0, 1307 0xff, cmd->c_datalen); 1308 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMACTL, 1309 RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK, 1310 RTSX_DMA_EN | dma_dir | RTSX_DMA_512); 1311 1312 /* Queue commands to perform SD transfer. */ 1313 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1314 0xff, tmode | RTSX_SD_TRANSFER_START); 1315 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1316 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 1317 1318 error = rtsx_hostcmd_send(sc, ncmd); 1319 if (error) 1320 goto ret; 1321 1322 mutex_enter(&sc->sc_host_mtx); 1323 1324 /* Tell the chip where the data buffer is and run the transfer. */ 1325 WRITE4(sc, RTSX_HDBAR, cmd->c_dmamap->dm_segs[0].ds_addr); 1326 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 1327 (cmd->c_dmamap->dm_segs[0].ds_len & 0x00ffffff)); 1328 1329 mutex_exit(&sc->sc_host_mtx); 1330 1331 /* Wait for completion. */ 1332 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 10*hz); 1333 ret: 1334 DPRINTF(3,("%s: xfer done, error=%d\n", DEVNAME(sc), error)); 1335 return error; 1336 } 1337 1338 static void 1339 rtsx_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1340 { 1341 struct rtsx_softc *sc = sch; 1342 bus_dma_segment_t segs[1]; 1343 int rsegs; 1344 void *cmdkvap; 1345 uint32_t *cmdbuf; 1346 uint8_t rsp_type; 1347 uint16_t r; 1348 int ncmd; 1349 int error = 0; 1350 1351 DPRINTF(3,("%s: executing cmd %hu\n", DEVNAME(sc), cmd->c_opcode)); 1352 1353 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 1354 if (cmd->c_opcode == SD_IO_SEND_OP_COND && 1355 !ISSET(sc->sc_flags, RTSX_F_SDIO_SUPPORT)) { 1356 error = ENOTSUP; 1357 goto ret; 1358 } 1359 1360 rsp_type = rtsx_response_type(cmd->c_flags & SCF_RSP_MASK); 1361 if (rsp_type == 0) { 1362 aprint_error_dev(sc->sc_dev, "unknown response type 0x%x\n", 1363 cmd->c_flags & SCF_RSP_MASK); 1364 error = EINVAL; 1365 goto ret; 1366 } 1367 1368 /* Allocate and map the host command buffer. */ 1369 error = bus_dmamem_alloc(sc->sc_dmat, RTSX_HOSTCMD_BUFSIZE, 0, 0, 1370 segs, 1, &rsegs, BUS_DMA_WAITOK); 1371 if (error) 1372 goto ret; 1373 error = bus_dmamem_map(sc->sc_dmat, segs, rsegs, RTSX_HOSTCMD_BUFSIZE, 1374 &cmdkvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1375 if (error) 1376 goto free_cmdbuf; 1377 1378 /* Load command DMA buffer. */ 1379 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap_cmd, cmdkvap, 1380 RTSX_HOSTCMD_BUFSIZE, NULL, BUS_DMA_WAITOK); 1381 if (error) 1382 goto unmap_cmdbuf; 1383 1384 /* Use another transfer method when data size < 512. */ 1385 if (cmd->c_data != NULL && cmd->c_datalen < 512) { 1386 error = rtsx_exec_short_xfer(sch, cmd, cmdkvap, rsp_type); 1387 goto unload_cmdbuf; 1388 } 1389 1390 /* The command buffer queues commands the host controller will 1391 * run asynchronously. */ 1392 cmdbuf = cmdkvap; 1393 ncmd = 0; 1394 1395 /* Queue commands to set SD command index and argument. */ 1396 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 1397 0xff, 0x40 | cmd->c_opcode); 1398 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 1399 0xff, cmd->c_arg >> 24); 1400 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 1401 0xff, cmd->c_arg >> 16); 1402 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 1403 0xff, cmd->c_arg >> 8); 1404 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 1405 0xff, cmd->c_arg); 1406 1407 /* Queue command to set response type. */ 1408 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 1409 0xff, rsp_type); 1410 1411 /* Use the ping-pong buffer for commands which do not transfer data. */ 1412 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 1413 0x01, RTSX_PINGPONG_BUFFER); 1414 1415 /* Queue commands to perform SD transfer. */ 1416 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1417 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 1418 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1419 RTSX_SD_TRANSFER_END | RTSX_SD_STAT_IDLE, 1420 RTSX_SD_TRANSFER_END | RTSX_SD_STAT_IDLE); 1421 1422 /* Queue commands to read back card status response.*/ 1423 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 1424 for (r = RTSX_PPBUF_BASE2 + 15; r > RTSX_PPBUF_BASE2; r--) 1425 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1426 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, RTSX_SD_CMD5, 1427 0, 0); 1428 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 1429 for (r = RTSX_SD_CMD0; r <= RTSX_SD_CMD4; r++) 1430 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1431 } 1432 1433 /* Run the command queue and wait for completion. */ 1434 error = rtsx_hostcmd_send(sc, ncmd); 1435 if (error == 0) 1436 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz); 1437 if (error) 1438 goto unload_cmdbuf; 1439 1440 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1441 BUS_DMASYNC_POSTREAD); 1442 1443 /* Copy card response into sdmmc response buffer. */ 1444 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1445 /* Copy bytes like sdhc(4), which on little-endian uses 1446 * different byte order for short and long responses... */ 1447 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1448 uint8_t *resp = cmdkvap; 1449 memcpy(cmd->c_resp, resp + 1, sizeof(cmd->c_resp)); 1450 } else { 1451 /* First byte is CHECK_REG_CMD return value, second 1452 * one is the command op code -- we skip those. */ 1453 cmd->c_resp[0] = 1454 ((be32toh(cmdbuf[0]) & 0x0000ffff) << 16) | 1455 ((be32toh(cmdbuf[1]) & 0xffff0000) >> 16); 1456 } 1457 } 1458 1459 if (cmd->c_data) { 1460 error = rtsx_xfer(sc, cmd, cmdbuf); 1461 if (error) { 1462 uint8_t stat1; 1463 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 1464 (stat1 & RTSX_SD_CRC_ERR)) { 1465 aprint_error_dev(sc->sc_dev, 1466 "CRC error (stat=0x%x)\n", stat1); 1467 } 1468 } 1469 } 1470 1471 unload_cmdbuf: 1472 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap_cmd); 1473 unmap_cmdbuf: 1474 bus_dmamem_unmap(sc->sc_dmat, cmdkvap, RTSX_HOSTCMD_BUFSIZE); 1475 free_cmdbuf: 1476 bus_dmamem_free(sc->sc_dmat, segs, rsegs); 1477 ret: 1478 SET(cmd->c_flags, SCF_ITSDONE); 1479 cmd->c_error = error; 1480 } 1481 1482 /* Prepare for another command. */ 1483 static void 1484 rtsx_soft_reset(struct rtsx_softc *sc) 1485 { 1486 1487 DPRINTF(1,("%s: soft reset\n", DEVNAME(sc))); 1488 1489 /* Stop command transfer. */ 1490 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 1491 1492 (void)rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP|RTSX_SD_CLR_ERR, 1493 RTSX_SD_STOP|RTSX_SD_CLR_ERR); 1494 1495 /* Stop DMA transfer. */ 1496 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 1497 (void)rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 1498 1499 (void)rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 1500 } 1501 1502 static int 1503 rtsx_wait_intr(struct rtsx_softc *sc, int mask, int timo) 1504 { 1505 int status; 1506 int error = 0; 1507 1508 mask |= RTSX_TRANS_FAIL_INT; 1509 1510 mutex_enter(&sc->sc_intr_mtx); 1511 1512 status = sc->sc_intr_status & mask; 1513 while (status == 0) { 1514 if (cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_mtx, timo) 1515 == EWOULDBLOCK) { 1516 rtsx_soft_reset(sc); 1517 error = ETIMEDOUT; 1518 break; 1519 } 1520 status = sc->sc_intr_status & mask; 1521 } 1522 sc->sc_intr_status &= ~status; 1523 1524 /* Has the card disappeared? */ 1525 if (!ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT)) 1526 error = ENODEV; 1527 1528 mutex_exit(&sc->sc_intr_mtx); 1529 1530 if (error == 0 && (status & RTSX_TRANS_FAIL_INT)) 1531 error = EIO; 1532 return error; 1533 } 1534 1535 static void 1536 rtsx_card_insert(struct rtsx_softc *sc) 1537 { 1538 1539 DPRINTF(1, ("%s: card inserted\n", DEVNAME(sc))); 1540 1541 sc->sc_flags |= RTSX_F_CARD_PRESENT; 1542 (void)rtsx_led_enable(sc); 1543 1544 /* Schedule card discovery task. */ 1545 sdmmc_needs_discover(sc->sc_sdmmc); 1546 } 1547 1548 static void 1549 rtsx_card_eject(struct rtsx_softc *sc) 1550 { 1551 1552 DPRINTF(1, ("%s: card ejected\n", DEVNAME(sc))); 1553 1554 sc->sc_flags &= ~RTSX_F_CARD_PRESENT; 1555 (void)rtsx_led_disable(sc); 1556 1557 /* Schedule card discovery task. */ 1558 sdmmc_needs_discover(sc->sc_sdmmc); 1559 } 1560 1561 /* 1562 * Established by attachment driver at interrupt priority IPL_SDMMC. 1563 */ 1564 int 1565 rtsx_intr(void *arg) 1566 { 1567 struct rtsx_softc *sc = arg; 1568 uint32_t enabled, status; 1569 1570 enabled = READ4(sc, RTSX_BIER); 1571 status = READ4(sc, RTSX_BIPR); 1572 1573 /* Ack interrupts. */ 1574 WRITE4(sc, RTSX_BIPR, status); 1575 1576 if (((enabled & status) == 0) || status == 0xffffffff) 1577 return 0; 1578 1579 mutex_enter(&sc->sc_intr_mtx); 1580 1581 if (status & RTSX_SD_INT) { 1582 if (status & RTSX_SD_EXIST) { 1583 if (!ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT)) 1584 rtsx_card_insert(sc); 1585 } else { 1586 rtsx_card_eject(sc); 1587 } 1588 } 1589 1590 if (status & (RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT)) { 1591 sc->sc_intr_status |= status; 1592 cv_broadcast(&sc->sc_intr_cv); 1593 } 1594 1595 mutex_exit(&sc->sc_intr_mtx); 1596 1597 return 1; 1598 } 1599
Indexes created Thu Oct 02 01:09:59 GMT 2025