rtsxreg.h revision 1.1
1 /* $NetBSD: rtsxreg.h,v 1.1 2014/03/19 15:26:41 nonaka Exp $ */ 2 /* $OpenBSD: rtsxreg.h,v 1.3 2013/11/26 20:33:16 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * Copyright (c) 2012 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #ifndef _RTSXREG_H_ 22 #define _RTSXREG_H_ 23 24 /* Host command buffer control register. */ 25 #define RTSX_HCBAR 0x00 26 #define RTSX_HCBCTLR 0x04 27 #define RTSX_START_CMD (1U << 31) 28 #define RTSX_HW_AUTO_RSP (1U << 30) 29 #define RTSX_STOP_CMD (1U << 28) 30 31 /* Host data buffer control register. */ 32 #define RTSX_HDBAR 0x08 33 #define RTSX_HDBCTLR 0x0C 34 #define RTSX_TRIG_DMA (1U << 31) 35 #define RTSX_DMA_READ (1U << 29) 36 #define RTSX_STOP_DMA (1U << 28) 37 #define RTSX_ADMA_MODE (2U << 26) 38 39 /* Interrupt pending register. */ 40 #define RTSX_BIPR 0x14 41 #define RTSX_CMD_DONE_INT (1U << 31) 42 #define RTSX_DATA_DONE_INT (1U << 30) 43 #define RTSX_TRANS_OK_INT (1U << 29) 44 #define RTSX_TRANS_FAIL_INT (1U << 28) 45 #define RTSX_XD_INT (1U << 27) 46 #define RTSX_MS_INT (1U << 26) 47 #define RTSX_SD_INT (1U << 25) 48 #define RTSX_SD_WRITE_PROTECT (1U << 19) 49 #define RTSX_XD_EXIST (1U << 18) 50 #define RTSX_MS_EXIST (1U << 17) 51 #define RTSX_SD_EXIST (1U << 16) 52 #define RTSX_CARD_EXIST (RTSX_XD_EXIST|RTSX_MS_EXIST|RTSX_SD_EXIST) 53 #define RTSX_CARD_INT (RTSX_XD_INT|RTSX_MS_INT|RTSX_SD_INT) 54 55 /* Chip register access. */ 56 #define RTSX_HAIMR 0x10 57 #define RTSX_HAIMR_WRITE 0x40000000 58 #define RTSX_HAIMR_BUSY 0x80000000 59 60 /* Interrupt enable register. */ 61 #define RTSX_BIER 0x18 62 #define RTSX_CMD_DONE_INT_EN (1U << 31) 63 #define RTSX_DATA_DONE_INT_EN (1U << 30) 64 #define RTSX_TRANS_OK_INT_EN (1U << 29) 65 #define RTSX_TRANS_FAIL_INT_EN (1U << 28) 66 #define RTSX_XD_INT_EN (1U << 27) 67 #define RTSX_MS_INT_EN (1U << 26) 68 #define RTSX_SD_INT_EN (1U << 25) 69 #define RTSX_GPIO0_INT_EN (1U << 24) 70 #define RTSX_MS_OC_INT_EN (1U << 23) 71 #define RTSX_SD_OC_INT_EN (1U << 22) 72 73 /* Power on/off. */ 74 #define RTSX_FPDCTL 0xFC00 75 #define RTSX_SSC_POWER_DOWN 0x01 76 #define RTSX_SD_OC_POWER_DOWN 0x02 77 #define RTSX_MS_OC_POWER_DOWN 0x04 78 #define RTSX_ALL_POWER_DOWN 0x07 79 #define RTSX_OC_POWER_DOWN 0x06 80 81 /* Card power control register. */ 82 #define RTSX_CARD_PWR_CTL 0xFD50 83 #define RTSX_SD_PWR_ON 0x00 84 #define RTSX_SD_PARTIAL_PWR_ON 0x01 85 #define RTSX_SD_PWR_OFF 0x03 86 #define RTSX_SD_PWR_MASK 0x03 87 #define RTSX_PMOS_STRG_MASK 0x10 88 #define RTSX_PMOS_STRG_400mA 0x00 89 #define RTSX_PMOS_STRG_800mA 0x10 90 91 #define RTSX_MS_PWR_OFF 0x0C 92 #define RTSX_MS_PWR_ON 0x00 93 #define RTSX_MS_PARTIAL_PWR_ON 0x04 94 95 #define RTSX_CARD_SHARE_MODE 0xFD52 96 #define RTSX_CARD_SHARE_48_XD 0x02 97 #define RTSX_CARD_SHARE_48_SD 0x04 98 #define RTSX_CARD_SHARE_48_MS 0x08 99 #define RTSX_CARD_DRIVE_SEL 0xFE53 100 101 /* Card clock. */ 102 #define RTSX_CARD_CLK_EN 0xFD69 103 #define RTSX_XD_CLK_EN 0x02 104 #define RTSX_SD_CLK_EN 0x04 105 #define RTSX_MS_CLK_EN 0x08 106 #define RTSX_SPI_CLK_EN 0x10 107 #define RTSX_CARD_CLK_EN_ALL \ 108 (RTSX_XD_CLK_EN|RTSX_SD_CLK_EN|RTSX_MS_CLK_EN|RTSX_SPI_CLK_EN) 109 110 #define RTSX_SDIO_CTRL 0xFD6B 111 #define RTSX_SDIO_BUS_CTRL 0x01 112 #define RTSX_SDIO_CD_CTRL 0x02 113 114 /* Internal clock. */ 115 #define RTSX_CLK_CTL 0xFC02 116 #define RTSX_CLK_LOW_FREQ 0x01 117 118 /* Internal clock divisor values. */ 119 #define RTSX_CLK_DIV 0xFC03 120 #define RTSX_CLK_DIV_1 0x01 121 #define RTSX_CLK_DIV_2 0x02 122 #define RTSX_CLK_DIV_4 0x03 123 #define RTSX_CLK_DIV_8 0x04 124 125 /* Internal clock selection. */ 126 #define RTSX_CLK_SEL 0xFC04 127 #define RTSX_SSC_80 0 128 #define RTSX_SSC_100 1 129 #define RTSX_SSC_120 2 130 #define RTSX_SSC_150 3 131 #define RTSX_SSC_200 4 132 133 #define RTSX_SSC_DIV_N_0 0xFC0F 134 135 #define RTSX_SSC_CTL1 0xFC11 136 #define RTSX_RSTB 0x80 137 #define RTSX_SSC_8X_EN 0x40 138 #define RTSX_SSC_FIX_FRAC 0x20 139 #define RTSX_SSC_SEL_1M 0x00 140 #define RTSX_SSC_SEL_2M 0x08 141 #define RTSX_SSC_SEL_2M 0x08 142 #define RTSX_SSC_SEL_4M 0x10 143 #define RTSX_SSC_SEL_8M 0x18 144 #define RTSX_SSC_CTL2 0xFC12 145 #define RTSX_SSC_DEPTH_MASK 0x07 146 147 /* RC oscillator, default is 2M */ 148 #define RTSX_RCCTL 0xFC14 149 #define RTSX_RCCTL_F_400K 0x0 150 #define RTSX_RCCTL_F_2M 0x1 151 152 /* RTS5229-only. */ 153 #define RTSX_OLT_LED_CTL 0xFC1E 154 #define RTSX_OLT_LED_PERIOD 0x02 155 #define RTSX_OLT_LED_AUTOBLINK 0x08 156 157 #define RTSX_GPIO_CTL 0xFC1F 158 #define RTSX_GPIO_LED_ON 0x02 159 160 /* Host controller commands. */ 161 #define RTSX_READ_REG_CMD 0 162 #define RTSX_WRITE_REG_CMD 1 163 #define RTSX_CHECK_REG_CMD 2 164 165 166 #define RTSX_OCPCTL 0xFC15 167 #define RTSX_OCPSTAT 0xFC16 168 #define RTSX_OCPGLITCH 0xFC17 169 #define RTSX_OCPPARA1 0xFC18 170 #define RTSX_OCPPARA2 0xFC19 171 172 /* FPGA */ 173 #define RTSX_FPGA_PULL_CTL 0xFC1D 174 #define RTSX_FPGA_MS_PULL_CTL_BIT 0x10 175 #define RTSX_FPGA_SD_PULL_CTL_BIT 0x08 176 177 /* Clock source configuration register. */ 178 #define RTSX_CARD_CLK_SOURCE 0xFC2E 179 #define RTSX_CRC_FIX_CLK (0x00 << 0) 180 #define RTSX_CRC_VAR_CLK0 (0x01 << 0) 181 #define RTSX_CRC_VAR_CLK1 (0x02 << 0) 182 #define RTSX_SD30_FIX_CLK (0x00 << 2) 183 #define RTSX_SD30_VAR_CLK0 (0x01 << 2) 184 #define RTSX_SD30_VAR_CLK1 (0x02 << 2) 185 #define RTSX_SAMPLE_FIX_CLK (0x00 << 4) 186 #define RTSX_SAMPLE_VAR_CLK0 (0x01 << 4) 187 #define RTSX_SAMPLE_VAR_CLK1 (0x02 << 4) 188 189 190 /* ASIC */ 191 #define RTSX_CARD_PULL_CTL1 0xFD60 192 #define RTSX_CARD_PULL_CTL2 0xFD61 193 #define RTSX_CARD_PULL_CTL3 0xFD62 194 195 #define RTSX_PULL_CTL_DISABLE12 0x55 196 #define RTSX_PULL_CTL_DISABLE3 0xD5 197 #define RTSX_PULL_CTL_DISABLE3_TYPE_C 0xE5 198 #define RTSX_PULL_CTL_ENABLE12 0xAA 199 #define RTSX_PULL_CTL_ENABLE3 0xE9 200 #define RTSX_PULL_CTL_ENABLE3_TYPE_C 0xD9 201 202 /* SD configuration register 1 (clock divider, bus mode and width). */ 203 #define RTSX_SD_CFG1 0xFDA0 204 #define RTSX_CLK_DIVIDE_0 0x00 205 #define RTSX_CLK_DIVIDE_128 0x80 206 #define RTSX_CLK_DIVIDE_256 0xC0 207 #define RTSX_CLK_DIVIDE_MASK 0xC0 208 #define RTSX_SD20_MODE 0x00 209 #define RTSX_SDDDR_MODE 0x04 210 #define RTSX_SD30_MODE 0x08 211 #define RTSX_SD_MODE_MASK 0x0C 212 #define RTSX_BUS_WIDTH_1 0x00 213 #define RTSX_BUS_WIDTH_4 0x01 214 #define RTSX_BUS_WIDTH_8 0x02 215 #define RTSX_BUS_WIDTH_MASK 0x03 216 217 /* SD configuration register 2 (SD command response flags). */ 218 #define RTSX_SD_CFG2 0xFDA1 219 #define RTSX_SD_CALCULATE_CRC7 0x00 220 #define RTSX_SD_NO_CALCULATE_CRC7 0x80 221 #define RTSX_SD_CHECK_CRC16 0x00 222 #define RTSX_SD_NO_CHECK_CRC16 0x40 223 #define RTSX_SD_NO_CHECK_WAIT_CRC_TO 0x20 224 #define RTSX_SD_WAIT_BUSY_END 0x08 225 #define RTSX_SD_NO_WAIT_BUSY_END 0x00 226 #define RTSX_SD_CHECK_CRC7 0x00 227 #define RTSX_SD_NO_CHECK_CRC7 0x04 228 #define RTSX_SD_RSP_LEN_0 0x00 229 #define RTSX_SD_RSP_LEN_6 0x01 230 #define RTSX_SD_RSP_LEN_17 0x02 231 /* SD command response types. */ 232 #define RTSX_SD_RSP_TYPE_R0 0x04 233 #define RTSX_SD_RSP_TYPE_R1 0x01 234 #define RTSX_SD_RSP_TYPE_R1B 0x09 235 #define RTSX_SD_RSP_TYPE_R2 0x02 236 #define RTSX_SD_RSP_TYPE_R3 0x05 237 #define RTSX_SD_RSP_TYPE_R4 0x05 238 #define RTSX_SD_RSP_TYPE_R5 0x01 239 #define RTSX_SD_RSP_TYPE_R6 0x01 240 #define RTSX_SD_RSP_TYPE_R7 0x01 241 242 #define RTSX_SD_STAT1 0xFDA3 243 #define RTSX_SD_CRC7_ERR 0x80 244 #define RTSX_SD_CRC16_ERR 0x40 245 #define RTSX_SD_CRC_WRITE_ERR 0x20 246 #define RTSX_SD_CRC_WRITE_ERR_MASK 0x1C 247 #define RTSX_GET_CRC_TIME_OUT 0x02 248 #define RTSX_SD_TUNING_COMPARE_ERR 0x01 249 #define RTSX_SD_STAT2 0xFDA4 250 #define RTSX_SD_RSP_80CLK_TIMEOUT 0x01 251 252 #define RTSX_SD_CRC_ERR (RTSX_SD_CRC7_ERR|RTSX_SD_CRC16_ERR|RTSX_SD_CRC_WRITE_ERR) 253 254 /* SD bus status register. */ 255 #define RTSX_SD_BUS_STAT 0xFDA5 256 #define RTSX_SD_CLK_TOGGLE_EN 0x80 257 #define RTSX_SD_CLK_FORCE_STOP 0x40 258 #define RTSX_SD_DAT3_STATUS 0x10 259 #define RTSX_SD_DAT2_STATUS 0x08 260 #define RTSX_SD_DAT1_STATUS 0x04 261 #define RTSX_SD_DAT0_STATUS 0x02 262 #define RTSX_SD_CMD_STATUS 0x01 263 264 #define RTSX_SD_PAD_CTL 0xFDA6 265 #define RTSX_SD_IO_USING_1V8 0x80 266 267 /* Sample point control register. */ 268 #define RTSX_SD_SAMPLE_POINT_CTL 0xFDA7 269 #define RTSX_DDR_FIX_RX_DAT 0x00 270 #define RTSX_DDR_VAR_RX_DAT 0x80 271 #define RTSX_DDR_FIX_RX_DAT_EDGE 0x00 272 #define RTSX_DDR_FIX_RX_DAT_14_DELAY 0x40 273 #define RTSX_DDR_FIX_RX_CMD 0x00 274 #define RTSX_DDR_VAR_RX_CMD 0x20 275 #define RTSX_DDR_FIX_RX_CMD_POS_EDGE 0x00 276 #define RTSX_DDR_FIX_RX_CMD_14_DELAY 0x10 277 #define RTSX_SD20_RX_POS_EDGE 0x00 278 #define RTSX_SD20_RX_14_DELAY 0x08 279 #define RTSX_SD20_RX_SEL_MASK 0x08 280 281 #define RTSX_SD_PUSH_POINT_CTL 0xFDA8 282 #define RTSX_SD20_TX_NEG_EDGE 0x00 283 284 #define RTSX_SD_CMD0 0xFDA9 285 #define RTSX_SD_CMD1 0xFDAA 286 #define RTSX_SD_CMD2 0xFDAB 287 #define RTSX_SD_CMD3 0xFDAC 288 #define RTSX_SD_CMD4 0xFDAD 289 #define RTSX_SD_CMD5 0xFDAE 290 #define RTSX_SD_BYTE_CNT_L 0xFDAF 291 #define RTSX_SD_BYTE_CNT_H 0xFDB0 292 #define RTSX_SD_BLOCK_CNT_L 0xFDB1 293 #define RTSX_SD_BLOCK_CNT_H 0xFDB2 294 295 /* 296 * Transfer modes. 297 */ 298 #define RTSX_SD_TRANSFER 0xFDB3 299 300 /* Write one or two bytes from SD_CMD2 and SD_CMD3 to the card. */ 301 #define RTSX_TM_NORMAL_WRITE 0x00 302 303 /* Write (SD_BYTE_CNT * SD_BLOCK_COUNTS) bytes from ring buffer to card. */ 304 #define RTSX_TM_AUTO_WRITE3 0x01 305 306 /* Like AUTO_WRITE3, plus automatically send CMD 12 when done. 307 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 308 #define RTSX_TM_AUTO_WRITE4 0x02 309 310 /* Read (SD_BYTE_CNT * SD_BLOCK_CNT) bytes from card into ring buffer. */ 311 #define RTSX_TM_AUTO_READ3 0x05 312 313 /* Like AUTO_READ3, plus automatically send CMD 12 when done. 314 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 315 #define RTSX_TM_AUTO_READ4 0x06 316 317 /* Send an SD command described in SD_CMD{0,1,2,3,4} to the card and put 318 * the response into SD_CMD{0,1,2,3,4}. Long responses (17 byte) are put 319 * into ping-pong buffer 2 instead. */ 320 #define RTSX_TM_CMD_RSP 0x08 321 322 /* Send write command, get response from the card, write data from ring 323 * buffer to card, and send CMD 12 when done. 324 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 325 #define RTSX_TM_AUTO_WRITE1 0x09 326 327 /* Like AUTO_WRITE1 except no CMD 12 is sent. */ 328 #define RTSX_TM_AUTO_WRITE2 0x0A 329 330 /* Send read command, read up to 512 bytes (SD_BYTE_CNT * SD_BLOCK_CNT) 331 * from the card into the ring buffer or ping-pong buffer 2. */ 332 #define RTSX_TM_NORMAL_READ 0x0C 333 334 /* Same as WRITE1, except data is read from the card to the ring buffer. */ 335 #define RTSX_TM_AUTO_READ1 0x0D 336 337 /* Same as WRITE2, except data is read from the card to the ring buffer. */ 338 #define RTSX_TM_AUTO_READ2 0x0E 339 340 /* Send CMD 19 and receive response and tuning pattern from card and 341 * report the result. */ 342 #define RTSX_TM_AUTO_TUNING 0x0F 343 344 /* transfer control */ 345 #define RTSX_SD_TRANSFER_START 0x80 346 #define RTSX_SD_TRANSFER_END 0x40 347 #define RTSX_SD_STAT_IDLE 0x20 348 #define RTSX_SD_TRANSFER_ERR 0x10 349 350 #define RTSX_SD_CMD_STATE 0xFDB5 351 #define RTSX_CMD_IDLE 0x80 352 #define RTSX_SD_DATA_STATE 0xFDB6 353 #define RTSX_DATA_IDLE 0x80 354 355 #define RTSX_CARD_STOP 0xFD54 356 #define RTSX_SPI_STOP 0x01 357 #define RTSX_XD_STOP 0x02 358 #define RTSX_SD_STOP 0x04 359 #define RTSX_MS_STOP 0x08 360 #define RTSX_SPI_CLR_ERR 0x10 361 #define RTSX_XD_CLR_ERR 0x20 362 #define RTSX_SD_CLR_ERR 0x40 363 #define RTSX_MS_CLR_ERR 0x80 364 #define RTSX_ALL_STOP 0x0F 365 #define RTSX_ALL_CLR_ERR 0xF0 366 367 #define RTSX_CARD_OE 0xFD55 368 #define RTSX_XD_OUTPUT_EN 0x02 369 #define RTSX_SD_OUTPUT_EN 0x04 370 #define RTSX_MS_OUTPUT_EN 0x08 371 #define RTSX_SPI_OUTPUT_EN 0x10 372 #define RTSX_CARD_OUTPUT_EN (RTSX_XD_OUTPUT_EN|RTSX_SD_OUTPUT_EN|\ 373 RTSX_MS_OUTPUT_EN) 374 375 #define RTSX_CARD_DATA_SOURCE 0xFD5B 376 #define RTSX_RING_BUFFER 0x00 377 #define RTSX_PINGPONG_BUFFER 0x01 378 #define RTSX_CARD_SELECT 0xFD5C 379 #define RTSX_XD_MOD_SEL 0x01 380 #define RTSX_SD_MOD_SEL 0x02 381 #define RTSX_MS_MOD_SEL 0x03 382 #define RTSX_SPI_MOD_SEL 0x04 383 384 #define RTSX_CARD_GPIO_DIR 0xFD57 385 #define RTSX_CARD_GPIO 0xFD58 386 #define RTSX_CARD_GPIO_LED_OFF 0x01 387 388 /* ping-pong buffer 2 */ 389 #define RTSX_PPBUF_BASE2 0xFA00 390 #define RTSX_PPBUF_SIZE 256 391 392 #define RTSX_SUPPORT_VOLTAGE (MMC_OCR_3_3V_3_4V \ 393 | MMC_OCR_3_2V_3_3V \ 394 | MMC_OCR_3_1V_3_2V \ 395 | MMC_OCR_3_0V_3_1V) 396 397 #define RTSX_CFG_PCI 0x1C 398 #define RTSX_CFG_ASIC 0x10 399 400 #define RTSX_IRQEN0 0xFE20 401 #define RTSX_LINK_DOWN_INT_EN 0x10 402 #define RTSX_LINK_READY_INT_EN 0x20 403 #define RTSX_SUSPEND_INT_EN 0x40 404 #define RTSX_DMA_DONE_INT_EN 0x80 405 #define RTSX_IRQSTAT0 0xFE21 406 #define RTSX_LINK_DOWN_INT 0x10 407 #define RTSX_LINK_READY_INT 0x20 408 #define RTSX_SUSPEND_INT 0x40 409 #define RTSX_DMA_DONE_INT 0x80 410 411 #define RTSX_DMATC0 0xFE28 412 #define RTSX_DMATC1 0xFE29 413 #define RTSX_DMATC2 0xFE2A 414 #define RTSX_DMATC3 0xFE2B 415 416 #define RTSX_DMACTL 0xFE2C 417 #define RTSX_DMA_EN 0x01 418 #define RTSX_DMA_DIR 0x02 419 #define RTSX_DMA_DIR_TO_CARD 0x00 420 #define RTSX_DMA_DIR_FROM_CARD 0x02 421 #define RTSX_DMA_BUSY 0x04 422 #define RTSX_DMA_RST 0x80 423 #define RTSX_DMA_128 (0 << 4) 424 #define RTSX_DMA_256 (1 << 4) 425 #define RTSX_DMA_512 (2 << 4) 426 #define RTSX_DMA_1024 (3 << 4) 427 #define RTSX_DMA_PACK_SIZE_MASK 0x30 428 429 #define RTSX_RBCTL 0xFE34 430 #define RTSX_RB_FLUSH 0x80 431 432 #define RTSX_CFGADDR0 0xFE35 433 #define RTSX_CFGADDR1 0xFE36 434 #define RTSX_CFGDATA0 0xFE37 435 #define RTSX_CFGDATA1 0xFE38 436 #define RTSX_CFGDATA2 0xFE39 437 #define RTSX_CFGDATA3 0xFE3A 438 #define RTSX_CFGRWCTL 0xFE3B 439 #define RTSX_CFG_WRITE_DATA0 0x01 440 #define RTSX_CFG_WRITE_DATA1 0x02 441 #define RTSX_CFG_WRITE_DATA2 0x04 442 #define RTSX_CFG_WRITE_DATA3 0x08 443 #define RTSX_CFG_BUSY 0x80 444 445 #define RTSX_SDIOCFG_REG 0x724 446 #define RTSX_SDIOCFG_NO_BYPASS_SDIO 0x02 447 #define RTSX_SDIOCFG_HAVE_SDIO 0x04 448 #define RTSX_SDIOCFG_SINGLE_LUN 0x08 449 #define RTSX_SDIOCFG_SDIO_ONLY 0x80 450 451 #define RTSX_HOST_SLEEP_STATE 0xFE60 452 #define RTSX_HOST_ENTER_S1 0x01 453 #define RTSX_HOST_ENTER_S3 0x02 454 455 #define RTSX_SDIO_CFG 0xFE70 456 #define RTSX_SDIO_BUS_AUTO_SWITCH 0x10 457 458 #define RTSX_NFTS_TX_CTRL 0xFE72 459 #define RTSX_INT_READ_CLR 0x02 460 461 #define RTSX_PWR_GATE_CTRL 0xFE75 462 #define RTSX_PWR_GATE_EN 0x01 463 #define RTSX_LDO3318_ON 0x00 464 #define RTSX_LDO3318_SUSPEND 0x04 465 #define RTSX_LDO3318_OFF 0x06 466 #define RTSX_LDO3318_VCC1 0x02 467 #define RTSX_LDO3318_VCC2 0x04 468 #define RTSX_PWD_SUSPEND_EN 0xFE76 469 #define RTSX_LDO_PWR_SEL 0xFE78 470 #define RTSX_LDO_PWR_SEL_3V3 0x01 471 #define RTSX_LDO_PWR_SEL_DV33 0x03 472 473 #define RTSX_PHY_RWCTL 0xFE3C 474 #define RTSX_PHY_READ 0x00 475 #define RTSX_PHY_WRITE 0x01 476 #define RTSX_PHY_BUSY 0x80 477 #define RTSX_PHY_DATA0 0xFE3D 478 #define RTSX_PHY_DATA1 0xFE3E 479 #define RTSX_PHY_ADDR 0xFE3F 480 481 #define RTSX_PHY_VOLTAGE 0x08 482 #define RTSX_PHY_VOLTAGE_MASK 0x3F 483 484 #define RTSX_PETXCFG 0xFE49 485 #define RTSX_PETXCFG_CLKREQ_PIN 0x08 486 487 #define RTSX_CARD_AUTO_BLINK 0xFD56 488 #define RTSX_LED_BLINK_EN 0x08 489 #define RTSX_LED_BLINK_SPEED 0x05 490 491 #define RTSX_WAKE_SEL_CTL 0xFE54 492 #define RTSX_PME_FORCE_CTL 0xFE56 493 494 #define RTSX_CHANGE_LINK_STATE 0xFE5B 495 #define RTSX_CD_RST_CORE_EN 0x01 496 #define RTSX_FORCE_RST_CORE_EN 0x02 497 #define RTSX_NON_STICKY_RST_N_DBG 0x08 498 #define RTSX_MAC_PHY_RST_N_DBG 0x10 499 500 #define RTSX_PERST_GLITCH_WIDTH 0xFE5C 501 502 #define RTSX_SD30_DRIVE_SEL 0xFE5E 503 #define RTSX_SD30_DRIVE_SEL_3V3 0x01 504 #define RTSX_SD30_DRIVE_SEL_1V8 0x03 505 #define RTSX_SD30_DRIVE_SEL_MASK 0x07 506 507 #define RTSX_DUMMY_REG 0xFE90 508 509 #define RTSX_SG_INT 0x04 510 #define RTSX_SG_END 0x02 511 #define RTSX_SG_VALID 0x01 512 513 #define RTSX_SG_NO_OP 0x00 514 #define RTSX_SG_TRANS_DATA (0x02 << 4) 515 #define RTSX_SG_LINK_DESC (0x03 << 4) 516 517 #define RTSX_IC_VERSION_A 0x00 518 #define RTSX_IC_VERSION_B 0x01 519 #define RTSX_IC_VERSION_C 0x02 520 #define RTSX_IC_VERSION_D 0x03 521 522 #endif /* _RTSXREG_H_ */ 523
Indexes created Tue Sep 30 20:09:53 GMT 2025