rtw.c revision 1.1.2.4
1 /* $NetBSD: rtw.c,v 1.1.2.4 2004/12/18 09:31:56 skrll Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.1.2.4 2004/12/18 09:31:56 skrll Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #if 0 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #endif 54 #include <sys/time.h> 55 #include <sys/types.h> 56 57 #include <machine/endian.h> 58 #include <machine/bus.h> 59 #include <machine/intr.h> /* splnet */ 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_compat.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <dev/ic/rtwreg.h> 76 #include <dev/ic/rtwvar.h> 77 #include <dev/ic/rtwphyio.h> 78 #include <dev/ic/rtwphy.h> 79 80 #include <dev/ic/smc93cx6var.h> 81 82 #define KASSERT2(__cond, __msg) \ 83 do { \ 84 if (!(__cond)) \ 85 panic __msg ; \ 86 } while (0) 87 88 int rtw_rfprog_fallback = 0; 89 int rtw_host_rfio = 0; 90 int rtw_flush_rfio = 1; 91 int rtw_rfio_delay = 0; 92 93 #ifdef RTW_DEBUG 94 int rtw_debug = 2; 95 #endif /* RTW_DEBUG */ 96 97 #define NEXT_ATTACH_STATE(sc, state) do { \ 98 DPRINTF(sc, ("%s: attach state %s\n", __func__, #state)); \ 99 sc->sc_attach_state = state; \ 100 } while (0) 101 102 int rtw_dwelltime = 1000; /* milliseconds */ 103 104 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 105 static int rtw_sysctl_verify_rfio_delay(SYSCTLFN_PROTO); 106 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 107 #ifdef RTW_DEBUG 108 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 109 #endif /* RTW_DEBUG */ 110 111 /* 112 * Setup sysctl(3) MIB, hw.rtw.* 113 * 114 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 115 */ 116 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 117 { 118 int rc; 119 struct sysctlnode *cnode, *rnode; 120 121 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 122 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 123 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 124 goto err; 125 126 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 127 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 128 "Realtek RTL818x 802.11 controls", 129 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 130 goto err; 131 132 #ifdef RTW_DEBUG 133 /* control debugging printfs */ 134 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 135 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 136 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 137 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 138 CTL_CREATE, CTL_EOL)) != 0) 139 goto err; 140 #endif /* RTW_DEBUG */ 141 /* set fallback RF programming method */ 142 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 143 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 144 "rfprog_fallback", 145 SYSCTL_DESCR("Set fallback RF programming method"), 146 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 147 CTL_CREATE, CTL_EOL)) != 0) 148 goto err; 149 150 /* force host to flush I/O by reading RTW_PHYADDR */ 151 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 152 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 153 "flush_rfio", SYSCTL_DESCR("Enable RF I/O flushing"), 154 rtw_sysctl_verify_rfio, 0, &rtw_flush_rfio, 0, 155 CTL_CREATE, CTL_EOL)) != 0) 156 goto err; 157 158 /* force host to control RF I/O bus */ 159 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 160 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 161 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 162 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 163 CTL_CREATE, CTL_EOL)) != 0) 164 goto err; 165 166 /* control RF I/O delay */ 167 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 168 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 169 "rfio_delay", SYSCTL_DESCR("Set RF I/O delay"), 170 rtw_sysctl_verify_rfio_delay, 0, &rtw_rfio_delay, 0, 171 CTL_CREATE, CTL_EOL)) != 0) 172 goto err; 173 174 return; 175 err: 176 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 177 } 178 179 static int 180 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 181 { 182 int error, t; 183 struct sysctlnode node; 184 185 node = *rnode; 186 t = *(int*)rnode->sysctl_data; 187 node.sysctl_data = &t; 188 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 189 if (error || newp == NULL) 190 return (error); 191 192 if (t < lower || t > upper) 193 return (EINVAL); 194 195 *(int*)rnode->sysctl_data = t; 196 197 return (0); 198 } 199 200 static int 201 rtw_sysctl_verify_rfio_delay(SYSCTLFN_ARGS) 202 { 203 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1000000); 204 } 205 206 static int 207 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 208 { 209 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 210 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 211 } 212 213 static int 214 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 215 { 216 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1); 217 } 218 219 #ifdef RTW_DEBUG 220 static int 221 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 222 { 223 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 2); 224 } 225 226 static void 227 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 228 { 229 #define PRINTREG32(sc, reg) \ 230 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 231 dvname, reg, RTW_READ(regs, reg))) 232 233 #define PRINTREG16(sc, reg) \ 234 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %04x\n", \ 235 dvname, reg, RTW_READ16(regs, reg))) 236 237 #define PRINTREG8(sc, reg) \ 238 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %02x\n", \ 239 dvname, reg, RTW_READ8(regs, reg))) 240 241 RTW_DPRINTF2(("%s: %s\n", dvname, where)); 242 243 PRINTREG32(regs, RTW_IDR0); 244 PRINTREG32(regs, RTW_IDR1); 245 PRINTREG32(regs, RTW_MAR0); 246 PRINTREG32(regs, RTW_MAR1); 247 PRINTREG32(regs, RTW_TSFTRL); 248 PRINTREG32(regs, RTW_TSFTRH); 249 PRINTREG32(regs, RTW_TLPDA); 250 PRINTREG32(regs, RTW_TNPDA); 251 PRINTREG32(regs, RTW_THPDA); 252 PRINTREG32(regs, RTW_TCR); 253 PRINTREG32(regs, RTW_RCR); 254 PRINTREG32(regs, RTW_TINT); 255 PRINTREG32(regs, RTW_TBDA); 256 PRINTREG32(regs, RTW_ANAPARM); 257 PRINTREG32(regs, RTW_BB); 258 PRINTREG32(regs, RTW_PHYCFG); 259 PRINTREG32(regs, RTW_WAKEUP0L); 260 PRINTREG32(regs, RTW_WAKEUP0H); 261 PRINTREG32(regs, RTW_WAKEUP1L); 262 PRINTREG32(regs, RTW_WAKEUP1H); 263 PRINTREG32(regs, RTW_WAKEUP2LL); 264 PRINTREG32(regs, RTW_WAKEUP2LH); 265 PRINTREG32(regs, RTW_WAKEUP2HL); 266 PRINTREG32(regs, RTW_WAKEUP2HH); 267 PRINTREG32(regs, RTW_WAKEUP3LL); 268 PRINTREG32(regs, RTW_WAKEUP3LH); 269 PRINTREG32(regs, RTW_WAKEUP3HL); 270 PRINTREG32(regs, RTW_WAKEUP3HH); 271 PRINTREG32(regs, RTW_WAKEUP4LL); 272 PRINTREG32(regs, RTW_WAKEUP4LH); 273 PRINTREG32(regs, RTW_WAKEUP4HL); 274 PRINTREG32(regs, RTW_WAKEUP4HH); 275 PRINTREG32(regs, RTW_DK0); 276 PRINTREG32(regs, RTW_DK1); 277 PRINTREG32(regs, RTW_DK2); 278 PRINTREG32(regs, RTW_DK3); 279 PRINTREG32(regs, RTW_RETRYCTR); 280 PRINTREG32(regs, RTW_RDSAR); 281 PRINTREG32(regs, RTW_FER); 282 PRINTREG32(regs, RTW_FEMR); 283 PRINTREG32(regs, RTW_FPSR); 284 PRINTREG32(regs, RTW_FFER); 285 286 /* 16-bit registers */ 287 PRINTREG16(regs, RTW_BRSR); 288 PRINTREG16(regs, RTW_IMR); 289 PRINTREG16(regs, RTW_ISR); 290 PRINTREG16(regs, RTW_BCNITV); 291 PRINTREG16(regs, RTW_ATIMWND); 292 PRINTREG16(regs, RTW_BINTRITV); 293 PRINTREG16(regs, RTW_ATIMTRITV); 294 PRINTREG16(regs, RTW_CRC16ERR); 295 PRINTREG16(regs, RTW_CRC0); 296 PRINTREG16(regs, RTW_CRC1); 297 PRINTREG16(regs, RTW_CRC2); 298 PRINTREG16(regs, RTW_CRC3); 299 PRINTREG16(regs, RTW_CRC4); 300 PRINTREG16(regs, RTW_CWR); 301 302 /* 8-bit registers */ 303 PRINTREG8(regs, RTW_CR); 304 PRINTREG8(regs, RTW_9346CR); 305 PRINTREG8(regs, RTW_CONFIG0); 306 PRINTREG8(regs, RTW_CONFIG1); 307 PRINTREG8(regs, RTW_CONFIG2); 308 PRINTREG8(regs, RTW_MSR); 309 PRINTREG8(regs, RTW_CONFIG3); 310 PRINTREG8(regs, RTW_CONFIG4); 311 PRINTREG8(regs, RTW_TESTR); 312 PRINTREG8(regs, RTW_PSR); 313 PRINTREG8(regs, RTW_SCR); 314 PRINTREG8(regs, RTW_PHYDELAY); 315 PRINTREG8(regs, RTW_CRCOUNT); 316 PRINTREG8(regs, RTW_PHYADDR); 317 PRINTREG8(regs, RTW_PHYDATAW); 318 PRINTREG8(regs, RTW_PHYDATAR); 319 PRINTREG8(regs, RTW_CONFIG5); 320 PRINTREG8(regs, RTW_TPPOLL); 321 322 PRINTREG16(regs, RTW_BSSID16); 323 PRINTREG32(regs, RTW_BSSID32); 324 #undef PRINTREG32 325 #undef PRINTREG16 326 #undef PRINTREG8 327 } 328 #endif /* RTW_DEBUG */ 329 330 void 331 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 332 { 333 struct rtw_regs *regs = &sc->sc_regs; 334 335 u_int32_t tcr; 336 tcr = RTW_READ(regs, RTW_TCR); 337 tcr &= ~RTW_TCR_LBK_MASK; 338 if (enable) 339 tcr |= RTW_TCR_LBK_CONT; 340 else 341 tcr |= RTW_TCR_LBK_NORMAL; 342 RTW_WRITE(regs, RTW_TCR, tcr); 343 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 344 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 345 rtw_txdac_enable(sc, !enable); 346 rtw_set_access(sc, RTW_ACCESS_ANAPARM); /* XXX Voodoo from Linux. */ 347 rtw_set_access(sc, RTW_ACCESS_NONE); 348 } 349 350 static const char * 351 rtw_access_string(enum rtw_access access) 352 { 353 switch (access) { 354 case RTW_ACCESS_NONE: 355 return "none"; 356 case RTW_ACCESS_CONFIG: 357 return "config"; 358 case RTW_ACCESS_ANAPARM: 359 return "anaparm"; 360 default: 361 return "unknown"; 362 } 363 } 364 365 static void 366 rtw_set_access1(struct rtw_regs *regs, 367 enum rtw_access oaccess, enum rtw_access naccess) 368 { 369 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 370 KASSERT(oaccess >= RTW_ACCESS_NONE && oaccess <= RTW_ACCESS_ANAPARM); 371 372 if (naccess == oaccess) 373 return; 374 375 switch (naccess) { 376 case RTW_ACCESS_NONE: 377 switch (oaccess) { 378 case RTW_ACCESS_ANAPARM: 379 rtw_anaparm_enable(regs, 0); 380 /*FALLTHROUGH*/ 381 case RTW_ACCESS_CONFIG: 382 rtw_config0123_enable(regs, 0); 383 /*FALLTHROUGH*/ 384 case RTW_ACCESS_NONE: 385 break; 386 } 387 break; 388 case RTW_ACCESS_CONFIG: 389 switch (oaccess) { 390 case RTW_ACCESS_NONE: 391 rtw_config0123_enable(regs, 1); 392 /*FALLTHROUGH*/ 393 case RTW_ACCESS_CONFIG: 394 break; 395 case RTW_ACCESS_ANAPARM: 396 rtw_anaparm_enable(regs, 0); 397 break; 398 } 399 break; 400 case RTW_ACCESS_ANAPARM: 401 switch (oaccess) { 402 case RTW_ACCESS_NONE: 403 rtw_config0123_enable(regs, 1); 404 /*FALLTHROUGH*/ 405 case RTW_ACCESS_CONFIG: 406 rtw_anaparm_enable(regs, 1); 407 /*FALLTHROUGH*/ 408 case RTW_ACCESS_ANAPARM: 409 break; 410 } 411 break; 412 } 413 } 414 415 void 416 rtw_set_access(struct rtw_softc *sc, enum rtw_access access) 417 { 418 rtw_set_access1(&sc->sc_regs, sc->sc_access, access); 419 RTW_DPRINTF(("%s: access %s -> %s\n", sc->sc_dev.dv_xname, 420 rtw_access_string(sc->sc_access), 421 rtw_access_string(access))); 422 sc->sc_access = access; 423 } 424 425 /* 426 * Enable registers, switch register banks. 427 */ 428 void 429 rtw_config0123_enable(struct rtw_regs *regs, int enable) 430 { 431 u_int8_t ecr; 432 ecr = RTW_READ8(regs, RTW_9346CR); 433 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 434 if (enable) 435 ecr |= RTW_9346CR_EEM_CONFIG; 436 else 437 ecr |= RTW_9346CR_EEM_NORMAL; 438 RTW_WRITE8(regs, RTW_9346CR, ecr); 439 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 440 } 441 442 /* requires rtw_config0123_enable(, 1) */ 443 void 444 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 445 { 446 u_int8_t cfg3; 447 448 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 449 cfg3 |= RTW_CONFIG3_CLKRUNEN; 450 if (enable) 451 cfg3 |= RTW_CONFIG3_PARMEN; 452 else 453 cfg3 &= ~RTW_CONFIG3_PARMEN; 454 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 455 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 456 } 457 458 /* requires rtw_anaparm_enable(, 1) */ 459 void 460 rtw_txdac_enable(struct rtw_softc *sc, int enable) 461 { 462 u_int32_t anaparm; 463 struct rtw_regs *regs = &sc->sc_regs; 464 465 anaparm = RTW_READ(regs, RTW_ANAPARM); 466 if (enable) 467 anaparm &= ~RTW_ANAPARM_TXDACOFF; 468 else 469 anaparm |= RTW_ANAPARM_TXDACOFF; 470 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 471 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 472 } 473 474 static __inline int 475 rtw_chip_reset1(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 476 { 477 u_int8_t cr; 478 int i; 479 480 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 481 482 RTW_WBR(regs, RTW_CR, RTW_CR); 483 484 for (i = 0; i < 10000; i++) { 485 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 486 RTW_DPRINTF(("%s: reset in %dus\n", *dvname, i)); 487 return 0; 488 } 489 RTW_RBR(regs, RTW_CR, RTW_CR); 490 DELAY(1); /* 1us */ 491 } 492 493 printf("%s: reset failed\n", *dvname); 494 return ETIMEDOUT; 495 } 496 497 static __inline int 498 rtw_chip_reset(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 499 { 500 uint32_t tcr; 501 502 /* from Linux driver */ 503 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 504 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 505 506 RTW_WRITE(regs, RTW_TCR, tcr); 507 508 RTW_WBW(regs, RTW_CR, RTW_TCR); 509 510 return rtw_chip_reset1(regs, dvname); 511 } 512 513 static __inline int 514 rtw_recall_eeprom(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 515 { 516 int i; 517 u_int8_t ecr; 518 519 ecr = RTW_READ8(regs, RTW_9346CR); 520 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 521 RTW_WRITE8(regs, RTW_9346CR, ecr); 522 523 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 524 525 /* wait 2.5ms for completion */ 526 for (i = 0; i < 25; i++) { 527 ecr = RTW_READ8(regs, RTW_9346CR); 528 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 529 RTW_DPRINTF(("%s: recall EEPROM in %dus\n", *dvname, 530 i * 100)); 531 return 0; 532 } 533 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 534 DELAY(100); 535 } 536 printf("%s: recall EEPROM failed\n", *dvname); 537 return ETIMEDOUT; 538 } 539 540 static __inline int 541 rtw_reset(struct rtw_softc *sc) 542 { 543 int rc; 544 uint8_t config1; 545 546 if ((rc = rtw_chip_reset(&sc->sc_regs, &sc->sc_dev.dv_xname)) != 0) 547 return rc; 548 549 if ((rc = rtw_recall_eeprom(&sc->sc_regs, &sc->sc_dev.dv_xname)) != 0) 550 ; 551 552 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 553 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 554 /* TBD turn off maximum power saving? */ 555 556 return 0; 557 } 558 559 static __inline int 560 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txctl *descs, 561 u_int ndescs) 562 { 563 int i, rc = 0; 564 for (i = 0; i < ndescs; i++) { 565 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 566 0, 0, &descs[i].stx_dmamap); 567 if (rc != 0) 568 break; 569 } 570 return rc; 571 } 572 573 static __inline int 574 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 575 u_int ndescs) 576 { 577 int i, rc = 0; 578 for (i = 0; i < ndescs; i++) { 579 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 580 &descs[i].srx_dmamap); 581 if (rc != 0) 582 break; 583 } 584 return rc; 585 } 586 587 static __inline void 588 rtw_rxctls_setup(struct rtw_rxctl *descs) 589 { 590 int i; 591 for (i = 0; i < RTW_RXQLEN; i++) 592 descs[i].srx_mbuf = NULL; 593 } 594 595 static __inline void 596 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 597 u_int ndescs) 598 { 599 int i; 600 for (i = 0; i < ndescs; i++) { 601 if (descs[i].srx_dmamap != NULL) 602 bus_dmamap_destroy(dmat, descs[i].srx_dmamap); 603 } 604 } 605 606 static __inline void 607 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txctl *descs, 608 u_int ndescs) 609 { 610 int i; 611 for (i = 0; i < ndescs; i++) { 612 if (descs[i].stx_dmamap != NULL) 613 bus_dmamap_destroy(dmat, descs[i].stx_dmamap); 614 } 615 } 616 617 static __inline void 618 rtw_srom_free(struct rtw_srom *sr) 619 { 620 sr->sr_size = 0; 621 if (sr->sr_content == NULL) 622 return; 623 free(sr->sr_content, M_DEVBUF); 624 sr->sr_content = NULL; 625 } 626 627 static void 628 rtw_srom_defaults(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 629 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, char (*dvname)[IFNAMSIZ]) 630 { 631 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 632 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 633 *rcr |= RTW_RCR_ENCS1; 634 *rfchipid = RTW_RFCHIPID_PHILIPS; 635 } 636 637 static int 638 rtw_srom_parse(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 639 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, enum rtw_locale *locale, 640 char (*dvname)[IFNAMSIZ]) 641 { 642 int i; 643 const char *rfname, *paname; 644 char scratch[sizeof("unknown 0xXX")]; 645 u_int16_t version; 646 u_int8_t mac[IEEE80211_ADDR_LEN]; 647 648 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 649 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 650 651 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 652 printf("%s: SROM version %d.%d", *dvname, version >> 8, version & 0xff); 653 654 if (version <= 0x0101) { 655 printf(" is not understood, limping along with defaults\n"); 656 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr, 657 dvname); 658 return 0; 659 } 660 printf("\n"); 661 662 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 663 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 664 665 RTW_DPRINTF(("%s: EEPROM MAC %s\n", *dvname, ether_sprintf(mac))); 666 667 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 668 669 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 670 *flags |= RTW_F_ANTDIV; 671 672 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) != 0) 673 *flags |= RTW_F_DIGPHY; 674 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 675 *flags |= RTW_F_DFLANTB; 676 677 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 678 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 679 680 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 681 switch (*rfchipid) { 682 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 683 rfname = "GCT GRF5101"; 684 paname = "Winspring WS9901"; 685 break; 686 case RTW_RFCHIPID_MAXIM: 687 rfname = "Maxim MAX2820"; /* guess */ 688 paname = "Maxim MAX2422"; /* guess */ 689 break; 690 case RTW_RFCHIPID_INTERSIL: 691 rfname = "Intersil HFA3873"; /* guess */ 692 paname = "Intersil <unknown>"; 693 break; 694 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 695 rfname = "Philips SA2400A"; 696 paname = "Philips SA2411"; 697 break; 698 case RTW_RFCHIPID_RFMD: 699 /* this is the same front-end as an atw(4)! */ 700 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 701 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 702 "SYN: Silicon Labs Si4126"; /* inferred from 703 * reference driver 704 */ 705 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 706 break; 707 case RTW_RFCHIPID_RESERVED: 708 rfname = paname = "reserved"; 709 break; 710 default: 711 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 712 rfname = paname = scratch; 713 } 714 printf("%s: RF: %s, PA: %s\n", *dvname, rfname, paname); 715 716 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 717 case RTW_CONFIG0_GL_USA: 718 *locale = RTW_LOCALE_USA; 719 break; 720 case RTW_CONFIG0_GL_EUROPE: 721 *locale = RTW_LOCALE_EUROPE; 722 break; 723 case RTW_CONFIG0_GL_JAPAN: 724 *locale = RTW_LOCALE_JAPAN; 725 break; 726 default: 727 *locale = RTW_LOCALE_UNKNOWN; 728 break; 729 } 730 return 0; 731 } 732 733 /* Returns -1 on failure. */ 734 static int 735 rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr, 736 char (*dvname)[IFNAMSIZ]) 737 { 738 int rc; 739 struct seeprom_descriptor sd; 740 u_int8_t ecr; 741 742 (void)memset(&sd, 0, sizeof(sd)); 743 744 ecr = RTW_READ8(regs, RTW_9346CR); 745 746 if ((flags & RTW_F_9356SROM) != 0) { 747 RTW_DPRINTF(("%s: 93c56 SROM\n", *dvname)); 748 sr->sr_size = 256; 749 sd.sd_chip = C56_66; 750 } else { 751 RTW_DPRINTF(("%s: 93c46 SROM\n", *dvname)); 752 sr->sr_size = 128; 753 sd.sd_chip = C46; 754 } 755 756 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 757 RTW_9346CR_EEM_MASK); 758 ecr |= RTW_9346CR_EEM_PROGRAM; 759 760 RTW_WRITE8(regs, RTW_9346CR, ecr); 761 762 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 763 764 if (sr->sr_content == NULL) { 765 printf("%s: unable to allocate SROM buffer\n", *dvname); 766 return ENOMEM; 767 } 768 769 (void)memset(sr->sr_content, 0, sr->sr_size); 770 771 /* RTL8180 has a single 8-bit register for controlling the 772 * 93cx6 SROM. There is no "ready" bit. The RTL8180 773 * input/output sense is the reverse of read_seeprom's. 774 */ 775 sd.sd_tag = regs->r_bt; 776 sd.sd_bsh = regs->r_bh; 777 sd.sd_regsize = 1; 778 sd.sd_control_offset = RTW_9346CR; 779 sd.sd_status_offset = RTW_9346CR; 780 sd.sd_dataout_offset = RTW_9346CR; 781 sd.sd_CK = RTW_9346CR_EESK; 782 sd.sd_CS = RTW_9346CR_EECS; 783 sd.sd_DI = RTW_9346CR_EEDO; 784 sd.sd_DO = RTW_9346CR_EEDI; 785 /* make read_seeprom enter EEPROM read/write mode */ 786 sd.sd_MS = ecr; 787 sd.sd_RDY = 0; 788 #if 0 789 sd.sd_clkdelay = 50; 790 #endif 791 792 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 793 printf("%s: could not read SROM\n", *dvname); 794 free(sr->sr_content, M_DEVBUF); 795 sr->sr_content = NULL; 796 return -1; /* XXX */ 797 } 798 799 /* end EEPROM read/write mode */ 800 RTW_WRITE8(regs, RTW_9346CR, 801 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 802 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 803 804 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 805 return rc; 806 807 #ifdef RTW_DEBUG 808 { 809 int i; 810 RTW_DPRINTF(("\n%s: serial ROM:\n\t", *dvname)); 811 for (i = 0; i < sr->sr_size/2; i++) { 812 if (((i % 8) == 0) && (i != 0)) 813 RTW_DPRINTF(("\n\t")); 814 RTW_DPRINTF((" %04x", sr->sr_content[i])); 815 } 816 RTW_DPRINTF(("\n")); 817 } 818 #endif /* RTW_DEBUG */ 819 return 0; 820 } 821 822 static void 823 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 824 const char *dvname) 825 { 826 u_int8_t cfg4; 827 const char *method; 828 829 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 830 831 switch (rfchipid) { 832 default: 833 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 834 method = "fallback"; 835 break; 836 case RTW_RFCHIPID_INTERSIL: 837 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 838 method = "Intersil"; 839 break; 840 case RTW_RFCHIPID_PHILIPS: 841 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 842 method = "Philips"; 843 break; 844 case RTW_RFCHIPID_RFMD: 845 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 846 method = "RFMD"; 847 break; 848 } 849 850 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 851 852 printf("%s: %s RF programming method, %#02x\n", dvname, method, 853 RTW_READ8(regs, RTW_CONFIG4)); 854 } 855 856 #if 0 857 static __inline int 858 rtw_identify_rf(struct rtw_regs *regs, enum rtw_rftype *rftype, 859 char (*dvname)[IFNAMSIZ]) 860 { 861 u_int8_t cfg4; 862 const char *name; 863 864 cfg4 = RTW_READ8(regs, RTW_CONFIG4); 865 866 switch (cfg4 & RTW_CONFIG4_RFTYPE_MASK) { 867 case RTW_CONFIG4_RFTYPE_PHILIPS: 868 *rftype = RTW_RFTYPE_PHILIPS; 869 name = "Philips"; 870 break; 871 case RTW_CONFIG4_RFTYPE_INTERSIL: 872 *rftype = RTW_RFTYPE_INTERSIL; 873 name = "Intersil"; 874 break; 875 case RTW_CONFIG4_RFTYPE_RFMD: 876 *rftype = RTW_RFTYPE_RFMD; 877 name = "RFMD"; 878 break; 879 default: 880 name = "<unknown>"; 881 return ENXIO; 882 } 883 884 printf("%s: RF prog type %s\n", *dvname, name); 885 return 0; 886 } 887 #endif 888 889 static __inline void 890 rtw_init_channels(enum rtw_locale locale, 891 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 892 char (*dvname)[IFNAMSIZ]) 893 { 894 int i; 895 const char *name = NULL; 896 #define ADD_CHANNEL(_chans, _chan) do { \ 897 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 898 (*_chans)[_chan].ic_freq = \ 899 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 900 } while (0) 901 902 switch (locale) { 903 case RTW_LOCALE_USA: /* 1-11 */ 904 name = "USA"; 905 for (i = 1; i <= 11; i++) 906 ADD_CHANNEL(chans, i); 907 break; 908 case RTW_LOCALE_JAPAN: /* 1-14 */ 909 name = "Japan"; 910 ADD_CHANNEL(chans, 14); 911 for (i = 1; i <= 14; i++) 912 ADD_CHANNEL(chans, i); 913 break; 914 case RTW_LOCALE_EUROPE: /* 1-13 */ 915 name = "Europe"; 916 for (i = 1; i <= 13; i++) 917 ADD_CHANNEL(chans, i); 918 break; 919 default: /* 10-11 allowed by most countries */ 920 name = "<unknown>"; 921 for (i = 10; i <= 11; i++) 922 ADD_CHANNEL(chans, i); 923 break; 924 } 925 printf("%s: Geographic Location %s\n", *dvname, name); 926 #undef ADD_CHANNEL 927 } 928 929 static __inline void 930 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 931 char (*dvname)[IFNAMSIZ]) 932 { 933 u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 934 935 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 936 case RTW_CONFIG0_GL_USA: 937 *locale = RTW_LOCALE_USA; 938 break; 939 case RTW_CONFIG0_GL_JAPAN: 940 *locale = RTW_LOCALE_JAPAN; 941 break; 942 case RTW_CONFIG0_GL_EUROPE: 943 *locale = RTW_LOCALE_EUROPE; 944 break; 945 default: 946 *locale = RTW_LOCALE_UNKNOWN; 947 break; 948 } 949 } 950 951 static __inline int 952 rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN], 953 char (*dvname)[IFNAMSIZ]) 954 { 955 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 956 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 957 }; 958 u_int32_t idr0 = RTW_READ(regs, RTW_IDR0), 959 idr1 = RTW_READ(regs, RTW_IDR1); 960 961 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 962 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 963 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 964 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 965 966 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 967 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 968 969 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 970 printf("%s: could not get mac address, attach failed\n", 971 *dvname); 972 return ENXIO; 973 } 974 975 printf("%s: 802.11 address %s\n", *dvname, ether_sprintf(*addr)); 976 977 return 0; 978 } 979 980 static u_int8_t 981 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 982 struct ieee80211_channel *chan) 983 { 984 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 985 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 986 ("%s: channel %d out of range", __func__, 987 idx - RTW_SR_TXPOWER1 + 1)); 988 return RTW_SR_GET(sr, idx); 989 } 990 991 static void 992 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *htcs) 993 { 994 int pri; 995 u_int ndesc[RTW_NTXPRI] = 996 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 997 998 for (pri = 0; pri < RTW_NTXPRI; pri++) { 999 htcs[pri].htc_nfree = ndesc[pri]; 1000 htcs[pri].htc_next = 0; 1001 } 1002 } 1003 1004 static int 1005 rtw_txctl_blk_init(struct rtw_txctl_blk *stc) 1006 { 1007 int i; 1008 struct rtw_txctl *stx; 1009 1010 SIMPLEQ_INIT(&stc->stc_dirtyq); 1011 SIMPLEQ_INIT(&stc->stc_freeq); 1012 for (i = 0; i < stc->stc_ndesc; i++) { 1013 stx = &stc->stc_desc[i]; 1014 stx->stx_mbuf = NULL; 1015 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1016 } 1017 return 0; 1018 } 1019 1020 static void 1021 rtw_txctl_blk_init_all(struct rtw_txctl_blk *stcs) 1022 { 1023 int pri; 1024 for (pri = 0; pri < RTW_NTXPRI; pri++) 1025 rtw_txctl_blk_init(&stcs[pri]); 1026 } 1027 1028 static __inline void 1029 rtw_rxdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, u_int desc0, u_int 1030 nsync, int ops) 1031 { 1032 /* sync to end of ring */ 1033 if (desc0 + nsync > RTW_NRXDESC) { 1034 bus_dmamap_sync(dmat, dmap, 1035 offsetof(struct rtw_descs, hd_rx[desc0]), 1036 sizeof(struct rtw_rxdesc) * (RTW_NRXDESC - desc0), ops); 1037 nsync -= (RTW_NRXDESC - desc0); 1038 desc0 = 0; 1039 } 1040 1041 /* sync what remains */ 1042 bus_dmamap_sync(dmat, dmap, 1043 offsetof(struct rtw_descs, hd_rx[desc0]), 1044 sizeof(struct rtw_rxdesc) * nsync, ops); 1045 } 1046 1047 static void 1048 rtw_txdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1049 struct rtw_txdesc_blk *htc, u_int desc0, u_int nsync, int ops) 1050 { 1051 /* sync to end of ring */ 1052 if (desc0 + nsync > htc->htc_ndesc) { 1053 bus_dmamap_sync(dmat, dmap, 1054 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1055 sizeof(struct rtw_txdesc) * (htc->htc_ndesc - desc0), 1056 ops); 1057 nsync -= (htc->htc_ndesc - desc0); 1058 desc0 = 0; 1059 } 1060 1061 /* sync what remains */ 1062 bus_dmamap_sync(dmat, dmap, 1063 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1064 sizeof(struct rtw_txdesc) * nsync, ops); 1065 } 1066 1067 static void 1068 rtw_txdescs_sync_all(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1069 struct rtw_txdesc_blk *htcs) 1070 { 1071 int pri; 1072 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1073 rtw_txdescs_sync(dmat, dmap, 1074 &htcs[pri], 0, htcs[pri].htc_ndesc, 1075 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1076 } 1077 } 1078 1079 static void 1080 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxctl *desc) 1081 { 1082 int i; 1083 struct rtw_rxctl *srx; 1084 1085 for (i = 0; i < RTW_NRXDESC; i++) { 1086 srx = &desc[i]; 1087 bus_dmamap_unload(dmat, srx->srx_dmamap); 1088 m_freem(srx->srx_mbuf); 1089 srx->srx_mbuf = NULL; 1090 } 1091 } 1092 1093 static __inline int 1094 rtw_rxbuf_alloc(bus_dma_tag_t dmat, struct rtw_rxctl *srx) 1095 { 1096 int rc; 1097 struct mbuf *m; 1098 1099 MGETHDR(m, M_DONTWAIT, MT_DATA); 1100 if (m == NULL) 1101 return ENOMEM; 1102 1103 MCLGET(m, M_DONTWAIT); 1104 if (m == NULL) 1105 return ENOMEM; 1106 1107 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1108 1109 rc = bus_dmamap_load_mbuf(dmat, srx->srx_dmamap, m, BUS_DMA_NOWAIT); 1110 if (rc != 0) 1111 return rc; 1112 1113 srx->srx_mbuf = m; 1114 1115 return 0; 1116 } 1117 1118 static int 1119 rtw_rxctl_init_all(bus_dma_tag_t dmat, struct rtw_rxctl *desc, 1120 u_int *next, char (*dvname)[IFNAMSIZ]) 1121 { 1122 int i, rc; 1123 struct rtw_rxctl *srx; 1124 1125 for (i = 0; i < RTW_NRXDESC; i++) { 1126 srx = &desc[i]; 1127 if ((rc = rtw_rxbuf_alloc(dmat, srx)) == 0) 1128 continue; 1129 printf("%s: failed rtw_rxbuf_alloc after %d buffers, rc = %d\n", 1130 *dvname, i, rc); 1131 if (i == 0) { 1132 rtw_rxbufs_release(dmat, desc); 1133 return rc; 1134 } 1135 } 1136 *next = 0; 1137 return 0; 1138 } 1139 1140 static __inline void 1141 rtw_rxdesc_init(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1142 struct rtw_rxdesc *hrx, struct rtw_rxctl *srx, int idx) 1143 { 1144 int is_last = (idx == RTW_NRXDESC - 1); 1145 uint32_t ctl; 1146 1147 hrx->hrx_buf = htole32(srx->srx_dmamap->dm_segs[0].ds_addr); 1148 1149 ctl = LSHIFT(srx->srx_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1150 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1151 1152 if (is_last) 1153 ctl |= RTW_RXCTL_EOR; 1154 1155 hrx->hrx_ctl = htole32(ctl); 1156 1157 /* sync the mbuf */ 1158 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, srx->srx_dmamap->dm_mapsize, 1159 BUS_DMASYNC_PREREAD); 1160 1161 /* sync the descriptor */ 1162 bus_dmamap_sync(dmat, dmam, RTW_DESC_OFFSET(hd_rx, idx), 1163 sizeof(struct rtw_rxdesc), 1164 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1165 } 1166 1167 static void 1168 rtw_rxdesc_init_all(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1169 struct rtw_rxdesc *desc, struct rtw_rxctl *ctl) 1170 { 1171 int i; 1172 struct rtw_rxdesc *hrx; 1173 struct rtw_rxctl *srx; 1174 1175 for (i = 0; i < RTW_NRXDESC; i++) { 1176 hrx = &desc[i]; 1177 srx = &ctl[i]; 1178 rtw_rxdesc_init(dmat, dmam, hrx, srx, i); 1179 } 1180 } 1181 1182 static void 1183 rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable) 1184 { 1185 u_int8_t cr; 1186 1187 RTW_DPRINTF(("%s: %s 0x%02x\n", __func__, 1188 enable ? "enable" : "disable", flags)); 1189 1190 cr = RTW_READ8(regs, RTW_CR); 1191 1192 /* XXX reference source does not enable MULRW */ 1193 #if 0 1194 /* enable PCI Read/Write Multiple */ 1195 cr |= RTW_CR_MULRW; 1196 #endif 1197 1198 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1199 if (enable) 1200 cr |= flags; 1201 else 1202 cr &= ~flags; 1203 RTW_WRITE8(regs, RTW_CR, cr); 1204 RTW_SYNC(regs, RTW_CR, RTW_CR); 1205 } 1206 1207 static void 1208 rtw_intr_rx(struct rtw_softc *sc, u_int16_t isr) 1209 { 1210 u_int next; 1211 int rate, rssi; 1212 u_int32_t hrssi, hstat, htsfth, htsftl; 1213 struct rtw_rxdesc *hrx; 1214 struct rtw_rxctl *srx; 1215 struct mbuf *m; 1216 1217 struct ieee80211_node *ni; 1218 struct ieee80211_frame *wh; 1219 1220 for (next = sc->sc_rxnext; ; next = (next + 1) % RTW_RXQLEN) { 1221 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1222 next, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1223 hrx = &sc->sc_rxdesc[next]; 1224 srx = &sc->sc_rxctl[next]; 1225 1226 hstat = le32toh(hrx->hrx_stat); 1227 hrssi = le32toh(hrx->hrx_rssi); 1228 htsfth = le32toh(hrx->hrx_tsfth); 1229 htsftl = le32toh(hrx->hrx_tsftl); 1230 1231 RTW_DPRINTF2(("%s: rxdesc[%d] hstat %#08x hrssi %#08x " 1232 "htsft %#08x%08x\n", __func__, next, 1233 hstat, hrssi, htsfth, htsftl)); 1234 1235 if ((hstat & RTW_RXSTAT_OWN) != 0) /* belongs to NIC */ 1236 break; 1237 1238 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1239 printf("%s: DMA error/FIFO overflow %08x, " 1240 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1241 hstat & RTW_RXSTAT_IOERROR, next); 1242 goto next; 1243 } 1244 1245 switch (hstat & RTW_RXSTAT_RATE_MASK) { 1246 case RTW_RXSTAT_RATE_1MBPS: 1247 rate = 10; 1248 break; 1249 case RTW_RXSTAT_RATE_2MBPS: 1250 rate = 20; 1251 break; 1252 case RTW_RXSTAT_RATE_5MBPS: 1253 rate = 55; 1254 break; 1255 default: 1256 #ifdef RTW_DEBUG 1257 if (rtw_debug > 1) 1258 printf("%s: interpreting rate #%d as 11 MB/s\n", 1259 sc->sc_dev.dv_xname, 1260 MASK_AND_RSHIFT(hstat, 1261 RTW_RXSTAT_RATE_MASK)); 1262 #endif /* RTW_DEBUG */ 1263 /*FALLTHROUGH*/ 1264 case RTW_RXSTAT_RATE_11MBPS: 1265 rate = 110; 1266 break; 1267 } 1268 1269 RTW_DPRINTF2(("%s: rate %d\n", __func__, rate)); 1270 1271 #ifdef RTW_DEBUG 1272 #define PRINTSTAT(flag) do { \ 1273 if ((hstat & flag) != 0) { \ 1274 printf("%s" #flag, delim); \ 1275 delim = ","; \ 1276 } \ 1277 } while (0) 1278 if (rtw_debug > 1) { 1279 const char *delim = "<"; 1280 printf("%s: ", sc->sc_dev.dv_xname); 1281 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1282 printf("status %08x<", hstat); 1283 PRINTSTAT(RTW_RXSTAT_SPLCP); 1284 PRINTSTAT(RTW_RXSTAT_MAR); 1285 PRINTSTAT(RTW_RXSTAT_PAR); 1286 PRINTSTAT(RTW_RXSTAT_BAR); 1287 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1288 PRINTSTAT(RTW_RXSTAT_CRC32); 1289 PRINTSTAT(RTW_RXSTAT_ICV); 1290 printf(">, "); 1291 } 1292 printf("rate %d.%d Mb/s, time %08x%08x\n", 1293 rate / 10, rate % 10, htsfth, htsftl); 1294 } 1295 #endif /* RTW_DEBUG */ 1296 1297 if ((hstat & RTW_RXSTAT_RES) != 0 && 1298 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1299 goto next; 1300 1301 /* if bad flags, skip descriptor */ 1302 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1303 printf("%s: too many rx segments\n", 1304 sc->sc_dev.dv_xname); 1305 goto next; 1306 } 1307 1308 m = srx->srx_mbuf; 1309 1310 /* if temporarily out of memory, re-use mbuf */ 1311 if (rtw_rxbuf_alloc(sc->sc_dmat, srx) != 0) { 1312 printf("%s: rtw_rxbuf_alloc(, %d) failed, " 1313 "dropping this packet\n", sc->sc_dev.dv_xname, 1314 next); 1315 goto next; 1316 } 1317 1318 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1319 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1320 else { 1321 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1322 /* TBD find out each front-end's LNA gain in the 1323 * front-end's units 1324 */ 1325 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1326 rssi |= 0x80; 1327 } 1328 1329 m->m_pkthdr.len = m->m_len = 1330 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1331 m->m_flags |= M_HASFCS; 1332 1333 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 1334 sc->sc_ic.ic_stats.is_rx_tooshort++; 1335 goto next; 1336 } 1337 wh = mtod(m, struct ieee80211_frame *); 1338 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1339 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1340 1341 sc->sc_tsfth = htsfth; 1342 1343 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1344 ieee80211_release_node(&sc->sc_ic, ni); 1345 next: 1346 rtw_rxdesc_init(sc->sc_dmat, sc->sc_desc_dmamap, 1347 hrx, srx, next); 1348 } 1349 sc->sc_rxnext = next; 1350 1351 return; 1352 } 1353 1354 static void 1355 rtw_intr_tx(struct rtw_softc *sc, u_int16_t isr) 1356 { 1357 /* TBD */ 1358 return; 1359 } 1360 1361 static void 1362 rtw_intr_beacon(struct rtw_softc *sc, u_int16_t isr) 1363 { 1364 /* TBD */ 1365 return; 1366 } 1367 1368 static void 1369 rtw_intr_atim(struct rtw_softc *sc) 1370 { 1371 /* TBD */ 1372 return; 1373 } 1374 1375 static void 1376 rtw_hwring_setup(struct rtw_softc *sc) 1377 { 1378 struct rtw_regs *regs = &sc->sc_regs; 1379 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1380 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1381 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1382 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1383 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1384 } 1385 1386 static void 1387 rtw_swring_setup(struct rtw_softc *sc) 1388 { 1389 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1390 1391 rtw_txctl_blk_init_all(&sc->sc_txctl_blk[0]); 1392 1393 rtw_rxctl_init_all(sc->sc_dmat, sc->sc_rxctl, &sc->sc_rxnext, 1394 &sc->sc_dev.dv_xname); 1395 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, 1396 sc->sc_rxdesc, sc->sc_rxctl); 1397 1398 rtw_txdescs_sync_all(sc->sc_dmat, sc->sc_desc_dmamap, 1399 &sc->sc_txdesc_blk[0]); 1400 #if 0 /* redundant with rtw_rxdesc_init_all */ 1401 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1402 0, RTW_NRXDESC, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1403 #endif 1404 } 1405 1406 static void 1407 rtw_kick(struct rtw_softc *sc) 1408 { 1409 struct rtw_regs *regs = &sc->sc_regs; 1410 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1411 RTW_WRITE16(regs, RTW_IMR, 0); 1412 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1413 /* TBD free tx bufs */ 1414 rtw_swring_setup(sc); 1415 rtw_hwring_setup(sc); 1416 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1417 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1418 } 1419 1420 static void 1421 rtw_intr_ioerror(struct rtw_softc *sc, u_int16_t isr) 1422 { 1423 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) { 1424 rtw_kick(sc); 1425 } 1426 if ((isr & RTW_INTR_TXFOVW) != 0) 1427 ; /* TBD restart transmit engine */ 1428 return; 1429 } 1430 1431 static __inline void 1432 rtw_suspend_ticks(struct rtw_softc *sc) 1433 { 1434 printf("%s: suspending ticks\n", sc->sc_dev.dv_xname); 1435 sc->sc_do_tick = 0; 1436 } 1437 1438 static __inline void 1439 rtw_resume_ticks(struct rtw_softc *sc) 1440 { 1441 u_int32_t tsftrl0, tsftrl1, next_tick; 1442 1443 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1444 1445 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1446 next_tick = tsftrl1 + 1000000; 1447 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1448 1449 sc->sc_do_tick = 1; 1450 1451 printf("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1452 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick); 1453 } 1454 1455 static void 1456 rtw_intr_timeout(struct rtw_softc *sc) 1457 { 1458 printf("%s: timeout\n", sc->sc_dev.dv_xname); 1459 if (sc->sc_do_tick) 1460 rtw_resume_ticks(sc); 1461 return; 1462 } 1463 1464 int 1465 rtw_intr(void *arg) 1466 { 1467 int i; 1468 struct rtw_softc *sc = arg; 1469 struct rtw_regs *regs = &sc->sc_regs; 1470 u_int16_t isr; 1471 1472 /* 1473 * If the interface isn't running, the interrupt couldn't 1474 * possibly have come from us. 1475 */ 1476 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1477 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1478 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1479 RTW_DPRINTF2(("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1480 return (0); 1481 } 1482 1483 for (i = 0; i < 10; i++) { 1484 isr = RTW_READ16(regs, RTW_ISR); 1485 1486 RTW_WRITE16(regs, RTW_ISR, isr); 1487 1488 if (sc->sc_intr_ack != NULL) 1489 (*sc->sc_intr_ack)(regs); 1490 1491 if (isr == 0) 1492 break; 1493 1494 #ifdef RTW_DEBUG 1495 #define PRINTINTR(flag) do { \ 1496 if ((isr & flag) != 0) { \ 1497 printf("%s" #flag, delim); \ 1498 delim = ","; \ 1499 } \ 1500 } while (0) 1501 1502 if (rtw_debug > 1 && isr != 0) { 1503 const char *delim = "<"; 1504 1505 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1506 1507 PRINTINTR(RTW_INTR_TXFOVW); 1508 PRINTINTR(RTW_INTR_TIMEOUT); 1509 PRINTINTR(RTW_INTR_BCNINT); 1510 PRINTINTR(RTW_INTR_ATIMINT); 1511 PRINTINTR(RTW_INTR_TBDER); 1512 PRINTINTR(RTW_INTR_TBDOK); 1513 PRINTINTR(RTW_INTR_THPDER); 1514 PRINTINTR(RTW_INTR_THPDOK); 1515 PRINTINTR(RTW_INTR_TNPDER); 1516 PRINTINTR(RTW_INTR_TNPDOK); 1517 PRINTINTR(RTW_INTR_RXFOVW); 1518 PRINTINTR(RTW_INTR_RDU); 1519 PRINTINTR(RTW_INTR_TLPDER); 1520 PRINTINTR(RTW_INTR_TLPDOK); 1521 PRINTINTR(RTW_INTR_RER); 1522 PRINTINTR(RTW_INTR_ROK); 1523 1524 printf(">\n"); 1525 } 1526 #undef PRINTINTR 1527 #endif /* RTW_DEBUG */ 1528 1529 if ((isr & RTW_INTR_RX) != 0) 1530 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1531 if ((isr & RTW_INTR_TX) != 0) 1532 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1533 if ((isr & RTW_INTR_BEACON) != 0) 1534 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1535 if ((isr & RTW_INTR_ATIMINT) != 0) 1536 rtw_intr_atim(sc); 1537 if ((isr & RTW_INTR_IOERROR) != 0) 1538 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1539 if ((isr & RTW_INTR_TIMEOUT) != 0) 1540 rtw_intr_timeout(sc); 1541 } 1542 1543 return 1; 1544 } 1545 1546 static void 1547 rtw_stop(struct ifnet *ifp, int disable) 1548 { 1549 int s; 1550 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1551 struct ieee80211com *ic = &sc->sc_ic; 1552 struct rtw_regs *regs = &sc->sc_regs; 1553 1554 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1555 return; 1556 1557 rtw_suspend_ticks(sc); 1558 1559 s = splnet(); 1560 1561 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1562 1563 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1564 /* Disable interrupts. */ 1565 RTW_WRITE16(regs, RTW_IMR, 0); 1566 1567 /* Stop the transmit and receive processes. First stop DMA, 1568 * then disable receiver and transmitter. 1569 */ 1570 RTW_WRITE8(regs, RTW_TPPOLL, 1571 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ| 1572 RTW_TPPOLL_SLPQ); 1573 1574 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1575 } 1576 1577 /* TBD Release transmit buffers. */ 1578 1579 if (disable) { 1580 rtw_disable(sc); 1581 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1582 } 1583 1584 /* Mark the interface as not running. Cancel the watchdog timer. */ 1585 ifp->if_flags &= ~IFF_RUNNING; 1586 ifp->if_timer = 0; 1587 1588 splx(s); 1589 1590 return; 1591 } 1592 1593 const char * 1594 rtw_pwrstate_string(enum rtw_pwrstate power) 1595 { 1596 switch (power) { 1597 case RTW_ON: 1598 return "on"; 1599 case RTW_SLEEP: 1600 return "sleep"; 1601 case RTW_OFF: 1602 return "off"; 1603 default: 1604 return "unknown"; 1605 } 1606 } 1607 1608 /* XXX I am using the RFMD settings gleaned from the reference 1609 * driver. 1610 */ 1611 static void 1612 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1613 int before_rf) 1614 { 1615 u_int32_t anaparm; 1616 1617 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1618 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1619 1620 anaparm = RTW_READ(regs, RTW_ANAPARM); 1621 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1622 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1623 1624 switch (power) { 1625 case RTW_OFF: 1626 if (before_rf) 1627 return; 1628 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_OFF; 1629 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_OFF; 1630 anaparm |= RTW_ANAPARM_TXDACOFF; 1631 break; 1632 case RTW_SLEEP: 1633 if (!before_rf) 1634 return; 1635 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_SLEEP; 1636 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_SLEEP; 1637 anaparm |= RTW_ANAPARM_TXDACOFF; 1638 break; 1639 case RTW_ON: 1640 if (!before_rf) 1641 return; 1642 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_ON; 1643 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_ON; 1644 break; 1645 } 1646 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1647 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1648 } 1649 1650 static void 1651 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1652 int before_rf) 1653 { 1654 u_int32_t anaparm; 1655 1656 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1657 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1658 1659 anaparm = RTW_READ(regs, RTW_ANAPARM); 1660 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1661 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1662 1663 switch (power) { 1664 case RTW_OFF: 1665 if (before_rf) 1666 return; 1667 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_OFF; 1668 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_OFF; 1669 anaparm |= RTW_ANAPARM_TXDACOFF; 1670 break; 1671 case RTW_SLEEP: 1672 if (!before_rf) 1673 return; 1674 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_SLEEP; 1675 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_SLEEP; 1676 anaparm |= RTW_ANAPARM_TXDACOFF; 1677 break; 1678 case RTW_ON: 1679 if (!before_rf) 1680 return; 1681 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_ON; 1682 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_ON; 1683 break; 1684 } 1685 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1686 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1687 } 1688 1689 static void 1690 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf) 1691 { 1692 struct rtw_regs *regs = &sc->sc_regs; 1693 1694 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 1695 1696 (*sc->sc_pwrstate_cb)(regs, power, before_rf); 1697 1698 rtw_set_access(sc, RTW_ACCESS_NONE); 1699 1700 return; 1701 } 1702 1703 static int 1704 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 1705 { 1706 int rc; 1707 1708 RTW_DPRINTF2(("%s: %s->%s\n", __func__, 1709 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 1710 1711 if (sc->sc_pwrstate == power) 1712 return 0; 1713 1714 rtw_pwrstate0(sc, power, 1); 1715 rc = rtw_rf_pwrstate(sc->sc_rf, power); 1716 rtw_pwrstate0(sc, power, 0); 1717 1718 switch (power) { 1719 case RTW_ON: 1720 /* TBD set LEDs */ 1721 break; 1722 case RTW_SLEEP: 1723 /* TBD */ 1724 break; 1725 case RTW_OFF: 1726 /* TBD */ 1727 break; 1728 } 1729 if (rc == 0) 1730 sc->sc_pwrstate = power; 1731 else 1732 sc->sc_pwrstate = RTW_OFF; 1733 return rc; 1734 } 1735 1736 static int 1737 rtw_tune(struct rtw_softc *sc) 1738 { 1739 struct ieee80211com *ic = &sc->sc_ic; 1740 u_int chan; 1741 int rc; 1742 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 1743 dflantb = sc->sc_flags & RTW_F_DFLANTB; 1744 1745 KASSERT(ic->ic_bss->ni_chan != NULL); 1746 1747 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1748 if (chan == IEEE80211_CHAN_ANY) 1749 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1750 1751 if (chan == sc->sc_cur_chan) { 1752 RTW_DPRINTF(("%s: already tuned chan #%d\n", __func__, chan)); 1753 return 0; 1754 } 1755 1756 rtw_suspend_ticks(sc); 1757 1758 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 1759 1760 /* TBD wait for Tx to complete */ 1761 1762 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 1763 1764 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 1765 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 1766 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 1767 dflantb, RTW_ON)) != 0) { 1768 /* XXX condition on powersaving */ 1769 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 1770 } 1771 1772 sc->sc_cur_chan = chan; 1773 1774 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 1775 1776 rtw_resume_ticks(sc); 1777 1778 return rc; 1779 } 1780 1781 void 1782 rtw_disable(struct rtw_softc *sc) 1783 { 1784 int rc; 1785 1786 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1787 return; 1788 1789 /* turn off PHY */ 1790 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 1791 printf("%s: failed to turn off PHY (%d)\n", 1792 sc->sc_dev.dv_xname, rc); 1793 1794 if (sc->sc_disable != NULL) 1795 (*sc->sc_disable)(sc); 1796 1797 sc->sc_flags &= ~RTW_F_ENABLED; 1798 } 1799 1800 int 1801 rtw_enable(struct rtw_softc *sc) 1802 { 1803 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 1804 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 1805 printf("%s: device enable failed\n", 1806 sc->sc_dev.dv_xname); 1807 return (EIO); 1808 } 1809 sc->sc_flags |= RTW_F_ENABLED; 1810 } 1811 return (0); 1812 } 1813 1814 static void 1815 rtw_transmit_config(struct rtw_regs *regs) 1816 { 1817 u_int32_t tcr; 1818 1819 tcr = RTW_READ(regs, RTW_TCR); 1820 1821 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 1822 tcr &= ~RTW_TCR_LBK_MASK; 1823 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 1824 1825 /* set short/long retry limits */ 1826 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 1827 tcr |= LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 1828 1829 tcr |= RTW_TCR_CRC; /* NIC appends CRC32 */ 1830 1831 RTW_WRITE(regs, RTW_TCR, tcr); 1832 } 1833 1834 static __inline void 1835 rtw_enable_interrupts(struct rtw_softc *sc) 1836 { 1837 struct rtw_regs *regs = &sc->sc_regs; 1838 1839 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 1840 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 1841 1842 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1843 RTW_WRITE16(regs, RTW_ISR, 0xffff); 1844 1845 /* XXX necessary? */ 1846 if (sc->sc_intr_ack != NULL) 1847 (*sc->sc_intr_ack)(regs); 1848 } 1849 1850 /* XXX is the endianness correct? test. */ 1851 #define rtw_calchash(addr) \ 1852 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1853 1854 static void 1855 rtw_pktfilt_load(struct rtw_softc *sc) 1856 { 1857 struct rtw_regs *regs = &sc->sc_regs; 1858 struct ieee80211com *ic = &sc->sc_ic; 1859 struct ethercom *ec = &ic->ic_ec; 1860 struct ifnet *ifp = &sc->sc_ic.ic_if; 1861 int hash; 1862 u_int32_t hashes[2] = { 0, 0 }; 1863 struct ether_multi *enm; 1864 struct ether_multistep step; 1865 1866 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 1867 1868 #define RTW_RCR_MONITOR (RTW_RCR_ACRC32|RTW_RCR_APM|RTW_RCR_AAP|RTW_RCR_AB) 1869 1870 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1871 sc->sc_rcr |= RTW_RCR_MONITOR; 1872 else 1873 sc->sc_rcr &= ~RTW_RCR_MONITOR; 1874 1875 /* XXX reference sources BEGIN */ 1876 sc->sc_rcr |= RTW_RCR_ENMARP | RTW_RCR_AICV | RTW_RCR_ACRC32; 1877 sc->sc_rcr |= RTW_RCR_AB | RTW_RCR_AM | RTW_RCR_APM; 1878 #if 0 1879 /* receive broadcasts in our BSS */ 1880 sc->sc_rcr |= RTW_RCR_ADD3; 1881 #endif 1882 /* XXX reference sources END */ 1883 1884 /* receive pwrmgmt frames. */ 1885 sc->sc_rcr |= RTW_RCR_APWRMGT; 1886 /* receive mgmt/ctrl/data frames. */ 1887 sc->sc_rcr |= RTW_RCR_AMF | RTW_RCR_ACF | RTW_RCR_ADF; 1888 /* initialize Rx DMA threshold, Tx DMA burst size */ 1889 sc->sc_rcr |= RTW_RCR_RXFTH_WHOLE | RTW_RCR_MXDMA_1024; 1890 1891 ifp->if_flags &= ~IFF_ALLMULTI; 1892 1893 if (ifp->if_flags & IFF_PROMISC) { 1894 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 1895 allmulti: 1896 ifp->if_flags |= IFF_ALLMULTI; 1897 goto setit; 1898 } 1899 1900 /* 1901 * Program the 64-bit multicast hash filter. 1902 */ 1903 ETHER_FIRST_MULTI(step, ec, enm); 1904 while (enm != NULL) { 1905 /* XXX */ 1906 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1907 ETHER_ADDR_LEN) != 0) 1908 goto allmulti; 1909 1910 hash = rtw_calchash(enm->enm_addrlo); 1911 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1912 ETHER_NEXT_MULTI(step, enm); 1913 } 1914 1915 if (ifp->if_flags & IFF_BROADCAST) { 1916 hash = rtw_calchash(etherbroadcastaddr); 1917 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1918 } 1919 1920 /* all bits set => hash is useless */ 1921 if (~(hashes[0] & hashes[1]) == 0) 1922 goto allmulti; 1923 1924 setit: 1925 if (ifp->if_flags & IFF_ALLMULTI) 1926 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 1927 1928 if (ic->ic_state == IEEE80211_S_SCAN) 1929 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 1930 1931 hashes[0] = hashes[1] = 0xffffffff; 1932 1933 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 1934 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 1935 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 1936 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 1937 1938 DPRINTF(sc, ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 1939 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 1940 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 1941 1942 return; 1943 } 1944 1945 static int 1946 rtw_init(struct ifnet *ifp) 1947 { 1948 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1949 struct ieee80211com *ic = &sc->sc_ic; 1950 struct rtw_regs *regs = &sc->sc_regs; 1951 int rc = 0; 1952 1953 if ((rc = rtw_enable(sc)) != 0) 1954 goto out; 1955 1956 /* Cancel pending I/O and reset. */ 1957 rtw_stop(ifp, 0); 1958 1959 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 1960 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1961 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 1962 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 1963 1964 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 1965 goto out; 1966 1967 rtw_swring_setup(sc); 1968 1969 rtw_transmit_config(regs); 1970 1971 rtw_set_access(sc, RTW_ACCESS_CONFIG); 1972 1973 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 1974 1975 /* long PLCP header, 1Mbps basic rate */ 1976 RTW_WRITE16(regs, RTW_BRSR, 0x0); 1977 1978 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 1979 rtw_set_access(sc, RTW_ACCESS_NONE); 1980 1981 #if 0 1982 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_GWAKE|RTW_FEMR_WKUP|RTW_FEMR_INTR); 1983 #endif 1984 /* XXX from reference sources */ 1985 RTW_WRITE(regs, RTW_FEMR, 0xffff); 1986 1987 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 1988 1989 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 1990 /* from Linux driver */ 1991 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 1992 1993 rtw_enable_interrupts(sc); 1994 1995 rtw_pktfilt_load(sc); 1996 1997 rtw_hwring_setup(sc); 1998 1999 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2000 2001 ifp->if_flags |= IFF_RUNNING; 2002 ic->ic_state = IEEE80211_S_INIT; 2003 2004 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2005 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2006 2007 rtw_resume_ticks(sc); 2008 2009 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2010 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2011 2012 switch (ic->ic_opmode) { 2013 case IEEE80211_M_AHDEMO: 2014 case IEEE80211_M_IBSS: 2015 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_ADHOC_OK); 2016 break; 2017 case IEEE80211_M_HOSTAP: 2018 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_AP_OK); 2019 break; 2020 case IEEE80211_M_MONITOR: 2021 /* XXX */ 2022 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_NOLINK); 2023 break; 2024 case IEEE80211_M_STA: 2025 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_INFRA_OK); 2026 break; 2027 } 2028 2029 rtw_set_access(sc, RTW_ACCESS_NONE); 2030 2031 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2032 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2033 else 2034 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2035 2036 out: 2037 return rc; 2038 } 2039 2040 static int 2041 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2042 { 2043 int rc = 0; 2044 struct rtw_softc *sc = ifp->if_softc; 2045 struct ifreq *ifr = (struct ifreq *)data; 2046 2047 switch (cmd) { 2048 case SIOCSIFFLAGS: 2049 if ((ifp->if_flags & IFF_UP) != 0) { 2050 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2051 rtw_pktfilt_load(sc); 2052 } else 2053 rc = rtw_init(ifp); 2054 #ifdef RTW_DEBUG 2055 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2056 #endif /* RTW_DEBUG */ 2057 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2058 #ifdef RTW_DEBUG 2059 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2060 #endif /* RTW_DEBUG */ 2061 rtw_stop(ifp, 1); 2062 } 2063 break; 2064 case SIOCADDMULTI: 2065 case SIOCDELMULTI: 2066 if (cmd == SIOCADDMULTI) 2067 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2068 else 2069 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2070 if (rc == ENETRESET) { 2071 if (ifp->if_flags & IFF_RUNNING) 2072 rtw_pktfilt_load(sc); 2073 rc = 0; 2074 } 2075 break; 2076 default: 2077 if ((rc = ieee80211_ioctl(ifp, cmd, data)) == ENETRESET) { 2078 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2079 rc = rtw_init(ifp); 2080 else 2081 rc = 0; 2082 } 2083 break; 2084 } 2085 return rc; 2086 } 2087 2088 /* Point *mp at the next 802.11 frame to transmit. Point *stcp 2089 * at the driver's selection of transmit control block for the packet. 2090 */ 2091 static __inline int 2092 rtw_dequeue(struct ifnet *ifp, struct rtw_txctl_blk **stcp, struct mbuf **mp, 2093 struct ieee80211_node **nip) 2094 { 2095 struct mbuf *m0; 2096 struct rtw_softc *sc; 2097 struct ieee80211com *ic; 2098 2099 sc = (struct rtw_softc *)ifp->if_softc; 2100 ic = &sc->sc_ic; 2101 2102 *mp = NULL; 2103 2104 if (!IF_IS_EMPTY(&ic->ic_mgtq)) { 2105 IF_DEQUEUE(&ic->ic_mgtq, m0); 2106 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2107 m0->m_pkthdr.rcvif = NULL; 2108 } else if (ic->ic_state != IEEE80211_S_RUN) 2109 return 0; 2110 else if (!IF_IS_EMPTY(&ic->ic_pwrsaveq)) { 2111 IF_DEQUEUE(&ic->ic_pwrsaveq, m0); 2112 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2113 m0->m_pkthdr.rcvif = NULL; 2114 } else { 2115 IFQ_POLL(&ifp->if_snd, m0); 2116 if (m0 == NULL) 2117 return 0; 2118 IFQ_DEQUEUE(&ifp->if_snd, m0); 2119 ifp->if_opackets++; 2120 #if NBPFILTER > 0 2121 if (ifp->if_bpf) 2122 bpf_mtap(ifp->if_bpf, m0); 2123 #endif 2124 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2125 ifp->if_oerrors++; 2126 return -1; 2127 } 2128 } 2129 *stcp = &sc->sc_txctl_blk[RTW_TXPRIMD]; 2130 *mp = m0; 2131 return 0; 2132 } 2133 2134 static void 2135 rtw_start(struct ifnet *ifp) 2136 { 2137 struct mbuf *m0; 2138 struct rtw_softc *sc; 2139 struct rtw_txctl_blk *stc; 2140 struct ieee80211_node *ni; 2141 2142 sc = (struct rtw_softc *)ifp->if_softc; 2143 2144 #if 0 2145 struct ifqueue ic_mgtq; 2146 struct ifqueue ic_pwrsaveq; 2147 struct rtw_txctl_blk { 2148 /* dirty/free s/w descriptors */ 2149 struct rtw_txq stc_dirtyq; 2150 struct rtw_txq stc_freeq; 2151 u_int stc_ndesc; 2152 struct rtw_txctl *stc_desc; 2153 }; 2154 #endif 2155 while (!SIMPLEQ_EMPTY(&stc->stc_freeq)) { 2156 if (rtw_dequeue(ifp, &stc, &m0, &ni) == -1) 2157 continue; 2158 if (m0 == NULL) 2159 break; 2160 ieee80211_release_node(&sc->sc_ic, ni); 2161 } 2162 return; 2163 } 2164 2165 static void 2166 rtw_watchdog(struct ifnet *ifp) 2167 { 2168 /* TBD */ 2169 return; 2170 } 2171 2172 static void 2173 rtw_start_beacon(struct rtw_softc *sc, int enable) 2174 { 2175 /* TBD */ 2176 return; 2177 } 2178 2179 static void 2180 rtw_next_scan(void *arg) 2181 { 2182 struct ieee80211com *ic = arg; 2183 int s; 2184 2185 /* don't call rtw_start w/o network interrupts blocked */ 2186 s = splnet(); 2187 if (ic->ic_state == IEEE80211_S_SCAN) 2188 ieee80211_next_scan(ic); 2189 splx(s); 2190 } 2191 2192 /* Synchronize the hardware state with the software state. */ 2193 static int 2194 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2195 { 2196 struct ifnet *ifp = &ic->ic_if; 2197 struct rtw_softc *sc = ifp->if_softc; 2198 enum ieee80211_state ostate; 2199 int error; 2200 2201 ostate = ic->ic_state; 2202 2203 if (nstate == IEEE80211_S_INIT) { 2204 callout_stop(&sc->sc_scan_ch); 2205 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2206 rtw_start_beacon(sc, 0); 2207 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2208 } 2209 2210 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 2211 rtw_pwrstate(sc, RTW_ON); 2212 2213 if ((error = rtw_tune(sc)) != 0) 2214 return error; 2215 2216 switch (nstate) { 2217 case IEEE80211_S_ASSOC: 2218 break; 2219 case IEEE80211_S_INIT: 2220 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2221 break; 2222 case IEEE80211_S_SCAN: 2223 #if 0 2224 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2225 rtw_write_bssid(sc); 2226 #endif 2227 2228 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 2229 rtw_next_scan, ic); 2230 2231 break; 2232 case IEEE80211_S_RUN: 2233 if (ic->ic_opmode == IEEE80211_M_STA) 2234 break; 2235 /*FALLTHROUGH*/ 2236 case IEEE80211_S_AUTH: 2237 #if 0 2238 rtw_write_bssid(sc); 2239 rtw_write_bcn_thresh(sc); 2240 rtw_write_ssid(sc); 2241 rtw_write_sup_rates(sc); 2242 #endif 2243 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2244 ic->ic_opmode == IEEE80211_M_MONITOR) 2245 break; 2246 2247 /* TBD set listen interval, beacon interval */ 2248 2249 #if 0 2250 rtw_tsf(sc); 2251 #endif 2252 break; 2253 } 2254 2255 if (nstate != IEEE80211_S_SCAN) 2256 callout_stop(&sc->sc_scan_ch); 2257 2258 if (nstate == IEEE80211_S_RUN && 2259 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2260 ic->ic_opmode == IEEE80211_M_IBSS)) 2261 rtw_start_beacon(sc, 1); 2262 else 2263 rtw_start_beacon(sc, 0); 2264 2265 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2266 } 2267 2268 static void 2269 rtw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2270 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2271 { 2272 /* TBD */ 2273 return; 2274 } 2275 2276 static void 2277 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2278 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2279 { 2280 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 2281 2282 switch (subtype) { 2283 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2284 /* do nothing: hardware answers probe request XXX */ 2285 break; 2286 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2287 case IEEE80211_FC0_SUBTYPE_BEACON: 2288 rtw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2289 break; 2290 default: 2291 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2292 break; 2293 } 2294 return; 2295 } 2296 2297 static struct ieee80211_node * 2298 rtw_node_alloc(struct ieee80211com *ic) 2299 { 2300 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2301 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 2302 2303 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 2304 return ni; 2305 } 2306 2307 static void 2308 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 2309 { 2310 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2311 2312 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 2313 ether_sprintf(ni->ni_bssid))); 2314 (*sc->sc_mtbl.mt_node_free)(ic, ni); 2315 } 2316 2317 static int 2318 rtw_media_change(struct ifnet *ifp) 2319 { 2320 int error; 2321 2322 error = ieee80211_media_change(ifp); 2323 if (error == ENETRESET) { 2324 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 2325 (IFF_RUNNING|IFF_UP)) 2326 rtw_init(ifp); /* XXX lose error */ 2327 error = 0; 2328 } 2329 return error; 2330 } 2331 2332 static void 2333 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 2334 { 2335 struct rtw_softc *sc = ifp->if_softc; 2336 2337 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2338 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 2339 imr->ifm_status = 0; 2340 return; 2341 } 2342 ieee80211_media_status(ifp, imr); 2343 } 2344 2345 void 2346 rtw_power(int why, void *arg) 2347 { 2348 struct rtw_softc *sc = arg; 2349 struct ifnet *ifp = &sc->sc_ic.ic_if; 2350 int s; 2351 2352 DPRINTF(sc, ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 2353 2354 s = splnet(); 2355 switch (why) { 2356 case PWR_STANDBY: 2357 /* XXX do nothing. */ 2358 break; 2359 case PWR_SUSPEND: 2360 rtw_stop(ifp, 0); 2361 if (sc->sc_power != NULL) 2362 (*sc->sc_power)(sc, why); 2363 break; 2364 case PWR_RESUME: 2365 if (ifp->if_flags & IFF_UP) { 2366 if (sc->sc_power != NULL) 2367 (*sc->sc_power)(sc, why); 2368 rtw_init(ifp); 2369 } 2370 break; 2371 case PWR_SOFTSUSPEND: 2372 case PWR_SOFTSTANDBY: 2373 case PWR_SOFTRESUME: 2374 break; 2375 } 2376 splx(s); 2377 } 2378 2379 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 2380 void 2381 rtw_shutdown(void *arg) 2382 { 2383 struct rtw_softc *sc = arg; 2384 2385 rtw_stop(&sc->sc_ic.ic_if, 1); 2386 } 2387 2388 static __inline void 2389 rtw_setifprops(struct ifnet *ifp, char (*dvname)[IFNAMSIZ], void *softc) 2390 { 2391 (void)memcpy(ifp->if_xname, *dvname, IFNAMSIZ); 2392 ifp->if_softc = softc; 2393 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 2394 IFF_NOTRAILERS; 2395 ifp->if_ioctl = rtw_ioctl; 2396 ifp->if_start = rtw_start; 2397 ifp->if_watchdog = rtw_watchdog; 2398 ifp->if_init = rtw_init; 2399 ifp->if_stop = rtw_stop; 2400 } 2401 2402 static __inline void 2403 rtw_set80211props(struct ieee80211com *ic) 2404 { 2405 int nrate; 2406 ic->ic_phytype = IEEE80211_T_DS; 2407 ic->ic_opmode = IEEE80211_M_STA; 2408 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 2409 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 2410 2411 nrate = 0; 2412 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 2413 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 2414 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 2415 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 2416 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 2417 } 2418 2419 static __inline void 2420 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 2421 { 2422 mtbl->mt_newstate = ic->ic_newstate; 2423 ic->ic_newstate = rtw_newstate; 2424 2425 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 2426 ic->ic_recv_mgmt = rtw_recv_mgmt; 2427 2428 mtbl->mt_node_free = ic->ic_node_free; 2429 ic->ic_node_free = rtw_node_free; 2430 2431 mtbl->mt_node_alloc = ic->ic_node_alloc; 2432 ic->ic_node_alloc = rtw_node_alloc; 2433 } 2434 2435 static __inline void 2436 rtw_establish_hooks(struct rtw_hooks *hooks, char (*dvname)[IFNAMSIZ], 2437 void *arg) 2438 { 2439 /* 2440 * Make sure the interface is shutdown during reboot. 2441 */ 2442 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 2443 if (hooks->rh_shutdown == NULL) 2444 printf("%s: WARNING: unable to establish shutdown hook\n", 2445 *dvname); 2446 2447 /* 2448 * Add a suspend hook to make sure we come back up after a 2449 * resume. 2450 */ 2451 hooks->rh_power = powerhook_establish(rtw_power, arg); 2452 if (hooks->rh_power == NULL) 2453 printf("%s: WARNING: unable to establish power hook\n", 2454 *dvname); 2455 } 2456 2457 static __inline void 2458 rtw_disestablish_hooks(struct rtw_hooks *hooks, char (*dvname)[IFNAMSIZ], 2459 void *arg) 2460 { 2461 if (hooks->rh_shutdown != NULL) 2462 shutdownhook_disestablish(hooks->rh_shutdown); 2463 2464 if (hooks->rh_power != NULL) 2465 powerhook_disestablish(hooks->rh_power); 2466 } 2467 2468 static __inline void 2469 rtw_init_radiotap(struct rtw_softc *sc) 2470 { 2471 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 2472 sc->sc_rxtap.rr_ihdr.it_len = sizeof(sc->sc_rxtapu); 2473 sc->sc_rxtap.rr_ihdr.it_present = RTW_RX_RADIOTAP_PRESENT; 2474 2475 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 2476 sc->sc_txtap.rt_ihdr.it_len = sizeof(sc->sc_txtapu); 2477 sc->sc_txtap.rt_ihdr.it_present = RTW_TX_RADIOTAP_PRESENT; 2478 } 2479 2480 static int 2481 rtw_txctl_blk_setup(struct rtw_txctl_blk *stc, u_int qlen) 2482 { 2483 SIMPLEQ_INIT(&stc->stc_dirtyq); 2484 SIMPLEQ_INIT(&stc->stc_freeq); 2485 stc->stc_ndesc = qlen; 2486 stc->stc_desc = malloc(qlen * sizeof(*stc->stc_desc), M_DEVBUF, 2487 M_NOWAIT); 2488 if (stc->stc_desc == NULL) 2489 return ENOMEM; 2490 return 0; 2491 } 2492 2493 static void 2494 rtw_txctl_blk_cleanup_all(struct rtw_softc *sc) 2495 { 2496 struct rtw_txctl_blk *stc; 2497 int qlen[RTW_NTXPRI] = 2498 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2499 int pri; 2500 2501 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2502 stc = &sc->sc_txctl_blk[pri]; 2503 free(stc->stc_desc, M_DEVBUF); 2504 stc->stc_desc = NULL; 2505 } 2506 } 2507 2508 static int 2509 rtw_txctl_blk_setup_all(struct rtw_softc *sc) 2510 { 2511 int pri, rc = 0; 2512 int qlen[RTW_NTXPRI] = 2513 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2514 2515 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2516 rc = rtw_txctl_blk_setup(&sc->sc_txctl_blk[pri], qlen[pri]); 2517 if (rc != 0) 2518 break; 2519 } 2520 return rc; 2521 } 2522 2523 static void 2524 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *htc, struct rtw_txdesc *desc, 2525 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 2526 { 2527 int i; 2528 2529 htc->htc_ndesc = ndesc; 2530 htc->htc_desc = desc; 2531 htc->htc_physbase = physbase; 2532 htc->htc_ofs = ofs; 2533 2534 (void)memset(htc->htc_desc, 0, 2535 sizeof(htc->htc_desc[0]) * htc->htc_ndesc); 2536 2537 for (i = 0; i < htc->htc_ndesc; i++) { 2538 htc->htc_desc[i].htx_next = htole32(RTW_NEXT_DESC(htc, i)); 2539 } 2540 } 2541 2542 static void 2543 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 2544 { 2545 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 2546 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 2547 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 2548 2549 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 2550 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 2551 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 2552 2553 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 2554 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 2555 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 2556 2557 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 2558 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 2559 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 2560 } 2561 2562 static struct rtw_rf * 2563 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, 2564 rtw_rf_write_t rf_write, int digphy) 2565 { 2566 struct rtw_rf *rf; 2567 2568 switch (rfchipid) { 2569 case RTW_RFCHIPID_MAXIM: 2570 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 2571 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 2572 break; 2573 case RTW_RFCHIPID_PHILIPS: 2574 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 2575 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 2576 break; 2577 default: 2578 return NULL; 2579 } 2580 rf->rf_continuous_tx_cb = 2581 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 2582 rf->rf_continuous_tx_arg = (void *)sc; 2583 return rf; 2584 } 2585 2586 /* Revision C and later use a different PHY delay setting than 2587 * revisions A and B. 2588 */ 2589 static u_int8_t 2590 rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0) 2591 { 2592 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 2593 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 2594 2595 u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 2596 2597 RTW_WRITE(regs, RTW_RCR, REVAB); 2598 RTW_WRITE(regs, RTW_RCR, REVC); 2599 2600 RTW_WBR(regs, RTW_RCR, RTW_RCR); 2601 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 2602 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 2603 2604 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 2605 2606 return phydelay; 2607 #undef REVC 2608 } 2609 2610 void 2611 rtw_attach(struct rtw_softc *sc) 2612 { 2613 rtw_rf_write_t rf_write; 2614 struct rtw_txctl_blk *stc; 2615 int pri, rc, vers; 2616 2617 #if 0 2618 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_txdesc) == 0, 2619 "RTW_DESC_ALIGNMENT is not a multiple of " 2620 "sizeof(struct rtw_txdesc)"); 2621 2622 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_rxdesc) == 0, 2623 "RTW_DESC_ALIGNMENT is not a multiple of " 2624 "sizeof(struct rtw_rxdesc)"); 2625 2626 CASSERT(RTW_DESC_ALIGNMENT % RTW_MAXPKTSEGS == 0, 2627 "RTW_DESC_ALIGNMENT is not a multiple of RTW_MAXPKTSEGS"); 2628 #endif 2629 2630 NEXT_ATTACH_STATE(sc, DETACHED); 2631 2632 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 2633 case RTW_TCR_HWVERID_F: 2634 vers = 'F'; 2635 rf_write = rtw_rf_hostwrite; 2636 break; 2637 case RTW_TCR_HWVERID_D: 2638 vers = 'D'; 2639 if (rtw_host_rfio) 2640 rf_write = rtw_rf_hostwrite; 2641 else 2642 rf_write = rtw_rf_macwrite; 2643 break; 2644 default: 2645 vers = '?'; 2646 rf_write = rtw_rf_macwrite; 2647 break; 2648 } 2649 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, vers); 2650 2651 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 2652 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 2653 0); 2654 2655 if (rc != 0) { 2656 printf("%s: could not allocate hw descriptors, error %d\n", 2657 sc->sc_dev.dv_xname, rc); 2658 goto err; 2659 } 2660 2661 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 2662 2663 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 2664 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 2665 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 2666 2667 if (rc != 0) { 2668 printf("%s: could not map hw descriptors, error %d\n", 2669 sc->sc_dev.dv_xname, rc); 2670 goto err; 2671 } 2672 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 2673 2674 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 2675 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 2676 2677 if (rc != 0) { 2678 printf("%s: could not create DMA map for hw descriptors, " 2679 "error %d\n", sc->sc_dev.dv_xname, rc); 2680 goto err; 2681 } 2682 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 2683 2684 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 2685 sizeof(struct rtw_descs), NULL, 0); 2686 2687 if (rc != 0) { 2688 printf("%s: could not load DMA map for hw descriptors, " 2689 "error %d\n", sc->sc_dev.dv_xname, rc); 2690 goto err; 2691 } 2692 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 2693 2694 if (rtw_txctl_blk_setup_all(sc) != 0) 2695 goto err; 2696 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 2697 2698 rtw_txdesc_blk_setup_all(sc); 2699 2700 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 2701 2702 sc->sc_rxdesc = &sc->sc_descs->hd_rx[0]; 2703 2704 rtw_rxctls_setup(&sc->sc_rxctl[0]); 2705 2706 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2707 stc = &sc->sc_txctl_blk[pri]; 2708 2709 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 2710 &stc->stc_desc[0], stc->stc_ndesc)) != 0) { 2711 printf("%s: could not load DMA map for " 2712 "hw tx descriptors, error %d\n", 2713 sc->sc_dev.dv_xname, rc); 2714 goto err; 2715 } 2716 } 2717 2718 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 2719 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxctl[0], 2720 RTW_RXQLEN)) != 0) { 2721 printf("%s: could not load DMA map for hw rx descriptors, " 2722 "error %d\n", sc->sc_dev.dv_xname, rc); 2723 goto err; 2724 } 2725 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 2726 2727 /* Reset the chip to a known state. */ 2728 if (rtw_reset(sc) != 0) 2729 goto err; 2730 NEXT_ATTACH_STATE(sc, FINISH_RESET); 2731 2732 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 2733 2734 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 2735 sc->sc_flags |= RTW_F_9356SROM; 2736 2737 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 2738 &sc->sc_dev.dv_xname) != 0) 2739 goto err; 2740 2741 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 2742 2743 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 2744 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 2745 &sc->sc_dev.dv_xname) != 0) { 2746 printf("%s: attach failed, malformed serial ROM\n", 2747 sc->sc_dev.dv_xname); 2748 goto err; 2749 } 2750 2751 RTW_DPRINTF(("%s: CS threshold %u\n", sc->sc_dev.dv_xname, 2752 sc->sc_csthr)); 2753 2754 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 2755 2756 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, rf_write, 2757 sc->sc_flags & RTW_F_DIGPHY); 2758 2759 if (sc->sc_rf == NULL) { 2760 printf("%s: attach failed, could not attach RF\n", 2761 sc->sc_dev.dv_xname); 2762 goto err; 2763 } 2764 2765 #if 0 2766 if (rtw_identify_rf(&sc->sc_regs, &sc->sc_rftype, 2767 &sc->sc_dev.dv_xname) != 0) { 2768 printf("%s: attach failed, unknown RF unidentified\n", 2769 sc->sc_dev.dv_xname); 2770 goto err; 2771 } 2772 #endif 2773 2774 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 2775 2776 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 2777 2778 RTW_DPRINTF(("%s: PHY delay %d\n", sc->sc_dev.dv_xname, 2779 sc->sc_phydelay)); 2780 2781 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 2782 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 2783 &sc->sc_dev.dv_xname); 2784 2785 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 2786 &sc->sc_dev.dv_xname); 2787 2788 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 2789 &sc->sc_dev.dv_xname) != 0) 2790 goto err; 2791 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 2792 2793 rtw_setifprops(&sc->sc_if, &sc->sc_dev.dv_xname, (void*)sc); 2794 2795 IFQ_SET_READY(&sc->sc_if.if_snd); 2796 2797 rtw_set80211props(&sc->sc_ic); 2798 2799 /* 2800 * Call MI attach routines. 2801 */ 2802 if_attach(&sc->sc_if); 2803 ieee80211_ifattach(&sc->sc_if); 2804 2805 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 2806 2807 /* possibly we should fill in our own sc_send_prresp, since 2808 * the RTL8180 is probably sending probe responses in ad hoc 2809 * mode. 2810 */ 2811 2812 /* complete initialization */ 2813 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 2814 callout_init(&sc->sc_scan_ch); 2815 2816 #if NBPFILTER > 0 2817 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 2818 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 2819 #endif 2820 2821 rtw_establish_hooks(&sc->sc_hooks, &sc->sc_dev.dv_xname, (void*)sc); 2822 2823 rtw_init_radiotap(sc); 2824 2825 NEXT_ATTACH_STATE(sc, FINISHED); 2826 2827 return; 2828 err: 2829 rtw_detach(sc); 2830 return; 2831 } 2832 2833 int 2834 rtw_detach(struct rtw_softc *sc) 2835 { 2836 int pri; 2837 2838 switch (sc->sc_attach_state) { 2839 case FINISHED: 2840 rtw_stop(&sc->sc_if, 1); 2841 2842 rtw_disestablish_hooks(&sc->sc_hooks, &sc->sc_dev.dv_xname, 2843 (void*)sc); 2844 callout_stop(&sc->sc_scan_ch); 2845 ieee80211_ifdetach(&sc->sc_if); 2846 if_detach(&sc->sc_if); 2847 break; 2848 case FINISH_ID_STA: 2849 case FINISH_RF_ATTACH: 2850 rtw_rf_destroy(sc->sc_rf); 2851 sc->sc_rf = NULL; 2852 /*FALLTHROUGH*/ 2853 case FINISH_PARSE_SROM: 2854 case FINISH_READ_SROM: 2855 rtw_srom_free(&sc->sc_srom); 2856 /*FALLTHROUGH*/ 2857 case FINISH_RESET: 2858 case FINISH_RXMAPS_CREATE: 2859 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxctl[0], 2860 RTW_RXQLEN); 2861 /*FALLTHROUGH*/ 2862 case FINISH_TXMAPS_CREATE: 2863 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2864 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 2865 sc->sc_txctl_blk[pri].stc_desc, 2866 sc->sc_txctl_blk[pri].stc_ndesc); 2867 } 2868 /*FALLTHROUGH*/ 2869 case FINISH_TXDESCBLK_SETUP: 2870 case FINISH_TXCTLBLK_SETUP: 2871 rtw_txctl_blk_cleanup_all(sc); 2872 /*FALLTHROUGH*/ 2873 case FINISH_DESCMAP_LOAD: 2874 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 2875 /*FALLTHROUGH*/ 2876 case FINISH_DESCMAP_CREATE: 2877 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 2878 /*FALLTHROUGH*/ 2879 case FINISH_DESC_MAP: 2880 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 2881 sizeof(struct rtw_descs)); 2882 /*FALLTHROUGH*/ 2883 case FINISH_DESC_ALLOC: 2884 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 2885 sc->sc_desc_nsegs); 2886 /*FALLTHROUGH*/ 2887 case DETACHED: 2888 NEXT_ATTACH_STATE(sc, DETACHED); 2889 break; 2890 } 2891 return 0; 2892 } 2893 2894 int 2895 rtw_activate(struct device *self, enum devact act) 2896 { 2897 struct rtw_softc *sc = (struct rtw_softc *)self; 2898 int rc = 0, s; 2899 2900 s = splnet(); 2901 switch (act) { 2902 case DVACT_ACTIVATE: 2903 rc = EOPNOTSUPP; 2904 break; 2905 2906 case DVACT_DEACTIVATE: 2907 if_deactivate(&sc->sc_ic.ic_if); 2908 break; 2909 } 2910 splx(s); 2911 return rc; 2912 } 2913
Indexes created Mon Oct 27 08:10:08 GMT 2025