rtw.c revision 1.1.2.5
1 /* $NetBSD: rtw.c,v 1.1.2.5 2005/01/17 19:30:40 skrll Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.1.2.5 2005/01/17 19:30:40 skrll Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/time.h> 49 #include <sys/types.h> 50 51 #include <machine/endian.h> 52 #include <machine/bus.h> 53 #include <machine/intr.h> /* splnet */ 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #include <net80211/ieee80211_var.h> 62 #include <net80211/ieee80211_compat.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <dev/ic/rtwreg.h> 70 #include <dev/ic/rtwvar.h> 71 #include <dev/ic/rtwphyio.h> 72 #include <dev/ic/rtwphy.h> 73 74 #include <dev/ic/smc93cx6var.h> 75 76 #define KASSERT2(__cond, __msg) \ 77 do { \ 78 if (!(__cond)) \ 79 panic __msg ; \ 80 } while (0) 81 82 int rtw_rfprog_fallback = 0; 83 int rtw_host_rfio = 0; 84 85 #ifdef RTW_DEBUG 86 int rtw_debug = 0; 87 int rtw_rxbufs_limit = RTW_RXQLEN; 88 #endif /* RTW_DEBUG */ 89 90 #define NEXT_ATTACH_STATE(sc, state) do { \ 91 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 92 ("%s: attach state %s\n", __func__, #state)); \ 93 sc->sc_attach_state = state; \ 94 } while (0) 95 96 int rtw_dwelltime = 200; /* milliseconds */ 97 98 static void rtw_start(struct ifnet *); 99 100 static void rtw_led_attach(struct rtw_softc *); 101 static void rtw_led_init(struct rtw_regs *); 102 static void rtw_led_slowblink(void *); 103 static void rtw_led_fastblink(void *); 104 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 105 106 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 107 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 108 #ifdef RTW_DEBUG 109 static void rtw_print_txdesc(struct rtw_softc *, const char *, 110 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 111 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 112 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 113 #endif /* RTW_DEBUG */ 114 115 /* 116 * Setup sysctl(3) MIB, hw.rtw.* 117 * 118 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 119 */ 120 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 121 { 122 int rc; 123 struct sysctlnode *cnode, *rnode; 124 125 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 126 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 127 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 128 goto err; 129 130 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 131 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 132 "Realtek RTL818x 802.11 controls", 133 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 134 goto err; 135 136 #ifdef RTW_DEBUG 137 /* control debugging printfs */ 138 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 139 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 140 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 141 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 142 CTL_CREATE, CTL_EOL)) != 0) 143 goto err; 144 145 /* Limit rx buffers, for simulating resource exhaustion. */ 146 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 147 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 148 "rxbufs_limit", 149 SYSCTL_DESCR("Set rx buffers limit"), 150 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 151 CTL_CREATE, CTL_EOL)) != 0) 152 goto err; 153 154 #endif /* RTW_DEBUG */ 155 /* set fallback RF programming method */ 156 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 157 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 158 "rfprog_fallback", 159 SYSCTL_DESCR("Set fallback RF programming method"), 160 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 161 CTL_CREATE, CTL_EOL)) != 0) 162 goto err; 163 164 /* force host to control RF I/O bus */ 165 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 166 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 167 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 168 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 169 CTL_CREATE, CTL_EOL)) != 0) 170 goto err; 171 172 return; 173 err: 174 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 175 } 176 177 static int 178 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 179 { 180 int error, t; 181 struct sysctlnode node; 182 183 node = *rnode; 184 t = *(int*)rnode->sysctl_data; 185 node.sysctl_data = &t; 186 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 187 if (error || newp == NULL) 188 return (error); 189 190 if (t < lower || t > upper) 191 return (EINVAL); 192 193 *(int*)rnode->sysctl_data = t; 194 195 return (0); 196 } 197 198 static int 199 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 200 { 201 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 202 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 203 } 204 205 static int 206 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 207 { 208 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1); 209 } 210 211 #ifdef RTW_DEBUG 212 static int 213 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 214 { 215 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, RTW_DEBUG_MAX); 216 } 217 218 static int 219 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 220 { 221 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, RTW_RXQLEN); 222 } 223 224 static void 225 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 226 { 227 #define PRINTREG32(sc, reg) \ 228 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 229 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 230 dvname, reg, RTW_READ(regs, reg))) 231 232 #define PRINTREG16(sc, reg) \ 233 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 234 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 235 dvname, reg, RTW_READ16(regs, reg))) 236 237 #define PRINTREG8(sc, reg) \ 238 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 239 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 240 dvname, reg, RTW_READ8(regs, reg))) 241 242 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 243 244 PRINTREG32(regs, RTW_IDR0); 245 PRINTREG32(regs, RTW_IDR1); 246 PRINTREG32(regs, RTW_MAR0); 247 PRINTREG32(regs, RTW_MAR1); 248 PRINTREG32(regs, RTW_TSFTRL); 249 PRINTREG32(regs, RTW_TSFTRH); 250 PRINTREG32(regs, RTW_TLPDA); 251 PRINTREG32(regs, RTW_TNPDA); 252 PRINTREG32(regs, RTW_THPDA); 253 PRINTREG32(regs, RTW_TCR); 254 PRINTREG32(regs, RTW_RCR); 255 PRINTREG32(regs, RTW_TINT); 256 PRINTREG32(regs, RTW_TBDA); 257 PRINTREG32(regs, RTW_ANAPARM); 258 PRINTREG32(regs, RTW_BB); 259 PRINTREG32(regs, RTW_PHYCFG); 260 PRINTREG32(regs, RTW_WAKEUP0L); 261 PRINTREG32(regs, RTW_WAKEUP0H); 262 PRINTREG32(regs, RTW_WAKEUP1L); 263 PRINTREG32(regs, RTW_WAKEUP1H); 264 PRINTREG32(regs, RTW_WAKEUP2LL); 265 PRINTREG32(regs, RTW_WAKEUP2LH); 266 PRINTREG32(regs, RTW_WAKEUP2HL); 267 PRINTREG32(regs, RTW_WAKEUP2HH); 268 PRINTREG32(regs, RTW_WAKEUP3LL); 269 PRINTREG32(regs, RTW_WAKEUP3LH); 270 PRINTREG32(regs, RTW_WAKEUP3HL); 271 PRINTREG32(regs, RTW_WAKEUP3HH); 272 PRINTREG32(regs, RTW_WAKEUP4LL); 273 PRINTREG32(regs, RTW_WAKEUP4LH); 274 PRINTREG32(regs, RTW_WAKEUP4HL); 275 PRINTREG32(regs, RTW_WAKEUP4HH); 276 PRINTREG32(regs, RTW_DK0); 277 PRINTREG32(regs, RTW_DK1); 278 PRINTREG32(regs, RTW_DK2); 279 PRINTREG32(regs, RTW_DK3); 280 PRINTREG32(regs, RTW_RETRYCTR); 281 PRINTREG32(regs, RTW_RDSAR); 282 PRINTREG32(regs, RTW_FER); 283 PRINTREG32(regs, RTW_FEMR); 284 PRINTREG32(regs, RTW_FPSR); 285 PRINTREG32(regs, RTW_FFER); 286 287 /* 16-bit registers */ 288 PRINTREG16(regs, RTW_BRSR); 289 PRINTREG16(regs, RTW_IMR); 290 PRINTREG16(regs, RTW_ISR); 291 PRINTREG16(regs, RTW_BCNITV); 292 PRINTREG16(regs, RTW_ATIMWND); 293 PRINTREG16(regs, RTW_BINTRITV); 294 PRINTREG16(regs, RTW_ATIMTRITV); 295 PRINTREG16(regs, RTW_CRC16ERR); 296 PRINTREG16(regs, RTW_CRC0); 297 PRINTREG16(regs, RTW_CRC1); 298 PRINTREG16(regs, RTW_CRC2); 299 PRINTREG16(regs, RTW_CRC3); 300 PRINTREG16(regs, RTW_CRC4); 301 PRINTREG16(regs, RTW_CWR); 302 303 /* 8-bit registers */ 304 PRINTREG8(regs, RTW_CR); 305 PRINTREG8(regs, RTW_9346CR); 306 PRINTREG8(regs, RTW_CONFIG0); 307 PRINTREG8(regs, RTW_CONFIG1); 308 PRINTREG8(regs, RTW_CONFIG2); 309 PRINTREG8(regs, RTW_MSR); 310 PRINTREG8(regs, RTW_CONFIG3); 311 PRINTREG8(regs, RTW_CONFIG4); 312 PRINTREG8(regs, RTW_TESTR); 313 PRINTREG8(regs, RTW_PSR); 314 PRINTREG8(regs, RTW_SCR); 315 PRINTREG8(regs, RTW_PHYDELAY); 316 PRINTREG8(regs, RTW_CRCOUNT); 317 PRINTREG8(regs, RTW_PHYADDR); 318 PRINTREG8(regs, RTW_PHYDATAW); 319 PRINTREG8(regs, RTW_PHYDATAR); 320 PRINTREG8(regs, RTW_CONFIG5); 321 PRINTREG8(regs, RTW_TPPOLL); 322 323 PRINTREG16(regs, RTW_BSSID16); 324 PRINTREG32(regs, RTW_BSSID32); 325 #undef PRINTREG32 326 #undef PRINTREG16 327 #undef PRINTREG8 328 } 329 #endif /* RTW_DEBUG */ 330 331 void 332 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 333 { 334 struct rtw_regs *regs = &sc->sc_regs; 335 336 uint32_t tcr; 337 tcr = RTW_READ(regs, RTW_TCR); 338 tcr &= ~RTW_TCR_LBK_MASK; 339 if (enable) 340 tcr |= RTW_TCR_LBK_CONT; 341 else 342 tcr |= RTW_TCR_LBK_NORMAL; 343 RTW_WRITE(regs, RTW_TCR, tcr); 344 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 345 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 346 rtw_txdac_enable(sc, !enable); 347 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 348 rtw_set_access(regs, RTW_ACCESS_NONE); 349 } 350 351 #ifdef RTW_DEBUG 352 static const char * 353 rtw_access_string(enum rtw_access access) 354 { 355 switch (access) { 356 case RTW_ACCESS_NONE: 357 return "none"; 358 case RTW_ACCESS_CONFIG: 359 return "config"; 360 case RTW_ACCESS_ANAPARM: 361 return "anaparm"; 362 default: 363 return "unknown"; 364 } 365 } 366 #endif /* RTW_DEBUG */ 367 368 static void 369 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 370 { 371 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 372 KASSERT(regs->r_access >= RTW_ACCESS_NONE && 373 regs->r_access <= RTW_ACCESS_ANAPARM); 374 375 if (naccess == regs->r_access) 376 return; 377 378 switch (naccess) { 379 case RTW_ACCESS_NONE: 380 switch (regs->r_access) { 381 case RTW_ACCESS_ANAPARM: 382 rtw_anaparm_enable(regs, 0); 383 /*FALLTHROUGH*/ 384 case RTW_ACCESS_CONFIG: 385 rtw_config0123_enable(regs, 0); 386 /*FALLTHROUGH*/ 387 case RTW_ACCESS_NONE: 388 break; 389 } 390 break; 391 case RTW_ACCESS_CONFIG: 392 switch (regs->r_access) { 393 case RTW_ACCESS_NONE: 394 rtw_config0123_enable(regs, 1); 395 /*FALLTHROUGH*/ 396 case RTW_ACCESS_CONFIG: 397 break; 398 case RTW_ACCESS_ANAPARM: 399 rtw_anaparm_enable(regs, 0); 400 break; 401 } 402 break; 403 case RTW_ACCESS_ANAPARM: 404 switch (regs->r_access) { 405 case RTW_ACCESS_NONE: 406 rtw_config0123_enable(regs, 1); 407 /*FALLTHROUGH*/ 408 case RTW_ACCESS_CONFIG: 409 rtw_anaparm_enable(regs, 1); 410 /*FALLTHROUGH*/ 411 case RTW_ACCESS_ANAPARM: 412 break; 413 } 414 break; 415 } 416 } 417 418 void 419 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 420 { 421 rtw_set_access1(regs, access); 422 RTW_DPRINTF(RTW_DEBUG_ACCESS, 423 ("%s: access %s -> %s\n", __func__, 424 rtw_access_string(regs->r_access), 425 rtw_access_string(access))); 426 regs->r_access = access; 427 } 428 429 /* 430 * Enable registers, switch register banks. 431 */ 432 void 433 rtw_config0123_enable(struct rtw_regs *regs, int enable) 434 { 435 uint8_t ecr; 436 ecr = RTW_READ8(regs, RTW_9346CR); 437 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 438 if (enable) 439 ecr |= RTW_9346CR_EEM_CONFIG; 440 else { 441 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 442 ecr |= RTW_9346CR_EEM_NORMAL; 443 } 444 RTW_WRITE8(regs, RTW_9346CR, ecr); 445 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 446 } 447 448 /* requires rtw_config0123_enable(, 1) */ 449 void 450 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 451 { 452 uint8_t cfg3; 453 454 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 455 cfg3 |= RTW_CONFIG3_CLKRUNEN; 456 if (enable) 457 cfg3 |= RTW_CONFIG3_PARMEN; 458 else 459 cfg3 &= ~RTW_CONFIG3_PARMEN; 460 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 461 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 462 } 463 464 /* requires rtw_anaparm_enable(, 1) */ 465 void 466 rtw_txdac_enable(struct rtw_softc *sc, int enable) 467 { 468 uint32_t anaparm; 469 struct rtw_regs *regs = &sc->sc_regs; 470 471 anaparm = RTW_READ(regs, RTW_ANAPARM); 472 if (enable) 473 anaparm &= ~RTW_ANAPARM_TXDACOFF; 474 else 475 anaparm |= RTW_ANAPARM_TXDACOFF; 476 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 477 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 478 } 479 480 static __inline int 481 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 482 { 483 uint8_t cr; 484 int i; 485 486 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 487 488 RTW_WBR(regs, RTW_CR, RTW_CR); 489 490 for (i = 0; i < 1000; i++) { 491 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 492 RTW_DPRINTF(RTW_DEBUG_RESET, 493 ("%s: reset in %dus\n", dvname, i)); 494 return 0; 495 } 496 RTW_RBR(regs, RTW_CR, RTW_CR); 497 DELAY(10); /* 10us */ 498 } 499 500 printf("%s: reset failed\n", dvname); 501 return ETIMEDOUT; 502 } 503 504 static __inline int 505 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 506 { 507 uint32_t tcr; 508 509 /* from Linux driver */ 510 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 511 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 512 513 RTW_WRITE(regs, RTW_TCR, tcr); 514 515 RTW_WBW(regs, RTW_CR, RTW_TCR); 516 517 return rtw_chip_reset1(regs, dvname); 518 } 519 520 static void 521 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_wepkey *wk, int txkey) 522 { 523 uint8_t cfg0, scr; 524 int i, j, tx_key_len; 525 struct rtw_regs *regs; 526 union rtw_keys *rk; 527 528 regs = &sc->sc_regs; 529 rk = &sc->sc_keys; 530 531 (void)memset(rk->rk_keys, 0, sizeof(rk->rk_keys)); 532 533 scr = RTW_READ8(regs, RTW_SCR); 534 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 535 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 536 cfg0 &= ~(RTW_CONFIG0_WEP104 | RTW_CONFIG0_WEP40); 537 538 rtw_set_access(regs, RTW_ACCESS_CONFIG); 539 540 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 541 goto out; 542 543 tx_key_len = wk[txkey].wk_len; 544 545 switch (tx_key_len) { 546 case 5: 547 scr |= RTW_SCR_TXSECON | RTW_SCR_RXSECON | RTW_SCR_KM_WEP40; 548 break; 549 case 13: 550 scr |= RTW_SCR_TXSECON | RTW_SCR_RXSECON | RTW_SCR_KM_WEP104; 551 break; 552 default: 553 goto out; 554 } 555 556 cfg0 |= RTW_CONFIG0_WEP104 | RTW_CONFIG0_WEP40; 557 558 for (i = j = 0; i < IEEE80211_WEP_NKID; i++) { 559 if (i == txkey) 560 sc->sc_txkey = j; 561 else if (wk[i].wk_len != tx_key_len) 562 continue; 563 (void)memcpy(rk->rk_keys[j++], wk[i].wk_key, wk[i].wk_len); 564 } 565 566 out: 567 bus_space_write_region_4(regs->r_bt, regs->r_bh, 568 RTW_DK0, rk->rk_words, 569 sizeof(rk->rk_words) / sizeof(rk->rk_words[0])); 570 571 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, 572 sizeof(rk->rk_words) / sizeof(rk->rk_words[0]), 573 BUS_SPACE_BARRIER_SYNC); 574 575 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 576 RTW_WBW(regs, RTW_CONFIG0, RTW_SCR); 577 RTW_WRITE8(regs, RTW_SCR, scr); 578 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 579 rtw_set_access(regs, RTW_ACCESS_NONE); 580 } 581 582 static __inline int 583 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 584 { 585 int i; 586 uint8_t ecr; 587 588 ecr = RTW_READ8(regs, RTW_9346CR); 589 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 590 RTW_WRITE8(regs, RTW_9346CR, ecr); 591 592 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 593 594 /* wait 2.5ms for completion */ 595 for (i = 0; i < 25; i++) { 596 ecr = RTW_READ8(regs, RTW_9346CR); 597 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 598 RTW_DPRINTF(RTW_DEBUG_RESET, 599 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 600 return 0; 601 } 602 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 603 DELAY(100); 604 } 605 printf("%s: recall EEPROM failed\n", dvname); 606 return ETIMEDOUT; 607 } 608 609 static __inline int 610 rtw_reset(struct rtw_softc *sc) 611 { 612 int rc; 613 uint8_t config1; 614 615 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 616 return rc; 617 618 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 619 ; 620 621 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 622 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 623 /* TBD turn off maximum power saving? */ 624 625 return 0; 626 } 627 628 static __inline int 629 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 630 u_int ndescs) 631 { 632 int i, rc = 0; 633 for (i = 0; i < ndescs; i++) { 634 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 635 0, 0, &descs[i].ts_dmamap); 636 if (rc != 0) 637 break; 638 } 639 return rc; 640 } 641 642 static __inline int 643 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 644 u_int ndescs) 645 { 646 int i, rc = 0; 647 for (i = 0; i < ndescs; i++) { 648 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 649 &descs[i].rs_dmamap); 650 if (rc != 0) 651 break; 652 } 653 return rc; 654 } 655 656 static __inline void 657 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 658 u_int ndescs) 659 { 660 int i; 661 for (i = 0; i < ndescs; i++) { 662 if (descs[i].rs_dmamap != NULL) 663 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 664 } 665 } 666 667 static __inline void 668 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 669 u_int ndescs) 670 { 671 int i; 672 for (i = 0; i < ndescs; i++) { 673 if (descs[i].ts_dmamap != NULL) 674 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 675 } 676 } 677 678 static __inline void 679 rtw_srom_free(struct rtw_srom *sr) 680 { 681 sr->sr_size = 0; 682 if (sr->sr_content == NULL) 683 return; 684 free(sr->sr_content, M_DEVBUF); 685 sr->sr_content = NULL; 686 } 687 688 static void 689 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 690 enum rtw_rfchipid *rfchipid, uint32_t *rcr) 691 { 692 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 693 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 694 *rcr |= RTW_RCR_ENCS1; 695 *rfchipid = RTW_RFCHIPID_PHILIPS; 696 } 697 698 static int 699 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 700 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 701 const char *dvname) 702 { 703 int i; 704 const char *rfname, *paname; 705 char scratch[sizeof("unknown 0xXX")]; 706 uint16_t version; 707 uint8_t mac[IEEE80211_ADDR_LEN]; 708 709 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 710 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 711 712 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 713 printf("%s: SROM version %d.%d", dvname, version >> 8, version & 0xff); 714 715 if (version <= 0x0101) { 716 printf(" is not understood, limping along with defaults\n"); 717 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 718 return 0; 719 } 720 printf("\n"); 721 722 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 723 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 724 725 RTW_DPRINTF(RTW_DEBUG_ATTACH, 726 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 727 728 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 729 730 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 731 *flags |= RTW_F_ANTDIV; 732 733 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 734 * to be reversed. 735 */ 736 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 737 *flags |= RTW_F_DIGPHY; 738 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 739 *flags |= RTW_F_DFLANTB; 740 741 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 742 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 743 744 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 745 switch (*rfchipid) { 746 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 747 rfname = "GCT GRF5101"; 748 paname = "Winspring WS9901"; 749 break; 750 case RTW_RFCHIPID_MAXIM: 751 rfname = "Maxim MAX2820"; /* guess */ 752 paname = "Maxim MAX2422"; /* guess */ 753 break; 754 case RTW_RFCHIPID_INTERSIL: 755 rfname = "Intersil HFA3873"; /* guess */ 756 paname = "Intersil <unknown>"; 757 break; 758 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 759 rfname = "Philips SA2400A"; 760 paname = "Philips SA2411"; 761 break; 762 case RTW_RFCHIPID_RFMD: 763 /* this is the same front-end as an atw(4)! */ 764 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 765 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 766 "SYN: Silicon Labs Si4126"; /* inferred from 767 * reference driver 768 */ 769 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 770 break; 771 case RTW_RFCHIPID_RESERVED: 772 rfname = paname = "reserved"; 773 break; 774 default: 775 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 776 rfname = paname = scratch; 777 } 778 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 779 780 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 781 case RTW_CONFIG0_GL_USA: 782 *locale = RTW_LOCALE_USA; 783 break; 784 case RTW_CONFIG0_GL_EUROPE: 785 *locale = RTW_LOCALE_EUROPE; 786 break; 787 case RTW_CONFIG0_GL_JAPAN: 788 *locale = RTW_LOCALE_JAPAN; 789 break; 790 default: 791 *locale = RTW_LOCALE_UNKNOWN; 792 break; 793 } 794 return 0; 795 } 796 797 /* Returns -1 on failure. */ 798 static int 799 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 800 const char *dvname) 801 { 802 int rc; 803 struct seeprom_descriptor sd; 804 uint8_t ecr; 805 806 (void)memset(&sd, 0, sizeof(sd)); 807 808 ecr = RTW_READ8(regs, RTW_9346CR); 809 810 if ((flags & RTW_F_9356SROM) != 0) { 811 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 812 sr->sr_size = 256; 813 sd.sd_chip = C56_66; 814 } else { 815 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 816 sr->sr_size = 128; 817 sd.sd_chip = C46; 818 } 819 820 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 821 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 822 ecr |= RTW_9346CR_EEM_PROGRAM; 823 824 RTW_WRITE8(regs, RTW_9346CR, ecr); 825 826 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 827 828 if (sr->sr_content == NULL) { 829 printf("%s: unable to allocate SROM buffer\n", dvname); 830 return ENOMEM; 831 } 832 833 (void)memset(sr->sr_content, 0, sr->sr_size); 834 835 /* RTL8180 has a single 8-bit register for controlling the 836 * 93cx6 SROM. There is no "ready" bit. The RTL8180 837 * input/output sense is the reverse of read_seeprom's. 838 */ 839 sd.sd_tag = regs->r_bt; 840 sd.sd_bsh = regs->r_bh; 841 sd.sd_regsize = 1; 842 sd.sd_control_offset = RTW_9346CR; 843 sd.sd_status_offset = RTW_9346CR; 844 sd.sd_dataout_offset = RTW_9346CR; 845 sd.sd_CK = RTW_9346CR_EESK; 846 sd.sd_CS = RTW_9346CR_EECS; 847 sd.sd_DI = RTW_9346CR_EEDO; 848 sd.sd_DO = RTW_9346CR_EEDI; 849 /* make read_seeprom enter EEPROM read/write mode */ 850 sd.sd_MS = ecr; 851 sd.sd_RDY = 0; 852 853 /* TBD bus barriers */ 854 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 855 printf("%s: could not read SROM\n", dvname); 856 free(sr->sr_content, M_DEVBUF); 857 sr->sr_content = NULL; 858 return -1; /* XXX */ 859 } 860 861 /* end EEPROM read/write mode */ 862 RTW_WRITE8(regs, RTW_9346CR, 863 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 864 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 865 866 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 867 return rc; 868 869 #ifdef RTW_DEBUG 870 { 871 int i; 872 RTW_DPRINTF(RTW_DEBUG_ATTACH, 873 ("\n%s: serial ROM:\n\t", dvname)); 874 for (i = 0; i < sr->sr_size/2; i++) { 875 if (((i % 8) == 0) && (i != 0)) 876 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 877 RTW_DPRINTF(RTW_DEBUG_ATTACH, 878 (" %04x", sr->sr_content[i])); 879 } 880 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 881 } 882 #endif /* RTW_DEBUG */ 883 return 0; 884 } 885 886 static void 887 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 888 const char *dvname) 889 { 890 uint8_t cfg4; 891 const char *method; 892 893 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 894 895 switch (rfchipid) { 896 default: 897 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 898 method = "fallback"; 899 break; 900 case RTW_RFCHIPID_INTERSIL: 901 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 902 method = "Intersil"; 903 break; 904 case RTW_RFCHIPID_PHILIPS: 905 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 906 method = "Philips"; 907 break; 908 case RTW_RFCHIPID_GCT: /* XXX a guess */ 909 case RTW_RFCHIPID_RFMD: 910 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 911 method = "RFMD"; 912 break; 913 } 914 915 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 916 917 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 918 919 RTW_DPRINTF(RTW_DEBUG_INIT, 920 ("%s: %s RF programming method, %#02x\n", dvname, method, 921 RTW_READ8(regs, RTW_CONFIG4))); 922 } 923 924 static __inline void 925 rtw_init_channels(enum rtw_locale locale, 926 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 927 const char *dvname) 928 { 929 int i; 930 const char *name = NULL; 931 #define ADD_CHANNEL(_chans, _chan) do { \ 932 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 933 (*_chans)[_chan].ic_freq = \ 934 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 935 } while (0) 936 937 switch (locale) { 938 case RTW_LOCALE_USA: /* 1-11 */ 939 name = "USA"; 940 for (i = 1; i <= 11; i++) 941 ADD_CHANNEL(chans, i); 942 break; 943 case RTW_LOCALE_JAPAN: /* 1-14 */ 944 name = "Japan"; 945 ADD_CHANNEL(chans, 14); 946 for (i = 1; i <= 14; i++) 947 ADD_CHANNEL(chans, i); 948 break; 949 case RTW_LOCALE_EUROPE: /* 1-13 */ 950 name = "Europe"; 951 for (i = 1; i <= 13; i++) 952 ADD_CHANNEL(chans, i); 953 break; 954 default: /* 10-11 allowed by most countries */ 955 name = "<unknown>"; 956 for (i = 10; i <= 11; i++) 957 ADD_CHANNEL(chans, i); 958 break; 959 } 960 printf("%s: Geographic Location %s\n", dvname, name); 961 #undef ADD_CHANNEL 962 } 963 964 static __inline void 965 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 966 const char *dvname) 967 { 968 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 969 970 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 971 case RTW_CONFIG0_GL_USA: 972 *locale = RTW_LOCALE_USA; 973 break; 974 case RTW_CONFIG0_GL_JAPAN: 975 *locale = RTW_LOCALE_JAPAN; 976 break; 977 case RTW_CONFIG0_GL_EUROPE: 978 *locale = RTW_LOCALE_EUROPE; 979 break; 980 default: 981 *locale = RTW_LOCALE_UNKNOWN; 982 break; 983 } 984 } 985 986 static __inline int 987 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 988 const char *dvname) 989 { 990 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 991 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 992 }; 993 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 994 idr1 = RTW_READ(regs, RTW_IDR1); 995 996 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 997 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 998 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 999 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 1000 1001 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 1002 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 1003 1004 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1005 printf("%s: could not get mac address, attach failed\n", 1006 dvname); 1007 return ENXIO; 1008 } 1009 1010 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 1011 1012 return 0; 1013 } 1014 1015 static uint8_t 1016 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1017 struct ieee80211_channel *chan) 1018 { 1019 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1020 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 1021 ("%s: channel %d out of range", __func__, 1022 idx - RTW_SR_TXPOWER1 + 1)); 1023 return RTW_SR_GET(sr, idx); 1024 } 1025 1026 static void 1027 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1028 { 1029 int pri; 1030 u_int ndesc[RTW_NTXPRI] = 1031 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 1032 1033 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1034 tdb[pri].tdb_nfree = ndesc[pri]; 1035 tdb[pri].tdb_next = 0; 1036 } 1037 } 1038 1039 static int 1040 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1041 { 1042 int i; 1043 struct rtw_txsoft *ts; 1044 1045 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1046 SIMPLEQ_INIT(&tsb->tsb_freeq); 1047 for (i = 0; i < tsb->tsb_ndesc; i++) { 1048 ts = &tsb->tsb_desc[i]; 1049 ts->ts_mbuf = NULL; 1050 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1051 } 1052 return 0; 1053 } 1054 1055 static void 1056 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1057 { 1058 int pri; 1059 for (pri = 0; pri < RTW_NTXPRI; pri++) 1060 rtw_txsoft_blk_init(&tsb[pri]); 1061 } 1062 1063 static __inline void 1064 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1065 { 1066 KASSERT(nsync <= rdb->rdb_ndesc); 1067 /* sync to end of ring */ 1068 if (desc0 + nsync > rdb->rdb_ndesc) { 1069 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1070 offsetof(struct rtw_descs, hd_rx[desc0]), 1071 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1072 nsync -= (rdb->rdb_ndesc - desc0); 1073 desc0 = 0; 1074 } 1075 1076 KASSERT(desc0 < rdb->rdb_ndesc); 1077 KASSERT(nsync <= rdb->rdb_ndesc); 1078 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1079 1080 /* sync what remains */ 1081 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1082 offsetof(struct rtw_descs, hd_rx[desc0]), 1083 sizeof(struct rtw_rxdesc) * nsync, ops); 1084 } 1085 1086 static void 1087 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1088 { 1089 /* sync to end of ring */ 1090 if (desc0 + nsync > tdb->tdb_ndesc) { 1091 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1092 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1093 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1094 ops); 1095 nsync -= (tdb->tdb_ndesc - desc0); 1096 desc0 = 0; 1097 } 1098 1099 /* sync what remains */ 1100 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1101 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1102 sizeof(struct rtw_txdesc) * nsync, ops); 1103 } 1104 1105 static void 1106 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1107 { 1108 int pri; 1109 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1110 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1111 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1112 } 1113 } 1114 1115 static void 1116 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1117 { 1118 int i; 1119 struct rtw_rxsoft *rs; 1120 1121 for (i = 0; i < RTW_RXQLEN; i++) { 1122 rs = &desc[i]; 1123 if (rs->rs_mbuf == NULL) 1124 continue; 1125 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1126 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1127 bus_dmamap_unload(dmat, rs->rs_dmamap); 1128 m_freem(rs->rs_mbuf); 1129 rs->rs_mbuf = NULL; 1130 } 1131 } 1132 1133 static __inline int 1134 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1135 { 1136 int rc; 1137 struct mbuf *m; 1138 1139 MGETHDR(m, M_DONTWAIT, MT_DATA); 1140 if (m == NULL) 1141 return ENOBUFS; 1142 1143 MCLGET(m, M_DONTWAIT); 1144 if ((m->m_flags & M_EXT) == 0) { 1145 m_freem(m); 1146 return ENOBUFS; 1147 } 1148 1149 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1150 1151 if (rs->rs_mbuf != NULL) 1152 bus_dmamap_unload(dmat, rs->rs_dmamap); 1153 1154 rs->rs_mbuf = NULL; 1155 1156 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1157 if (rc != 0) { 1158 m_freem(m); 1159 return -1; 1160 } 1161 1162 rs->rs_mbuf = m; 1163 1164 return 0; 1165 } 1166 1167 static int 1168 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1169 int *ndesc, const char *dvname) 1170 { 1171 int i, rc = 0; 1172 struct rtw_rxsoft *rs; 1173 1174 for (i = 0; i < RTW_RXQLEN; i++) { 1175 rs = &desc[i]; 1176 /* we're in rtw_init, so there should be no mbufs allocated */ 1177 KASSERT(rs->rs_mbuf == NULL); 1178 #ifdef RTW_DEBUG 1179 if (i == rtw_rxbufs_limit) { 1180 printf("%s: TEST hit %d-buffer limit\n", dvname, i); 1181 rc = ENOBUFS; 1182 break; 1183 } 1184 #endif /* RTW_DEBUG */ 1185 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1186 printf("%s: rtw_rxsoft_alloc failed, %d buffers, " 1187 "rc %d\n", dvname, i, rc); 1188 break; 1189 } 1190 } 1191 *ndesc = i; 1192 return rc; 1193 } 1194 1195 static __inline void 1196 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1197 int idx, int kick) 1198 { 1199 int is_last = (idx == rdb->rdb_ndesc - 1); 1200 uint32_t ctl, octl, obuf; 1201 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1202 1203 obuf = rd->rd_buf; 1204 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1205 1206 ctl = LSHIFT(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1207 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1208 1209 if (is_last) 1210 ctl |= RTW_RXCTL_EOR; 1211 1212 octl = rd->rd_ctl; 1213 rd->rd_ctl = htole32(ctl); 1214 1215 RTW_DPRINTF( 1216 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1217 : RTW_DEBUG_RECV_DESC, 1218 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1219 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1220 le32toh(rd->rd_ctl))); 1221 1222 /* sync the mbuf */ 1223 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1224 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1225 1226 /* sync the descriptor */ 1227 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1228 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1229 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1230 } 1231 1232 static void 1233 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1234 { 1235 int i; 1236 struct rtw_rxdesc *rd; 1237 struct rtw_rxsoft *rs; 1238 1239 for (i = 0; i < rdb->rdb_ndesc; i++) { 1240 rd = &rdb->rdb_desc[i]; 1241 rs = &ctl[i]; 1242 rtw_rxdesc_init(rdb, rs, i, kick); 1243 } 1244 rdb->rdb_next = 0; 1245 } 1246 1247 static void 1248 rtw_io_enable(struct rtw_regs *regs, uint8_t flags, int enable) 1249 { 1250 uint8_t cr; 1251 1252 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1253 enable ? "enable" : "disable", flags)); 1254 1255 cr = RTW_READ8(regs, RTW_CR); 1256 1257 /* XXX reference source does not enable MULRW */ 1258 #if 0 1259 /* enable PCI Read/Write Multiple */ 1260 cr |= RTW_CR_MULRW; 1261 #endif 1262 1263 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1264 if (enable) 1265 cr |= flags; 1266 else 1267 cr &= ~flags; 1268 RTW_WRITE8(regs, RTW_CR, cr); 1269 RTW_SYNC(regs, RTW_CR, RTW_CR); 1270 } 1271 1272 static void 1273 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1274 { 1275 #define IS_BEACON(__fc0) \ 1276 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1277 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1278 1279 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1280 * hardware -> net80211 1281 */ 1282 u_int next, nproc = 0; 1283 int hwrate, len, rate, rssi, sq; 1284 uint32_t hrssi, hstat, htsfth, htsftl; 1285 struct rtw_rxdesc *rd; 1286 struct rtw_rxsoft *rs; 1287 struct rtw_rxdesc_blk *rdb; 1288 struct mbuf *m; 1289 1290 struct ieee80211_node *ni; 1291 struct ieee80211_frame *wh; 1292 1293 rdb = &sc->sc_rxdesc_blk; 1294 1295 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1296 1297 for (next = rdb->rdb_next; ; next = (next + 1) % rdb->rdb_ndesc) { 1298 rtw_rxdescs_sync(rdb, next, 1, 1299 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1300 rd = &rdb->rdb_desc[next]; 1301 rs = &sc->sc_rxsoft[next]; 1302 1303 hstat = le32toh(rd->rd_stat); 1304 hrssi = le32toh(rd->rd_rssi); 1305 htsfth = le32toh(rd->rd_tsfth); 1306 htsftl = le32toh(rd->rd_tsftl); 1307 1308 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1309 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1310 __func__, next, hstat, hrssi, htsfth, htsftl)); 1311 1312 ++nproc; 1313 1314 /* still belongs to NIC */ 1315 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1316 if (nproc > 1) 1317 break; 1318 1319 /* sometimes the NIC skips to the 0th descriptor */ 1320 rtw_rxdescs_sync(rdb, 0, 1, 1321 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1322 rd = &rdb->rdb_desc[0]; 1323 if ((rd->rd_stat & htole32(RTW_RXSTAT_OWN)) != 0) 1324 break; 1325 RTW_DPRINTF(RTW_DEBUG_BUGS, 1326 ("%s: NIC skipped to rxdesc[0]\n", 1327 sc->sc_dev.dv_xname)); 1328 next = 0; 1329 continue; 1330 } 1331 1332 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1333 printf("%s: DMA error/FIFO overflow %08x, " 1334 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1335 hstat & RTW_RXSTAT_IOERROR, next); 1336 sc->sc_if.if_ierrors++; 1337 goto next; 1338 } 1339 1340 len = MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1341 if (len < IEEE80211_MIN_LEN) { 1342 sc->sc_ic.ic_stats.is_rx_tooshort++; 1343 goto next; 1344 } 1345 1346 hwrate = MASK_AND_RSHIFT(hstat, RTW_RXSTAT_RATE_MASK); 1347 if (hwrate >= sizeof(ratetbl) / sizeof(ratetbl[0])) { 1348 printf("%s: unknown rate #%d\n", sc->sc_dev.dv_xname, 1349 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_RATE_MASK)); 1350 sc->sc_if.if_ierrors++; 1351 goto next; 1352 } 1353 rate = ratetbl[hwrate]; 1354 1355 #ifdef RTW_DEBUG 1356 #define PRINTSTAT(flag) do { \ 1357 if ((hstat & flag) != 0) { \ 1358 printf("%s" #flag, delim); \ 1359 delim = ","; \ 1360 } \ 1361 } while (0) 1362 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1363 const char *delim = "<"; 1364 printf("%s: ", sc->sc_dev.dv_xname); 1365 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1366 printf("status %08x", hstat); 1367 PRINTSTAT(RTW_RXSTAT_SPLCP); 1368 PRINTSTAT(RTW_RXSTAT_MAR); 1369 PRINTSTAT(RTW_RXSTAT_PAR); 1370 PRINTSTAT(RTW_RXSTAT_BAR); 1371 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1372 PRINTSTAT(RTW_RXSTAT_CRC32); 1373 PRINTSTAT(RTW_RXSTAT_ICV); 1374 printf(">, "); 1375 } 1376 printf("rate %d.%d Mb/s, time %08x%08x\n", 1377 (rate * 5) / 10, (rate * 5) % 10, htsfth, htsftl); 1378 } 1379 #endif /* RTW_DEBUG */ 1380 1381 if ((hstat & RTW_RXSTAT_RES) != 0 && 1382 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1383 goto next; 1384 1385 /* if bad flags, skip descriptor */ 1386 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1387 printf("%s: too many rx segments\n", 1388 sc->sc_dev.dv_xname); 1389 goto next; 1390 } 1391 1392 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1393 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1394 1395 m = rs->rs_mbuf; 1396 1397 /* if temporarily out of memory, re-use mbuf */ 1398 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1399 case 0: 1400 break; 1401 case ENOBUFS: 1402 printf("%s: rtw_rxsoft_alloc(, %d) failed, " 1403 "dropping packet\n", sc->sc_dev.dv_xname, next); 1404 goto next; 1405 default: 1406 /* XXX shorten rx ring, instead? */ 1407 panic("%s: could not load DMA map\n", 1408 sc->sc_dev.dv_xname); 1409 } 1410 1411 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1412 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1413 else { 1414 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1415 /* TBD find out each front-end's LNA gain in the 1416 * front-end's units 1417 */ 1418 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1419 rssi |= 0x80; 1420 } 1421 sq = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_SQ); 1422 1423 /* Note well: now we cannot recycle the rs_mbuf unless 1424 * we restore its original length. 1425 */ 1426 m->m_pkthdr.rcvif = &sc->sc_if; 1427 m->m_pkthdr.len = m->m_len = len; 1428 m->m_flags |= M_HASFCS; 1429 1430 wh = mtod(m, struct ieee80211_frame *); 1431 1432 if (!IS_BEACON(wh->i_fc[0])) 1433 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1434 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1435 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1436 1437 sc->sc_tsfth = htsfth; 1438 1439 #ifdef RTW_DEBUG 1440 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 1441 (IFF_DEBUG|IFF_LINK2)) { 1442 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1443 rate, rssi); 1444 } 1445 #endif /* RTW_DEBUG */ 1446 1447 #if NBPFILTER > 0 1448 if (sc->sc_radiobpf != NULL) { 1449 struct ieee80211com *ic = &sc->sc_ic; 1450 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1451 1452 rr->rr_tsft = 1453 htole64(((uint64_t)htsfth << 32) | htsftl); 1454 1455 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1456 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE; 1457 1458 rr->rr_flags = 0; 1459 rr->rr_rate = rate; 1460 rr->rr_chan_freq = 1461 htole16(ic->ic_bss->ni_chan->ic_freq); 1462 rr->rr_chan_flags = 1463 htole16(ic->ic_bss->ni_chan->ic_flags); 1464 rr->rr_antsignal = rssi; 1465 rr->rr_barker_lock = htole16(sq); 1466 1467 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rr, 1468 sizeof(sc->sc_rxtapu), m); 1469 } 1470 #endif /* NPBFILTER > 0 */ 1471 1472 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1473 ieee80211_release_node(&sc->sc_ic, ni); 1474 next: 1475 rtw_rxdesc_init(rdb, rs, next, 0); 1476 } 1477 rdb->rdb_next = next; 1478 1479 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1480 1481 return; 1482 #undef IS_BEACON 1483 } 1484 1485 static void 1486 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1487 struct rtw_txsoft *ts) 1488 { 1489 struct mbuf *m; 1490 struct ieee80211_node *ni; 1491 1492 m = ts->ts_mbuf; 1493 ni = ts->ts_ni; 1494 KASSERT(m != NULL); 1495 KASSERT(ni != NULL); 1496 ts->ts_mbuf = NULL; 1497 ts->ts_ni = NULL; 1498 1499 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1500 BUS_DMASYNC_POSTWRITE); 1501 bus_dmamap_unload(dmat, ts->ts_dmamap); 1502 m_freem(m); 1503 ieee80211_release_node(ic, ni); 1504 } 1505 1506 static void 1507 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1508 struct rtw_txsoft_blk *tsb) 1509 { 1510 struct rtw_txsoft *ts; 1511 1512 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1513 rtw_txsoft_release(dmat, ic, ts); 1514 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1515 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1516 } 1517 } 1518 1519 static __inline void 1520 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1521 struct rtw_txsoft *ts, int ndesc) 1522 { 1523 uint32_t hstat; 1524 int data_retry, rts_retry; 1525 struct rtw_txdesc *tdn; 1526 const char *condstring; 1527 1528 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1529 1530 tdb->tdb_nfree += ndesc; 1531 1532 tdn = &tdb->tdb_desc[ts->ts_last]; 1533 1534 hstat = le32toh(tdn->td_stat); 1535 rts_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1536 data_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_DRC_MASK); 1537 1538 sc->sc_if.if_collisions += rts_retry + data_retry; 1539 1540 if ((hstat & RTW_TXSTAT_TOK) != 0) 1541 condstring = "ok"; 1542 else { 1543 sc->sc_if.if_oerrors++; 1544 condstring = "error"; 1545 } 1546 1547 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1548 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1549 sc->sc_dev.dv_xname, ts, ts->ts_first, ts->ts_last, 1550 condstring, rts_retry, data_retry)); 1551 } 1552 1553 /* Collect transmitted packets. */ 1554 static __inline void 1555 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1556 struct rtw_txdesc_blk *tdb) 1557 { 1558 int ndesc; 1559 struct rtw_txsoft *ts; 1560 1561 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1562 ndesc = 1 + ts->ts_last - ts->ts_first; 1563 if (ts->ts_last < ts->ts_first) 1564 ndesc += tdb->tdb_ndesc; 1565 1566 KASSERT(ndesc > 0); 1567 1568 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1569 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1570 1571 if ((tdb->tdb_desc[ts->ts_last].td_stat & 1572 htole32(RTW_TXSTAT_OWN)) != 0) 1573 break; 1574 1575 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1576 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1577 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1578 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1579 } 1580 if (ts == NULL) 1581 tsb->tsb_tx_timer = 0; 1582 } 1583 1584 static void 1585 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1586 { 1587 int pri; 1588 struct rtw_txsoft_blk *tsb; 1589 struct rtw_txdesc_blk *tdb; 1590 1591 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1592 tsb = &sc->sc_txsoft_blk[pri]; 1593 tdb = &sc->sc_txdesc_blk[pri]; 1594 1595 rtw_collect_txring(sc, tsb, tdb); 1596 1597 if ((isr & RTW_INTR_TX) != 0) 1598 rtw_start(&sc->sc_if); 1599 } 1600 1601 /* TBD */ 1602 return; 1603 } 1604 1605 static void 1606 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1607 { 1608 /* TBD */ 1609 return; 1610 } 1611 1612 static void 1613 rtw_intr_atim(struct rtw_softc *sc) 1614 { 1615 /* TBD */ 1616 return; 1617 } 1618 1619 #ifdef RTW_DEBUG 1620 static void 1621 rtw_dump_rings(struct rtw_softc *sc) 1622 { 1623 struct rtw_txdesc_blk *tdb; 1624 struct rtw_rxdesc *rd; 1625 struct rtw_rxdesc_blk *rdb; 1626 int desc, pri; 1627 1628 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1629 return; 1630 1631 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1632 tdb = &sc->sc_txdesc_blk[pri]; 1633 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1634 tdb->tdb_ndesc, tdb->tdb_nfree); 1635 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1636 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1637 } 1638 1639 rdb = &sc->sc_rxdesc_blk; 1640 1641 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1642 rd = &rdb->rdb_desc[desc]; 1643 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1644 "rsvd1/tsfth %08x\n", __func__, 1645 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1646 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1647 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1648 } 1649 } 1650 #endif /* RTW_DEBUG */ 1651 1652 static void 1653 rtw_hwring_setup(struct rtw_softc *sc) 1654 { 1655 struct rtw_regs *regs = &sc->sc_regs; 1656 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1657 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1658 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1659 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1660 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1661 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1662 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1663 ("%s: reg[TLPDA] <- %" PRIxPTR "\n", __func__, 1664 (uintptr_t)RTW_RING_BASE(sc, hd_txlo))); 1665 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1666 ("%s: reg[TNPDA] <- %" PRIxPTR "\n", __func__, 1667 (uintptr_t)RTW_RING_BASE(sc, hd_txmd))); 1668 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1669 ("%s: reg[THPDA] <- %" PRIxPTR "\n", __func__, 1670 (uintptr_t)RTW_RING_BASE(sc, hd_txhi))); 1671 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1672 ("%s: reg[TBDA] <- %" PRIxPTR "\n", __func__, 1673 (uintptr_t)RTW_RING_BASE(sc, hd_bcn))); 1674 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1675 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1676 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1677 } 1678 1679 static int 1680 rtw_swring_setup(struct rtw_softc *sc) 1681 { 1682 int rc; 1683 struct rtw_rxdesc_blk *rdb; 1684 1685 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1686 1687 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1688 1689 rdb = &sc->sc_rxdesc_blk; 1690 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1691 sc->sc_dev.dv_xname)) != 0 && rdb->rdb_ndesc == 0) { 1692 printf("%s: could not allocate rx buffers\n", 1693 sc->sc_dev.dv_xname); 1694 return rc; 1695 } 1696 1697 rdb = &sc->sc_rxdesc_blk; 1698 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1699 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1700 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1701 1702 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1703 return 0; 1704 } 1705 1706 static void 1707 rtw_txdesc_blk_reset(struct rtw_txdesc_blk *tdb) 1708 { 1709 int i; 1710 1711 (void)memset(tdb->tdb_desc, 0, 1712 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 1713 for (i = 0; i < tdb->tdb_ndesc; i++) 1714 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 1715 tdb->tdb_nfree = tdb->tdb_ndesc; 1716 tdb->tdb_next = 0; 1717 } 1718 1719 static void 1720 rtw_txdescs_reset(struct rtw_softc *sc) 1721 { 1722 int pri; 1723 struct rtw_txdesc_blk *tdb; 1724 1725 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1726 tdb = &sc->sc_txdesc_blk[pri]; 1727 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 1728 &sc->sc_txsoft_blk[pri]); 1729 rtw_txdesc_blk_reset(tdb); 1730 rtw_txdescs_sync(tdb, 0, tdb->tdb_ndesc, 1731 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1732 } 1733 } 1734 1735 static void 1736 rtw_rxdescs_reset(struct rtw_softc *sc) 1737 { 1738 rtw_rxdesc_init_all(&sc->sc_rxdesc_blk, &sc->sc_rxsoft[0], 1); 1739 } 1740 1741 static void 1742 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 1743 { 1744 struct rtw_regs *regs = &sc->sc_regs; 1745 1746 if ((isr & RTW_INTR_TXFOVW) != 0) 1747 printf("%s: tx fifo overflow\n", sc->sc_dev.dv_xname); 1748 1749 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) == 0) 1750 return; 1751 1752 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: restarting xmit/recv\n", 1753 sc->sc_dev.dv_xname)); 1754 1755 #ifdef RTW_DEBUG 1756 rtw_dump_rings(sc); 1757 #endif /* RTW_DEBUG */ 1758 1759 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1760 1761 /* Collect rx'd packets. Refresh rx buffers. */ 1762 rtw_intr_rx(sc, 0); 1763 /* Collect tx'd packets. */ 1764 rtw_intr_tx(sc, 0); 1765 1766 RTW_WRITE16(regs, RTW_IMR, 0); 1767 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1768 1769 rtw_chip_reset1(regs, sc->sc_dev.dv_xname); 1770 1771 rtw_rxdescs_reset(sc); 1772 rtw_txdescs_reset(sc); 1773 1774 rtw_hwring_setup(sc); 1775 1776 #ifdef RTW_DEBUG 1777 rtw_dump_rings(sc); 1778 #endif /* RTW_DEBUG */ 1779 1780 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1781 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1782 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1783 } 1784 1785 static __inline void 1786 rtw_suspend_ticks(struct rtw_softc *sc) 1787 { 1788 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1789 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 1790 sc->sc_do_tick = 0; 1791 } 1792 1793 static __inline void 1794 rtw_resume_ticks(struct rtw_softc *sc) 1795 { 1796 uint32_t tsftrl0, tsftrl1, next_tick; 1797 1798 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1799 1800 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1801 next_tick = tsftrl1 + 1000000; 1802 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1803 1804 sc->sc_do_tick = 1; 1805 1806 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1807 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1808 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 1809 } 1810 1811 static void 1812 rtw_intr_timeout(struct rtw_softc *sc) 1813 { 1814 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 1815 if (sc->sc_do_tick) 1816 rtw_resume_ticks(sc); 1817 return; 1818 } 1819 1820 int 1821 rtw_intr(void *arg) 1822 { 1823 int i; 1824 struct rtw_softc *sc = arg; 1825 struct rtw_regs *regs = &sc->sc_regs; 1826 uint16_t isr; 1827 1828 /* 1829 * If the interface isn't running, the interrupt couldn't 1830 * possibly have come from us. 1831 */ 1832 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1833 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1834 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1835 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1836 return (0); 1837 } 1838 1839 for (i = 0; i < 10; i++) { 1840 isr = RTW_READ16(regs, RTW_ISR); 1841 1842 RTW_WRITE16(regs, RTW_ISR, isr); 1843 RTW_WBR(regs, RTW_ISR, RTW_ISR); 1844 1845 if (sc->sc_intr_ack != NULL) 1846 (*sc->sc_intr_ack)(regs); 1847 1848 if (isr == 0) 1849 break; 1850 1851 #ifdef RTW_DEBUG 1852 #define PRINTINTR(flag) do { \ 1853 if ((isr & flag) != 0) { \ 1854 printf("%s" #flag, delim); \ 1855 delim = ","; \ 1856 } \ 1857 } while (0) 1858 1859 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 1860 const char *delim = "<"; 1861 1862 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1863 1864 PRINTINTR(RTW_INTR_TXFOVW); 1865 PRINTINTR(RTW_INTR_TIMEOUT); 1866 PRINTINTR(RTW_INTR_BCNINT); 1867 PRINTINTR(RTW_INTR_ATIMINT); 1868 PRINTINTR(RTW_INTR_TBDER); 1869 PRINTINTR(RTW_INTR_TBDOK); 1870 PRINTINTR(RTW_INTR_THPDER); 1871 PRINTINTR(RTW_INTR_THPDOK); 1872 PRINTINTR(RTW_INTR_TNPDER); 1873 PRINTINTR(RTW_INTR_TNPDOK); 1874 PRINTINTR(RTW_INTR_RXFOVW); 1875 PRINTINTR(RTW_INTR_RDU); 1876 PRINTINTR(RTW_INTR_TLPDER); 1877 PRINTINTR(RTW_INTR_TLPDOK); 1878 PRINTINTR(RTW_INTR_RER); 1879 PRINTINTR(RTW_INTR_ROK); 1880 1881 printf(">\n"); 1882 } 1883 #undef PRINTINTR 1884 #endif /* RTW_DEBUG */ 1885 1886 if ((isr & RTW_INTR_RX) != 0) 1887 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1888 if ((isr & RTW_INTR_TX) != 0) 1889 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1890 if ((isr & RTW_INTR_BEACON) != 0) 1891 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1892 if ((isr & RTW_INTR_ATIMINT) != 0) 1893 rtw_intr_atim(sc); 1894 if ((isr & RTW_INTR_IOERROR) != 0) 1895 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1896 if ((isr & RTW_INTR_TIMEOUT) != 0) 1897 rtw_intr_timeout(sc); 1898 } 1899 1900 return 1; 1901 } 1902 1903 /* Must be called at splnet. */ 1904 static void 1905 rtw_stop(struct ifnet *ifp, int disable) 1906 { 1907 int pri; 1908 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1909 struct ieee80211com *ic = &sc->sc_ic; 1910 struct rtw_regs *regs = &sc->sc_regs; 1911 1912 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1913 return; 1914 1915 rtw_suspend_ticks(sc); 1916 1917 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1918 1919 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1920 /* Disable interrupts. */ 1921 RTW_WRITE16(regs, RTW_IMR, 0); 1922 1923 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 1924 1925 /* Stop the transmit and receive processes. First stop DMA, 1926 * then disable receiver and transmitter. 1927 */ 1928 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 1929 1930 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 1931 1932 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1933 } 1934 1935 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1936 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 1937 &sc->sc_txsoft_blk[pri]); 1938 } 1939 1940 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 1941 1942 if (disable) 1943 rtw_disable(sc); 1944 1945 /* Mark the interface as not running. Cancel the watchdog timer. */ 1946 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1947 ifp->if_timer = 0; 1948 1949 return; 1950 } 1951 1952 const char * 1953 rtw_pwrstate_string(enum rtw_pwrstate power) 1954 { 1955 switch (power) { 1956 case RTW_ON: 1957 return "on"; 1958 case RTW_SLEEP: 1959 return "sleep"; 1960 case RTW_OFF: 1961 return "off"; 1962 default: 1963 return "unknown"; 1964 } 1965 } 1966 1967 /* XXX For Maxim, I am using the RFMD settings gleaned from the 1968 * reference driver, plus a magic Maxim "ON" value that comes from 1969 * the Realtek document "Windows PG for Rtl8180." 1970 */ 1971 static void 1972 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1973 int before_rf, int digphy) 1974 { 1975 uint32_t anaparm; 1976 1977 anaparm = RTW_READ(regs, RTW_ANAPARM); 1978 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1979 1980 switch (power) { 1981 case RTW_OFF: 1982 if (before_rf) 1983 return; 1984 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 1985 anaparm |= RTW_ANAPARM_TXDACOFF; 1986 break; 1987 case RTW_SLEEP: 1988 if (!before_rf) 1989 return; 1990 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 1991 anaparm |= RTW_ANAPARM_TXDACOFF; 1992 break; 1993 case RTW_ON: 1994 if (!before_rf) 1995 return; 1996 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 1997 break; 1998 } 1999 RTW_DPRINTF(RTW_DEBUG_PWR, 2000 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2001 __func__, rtw_pwrstate_string(power), 2002 (before_rf) ? "before" : "after", anaparm)); 2003 2004 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2005 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2006 } 2007 2008 /* XXX I am using the RFMD settings gleaned from the reference 2009 * driver. They agree 2010 */ 2011 static void 2012 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2013 int before_rf, int digphy) 2014 { 2015 uint32_t anaparm; 2016 2017 anaparm = RTW_READ(regs, RTW_ANAPARM); 2018 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2019 2020 switch (power) { 2021 case RTW_OFF: 2022 if (before_rf) 2023 return; 2024 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2025 anaparm |= RTW_ANAPARM_TXDACOFF; 2026 break; 2027 case RTW_SLEEP: 2028 if (!before_rf) 2029 return; 2030 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2031 anaparm |= RTW_ANAPARM_TXDACOFF; 2032 break; 2033 case RTW_ON: 2034 if (!before_rf) 2035 return; 2036 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2037 break; 2038 } 2039 RTW_DPRINTF(RTW_DEBUG_PWR, 2040 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2041 __func__, rtw_pwrstate_string(power), 2042 (before_rf) ? "before" : "after", anaparm)); 2043 2044 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2045 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2046 } 2047 2048 static void 2049 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2050 int before_rf, int digphy) 2051 { 2052 uint32_t anaparm; 2053 2054 anaparm = RTW_READ(regs, RTW_ANAPARM); 2055 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2056 2057 switch (power) { 2058 case RTW_OFF: 2059 if (before_rf) 2060 return; 2061 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2062 anaparm |= RTW_ANAPARM_TXDACOFF; 2063 break; 2064 case RTW_SLEEP: 2065 if (!before_rf) 2066 return; 2067 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2068 anaparm |= RTW_ANAPARM_TXDACOFF; 2069 break; 2070 case RTW_ON: 2071 if (!before_rf) 2072 return; 2073 if (digphy) { 2074 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2075 /* XXX guess */ 2076 anaparm |= RTW_ANAPARM_TXDACOFF; 2077 } else 2078 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2079 break; 2080 } 2081 RTW_DPRINTF(RTW_DEBUG_PWR, 2082 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2083 __func__, rtw_pwrstate_string(power), 2084 (before_rf) ? "before" : "after", anaparm)); 2085 2086 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2087 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2088 } 2089 2090 static void 2091 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2092 int digphy) 2093 { 2094 struct rtw_regs *regs = &sc->sc_regs; 2095 2096 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2097 2098 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2099 2100 rtw_set_access(regs, RTW_ACCESS_NONE); 2101 2102 return; 2103 } 2104 2105 static int 2106 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2107 { 2108 int rc; 2109 2110 RTW_DPRINTF(RTW_DEBUG_PWR, 2111 ("%s: %s->%s\n", __func__, 2112 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2113 2114 if (sc->sc_pwrstate == power) 2115 return 0; 2116 2117 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2118 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2119 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2120 2121 switch (power) { 2122 case RTW_ON: 2123 /* TBD set LEDs */ 2124 break; 2125 case RTW_SLEEP: 2126 /* TBD */ 2127 break; 2128 case RTW_OFF: 2129 /* TBD */ 2130 break; 2131 } 2132 if (rc == 0) 2133 sc->sc_pwrstate = power; 2134 else 2135 sc->sc_pwrstate = RTW_OFF; 2136 return rc; 2137 } 2138 2139 static int 2140 rtw_tune(struct rtw_softc *sc) 2141 { 2142 struct ieee80211com *ic = &sc->sc_ic; 2143 u_int chan; 2144 int rc; 2145 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2146 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2147 2148 KASSERT(ic->ic_bss->ni_chan != NULL); 2149 2150 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2151 if (chan == IEEE80211_CHAN_ANY) 2152 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 2153 2154 if (chan == sc->sc_cur_chan) { 2155 RTW_DPRINTF(RTW_DEBUG_TUNE, 2156 ("%s: already tuned chan #%d\n", __func__, chan)); 2157 return 0; 2158 } 2159 2160 rtw_suspend_ticks(sc); 2161 2162 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 2163 2164 /* TBD wait for Tx to complete */ 2165 2166 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2167 2168 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2169 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 2170 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 2171 dflantb, RTW_ON)) != 0) { 2172 /* XXX condition on powersaving */ 2173 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2174 } 2175 2176 sc->sc_cur_chan = chan; 2177 2178 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 2179 2180 rtw_resume_ticks(sc); 2181 2182 return rc; 2183 } 2184 2185 void 2186 rtw_disable(struct rtw_softc *sc) 2187 { 2188 int rc; 2189 2190 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2191 return; 2192 2193 /* turn off PHY */ 2194 if ((sc->sc_flags & RTW_F_INVALID) == 0 && 2195 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2196 printf("%s: failed to turn off PHY (%d)\n", 2197 sc->sc_dev.dv_xname, rc); 2198 } 2199 2200 if (sc->sc_disable != NULL) 2201 (*sc->sc_disable)(sc); 2202 2203 sc->sc_flags &= ~RTW_F_ENABLED; 2204 } 2205 2206 int 2207 rtw_enable(struct rtw_softc *sc) 2208 { 2209 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2210 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2211 printf("%s: device enable failed\n", 2212 sc->sc_dev.dv_xname); 2213 return (EIO); 2214 } 2215 sc->sc_flags |= RTW_F_ENABLED; 2216 } 2217 return (0); 2218 } 2219 2220 static void 2221 rtw_transmit_config(struct rtw_regs *regs) 2222 { 2223 uint32_t tcr; 2224 2225 tcr = RTW_READ(regs, RTW_TCR); 2226 2227 tcr |= RTW_TCR_CWMIN; 2228 tcr &= ~RTW_TCR_MXDMA_MASK; 2229 tcr |= RTW_TCR_MXDMA_256; 2230 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2231 tcr &= ~RTW_TCR_LBK_MASK; 2232 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2233 2234 /* set short/long retry limits */ 2235 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2236 tcr |= LSHIFT(4, RTW_TCR_SRL_MASK) | LSHIFT(4, RTW_TCR_LRL_MASK); 2237 2238 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2239 2240 RTW_WRITE(regs, RTW_TCR, tcr); 2241 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2242 } 2243 2244 static __inline void 2245 rtw_enable_interrupts(struct rtw_softc *sc) 2246 { 2247 struct rtw_regs *regs = &sc->sc_regs; 2248 2249 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2250 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2251 2252 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2253 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2254 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2255 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2256 2257 /* XXX necessary? */ 2258 if (sc->sc_intr_ack != NULL) 2259 (*sc->sc_intr_ack)(regs); 2260 } 2261 2262 static void 2263 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2264 { 2265 uint8_t msr; 2266 2267 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2268 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2269 2270 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2271 2272 switch (opmode) { 2273 case IEEE80211_M_AHDEMO: 2274 case IEEE80211_M_IBSS: 2275 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2276 break; 2277 case IEEE80211_M_HOSTAP: 2278 msr |= RTW_MSR_NETYPE_AP_OK; 2279 break; 2280 case IEEE80211_M_MONITOR: 2281 /* XXX */ 2282 msr |= RTW_MSR_NETYPE_NOLINK; 2283 break; 2284 case IEEE80211_M_STA: 2285 msr |= RTW_MSR_NETYPE_INFRA_OK; 2286 break; 2287 } 2288 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2289 2290 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2291 } 2292 2293 #define rtw_calchash(addr) \ 2294 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2295 2296 static void 2297 rtw_pktfilt_load(struct rtw_softc *sc) 2298 { 2299 struct rtw_regs *regs = &sc->sc_regs; 2300 struct ieee80211com *ic = &sc->sc_ic; 2301 struct ethercom *ec = &ic->ic_ec; 2302 struct ifnet *ifp = &sc->sc_ic.ic_if; 2303 int hash; 2304 uint32_t hashes[2] = { 0, 0 }; 2305 struct ether_multi *enm; 2306 struct ether_multistep step; 2307 2308 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2309 2310 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2311 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2312 2313 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2314 /* MAC auto-reset PHY (huh?) */ 2315 sc->sc_rcr |= RTW_RCR_ENMARP; 2316 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2317 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2318 2319 switch (ic->ic_opmode) { 2320 case IEEE80211_M_MONITOR: 2321 sc->sc_rcr |= RTW_RCR_MONITOR; 2322 break; 2323 case IEEE80211_M_AHDEMO: 2324 case IEEE80211_M_IBSS: 2325 /* receive broadcasts in our BSS */ 2326 sc->sc_rcr |= RTW_RCR_ADD3; 2327 break; 2328 default: 2329 break; 2330 } 2331 2332 ifp->if_flags &= ~IFF_ALLMULTI; 2333 2334 /* XXX accept all broadcast if scanning */ 2335 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2336 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2337 2338 if (ifp->if_flags & IFF_PROMISC) { 2339 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2340 allmulti: 2341 ifp->if_flags |= IFF_ALLMULTI; 2342 goto setit; 2343 } 2344 2345 /* 2346 * Program the 64-bit multicast hash filter. 2347 */ 2348 ETHER_FIRST_MULTI(step, ec, enm); 2349 while (enm != NULL) { 2350 /* XXX */ 2351 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2352 ETHER_ADDR_LEN) != 0) 2353 goto allmulti; 2354 2355 hash = rtw_calchash(enm->enm_addrlo); 2356 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2357 sc->sc_rcr |= RTW_RCR_AM; 2358 ETHER_NEXT_MULTI(step, enm); 2359 } 2360 2361 /* all bits set => hash is useless */ 2362 if (~(hashes[0] & hashes[1]) == 0) 2363 goto allmulti; 2364 2365 setit: 2366 if (ifp->if_flags & IFF_ALLMULTI) { 2367 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2368 hashes[0] = hashes[1] = 0xffffffff; 2369 } 2370 2371 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2372 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2373 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2374 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2375 2376 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2377 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2378 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2379 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2380 2381 return; 2382 } 2383 2384 #define IEEE80211_BEACON_TIMESTAMP_LEN 8 2385 #define IEEE80211_BEACON_BINTVL_LEN 2 2386 #define IEEE80211_BEACON_CAPINFO_LEN 2 2387 #define IEEE80211_TLV_SSID_LEN(__esslen) (2 + (__esslen)) 2388 #define IEEE80211_TLV_SUPRATES_LEN(__nrates) (2 + (__nrates)) 2389 #define IEEE80211_TLV_XSUPRATES_LEN(__nrates) (2 + (__nrates)) 2390 #define IEEE80211_TLV_DSPARMS_LEN 3 2391 #define IEEE80211_TLV_IBSSPARMS 4 2392 #define IEEE80211_TLV_MIN_TIM 6 2393 2394 #define IEEE80211_TLV_ALLRATES_LEN(__nrates) \ 2395 (((__nrates) > IEEE80211_RATE_SIZE) ? 4 + (__nrates) : 2 + (__nrates)) 2396 2397 /* TBD factor with ieee80211_getmbuf */ 2398 static struct mbuf * 2399 rtw_getmbuf(int flags, int type, u_int pktlen) 2400 { 2401 struct mbuf *m; 2402 2403 KASSERT2(pktlen <= MCLBYTES, ("802.11 packet too large: %u", pktlen)); 2404 MGETHDR(m, flags, type); 2405 if (m == NULL || pktlen <= MHLEN) 2406 return m; 2407 MCLGET(m, flags); 2408 if ((m->m_flags & M_EXT) != 0) 2409 return m; 2410 m_free(m); 2411 return NULL; 2412 } 2413 2414 /* TBD factor with ath_beacon_alloc */ 2415 static struct mbuf * 2416 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2417 { 2418 struct ieee80211com *ic = &sc->sc_ic; 2419 struct ifnet *ifp = &ic->ic_if; 2420 struct ieee80211_frame *wh; 2421 struct mbuf *m; 2422 int pktlen; 2423 uint8_t *frm; 2424 uint16_t capinfo; 2425 struct ieee80211_rateset *rs; 2426 2427 /* 2428 * NB: the beacon data buffer must be 32-bit aligned; 2429 * we assume the mbuf routines will return us something 2430 * with this alignment (perhaps should assert). 2431 */ 2432 rs = &ni->ni_rates; 2433 pktlen = sizeof(struct ieee80211_frame) 2434 + IEEE80211_BEACON_TIMESTAMP_LEN 2435 + IEEE80211_BEACON_BINTVL_LEN 2436 + IEEE80211_BEACON_CAPINFO_LEN 2437 + IEEE80211_TLV_SSID_LEN(ni->ni_esslen) 2438 + IEEE80211_TLV_ALLRATES_LEN(rs->rs_nrates) 2439 + IEEE80211_TLV_DSPARMS_LEN 2440 + MAX(IEEE80211_TLV_IBSSPARMS, IEEE80211_TLV_MIN_TIM); 2441 2442 m = rtw_getmbuf(M_DONTWAIT, MT_DATA, pktlen); 2443 if (m == NULL) { 2444 RTW_DPRINTF(RTW_DEBUG_BEACON, 2445 ("%s: cannot get mbuf/cluster; size %u\n", 2446 __func__, pktlen)); 2447 #if 0 2448 sc->sc_stats.ast_be_nombuf++; 2449 #endif 2450 return NULL; 2451 } 2452 2453 wh = mtod(m, struct ieee80211_frame *); 2454 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 2455 IEEE80211_FC0_SUBTYPE_BEACON; 2456 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 2457 *(u_int16_t *)wh->i_dur = 0; 2458 memcpy(wh->i_addr1, ifp->if_broadcastaddr, IEEE80211_ADDR_LEN); 2459 memcpy(wh->i_addr2, ic->ic_myaddr, IEEE80211_ADDR_LEN); 2460 memcpy(wh->i_addr3, ni->ni_bssid, IEEE80211_ADDR_LEN); 2461 *(u_int16_t *)wh->i_seq = 0; 2462 2463 /* 2464 * beacon frame format 2465 * [8] time stamp 2466 * [2] beacon interval 2467 * [2] cabability information 2468 * [tlv] ssid 2469 * [tlv] supported rates 2470 * [tlv] parameter set (IBSS) 2471 * [tlv] extended supported rates 2472 */ 2473 frm = (u_int8_t *)&wh[1]; 2474 /* timestamp is set by hardware */ 2475 memset(frm, 0, IEEE80211_BEACON_TIMESTAMP_LEN); 2476 frm += IEEE80211_BEACON_TIMESTAMP_LEN; 2477 *(u_int16_t *)frm = htole16(ni->ni_intval); 2478 frm += IEEE80211_BEACON_BINTVL_LEN; 2479 if (ic->ic_opmode == IEEE80211_M_IBSS) 2480 capinfo = IEEE80211_CAPINFO_IBSS; 2481 else 2482 capinfo = IEEE80211_CAPINFO_ESS; 2483 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2484 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2485 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2486 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2487 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2488 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2489 capinfo |= IEEE80211_CAPINFO_SHORT_SLOTTIME; 2490 *(u_int16_t *)frm = htole16(capinfo); 2491 frm += IEEE80211_BEACON_CAPINFO_LEN; 2492 *frm++ = IEEE80211_ELEMID_SSID; 2493 *frm++ = ni->ni_esslen; 2494 memcpy(frm, ni->ni_essid, ni->ni_esslen); 2495 frm += ni->ni_esslen; 2496 frm = ieee80211_add_rates(frm, rs); 2497 *frm++ = IEEE80211_ELEMID_DSPARMS; 2498 *frm++ = 1; 2499 *frm++ = ieee80211_chan2ieee(ic, ni->ni_chan); 2500 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2501 *frm++ = IEEE80211_ELEMID_IBSSPARMS; 2502 *frm++ = 2; 2503 *frm++ = 0; *frm++ = 0; /* TODO: ATIM window */ 2504 } else { 2505 /* TODO: TIM */ 2506 *frm++ = IEEE80211_ELEMID_TIM; 2507 *frm++ = 4; /* length */ 2508 *frm++ = 0; /* DTIM count */ 2509 *frm++ = 1; /* DTIM period */ 2510 *frm++ = 0; /* bitmap control */ 2511 *frm++ = 0; /* Partial Virtual Bitmap (variable length) */ 2512 } 2513 frm = ieee80211_add_xrates(frm, rs); 2514 m->m_pkthdr.len = m->m_len = frm - mtod(m, u_int8_t *); 2515 m->m_pkthdr.rcvif = (void *)ni; 2516 KASSERT2(m->m_pkthdr.len <= pktlen, 2517 ("beacon bigger than expected, len %u calculated %u", 2518 m->m_pkthdr.len, pktlen)); 2519 2520 RTW_DPRINTF(RTW_DEBUG_BEACON, 2521 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2522 2523 return m; 2524 } 2525 2526 /* Must be called at splnet. */ 2527 static int 2528 rtw_init(struct ifnet *ifp) 2529 { 2530 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2531 struct ieee80211com *ic = &sc->sc_ic; 2532 struct rtw_regs *regs = &sc->sc_regs; 2533 int rc = 0; 2534 2535 if ((rc = rtw_enable(sc)) != 0) 2536 goto out; 2537 2538 /* Cancel pending I/O and reset. */ 2539 rtw_stop(ifp, 0); 2540 2541 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2542 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2543 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2544 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2545 2546 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2547 goto out; 2548 2549 if ((rc = rtw_swring_setup(sc)) != 0) 2550 goto out; 2551 2552 rtw_transmit_config(regs); 2553 2554 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2555 2556 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2557 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2558 2559 /* long PLCP header, 1Mb/2Mb basic rate */ 2560 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2561 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2562 2563 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2564 rtw_set_access(regs, RTW_ACCESS_NONE); 2565 2566 /* XXX from reference sources */ 2567 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2568 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2569 2570 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2571 2572 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2573 /* from Linux driver */ 2574 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2575 2576 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2577 2578 rtw_enable_interrupts(sc); 2579 2580 rtw_pktfilt_load(sc); 2581 2582 rtw_hwring_setup(sc); 2583 2584 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_wep_txkey); 2585 2586 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2587 2588 ifp->if_flags |= IFF_RUNNING; 2589 ic->ic_state = IEEE80211_S_INIT; 2590 2591 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2592 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2593 2594 rtw_resume_ticks(sc); 2595 2596 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2597 2598 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2599 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2600 else 2601 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2602 2603 out: 2604 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2605 return rc; 2606 } 2607 2608 static __inline void 2609 rtw_led_init(struct rtw_regs *regs) 2610 { 2611 uint8_t cfg0, cfg1; 2612 2613 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2614 2615 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2616 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2617 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2618 2619 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2620 RTW_DPRINTF(RTW_DEBUG_LED, 2621 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2622 2623 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2624 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2625 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2626 2627 rtw_set_access(regs, RTW_ACCESS_NONE); 2628 } 2629 2630 /* 2631 * IEEE80211_S_INIT: LED1 off 2632 * 2633 * IEEE80211_S_AUTH, 2634 * IEEE80211_S_ASSOC, 2635 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2636 * 2637 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2638 */ 2639 static void 2640 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2641 { 2642 struct rtw_led_state *ls; 2643 2644 ls = &sc->sc_led_state; 2645 2646 switch (nstate) { 2647 case IEEE80211_S_INIT: 2648 rtw_led_init(&sc->sc_regs); 2649 callout_stop(&ls->ls_slow_ch); 2650 callout_stop(&ls->ls_fast_ch); 2651 ls->ls_slowblink = 0; 2652 ls->ls_actblink = 0; 2653 ls->ls_default = 0; 2654 break; 2655 case IEEE80211_S_SCAN: 2656 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2657 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2658 /*FALLTHROUGH*/ 2659 case IEEE80211_S_AUTH: 2660 case IEEE80211_S_ASSOC: 2661 ls->ls_default = RTW_LED1; 2662 ls->ls_actblink = RTW_LED1; 2663 ls->ls_slowblink = RTW_LED1; 2664 break; 2665 case IEEE80211_S_RUN: 2666 ls->ls_slowblink = 0; 2667 break; 2668 } 2669 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2670 } 2671 2672 static void 2673 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2674 { 2675 uint8_t led_condition; 2676 bus_size_t ofs; 2677 uint8_t mask, newval, val; 2678 2679 led_condition = ls->ls_default; 2680 2681 if (ls->ls_state & RTW_LED_S_SLOW) 2682 led_condition ^= ls->ls_slowblink; 2683 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2684 led_condition ^= ls->ls_actblink; 2685 2686 RTW_DPRINTF(RTW_DEBUG_LED, 2687 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2688 2689 switch (hwverid) { 2690 default: 2691 case 'F': 2692 ofs = RTW_PSR; 2693 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2694 if (led_condition & RTW_LED0) 2695 newval &= ~RTW_PSR_LEDGPO0; 2696 if (led_condition & RTW_LED1) 2697 newval &= ~RTW_PSR_LEDGPO1; 2698 break; 2699 case 'D': 2700 ofs = RTW_9346CR; 2701 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2702 newval = RTW_9346CR_EEM_PROGRAM; 2703 if (led_condition & RTW_LED0) 2704 newval |= RTW_9346CR_EEDI; 2705 if (led_condition & RTW_LED1) 2706 newval |= RTW_9346CR_EECS; 2707 break; 2708 } 2709 val = RTW_READ8(regs, ofs); 2710 RTW_DPRINTF(RTW_DEBUG_LED, 2711 ("%s: read %" PRIx8 " from reg[%#02x]\n", __func__, val, ofs)); 2712 val &= ~mask; 2713 val |= newval; 2714 RTW_WRITE8(regs, ofs, val); 2715 RTW_DPRINTF(RTW_DEBUG_LED, 2716 ("%s: wrote %" PRIx8 " to reg[%#02x]\n", __func__, val, ofs)); 2717 RTW_SYNC(regs, ofs, ofs); 2718 } 2719 2720 static void 2721 rtw_led_fastblink(void *arg) 2722 { 2723 int ostate, s; 2724 struct rtw_softc *sc = (struct rtw_softc *)arg; 2725 struct rtw_led_state *ls = &sc->sc_led_state; 2726 2727 s = splnet(); 2728 ostate = ls->ls_state; 2729 ls->ls_state ^= ls->ls_event; 2730 2731 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2732 ls->ls_state &= ~RTW_LED_S_TX; 2733 2734 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2735 ls->ls_state &= ~RTW_LED_S_RX; 2736 2737 ls->ls_event = 0; 2738 2739 if (ostate != ls->ls_state) 2740 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2741 splx(s); 2742 2743 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2744 } 2745 2746 static void 2747 rtw_led_slowblink(void *arg) 2748 { 2749 int s; 2750 struct rtw_softc *sc = (struct rtw_softc *)arg; 2751 struct rtw_led_state *ls = &sc->sc_led_state; 2752 2753 s = splnet(); 2754 ls->ls_state ^= RTW_LED_S_SLOW; 2755 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2756 splx(s); 2757 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2758 } 2759 2760 static __inline void 2761 rtw_led_attach(struct rtw_softc *sc) 2762 { 2763 struct rtw_led_state *ls = &sc->sc_led_state; 2764 2765 callout_init(&ls->ls_fast_ch); 2766 callout_init(&ls->ls_slow_ch); 2767 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, (void *)sc); 2768 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, (void *)sc); 2769 } 2770 2771 static int 2772 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2773 { 2774 int rc = 0, s; 2775 struct rtw_softc *sc = ifp->if_softc; 2776 struct ifreq *ifr = (struct ifreq *)data; 2777 2778 s = splnet(); 2779 switch (cmd) { 2780 case SIOCSIFFLAGS: 2781 if ((ifp->if_flags & IFF_UP) != 0) { 2782 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2783 rtw_pktfilt_load(sc); 2784 } else 2785 rc = rtw_init(ifp); 2786 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2787 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2788 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2789 rtw_stop(ifp, 1); 2790 } 2791 break; 2792 case SIOCADDMULTI: 2793 case SIOCDELMULTI: 2794 if (cmd == SIOCADDMULTI) 2795 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2796 else 2797 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2798 if (rc != ENETRESET) 2799 break; 2800 if (ifp->if_flags & IFF_RUNNING) 2801 rtw_pktfilt_load(sc); 2802 rc = 0; 2803 break; 2804 case SIOCS80211NWKEY: 2805 if ((rc = ieee80211_ioctl(ifp, cmd, data)) != ENETRESET) 2806 break; 2807 rc = 0; 2808 if ((ifp->if_flags & IFF_RUNNING) == 0) 2809 break; 2810 rtw_wep_setkeys(sc, sc->sc_ic.ic_nw_keys, 2811 sc->sc_ic.ic_wep_txkey); 2812 break; 2813 default: 2814 if ((rc = ieee80211_ioctl(ifp, cmd, data)) != ENETRESET) 2815 break; 2816 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2817 rc = rtw_init(ifp); 2818 else 2819 rc = 0; 2820 break; 2821 } 2822 splx(s); 2823 return rc; 2824 } 2825 2826 /* Select a transmit ring with at least one h/w and s/w descriptor free. 2827 * Return 0 on success, -1 on failure. 2828 */ 2829 static __inline int 2830 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 2831 struct rtw_txdesc_blk **tdbp, int pri) 2832 { 2833 struct rtw_txsoft_blk *tsb; 2834 struct rtw_txdesc_blk *tdb; 2835 2836 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 2837 2838 tsb = &sc->sc_txsoft_blk[pri]; 2839 tdb = &sc->sc_txdesc_blk[pri]; 2840 2841 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 2842 *tsbp = NULL; 2843 *tdbp = NULL; 2844 return -1; 2845 } 2846 *tsbp = tsb; 2847 *tdbp = tdb; 2848 return 0; 2849 } 2850 2851 static __inline struct mbuf * 2852 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 2853 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 2854 struct ieee80211_node **nip, short *if_flagsp) 2855 { 2856 struct mbuf *m; 2857 2858 if (IF_IS_EMPTY(ifq)) 2859 return NULL; 2860 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 2861 *if_flagsp |= IFF_OACTIVE; 2862 return NULL; 2863 } 2864 IF_DEQUEUE(ifq, m); 2865 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2866 m->m_pkthdr.rcvif = NULL; 2867 return m; 2868 } 2869 2870 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 2871 * at the driver's selection of transmit control block for the packet. 2872 */ 2873 static __inline int 2874 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 2875 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 2876 struct ieee80211_node **nip) 2877 { 2878 struct mbuf *m0; 2879 struct rtw_softc *sc; 2880 short *if_flagsp; 2881 2882 sc = (struct rtw_softc *)ifp->if_softc; 2883 2884 DPRINTF(sc, RTW_DEBUG_XMIT, 2885 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2886 2887 if_flagsp = &ifp->if_flags; 2888 2889 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 2890 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 2891 tdbp, nip, if_flagsp)) != NULL) { 2892 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 2893 __func__)); 2894 return 0; 2895 } 2896 2897 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 2898 tdbp, nip, if_flagsp)) != NULL) { 2899 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 2900 __func__)); 2901 return 0; 2902 } 2903 2904 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 2905 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 2906 return 0; 2907 } 2908 2909 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_pwrsaveq, RTW_TXPRIHI, 2910 tsbp, tdbp, nip, if_flagsp)) != NULL) { 2911 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue pwrsave frame\n", 2912 __func__)); 2913 return 0; 2914 } 2915 2916 if (rtw_txring_choose(sc, tsbp, tdbp, RTW_TXPRIMD) == -1) { 2917 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no descriptor\n", __func__)); 2918 *if_flagsp |= IFF_OACTIVE; 2919 return 0; 2920 } 2921 2922 *mp = NULL; 2923 2924 IFQ_DEQUEUE(&ifp->if_snd, m0); 2925 if (m0 == NULL) { 2926 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame/ring ready\n", 2927 __func__)); 2928 return 0; 2929 } 2930 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 2931 ifp->if_opackets++; 2932 #if NBPFILTER > 0 2933 if (ifp->if_bpf) 2934 bpf_mtap(ifp->if_bpf, m0); 2935 #endif 2936 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2937 DPRINTF(sc, RTW_DEBUG_XMIT, 2938 ("%s: encap error\n", __func__)); 2939 ifp->if_oerrors++; 2940 return -1; 2941 } 2942 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 2943 *mp = m0; 2944 return 0; 2945 } 2946 2947 static int 2948 rtw_seg_too_short(bus_dmamap_t dmamap) 2949 { 2950 int i; 2951 for (i = 0; i < dmamap->dm_nsegs; i++) { 2952 if (dmamap->dm_segs[i].ds_len < 4) { 2953 printf("%s: segment too short\n", __func__); 2954 return 1; 2955 } 2956 } 2957 return 0; 2958 } 2959 2960 /* TBD factor with atw_start */ 2961 static struct mbuf * 2962 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2963 u_int ndescfree, short *ifflagsp, const char *dvname) 2964 { 2965 int first, rc; 2966 struct mbuf *m, *m0; 2967 2968 m0 = chain; 2969 2970 /* 2971 * Load the DMA map. Copy and try (once) again if the packet 2972 * didn't fit in the alloted number of segments. 2973 */ 2974 for (first = 1; 2975 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2976 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2977 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 2978 first = 0) { 2979 if (rc == 0) 2980 bus_dmamap_unload(dmat, dmam); 2981 MGETHDR(m, M_DONTWAIT, MT_DATA); 2982 if (m == NULL) { 2983 printf("%s: unable to allocate Tx mbuf\n", 2984 dvname); 2985 break; 2986 } 2987 if (m0->m_pkthdr.len > MHLEN) { 2988 MCLGET(m, M_DONTWAIT); 2989 if ((m->m_flags & M_EXT) == 0) { 2990 printf("%s: cannot allocate Tx cluster\n", 2991 dvname); 2992 m_freem(m); 2993 break; 2994 } 2995 } 2996 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2997 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 2998 m_freem(m0); 2999 m0 = m; 3000 m = NULL; 3001 } 3002 if (rc != 0) { 3003 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 3004 m_freem(m0); 3005 return NULL; 3006 } else if (rtw_seg_too_short(dmam)) { 3007 printf("%s: cannot load Tx buffer, segment too short\n", 3008 dvname); 3009 bus_dmamap_unload(dmat, dmam); 3010 m_freem(m0); 3011 return NULL; 3012 } else if (dmam->dm_nsegs > ndescfree) { 3013 *ifflagsp |= IFF_OACTIVE; 3014 bus_dmamap_unload(dmat, dmam); 3015 m_freem(m0); 3016 return NULL; 3017 } 3018 return m0; 3019 } 3020 3021 #ifdef RTW_DEBUG 3022 static void 3023 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3024 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3025 { 3026 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3027 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] ctl0 %#08x " 3028 "ctl1 %#08x buf %#08x len %#08x\n", 3029 sc->sc_dev.dv_xname, ts, action, desc, 3030 le32toh(td->td_ctl0), 3031 le32toh(td->td_ctl1), le32toh(td->td_buf), 3032 le32toh(td->td_len))); 3033 } 3034 #endif /* RTW_DEBUG */ 3035 3036 static void 3037 rtw_start(struct ifnet *ifp) 3038 { 3039 uint8_t tppoll; 3040 int desc, i, lastdesc, npkt, rate; 3041 uint32_t proto_ctl0, ctl0, ctl1; 3042 bus_dmamap_t dmamap; 3043 struct ieee80211com *ic; 3044 struct ieee80211_duration *d0; 3045 struct ieee80211_frame *wh; 3046 struct ieee80211_node *ni; 3047 struct mbuf *m0; 3048 struct rtw_softc *sc; 3049 struct rtw_txsoft_blk *tsb; 3050 struct rtw_txdesc_blk *tdb; 3051 struct rtw_txsoft *ts; 3052 struct rtw_txdesc *td; 3053 3054 sc = (struct rtw_softc *)ifp->if_softc; 3055 ic = &sc->sc_ic; 3056 3057 DPRINTF(sc, RTW_DEBUG_XMIT, 3058 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3059 3060 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3061 goto out; 3062 3063 /* XXX do real rate control */ 3064 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3065 3066 rate = MAX(2, ieee80211_get_rate(ic)); 3067 3068 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3069 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3070 3071 for (;;) { 3072 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3073 continue; 3074 if (m0 == NULL) 3075 break; 3076 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3077 3078 dmamap = ts->ts_dmamap; 3079 3080 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3081 tdb->tdb_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 3082 3083 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3084 DPRINTF(sc, RTW_DEBUG_XMIT, 3085 ("%s: fail dmamap load\n", __func__)); 3086 goto post_dequeue_err; 3087 } 3088 3089 #ifdef RTW_DEBUG 3090 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 3091 (IFF_DEBUG|IFF_LINK2)) { 3092 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3093 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3094 : sizeof(wh), 3095 rate, 0); 3096 } 3097 #endif /* RTW_DEBUG */ 3098 ctl0 = proto_ctl0 | 3099 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3100 3101 wh = mtod(m0, struct ieee80211_frame *); 3102 3103 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3104 IEEE80211_FC0_TYPE_MGT) { 3105 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3106 } else switch (rate) { 3107 default: 3108 case 2: 3109 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3110 break; 3111 case 4: 3112 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3113 break; 3114 case 11: 3115 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3116 break; 3117 case 22: 3118 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3119 break; 3120 } 3121 3122 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) 3123 ctl0 |= LSHIFT(sc->sc_txkey, RTW_TXCTL0_KEYID_MASK); 3124 3125 if (ieee80211_compute_duration(wh, m0->m_pkthdr.len, 3126 ic->ic_flags, ic->ic_fragthreshold, 3127 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3128 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 3129 (IFF_DEBUG|IFF_LINK2)) == -1) { 3130 DPRINTF(sc, RTW_DEBUG_XMIT, 3131 ("%s: fail compute duration\n", __func__)); 3132 goto post_load_err; 3133 } 3134 3135 /* XXX >= ? */ 3136 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3137 ctl0 |= RTW_TXCTL0_RTSEN; 3138 3139 d0 = &ts->ts_d0; 3140 3141 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3142 3143 ctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3144 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3145 3146 if (d0->d_residue) 3147 ctl1 |= RTW_TXCTL1_LENGEXT; 3148 3149 /* TBD fragmentation */ 3150 3151 ts->ts_first = tdb->tdb_next; 3152 3153 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3154 BUS_DMASYNC_PREWRITE); 3155 3156 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3157 3158 #if NBPFILTER > 0 3159 if (ic->ic_rawbpf != NULL) 3160 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3161 3162 if (sc->sc_radiobpf != NULL) { 3163 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3164 3165 rt->rt_flags = 0; 3166 rt->rt_rate = rate; 3167 rt->rt_chan_freq = 3168 htole16(ic->ic_bss->ni_chan->ic_freq); 3169 rt->rt_chan_flags = 3170 htole16(ic->ic_bss->ni_chan->ic_flags); 3171 3172 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rt, 3173 sizeof(sc->sc_txtapu), m0); 3174 } 3175 #endif /* NPBFILTER > 0 */ 3176 3177 for (i = 0, lastdesc = desc = ts->ts_first; 3178 i < dmamap->dm_nsegs; 3179 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3180 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3181 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3182 ("%s: seg too long\n", __func__)); 3183 goto post_load_err; 3184 } 3185 td = &tdb->tdb_desc[desc]; 3186 td->td_ctl0 = htole32(ctl0); 3187 if (i != 0) 3188 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3189 td->td_ctl1 = htole32(ctl1); 3190 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3191 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3192 lastdesc = desc; 3193 #ifdef RTW_DEBUG 3194 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3195 #endif /* RTW_DEBUG */ 3196 } 3197 3198 KASSERT(desc < tdb->tdb_ndesc); 3199 3200 ts->ts_ni = ni; 3201 ts->ts_mbuf = m0; 3202 ts->ts_last = lastdesc; 3203 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3204 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3205 htole32(RTW_TXCTL0_FS); 3206 3207 #ifdef RTW_DEBUG 3208 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3209 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3210 #endif /* RTW_DEBUG */ 3211 3212 tdb->tdb_nfree -= dmamap->dm_nsegs; 3213 tdb->tdb_next = desc; 3214 3215 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3216 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3217 3218 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3219 htole32(RTW_TXCTL0_OWN); 3220 3221 #ifdef RTW_DEBUG 3222 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3223 #endif /* RTW_DEBUG */ 3224 3225 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3226 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3227 3228 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3229 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3230 3231 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) { 3232 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3233 tsb->tsb_tx_timer = 5; 3234 ifp->if_timer = 1; 3235 } 3236 3237 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3238 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, 3239 tppoll | (tsb->tsb_poll & RTW_TPPOLL_ALL)); 3240 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3241 } 3242 out: 3243 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3244 return; 3245 post_load_err: 3246 bus_dmamap_unload(sc->sc_dmat, dmamap); 3247 m_freem(m0); 3248 post_dequeue_err: 3249 ieee80211_release_node(&sc->sc_ic, ni); 3250 return; 3251 } 3252 3253 static void 3254 rtw_watchdog(struct ifnet *ifp) 3255 { 3256 uint8_t tppoll; 3257 int pri; 3258 struct rtw_softc *sc; 3259 struct rtw_txsoft_blk *tsb; 3260 3261 sc = ifp->if_softc; 3262 3263 ifp->if_timer = 0; 3264 3265 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 3266 return; 3267 3268 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3269 tsb = &sc->sc_txsoft_blk[pri]; 3270 3271 if (tsb->tsb_tx_timer == 0) 3272 continue; 3273 3274 if (--tsb->tsb_tx_timer == 0) { 3275 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3276 continue; 3277 printf("%s: transmit timeout, priority %d\n", 3278 ifp->if_xname, pri); 3279 ifp->if_oerrors++; 3280 /* Stop Tx DMA, disable transmitter, clear 3281 * Tx rings, and restart. 3282 * 3283 * TBD Stop/restart just the broken ring? 3284 */ 3285 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3286 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, 3287 tppoll | RTW_TPPOLL_SALL); 3288 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3289 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 0); 3290 rtw_txdescs_reset(sc); 3291 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 1); 3292 rtw_start(ifp); 3293 } else 3294 ifp->if_timer = 1; 3295 } 3296 ieee80211_watchdog(ifp); 3297 return; 3298 } 3299 3300 static void 3301 rtw_start_beacon(struct rtw_softc *sc, int enable) 3302 { 3303 /* TBD */ 3304 return; 3305 } 3306 3307 static void 3308 rtw_next_scan(void *arg) 3309 { 3310 struct ieee80211com *ic = arg; 3311 int s; 3312 3313 /* don't call rtw_start w/o network interrupts blocked */ 3314 s = splnet(); 3315 if (ic->ic_state == IEEE80211_S_SCAN) 3316 ieee80211_next_scan(ic); 3317 splx(s); 3318 } 3319 3320 static void 3321 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, enum ieee80211_opmode opmode, 3322 uint16_t intval0) 3323 { 3324 uint16_t bcnitv, intval; 3325 int i; 3326 struct rtw_regs *regs = &sc->sc_regs; 3327 3328 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3329 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3330 3331 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3332 3333 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3334 3335 intval = MIN(intval0, PRESHIFT(RTW_BCNITV_BCNITV_MASK)); 3336 3337 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3338 bcnitv |= LSHIFT(intval, RTW_BCNITV_BCNITV_MASK); 3339 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3340 /* magic from Linux */ 3341 RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND)); 3342 RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV)); 3343 3344 rtw_set_nettype(sc, opmode); 3345 3346 rtw_set_access(regs, RTW_ACCESS_NONE); 3347 3348 /* TBD WEP */ 3349 RTW_WRITE8(regs, RTW_SCR, 0); 3350 3351 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 3352 } 3353 3354 /* Synchronize the hardware state with the software state. */ 3355 static int 3356 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3357 { 3358 struct ifnet *ifp = &ic->ic_if; 3359 struct rtw_softc *sc = ifp->if_softc; 3360 struct mbuf *m; 3361 enum ieee80211_state ostate; 3362 int error; 3363 3364 ostate = ic->ic_state; 3365 3366 rtw_led_newstate(sc, nstate); 3367 3368 if (nstate == IEEE80211_S_INIT) { 3369 callout_stop(&sc->sc_scan_ch); 3370 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3371 rtw_start_beacon(sc, 0); 3372 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3373 } 3374 3375 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3376 rtw_pwrstate(sc, RTW_ON); 3377 3378 if ((error = rtw_tune(sc)) != 0) 3379 return error; 3380 3381 switch (nstate) { 3382 case IEEE80211_S_ASSOC: 3383 rtw_join_bss(sc, ic->ic_bss->ni_bssid, ic->ic_opmode, 3384 ic->ic_bss->ni_intval); 3385 break; 3386 case IEEE80211_S_INIT: 3387 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3388 break; 3389 case IEEE80211_S_SCAN: 3390 if (ostate != IEEE80211_S_SCAN) { 3391 (void)memset(ic->ic_bss->ni_bssid, 0, 3392 IEEE80211_ADDR_LEN); 3393 rtw_join_bss(sc, ic->ic_bss->ni_bssid, ic->ic_opmode, 3394 ic->ic_bss->ni_intval); 3395 } 3396 3397 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3398 rtw_next_scan, ic); 3399 3400 break; 3401 case IEEE80211_S_RUN: 3402 switch (ic->ic_opmode) { 3403 case IEEE80211_M_HOSTAP: 3404 case IEEE80211_M_IBSS: 3405 m = rtw_beacon_alloc(sc, ic->ic_bss); 3406 if (m == NULL) { 3407 printf("%s: could not allocate beacon\n", 3408 sc->sc_dev.dv_xname); 3409 } else 3410 IF_ENQUEUE(&sc->sc_beaconq, m); 3411 /*FALLTHROUGH*/ 3412 case IEEE80211_M_AHDEMO: 3413 rtw_join_bss(sc, ic->ic_bss->ni_bssid, ic->ic_opmode, 3414 ic->ic_bss->ni_intval); 3415 break; 3416 case IEEE80211_M_MONITOR: 3417 case IEEE80211_M_STA: 3418 break; 3419 } 3420 break; 3421 case IEEE80211_S_AUTH: 3422 break; 3423 } 3424 3425 if (nstate != IEEE80211_S_SCAN) 3426 callout_stop(&sc->sc_scan_ch); 3427 3428 if (nstate == IEEE80211_S_RUN && 3429 (ic->ic_opmode == IEEE80211_M_HOSTAP || 3430 ic->ic_opmode == IEEE80211_M_IBSS)) 3431 rtw_start_beacon(sc, 1); 3432 else 3433 rtw_start_beacon(sc, 0); 3434 3435 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3436 } 3437 3438 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3439 static uint64_t 3440 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3441 { 3442 uint32_t tsftl, tsfth; 3443 3444 tsfth = RTW_READ(regs, RTW_TSFTRH); 3445 tsftl = RTW_READ(regs, RTW_TSFTRL); 3446 if (tsftl < rstamp) /* Compensate for rollover. */ 3447 tsfth--; 3448 return ((uint64_t)tsfth << 32) | rstamp; 3449 } 3450 3451 static void 3452 rtw_ibss_merge(struct rtw_softc *sc, struct ieee80211_node *ni, uint32_t rstamp) 3453 { 3454 struct ieee80211com *ic = &sc->sc_ic; 3455 3456 if (le64toh(ni->ni_tsf) >= rtw_tsf_extend(&sc->sc_regs, rstamp) && 3457 ieee80211_ibss_merge(ic, ni) == ENETRESET) { 3458 rtw_join_bss(sc, ic->ic_bss->ni_bssid, ic->ic_opmode, 3459 ic->ic_bss->ni_intval); 3460 } 3461 return; 3462 } 3463 3464 static void 3465 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3466 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3467 { 3468 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 3469 3470 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3471 3472 switch (subtype) { 3473 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3474 case IEEE80211_FC0_SUBTYPE_BEACON: 3475 if (ic->ic_opmode != IEEE80211_M_IBSS || 3476 ic->ic_state != IEEE80211_S_RUN) 3477 return; 3478 rtw_ibss_merge(sc, ni, rstamp); 3479 break; 3480 default: 3481 break; 3482 } 3483 return; 3484 } 3485 3486 static struct ieee80211_node * 3487 rtw_node_alloc(struct ieee80211com *ic) 3488 { 3489 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 3490 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 3491 3492 DPRINTF(sc, RTW_DEBUG_NODE, 3493 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3494 return ni; 3495 } 3496 3497 static void 3498 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 3499 { 3500 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 3501 3502 DPRINTF(sc, RTW_DEBUG_NODE, 3503 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3504 ether_sprintf(ni->ni_bssid))); 3505 (*sc->sc_mtbl.mt_node_free)(ic, ni); 3506 } 3507 3508 static int 3509 rtw_media_change(struct ifnet *ifp) 3510 { 3511 int error; 3512 3513 error = ieee80211_media_change(ifp); 3514 if (error == ENETRESET) { 3515 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3516 (IFF_RUNNING|IFF_UP)) 3517 rtw_init(ifp); /* XXX lose error */ 3518 error = 0; 3519 } 3520 return error; 3521 } 3522 3523 static void 3524 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3525 { 3526 struct rtw_softc *sc = ifp->if_softc; 3527 3528 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3529 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3530 imr->ifm_status = 0; 3531 return; 3532 } 3533 ieee80211_media_status(ifp, imr); 3534 } 3535 3536 void 3537 rtw_power(int why, void *arg) 3538 { 3539 struct rtw_softc *sc = arg; 3540 struct ifnet *ifp = &sc->sc_ic.ic_if; 3541 int s; 3542 3543 DPRINTF(sc, RTW_DEBUG_PWR, 3544 ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3545 3546 s = splnet(); 3547 switch (why) { 3548 case PWR_STANDBY: 3549 /* XXX do nothing. */ 3550 break; 3551 case PWR_SUSPEND: 3552 rtw_stop(ifp, 0); 3553 if (sc->sc_power != NULL) 3554 (*sc->sc_power)(sc, why); 3555 break; 3556 case PWR_RESUME: 3557 if (ifp->if_flags & IFF_UP) { 3558 if (sc->sc_power != NULL) 3559 (*sc->sc_power)(sc, why); 3560 rtw_init(ifp); 3561 } 3562 break; 3563 case PWR_SOFTSUSPEND: 3564 case PWR_SOFTSTANDBY: 3565 case PWR_SOFTRESUME: 3566 break; 3567 } 3568 splx(s); 3569 } 3570 3571 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 3572 void 3573 rtw_shutdown(void *arg) 3574 { 3575 struct rtw_softc *sc = arg; 3576 3577 rtw_stop(&sc->sc_ic.ic_if, 1); 3578 } 3579 3580 static __inline void 3581 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3582 { 3583 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3584 ifp->if_softc = softc; 3585 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3586 IFF_NOTRAILERS; 3587 ifp->if_ioctl = rtw_ioctl; 3588 ifp->if_start = rtw_start; 3589 ifp->if_watchdog = rtw_watchdog; 3590 ifp->if_init = rtw_init; 3591 ifp->if_stop = rtw_stop; 3592 } 3593 3594 static __inline void 3595 rtw_set80211props(struct ieee80211com *ic) 3596 { 3597 int nrate; 3598 ic->ic_phytype = IEEE80211_T_DS; 3599 ic->ic_opmode = IEEE80211_M_STA; 3600 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3601 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 3602 3603 nrate = 0; 3604 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3605 IEEE80211_RATE_BASIC | 2; 3606 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3607 IEEE80211_RATE_BASIC | 4; 3608 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3609 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3610 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3611 } 3612 3613 static __inline void 3614 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3615 { 3616 mtbl->mt_newstate = ic->ic_newstate; 3617 ic->ic_newstate = rtw_newstate; 3618 3619 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3620 ic->ic_recv_mgmt = rtw_recv_mgmt; 3621 3622 mtbl->mt_node_free = ic->ic_node_free; 3623 ic->ic_node_free = rtw_node_free; 3624 3625 mtbl->mt_node_alloc = ic->ic_node_alloc; 3626 ic->ic_node_alloc = rtw_node_alloc; 3627 } 3628 3629 static __inline void 3630 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 3631 void *arg) 3632 { 3633 /* 3634 * Make sure the interface is shutdown during reboot. 3635 */ 3636 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 3637 if (hooks->rh_shutdown == NULL) 3638 printf("%s: WARNING: unable to establish shutdown hook\n", 3639 dvname); 3640 3641 /* 3642 * Add a suspend hook to make sure we come back up after a 3643 * resume. 3644 */ 3645 hooks->rh_power = powerhook_establish(rtw_power, arg); 3646 if (hooks->rh_power == NULL) 3647 printf("%s: WARNING: unable to establish power hook\n", 3648 dvname); 3649 } 3650 3651 static __inline void 3652 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 3653 void *arg) 3654 { 3655 if (hooks->rh_shutdown != NULL) 3656 shutdownhook_disestablish(hooks->rh_shutdown); 3657 3658 if (hooks->rh_power != NULL) 3659 powerhook_disestablish(hooks->rh_power); 3660 } 3661 3662 static __inline void 3663 rtw_init_radiotap(struct rtw_softc *sc) 3664 { 3665 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3666 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3667 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT); 3668 3669 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3670 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3671 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3672 } 3673 3674 static int 3675 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3676 { 3677 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3678 SIMPLEQ_INIT(&tsb->tsb_freeq); 3679 tsb->tsb_ndesc = qlen; 3680 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3681 M_NOWAIT); 3682 if (tsb->tsb_desc == NULL) 3683 return ENOMEM; 3684 return 0; 3685 } 3686 3687 static void 3688 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3689 { 3690 int pri; 3691 struct rtw_txsoft_blk *tsb; 3692 3693 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3694 tsb = &sc->sc_txsoft_blk[pri]; 3695 free(tsb->tsb_desc, M_DEVBUF); 3696 tsb->tsb_desc = NULL; 3697 } 3698 } 3699 3700 static int 3701 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3702 { 3703 int pri, rc = 0; 3704 int qlen[RTW_NTXPRI] = 3705 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3706 struct rtw_txsoft_blk *tsbs; 3707 3708 tsbs = sc->sc_txsoft_blk; 3709 3710 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3711 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3712 if (rc != 0) 3713 break; 3714 } 3715 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3716 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3717 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3718 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3719 return rc; 3720 } 3721 3722 static void 3723 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3724 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3725 { 3726 tdb->tdb_ndesc = ndesc; 3727 tdb->tdb_desc = desc; 3728 tdb->tdb_physbase = physbase; 3729 tdb->tdb_ofs = ofs; 3730 3731 (void)memset(tdb->tdb_desc, 0, 3732 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3733 3734 rtw_txdesc_blk_reset(tdb); 3735 } 3736 3737 static void 3738 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3739 { 3740 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3741 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3742 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3743 3744 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3745 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3746 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3747 3748 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3749 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3750 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3751 3752 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3753 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3754 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3755 } 3756 3757 static struct rtw_rf * 3758 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3759 { 3760 rtw_rf_write_t rf_write; 3761 struct rtw_rf *rf; 3762 3763 switch (rfchipid) { 3764 default: 3765 rf_write = rtw_rf_hostwrite; 3766 break; 3767 case RTW_RFCHIPID_INTERSIL: 3768 case RTW_RFCHIPID_PHILIPS: 3769 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3770 case RTW_RFCHIPID_RFMD: 3771 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3772 break; 3773 } 3774 3775 switch (rfchipid) { 3776 case RTW_RFCHIPID_MAXIM: 3777 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3778 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3779 break; 3780 case RTW_RFCHIPID_PHILIPS: 3781 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3782 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3783 break; 3784 case RTW_RFCHIPID_RFMD: 3785 /* XXX RFMD has no RF constructor */ 3786 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3787 /*FALLTHROUGH*/ 3788 default: 3789 return NULL; 3790 } 3791 rf->rf_continuous_tx_cb = 3792 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3793 rf->rf_continuous_tx_arg = (void *)sc; 3794 return rf; 3795 } 3796 3797 /* Revision C and later use a different PHY delay setting than 3798 * revisions A and B. 3799 */ 3800 static uint8_t 3801 rtw_check_phydelay(struct rtw_regs *regs, uint32_t rcr0) 3802 { 3803 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3804 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3805 3806 uint8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 3807 3808 RTW_WRITE(regs, RTW_RCR, REVAB); 3809 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3810 RTW_WRITE(regs, RTW_RCR, REVC); 3811 3812 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3813 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3814 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3815 3816 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 3817 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3818 3819 return phydelay; 3820 #undef REVC 3821 } 3822 3823 void 3824 rtw_attach(struct rtw_softc *sc) 3825 { 3826 struct rtw_txsoft_blk *tsb; 3827 int pri, rc; 3828 3829 NEXT_ATTACH_STATE(sc, DETACHED); 3830 3831 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3832 case RTW_TCR_HWVERID_F: 3833 sc->sc_hwverid = 'F'; 3834 break; 3835 case RTW_TCR_HWVERID_D: 3836 sc->sc_hwverid = 'D'; 3837 break; 3838 default: 3839 sc->sc_hwverid = '?'; 3840 break; 3841 } 3842 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, 3843 sc->sc_hwverid); 3844 3845 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3846 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3847 0); 3848 3849 if (rc != 0) { 3850 printf("%s: could not allocate hw descriptors, error %d\n", 3851 sc->sc_dev.dv_xname, rc); 3852 goto err; 3853 } 3854 3855 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3856 3857 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3858 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3859 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3860 3861 if (rc != 0) { 3862 printf("%s: could not map hw descriptors, error %d\n", 3863 sc->sc_dev.dv_xname, rc); 3864 goto err; 3865 } 3866 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3867 3868 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3869 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3870 3871 if (rc != 0) { 3872 printf("%s: could not create DMA map for hw descriptors, " 3873 "error %d\n", sc->sc_dev.dv_xname, rc); 3874 goto err; 3875 } 3876 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3877 3878 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 3879 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 3880 3881 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3882 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 3883 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 3884 } 3885 3886 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3887 sizeof(struct rtw_descs), NULL, 0); 3888 3889 if (rc != 0) { 3890 printf("%s: could not load DMA map for hw descriptors, " 3891 "error %d\n", sc->sc_dev.dv_xname, rc); 3892 goto err; 3893 } 3894 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3895 3896 if (rtw_txsoft_blk_setup_all(sc) != 0) 3897 goto err; 3898 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3899 3900 rtw_txdesc_blk_setup_all(sc); 3901 3902 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3903 3904 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 3905 3906 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3907 tsb = &sc->sc_txsoft_blk[pri]; 3908 3909 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3910 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 3911 printf("%s: could not load DMA map for " 3912 "hw tx descriptors, error %d\n", 3913 sc->sc_dev.dv_xname, rc); 3914 goto err; 3915 } 3916 } 3917 3918 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3919 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 3920 RTW_RXQLEN)) != 0) { 3921 printf("%s: could not load DMA map for hw rx descriptors, " 3922 "error %d\n", sc->sc_dev.dv_xname, rc); 3923 goto err; 3924 } 3925 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3926 3927 /* Reset the chip to a known state. */ 3928 if (rtw_reset(sc) != 0) 3929 goto err; 3930 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3931 3932 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3933 3934 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3935 sc->sc_flags |= RTW_F_9356SROM; 3936 3937 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3938 sc->sc_dev.dv_xname) != 0) 3939 goto err; 3940 3941 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3942 3943 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3944 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3945 sc->sc_dev.dv_xname) != 0) { 3946 printf("%s: attach failed, malformed serial ROM\n", 3947 sc->sc_dev.dv_xname); 3948 goto err; 3949 } 3950 3951 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 3952 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 3953 3954 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 3955 3956 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3957 3958 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 3959 sc->sc_flags & RTW_F_DIGPHY); 3960 3961 if (sc->sc_rf == NULL) { 3962 printf("%s: attach failed, could not attach RF\n", 3963 sc->sc_dev.dv_xname); 3964 goto err; 3965 } 3966 3967 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3968 3969 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 3970 3971 RTW_DPRINTF(RTW_DEBUG_ATTACH, 3972 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 3973 3974 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 3975 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 3976 sc->sc_dev.dv_xname); 3977 3978 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 3979 sc->sc_dev.dv_xname); 3980 3981 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 3982 sc->sc_dev.dv_xname) != 0) 3983 goto err; 3984 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 3985 3986 rtw_setifprops(&sc->sc_if, sc->sc_dev.dv_xname, (void*)sc); 3987 3988 IFQ_SET_READY(&sc->sc_if.if_snd); 3989 3990 rtw_set80211props(&sc->sc_ic); 3991 3992 rtw_led_attach(sc); 3993 3994 /* 3995 * Call MI attach routines. 3996 */ 3997 if_attach(&sc->sc_if); 3998 ieee80211_ifattach(&sc->sc_if); 3999 4000 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4001 4002 /* possibly we should fill in our own sc_send_prresp, since 4003 * the RTL8180 is probably sending probe responses in ad hoc 4004 * mode. 4005 */ 4006 4007 /* complete initialization */ 4008 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 4009 callout_init(&sc->sc_scan_ch); 4010 4011 rtw_init_radiotap(sc); 4012 4013 #if NBPFILTER > 0 4014 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 4015 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4016 #endif 4017 4018 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 4019 4020 NEXT_ATTACH_STATE(sc, FINISHED); 4021 4022 return; 4023 err: 4024 rtw_detach(sc); 4025 return; 4026 } 4027 4028 int 4029 rtw_detach(struct rtw_softc *sc) 4030 { 4031 int pri; 4032 4033 sc->sc_flags |= RTW_F_INVALID; 4034 4035 switch (sc->sc_attach_state) { 4036 case FINISHED: 4037 rtw_stop(&sc->sc_if, 1); 4038 4039 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 4040 (void*)sc); 4041 callout_stop(&sc->sc_scan_ch); 4042 ieee80211_ifdetach(&sc->sc_if); 4043 if_detach(&sc->sc_if); 4044 break; 4045 case FINISH_ID_STA: 4046 case FINISH_RF_ATTACH: 4047 rtw_rf_destroy(sc->sc_rf); 4048 sc->sc_rf = NULL; 4049 /*FALLTHROUGH*/ 4050 case FINISH_PARSE_SROM: 4051 case FINISH_READ_SROM: 4052 rtw_srom_free(&sc->sc_srom); 4053 /*FALLTHROUGH*/ 4054 case FINISH_RESET: 4055 case FINISH_RXMAPS_CREATE: 4056 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4057 RTW_RXQLEN); 4058 /*FALLTHROUGH*/ 4059 case FINISH_TXMAPS_CREATE: 4060 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4061 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4062 sc->sc_txsoft_blk[pri].tsb_desc, 4063 sc->sc_txsoft_blk[pri].tsb_ndesc); 4064 } 4065 /*FALLTHROUGH*/ 4066 case FINISH_TXDESCBLK_SETUP: 4067 case FINISH_TXCTLBLK_SETUP: 4068 rtw_txsoft_blk_cleanup_all(sc); 4069 /*FALLTHROUGH*/ 4070 case FINISH_DESCMAP_LOAD: 4071 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4072 /*FALLTHROUGH*/ 4073 case FINISH_DESCMAP_CREATE: 4074 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4075 /*FALLTHROUGH*/ 4076 case FINISH_DESC_MAP: 4077 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 4078 sizeof(struct rtw_descs)); 4079 /*FALLTHROUGH*/ 4080 case FINISH_DESC_ALLOC: 4081 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4082 sc->sc_desc_nsegs); 4083 /*FALLTHROUGH*/ 4084 case DETACHED: 4085 NEXT_ATTACH_STATE(sc, DETACHED); 4086 break; 4087 } 4088 return 0; 4089 } 4090 4091 int 4092 rtw_activate(struct device *self, enum devact act) 4093 { 4094 struct rtw_softc *sc = (struct rtw_softc *)self; 4095 int rc = 0, s; 4096 4097 s = splnet(); 4098 switch (act) { 4099 case DVACT_ACTIVATE: 4100 rc = EOPNOTSUPP; 4101 break; 4102 4103 case DVACT_DEACTIVATE: 4104 if_deactivate(&sc->sc_ic.ic_if); 4105 break; 4106 } 4107 splx(s); 4108 return rc; 4109 } 4110
Indexes created Thu Oct 30 23:09:54 GMT 2025