rtw.c revision 1.118
1 /* $NetBSD: rtw.c,v 1.118 2010/11/15 05:56:29 uebayasi Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005, 2006, 2007 David Young. All rights 4 * reserved. 5 * 6 * Programmed for NetBSD by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 21 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 28 * OF SUCH DAMAGE. 29 */ 30 /* 31 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.118 2010/11/15 05:56:29 uebayasi Exp $"); 36 37 38 #include <sys/param.h> 39 #include <sys/sysctl.h> 40 #include <sys/systm.h> 41 #include <sys/callout.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/time.h> 46 #include <sys/types.h> 47 #include <sys/device.h> 48 #include <sys/sockio.h> 49 50 #include <machine/endian.h> 51 #include <sys/bus.h> 52 #include <sys/intr.h> /* splnet */ 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net80211/ieee80211_netbsd.h> 59 #include <net80211/ieee80211_var.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <net/bpf.h> 63 64 #include <dev/ic/rtwreg.h> 65 #include <dev/ic/rtwvar.h> 66 #include <dev/ic/rtwphyio.h> 67 #include <dev/ic/rtwphy.h> 68 69 #include <dev/ic/smc93cx6var.h> 70 71 static int rtw_rfprog_fallback = 0; 72 static int rtw_host_rfio = 0; 73 74 #ifdef RTW_DEBUG 75 int rtw_debug = 0; 76 static int rtw_rxbufs_limit = RTW_RXQLEN; 77 #endif /* RTW_DEBUG */ 78 79 #define NEXT_ATTACH_STATE(sc, state) do { \ 80 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 81 ("%s: attach state %s\n", __func__, #state)); \ 82 sc->sc_attach_state = state; \ 83 } while (0) 84 85 int rtw_dwelltime = 200; /* milliseconds */ 86 static struct ieee80211_cipher rtw_cipher_wep; 87 88 static void rtw_disable_interrupts(struct rtw_regs *); 89 static void rtw_enable_interrupts(struct rtw_softc *); 90 91 static int rtw_init(struct ifnet *); 92 93 static void rtw_start(struct ifnet *); 94 static void rtw_reset_oactive(struct rtw_softc *); 95 static struct mbuf *rtw_beacon_alloc(struct rtw_softc *, 96 struct ieee80211_node *); 97 static u_int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *); 98 99 static void rtw_io_enable(struct rtw_softc *, uint8_t, int); 100 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 101 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 102 const u_int8_t[IEEE80211_ADDR_LEN]); 103 static void rtw_key_update_end(struct ieee80211com *); 104 static void rtw_key_update_begin(struct ieee80211com *); 105 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 106 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 107 108 static void rtw_led_attach(struct rtw_led_state *, void *); 109 static void rtw_led_detach(struct rtw_led_state *); 110 static void rtw_led_init(struct rtw_regs *); 111 static void rtw_led_slowblink(void *); 112 static void rtw_led_fastblink(void *); 113 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 114 115 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 116 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 117 #ifdef RTW_DEBUG 118 static void rtw_dump_rings(struct rtw_softc *sc); 119 static void rtw_print_txdesc(struct rtw_softc *, const char *, 120 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 121 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 122 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 123 #endif /* RTW_DEBUG */ 124 #ifdef RTW_DIAG 125 static void rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln); 126 #endif /* RTW_DIAG */ 127 128 /* 129 * Setup sysctl(3) MIB, hw.rtw.* 130 * 131 * TBD condition CTLFLAG_PERMANENT on being a module or not 132 */ 133 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 134 { 135 int rc; 136 const struct sysctlnode *cnode, *rnode; 137 138 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 139 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 140 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 141 goto err; 142 143 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 144 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 145 "Realtek RTL818x 802.11 controls", 146 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 147 goto err; 148 149 #ifdef RTW_DEBUG 150 /* control debugging printfs */ 151 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 152 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 153 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 154 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 155 CTL_CREATE, CTL_EOL)) != 0) 156 goto err; 157 158 /* Limit rx buffers, for simulating resource exhaustion. */ 159 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 160 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 161 "rxbufs_limit", 162 SYSCTL_DESCR("Set rx buffers limit"), 163 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 164 CTL_CREATE, CTL_EOL)) != 0) 165 goto err; 166 167 #endif /* RTW_DEBUG */ 168 /* set fallback RF programming method */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfprog_fallback", 172 SYSCTL_DESCR("Set fallback RF programming method"), 173 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 174 CTL_CREATE, CTL_EOL)) != 0) 175 goto err; 176 177 /* force host to control RF I/O bus */ 178 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 179 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 180 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 181 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 182 CTL_CREATE, CTL_EOL)) != 0) 183 goto err; 184 185 return; 186 err: 187 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 188 } 189 190 static int 191 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 192 { 193 int error, t; 194 struct sysctlnode node; 195 196 node = *rnode; 197 t = *(int*)rnode->sysctl_data; 198 node.sysctl_data = &t; 199 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 200 if (error || newp == NULL) 201 return (error); 202 203 if (t < lower || t > upper) 204 return (EINVAL); 205 206 *(int*)rnode->sysctl_data = t; 207 208 return (0); 209 } 210 211 static int 212 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 213 { 214 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 215 __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 216 } 217 218 static int 219 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 220 { 221 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 222 } 223 224 #ifdef RTW_DEBUG 225 static int 226 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 227 { 228 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 229 0, RTW_DEBUG_MAX); 230 } 231 232 static int 233 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 234 { 235 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 236 0, RTW_RXQLEN); 237 } 238 239 static void 240 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 241 { 242 #define PRINTREG32(sc, reg) \ 243 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 244 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 245 dvname, reg, RTW_READ(regs, reg))) 246 247 #define PRINTREG16(sc, reg) \ 248 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 249 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 250 dvname, reg, RTW_READ16(regs, reg))) 251 252 #define PRINTREG8(sc, reg) \ 253 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 254 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 255 dvname, reg, RTW_READ8(regs, reg))) 256 257 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 258 259 PRINTREG32(regs, RTW_IDR0); 260 PRINTREG32(regs, RTW_IDR1); 261 PRINTREG32(regs, RTW_MAR0); 262 PRINTREG32(regs, RTW_MAR1); 263 PRINTREG32(regs, RTW_TSFTRL); 264 PRINTREG32(regs, RTW_TSFTRH); 265 PRINTREG32(regs, RTW_TLPDA); 266 PRINTREG32(regs, RTW_TNPDA); 267 PRINTREG32(regs, RTW_THPDA); 268 PRINTREG32(regs, RTW_TCR); 269 PRINTREG32(regs, RTW_RCR); 270 PRINTREG32(regs, RTW_TINT); 271 PRINTREG32(regs, RTW_TBDA); 272 PRINTREG32(regs, RTW_ANAPARM); 273 PRINTREG32(regs, RTW_BB); 274 PRINTREG32(regs, RTW_PHYCFG); 275 PRINTREG32(regs, RTW_WAKEUP0L); 276 PRINTREG32(regs, RTW_WAKEUP0H); 277 PRINTREG32(regs, RTW_WAKEUP1L); 278 PRINTREG32(regs, RTW_WAKEUP1H); 279 PRINTREG32(regs, RTW_WAKEUP2LL); 280 PRINTREG32(regs, RTW_WAKEUP2LH); 281 PRINTREG32(regs, RTW_WAKEUP2HL); 282 PRINTREG32(regs, RTW_WAKEUP2HH); 283 PRINTREG32(regs, RTW_WAKEUP3LL); 284 PRINTREG32(regs, RTW_WAKEUP3LH); 285 PRINTREG32(regs, RTW_WAKEUP3HL); 286 PRINTREG32(regs, RTW_WAKEUP3HH); 287 PRINTREG32(regs, RTW_WAKEUP4LL); 288 PRINTREG32(regs, RTW_WAKEUP4LH); 289 PRINTREG32(regs, RTW_WAKEUP4HL); 290 PRINTREG32(regs, RTW_WAKEUP4HH); 291 PRINTREG32(regs, RTW_DK0); 292 PRINTREG32(regs, RTW_DK1); 293 PRINTREG32(regs, RTW_DK2); 294 PRINTREG32(regs, RTW_DK3); 295 PRINTREG32(regs, RTW_RETRYCTR); 296 PRINTREG32(regs, RTW_RDSAR); 297 PRINTREG32(regs, RTW_FER); 298 PRINTREG32(regs, RTW_FEMR); 299 PRINTREG32(regs, RTW_FPSR); 300 PRINTREG32(regs, RTW_FFER); 301 302 /* 16-bit registers */ 303 PRINTREG16(regs, RTW_BRSR); 304 PRINTREG16(regs, RTW_IMR); 305 PRINTREG16(regs, RTW_ISR); 306 PRINTREG16(regs, RTW_BCNITV); 307 PRINTREG16(regs, RTW_ATIMWND); 308 PRINTREG16(regs, RTW_BINTRITV); 309 PRINTREG16(regs, RTW_ATIMTRITV); 310 PRINTREG16(regs, RTW_CRC16ERR); 311 PRINTREG16(regs, RTW_CRC0); 312 PRINTREG16(regs, RTW_CRC1); 313 PRINTREG16(regs, RTW_CRC2); 314 PRINTREG16(regs, RTW_CRC3); 315 PRINTREG16(regs, RTW_CRC4); 316 PRINTREG16(regs, RTW_CWR); 317 318 /* 8-bit registers */ 319 PRINTREG8(regs, RTW_CR); 320 PRINTREG8(regs, RTW_9346CR); 321 PRINTREG8(regs, RTW_CONFIG0); 322 PRINTREG8(regs, RTW_CONFIG1); 323 PRINTREG8(regs, RTW_CONFIG2); 324 PRINTREG8(regs, RTW_MSR); 325 PRINTREG8(regs, RTW_CONFIG3); 326 PRINTREG8(regs, RTW_CONFIG4); 327 PRINTREG8(regs, RTW_TESTR); 328 PRINTREG8(regs, RTW_PSR); 329 PRINTREG8(regs, RTW_SCR); 330 PRINTREG8(regs, RTW_PHYDELAY); 331 PRINTREG8(regs, RTW_CRCOUNT); 332 PRINTREG8(regs, RTW_PHYADDR); 333 PRINTREG8(regs, RTW_PHYDATAW); 334 PRINTREG8(regs, RTW_PHYDATAR); 335 PRINTREG8(regs, RTW_CONFIG5); 336 PRINTREG8(regs, RTW_TPPOLL); 337 338 PRINTREG16(regs, RTW_BSSID16); 339 PRINTREG32(regs, RTW_BSSID32); 340 #undef PRINTREG32 341 #undef PRINTREG16 342 #undef PRINTREG8 343 } 344 #endif /* RTW_DEBUG */ 345 346 void 347 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 348 { 349 struct rtw_regs *regs = &sc->sc_regs; 350 351 uint32_t tcr; 352 tcr = RTW_READ(regs, RTW_TCR); 353 tcr &= ~RTW_TCR_LBK_MASK; 354 if (enable) 355 tcr |= RTW_TCR_LBK_CONT; 356 else 357 tcr |= RTW_TCR_LBK_NORMAL; 358 RTW_WRITE(regs, RTW_TCR, tcr); 359 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 360 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 361 rtw_txdac_enable(sc, !enable); 362 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 363 rtw_set_access(regs, RTW_ACCESS_NONE); 364 } 365 366 #ifdef RTW_DEBUG 367 static const char * 368 rtw_access_string(enum rtw_access access) 369 { 370 switch (access) { 371 case RTW_ACCESS_NONE: 372 return "none"; 373 case RTW_ACCESS_CONFIG: 374 return "config"; 375 case RTW_ACCESS_ANAPARM: 376 return "anaparm"; 377 default: 378 return "unknown"; 379 } 380 } 381 #endif /* RTW_DEBUG */ 382 383 static void 384 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 385 { 386 KASSERT(/* naccess >= RTW_ACCESS_NONE && */ 387 naccess <= RTW_ACCESS_ANAPARM); 388 KASSERT(/* regs->r_access >= RTW_ACCESS_NONE && */ 389 regs->r_access <= RTW_ACCESS_ANAPARM); 390 391 if (naccess == regs->r_access) 392 return; 393 394 switch (naccess) { 395 case RTW_ACCESS_NONE: 396 switch (regs->r_access) { 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 /*FALLTHROUGH*/ 400 case RTW_ACCESS_CONFIG: 401 rtw_config0123_enable(regs, 0); 402 /*FALLTHROUGH*/ 403 case RTW_ACCESS_NONE: 404 break; 405 } 406 break; 407 case RTW_ACCESS_CONFIG: 408 switch (regs->r_access) { 409 case RTW_ACCESS_NONE: 410 rtw_config0123_enable(regs, 1); 411 /*FALLTHROUGH*/ 412 case RTW_ACCESS_CONFIG: 413 break; 414 case RTW_ACCESS_ANAPARM: 415 rtw_anaparm_enable(regs, 0); 416 break; 417 } 418 break; 419 case RTW_ACCESS_ANAPARM: 420 switch (regs->r_access) { 421 case RTW_ACCESS_NONE: 422 rtw_config0123_enable(regs, 1); 423 /*FALLTHROUGH*/ 424 case RTW_ACCESS_CONFIG: 425 rtw_anaparm_enable(regs, 1); 426 /*FALLTHROUGH*/ 427 case RTW_ACCESS_ANAPARM: 428 break; 429 } 430 break; 431 } 432 } 433 434 void 435 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 436 { 437 rtw_set_access1(regs, access); 438 RTW_DPRINTF(RTW_DEBUG_ACCESS, 439 ("%s: access %s -> %s\n", __func__, 440 rtw_access_string(regs->r_access), 441 rtw_access_string(access))); 442 regs->r_access = access; 443 } 444 445 /* 446 * Enable registers, switch register banks. 447 */ 448 void 449 rtw_config0123_enable(struct rtw_regs *regs, int enable) 450 { 451 uint8_t ecr; 452 ecr = RTW_READ8(regs, RTW_9346CR); 453 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 454 if (enable) 455 ecr |= RTW_9346CR_EEM_CONFIG; 456 else { 457 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 458 ecr |= RTW_9346CR_EEM_NORMAL; 459 } 460 RTW_WRITE8(regs, RTW_9346CR, ecr); 461 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 462 } 463 464 /* requires rtw_config0123_enable(, 1) */ 465 void 466 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 467 { 468 uint8_t cfg3; 469 470 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 471 cfg3 |= RTW_CONFIG3_CLKRUNEN; 472 if (enable) 473 cfg3 |= RTW_CONFIG3_PARMEN; 474 else 475 cfg3 &= ~RTW_CONFIG3_PARMEN; 476 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 477 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 478 } 479 480 /* requires rtw_anaparm_enable(, 1) */ 481 void 482 rtw_txdac_enable(struct rtw_softc *sc, int enable) 483 { 484 uint32_t anaparm; 485 struct rtw_regs *regs = &sc->sc_regs; 486 487 anaparm = RTW_READ(regs, RTW_ANAPARM); 488 if (enable) 489 anaparm &= ~RTW_ANAPARM_TXDACOFF; 490 else 491 anaparm |= RTW_ANAPARM_TXDACOFF; 492 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 493 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 494 } 495 496 static inline int 497 rtw_chip_reset1(struct rtw_regs *regs, device_t dev) 498 { 499 uint8_t cr; 500 int i; 501 502 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 503 504 RTW_WBR(regs, RTW_CR, RTW_CR); 505 506 for (i = 0; i < 1000; i++) { 507 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 508 RTW_DPRINTF(RTW_DEBUG_RESET, 509 ("%s: reset in %dus\n", device_xname(dev), i)); 510 return 0; 511 } 512 RTW_RBR(regs, RTW_CR, RTW_CR); 513 DELAY(10); /* 10us */ 514 } 515 516 aprint_error_dev(dev, "reset failed\n"); 517 return ETIMEDOUT; 518 } 519 520 static inline int 521 rtw_chip_reset(struct rtw_regs *regs, device_t dev) 522 { 523 uint32_t tcr; 524 525 /* from Linux driver */ 526 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 527 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK); 528 529 RTW_WRITE(regs, RTW_TCR, tcr); 530 531 RTW_WBW(regs, RTW_CR, RTW_TCR); 532 533 return rtw_chip_reset1(regs, dev); 534 } 535 536 static int 537 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen) 538 { 539 struct ieee80211_key keycopy; 540 541 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 542 543 keycopy = *k; 544 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 545 546 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, hdrlen); 547 } 548 549 static int 550 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 551 { 552 struct rtw_softc *sc = ic->ic_ifp->if_softc; 553 554 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, 555 k->wk_keyix)); 556 557 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID); 558 559 if (k->wk_keylen != 0 && 560 k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 561 sc->sc_flags &= ~RTW_F_DK_VALID; 562 563 return 1; 564 } 565 566 static int 567 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 568 const u_int8_t mac[IEEE80211_ADDR_LEN]) 569 { 570 struct rtw_softc *sc = ic->ic_ifp->if_softc; 571 572 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 573 574 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID); 575 576 sc->sc_flags &= ~RTW_F_DK_VALID; 577 578 return 1; 579 } 580 581 static void 582 rtw_key_update_begin(struct ieee80211com *ic) 583 { 584 #ifdef RTW_DEBUG 585 struct ifnet *ifp = ic->ic_ifp; 586 struct rtw_softc *sc = ifp->if_softc; 587 #endif 588 589 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 590 } 591 592 static void 593 rtw_tx_kick(struct rtw_regs *regs, uint8_t ringsel) 594 { 595 uint8_t tppoll; 596 597 tppoll = RTW_READ8(regs, RTW_TPPOLL); 598 tppoll &= ~RTW_TPPOLL_SALL; 599 tppoll |= ringsel & RTW_TPPOLL_ALL; 600 RTW_WRITE8(regs, RTW_TPPOLL, tppoll); 601 RTW_SYNC(regs, RTW_TPPOLL, RTW_TPPOLL); 602 } 603 604 static void 605 rtw_key_update_end(struct ieee80211com *ic) 606 { 607 struct ifnet *ifp = ic->ic_ifp; 608 struct rtw_softc *sc = ifp->if_softc; 609 610 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 611 612 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 || 613 !device_is_active(sc->sc_dev)) 614 return; 615 616 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 617 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 618 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 619 (ifp->if_flags & IFF_RUNNING) != 0); 620 } 621 622 static bool 623 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k) 624 { 625 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 626 return false; 627 628 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) || 629 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13); 630 } 631 632 static void 633 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 634 { 635 uint8_t psr, scr; 636 int i, keylen = 0; 637 struct rtw_regs *regs; 638 union rtw_keys *rk; 639 640 regs = &sc->sc_regs; 641 rk = &sc->sc_keys; 642 643 (void)memset(rk, 0, sizeof(rk)); 644 645 /* Temporarily use software crypto for all keys. */ 646 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 647 if (wk[i].wk_cipher == &rtw_cipher_wep) 648 wk[i].wk_cipher = &ieee80211_cipher_wep; 649 } 650 651 rtw_set_access(regs, RTW_ACCESS_CONFIG); 652 653 psr = RTW_READ8(regs, RTW_PSR); 654 scr = RTW_READ8(regs, RTW_SCR); 655 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 656 657 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 658 goto out; 659 660 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 661 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i])) 662 continue; 663 if (i == txkey) { 664 keylen = wk[i].wk_keylen; 665 break; 666 } 667 keylen = MAX(keylen, wk[i].wk_keylen); 668 } 669 670 if (keylen == 5) 671 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON; 672 else if (keylen == 13) 673 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON; 674 675 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 676 if (wk[i].wk_keylen != keylen || 677 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 678 continue; 679 /* h/w will decrypt, s/w still strips headers */ 680 wk[i].wk_cipher = &rtw_cipher_wep; 681 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 682 } 683 684 out: 685 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 686 687 bus_space_write_region_stream_4(regs->r_bt, regs->r_bh, 688 RTW_DK0, rk->rk_words, __arraycount(rk->rk_words)); 689 690 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 691 BUS_SPACE_BARRIER_SYNC); 692 693 RTW_DPRINTF(RTW_DEBUG_KEY, 694 ("%s.%d: scr %02" PRIx8 ", keylen %d\n", __func__, __LINE__, scr, 695 keylen)); 696 697 RTW_WBW(regs, RTW_DK0, RTW_PSR); 698 RTW_WRITE8(regs, RTW_PSR, psr); 699 RTW_WBW(regs, RTW_PSR, RTW_SCR); 700 RTW_WRITE8(regs, RTW_SCR, scr); 701 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 702 rtw_set_access(regs, RTW_ACCESS_NONE); 703 sc->sc_flags |= RTW_F_DK_VALID; 704 } 705 706 static inline int 707 rtw_recall_eeprom(struct rtw_regs *regs, device_t dev) 708 { 709 int i; 710 uint8_t ecr; 711 712 ecr = RTW_READ8(regs, RTW_9346CR); 713 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 714 RTW_WRITE8(regs, RTW_9346CR, ecr); 715 716 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 717 718 /* wait 25ms for completion */ 719 for (i = 0; i < 250; i++) { 720 ecr = RTW_READ8(regs, RTW_9346CR); 721 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 722 RTW_DPRINTF(RTW_DEBUG_RESET, 723 ("%s: recall EEPROM in %dus\n", device_xname(dev), 724 i * 100)); 725 return 0; 726 } 727 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 728 DELAY(100); 729 } 730 aprint_error_dev(dev, "recall EEPROM failed\n"); 731 return ETIMEDOUT; 732 } 733 734 static inline int 735 rtw_reset(struct rtw_softc *sc) 736 { 737 int rc; 738 uint8_t config1; 739 740 sc->sc_flags &= ~RTW_F_DK_VALID; 741 742 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev)) != 0) 743 return rc; 744 745 rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev); 746 747 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 748 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 749 /* TBD turn off maximum power saving? */ 750 751 return 0; 752 } 753 754 static inline int 755 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 756 u_int ndescs) 757 { 758 int i, rc = 0; 759 for (i = 0; i < ndescs; i++) { 760 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 761 0, 0, &descs[i].ts_dmamap); 762 if (rc != 0) 763 break; 764 } 765 return rc; 766 } 767 768 static inline int 769 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 770 u_int ndescs) 771 { 772 int i, rc = 0; 773 for (i = 0; i < ndescs; i++) { 774 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 775 &descs[i].rs_dmamap); 776 if (rc != 0) 777 break; 778 } 779 return rc; 780 } 781 782 static inline void 783 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 784 u_int ndescs) 785 { 786 int i; 787 for (i = 0; i < ndescs; i++) { 788 if (descs[i].rs_dmamap != NULL) 789 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 790 } 791 } 792 793 static inline void 794 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 795 u_int ndescs) 796 { 797 int i; 798 for (i = 0; i < ndescs; i++) { 799 if (descs[i].ts_dmamap != NULL) 800 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 801 } 802 } 803 804 static inline void 805 rtw_srom_free(struct rtw_srom *sr) 806 { 807 sr->sr_size = 0; 808 if (sr->sr_content == NULL) 809 return; 810 free(sr->sr_content, M_DEVBUF); 811 sr->sr_content = NULL; 812 } 813 814 static void 815 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, 816 uint8_t *cs_threshold, enum rtw_rfchipid *rfchipid, uint32_t *rcr) 817 { 818 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 819 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 820 *rcr |= RTW_RCR_ENCS1; 821 *rfchipid = RTW_RFCHIPID_PHILIPS; 822 } 823 824 static int 825 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 826 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 827 device_t dev) 828 { 829 int i; 830 const char *rfname, *paname; 831 char scratch[sizeof("unknown 0xXX")]; 832 uint16_t srom_version; 833 uint8_t mac[IEEE80211_ADDR_LEN]; 834 835 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 836 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 837 838 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 839 840 if (srom_version <= 0x0101) { 841 aprint_error_dev(dev, 842 "SROM version %d.%d is not understood, " 843 "limping along with defaults\n", 844 srom_version >> 8, srom_version & 0xff); 845 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 846 return 0; 847 } else { 848 aprint_verbose_dev(dev, "SROM version %d.%d\n", 849 srom_version >> 8, srom_version & 0xff); 850 } 851 852 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 853 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 854 855 RTW_DPRINTF(RTW_DEBUG_ATTACH, 856 ("%s: EEPROM MAC %s\n", device_xname(dev), ether_sprintf(mac))); 857 858 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 859 860 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 861 *flags |= RTW_F_ANTDIV; 862 863 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 864 * to be reversed. 865 */ 866 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 867 *flags |= RTW_F_DIGPHY; 868 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 869 *flags |= RTW_F_DFLANTB; 870 871 *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), 872 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 873 874 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0) 875 *flags |= RTW_C_RXWEP_104; 876 877 *flags |= RTW_C_RXWEP_40; /* XXX */ 878 879 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 880 switch (*rfchipid) { 881 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 882 rfname = "GCT GRF5101"; 883 paname = "Winspring WS9901"; 884 break; 885 case RTW_RFCHIPID_MAXIM: 886 rfname = "Maxim MAX2820"; /* guess */ 887 paname = "Maxim MAX2422"; /* guess */ 888 break; 889 case RTW_RFCHIPID_INTERSIL: 890 rfname = "Intersil HFA3873"; /* guess */ 891 paname = "Intersil <unknown>"; 892 break; 893 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 894 rfname = "Philips SA2400A"; 895 paname = "Philips SA2411"; 896 break; 897 case RTW_RFCHIPID_RFMD: 898 /* this is the same front-end as an atw(4)! */ 899 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 900 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 901 "SYN: Silicon Labs Si4126"; /* inferred from 902 * reference driver 903 */ 904 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 905 break; 906 case RTW_RFCHIPID_RESERVED: 907 rfname = paname = "reserved"; 908 break; 909 default: 910 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 911 rfname = paname = scratch; 912 } 913 aprint_normal_dev(dev, "RF: %s, PA: %s\n", rfname, paname); 914 915 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 916 case RTW_CONFIG0_GL_USA: 917 case _RTW_CONFIG0_GL_USA: 918 *locale = RTW_LOCALE_USA; 919 break; 920 case RTW_CONFIG0_GL_EUROPE: 921 *locale = RTW_LOCALE_EUROPE; 922 break; 923 case RTW_CONFIG0_GL_JAPAN: 924 *locale = RTW_LOCALE_JAPAN; 925 break; 926 default: 927 *locale = RTW_LOCALE_UNKNOWN; 928 break; 929 } 930 return 0; 931 } 932 933 /* Returns -1 on failure. */ 934 static int 935 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 936 device_t dev) 937 { 938 int rc; 939 struct seeprom_descriptor sd; 940 uint8_t ecr; 941 942 (void)memset(&sd, 0, sizeof(sd)); 943 944 ecr = RTW_READ8(regs, RTW_9346CR); 945 946 if ((flags & RTW_F_9356SROM) != 0) { 947 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", 948 device_xname(dev))); 949 sr->sr_size = 256; 950 sd.sd_chip = C56_66; 951 } else { 952 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", 953 device_xname(dev))); 954 sr->sr_size = 128; 955 sd.sd_chip = C46; 956 } 957 958 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 959 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 960 ecr |= RTW_9346CR_EEM_PROGRAM; 961 962 RTW_WRITE8(regs, RTW_9346CR, ecr); 963 964 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 965 966 if (sr->sr_content == NULL) { 967 aprint_error_dev(dev, "unable to allocate SROM buffer\n"); 968 return ENOMEM; 969 } 970 971 (void)memset(sr->sr_content, 0, sr->sr_size); 972 973 /* RTL8180 has a single 8-bit register for controlling the 974 * 93cx6 SROM. There is no "ready" bit. The RTL8180 975 * input/output sense is the reverse of read_seeprom's. 976 */ 977 sd.sd_tag = regs->r_bt; 978 sd.sd_bsh = regs->r_bh; 979 sd.sd_regsize = 1; 980 sd.sd_control_offset = RTW_9346CR; 981 sd.sd_status_offset = RTW_9346CR; 982 sd.sd_dataout_offset = RTW_9346CR; 983 sd.sd_CK = RTW_9346CR_EESK; 984 sd.sd_CS = RTW_9346CR_EECS; 985 sd.sd_DI = RTW_9346CR_EEDO; 986 sd.sd_DO = RTW_9346CR_EEDI; 987 /* make read_seeprom enter EEPROM read/write mode */ 988 sd.sd_MS = ecr; 989 sd.sd_RDY = 0; 990 991 /* TBD bus barriers */ 992 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 993 aprint_error_dev(dev, "could not read SROM\n"); 994 free(sr->sr_content, M_DEVBUF); 995 sr->sr_content = NULL; 996 return -1; /* XXX */ 997 } 998 999 /* end EEPROM read/write mode */ 1000 RTW_WRITE8(regs, RTW_9346CR, 1001 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 1002 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 1003 1004 if ((rc = rtw_recall_eeprom(regs, dev)) != 0) 1005 return rc; 1006 1007 #ifdef RTW_DEBUG 1008 { 1009 int i; 1010 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1011 ("\n%s: serial ROM:\n\t", device_xname(dev))); 1012 for (i = 0; i < sr->sr_size/2; i++) { 1013 if (((i % 8) == 0) && (i != 0)) 1014 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 1015 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1016 (" %04x", sr->sr_content[i])); 1017 } 1018 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 1019 } 1020 #endif /* RTW_DEBUG */ 1021 return 0; 1022 } 1023 1024 static void 1025 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 1026 device_t dev) 1027 { 1028 uint8_t cfg4; 1029 const char *method; 1030 1031 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 1032 1033 switch (rfchipid) { 1034 default: 1035 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 1036 method = "fallback"; 1037 break; 1038 case RTW_RFCHIPID_INTERSIL: 1039 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1040 method = "Intersil"; 1041 break; 1042 case RTW_RFCHIPID_PHILIPS: 1043 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1044 method = "Philips"; 1045 break; 1046 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1047 case RTW_RFCHIPID_RFMD: 1048 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1049 method = "RFMD"; 1050 break; 1051 } 1052 1053 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1054 1055 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1056 1057 RTW_DPRINTF(RTW_DEBUG_INIT, 1058 ("%s: %s RF programming method, %#02x\n", device_xname(dev), method, 1059 RTW_READ8(regs, RTW_CONFIG4))); 1060 } 1061 1062 static inline void 1063 rtw_init_channels(enum rtw_locale locale, 1064 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], device_t dev) 1065 { 1066 int i; 1067 const char *name = NULL; 1068 #define ADD_CHANNEL(_chans, _chan) do { \ 1069 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1070 (*_chans)[_chan].ic_freq = \ 1071 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1072 } while (0) 1073 1074 switch (locale) { 1075 case RTW_LOCALE_USA: /* 1-11 */ 1076 name = "USA"; 1077 for (i = 1; i <= 11; i++) 1078 ADD_CHANNEL(chans, i); 1079 break; 1080 case RTW_LOCALE_JAPAN: /* 1-14 */ 1081 name = "Japan"; 1082 ADD_CHANNEL(chans, 14); 1083 for (i = 1; i <= 14; i++) 1084 ADD_CHANNEL(chans, i); 1085 break; 1086 case RTW_LOCALE_EUROPE: /* 1-13 */ 1087 name = "Europe"; 1088 for (i = 1; i <= 13; i++) 1089 ADD_CHANNEL(chans, i); 1090 break; 1091 default: /* 10-11 allowed by most countries */ 1092 name = "<unknown>"; 1093 for (i = 10; i <= 11; i++) 1094 ADD_CHANNEL(chans, i); 1095 break; 1096 } 1097 aprint_normal_dev(dev, "Geographic Location %s\n", name); 1098 #undef ADD_CHANNEL 1099 } 1100 1101 1102 static inline void 1103 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale) 1104 { 1105 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1106 1107 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1108 case RTW_CONFIG0_GL_USA: 1109 case _RTW_CONFIG0_GL_USA: 1110 *locale = RTW_LOCALE_USA; 1111 break; 1112 case RTW_CONFIG0_GL_JAPAN: 1113 *locale = RTW_LOCALE_JAPAN; 1114 break; 1115 case RTW_CONFIG0_GL_EUROPE: 1116 *locale = RTW_LOCALE_EUROPE; 1117 break; 1118 default: 1119 *locale = RTW_LOCALE_UNKNOWN; 1120 break; 1121 } 1122 } 1123 1124 static inline int 1125 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1126 device_t dev) 1127 { 1128 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1129 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1130 }; 1131 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1132 idr1 = RTW_READ(regs, RTW_IDR1); 1133 1134 (*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7)); 1135 (*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15)); 1136 (*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23)); 1137 (*addr)[3] = __SHIFTOUT(idr0, __BITS(24 ,31)); 1138 1139 (*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7)); 1140 (*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15)); 1141 1142 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1143 aprint_error_dev(dev, 1144 "could not get mac address, attach failed\n"); 1145 return ENXIO; 1146 } 1147 1148 aprint_normal_dev(dev, "802.11 address %s\n", ether_sprintf(*addr)); 1149 1150 return 0; 1151 } 1152 1153 static uint8_t 1154 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1155 struct ieee80211_channel *chan) 1156 { 1157 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1158 KASSERT(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14); 1159 return RTW_SR_GET(sr, idx); 1160 } 1161 1162 static void 1163 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1164 { 1165 int pri; 1166 /* nfree: the number of free descriptors in each ring. 1167 * The beacon ring is a special case: I do not let the 1168 * driver use all of the descriptors on the beacon ring. 1169 * The reasons are two-fold: 1170 * 1171 * (1) A BEACON descriptor's OWN bit is (apparently) not 1172 * updated, so the driver cannot easily know if the descriptor 1173 * belongs to it, or if it is racing the NIC. If the NIC 1174 * does not OWN every descriptor, then the driver can safely 1175 * update the descriptors when RTW_TBDA points at tdb_next. 1176 * 1177 * (2) I hope that the NIC will process more than one BEACON 1178 * descriptor in a single beacon interval, since that will 1179 * enable multiple-BSS support. Since the NIC does not 1180 * clear the OWN bit, there is no natural place for it to 1181 * stop processing BEACON desciptors. Maybe it will *not* 1182 * stop processing them! I do not want to chance the NIC 1183 * looping around and around a saturated beacon ring, so 1184 * I will leave one descriptor unOWNed at all times. 1185 */ 1186 u_int nfree[RTW_NTXPRI] = 1187 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, 1188 RTW_NTXDESCBCN - 1}; 1189 1190 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1191 tdb[pri].tdb_nfree = nfree[pri]; 1192 tdb[pri].tdb_next = 0; 1193 } 1194 } 1195 1196 static int 1197 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1198 { 1199 int i; 1200 struct rtw_txsoft *ts; 1201 1202 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1203 SIMPLEQ_INIT(&tsb->tsb_freeq); 1204 for (i = 0; i < tsb->tsb_ndesc; i++) { 1205 ts = &tsb->tsb_desc[i]; 1206 ts->ts_mbuf = NULL; 1207 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1208 } 1209 tsb->tsb_tx_timer = 0; 1210 return 0; 1211 } 1212 1213 static void 1214 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1215 { 1216 int pri; 1217 for (pri = 0; pri < RTW_NTXPRI; pri++) 1218 rtw_txsoft_blk_init(&tsb[pri]); 1219 } 1220 1221 static inline void 1222 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1223 { 1224 KASSERT(nsync <= rdb->rdb_ndesc); 1225 /* sync to end of ring */ 1226 if (desc0 + nsync > rdb->rdb_ndesc) { 1227 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1228 offsetof(struct rtw_descs, hd_rx[desc0]), 1229 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1230 nsync -= (rdb->rdb_ndesc - desc0); 1231 desc0 = 0; 1232 } 1233 1234 KASSERT(desc0 < rdb->rdb_ndesc); 1235 KASSERT(nsync <= rdb->rdb_ndesc); 1236 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1237 1238 /* sync what remains */ 1239 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1240 offsetof(struct rtw_descs, hd_rx[desc0]), 1241 sizeof(struct rtw_rxdesc) * nsync, ops); 1242 } 1243 1244 static void 1245 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1246 { 1247 /* sync to end of ring */ 1248 if (desc0 + nsync > tdb->tdb_ndesc) { 1249 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1250 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1251 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1252 ops); 1253 nsync -= (tdb->tdb_ndesc - desc0); 1254 desc0 = 0; 1255 } 1256 1257 /* sync what remains */ 1258 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1259 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1260 sizeof(struct rtw_txdesc) * nsync, ops); 1261 } 1262 1263 static void 1264 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1265 { 1266 int pri; 1267 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1268 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1269 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1270 } 1271 } 1272 1273 static void 1274 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1275 { 1276 int i; 1277 struct rtw_rxsoft *rs; 1278 1279 for (i = 0; i < RTW_RXQLEN; i++) { 1280 rs = &desc[i]; 1281 if (rs->rs_mbuf == NULL) 1282 continue; 1283 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1284 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1285 bus_dmamap_unload(dmat, rs->rs_dmamap); 1286 m_freem(rs->rs_mbuf); 1287 rs->rs_mbuf = NULL; 1288 } 1289 } 1290 1291 static inline int 1292 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1293 { 1294 int rc; 1295 struct mbuf *m; 1296 1297 MGETHDR(m, M_DONTWAIT, MT_DATA); 1298 if (m == NULL) 1299 return ENOBUFS; 1300 1301 MCLGET(m, M_DONTWAIT); 1302 if ((m->m_flags & M_EXT) == 0) { 1303 m_freem(m); 1304 return ENOBUFS; 1305 } 1306 1307 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1308 1309 if (rs->rs_mbuf != NULL) 1310 bus_dmamap_unload(dmat, rs->rs_dmamap); 1311 1312 rs->rs_mbuf = NULL; 1313 1314 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1315 if (rc != 0) { 1316 m_freem(m); 1317 return -1; 1318 } 1319 1320 rs->rs_mbuf = m; 1321 1322 return 0; 1323 } 1324 1325 static int 1326 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1327 int *ndesc, device_t dev) 1328 { 1329 int i, rc = 0; 1330 struct rtw_rxsoft *rs; 1331 1332 for (i = 0; i < RTW_RXQLEN; i++) { 1333 rs = &desc[i]; 1334 /* we're in rtw_init, so there should be no mbufs allocated */ 1335 KASSERT(rs->rs_mbuf == NULL); 1336 #ifdef RTW_DEBUG 1337 if (i == rtw_rxbufs_limit) { 1338 aprint_error_dev(dev, "TEST hit %d-buffer limit\n", i); 1339 rc = ENOBUFS; 1340 break; 1341 } 1342 #endif /* RTW_DEBUG */ 1343 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1344 aprint_error_dev(dev, 1345 "rtw_rxsoft_alloc failed, %d buffers, rc %d\n", 1346 i, rc); 1347 break; 1348 } 1349 } 1350 *ndesc = i; 1351 return rc; 1352 } 1353 1354 static inline void 1355 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1356 int idx, int kick) 1357 { 1358 int is_last = (idx == rdb->rdb_ndesc - 1); 1359 uint32_t ctl, octl, obuf; 1360 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1361 1362 /* sync the mbuf before the descriptor */ 1363 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1364 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1365 1366 obuf = rd->rd_buf; 1367 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1368 1369 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1370 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1371 1372 if (is_last) 1373 ctl |= RTW_RXCTL_EOR; 1374 1375 octl = rd->rd_ctl; 1376 rd->rd_ctl = htole32(ctl); 1377 1378 RTW_DPRINTF( 1379 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1380 : RTW_DEBUG_RECV_DESC, 1381 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1382 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1383 le32toh(rd->rd_ctl))); 1384 1385 /* sync the descriptor */ 1386 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1387 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1388 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1389 } 1390 1391 static void 1392 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1393 { 1394 int i; 1395 struct rtw_rxdesc *rd; 1396 struct rtw_rxsoft *rs; 1397 1398 for (i = 0; i < rdb->rdb_ndesc; i++) { 1399 rd = &rdb->rdb_desc[i]; 1400 rs = &ctl[i]; 1401 rtw_rxdesc_init(rdb, rs, i, kick); 1402 } 1403 } 1404 1405 static void 1406 rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable) 1407 { 1408 struct rtw_regs *regs = &sc->sc_regs; 1409 uint8_t cr; 1410 1411 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1412 enable ? "enable" : "disable", flags)); 1413 1414 cr = RTW_READ8(regs, RTW_CR); 1415 1416 /* XXX reference source does not enable MULRW */ 1417 /* enable PCI Read/Write Multiple */ 1418 cr |= RTW_CR_MULRW; 1419 1420 /* The receive engine will always start at RDSAR. */ 1421 if (enable && (flags & ~cr & RTW_CR_RE)) { 1422 struct rtw_rxdesc_blk *rdb; 1423 rdb = &sc->sc_rxdesc_blk; 1424 rdb->rdb_next = 0; 1425 } 1426 1427 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1428 if (enable) 1429 cr |= flags; 1430 else 1431 cr &= ~flags; 1432 RTW_WRITE8(regs, RTW_CR, cr); 1433 RTW_SYNC(regs, RTW_CR, RTW_CR); 1434 1435 #ifdef RTW_DIAG 1436 if (cr & RTW_CR_TE) 1437 rtw_txring_fixup(sc, __func__, __LINE__); 1438 #endif 1439 if (cr & RTW_CR_TE) { 1440 rtw_tx_kick(&sc->sc_regs, 1441 RTW_TPPOLL_HPQ | RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ); 1442 } 1443 } 1444 1445 static void 1446 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1447 { 1448 #define IS_BEACON(__fc0) \ 1449 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1450 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1451 1452 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1453 * hardware -> net80211 1454 */ 1455 u_int next, nproc = 0; 1456 int hwrate, len, rate, rssi, sq; 1457 uint32_t hrssi, hstat, htsfth, htsftl; 1458 struct rtw_rxdesc *rd; 1459 struct rtw_rxsoft *rs; 1460 struct rtw_rxdesc_blk *rdb; 1461 struct mbuf *m; 1462 struct ifnet *ifp = &sc->sc_if; 1463 1464 struct ieee80211_node *ni; 1465 struct ieee80211_frame_min *wh; 1466 1467 rdb = &sc->sc_rxdesc_blk; 1468 1469 for (next = rdb->rdb_next; ; next = rdb->rdb_next) { 1470 KASSERT(next < rdb->rdb_ndesc); 1471 1472 rtw_rxdescs_sync(rdb, next, 1, 1473 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1474 rd = &rdb->rdb_desc[next]; 1475 rs = &sc->sc_rxsoft[next]; 1476 1477 hstat = le32toh(rd->rd_stat); 1478 hrssi = le32toh(rd->rd_rssi); 1479 htsfth = le32toh(rd->rd_tsfth); 1480 htsftl = le32toh(rd->rd_tsftl); 1481 1482 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1483 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1484 __func__, next, hstat, hrssi, htsfth, htsftl)); 1485 1486 ++nproc; 1487 1488 /* still belongs to NIC */ 1489 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1490 rtw_rxdescs_sync(rdb, next, 1, BUS_DMASYNC_PREREAD); 1491 break; 1492 } 1493 1494 /* ieee80211_input() might reset the receive engine 1495 * (e.g. by indirectly calling rtw_tune()), so save 1496 * the next pointer here and retrieve it again on 1497 * the next round. 1498 */ 1499 rdb->rdb_next = (next + 1) % rdb->rdb_ndesc; 1500 1501 #ifdef RTW_DEBUG 1502 #define PRINTSTAT(flag) do { \ 1503 if ((hstat & flag) != 0) { \ 1504 printf("%s" #flag, delim); \ 1505 delim = ","; \ 1506 } \ 1507 } while (0) 1508 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1509 const char *delim = "<"; 1510 printf("%s: ", device_xname(sc->sc_dev)); 1511 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1512 printf("status %08x", hstat); 1513 PRINTSTAT(RTW_RXSTAT_SPLCP); 1514 PRINTSTAT(RTW_RXSTAT_MAR); 1515 PRINTSTAT(RTW_RXSTAT_PAR); 1516 PRINTSTAT(RTW_RXSTAT_BAR); 1517 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1518 PRINTSTAT(RTW_RXSTAT_CRC32); 1519 PRINTSTAT(RTW_RXSTAT_ICV); 1520 printf(">, "); 1521 } 1522 } 1523 #endif /* RTW_DEBUG */ 1524 1525 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1526 aprint_error_dev(sc->sc_dev, 1527 "DMA error/FIFO overflow %08" PRIx32 ", " 1528 "rx descriptor %d\n", hstat, next); 1529 ifp->if_ierrors++; 1530 goto next; 1531 } 1532 1533 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); 1534 if (len < IEEE80211_MIN_LEN) { 1535 sc->sc_ic.ic_stats.is_rx_tooshort++; 1536 goto next; 1537 } 1538 if (len > rs->rs_mbuf->m_len) { 1539 aprint_error_dev(sc->sc_dev, 1540 "rx frame too long, %d > %d, %08" PRIx32 1541 ", desc %d\n", 1542 len, rs->rs_mbuf->m_len, hstat, next); 1543 ifp->if_ierrors++; 1544 goto next; 1545 } 1546 1547 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); 1548 if (hwrate >= __arraycount(ratetbl)) { 1549 aprint_error_dev(sc->sc_dev, 1550 "unknown rate #%" __PRIuBITS "\n", 1551 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); 1552 ifp->if_ierrors++; 1553 goto next; 1554 } 1555 rate = ratetbl[hwrate]; 1556 1557 #ifdef RTW_DEBUG 1558 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1559 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1560 (rate * 5) % 10, htsfth, htsftl)); 1561 #endif /* RTW_DEBUG */ 1562 1563 /* if bad flags, skip descriptor */ 1564 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1565 aprint_error_dev(sc->sc_dev, "too many rx segments, " 1566 "next=%d, %08" PRIx32 "\n", next, hstat); 1567 goto next; 1568 } 1569 1570 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1571 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1572 1573 m = rs->rs_mbuf; 1574 1575 /* if temporarily out of memory, re-use mbuf */ 1576 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1577 case 0: 1578 break; 1579 case ENOBUFS: 1580 aprint_error_dev(sc->sc_dev, 1581 "rtw_rxsoft_alloc(, %d) failed, dropping packet\n", 1582 next); 1583 goto next; 1584 default: 1585 /* XXX shorten rx ring, instead? */ 1586 aprint_error_dev(sc->sc_dev, 1587 "could not load DMA map\n"); 1588 } 1589 1590 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ); 1591 1592 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1593 rssi = UINT8_MAX - sq; 1594 else { 1595 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); 1596 /* TBD find out each front-end's LNA gain in the 1597 * front-end's units 1598 */ 1599 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1600 rssi |= 0x80; 1601 } 1602 1603 /* Note well: now we cannot recycle the rs_mbuf unless 1604 * we restore its original length. 1605 */ 1606 m->m_pkthdr.rcvif = ifp; 1607 m->m_pkthdr.len = m->m_len = len; 1608 1609 wh = mtod(m, struct ieee80211_frame_min *); 1610 1611 if (!IS_BEACON(wh->i_fc[0])) 1612 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1613 1614 sc->sc_tsfth = htsfth; 1615 1616 #ifdef RTW_DEBUG 1617 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 1618 (IFF_DEBUG|IFF_LINK2)) { 1619 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1620 rate, rssi); 1621 } 1622 #endif /* RTW_DEBUG */ 1623 1624 if (sc->sc_radiobpf != NULL) { 1625 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1626 1627 rr->rr_tsft = 1628 htole64(((uint64_t)htsfth << 32) | htsftl); 1629 1630 rr->rr_flags = IEEE80211_RADIOTAP_F_FCS; 1631 1632 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1633 rr->rr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1634 if ((hstat & RTW_RXSTAT_CRC32) != 0) 1635 rr->rr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 1636 1637 rr->rr_rate = rate; 1638 1639 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1640 rr->rr_u.u_philips.p_antsignal = rssi; 1641 else { 1642 rr->rr_u.u_other.o_antsignal = rssi; 1643 rr->rr_u.u_other.o_barker_lock = 1644 htole16(UINT8_MAX - sq); 1645 } 1646 1647 bpf_mtap2(sc->sc_radiobpf, 1648 rr, sizeof(sc->sc_rxtapu), m); 1649 } 1650 1651 if ((hstat & RTW_RXSTAT_RES) != 0) { 1652 m_freem(m); 1653 goto next; 1654 } 1655 1656 /* CRC is included with the packet; trim it off. */ 1657 m_adj(m, -IEEE80211_CRC_LEN); 1658 1659 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1660 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1661 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1662 ieee80211_free_node(ni); 1663 next: 1664 rtw_rxdesc_init(rdb, rs, next, 0); 1665 } 1666 #undef IS_BEACON 1667 } 1668 1669 static void 1670 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1671 struct rtw_txsoft *ts) 1672 { 1673 struct mbuf *m; 1674 struct ieee80211_node *ni; 1675 1676 m = ts->ts_mbuf; 1677 ni = ts->ts_ni; 1678 KASSERT(m != NULL); 1679 KASSERT(ni != NULL); 1680 ts->ts_mbuf = NULL; 1681 ts->ts_ni = NULL; 1682 1683 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1684 BUS_DMASYNC_POSTWRITE); 1685 bus_dmamap_unload(dmat, ts->ts_dmamap); 1686 m_freem(m); 1687 ieee80211_free_node(ni); 1688 } 1689 1690 static void 1691 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1692 struct rtw_txsoft_blk *tsb) 1693 { 1694 struct rtw_txsoft *ts; 1695 1696 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1697 rtw_txsoft_release(dmat, ic, ts); 1698 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1699 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1700 } 1701 tsb->tsb_tx_timer = 0; 1702 } 1703 1704 static inline void 1705 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1706 struct rtw_txsoft *ts, int ndesc) 1707 { 1708 uint32_t hstat; 1709 int data_retry, rts_retry; 1710 struct rtw_txdesc *tdn; 1711 const char *condstring; 1712 struct ifnet *ifp = &sc->sc_if; 1713 1714 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1715 1716 tdb->tdb_nfree += ndesc; 1717 1718 tdn = &tdb->tdb_desc[ts->ts_last]; 1719 1720 hstat = le32toh(tdn->td_stat); 1721 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1722 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); 1723 1724 ifp->if_collisions += rts_retry + data_retry; 1725 1726 if ((hstat & RTW_TXSTAT_TOK) != 0) 1727 condstring = "ok"; 1728 else { 1729 ifp->if_oerrors++; 1730 condstring = "error"; 1731 } 1732 1733 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1734 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1735 device_xname(sc->sc_dev), ts, ts->ts_first, ts->ts_last, 1736 condstring, rts_retry, data_retry)); 1737 } 1738 1739 static void 1740 rtw_reset_oactive(struct rtw_softc *sc) 1741 { 1742 short oflags; 1743 int pri; 1744 struct rtw_txsoft_blk *tsb; 1745 struct rtw_txdesc_blk *tdb; 1746 oflags = sc->sc_if.if_flags; 1747 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1748 tsb = &sc->sc_txsoft_blk[pri]; 1749 tdb = &sc->sc_txdesc_blk[pri]; 1750 if (!SIMPLEQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0) 1751 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1752 } 1753 if (oflags != sc->sc_if.if_flags) { 1754 DPRINTF(sc, RTW_DEBUG_OACTIVE, 1755 ("%s: reset OACTIVE\n", __func__)); 1756 } 1757 } 1758 1759 /* Collect transmitted packets. */ 1760 static bool 1761 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1762 struct rtw_txdesc_blk *tdb, int force) 1763 { 1764 bool collected = false; 1765 int ndesc; 1766 struct rtw_txsoft *ts; 1767 1768 #ifdef RTW_DEBUG 1769 rtw_dump_rings(sc); 1770 #endif 1771 1772 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1773 /* If we're clearing a failed transmission, only clear 1774 up to the last packet the hardware has processed. */ 1775 if (ts->ts_first == rtw_txring_next(&sc->sc_regs, tdb)) 1776 break; 1777 1778 ndesc = 1 + ts->ts_last - ts->ts_first; 1779 if (ts->ts_last < ts->ts_first) 1780 ndesc += tdb->tdb_ndesc; 1781 1782 KASSERT(ndesc > 0); 1783 1784 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1785 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1786 1787 if (force) { 1788 int next; 1789 #ifdef RTW_DIAG 1790 printf("%s: clearing packet, stats", __func__); 1791 #endif 1792 for (next = ts->ts_first; ; 1793 next = RTW_NEXT_IDX(tdb, next)) { 1794 #ifdef RTW_DIAG 1795 printf(" %" PRIx32 "/%" PRIx32 "/%" PRIx32 "/%" PRIu32 "/%" PRIx32, le32toh(tdb->tdb_desc[next].td_stat), le32toh(tdb->tdb_desc[next].td_ctl1), le32toh(tdb->tdb_desc[next].td_buf), le32toh(tdb->tdb_desc[next].td_len), le32toh(tdb->tdb_desc[next].td_next)); 1796 #endif 1797 tdb->tdb_desc[next].td_stat &= 1798 ~htole32(RTW_TXSTAT_OWN); 1799 if (next == ts->ts_last) 1800 break; 1801 } 1802 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1803 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1804 #ifdef RTW_DIAG 1805 next = RTW_NEXT_IDX(tdb, next); 1806 printf(" -> end %u stat %" PRIx32 ", was %u\n", next, 1807 le32toh(tdb->tdb_desc[next].td_stat), 1808 rtw_txring_next(&sc->sc_regs, tdb)); 1809 #endif 1810 } else if ((tdb->tdb_desc[ts->ts_last].td_stat & 1811 htole32(RTW_TXSTAT_OWN)) != 0) { 1812 rtw_txdescs_sync(tdb, ts->ts_last, 1, 1813 BUS_DMASYNC_PREREAD); 1814 break; 1815 } 1816 1817 collected = true; 1818 1819 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1820 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1821 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1822 } 1823 1824 /* no more pending transmissions, cancel watchdog */ 1825 if (ts == NULL) 1826 tsb->tsb_tx_timer = 0; 1827 rtw_reset_oactive(sc); 1828 1829 return collected; 1830 } 1831 1832 static void 1833 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1834 { 1835 int pri; 1836 struct rtw_txsoft_blk *tsb; 1837 struct rtw_txdesc_blk *tdb; 1838 struct ifnet *ifp = &sc->sc_if; 1839 1840 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1841 tsb = &sc->sc_txsoft_blk[pri]; 1842 tdb = &sc->sc_txdesc_blk[pri]; 1843 rtw_collect_txring(sc, tsb, tdb, 0); 1844 } 1845 1846 if ((isr & RTW_INTR_TX) != 0) 1847 rtw_start(ifp); 1848 1849 return; 1850 } 1851 1852 static void 1853 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1854 { 1855 u_int next; 1856 uint32_t tsfth, tsftl; 1857 struct ieee80211com *ic; 1858 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN]; 1859 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN]; 1860 struct mbuf *m; 1861 1862 tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH); 1863 tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1864 1865 if ((isr & (RTW_INTR_TBDOK|RTW_INTR_TBDER)) != 0) { 1866 next = rtw_txring_next(&sc->sc_regs, tdb); 1867 RTW_DPRINTF(RTW_DEBUG_BEACON, 1868 ("%s: beacon ring %sprocessed, isr = %#04" PRIx16 1869 ", next %u expected %u, %" PRIu64 "\n", __func__, 1870 (next == tdb->tdb_next) ? "" : "un", isr, next, 1871 tdb->tdb_next, (uint64_t)tsfth << 32 | tsftl)); 1872 if ((RTW_READ8(&sc->sc_regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0) 1873 rtw_collect_txring(sc, tsb, tdb, 1); 1874 } 1875 /* Start beacon transmission. */ 1876 1877 if ((isr & RTW_INTR_BCNINT) != 0 && 1878 sc->sc_ic.ic_state == IEEE80211_S_RUN && 1879 SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) { 1880 RTW_DPRINTF(RTW_DEBUG_BEACON, 1881 ("%s: beacon prep. time, isr = %#04" PRIx16 1882 ", %16" PRIu64 "\n", __func__, isr, 1883 (uint64_t)tsfth << 32 | tsftl)); 1884 ic = &sc->sc_ic; 1885 m = rtw_beacon_alloc(sc, ic->ic_bss); 1886 1887 if (m == NULL) { 1888 aprint_error_dev(sc->sc_dev, 1889 "could not allocate beacon\n"); 1890 return; 1891 } 1892 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss); 1893 IF_ENQUEUE(&sc->sc_beaconq, m); 1894 rtw_start(&sc->sc_if); 1895 } 1896 } 1897 1898 static void 1899 rtw_intr_atim(struct rtw_softc *sc) 1900 { 1901 /* TBD */ 1902 return; 1903 } 1904 1905 #ifdef RTW_DEBUG 1906 static void 1907 rtw_dump_rings(struct rtw_softc *sc) 1908 { 1909 struct rtw_txdesc_blk *tdb; 1910 struct rtw_rxdesc *rd; 1911 struct rtw_rxdesc_blk *rdb; 1912 int desc, pri; 1913 1914 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1915 return; 1916 1917 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1918 tdb = &sc->sc_txdesc_blk[pri]; 1919 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1920 tdb->tdb_ndesc, tdb->tdb_nfree); 1921 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1922 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1923 } 1924 1925 rdb = &sc->sc_rxdesc_blk; 1926 1927 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1928 rd = &rdb->rdb_desc[desc]; 1929 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1930 "rsvd1/tsfth %08x\n", __func__, 1931 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1932 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1933 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1934 } 1935 } 1936 #endif /* RTW_DEBUG */ 1937 1938 static void 1939 rtw_hwring_setup(struct rtw_softc *sc) 1940 { 1941 int pri; 1942 struct rtw_regs *regs = &sc->sc_regs; 1943 struct rtw_txdesc_blk *tdb; 1944 1945 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_basereg = RTW_TLPDA; 1946 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_base = RTW_RING_BASE(sc, hd_txlo); 1947 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_basereg = RTW_TNPDA; 1948 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_base = RTW_RING_BASE(sc, hd_txmd); 1949 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_basereg = RTW_THPDA; 1950 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_base = RTW_RING_BASE(sc, hd_txhi); 1951 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_basereg = RTW_TBDA; 1952 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_base = RTW_RING_BASE(sc, hd_bcn); 1953 1954 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1955 tdb = &sc->sc_txdesc_blk[pri]; 1956 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base); 1957 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1958 ("%s: reg[tdb->tdb_basereg] <- %" PRIxPTR "\n", __func__, 1959 (uintptr_t)tdb->tdb_base)); 1960 } 1961 1962 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1963 1964 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1965 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1966 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1967 1968 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1969 1970 } 1971 1972 static int 1973 rtw_swring_setup(struct rtw_softc *sc) 1974 { 1975 int rc; 1976 struct rtw_rxdesc_blk *rdb; 1977 1978 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1979 1980 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1981 1982 rdb = &sc->sc_rxdesc_blk; 1983 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1984 sc->sc_dev)) != 0 && rdb->rdb_ndesc == 0) { 1985 aprint_error_dev(sc->sc_dev, "could not allocate rx buffers\n"); 1986 return rc; 1987 } 1988 1989 rdb = &sc->sc_rxdesc_blk; 1990 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1991 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1992 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1993 rdb->rdb_next = 0; 1994 1995 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1996 return 0; 1997 } 1998 1999 static void 2000 rtw_txdesc_blk_init(struct rtw_txdesc_blk *tdb) 2001 { 2002 int i; 2003 2004 (void)memset(tdb->tdb_desc, 0, 2005 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 2006 for (i = 0; i < tdb->tdb_ndesc; i++) 2007 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 2008 } 2009 2010 static u_int 2011 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb) 2012 { 2013 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) / 2014 sizeof(struct rtw_txdesc); 2015 } 2016 2017 #ifdef RTW_DIAG 2018 static void 2019 rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln) 2020 { 2021 int pri; 2022 u_int next; 2023 struct rtw_txdesc_blk *tdb; 2024 struct rtw_regs *regs = &sc->sc_regs; 2025 2026 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2027 int i; 2028 tdb = &sc->sc_txdesc_blk[pri]; 2029 next = rtw_txring_next(regs, tdb); 2030 if (tdb->tdb_next == next) 2031 continue; 2032 for (i = 0; next != tdb->tdb_next; 2033 next = RTW_NEXT_IDX(tdb, next), i++) { 2034 if ((tdb->tdb_desc[next].td_stat & htole32(RTW_TXSTAT_OWN)) == 0) 2035 break; 2036 } 2037 printf("%s:%d: tx-ring %d expected next %u, read %u+%d -> %s\n", fn, 2038 ln, pri, tdb->tdb_next, next, i, tdb->tdb_next == next ? "okay" : "BAD"); 2039 if (tdb->tdb_next == next) 2040 continue; 2041 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1); 2042 } 2043 } 2044 #endif 2045 2046 static void 2047 rtw_txdescs_reset(struct rtw_softc *sc) 2048 { 2049 int pri; 2050 struct rtw_txsoft_blk *tsb; 2051 struct rtw_txdesc_blk *tdb; 2052 2053 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2054 tsb = &sc->sc_txsoft_blk[pri]; 2055 tdb = &sc->sc_txdesc_blk[pri]; 2056 rtw_collect_txring(sc, tsb, tdb, 1); 2057 #ifdef RTW_DIAG 2058 if (!SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 2059 printf("%s: packets left in ring %d\n", __func__, pri); 2060 #endif 2061 } 2062 } 2063 2064 static void 2065 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 2066 { 2067 aprint_error_dev(sc->sc_dev, "tx fifo underflow\n"); 2068 2069 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: cleaning up xmit, isr %" PRIx16 2070 "\n", device_xname(sc->sc_dev), isr)); 2071 2072 #ifdef RTW_DEBUG 2073 rtw_dump_rings(sc); 2074 #endif /* RTW_DEBUG */ 2075 2076 /* Collect tx'd packets. XXX let's hope this stops the transmit 2077 * timeouts. 2078 */ 2079 rtw_txdescs_reset(sc); 2080 2081 #ifdef RTW_DEBUG 2082 rtw_dump_rings(sc); 2083 #endif /* RTW_DEBUG */ 2084 } 2085 2086 static inline void 2087 rtw_suspend_ticks(struct rtw_softc *sc) 2088 { 2089 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2090 ("%s: suspending ticks\n", device_xname(sc->sc_dev))); 2091 sc->sc_do_tick = 0; 2092 } 2093 2094 static inline void 2095 rtw_resume_ticks(struct rtw_softc *sc) 2096 { 2097 uint32_t tsftrl0, tsftrl1, next_tint; 2098 2099 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2100 2101 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2102 next_tint = tsftrl1 + 1000000; 2103 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tint); 2104 2105 sc->sc_do_tick = 1; 2106 2107 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2108 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 2109 device_xname(sc->sc_dev), tsftrl1 - tsftrl0, tsftrl1, next_tint)); 2110 } 2111 2112 static void 2113 rtw_intr_timeout(struct rtw_softc *sc) 2114 { 2115 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", device_xname(sc->sc_dev))); 2116 if (sc->sc_do_tick) 2117 rtw_resume_ticks(sc); 2118 return; 2119 } 2120 2121 int 2122 rtw_intr(void *arg) 2123 { 2124 int i; 2125 struct rtw_softc *sc = arg; 2126 struct rtw_regs *regs = &sc->sc_regs; 2127 uint16_t isr; 2128 struct ifnet *ifp = &sc->sc_if; 2129 2130 /* 2131 * If the interface isn't running, the interrupt couldn't 2132 * possibly have come from us. 2133 */ 2134 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2135 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) { 2136 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", 2137 device_xname(sc->sc_dev))); 2138 return (0); 2139 } 2140 2141 for (i = 0; i < 10; i++) { 2142 isr = RTW_READ16(regs, RTW_ISR); 2143 2144 RTW_WRITE16(regs, RTW_ISR, isr); 2145 RTW_WBR(regs, RTW_ISR, RTW_ISR); 2146 2147 if (sc->sc_intr_ack != NULL) 2148 (*sc->sc_intr_ack)(regs); 2149 2150 if (isr == 0) 2151 break; 2152 2153 #ifdef RTW_DEBUG 2154 #define PRINTINTR(flag) do { \ 2155 if ((isr & flag) != 0) { \ 2156 printf("%s" #flag, delim); \ 2157 delim = ","; \ 2158 } \ 2159 } while (0) 2160 2161 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 2162 const char *delim = "<"; 2163 2164 printf("%s: reg[ISR] = %x", device_xname(sc->sc_dev), 2165 isr); 2166 2167 PRINTINTR(RTW_INTR_TXFOVW); 2168 PRINTINTR(RTW_INTR_TIMEOUT); 2169 PRINTINTR(RTW_INTR_BCNINT); 2170 PRINTINTR(RTW_INTR_ATIMINT); 2171 PRINTINTR(RTW_INTR_TBDER); 2172 PRINTINTR(RTW_INTR_TBDOK); 2173 PRINTINTR(RTW_INTR_THPDER); 2174 PRINTINTR(RTW_INTR_THPDOK); 2175 PRINTINTR(RTW_INTR_TNPDER); 2176 PRINTINTR(RTW_INTR_TNPDOK); 2177 PRINTINTR(RTW_INTR_RXFOVW); 2178 PRINTINTR(RTW_INTR_RDU); 2179 PRINTINTR(RTW_INTR_TLPDER); 2180 PRINTINTR(RTW_INTR_TLPDOK); 2181 PRINTINTR(RTW_INTR_RER); 2182 PRINTINTR(RTW_INTR_ROK); 2183 2184 printf(">\n"); 2185 } 2186 #undef PRINTINTR 2187 #endif /* RTW_DEBUG */ 2188 2189 if ((isr & RTW_INTR_RX) != 0) 2190 rtw_intr_rx(sc, isr); 2191 if ((isr & RTW_INTR_TX) != 0) 2192 rtw_intr_tx(sc, isr); 2193 if ((isr & RTW_INTR_BEACON) != 0) 2194 rtw_intr_beacon(sc, isr); 2195 if ((isr & RTW_INTR_ATIMINT) != 0) 2196 rtw_intr_atim(sc); 2197 if ((isr & RTW_INTR_IOERROR) != 0) 2198 rtw_intr_ioerror(sc, isr); 2199 if ((isr & RTW_INTR_TIMEOUT) != 0) 2200 rtw_intr_timeout(sc); 2201 } 2202 2203 return 1; 2204 } 2205 2206 /* Must be called at splnet. */ 2207 static void 2208 rtw_stop(struct ifnet *ifp, int disable) 2209 { 2210 int pri; 2211 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2212 struct ieee80211com *ic = &sc->sc_ic; 2213 struct rtw_regs *regs = &sc->sc_regs; 2214 2215 rtw_suspend_ticks(sc); 2216 2217 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2218 2219 if (device_has_power(sc->sc_dev)) { 2220 /* Disable interrupts. */ 2221 RTW_WRITE16(regs, RTW_IMR, 0); 2222 2223 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2224 2225 /* Stop the transmit and receive processes. First stop DMA, 2226 * then disable receiver and transmitter. 2227 */ 2228 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2229 2230 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2231 2232 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2233 } 2234 2235 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2236 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2237 &sc->sc_txsoft_blk[pri]); 2238 } 2239 2240 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2241 2242 /* Mark the interface as not running. Cancel the watchdog timer. */ 2243 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2244 ifp->if_timer = 0; 2245 2246 if (disable) 2247 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 2248 2249 return; 2250 } 2251 2252 const char * 2253 rtw_pwrstate_string(enum rtw_pwrstate power) 2254 { 2255 switch (power) { 2256 case RTW_ON: 2257 return "on"; 2258 case RTW_SLEEP: 2259 return "sleep"; 2260 case RTW_OFF: 2261 return "off"; 2262 default: 2263 return "unknown"; 2264 } 2265 } 2266 2267 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2268 * reference driver, plus a magic Maxim "ON" value that comes from 2269 * the Realtek document "Windows PG for Rtl8180." 2270 */ 2271 static void 2272 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2273 int before_rf, int digphy) 2274 { 2275 uint32_t anaparm; 2276 2277 anaparm = RTW_READ(regs, RTW_ANAPARM); 2278 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2279 2280 switch (power) { 2281 case RTW_OFF: 2282 if (before_rf) 2283 return; 2284 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2285 anaparm |= RTW_ANAPARM_TXDACOFF; 2286 break; 2287 case RTW_SLEEP: 2288 if (!before_rf) 2289 return; 2290 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2291 anaparm |= RTW_ANAPARM_TXDACOFF; 2292 break; 2293 case RTW_ON: 2294 if (!before_rf) 2295 return; 2296 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2297 break; 2298 } 2299 RTW_DPRINTF(RTW_DEBUG_PWR, 2300 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2301 __func__, rtw_pwrstate_string(power), 2302 (before_rf) ? "before" : "after", anaparm)); 2303 2304 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2305 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2306 } 2307 2308 /* XXX I am using the RFMD settings gleaned from the reference 2309 * driver. They agree 2310 */ 2311 static void 2312 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2313 int before_rf, int digphy) 2314 { 2315 uint32_t anaparm; 2316 2317 anaparm = RTW_READ(regs, RTW_ANAPARM); 2318 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2319 2320 switch (power) { 2321 case RTW_OFF: 2322 if (before_rf) 2323 return; 2324 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2325 anaparm |= RTW_ANAPARM_TXDACOFF; 2326 break; 2327 case RTW_SLEEP: 2328 if (!before_rf) 2329 return; 2330 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2331 anaparm |= RTW_ANAPARM_TXDACOFF; 2332 break; 2333 case RTW_ON: 2334 if (!before_rf) 2335 return; 2336 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2337 break; 2338 } 2339 RTW_DPRINTF(RTW_DEBUG_PWR, 2340 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2341 __func__, rtw_pwrstate_string(power), 2342 (before_rf) ? "before" : "after", anaparm)); 2343 2344 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2345 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2346 } 2347 2348 static void 2349 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2350 int before_rf, int digphy) 2351 { 2352 uint32_t anaparm; 2353 2354 anaparm = RTW_READ(regs, RTW_ANAPARM); 2355 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2356 2357 switch (power) { 2358 case RTW_OFF: 2359 if (before_rf) 2360 return; 2361 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2362 anaparm |= RTW_ANAPARM_TXDACOFF; 2363 break; 2364 case RTW_SLEEP: 2365 if (!before_rf) 2366 return; 2367 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2368 anaparm |= RTW_ANAPARM_TXDACOFF; 2369 break; 2370 case RTW_ON: 2371 if (!before_rf) 2372 return; 2373 if (digphy) { 2374 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2375 /* XXX guess */ 2376 anaparm |= RTW_ANAPARM_TXDACOFF; 2377 } else 2378 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2379 break; 2380 } 2381 RTW_DPRINTF(RTW_DEBUG_PWR, 2382 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2383 __func__, rtw_pwrstate_string(power), 2384 (before_rf) ? "before" : "after", anaparm)); 2385 2386 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2387 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2388 } 2389 2390 static void 2391 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2392 int digphy) 2393 { 2394 struct rtw_regs *regs = &sc->sc_regs; 2395 2396 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2397 2398 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2399 2400 rtw_set_access(regs, RTW_ACCESS_NONE); 2401 2402 return; 2403 } 2404 2405 static int 2406 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2407 { 2408 int rc; 2409 2410 RTW_DPRINTF(RTW_DEBUG_PWR, 2411 ("%s: %s->%s\n", __func__, 2412 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2413 2414 if (sc->sc_pwrstate == power) 2415 return 0; 2416 2417 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2418 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2419 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2420 2421 switch (power) { 2422 case RTW_ON: 2423 /* TBD set LEDs */ 2424 break; 2425 case RTW_SLEEP: 2426 /* TBD */ 2427 break; 2428 case RTW_OFF: 2429 /* TBD */ 2430 break; 2431 } 2432 if (rc == 0) 2433 sc->sc_pwrstate = power; 2434 else 2435 sc->sc_pwrstate = RTW_OFF; 2436 return rc; 2437 } 2438 2439 static int 2440 rtw_tune(struct rtw_softc *sc) 2441 { 2442 struct ieee80211com *ic = &sc->sc_ic; 2443 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 2444 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 2445 u_int chan; 2446 int rc; 2447 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2448 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2449 2450 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2451 KASSERT(chan != IEEE80211_CHAN_ANY); 2452 2453 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2454 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2455 2456 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2457 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2458 2459 if (chan == sc->sc_cur_chan) { 2460 RTW_DPRINTF(RTW_DEBUG_TUNE, 2461 ("%s: already tuned chan #%d\n", __func__, chan)); 2462 return 0; 2463 } 2464 2465 rtw_suspend_ticks(sc); 2466 2467 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2468 2469 /* TBD wait for Tx to complete */ 2470 2471 KASSERT(device_has_power(sc->sc_dev)); 2472 2473 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2474 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr, 2475 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) { 2476 /* XXX condition on powersaving */ 2477 aprint_error_dev(sc->sc_dev, "phy init failed\n"); 2478 } 2479 2480 sc->sc_cur_chan = chan; 2481 2482 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2483 2484 rtw_resume_ticks(sc); 2485 2486 return rc; 2487 } 2488 2489 bool 2490 rtw_suspend(device_t self, const pmf_qual_t *qual) 2491 { 2492 int rc; 2493 struct rtw_softc *sc = device_private(self); 2494 2495 sc->sc_flags &= ~RTW_F_DK_VALID; 2496 2497 if (!device_has_power(self)) 2498 return false; 2499 2500 /* turn off PHY */ 2501 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2502 aprint_error_dev(self, "failed to turn off PHY (%d)\n", rc); 2503 return false; 2504 } 2505 2506 rtw_disable_interrupts(&sc->sc_regs); 2507 2508 return true; 2509 } 2510 2511 bool 2512 rtw_resume(device_t self, const pmf_qual_t *qual) 2513 { 2514 struct rtw_softc *sc = device_private(self); 2515 2516 /* Power may have been removed, resetting WEP keys. 2517 */ 2518 sc->sc_flags &= ~RTW_F_DK_VALID; 2519 rtw_enable_interrupts(sc); 2520 2521 return true; 2522 } 2523 2524 static void 2525 rtw_transmit_config(struct rtw_regs *regs) 2526 { 2527 uint32_t tcr; 2528 2529 tcr = RTW_READ(regs, RTW_TCR); 2530 2531 tcr |= RTW_TCR_CWMIN; 2532 tcr &= ~RTW_TCR_MXDMA_MASK; 2533 tcr |= RTW_TCR_MXDMA_256; 2534 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2535 tcr &= ~RTW_TCR_LBK_MASK; 2536 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2537 2538 /* set short/long retry limits */ 2539 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2540 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK); 2541 2542 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2543 2544 RTW_WRITE(regs, RTW_TCR, tcr); 2545 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2546 } 2547 2548 static void 2549 rtw_disable_interrupts(struct rtw_regs *regs) 2550 { 2551 RTW_WRITE16(regs, RTW_IMR, 0); 2552 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2553 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2554 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2555 } 2556 2557 static void 2558 rtw_enable_interrupts(struct rtw_softc *sc) 2559 { 2560 struct rtw_regs *regs = &sc->sc_regs; 2561 2562 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2563 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2564 2565 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2566 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2567 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2568 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2569 2570 /* XXX necessary? */ 2571 if (sc->sc_intr_ack != NULL) 2572 (*sc->sc_intr_ack)(regs); 2573 } 2574 2575 static void 2576 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2577 { 2578 uint8_t msr; 2579 2580 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2581 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2582 2583 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2584 2585 switch (opmode) { 2586 case IEEE80211_M_AHDEMO: 2587 case IEEE80211_M_IBSS: 2588 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2589 break; 2590 case IEEE80211_M_HOSTAP: 2591 msr |= RTW_MSR_NETYPE_AP_OK; 2592 break; 2593 case IEEE80211_M_MONITOR: 2594 /* XXX */ 2595 msr |= RTW_MSR_NETYPE_NOLINK; 2596 break; 2597 case IEEE80211_M_STA: 2598 msr |= RTW_MSR_NETYPE_INFRA_OK; 2599 break; 2600 } 2601 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2602 2603 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2604 } 2605 2606 #define rtw_calchash(addr) \ 2607 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2608 2609 static void 2610 rtw_pktfilt_load(struct rtw_softc *sc) 2611 { 2612 struct rtw_regs *regs = &sc->sc_regs; 2613 struct ieee80211com *ic = &sc->sc_ic; 2614 struct ethercom *ec = &sc->sc_ec; 2615 struct ifnet *ifp = &sc->sc_if; 2616 int hash; 2617 uint32_t hashes[2] = { 0, 0 }; 2618 struct ether_multi *enm; 2619 struct ether_multistep step; 2620 2621 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2622 2623 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2624 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2625 2626 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2627 /* MAC auto-reset PHY (huh?) */ 2628 sc->sc_rcr |= RTW_RCR_ENMARP; 2629 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2630 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2631 2632 switch (ic->ic_opmode) { 2633 case IEEE80211_M_MONITOR: 2634 sc->sc_rcr |= RTW_RCR_MONITOR; 2635 break; 2636 case IEEE80211_M_AHDEMO: 2637 case IEEE80211_M_IBSS: 2638 /* receive broadcasts in our BSS */ 2639 sc->sc_rcr |= RTW_RCR_ADD3; 2640 break; 2641 default: 2642 break; 2643 } 2644 2645 ifp->if_flags &= ~IFF_ALLMULTI; 2646 2647 /* 2648 * Program the 64-bit multicast hash filter. 2649 */ 2650 ETHER_FIRST_MULTI(step, ec, enm); 2651 while (enm != NULL) { 2652 /* XXX */ 2653 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2654 ETHER_ADDR_LEN) != 0) { 2655 ifp->if_flags |= IFF_ALLMULTI; 2656 break; 2657 } 2658 2659 hash = rtw_calchash(enm->enm_addrlo); 2660 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2661 ETHER_NEXT_MULTI(step, enm); 2662 } 2663 2664 /* XXX accept all broadcast if scanning */ 2665 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2666 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2667 2668 if (ifp->if_flags & IFF_PROMISC) { 2669 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2670 sc->sc_rcr |= RTW_RCR_ACRC32; /* accept frames failing CRC */ 2671 sc->sc_rcr |= RTW_RCR_AICV; /* accept frames failing ICV */ 2672 ifp->if_flags |= IFF_ALLMULTI; 2673 } 2674 2675 if (ifp->if_flags & IFF_ALLMULTI) 2676 hashes[0] = hashes[1] = 0xffffffff; 2677 2678 if ((hashes[0] | hashes[1]) != 0) 2679 sc->sc_rcr |= RTW_RCR_AM; /* accept multicast */ 2680 2681 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2682 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2683 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2684 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2685 2686 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2687 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2688 device_xname(sc->sc_dev), RTW_READ(regs, RTW_MAR0), 2689 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2690 } 2691 2692 static struct mbuf * 2693 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2694 { 2695 struct ieee80211com *ic = &sc->sc_ic; 2696 struct mbuf *m; 2697 struct ieee80211_beacon_offsets boff; 2698 2699 if ((m = ieee80211_beacon_alloc(ic, ni, &boff)) != NULL) { 2700 RTW_DPRINTF(RTW_DEBUG_BEACON, 2701 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2702 } 2703 return m; 2704 } 2705 2706 /* Must be called at splnet. */ 2707 static int 2708 rtw_init(struct ifnet *ifp) 2709 { 2710 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2711 struct ieee80211com *ic = &sc->sc_ic; 2712 struct rtw_regs *regs = &sc->sc_regs; 2713 int rc; 2714 2715 if (device_is_active(sc->sc_dev)) { 2716 /* Cancel pending I/O and reset. */ 2717 rtw_stop(ifp, 0); 2718 } else if (!pmf_device_resume(sc->sc_dev, &sc->sc_qual) || 2719 !device_is_active(sc->sc_dev)) 2720 return 0; 2721 2722 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2723 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 2724 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 2725 2726 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2727 goto out; 2728 2729 if ((rc = rtw_swring_setup(sc)) != 0) 2730 goto out; 2731 2732 rtw_transmit_config(regs); 2733 2734 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2735 2736 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2737 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2738 2739 /* long PLCP header, 1Mb/2Mb basic rate */ 2740 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2741 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2742 2743 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2744 rtw_set_access(regs, RTW_ACCESS_NONE); 2745 2746 /* XXX from reference sources */ 2747 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2748 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2749 2750 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev); 2751 2752 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2753 /* from Linux driver */ 2754 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2755 2756 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2757 2758 rtw_enable_interrupts(sc); 2759 2760 rtw_pktfilt_load(sc); 2761 2762 rtw_hwring_setup(sc); 2763 2764 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2765 2766 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2767 2768 ifp->if_flags |= IFF_RUNNING; 2769 ic->ic_state = IEEE80211_S_INIT; 2770 2771 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2772 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2773 2774 rtw_resume_ticks(sc); 2775 2776 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2777 2778 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2779 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2780 else 2781 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2782 2783 out: 2784 aprint_error_dev(sc->sc_dev, "interface not running\n"); 2785 return rc; 2786 } 2787 2788 static inline void 2789 rtw_led_init(struct rtw_regs *regs) 2790 { 2791 uint8_t cfg0, cfg1; 2792 2793 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2794 2795 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2796 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2797 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2798 2799 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2800 RTW_DPRINTF(RTW_DEBUG_LED, 2801 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2802 2803 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2804 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2805 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2806 2807 rtw_set_access(regs, RTW_ACCESS_NONE); 2808 } 2809 2810 /* 2811 * IEEE80211_S_INIT: LED1 off 2812 * 2813 * IEEE80211_S_AUTH, 2814 * IEEE80211_S_ASSOC, 2815 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2816 * 2817 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2818 */ 2819 static void 2820 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2821 { 2822 struct rtw_led_state *ls; 2823 2824 ls = &sc->sc_led_state; 2825 2826 switch (nstate) { 2827 case IEEE80211_S_INIT: 2828 rtw_led_init(&sc->sc_regs); 2829 aprint_debug_dev(sc->sc_dev, "stopping blink\n"); 2830 callout_stop(&ls->ls_slow_ch); 2831 callout_stop(&ls->ls_fast_ch); 2832 ls->ls_slowblink = 0; 2833 ls->ls_actblink = 0; 2834 ls->ls_default = 0; 2835 break; 2836 case IEEE80211_S_SCAN: 2837 aprint_debug_dev(sc->sc_dev, "scheduling blink\n"); 2838 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2839 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2840 /*FALLTHROUGH*/ 2841 case IEEE80211_S_AUTH: 2842 case IEEE80211_S_ASSOC: 2843 ls->ls_default = RTW_LED1; 2844 ls->ls_actblink = RTW_LED1; 2845 ls->ls_slowblink = RTW_LED1; 2846 break; 2847 case IEEE80211_S_RUN: 2848 ls->ls_slowblink = 0; 2849 break; 2850 } 2851 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2852 } 2853 2854 static void 2855 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2856 { 2857 uint8_t led_condition; 2858 bus_size_t ofs; 2859 uint8_t mask, newval, val; 2860 2861 led_condition = ls->ls_default; 2862 2863 if (ls->ls_state & RTW_LED_S_SLOW) 2864 led_condition ^= ls->ls_slowblink; 2865 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2866 led_condition ^= ls->ls_actblink; 2867 2868 RTW_DPRINTF(RTW_DEBUG_LED, 2869 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2870 2871 switch (hwverid) { 2872 default: 2873 case 'F': 2874 ofs = RTW_PSR; 2875 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2876 if (led_condition & RTW_LED0) 2877 newval &= ~RTW_PSR_LEDGPO0; 2878 if (led_condition & RTW_LED1) 2879 newval &= ~RTW_PSR_LEDGPO1; 2880 break; 2881 case 'D': 2882 ofs = RTW_9346CR; 2883 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2884 newval = RTW_9346CR_EEM_PROGRAM; 2885 if (led_condition & RTW_LED0) 2886 newval |= RTW_9346CR_EEDI; 2887 if (led_condition & RTW_LED1) 2888 newval |= RTW_9346CR_EECS; 2889 break; 2890 } 2891 val = RTW_READ8(regs, ofs); 2892 RTW_DPRINTF(RTW_DEBUG_LED, 2893 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2894 (uintptr_t)ofs)); 2895 val &= ~mask; 2896 val |= newval; 2897 RTW_WRITE8(regs, ofs, val); 2898 RTW_DPRINTF(RTW_DEBUG_LED, 2899 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2900 (uintptr_t)ofs)); 2901 RTW_SYNC(regs, ofs, ofs); 2902 } 2903 2904 static void 2905 rtw_led_fastblink(void *arg) 2906 { 2907 int ostate, s; 2908 struct rtw_softc *sc = (struct rtw_softc *)arg; 2909 struct rtw_led_state *ls = &sc->sc_led_state; 2910 2911 s = splnet(); 2912 ostate = ls->ls_state; 2913 ls->ls_state ^= ls->ls_event; 2914 2915 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2916 ls->ls_state &= ~RTW_LED_S_TX; 2917 2918 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2919 ls->ls_state &= ~RTW_LED_S_RX; 2920 2921 ls->ls_event = 0; 2922 2923 if (ostate != ls->ls_state) 2924 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2925 splx(s); 2926 2927 aprint_debug_dev(sc->sc_dev, "scheduling fast blink\n"); 2928 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2929 } 2930 2931 static void 2932 rtw_led_slowblink(void *arg) 2933 { 2934 int s; 2935 struct rtw_softc *sc = (struct rtw_softc *)arg; 2936 struct rtw_led_state *ls = &sc->sc_led_state; 2937 2938 s = splnet(); 2939 ls->ls_state ^= RTW_LED_S_SLOW; 2940 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2941 splx(s); 2942 aprint_debug_dev(sc->sc_dev, "scheduling slow blink\n"); 2943 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2944 } 2945 2946 static void 2947 rtw_led_detach(struct rtw_led_state *ls) 2948 { 2949 callout_destroy(&ls->ls_fast_ch); 2950 callout_destroy(&ls->ls_slow_ch); 2951 } 2952 2953 static void 2954 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2955 { 2956 callout_init(&ls->ls_fast_ch, 0); 2957 callout_init(&ls->ls_slow_ch, 0); 2958 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2959 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2960 } 2961 2962 static int 2963 rtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2964 { 2965 int rc = 0, s; 2966 struct rtw_softc *sc = ifp->if_softc; 2967 2968 s = splnet(); 2969 if (cmd == SIOCSIFFLAGS) { 2970 if ((rc = ifioctl_common(ifp, cmd, data)) != 0) 2971 ; 2972 else switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2973 case IFF_UP: 2974 rc = rtw_init(ifp); 2975 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2976 break; 2977 case IFF_UP|IFF_RUNNING: 2978 if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2979 rtw_pktfilt_load(sc); 2980 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2981 break; 2982 case IFF_RUNNING: 2983 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2984 rtw_stop(ifp, 1); 2985 break; 2986 default: 2987 break; 2988 } 2989 } else if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 2990 ; /* nothing to do */ 2991 else if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 2992 /* reload packet filter if running */ 2993 if (ifp->if_flags & IFF_RUNNING) 2994 rtw_pktfilt_load(sc); 2995 rc = 0; 2996 } else if ((ifp->if_flags & IFF_UP) != 0) 2997 rc = rtw_init(ifp); 2998 else 2999 rc = 0; 3000 splx(s); 3001 return rc; 3002 } 3003 3004 /* Select a transmit ring with at least one h/w and s/w descriptor free. 3005 * Return 0 on success, -1 on failure. 3006 */ 3007 static inline int 3008 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 3009 struct rtw_txdesc_blk **tdbp, int pri) 3010 { 3011 struct rtw_txsoft_blk *tsb; 3012 struct rtw_txdesc_blk *tdb; 3013 3014 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 3015 3016 tsb = &sc->sc_txsoft_blk[pri]; 3017 tdb = &sc->sc_txdesc_blk[pri]; 3018 3019 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 3020 if (tsb->tsb_tx_timer == 0) 3021 tsb->tsb_tx_timer = 5; 3022 *tsbp = NULL; 3023 *tdbp = NULL; 3024 return -1; 3025 } 3026 *tsbp = tsb; 3027 *tdbp = tdb; 3028 return 0; 3029 } 3030 3031 static inline struct mbuf * 3032 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 3033 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 3034 struct ieee80211_node **nip, short *if_flagsp) 3035 { 3036 struct mbuf *m; 3037 3038 if (IF_IS_EMPTY(ifq)) 3039 return NULL; 3040 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3041 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3042 __func__, pri)); 3043 *if_flagsp |= IFF_OACTIVE; 3044 sc->sc_if.if_timer = 1; 3045 return NULL; 3046 } 3047 IF_DEQUEUE(ifq, m); 3048 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3049 m->m_pkthdr.rcvif = NULL; 3050 KASSERT(*nip != NULL); 3051 return m; 3052 } 3053 3054 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 3055 * at the driver's selection of transmit control block for the packet. 3056 */ 3057 static inline int 3058 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 3059 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 3060 struct ieee80211_node **nip) 3061 { 3062 int pri; 3063 struct ether_header *eh; 3064 struct mbuf *m0; 3065 struct rtw_softc *sc; 3066 short *if_flagsp; 3067 3068 *mp = NULL; 3069 3070 sc = (struct rtw_softc *)ifp->if_softc; 3071 3072 DPRINTF(sc, RTW_DEBUG_XMIT, 3073 ("%s: enter %s\n", device_xname(sc->sc_dev), __func__)); 3074 3075 if_flagsp = &ifp->if_flags; 3076 3077 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 3078 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 3079 tdbp, nip, if_flagsp)) != NULL) { 3080 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 3081 __func__)); 3082 return 0; 3083 } 3084 3085 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 3086 tdbp, nip, if_flagsp)) != NULL) { 3087 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 3088 __func__)); 3089 return 0; 3090 } 3091 3092 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 3093 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 3094 return 0; 3095 } 3096 3097 IFQ_POLL(&ifp->if_snd, m0); 3098 if (m0 == NULL) { 3099 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3100 __func__)); 3101 return 0; 3102 } 3103 3104 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 3105 3106 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3107 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3108 __func__, pri)); 3109 *if_flagsp |= IFF_OACTIVE; 3110 sc->sc_if.if_timer = 1; 3111 return 0; 3112 } 3113 3114 IFQ_DEQUEUE(&ifp->if_snd, m0); 3115 if (m0 == NULL) { 3116 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3117 __func__)); 3118 return 0; 3119 } 3120 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 3121 ifp->if_opackets++; 3122 bpf_mtap(ifp, m0); 3123 eh = mtod(m0, struct ether_header *); 3124 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 3125 if (*nip == NULL) { 3126 /* NB: ieee80211_find_txnode does stat+msg */ 3127 m_freem(m0); 3128 return -1; 3129 } 3130 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 3131 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 3132 ifp->if_oerrors++; 3133 return -1; 3134 } 3135 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3136 *mp = m0; 3137 return 0; 3138 } 3139 3140 static int 3141 rtw_seg_too_short(bus_dmamap_t dmamap) 3142 { 3143 int i; 3144 for (i = 0; i < dmamap->dm_nsegs; i++) { 3145 if (dmamap->dm_segs[i].ds_len < 4) 3146 return 1; 3147 } 3148 return 0; 3149 } 3150 3151 /* TBD factor with atw_start */ 3152 static struct mbuf * 3153 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 3154 u_int ndescfree, device_t dev) 3155 { 3156 int first, rc; 3157 struct mbuf *m, *m0; 3158 3159 m0 = chain; 3160 3161 /* 3162 * Load the DMA map. Copy and try (once) again if the packet 3163 * didn't fit in the alloted number of segments. 3164 */ 3165 for (first = 1; 3166 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 3167 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 3168 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 3169 first = 0) { 3170 if (rc == 0) { 3171 #ifdef RTW_DIAGxxx 3172 if (rtw_seg_too_short(dmam)) { 3173 printf("%s: short segment, mbuf lengths:", __func__); 3174 for (m = m0; m; m = m->m_next) 3175 printf(" %d", m->m_len); 3176 printf("\n"); 3177 } 3178 #endif 3179 bus_dmamap_unload(dmat, dmam); 3180 } 3181 MGETHDR(m, M_DONTWAIT, MT_DATA); 3182 if (m == NULL) { 3183 aprint_error_dev(dev, "unable to allocate Tx mbuf\n"); 3184 break; 3185 } 3186 if (m0->m_pkthdr.len > MHLEN) { 3187 MCLGET(m, M_DONTWAIT); 3188 if ((m->m_flags & M_EXT) == 0) { 3189 aprint_error_dev(dev, 3190 "cannot allocate Tx cluster\n"); 3191 m_freem(m); 3192 break; 3193 } 3194 } 3195 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3196 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3197 m_freem(m0); 3198 m0 = m; 3199 m = NULL; 3200 } 3201 if (rc != 0) { 3202 aprint_error_dev(dev, "cannot load Tx buffer, rc = %d\n", rc); 3203 m_freem(m0); 3204 return NULL; 3205 } else if (rtw_seg_too_short(dmam)) { 3206 aprint_error_dev(dev, 3207 "cannot load Tx buffer, segment too short\n"); 3208 bus_dmamap_unload(dmat, dmam); 3209 m_freem(m0); 3210 return NULL; 3211 } else if (dmam->dm_nsegs > ndescfree) { 3212 aprint_error_dev(dev, "too many tx segments\n"); 3213 bus_dmamap_unload(dmat, dmam); 3214 m_freem(m0); 3215 return NULL; 3216 } 3217 return m0; 3218 } 3219 3220 #ifdef RTW_DEBUG 3221 static void 3222 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3223 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3224 { 3225 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3226 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] next %#08x " 3227 "buf %#08x ctl0 %#08x ctl1 %#08x len %#08x\n", 3228 device_xname(sc->sc_dev), ts, action, desc, 3229 le32toh(td->td_buf), le32toh(td->td_next), 3230 le32toh(td->td_ctl0), le32toh(td->td_ctl1), 3231 le32toh(td->td_len))); 3232 } 3233 #endif /* RTW_DEBUG */ 3234 3235 static void 3236 rtw_start(struct ifnet *ifp) 3237 { 3238 int desc, i, lastdesc, npkt, rate; 3239 uint32_t proto_ctl0, ctl0, ctl1; 3240 bus_dmamap_t dmamap; 3241 struct ieee80211com *ic; 3242 struct ieee80211_duration *d0; 3243 struct ieee80211_frame_min *wh; 3244 struct ieee80211_node *ni = NULL; /* XXX: GCC */ 3245 struct mbuf *m0; 3246 struct rtw_softc *sc; 3247 struct rtw_txsoft_blk *tsb = NULL; /* XXX: GCC */ 3248 struct rtw_txdesc_blk *tdb = NULL; /* XXX: GCC */ 3249 struct rtw_txsoft *ts; 3250 struct rtw_txdesc *td; 3251 struct ieee80211_key *k; 3252 3253 sc = (struct rtw_softc *)ifp->if_softc; 3254 ic = &sc->sc_ic; 3255 3256 DPRINTF(sc, RTW_DEBUG_XMIT, 3257 ("%s: enter %s\n", device_xname(sc->sc_dev), __func__)); 3258 3259 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3260 goto out; 3261 3262 /* XXX do real rate control */ 3263 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3264 3265 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3266 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3267 3268 for (;;) { 3269 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3270 continue; 3271 if (m0 == NULL) 3272 break; 3273 3274 wh = mtod(m0, struct ieee80211_frame_min *); 3275 3276 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3277 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3278 m_freem(m0); 3279 break; 3280 } else 3281 k = NULL; 3282 3283 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3284 3285 dmamap = ts->ts_dmamap; 3286 3287 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3288 tdb->tdb_nfree, sc->sc_dev); 3289 3290 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3291 DPRINTF(sc, RTW_DEBUG_XMIT, 3292 ("%s: fail dmamap load\n", __func__)); 3293 goto post_dequeue_err; 3294 } 3295 3296 /* Note well: rtw_dmamap_load_txbuf may have created 3297 * a new chain, so we must find the header once 3298 * more. 3299 */ 3300 wh = mtod(m0, struct ieee80211_frame_min *); 3301 3302 /* XXX do real rate control */ 3303 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3304 IEEE80211_FC0_TYPE_MGT) 3305 rate = 2; 3306 else 3307 rate = MAX(2, ieee80211_get_rate(ni)); 3308 3309 #ifdef RTW_DEBUG 3310 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3311 (IFF_DEBUG|IFF_LINK2)) { 3312 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3313 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3314 : sizeof(wh), 3315 rate, 0); 3316 } 3317 #endif /* RTW_DEBUG */ 3318 ctl0 = proto_ctl0 | 3319 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3320 3321 switch (rate) { 3322 default: 3323 case 2: 3324 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3325 break; 3326 case 4: 3327 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3328 break; 3329 case 11: 3330 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3331 break; 3332 case 22: 3333 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3334 break; 3335 } 3336 /* XXX >= ? Compare after fragmentation? */ 3337 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3338 ctl0 |= RTW_TXCTL0_RTSEN; 3339 3340 /* XXX Sometimes writes a bogus keyid; h/w doesn't 3341 * seem to care, since we don't activate h/w Tx 3342 * encryption. 3343 */ 3344 if (k != NULL && 3345 k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 3346 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3347 RTW_TXCTL0_KEYID_MASK; 3348 } 3349 3350 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3351 IEEE80211_FC0_TYPE_MGT) { 3352 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3353 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3354 IEEE80211_FC0_SUBTYPE_BEACON) 3355 ctl0 |= RTW_TXCTL0_BEACON; 3356 } 3357 3358 if (ieee80211_compute_duration(wh, k, m0->m_pkthdr.len, 3359 ic->ic_flags, ic->ic_fragthreshold, 3360 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3361 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3362 (IFF_DEBUG|IFF_LINK2)) == -1) { 3363 DPRINTF(sc, RTW_DEBUG_XMIT, 3364 ("%s: fail compute duration\n", __func__)); 3365 goto post_load_err; 3366 } 3367 3368 d0 = &ts->ts_d0; 3369 3370 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3371 3372 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3373 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3374 3375 if (d0->d_residue) 3376 ctl1 |= RTW_TXCTL1_LENGEXT; 3377 3378 /* TBD fragmentation */ 3379 3380 ts->ts_first = tdb->tdb_next; 3381 3382 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3383 BUS_DMASYNC_PREWRITE); 3384 3385 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3386 3387 bpf_mtap3(ic->ic_rawbpf, m0); 3388 3389 if (sc->sc_radiobpf != NULL) { 3390 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3391 3392 rt->rt_rate = rate; 3393 3394 bpf_mtap2(sc->sc_radiobpf, rt, sizeof(sc->sc_txtapu), 3395 m0); 3396 } 3397 3398 for (i = 0, lastdesc = desc = ts->ts_first; 3399 i < dmamap->dm_nsegs; 3400 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3401 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3402 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3403 ("%s: seg too long\n", __func__)); 3404 goto post_load_err; 3405 } 3406 td = &tdb->tdb_desc[desc]; 3407 td->td_ctl0 = htole32(ctl0); 3408 td->td_ctl1 = htole32(ctl1); 3409 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3410 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3411 td->td_next = htole32(RTW_NEXT_DESC(tdb, desc)); 3412 if (i != 0) 3413 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3414 lastdesc = desc; 3415 #ifdef RTW_DEBUG 3416 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3417 #endif /* RTW_DEBUG */ 3418 } 3419 3420 KASSERT(desc < tdb->tdb_ndesc); 3421 3422 ts->ts_ni = ni; 3423 KASSERT(ni != NULL); 3424 ts->ts_mbuf = m0; 3425 ts->ts_last = lastdesc; 3426 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3427 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3428 htole32(RTW_TXCTL0_FS); 3429 3430 #ifdef RTW_DEBUG 3431 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3432 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3433 #endif /* RTW_DEBUG */ 3434 3435 tdb->tdb_nfree -= dmamap->dm_nsegs; 3436 tdb->tdb_next = desc; 3437 3438 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3439 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3440 3441 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3442 htole32(RTW_TXCTL0_OWN); 3443 3444 #ifdef RTW_DEBUG 3445 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3446 #endif /* RTW_DEBUG */ 3447 3448 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3449 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3450 3451 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3452 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3453 3454 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) 3455 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3456 tsb->tsb_tx_timer = 5; 3457 ifp->if_timer = 1; 3458 rtw_tx_kick(&sc->sc_regs, tsb->tsb_poll); 3459 } 3460 out: 3461 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3462 return; 3463 post_load_err: 3464 bus_dmamap_unload(sc->sc_dmat, dmamap); 3465 m_freem(m0); 3466 post_dequeue_err: 3467 ieee80211_free_node(ni); 3468 return; 3469 } 3470 3471 static void 3472 rtw_idle(struct rtw_regs *regs) 3473 { 3474 int active; 3475 uint8_t tppoll; 3476 3477 /* request stop DMA; wait for packets to stop transmitting. */ 3478 3479 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3480 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL); 3481 3482 for (active = 0; active < 300 && 3483 (tppoll = RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0; 3484 active++) 3485 DELAY(10); 3486 printf("%s: transmit DMA idle in %dus, tppoll %02" PRIx8 "\n", __func__, 3487 active * 10, tppoll); 3488 } 3489 3490 static void 3491 rtw_watchdog(struct ifnet *ifp) 3492 { 3493 int pri, tx_timeouts = 0; 3494 struct rtw_softc *sc; 3495 struct rtw_txsoft_blk *tsb; 3496 3497 sc = ifp->if_softc; 3498 3499 ifp->if_timer = 0; 3500 3501 if (!device_is_active(sc->sc_dev)) 3502 return; 3503 3504 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3505 tsb = &sc->sc_txsoft_blk[pri]; 3506 3507 if (tsb->tsb_tx_timer == 0) 3508 continue; 3509 else if (--tsb->tsb_tx_timer == 0) { 3510 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3511 continue; 3512 else if (rtw_collect_txring(sc, tsb, 3513 &sc->sc_txdesc_blk[pri], 0)) 3514 continue; 3515 printf("%s: transmit timeout, priority %d\n", 3516 ifp->if_xname, pri); 3517 ifp->if_oerrors++; 3518 if (pri != RTW_TXPRIBCN) 3519 tx_timeouts++; 3520 } else 3521 ifp->if_timer = 1; 3522 } 3523 3524 if (tx_timeouts > 0) { 3525 /* Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr, 3526 * reset s/w tx-ring pointers, and start transmission. 3527 * 3528 * TBD Stop/restart just the broken rings? 3529 */ 3530 rtw_idle(&sc->sc_regs); 3531 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 3532 rtw_txdescs_reset(sc); 3533 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 3534 rtw_start(ifp); 3535 } 3536 ieee80211_watchdog(&sc->sc_ic); 3537 return; 3538 } 3539 3540 static void 3541 rtw_next_scan(void *arg) 3542 { 3543 struct ieee80211com *ic = arg; 3544 int s; 3545 3546 /* don't call rtw_start w/o network interrupts blocked */ 3547 s = splnet(); 3548 if (ic->ic_state == IEEE80211_S_SCAN) 3549 ieee80211_next_scan(ic); 3550 splx(s); 3551 } 3552 3553 static void 3554 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3555 { 3556 uint16_t bcnitv, bintritv, intval; 3557 int i; 3558 struct rtw_regs *regs = &sc->sc_regs; 3559 3560 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3561 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3562 3563 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3564 3565 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3566 3567 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); 3568 3569 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3570 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); 3571 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3572 /* interrupt host 1ms before the TBTT */ 3573 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV; 3574 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV); 3575 RTW_WRITE16(regs, RTW_BINTRITV, bintritv); 3576 /* magic from Linux */ 3577 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND)); 3578 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); 3579 rtw_set_access(regs, RTW_ACCESS_NONE); 3580 3581 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 3582 } 3583 3584 /* Synchronize the hardware state with the software state. */ 3585 static int 3586 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3587 { 3588 struct ifnet *ifp = ic->ic_ifp; 3589 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3590 enum ieee80211_state ostate; 3591 int error; 3592 3593 ostate = ic->ic_state; 3594 3595 aprint_debug_dev(sc->sc_dev, "%s: l.%d\n", __func__, __LINE__); 3596 rtw_led_newstate(sc, nstate); 3597 3598 aprint_debug_dev(sc->sc_dev, "%s: l.%d\n", __func__, __LINE__); 3599 if (nstate == IEEE80211_S_INIT) { 3600 callout_stop(&sc->sc_scan_ch); 3601 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3602 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3603 } 3604 3605 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3606 rtw_pwrstate(sc, RTW_ON); 3607 3608 if ((error = rtw_tune(sc)) != 0) 3609 return error; 3610 3611 switch (nstate) { 3612 case IEEE80211_S_INIT: 3613 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3614 break; 3615 case IEEE80211_S_SCAN: 3616 if (ostate != IEEE80211_S_SCAN) { 3617 (void)memset(ic->ic_bss->ni_bssid, 0, 3618 IEEE80211_ADDR_LEN); 3619 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3620 } 3621 3622 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3623 rtw_next_scan, ic); 3624 3625 break; 3626 case IEEE80211_S_RUN: 3627 switch (ic->ic_opmode) { 3628 case IEEE80211_M_HOSTAP: 3629 case IEEE80211_M_IBSS: 3630 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3631 /*FALLTHROUGH*/ 3632 case IEEE80211_M_AHDEMO: 3633 case IEEE80211_M_STA: 3634 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3635 ic->ic_bss->ni_intval); 3636 break; 3637 case IEEE80211_M_MONITOR: 3638 break; 3639 } 3640 rtw_set_nettype(sc, ic->ic_opmode); 3641 break; 3642 case IEEE80211_S_ASSOC: 3643 case IEEE80211_S_AUTH: 3644 break; 3645 } 3646 3647 if (nstate != IEEE80211_S_SCAN) 3648 callout_stop(&sc->sc_scan_ch); 3649 3650 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3651 } 3652 3653 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3654 static uint64_t 3655 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3656 { 3657 uint32_t tsftl, tsfth; 3658 3659 tsfth = RTW_READ(regs, RTW_TSFTRH); 3660 tsftl = RTW_READ(regs, RTW_TSFTRL); 3661 if (tsftl < rstamp) /* Compensate for rollover. */ 3662 tsfth--; 3663 return ((uint64_t)tsfth << 32) | rstamp; 3664 } 3665 3666 static void 3667 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3668 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3669 { 3670 struct ifnet *ifp = ic->ic_ifp; 3671 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3672 3673 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3674 3675 switch (subtype) { 3676 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3677 case IEEE80211_FC0_SUBTYPE_BEACON: 3678 if (ic->ic_opmode == IEEE80211_M_IBSS && 3679 ic->ic_state == IEEE80211_S_RUN && 3680 device_is_active(sc->sc_dev)) { 3681 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp); 3682 if (le64toh(ni->ni_tstamp.tsf) >= tsf) 3683 (void)ieee80211_ibss_merge(ni); 3684 } 3685 break; 3686 default: 3687 break; 3688 } 3689 return; 3690 } 3691 3692 static struct ieee80211_node * 3693 rtw_node_alloc(struct ieee80211_node_table *nt) 3694 { 3695 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3696 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3697 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3698 3699 DPRINTF(sc, RTW_DEBUG_NODE, 3700 ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 3701 return ni; 3702 } 3703 3704 static void 3705 rtw_node_free(struct ieee80211_node *ni) 3706 { 3707 struct ieee80211com *ic = ni->ni_ic; 3708 struct ifnet *ifp = ic->ic_ifp; 3709 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3710 3711 DPRINTF(sc, RTW_DEBUG_NODE, 3712 ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 3713 ether_sprintf(ni->ni_bssid))); 3714 (*sc->sc_mtbl.mt_node_free)(ni); 3715 } 3716 3717 static int 3718 rtw_media_change(struct ifnet *ifp) 3719 { 3720 int error; 3721 3722 error = ieee80211_media_change(ifp); 3723 if (error == ENETRESET) { 3724 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3725 (IFF_RUNNING|IFF_UP)) 3726 rtw_init(ifp); /* XXX lose error */ 3727 error = 0; 3728 } 3729 return error; 3730 } 3731 3732 static void 3733 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3734 { 3735 struct rtw_softc *sc = ifp->if_softc; 3736 3737 if (!device_is_active(sc->sc_dev)) { 3738 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3739 imr->ifm_status = 0; 3740 return; 3741 } 3742 ieee80211_media_status(ifp, imr); 3743 } 3744 3745 static inline void 3746 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3747 { 3748 (void)strlcpy(ifp->if_xname, dvname, IFNAMSIZ); 3749 ifp->if_softc = softc; 3750 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3751 IFF_NOTRAILERS; 3752 ifp->if_ioctl = rtw_ioctl; 3753 ifp->if_start = rtw_start; 3754 ifp->if_watchdog = rtw_watchdog; 3755 ifp->if_init = rtw_init; 3756 ifp->if_stop = rtw_stop; 3757 } 3758 3759 static inline void 3760 rtw_set80211props(struct ieee80211com *ic) 3761 { 3762 int nrate; 3763 ic->ic_phytype = IEEE80211_T_DS; 3764 ic->ic_opmode = IEEE80211_M_STA; 3765 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3766 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 3767 3768 nrate = 0; 3769 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3770 IEEE80211_RATE_BASIC | 2; 3771 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3772 IEEE80211_RATE_BASIC | 4; 3773 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3774 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3775 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3776 } 3777 3778 static inline void 3779 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3780 { 3781 mtbl->mt_newstate = ic->ic_newstate; 3782 ic->ic_newstate = rtw_newstate; 3783 3784 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3785 ic->ic_recv_mgmt = rtw_recv_mgmt; 3786 3787 mtbl->mt_node_free = ic->ic_node_free; 3788 ic->ic_node_free = rtw_node_free; 3789 3790 mtbl->mt_node_alloc = ic->ic_node_alloc; 3791 ic->ic_node_alloc = rtw_node_alloc; 3792 3793 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3794 ic->ic_crypto.cs_key_set = rtw_key_set; 3795 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3796 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3797 } 3798 3799 static inline void 3800 rtw_init_radiotap(struct rtw_softc *sc) 3801 { 3802 uint32_t present; 3803 3804 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3805 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3806 3807 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 3808 present = htole32(RTW_PHILIPS_RX_RADIOTAP_PRESENT); 3809 else 3810 present = htole32(RTW_RX_RADIOTAP_PRESENT); 3811 sc->sc_rxtap.rr_ihdr.it_present = present; 3812 3813 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3814 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3815 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3816 } 3817 3818 static int 3819 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3820 { 3821 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3822 SIMPLEQ_INIT(&tsb->tsb_freeq); 3823 tsb->tsb_ndesc = qlen; 3824 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3825 M_NOWAIT); 3826 if (tsb->tsb_desc == NULL) 3827 return ENOMEM; 3828 return 0; 3829 } 3830 3831 static void 3832 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3833 { 3834 int pri; 3835 struct rtw_txsoft_blk *tsb; 3836 3837 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3838 tsb = &sc->sc_txsoft_blk[pri]; 3839 free(tsb->tsb_desc, M_DEVBUF); 3840 tsb->tsb_desc = NULL; 3841 } 3842 } 3843 3844 static int 3845 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3846 { 3847 int pri, rc = 0; 3848 int qlen[RTW_NTXPRI] = 3849 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3850 struct rtw_txsoft_blk *tsbs; 3851 3852 tsbs = sc->sc_txsoft_blk; 3853 3854 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3855 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3856 if (rc != 0) 3857 break; 3858 } 3859 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3860 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3861 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3862 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3863 return rc; 3864 } 3865 3866 static void 3867 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3868 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3869 { 3870 tdb->tdb_ndesc = ndesc; 3871 tdb->tdb_desc = desc; 3872 tdb->tdb_physbase = physbase; 3873 tdb->tdb_ofs = ofs; 3874 3875 (void)memset(tdb->tdb_desc, 0, 3876 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3877 3878 rtw_txdesc_blk_init(tdb); 3879 tdb->tdb_next = 0; 3880 } 3881 3882 static void 3883 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3884 { 3885 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3886 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3887 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3888 3889 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3890 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3891 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3892 3893 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3894 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3895 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3896 3897 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3898 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3899 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3900 } 3901 3902 static struct rtw_rf * 3903 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3904 { 3905 rtw_rf_write_t rf_write; 3906 struct rtw_rf *rf; 3907 3908 switch (rfchipid) { 3909 default: 3910 rf_write = rtw_rf_hostwrite; 3911 break; 3912 case RTW_RFCHIPID_INTERSIL: 3913 case RTW_RFCHIPID_PHILIPS: 3914 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3915 case RTW_RFCHIPID_RFMD: 3916 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3917 break; 3918 } 3919 3920 switch (rfchipid) { 3921 case RTW_RFCHIPID_GCT: 3922 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0); 3923 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3924 break; 3925 case RTW_RFCHIPID_MAXIM: 3926 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3927 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3928 break; 3929 case RTW_RFCHIPID_PHILIPS: 3930 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3931 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3932 break; 3933 case RTW_RFCHIPID_RFMD: 3934 /* XXX RFMD has no RF constructor */ 3935 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3936 /*FALLTHROUGH*/ 3937 default: 3938 return NULL; 3939 } 3940 rf->rf_continuous_tx_cb = 3941 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3942 rf->rf_continuous_tx_arg = (void *)sc; 3943 return rf; 3944 } 3945 3946 /* Revision C and later use a different PHY delay setting than 3947 * revisions A and B. 3948 */ 3949 static uint8_t 3950 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 3951 { 3952 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3953 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3954 3955 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); 3956 3957 RTW_WRITE(regs, RTW_RCR, REVAB); 3958 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3959 RTW_WRITE(regs, RTW_RCR, REVC); 3960 3961 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3962 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3963 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3964 3965 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 3966 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3967 3968 return phydelay; 3969 #undef REVC 3970 } 3971 3972 void 3973 rtw_attach(struct rtw_softc *sc) 3974 { 3975 struct ifnet *ifp = &sc->sc_if; 3976 struct ieee80211com *ic = &sc->sc_ic; 3977 struct rtw_txsoft_blk *tsb; 3978 int pri, rc; 3979 3980 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 3981 3982 rtw_cipher_wep = ieee80211_cipher_wep; 3983 rtw_cipher_wep.ic_decap = rtw_wep_decap; 3984 3985 NEXT_ATTACH_STATE(sc, DETACHED); 3986 3987 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3988 case RTW_TCR_HWVERID_F: 3989 sc->sc_hwverid = 'F'; 3990 break; 3991 case RTW_TCR_HWVERID_D: 3992 sc->sc_hwverid = 'D'; 3993 break; 3994 default: 3995 sc->sc_hwverid = '?'; 3996 break; 3997 } 3998 aprint_verbose_dev(sc->sc_dev, "hardware version %c\n", 3999 sc->sc_hwverid); 4000 4001 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 4002 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 4003 0); 4004 4005 if (rc != 0) { 4006 aprint_error_dev(sc->sc_dev, 4007 "could not allocate hw descriptors, error %d\n", rc); 4008 goto err; 4009 } 4010 4011 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 4012 4013 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 4014 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 4015 (void **)&sc->sc_descs, BUS_DMA_COHERENT); 4016 4017 if (rc != 0) { 4018 aprint_error_dev(sc->sc_dev, 4019 "could not map hw descriptors, error %d\n", rc); 4020 goto err; 4021 } 4022 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 4023 4024 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 4025 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 4026 4027 if (rc != 0) { 4028 aprint_error_dev(sc->sc_dev, 4029 "could not create DMA map for hw descriptors, error %d\n", 4030 rc); 4031 goto err; 4032 } 4033 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 4034 4035 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 4036 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 4037 4038 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4039 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 4040 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 4041 } 4042 4043 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 4044 sizeof(struct rtw_descs), NULL, 0); 4045 4046 if (rc != 0) { 4047 aprint_error_dev(sc->sc_dev, 4048 "could not load DMA map for hw descriptors, error %d\n", 4049 rc); 4050 goto err; 4051 } 4052 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 4053 4054 if (rtw_txsoft_blk_setup_all(sc) != 0) 4055 goto err; 4056 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 4057 4058 rtw_txdesc_blk_setup_all(sc); 4059 4060 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 4061 4062 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 4063 4064 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4065 tsb = &sc->sc_txsoft_blk[pri]; 4066 4067 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 4068 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 4069 aprint_error_dev(sc->sc_dev, 4070 "could not load DMA map for hw tx descriptors, " 4071 "error %d\n", rc); 4072 goto err; 4073 } 4074 } 4075 4076 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 4077 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 4078 RTW_RXQLEN)) != 0) { 4079 aprint_error_dev(sc->sc_dev, 4080 "could not load DMA map for hw rx descriptors, error %d\n", 4081 rc); 4082 goto err; 4083 } 4084 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 4085 4086 /* Reset the chip to a known state. */ 4087 if (rtw_reset(sc) != 0) 4088 goto err; 4089 NEXT_ATTACH_STATE(sc, FINISH_RESET); 4090 4091 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 4092 4093 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 4094 sc->sc_flags |= RTW_F_9356SROM; 4095 4096 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 4097 sc->sc_dev) != 0) 4098 goto err; 4099 4100 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 4101 4102 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 4103 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 4104 sc->sc_dev) != 0) { 4105 aprint_error_dev(sc->sc_dev, 4106 "attach failed, malformed serial ROM\n"); 4107 goto err; 4108 } 4109 4110 aprint_verbose_dev(sc->sc_dev, "%s PHY\n", 4111 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 4112 4113 aprint_verbose_dev(sc->sc_dev, "carrier-sense threshold %u\n", 4114 sc->sc_csthr); 4115 4116 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 4117 4118 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 4119 sc->sc_flags & RTW_F_DIGPHY); 4120 4121 if (sc->sc_rf == NULL) { 4122 aprint_verbose_dev(sc->sc_dev, 4123 "attach failed, could not attach RF\n"); 4124 goto err; 4125 } 4126 4127 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 4128 4129 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4130 4131 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4132 ("%s: PHY delay %d\n", device_xname(sc->sc_dev), sc->sc_phydelay)); 4133 4134 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4135 rtw_identify_country(&sc->sc_regs, &sc->sc_locale); 4136 4137 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, sc->sc_dev); 4138 4139 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4140 sc->sc_dev) != 0) 4141 goto err; 4142 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4143 4144 rtw_setifprops(ifp, device_xname(sc->sc_dev), (void*)sc); 4145 4146 IFQ_SET_READY(&ifp->if_snd); 4147 4148 sc->sc_ic.ic_ifp = ifp; 4149 rtw_set80211props(&sc->sc_ic); 4150 4151 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4152 4153 /* 4154 * Call MI attach routines. 4155 */ 4156 if_attach(ifp); 4157 ieee80211_ifattach(&sc->sc_ic); 4158 4159 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4160 4161 /* possibly we should fill in our own sc_send_prresp, since 4162 * the RTL8180 is probably sending probe responses in ad hoc 4163 * mode. 4164 */ 4165 4166 /* complete initialization */ 4167 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4168 callout_init(&sc->sc_scan_ch, 0); 4169 4170 rtw_init_radiotap(sc); 4171 4172 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 4173 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4174 4175 NEXT_ATTACH_STATE(sc, FINISHED); 4176 4177 ieee80211_announce(ic); 4178 return; 4179 err: 4180 rtw_detach(sc); 4181 return; 4182 } 4183 4184 int 4185 rtw_detach(struct rtw_softc *sc) 4186 { 4187 struct ifnet *ifp = &sc->sc_if; 4188 int pri, s; 4189 4190 s = splnet(); 4191 4192 switch (sc->sc_attach_state) { 4193 case FINISHED: 4194 rtw_stop(ifp, 1); 4195 4196 pmf_device_deregister(sc->sc_dev); 4197 callout_stop(&sc->sc_scan_ch); 4198 ieee80211_ifdetach(&sc->sc_ic); 4199 if_detach(ifp); 4200 rtw_led_detach(&sc->sc_led_state); 4201 /*FALLTHROUGH*/ 4202 case FINISH_ID_STA: 4203 case FINISH_RF_ATTACH: 4204 rtw_rf_destroy(sc->sc_rf); 4205 sc->sc_rf = NULL; 4206 /*FALLTHROUGH*/ 4207 case FINISH_PARSE_SROM: 4208 case FINISH_READ_SROM: 4209 rtw_srom_free(&sc->sc_srom); 4210 /*FALLTHROUGH*/ 4211 case FINISH_RESET: 4212 case FINISH_RXMAPS_CREATE: 4213 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4214 RTW_RXQLEN); 4215 /*FALLTHROUGH*/ 4216 case FINISH_TXMAPS_CREATE: 4217 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4218 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4219 sc->sc_txsoft_blk[pri].tsb_desc, 4220 sc->sc_txsoft_blk[pri].tsb_ndesc); 4221 } 4222 /*FALLTHROUGH*/ 4223 case FINISH_TXDESCBLK_SETUP: 4224 case FINISH_TXCTLBLK_SETUP: 4225 rtw_txsoft_blk_cleanup_all(sc); 4226 /*FALLTHROUGH*/ 4227 case FINISH_DESCMAP_LOAD: 4228 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4229 /*FALLTHROUGH*/ 4230 case FINISH_DESCMAP_CREATE: 4231 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4232 /*FALLTHROUGH*/ 4233 case FINISH_DESC_MAP: 4234 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 4235 sizeof(struct rtw_descs)); 4236 /*FALLTHROUGH*/ 4237 case FINISH_DESC_ALLOC: 4238 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4239 sc->sc_desc_nsegs); 4240 /*FALLTHROUGH*/ 4241 case DETACHED: 4242 NEXT_ATTACH_STATE(sc, DETACHED); 4243 break; 4244 } 4245 splx(s); 4246 return 0; 4247 } 4248
Indexes created Mon Sep 29 21:09:56 GMT 2025