rtw.c revision 1.120
1 /* $NetBSD: rtw.c,v 1.120 2013/10/17 21:24:24 christos Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005, 2006, 2007 David Young. All rights 4 * reserved. 5 * 6 * Programmed for NetBSD by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 21 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 28 * OF SUCH DAMAGE. 29 */ 30 /* 31 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.120 2013/10/17 21:24:24 christos Exp $"); 36 37 38 #include <sys/param.h> 39 #include <sys/sysctl.h> 40 #include <sys/systm.h> 41 #include <sys/callout.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/time.h> 46 #include <sys/types.h> 47 #include <sys/device.h> 48 #include <sys/sockio.h> 49 50 #include <machine/endian.h> 51 #include <sys/bus.h> 52 #include <sys/intr.h> /* splnet */ 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net80211/ieee80211_netbsd.h> 59 #include <net80211/ieee80211_var.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <net/bpf.h> 63 64 #include <dev/ic/rtwreg.h> 65 #include <dev/ic/rtwvar.h> 66 #include <dev/ic/rtwphyio.h> 67 #include <dev/ic/rtwphy.h> 68 69 #include <dev/ic/smc93cx6var.h> 70 71 static int rtw_rfprog_fallback = 0; 72 static int rtw_host_rfio = 0; 73 74 #ifdef RTW_DEBUG 75 int rtw_debug = 0; 76 static int rtw_rxbufs_limit = RTW_RXQLEN; 77 #endif /* RTW_DEBUG */ 78 79 #define NEXT_ATTACH_STATE(sc, state) do { \ 80 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 81 ("%s: attach state %s\n", __func__, #state)); \ 82 sc->sc_attach_state = state; \ 83 } while (0) 84 85 int rtw_dwelltime = 200; /* milliseconds */ 86 static struct ieee80211_cipher rtw_cipher_wep; 87 88 static void rtw_disable_interrupts(struct rtw_regs *); 89 static void rtw_enable_interrupts(struct rtw_softc *); 90 91 static int rtw_init(struct ifnet *); 92 93 static void rtw_start(struct ifnet *); 94 static void rtw_reset_oactive(struct rtw_softc *); 95 static struct mbuf *rtw_beacon_alloc(struct rtw_softc *, 96 struct ieee80211_node *); 97 static u_int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *); 98 99 static void rtw_io_enable(struct rtw_softc *, uint8_t, int); 100 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 101 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 102 const u_int8_t[IEEE80211_ADDR_LEN]); 103 static void rtw_key_update_end(struct ieee80211com *); 104 static void rtw_key_update_begin(struct ieee80211com *); 105 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 106 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 107 108 static void rtw_led_attach(struct rtw_led_state *, void *); 109 static void rtw_led_detach(struct rtw_led_state *); 110 static void rtw_led_init(struct rtw_regs *); 111 static void rtw_led_slowblink(void *); 112 static void rtw_led_fastblink(void *); 113 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 114 115 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 116 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 117 #ifdef RTW_DEBUG 118 static void rtw_dump_rings(struct rtw_softc *sc); 119 static void rtw_print_txdesc(struct rtw_softc *, const char *, 120 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 121 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 122 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 123 #endif /* RTW_DEBUG */ 124 #ifdef RTW_DIAG 125 static void rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln); 126 #endif /* RTW_DIAG */ 127 128 /* 129 * Setup sysctl(3) MIB, hw.rtw.* 130 * 131 * TBD condition CTLFLAG_PERMANENT on being a module or not 132 */ 133 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 134 { 135 int rc; 136 const struct sysctlnode *cnode, *rnode; 137 138 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 139 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 140 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 141 goto err; 142 143 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 144 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 145 "Realtek RTL818x 802.11 controls", 146 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 147 goto err; 148 149 #ifdef RTW_DEBUG 150 /* control debugging printfs */ 151 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 152 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 153 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 154 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 155 CTL_CREATE, CTL_EOL)) != 0) 156 goto err; 157 158 /* Limit rx buffers, for simulating resource exhaustion. */ 159 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 160 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 161 "rxbufs_limit", 162 SYSCTL_DESCR("Set rx buffers limit"), 163 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 164 CTL_CREATE, CTL_EOL)) != 0) 165 goto err; 166 167 #endif /* RTW_DEBUG */ 168 /* set fallback RF programming method */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfprog_fallback", 172 SYSCTL_DESCR("Set fallback RF programming method"), 173 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 174 CTL_CREATE, CTL_EOL)) != 0) 175 goto err; 176 177 /* force host to control RF I/O bus */ 178 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 179 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 180 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 181 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 182 CTL_CREATE, CTL_EOL)) != 0) 183 goto err; 184 185 return; 186 err: 187 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 188 } 189 190 static int 191 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 192 { 193 int error, t; 194 struct sysctlnode node; 195 196 node = *rnode; 197 t = *(int*)rnode->sysctl_data; 198 node.sysctl_data = &t; 199 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 200 if (error || newp == NULL) 201 return (error); 202 203 if (t < lower || t > upper) 204 return (EINVAL); 205 206 *(int*)rnode->sysctl_data = t; 207 208 return (0); 209 } 210 211 static int 212 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 213 { 214 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 215 __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 216 } 217 218 static int 219 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 220 { 221 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 222 } 223 224 #ifdef RTW_DEBUG 225 static int 226 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 227 { 228 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 229 0, RTW_DEBUG_MAX); 230 } 231 232 static int 233 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 234 { 235 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 236 0, RTW_RXQLEN); 237 } 238 239 static void 240 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 241 { 242 #define PRINTREG32(sc, reg) \ 243 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 244 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 245 dvname, reg, RTW_READ(regs, reg))) 246 247 #define PRINTREG16(sc, reg) \ 248 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 249 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 250 dvname, reg, RTW_READ16(regs, reg))) 251 252 #define PRINTREG8(sc, reg) \ 253 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 254 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 255 dvname, reg, RTW_READ8(regs, reg))) 256 257 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 258 259 PRINTREG32(regs, RTW_IDR0); 260 PRINTREG32(regs, RTW_IDR1); 261 PRINTREG32(regs, RTW_MAR0); 262 PRINTREG32(regs, RTW_MAR1); 263 PRINTREG32(regs, RTW_TSFTRL); 264 PRINTREG32(regs, RTW_TSFTRH); 265 PRINTREG32(regs, RTW_TLPDA); 266 PRINTREG32(regs, RTW_TNPDA); 267 PRINTREG32(regs, RTW_THPDA); 268 PRINTREG32(regs, RTW_TCR); 269 PRINTREG32(regs, RTW_RCR); 270 PRINTREG32(regs, RTW_TINT); 271 PRINTREG32(regs, RTW_TBDA); 272 PRINTREG32(regs, RTW_ANAPARM); 273 PRINTREG32(regs, RTW_BB); 274 PRINTREG32(regs, RTW_PHYCFG); 275 PRINTREG32(regs, RTW_WAKEUP0L); 276 PRINTREG32(regs, RTW_WAKEUP0H); 277 PRINTREG32(regs, RTW_WAKEUP1L); 278 PRINTREG32(regs, RTW_WAKEUP1H); 279 PRINTREG32(regs, RTW_WAKEUP2LL); 280 PRINTREG32(regs, RTW_WAKEUP2LH); 281 PRINTREG32(regs, RTW_WAKEUP2HL); 282 PRINTREG32(regs, RTW_WAKEUP2HH); 283 PRINTREG32(regs, RTW_WAKEUP3LL); 284 PRINTREG32(regs, RTW_WAKEUP3LH); 285 PRINTREG32(regs, RTW_WAKEUP3HL); 286 PRINTREG32(regs, RTW_WAKEUP3HH); 287 PRINTREG32(regs, RTW_WAKEUP4LL); 288 PRINTREG32(regs, RTW_WAKEUP4LH); 289 PRINTREG32(regs, RTW_WAKEUP4HL); 290 PRINTREG32(regs, RTW_WAKEUP4HH); 291 PRINTREG32(regs, RTW_DK0); 292 PRINTREG32(regs, RTW_DK1); 293 PRINTREG32(regs, RTW_DK2); 294 PRINTREG32(regs, RTW_DK3); 295 PRINTREG32(regs, RTW_RETRYCTR); 296 PRINTREG32(regs, RTW_RDSAR); 297 PRINTREG32(regs, RTW_FER); 298 PRINTREG32(regs, RTW_FEMR); 299 PRINTREG32(regs, RTW_FPSR); 300 PRINTREG32(regs, RTW_FFER); 301 302 /* 16-bit registers */ 303 PRINTREG16(regs, RTW_BRSR); 304 PRINTREG16(regs, RTW_IMR); 305 PRINTREG16(regs, RTW_ISR); 306 PRINTREG16(regs, RTW_BCNITV); 307 PRINTREG16(regs, RTW_ATIMWND); 308 PRINTREG16(regs, RTW_BINTRITV); 309 PRINTREG16(regs, RTW_ATIMTRITV); 310 PRINTREG16(regs, RTW_CRC16ERR); 311 PRINTREG16(regs, RTW_CRC0); 312 PRINTREG16(regs, RTW_CRC1); 313 PRINTREG16(regs, RTW_CRC2); 314 PRINTREG16(regs, RTW_CRC3); 315 PRINTREG16(regs, RTW_CRC4); 316 PRINTREG16(regs, RTW_CWR); 317 318 /* 8-bit registers */ 319 PRINTREG8(regs, RTW_CR); 320 PRINTREG8(regs, RTW_9346CR); 321 PRINTREG8(regs, RTW_CONFIG0); 322 PRINTREG8(regs, RTW_CONFIG1); 323 PRINTREG8(regs, RTW_CONFIG2); 324 PRINTREG8(regs, RTW_MSR); 325 PRINTREG8(regs, RTW_CONFIG3); 326 PRINTREG8(regs, RTW_CONFIG4); 327 PRINTREG8(regs, RTW_TESTR); 328 PRINTREG8(regs, RTW_PSR); 329 PRINTREG8(regs, RTW_SCR); 330 PRINTREG8(regs, RTW_PHYDELAY); 331 PRINTREG8(regs, RTW_CRCOUNT); 332 PRINTREG8(regs, RTW_PHYADDR); 333 PRINTREG8(regs, RTW_PHYDATAW); 334 PRINTREG8(regs, RTW_PHYDATAR); 335 PRINTREG8(regs, RTW_CONFIG5); 336 PRINTREG8(regs, RTW_TPPOLL); 337 338 PRINTREG16(regs, RTW_BSSID16); 339 PRINTREG32(regs, RTW_BSSID32); 340 #undef PRINTREG32 341 #undef PRINTREG16 342 #undef PRINTREG8 343 } 344 #endif /* RTW_DEBUG */ 345 346 void 347 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 348 { 349 struct rtw_regs *regs = &sc->sc_regs; 350 351 uint32_t tcr; 352 tcr = RTW_READ(regs, RTW_TCR); 353 tcr &= ~RTW_TCR_LBK_MASK; 354 if (enable) 355 tcr |= RTW_TCR_LBK_CONT; 356 else 357 tcr |= RTW_TCR_LBK_NORMAL; 358 RTW_WRITE(regs, RTW_TCR, tcr); 359 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 360 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 361 rtw_txdac_enable(sc, !enable); 362 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 363 rtw_set_access(regs, RTW_ACCESS_NONE); 364 } 365 366 #ifdef RTW_DEBUG 367 static const char * 368 rtw_access_string(enum rtw_access access) 369 { 370 switch (access) { 371 case RTW_ACCESS_NONE: 372 return "none"; 373 case RTW_ACCESS_CONFIG: 374 return "config"; 375 case RTW_ACCESS_ANAPARM: 376 return "anaparm"; 377 default: 378 return "unknown"; 379 } 380 } 381 #endif /* RTW_DEBUG */ 382 383 static void 384 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 385 { 386 KASSERT(/* naccess >= RTW_ACCESS_NONE && */ 387 naccess <= RTW_ACCESS_ANAPARM); 388 KASSERT(/* regs->r_access >= RTW_ACCESS_NONE && */ 389 regs->r_access <= RTW_ACCESS_ANAPARM); 390 391 if (naccess == regs->r_access) 392 return; 393 394 switch (naccess) { 395 case RTW_ACCESS_NONE: 396 switch (regs->r_access) { 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 /*FALLTHROUGH*/ 400 case RTW_ACCESS_CONFIG: 401 rtw_config0123_enable(regs, 0); 402 /*FALLTHROUGH*/ 403 case RTW_ACCESS_NONE: 404 break; 405 } 406 break; 407 case RTW_ACCESS_CONFIG: 408 switch (regs->r_access) { 409 case RTW_ACCESS_NONE: 410 rtw_config0123_enable(regs, 1); 411 /*FALLTHROUGH*/ 412 case RTW_ACCESS_CONFIG: 413 break; 414 case RTW_ACCESS_ANAPARM: 415 rtw_anaparm_enable(regs, 0); 416 break; 417 } 418 break; 419 case RTW_ACCESS_ANAPARM: 420 switch (regs->r_access) { 421 case RTW_ACCESS_NONE: 422 rtw_config0123_enable(regs, 1); 423 /*FALLTHROUGH*/ 424 case RTW_ACCESS_CONFIG: 425 rtw_anaparm_enable(regs, 1); 426 /*FALLTHROUGH*/ 427 case RTW_ACCESS_ANAPARM: 428 break; 429 } 430 break; 431 } 432 } 433 434 void 435 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 436 { 437 rtw_set_access1(regs, access); 438 RTW_DPRINTF(RTW_DEBUG_ACCESS, 439 ("%s: access %s -> %s\n", __func__, 440 rtw_access_string(regs->r_access), 441 rtw_access_string(access))); 442 regs->r_access = access; 443 } 444 445 /* 446 * Enable registers, switch register banks. 447 */ 448 void 449 rtw_config0123_enable(struct rtw_regs *regs, int enable) 450 { 451 uint8_t ecr; 452 ecr = RTW_READ8(regs, RTW_9346CR); 453 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 454 if (enable) 455 ecr |= RTW_9346CR_EEM_CONFIG; 456 else { 457 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 458 ecr |= RTW_9346CR_EEM_NORMAL; 459 } 460 RTW_WRITE8(regs, RTW_9346CR, ecr); 461 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 462 } 463 464 /* requires rtw_config0123_enable(, 1) */ 465 void 466 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 467 { 468 uint8_t cfg3; 469 470 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 471 cfg3 |= RTW_CONFIG3_CLKRUNEN; 472 if (enable) 473 cfg3 |= RTW_CONFIG3_PARMEN; 474 else 475 cfg3 &= ~RTW_CONFIG3_PARMEN; 476 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 477 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 478 } 479 480 /* requires rtw_anaparm_enable(, 1) */ 481 void 482 rtw_txdac_enable(struct rtw_softc *sc, int enable) 483 { 484 uint32_t anaparm; 485 struct rtw_regs *regs = &sc->sc_regs; 486 487 anaparm = RTW_READ(regs, RTW_ANAPARM); 488 if (enable) 489 anaparm &= ~RTW_ANAPARM_TXDACOFF; 490 else 491 anaparm |= RTW_ANAPARM_TXDACOFF; 492 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 493 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 494 } 495 496 static inline int 497 rtw_chip_reset1(struct rtw_regs *regs, device_t dev) 498 { 499 uint8_t cr; 500 int i; 501 502 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 503 504 RTW_WBR(regs, RTW_CR, RTW_CR); 505 506 for (i = 0; i < 1000; i++) { 507 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 508 RTW_DPRINTF(RTW_DEBUG_RESET, 509 ("%s: reset in %dus\n", device_xname(dev), i)); 510 return 0; 511 } 512 RTW_RBR(regs, RTW_CR, RTW_CR); 513 DELAY(10); /* 10us */ 514 } 515 516 aprint_error_dev(dev, "reset failed\n"); 517 return ETIMEDOUT; 518 } 519 520 static inline int 521 rtw_chip_reset(struct rtw_regs *regs, device_t dev) 522 { 523 uint32_t tcr; 524 525 /* from Linux driver */ 526 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 527 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK); 528 529 RTW_WRITE(regs, RTW_TCR, tcr); 530 531 RTW_WBW(regs, RTW_CR, RTW_TCR); 532 533 return rtw_chip_reset1(regs, dev); 534 } 535 536 static int 537 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen) 538 { 539 struct ieee80211_key keycopy; 540 541 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 542 543 keycopy = *k; 544 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 545 546 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, hdrlen); 547 } 548 549 static int 550 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 551 { 552 struct rtw_softc *sc = ic->ic_ifp->if_softc; 553 554 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, 555 k->wk_keyix)); 556 557 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID); 558 559 if (k->wk_keylen != 0 && 560 k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 561 sc->sc_flags &= ~RTW_F_DK_VALID; 562 563 return 1; 564 } 565 566 static int 567 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 568 const u_int8_t mac[IEEE80211_ADDR_LEN]) 569 { 570 struct rtw_softc *sc = ic->ic_ifp->if_softc; 571 572 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 573 574 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID); 575 576 sc->sc_flags &= ~RTW_F_DK_VALID; 577 578 return 1; 579 } 580 581 static void 582 rtw_key_update_begin(struct ieee80211com *ic) 583 { 584 #ifdef RTW_DEBUG 585 struct ifnet *ifp = ic->ic_ifp; 586 struct rtw_softc *sc = ifp->if_softc; 587 #endif 588 589 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 590 } 591 592 static void 593 rtw_tx_kick(struct rtw_regs *regs, uint8_t ringsel) 594 { 595 uint8_t tppoll; 596 597 tppoll = RTW_READ8(regs, RTW_TPPOLL); 598 tppoll &= ~RTW_TPPOLL_SALL; 599 tppoll |= ringsel & RTW_TPPOLL_ALL; 600 RTW_WRITE8(regs, RTW_TPPOLL, tppoll); 601 RTW_SYNC(regs, RTW_TPPOLL, RTW_TPPOLL); 602 } 603 604 static void 605 rtw_key_update_end(struct ieee80211com *ic) 606 { 607 struct ifnet *ifp = ic->ic_ifp; 608 struct rtw_softc *sc = ifp->if_softc; 609 610 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 611 612 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 || 613 !device_is_active(sc->sc_dev)) 614 return; 615 616 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 617 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 618 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 619 (ifp->if_flags & IFF_RUNNING) != 0); 620 } 621 622 static bool 623 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k) 624 { 625 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 626 return false; 627 628 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) || 629 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13); 630 } 631 632 static void 633 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 634 { 635 uint8_t psr, scr; 636 int i, keylen = 0; 637 struct rtw_regs *regs; 638 union rtw_keys *rk; 639 640 regs = &sc->sc_regs; 641 rk = &sc->sc_keys; 642 643 (void)memset(rk, 0, sizeof(*rk)); 644 645 /* Temporarily use software crypto for all keys. */ 646 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 647 if (wk[i].wk_cipher == &rtw_cipher_wep) 648 wk[i].wk_cipher = &ieee80211_cipher_wep; 649 } 650 651 rtw_set_access(regs, RTW_ACCESS_CONFIG); 652 653 psr = RTW_READ8(regs, RTW_PSR); 654 scr = RTW_READ8(regs, RTW_SCR); 655 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 656 657 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 658 goto out; 659 660 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 661 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i])) 662 continue; 663 if (i == txkey) { 664 keylen = wk[i].wk_keylen; 665 break; 666 } 667 keylen = MAX(keylen, wk[i].wk_keylen); 668 } 669 670 if (keylen == 5) 671 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON; 672 else if (keylen == 13) 673 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON; 674 675 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 676 if (wk[i].wk_keylen != keylen || 677 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 678 continue; 679 /* h/w will decrypt, s/w still strips headers */ 680 wk[i].wk_cipher = &rtw_cipher_wep; 681 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 682 } 683 684 out: 685 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 686 687 bus_space_write_region_stream_4(regs->r_bt, regs->r_bh, 688 RTW_DK0, rk->rk_words, __arraycount(rk->rk_words)); 689 690 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 691 BUS_SPACE_BARRIER_SYNC); 692 693 RTW_DPRINTF(RTW_DEBUG_KEY, 694 ("%s.%d: scr %02" PRIx8 ", keylen %d\n", __func__, __LINE__, scr, 695 keylen)); 696 697 RTW_WBW(regs, RTW_DK0, RTW_PSR); 698 RTW_WRITE8(regs, RTW_PSR, psr); 699 RTW_WBW(regs, RTW_PSR, RTW_SCR); 700 RTW_WRITE8(regs, RTW_SCR, scr); 701 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 702 rtw_set_access(regs, RTW_ACCESS_NONE); 703 sc->sc_flags |= RTW_F_DK_VALID; 704 } 705 706 static inline int 707 rtw_recall_eeprom(struct rtw_regs *regs, device_t dev) 708 { 709 int i; 710 uint8_t ecr; 711 712 ecr = RTW_READ8(regs, RTW_9346CR); 713 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 714 RTW_WRITE8(regs, RTW_9346CR, ecr); 715 716 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 717 718 /* wait 25ms for completion */ 719 for (i = 0; i < 250; i++) { 720 ecr = RTW_READ8(regs, RTW_9346CR); 721 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 722 RTW_DPRINTF(RTW_DEBUG_RESET, 723 ("%s: recall EEPROM in %dus\n", device_xname(dev), 724 i * 100)); 725 return 0; 726 } 727 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 728 DELAY(100); 729 } 730 aprint_error_dev(dev, "recall EEPROM failed\n"); 731 return ETIMEDOUT; 732 } 733 734 static inline int 735 rtw_reset(struct rtw_softc *sc) 736 { 737 int rc; 738 uint8_t config1; 739 740 sc->sc_flags &= ~RTW_F_DK_VALID; 741 742 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev)) != 0) 743 return rc; 744 745 rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev); 746 747 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 748 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 749 /* TBD turn off maximum power saving? */ 750 751 return 0; 752 } 753 754 static inline int 755 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 756 u_int ndescs) 757 { 758 int i, rc = 0; 759 for (i = 0; i < ndescs; i++) { 760 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 761 0, 0, &descs[i].ts_dmamap); 762 if (rc != 0) 763 break; 764 } 765 return rc; 766 } 767 768 static inline int 769 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 770 u_int ndescs) 771 { 772 int i, rc = 0; 773 for (i = 0; i < ndescs; i++) { 774 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 775 &descs[i].rs_dmamap); 776 if (rc != 0) 777 break; 778 } 779 return rc; 780 } 781 782 static inline void 783 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 784 u_int ndescs) 785 { 786 int i; 787 for (i = 0; i < ndescs; i++) { 788 if (descs[i].rs_dmamap != NULL) 789 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 790 } 791 } 792 793 static inline void 794 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 795 u_int ndescs) 796 { 797 int i; 798 for (i = 0; i < ndescs; i++) { 799 if (descs[i].ts_dmamap != NULL) 800 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 801 } 802 } 803 804 static inline void 805 rtw_srom_free(struct rtw_srom *sr) 806 { 807 sr->sr_size = 0; 808 if (sr->sr_content == NULL) 809 return; 810 free(sr->sr_content, M_DEVBUF); 811 sr->sr_content = NULL; 812 } 813 814 static void 815 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, 816 uint8_t *cs_threshold, enum rtw_rfchipid *rfchipid, uint32_t *rcr) 817 { 818 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 819 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 820 *rcr |= RTW_RCR_ENCS1; 821 *rfchipid = RTW_RFCHIPID_PHILIPS; 822 } 823 824 static int 825 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 826 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 827 device_t dev) 828 { 829 int i; 830 const char *rfname, *paname; 831 char scratch[sizeof("unknown 0xXX")]; 832 uint16_t srom_version; 833 834 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 835 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 836 837 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 838 839 if (srom_version <= 0x0101) { 840 aprint_error_dev(dev, 841 "SROM version %d.%d is not understood, " 842 "limping along with defaults\n", 843 srom_version >> 8, srom_version & 0xff); 844 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 845 return 0; 846 } else { 847 aprint_verbose_dev(dev, "SROM version %d.%d\n", 848 srom_version >> 8, srom_version & 0xff); 849 } 850 851 uint8_t mac[IEEE80211_ADDR_LEN]; 852 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 853 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 854 __USE(mac); 855 856 RTW_DPRINTF(RTW_DEBUG_ATTACH, 857 ("%s: EEPROM MAC %s\n", device_xname(dev), ether_sprintf(mac))); 858 859 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 860 861 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 862 *flags |= RTW_F_ANTDIV; 863 864 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 865 * to be reversed. 866 */ 867 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 868 *flags |= RTW_F_DIGPHY; 869 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 870 *flags |= RTW_F_DFLANTB; 871 872 *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), 873 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 874 875 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0) 876 *flags |= RTW_C_RXWEP_104; 877 878 *flags |= RTW_C_RXWEP_40; /* XXX */ 879 880 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 881 switch (*rfchipid) { 882 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 883 rfname = "GCT GRF5101"; 884 paname = "Winspring WS9901"; 885 break; 886 case RTW_RFCHIPID_MAXIM: 887 rfname = "Maxim MAX2820"; /* guess */ 888 paname = "Maxim MAX2422"; /* guess */ 889 break; 890 case RTW_RFCHIPID_INTERSIL: 891 rfname = "Intersil HFA3873"; /* guess */ 892 paname = "Intersil <unknown>"; 893 break; 894 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 895 rfname = "Philips SA2400A"; 896 paname = "Philips SA2411"; 897 break; 898 case RTW_RFCHIPID_RFMD: 899 /* this is the same front-end as an atw(4)! */ 900 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 901 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 902 "SYN: Silicon Labs Si4126"; /* inferred from 903 * reference driver 904 */ 905 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 906 break; 907 case RTW_RFCHIPID_RESERVED: 908 rfname = paname = "reserved"; 909 break; 910 default: 911 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 912 rfname = paname = scratch; 913 } 914 aprint_normal_dev(dev, "RF: %s, PA: %s\n", rfname, paname); 915 916 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 917 case RTW_CONFIG0_GL_USA: 918 case _RTW_CONFIG0_GL_USA: 919 *locale = RTW_LOCALE_USA; 920 break; 921 case RTW_CONFIG0_GL_EUROPE: 922 *locale = RTW_LOCALE_EUROPE; 923 break; 924 case RTW_CONFIG0_GL_JAPAN: 925 *locale = RTW_LOCALE_JAPAN; 926 break; 927 default: 928 *locale = RTW_LOCALE_UNKNOWN; 929 break; 930 } 931 return 0; 932 } 933 934 /* Returns -1 on failure. */ 935 static int 936 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 937 device_t dev) 938 { 939 int rc; 940 struct seeprom_descriptor sd; 941 uint8_t ecr; 942 943 (void)memset(&sd, 0, sizeof(sd)); 944 945 ecr = RTW_READ8(regs, RTW_9346CR); 946 947 if ((flags & RTW_F_9356SROM) != 0) { 948 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", 949 device_xname(dev))); 950 sr->sr_size = 256; 951 sd.sd_chip = C56_66; 952 } else { 953 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", 954 device_xname(dev))); 955 sr->sr_size = 128; 956 sd.sd_chip = C46; 957 } 958 959 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 960 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 961 ecr |= RTW_9346CR_EEM_PROGRAM; 962 963 RTW_WRITE8(regs, RTW_9346CR, ecr); 964 965 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 966 967 if (sr->sr_content == NULL) { 968 aprint_error_dev(dev, "unable to allocate SROM buffer\n"); 969 return ENOMEM; 970 } 971 972 (void)memset(sr->sr_content, 0, sr->sr_size); 973 974 /* RTL8180 has a single 8-bit register for controlling the 975 * 93cx6 SROM. There is no "ready" bit. The RTL8180 976 * input/output sense is the reverse of read_seeprom's. 977 */ 978 sd.sd_tag = regs->r_bt; 979 sd.sd_bsh = regs->r_bh; 980 sd.sd_regsize = 1; 981 sd.sd_control_offset = RTW_9346CR; 982 sd.sd_status_offset = RTW_9346CR; 983 sd.sd_dataout_offset = RTW_9346CR; 984 sd.sd_CK = RTW_9346CR_EESK; 985 sd.sd_CS = RTW_9346CR_EECS; 986 sd.sd_DI = RTW_9346CR_EEDO; 987 sd.sd_DO = RTW_9346CR_EEDI; 988 /* make read_seeprom enter EEPROM read/write mode */ 989 sd.sd_MS = ecr; 990 sd.sd_RDY = 0; 991 992 /* TBD bus barriers */ 993 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 994 aprint_error_dev(dev, "could not read SROM\n"); 995 free(sr->sr_content, M_DEVBUF); 996 sr->sr_content = NULL; 997 return -1; /* XXX */ 998 } 999 1000 /* end EEPROM read/write mode */ 1001 RTW_WRITE8(regs, RTW_9346CR, 1002 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 1003 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 1004 1005 if ((rc = rtw_recall_eeprom(regs, dev)) != 0) 1006 return rc; 1007 1008 #ifdef RTW_DEBUG 1009 { 1010 int i; 1011 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1012 ("\n%s: serial ROM:\n\t", device_xname(dev))); 1013 for (i = 0; i < sr->sr_size/2; i++) { 1014 if (((i % 8) == 0) && (i != 0)) 1015 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 1016 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1017 (" %04x", sr->sr_content[i])); 1018 } 1019 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 1020 } 1021 #endif /* RTW_DEBUG */ 1022 return 0; 1023 } 1024 1025 static void 1026 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 1027 device_t dev) 1028 { 1029 uint8_t cfg4; 1030 const char *method; 1031 1032 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 1033 1034 switch (rfchipid) { 1035 default: 1036 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 1037 method = "fallback"; 1038 break; 1039 case RTW_RFCHIPID_INTERSIL: 1040 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1041 method = "Intersil"; 1042 break; 1043 case RTW_RFCHIPID_PHILIPS: 1044 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1045 method = "Philips"; 1046 break; 1047 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1048 case RTW_RFCHIPID_RFMD: 1049 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1050 method = "RFMD"; 1051 break; 1052 } 1053 1054 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1055 1056 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1057 1058 #ifdef RTW_DEBUG 1059 RTW_DPRINTF(RTW_DEBUG_INIT, 1060 ("%s: %s RF programming method, %#02x\n", device_xname(dev), method, 1061 RTW_READ8(regs, RTW_CONFIG4))); 1062 #else 1063 __USE(method); 1064 #endif 1065 } 1066 1067 static inline void 1068 rtw_init_channels(enum rtw_locale locale, 1069 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], device_t dev) 1070 { 1071 int i; 1072 const char *name = NULL; 1073 #define ADD_CHANNEL(_chans, _chan) do { \ 1074 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1075 (*_chans)[_chan].ic_freq = \ 1076 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1077 } while (0) 1078 1079 switch (locale) { 1080 case RTW_LOCALE_USA: /* 1-11 */ 1081 name = "USA"; 1082 for (i = 1; i <= 11; i++) 1083 ADD_CHANNEL(chans, i); 1084 break; 1085 case RTW_LOCALE_JAPAN: /* 1-14 */ 1086 name = "Japan"; 1087 ADD_CHANNEL(chans, 14); 1088 for (i = 1; i <= 14; i++) 1089 ADD_CHANNEL(chans, i); 1090 break; 1091 case RTW_LOCALE_EUROPE: /* 1-13 */ 1092 name = "Europe"; 1093 for (i = 1; i <= 13; i++) 1094 ADD_CHANNEL(chans, i); 1095 break; 1096 default: /* 10-11 allowed by most countries */ 1097 name = "<unknown>"; 1098 for (i = 10; i <= 11; i++) 1099 ADD_CHANNEL(chans, i); 1100 break; 1101 } 1102 aprint_normal_dev(dev, "Geographic Location %s\n", name); 1103 #undef ADD_CHANNEL 1104 } 1105 1106 1107 static inline void 1108 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale) 1109 { 1110 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1111 1112 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1113 case RTW_CONFIG0_GL_USA: 1114 case _RTW_CONFIG0_GL_USA: 1115 *locale = RTW_LOCALE_USA; 1116 break; 1117 case RTW_CONFIG0_GL_JAPAN: 1118 *locale = RTW_LOCALE_JAPAN; 1119 break; 1120 case RTW_CONFIG0_GL_EUROPE: 1121 *locale = RTW_LOCALE_EUROPE; 1122 break; 1123 default: 1124 *locale = RTW_LOCALE_UNKNOWN; 1125 break; 1126 } 1127 } 1128 1129 static inline int 1130 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1131 device_t dev) 1132 { 1133 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1134 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1135 }; 1136 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1137 idr1 = RTW_READ(regs, RTW_IDR1); 1138 1139 (*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7)); 1140 (*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15)); 1141 (*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23)); 1142 (*addr)[3] = __SHIFTOUT(idr0, __BITS(24 ,31)); 1143 1144 (*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7)); 1145 (*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15)); 1146 1147 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1148 aprint_error_dev(dev, 1149 "could not get mac address, attach failed\n"); 1150 return ENXIO; 1151 } 1152 1153 aprint_normal_dev(dev, "802.11 address %s\n", ether_sprintf(*addr)); 1154 1155 return 0; 1156 } 1157 1158 static uint8_t 1159 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1160 struct ieee80211_channel *chan) 1161 { 1162 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1163 KASSERT(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14); 1164 return RTW_SR_GET(sr, idx); 1165 } 1166 1167 static void 1168 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1169 { 1170 int pri; 1171 /* nfree: the number of free descriptors in each ring. 1172 * The beacon ring is a special case: I do not let the 1173 * driver use all of the descriptors on the beacon ring. 1174 * The reasons are two-fold: 1175 * 1176 * (1) A BEACON descriptor's OWN bit is (apparently) not 1177 * updated, so the driver cannot easily know if the descriptor 1178 * belongs to it, or if it is racing the NIC. If the NIC 1179 * does not OWN every descriptor, then the driver can safely 1180 * update the descriptors when RTW_TBDA points at tdb_next. 1181 * 1182 * (2) I hope that the NIC will process more than one BEACON 1183 * descriptor in a single beacon interval, since that will 1184 * enable multiple-BSS support. Since the NIC does not 1185 * clear the OWN bit, there is no natural place for it to 1186 * stop processing BEACON desciptors. Maybe it will *not* 1187 * stop processing them! I do not want to chance the NIC 1188 * looping around and around a saturated beacon ring, so 1189 * I will leave one descriptor unOWNed at all times. 1190 */ 1191 u_int nfree[RTW_NTXPRI] = 1192 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, 1193 RTW_NTXDESCBCN - 1}; 1194 1195 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1196 tdb[pri].tdb_nfree = nfree[pri]; 1197 tdb[pri].tdb_next = 0; 1198 } 1199 } 1200 1201 static int 1202 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1203 { 1204 int i; 1205 struct rtw_txsoft *ts; 1206 1207 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1208 SIMPLEQ_INIT(&tsb->tsb_freeq); 1209 for (i = 0; i < tsb->tsb_ndesc; i++) { 1210 ts = &tsb->tsb_desc[i]; 1211 ts->ts_mbuf = NULL; 1212 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1213 } 1214 tsb->tsb_tx_timer = 0; 1215 return 0; 1216 } 1217 1218 static void 1219 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1220 { 1221 int pri; 1222 for (pri = 0; pri < RTW_NTXPRI; pri++) 1223 rtw_txsoft_blk_init(&tsb[pri]); 1224 } 1225 1226 static inline void 1227 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1228 { 1229 KASSERT(nsync <= rdb->rdb_ndesc); 1230 /* sync to end of ring */ 1231 if (desc0 + nsync > rdb->rdb_ndesc) { 1232 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1233 offsetof(struct rtw_descs, hd_rx[desc0]), 1234 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1235 nsync -= (rdb->rdb_ndesc - desc0); 1236 desc0 = 0; 1237 } 1238 1239 KASSERT(desc0 < rdb->rdb_ndesc); 1240 KASSERT(nsync <= rdb->rdb_ndesc); 1241 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1242 1243 /* sync what remains */ 1244 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1245 offsetof(struct rtw_descs, hd_rx[desc0]), 1246 sizeof(struct rtw_rxdesc) * nsync, ops); 1247 } 1248 1249 static void 1250 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1251 { 1252 /* sync to end of ring */ 1253 if (desc0 + nsync > tdb->tdb_ndesc) { 1254 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1255 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1256 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1257 ops); 1258 nsync -= (tdb->tdb_ndesc - desc0); 1259 desc0 = 0; 1260 } 1261 1262 /* sync what remains */ 1263 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1264 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1265 sizeof(struct rtw_txdesc) * nsync, ops); 1266 } 1267 1268 static void 1269 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1270 { 1271 int pri; 1272 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1273 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1274 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1275 } 1276 } 1277 1278 static void 1279 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1280 { 1281 int i; 1282 struct rtw_rxsoft *rs; 1283 1284 for (i = 0; i < RTW_RXQLEN; i++) { 1285 rs = &desc[i]; 1286 if (rs->rs_mbuf == NULL) 1287 continue; 1288 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1289 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1290 bus_dmamap_unload(dmat, rs->rs_dmamap); 1291 m_freem(rs->rs_mbuf); 1292 rs->rs_mbuf = NULL; 1293 } 1294 } 1295 1296 static inline int 1297 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1298 { 1299 int rc; 1300 struct mbuf *m; 1301 1302 MGETHDR(m, M_DONTWAIT, MT_DATA); 1303 if (m == NULL) 1304 return ENOBUFS; 1305 1306 MCLGET(m, M_DONTWAIT); 1307 if ((m->m_flags & M_EXT) == 0) { 1308 m_freem(m); 1309 return ENOBUFS; 1310 } 1311 1312 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1313 1314 if (rs->rs_mbuf != NULL) 1315 bus_dmamap_unload(dmat, rs->rs_dmamap); 1316 1317 rs->rs_mbuf = NULL; 1318 1319 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1320 if (rc != 0) { 1321 m_freem(m); 1322 return -1; 1323 } 1324 1325 rs->rs_mbuf = m; 1326 1327 return 0; 1328 } 1329 1330 static int 1331 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1332 int *ndesc, device_t dev) 1333 { 1334 int i, rc = 0; 1335 struct rtw_rxsoft *rs; 1336 1337 for (i = 0; i < RTW_RXQLEN; i++) { 1338 rs = &desc[i]; 1339 /* we're in rtw_init, so there should be no mbufs allocated */ 1340 KASSERT(rs->rs_mbuf == NULL); 1341 #ifdef RTW_DEBUG 1342 if (i == rtw_rxbufs_limit) { 1343 aprint_error_dev(dev, "TEST hit %d-buffer limit\n", i); 1344 rc = ENOBUFS; 1345 break; 1346 } 1347 #endif /* RTW_DEBUG */ 1348 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1349 aprint_error_dev(dev, 1350 "rtw_rxsoft_alloc failed, %d buffers, rc %d\n", 1351 i, rc); 1352 break; 1353 } 1354 } 1355 *ndesc = i; 1356 return rc; 1357 } 1358 1359 static inline void 1360 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1361 int idx, int kick) 1362 { 1363 int is_last = (idx == rdb->rdb_ndesc - 1); 1364 uint32_t ctl, octl, obuf; 1365 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1366 1367 /* sync the mbuf before the descriptor */ 1368 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1369 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1370 1371 obuf = rd->rd_buf; 1372 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1373 1374 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1375 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1376 1377 if (is_last) 1378 ctl |= RTW_RXCTL_EOR; 1379 1380 octl = rd->rd_ctl; 1381 rd->rd_ctl = htole32(ctl); 1382 1383 #ifdef RTW_DEBUG 1384 RTW_DPRINTF( 1385 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1386 : RTW_DEBUG_RECV_DESC, 1387 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1388 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1389 le32toh(rd->rd_ctl))); 1390 #else 1391 __USE(octl); 1392 __USE(obuf); 1393 #endif 1394 1395 /* sync the descriptor */ 1396 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1397 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1398 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1399 } 1400 1401 static void 1402 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1403 { 1404 int i; 1405 struct rtw_rxsoft *rs; 1406 1407 for (i = 0; i < rdb->rdb_ndesc; i++) { 1408 rs = &ctl[i]; 1409 rtw_rxdesc_init(rdb, rs, i, kick); 1410 } 1411 } 1412 1413 static void 1414 rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable) 1415 { 1416 struct rtw_regs *regs = &sc->sc_regs; 1417 uint8_t cr; 1418 1419 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1420 enable ? "enable" : "disable", flags)); 1421 1422 cr = RTW_READ8(regs, RTW_CR); 1423 1424 /* XXX reference source does not enable MULRW */ 1425 /* enable PCI Read/Write Multiple */ 1426 cr |= RTW_CR_MULRW; 1427 1428 /* The receive engine will always start at RDSAR. */ 1429 if (enable && (flags & ~cr & RTW_CR_RE)) { 1430 struct rtw_rxdesc_blk *rdb; 1431 rdb = &sc->sc_rxdesc_blk; 1432 rdb->rdb_next = 0; 1433 } 1434 1435 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1436 if (enable) 1437 cr |= flags; 1438 else 1439 cr &= ~flags; 1440 RTW_WRITE8(regs, RTW_CR, cr); 1441 RTW_SYNC(regs, RTW_CR, RTW_CR); 1442 1443 #ifdef RTW_DIAG 1444 if (cr & RTW_CR_TE) 1445 rtw_txring_fixup(sc, __func__, __LINE__); 1446 #endif 1447 if (cr & RTW_CR_TE) { 1448 rtw_tx_kick(&sc->sc_regs, 1449 RTW_TPPOLL_HPQ | RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ); 1450 } 1451 } 1452 1453 static void 1454 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1455 { 1456 #define IS_BEACON(__fc0) \ 1457 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1458 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1459 1460 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1461 * hardware -> net80211 1462 */ 1463 u_int next, nproc = 0; 1464 int hwrate, len, rate, rssi, sq; 1465 uint32_t hrssi, hstat, htsfth, htsftl; 1466 struct rtw_rxdesc *rd; 1467 struct rtw_rxsoft *rs; 1468 struct rtw_rxdesc_blk *rdb; 1469 struct mbuf *m; 1470 struct ifnet *ifp = &sc->sc_if; 1471 1472 struct ieee80211_node *ni; 1473 struct ieee80211_frame_min *wh; 1474 1475 rdb = &sc->sc_rxdesc_blk; 1476 1477 for (next = rdb->rdb_next; ; next = rdb->rdb_next) { 1478 KASSERT(next < rdb->rdb_ndesc); 1479 1480 rtw_rxdescs_sync(rdb, next, 1, 1481 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1482 rd = &rdb->rdb_desc[next]; 1483 rs = &sc->sc_rxsoft[next]; 1484 1485 hstat = le32toh(rd->rd_stat); 1486 hrssi = le32toh(rd->rd_rssi); 1487 htsfth = le32toh(rd->rd_tsfth); 1488 htsftl = le32toh(rd->rd_tsftl); 1489 1490 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1491 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1492 __func__, next, hstat, hrssi, htsfth, htsftl)); 1493 1494 ++nproc; 1495 1496 /* still belongs to NIC */ 1497 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1498 rtw_rxdescs_sync(rdb, next, 1, BUS_DMASYNC_PREREAD); 1499 break; 1500 } 1501 1502 /* ieee80211_input() might reset the receive engine 1503 * (e.g. by indirectly calling rtw_tune()), so save 1504 * the next pointer here and retrieve it again on 1505 * the next round. 1506 */ 1507 rdb->rdb_next = (next + 1) % rdb->rdb_ndesc; 1508 1509 #ifdef RTW_DEBUG 1510 #define PRINTSTAT(flag) do { \ 1511 if ((hstat & flag) != 0) { \ 1512 printf("%s" #flag, delim); \ 1513 delim = ","; \ 1514 } \ 1515 } while (0) 1516 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1517 const char *delim = "<"; 1518 printf("%s: ", device_xname(sc->sc_dev)); 1519 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1520 printf("status %08x", hstat); 1521 PRINTSTAT(RTW_RXSTAT_SPLCP); 1522 PRINTSTAT(RTW_RXSTAT_MAR); 1523 PRINTSTAT(RTW_RXSTAT_PAR); 1524 PRINTSTAT(RTW_RXSTAT_BAR); 1525 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1526 PRINTSTAT(RTW_RXSTAT_CRC32); 1527 PRINTSTAT(RTW_RXSTAT_ICV); 1528 printf(">, "); 1529 } 1530 } 1531 #endif /* RTW_DEBUG */ 1532 1533 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1534 aprint_error_dev(sc->sc_dev, 1535 "DMA error/FIFO overflow %08" PRIx32 ", " 1536 "rx descriptor %d\n", hstat, next); 1537 ifp->if_ierrors++; 1538 goto next; 1539 } 1540 1541 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); 1542 if (len < IEEE80211_MIN_LEN) { 1543 sc->sc_ic.ic_stats.is_rx_tooshort++; 1544 goto next; 1545 } 1546 if (len > rs->rs_mbuf->m_len) { 1547 aprint_error_dev(sc->sc_dev, 1548 "rx frame too long, %d > %d, %08" PRIx32 1549 ", desc %d\n", 1550 len, rs->rs_mbuf->m_len, hstat, next); 1551 ifp->if_ierrors++; 1552 goto next; 1553 } 1554 1555 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); 1556 if (hwrate >= __arraycount(ratetbl)) { 1557 aprint_error_dev(sc->sc_dev, 1558 "unknown rate #%" __PRIuBITS "\n", 1559 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); 1560 ifp->if_ierrors++; 1561 goto next; 1562 } 1563 rate = ratetbl[hwrate]; 1564 1565 #ifdef RTW_DEBUG 1566 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1567 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1568 (rate * 5) % 10, htsfth, htsftl)); 1569 #endif /* RTW_DEBUG */ 1570 1571 /* if bad flags, skip descriptor */ 1572 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1573 aprint_error_dev(sc->sc_dev, "too many rx segments, " 1574 "next=%d, %08" PRIx32 "\n", next, hstat); 1575 goto next; 1576 } 1577 1578 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1579 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1580 1581 m = rs->rs_mbuf; 1582 1583 /* if temporarily out of memory, re-use mbuf */ 1584 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1585 case 0: 1586 break; 1587 case ENOBUFS: 1588 aprint_error_dev(sc->sc_dev, 1589 "rtw_rxsoft_alloc(, %d) failed, dropping packet\n", 1590 next); 1591 goto next; 1592 default: 1593 /* XXX shorten rx ring, instead? */ 1594 aprint_error_dev(sc->sc_dev, 1595 "could not load DMA map\n"); 1596 } 1597 1598 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ); 1599 1600 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1601 rssi = UINT8_MAX - sq; 1602 else { 1603 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); 1604 /* TBD find out each front-end's LNA gain in the 1605 * front-end's units 1606 */ 1607 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1608 rssi |= 0x80; 1609 } 1610 1611 /* Note well: now we cannot recycle the rs_mbuf unless 1612 * we restore its original length. 1613 */ 1614 m->m_pkthdr.rcvif = ifp; 1615 m->m_pkthdr.len = m->m_len = len; 1616 1617 wh = mtod(m, struct ieee80211_frame_min *); 1618 1619 if (!IS_BEACON(wh->i_fc[0])) 1620 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1621 1622 sc->sc_tsfth = htsfth; 1623 1624 #ifdef RTW_DEBUG 1625 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 1626 (IFF_DEBUG|IFF_LINK2)) { 1627 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1628 rate, rssi); 1629 } 1630 #endif /* RTW_DEBUG */ 1631 1632 if (sc->sc_radiobpf != NULL) { 1633 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1634 1635 rr->rr_tsft = 1636 htole64(((uint64_t)htsfth << 32) | htsftl); 1637 1638 rr->rr_flags = IEEE80211_RADIOTAP_F_FCS; 1639 1640 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1641 rr->rr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1642 if ((hstat & RTW_RXSTAT_CRC32) != 0) 1643 rr->rr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 1644 1645 rr->rr_rate = rate; 1646 1647 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1648 rr->rr_u.u_philips.p_antsignal = rssi; 1649 else { 1650 rr->rr_u.u_other.o_antsignal = rssi; 1651 rr->rr_u.u_other.o_barker_lock = 1652 htole16(UINT8_MAX - sq); 1653 } 1654 1655 bpf_mtap2(sc->sc_radiobpf, 1656 rr, sizeof(sc->sc_rxtapu), m); 1657 } 1658 1659 if ((hstat & RTW_RXSTAT_RES) != 0) { 1660 m_freem(m); 1661 goto next; 1662 } 1663 1664 /* CRC is included with the packet; trim it off. */ 1665 m_adj(m, -IEEE80211_CRC_LEN); 1666 1667 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1668 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1669 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1670 ieee80211_free_node(ni); 1671 next: 1672 rtw_rxdesc_init(rdb, rs, next, 0); 1673 } 1674 #undef IS_BEACON 1675 } 1676 1677 static void 1678 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1679 struct rtw_txsoft *ts) 1680 { 1681 struct mbuf *m; 1682 struct ieee80211_node *ni; 1683 1684 m = ts->ts_mbuf; 1685 ni = ts->ts_ni; 1686 KASSERT(m != NULL); 1687 KASSERT(ni != NULL); 1688 ts->ts_mbuf = NULL; 1689 ts->ts_ni = NULL; 1690 1691 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1692 BUS_DMASYNC_POSTWRITE); 1693 bus_dmamap_unload(dmat, ts->ts_dmamap); 1694 m_freem(m); 1695 ieee80211_free_node(ni); 1696 } 1697 1698 static void 1699 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1700 struct rtw_txsoft_blk *tsb) 1701 { 1702 struct rtw_txsoft *ts; 1703 1704 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1705 rtw_txsoft_release(dmat, ic, ts); 1706 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1707 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1708 } 1709 tsb->tsb_tx_timer = 0; 1710 } 1711 1712 static inline void 1713 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1714 struct rtw_txsoft *ts, int ndesc) 1715 { 1716 uint32_t hstat; 1717 int data_retry, rts_retry; 1718 struct rtw_txdesc *tdn; 1719 const char *condstring; 1720 struct ifnet *ifp = &sc->sc_if; 1721 1722 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1723 1724 tdb->tdb_nfree += ndesc; 1725 1726 tdn = &tdb->tdb_desc[ts->ts_last]; 1727 1728 hstat = le32toh(tdn->td_stat); 1729 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1730 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); 1731 1732 ifp->if_collisions += rts_retry + data_retry; 1733 1734 if ((hstat & RTW_TXSTAT_TOK) != 0) 1735 condstring = "ok"; 1736 else { 1737 ifp->if_oerrors++; 1738 condstring = "error"; 1739 } 1740 1741 #ifdef RTW_DEBUG 1742 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1743 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1744 device_xname(sc->sc_dev), ts, ts->ts_first, ts->ts_last, 1745 condstring, rts_retry, data_retry)); 1746 #else 1747 __USE(condstring); 1748 #endif 1749 } 1750 1751 static void 1752 rtw_reset_oactive(struct rtw_softc *sc) 1753 { 1754 short oflags; 1755 int pri; 1756 struct rtw_txsoft_blk *tsb; 1757 struct rtw_txdesc_blk *tdb; 1758 oflags = sc->sc_if.if_flags; 1759 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1760 tsb = &sc->sc_txsoft_blk[pri]; 1761 tdb = &sc->sc_txdesc_blk[pri]; 1762 if (!SIMPLEQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0) 1763 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1764 } 1765 if (oflags != sc->sc_if.if_flags) { 1766 DPRINTF(sc, RTW_DEBUG_OACTIVE, 1767 ("%s: reset OACTIVE\n", __func__)); 1768 } 1769 } 1770 1771 /* Collect transmitted packets. */ 1772 static bool 1773 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1774 struct rtw_txdesc_blk *tdb, int force) 1775 { 1776 bool collected = false; 1777 int ndesc; 1778 struct rtw_txsoft *ts; 1779 1780 #ifdef RTW_DEBUG 1781 rtw_dump_rings(sc); 1782 #endif 1783 1784 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1785 /* If we're clearing a failed transmission, only clear 1786 up to the last packet the hardware has processed. */ 1787 if (ts->ts_first == rtw_txring_next(&sc->sc_regs, tdb)) 1788 break; 1789 1790 ndesc = 1 + ts->ts_last - ts->ts_first; 1791 if (ts->ts_last < ts->ts_first) 1792 ndesc += tdb->tdb_ndesc; 1793 1794 KASSERT(ndesc > 0); 1795 1796 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1797 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1798 1799 if (force) { 1800 int next; 1801 #ifdef RTW_DIAG 1802 printf("%s: clearing packet, stats", __func__); 1803 #endif 1804 for (next = ts->ts_first; ; 1805 next = RTW_NEXT_IDX(tdb, next)) { 1806 #ifdef RTW_DIAG 1807 printf(" %" PRIx32 "/%" PRIx32 "/%" PRIx32 "/%" PRIu32 "/%" PRIx32, le32toh(tdb->tdb_desc[next].td_stat), le32toh(tdb->tdb_desc[next].td_ctl1), le32toh(tdb->tdb_desc[next].td_buf), le32toh(tdb->tdb_desc[next].td_len), le32toh(tdb->tdb_desc[next].td_next)); 1808 #endif 1809 tdb->tdb_desc[next].td_stat &= 1810 ~htole32(RTW_TXSTAT_OWN); 1811 if (next == ts->ts_last) 1812 break; 1813 } 1814 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1815 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1816 #ifdef RTW_DIAG 1817 next = RTW_NEXT_IDX(tdb, next); 1818 printf(" -> end %u stat %" PRIx32 ", was %u\n", next, 1819 le32toh(tdb->tdb_desc[next].td_stat), 1820 rtw_txring_next(&sc->sc_regs, tdb)); 1821 #endif 1822 } else if ((tdb->tdb_desc[ts->ts_last].td_stat & 1823 htole32(RTW_TXSTAT_OWN)) != 0) { 1824 rtw_txdescs_sync(tdb, ts->ts_last, 1, 1825 BUS_DMASYNC_PREREAD); 1826 break; 1827 } 1828 1829 collected = true; 1830 1831 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1832 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1833 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1834 } 1835 1836 /* no more pending transmissions, cancel watchdog */ 1837 if (ts == NULL) 1838 tsb->tsb_tx_timer = 0; 1839 rtw_reset_oactive(sc); 1840 1841 return collected; 1842 } 1843 1844 static void 1845 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1846 { 1847 int pri; 1848 struct rtw_txsoft_blk *tsb; 1849 struct rtw_txdesc_blk *tdb; 1850 struct ifnet *ifp = &sc->sc_if; 1851 1852 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1853 tsb = &sc->sc_txsoft_blk[pri]; 1854 tdb = &sc->sc_txdesc_blk[pri]; 1855 rtw_collect_txring(sc, tsb, tdb, 0); 1856 } 1857 1858 if ((isr & RTW_INTR_TX) != 0) 1859 rtw_start(ifp); 1860 1861 return; 1862 } 1863 1864 static void 1865 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1866 { 1867 u_int next; 1868 uint32_t tsfth, tsftl; 1869 struct ieee80211com *ic; 1870 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN]; 1871 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN]; 1872 struct mbuf *m; 1873 1874 tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH); 1875 tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1876 1877 if ((isr & (RTW_INTR_TBDOK|RTW_INTR_TBDER)) != 0) { 1878 next = rtw_txring_next(&sc->sc_regs, tdb); 1879 #ifdef RTW_DEBUG 1880 RTW_DPRINTF(RTW_DEBUG_BEACON, 1881 ("%s: beacon ring %sprocessed, isr = %#04" PRIx16 1882 ", next %u expected %u, %" PRIu64 "\n", __func__, 1883 (next == tdb->tdb_next) ? "" : "un", isr, next, 1884 tdb->tdb_next, (uint64_t)tsfth << 32 | tsftl)); 1885 #else 1886 __USE(next); 1887 __USE(tsfth); 1888 __USE(tsftl); 1889 #endif 1890 if ((RTW_READ8(&sc->sc_regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0) 1891 rtw_collect_txring(sc, tsb, tdb, 1); 1892 } 1893 /* Start beacon transmission. */ 1894 1895 if ((isr & RTW_INTR_BCNINT) != 0 && 1896 sc->sc_ic.ic_state == IEEE80211_S_RUN && 1897 SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) { 1898 RTW_DPRINTF(RTW_DEBUG_BEACON, 1899 ("%s: beacon prep. time, isr = %#04" PRIx16 1900 ", %16" PRIu64 "\n", __func__, isr, 1901 (uint64_t)tsfth << 32 | tsftl)); 1902 ic = &sc->sc_ic; 1903 m = rtw_beacon_alloc(sc, ic->ic_bss); 1904 1905 if (m == NULL) { 1906 aprint_error_dev(sc->sc_dev, 1907 "could not allocate beacon\n"); 1908 return; 1909 } 1910 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss); 1911 IF_ENQUEUE(&sc->sc_beaconq, m); 1912 rtw_start(&sc->sc_if); 1913 } 1914 } 1915 1916 static void 1917 rtw_intr_atim(struct rtw_softc *sc) 1918 { 1919 /* TBD */ 1920 return; 1921 } 1922 1923 #ifdef RTW_DEBUG 1924 static void 1925 rtw_dump_rings(struct rtw_softc *sc) 1926 { 1927 struct rtw_txdesc_blk *tdb; 1928 struct rtw_rxdesc *rd; 1929 struct rtw_rxdesc_blk *rdb; 1930 int desc, pri; 1931 1932 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1933 return; 1934 1935 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1936 tdb = &sc->sc_txdesc_blk[pri]; 1937 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1938 tdb->tdb_ndesc, tdb->tdb_nfree); 1939 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1940 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1941 } 1942 1943 rdb = &sc->sc_rxdesc_blk; 1944 1945 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1946 rd = &rdb->rdb_desc[desc]; 1947 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1948 "rsvd1/tsfth %08x\n", __func__, 1949 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1950 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1951 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1952 } 1953 } 1954 #endif /* RTW_DEBUG */ 1955 1956 static void 1957 rtw_hwring_setup(struct rtw_softc *sc) 1958 { 1959 int pri; 1960 struct rtw_regs *regs = &sc->sc_regs; 1961 struct rtw_txdesc_blk *tdb; 1962 1963 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_basereg = RTW_TLPDA; 1964 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_base = RTW_RING_BASE(sc, hd_txlo); 1965 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_basereg = RTW_TNPDA; 1966 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_base = RTW_RING_BASE(sc, hd_txmd); 1967 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_basereg = RTW_THPDA; 1968 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_base = RTW_RING_BASE(sc, hd_txhi); 1969 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_basereg = RTW_TBDA; 1970 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_base = RTW_RING_BASE(sc, hd_bcn); 1971 1972 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1973 tdb = &sc->sc_txdesc_blk[pri]; 1974 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base); 1975 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1976 ("%s: reg[tdb->tdb_basereg] <- %" PRIxPTR "\n", __func__, 1977 (uintptr_t)tdb->tdb_base)); 1978 } 1979 1980 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1981 1982 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1983 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1984 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1985 1986 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1987 1988 } 1989 1990 static int 1991 rtw_swring_setup(struct rtw_softc *sc) 1992 { 1993 int rc; 1994 struct rtw_rxdesc_blk *rdb; 1995 1996 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1997 1998 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1999 2000 rdb = &sc->sc_rxdesc_blk; 2001 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 2002 sc->sc_dev)) != 0 && rdb->rdb_ndesc == 0) { 2003 aprint_error_dev(sc->sc_dev, "could not allocate rx buffers\n"); 2004 return rc; 2005 } 2006 2007 rdb = &sc->sc_rxdesc_blk; 2008 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 2009 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2010 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 2011 rdb->rdb_next = 0; 2012 2013 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 2014 return 0; 2015 } 2016 2017 static void 2018 rtw_txdesc_blk_init(struct rtw_txdesc_blk *tdb) 2019 { 2020 int i; 2021 2022 (void)memset(tdb->tdb_desc, 0, 2023 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 2024 for (i = 0; i < tdb->tdb_ndesc; i++) 2025 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 2026 } 2027 2028 static u_int 2029 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb) 2030 { 2031 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) / 2032 sizeof(struct rtw_txdesc); 2033 } 2034 2035 #ifdef RTW_DIAG 2036 static void 2037 rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln) 2038 { 2039 int pri; 2040 u_int next; 2041 struct rtw_txdesc_blk *tdb; 2042 struct rtw_regs *regs = &sc->sc_regs; 2043 2044 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2045 int i; 2046 tdb = &sc->sc_txdesc_blk[pri]; 2047 next = rtw_txring_next(regs, tdb); 2048 if (tdb->tdb_next == next) 2049 continue; 2050 for (i = 0; next != tdb->tdb_next; 2051 next = RTW_NEXT_IDX(tdb, next), i++) { 2052 if ((tdb->tdb_desc[next].td_stat & htole32(RTW_TXSTAT_OWN)) == 0) 2053 break; 2054 } 2055 printf("%s:%d: tx-ring %d expected next %u, read %u+%d -> %s\n", fn, 2056 ln, pri, tdb->tdb_next, next, i, tdb->tdb_next == next ? "okay" : "BAD"); 2057 if (tdb->tdb_next == next) 2058 continue; 2059 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1); 2060 } 2061 } 2062 #endif 2063 2064 static void 2065 rtw_txdescs_reset(struct rtw_softc *sc) 2066 { 2067 int pri; 2068 struct rtw_txsoft_blk *tsb; 2069 struct rtw_txdesc_blk *tdb; 2070 2071 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2072 tsb = &sc->sc_txsoft_blk[pri]; 2073 tdb = &sc->sc_txdesc_blk[pri]; 2074 rtw_collect_txring(sc, tsb, tdb, 1); 2075 #ifdef RTW_DIAG 2076 if (!SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 2077 printf("%s: packets left in ring %d\n", __func__, pri); 2078 #endif 2079 } 2080 } 2081 2082 static void 2083 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 2084 { 2085 aprint_error_dev(sc->sc_dev, "tx fifo underflow\n"); 2086 2087 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: cleaning up xmit, isr %" PRIx16 2088 "\n", device_xname(sc->sc_dev), isr)); 2089 2090 #ifdef RTW_DEBUG 2091 rtw_dump_rings(sc); 2092 #endif /* RTW_DEBUG */ 2093 2094 /* Collect tx'd packets. XXX let's hope this stops the transmit 2095 * timeouts. 2096 */ 2097 rtw_txdescs_reset(sc); 2098 2099 #ifdef RTW_DEBUG 2100 rtw_dump_rings(sc); 2101 #endif /* RTW_DEBUG */ 2102 } 2103 2104 static inline void 2105 rtw_suspend_ticks(struct rtw_softc *sc) 2106 { 2107 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2108 ("%s: suspending ticks\n", device_xname(sc->sc_dev))); 2109 sc->sc_do_tick = 0; 2110 } 2111 2112 static inline void 2113 rtw_resume_ticks(struct rtw_softc *sc) 2114 { 2115 uint32_t tsftrl0, tsftrl1, next_tint; 2116 2117 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2118 2119 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2120 next_tint = tsftrl1 + 1000000; 2121 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tint); 2122 2123 sc->sc_do_tick = 1; 2124 2125 #ifdef RTW_DEBUG 2126 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2127 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 2128 device_xname(sc->sc_dev), tsftrl1 - tsftrl0, tsftrl1, next_tint)); 2129 #else 2130 __USE(tsftrl0); 2131 #endif 2132 } 2133 2134 static void 2135 rtw_intr_timeout(struct rtw_softc *sc) 2136 { 2137 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", device_xname(sc->sc_dev))); 2138 if (sc->sc_do_tick) 2139 rtw_resume_ticks(sc); 2140 return; 2141 } 2142 2143 int 2144 rtw_intr(void *arg) 2145 { 2146 int i; 2147 struct rtw_softc *sc = arg; 2148 struct rtw_regs *regs = &sc->sc_regs; 2149 uint16_t isr; 2150 struct ifnet *ifp = &sc->sc_if; 2151 2152 /* 2153 * If the interface isn't running, the interrupt couldn't 2154 * possibly have come from us. 2155 */ 2156 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2157 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) { 2158 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", 2159 device_xname(sc->sc_dev))); 2160 return (0); 2161 } 2162 2163 for (i = 0; i < 10; i++) { 2164 isr = RTW_READ16(regs, RTW_ISR); 2165 2166 RTW_WRITE16(regs, RTW_ISR, isr); 2167 RTW_WBR(regs, RTW_ISR, RTW_ISR); 2168 2169 if (sc->sc_intr_ack != NULL) 2170 (*sc->sc_intr_ack)(regs); 2171 2172 if (isr == 0) 2173 break; 2174 2175 #ifdef RTW_DEBUG 2176 #define PRINTINTR(flag) do { \ 2177 if ((isr & flag) != 0) { \ 2178 printf("%s" #flag, delim); \ 2179 delim = ","; \ 2180 } \ 2181 } while (0) 2182 2183 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 2184 const char *delim = "<"; 2185 2186 printf("%s: reg[ISR] = %x", device_xname(sc->sc_dev), 2187 isr); 2188 2189 PRINTINTR(RTW_INTR_TXFOVW); 2190 PRINTINTR(RTW_INTR_TIMEOUT); 2191 PRINTINTR(RTW_INTR_BCNINT); 2192 PRINTINTR(RTW_INTR_ATIMINT); 2193 PRINTINTR(RTW_INTR_TBDER); 2194 PRINTINTR(RTW_INTR_TBDOK); 2195 PRINTINTR(RTW_INTR_THPDER); 2196 PRINTINTR(RTW_INTR_THPDOK); 2197 PRINTINTR(RTW_INTR_TNPDER); 2198 PRINTINTR(RTW_INTR_TNPDOK); 2199 PRINTINTR(RTW_INTR_RXFOVW); 2200 PRINTINTR(RTW_INTR_RDU); 2201 PRINTINTR(RTW_INTR_TLPDER); 2202 PRINTINTR(RTW_INTR_TLPDOK); 2203 PRINTINTR(RTW_INTR_RER); 2204 PRINTINTR(RTW_INTR_ROK); 2205 2206 printf(">\n"); 2207 } 2208 #undef PRINTINTR 2209 #endif /* RTW_DEBUG */ 2210 2211 if ((isr & RTW_INTR_RX) != 0) 2212 rtw_intr_rx(sc, isr); 2213 if ((isr & RTW_INTR_TX) != 0) 2214 rtw_intr_tx(sc, isr); 2215 if ((isr & RTW_INTR_BEACON) != 0) 2216 rtw_intr_beacon(sc, isr); 2217 if ((isr & RTW_INTR_ATIMINT) != 0) 2218 rtw_intr_atim(sc); 2219 if ((isr & RTW_INTR_IOERROR) != 0) 2220 rtw_intr_ioerror(sc, isr); 2221 if ((isr & RTW_INTR_TIMEOUT) != 0) 2222 rtw_intr_timeout(sc); 2223 } 2224 2225 return 1; 2226 } 2227 2228 /* Must be called at splnet. */ 2229 static void 2230 rtw_stop(struct ifnet *ifp, int disable) 2231 { 2232 int pri; 2233 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2234 struct ieee80211com *ic = &sc->sc_ic; 2235 struct rtw_regs *regs = &sc->sc_regs; 2236 2237 rtw_suspend_ticks(sc); 2238 2239 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2240 2241 if (device_has_power(sc->sc_dev)) { 2242 /* Disable interrupts. */ 2243 RTW_WRITE16(regs, RTW_IMR, 0); 2244 2245 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2246 2247 /* Stop the transmit and receive processes. First stop DMA, 2248 * then disable receiver and transmitter. 2249 */ 2250 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2251 2252 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2253 2254 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2255 } 2256 2257 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2258 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2259 &sc->sc_txsoft_blk[pri]); 2260 } 2261 2262 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2263 2264 /* Mark the interface as not running. Cancel the watchdog timer. */ 2265 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2266 ifp->if_timer = 0; 2267 2268 if (disable) 2269 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 2270 2271 return; 2272 } 2273 2274 const char * 2275 rtw_pwrstate_string(enum rtw_pwrstate power) 2276 { 2277 switch (power) { 2278 case RTW_ON: 2279 return "on"; 2280 case RTW_SLEEP: 2281 return "sleep"; 2282 case RTW_OFF: 2283 return "off"; 2284 default: 2285 return "unknown"; 2286 } 2287 } 2288 2289 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2290 * reference driver, plus a magic Maxim "ON" value that comes from 2291 * the Realtek document "Windows PG for Rtl8180." 2292 */ 2293 static void 2294 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2295 int before_rf, int digphy) 2296 { 2297 uint32_t anaparm; 2298 2299 anaparm = RTW_READ(regs, RTW_ANAPARM); 2300 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2301 2302 switch (power) { 2303 case RTW_OFF: 2304 if (before_rf) 2305 return; 2306 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2307 anaparm |= RTW_ANAPARM_TXDACOFF; 2308 break; 2309 case RTW_SLEEP: 2310 if (!before_rf) 2311 return; 2312 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2313 anaparm |= RTW_ANAPARM_TXDACOFF; 2314 break; 2315 case RTW_ON: 2316 if (!before_rf) 2317 return; 2318 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2319 break; 2320 } 2321 RTW_DPRINTF(RTW_DEBUG_PWR, 2322 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2323 __func__, rtw_pwrstate_string(power), 2324 (before_rf) ? "before" : "after", anaparm)); 2325 2326 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2327 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2328 } 2329 2330 /* XXX I am using the RFMD settings gleaned from the reference 2331 * driver. They agree 2332 */ 2333 static void 2334 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2335 int before_rf, int digphy) 2336 { 2337 uint32_t anaparm; 2338 2339 anaparm = RTW_READ(regs, RTW_ANAPARM); 2340 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2341 2342 switch (power) { 2343 case RTW_OFF: 2344 if (before_rf) 2345 return; 2346 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2347 anaparm |= RTW_ANAPARM_TXDACOFF; 2348 break; 2349 case RTW_SLEEP: 2350 if (!before_rf) 2351 return; 2352 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2353 anaparm |= RTW_ANAPARM_TXDACOFF; 2354 break; 2355 case RTW_ON: 2356 if (!before_rf) 2357 return; 2358 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2359 break; 2360 } 2361 RTW_DPRINTF(RTW_DEBUG_PWR, 2362 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2363 __func__, rtw_pwrstate_string(power), 2364 (before_rf) ? "before" : "after", anaparm)); 2365 2366 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2367 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2368 } 2369 2370 static void 2371 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2372 int before_rf, int digphy) 2373 { 2374 uint32_t anaparm; 2375 2376 anaparm = RTW_READ(regs, RTW_ANAPARM); 2377 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2378 2379 switch (power) { 2380 case RTW_OFF: 2381 if (before_rf) 2382 return; 2383 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2384 anaparm |= RTW_ANAPARM_TXDACOFF; 2385 break; 2386 case RTW_SLEEP: 2387 if (!before_rf) 2388 return; 2389 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2390 anaparm |= RTW_ANAPARM_TXDACOFF; 2391 break; 2392 case RTW_ON: 2393 if (!before_rf) 2394 return; 2395 if (digphy) { 2396 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2397 /* XXX guess */ 2398 anaparm |= RTW_ANAPARM_TXDACOFF; 2399 } else 2400 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2401 break; 2402 } 2403 RTW_DPRINTF(RTW_DEBUG_PWR, 2404 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2405 __func__, rtw_pwrstate_string(power), 2406 (before_rf) ? "before" : "after", anaparm)); 2407 2408 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2409 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2410 } 2411 2412 static void 2413 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2414 int digphy) 2415 { 2416 struct rtw_regs *regs = &sc->sc_regs; 2417 2418 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2419 2420 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2421 2422 rtw_set_access(regs, RTW_ACCESS_NONE); 2423 2424 return; 2425 } 2426 2427 static int 2428 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2429 { 2430 int rc; 2431 2432 RTW_DPRINTF(RTW_DEBUG_PWR, 2433 ("%s: %s->%s\n", __func__, 2434 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2435 2436 if (sc->sc_pwrstate == power) 2437 return 0; 2438 2439 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2440 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2441 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2442 2443 switch (power) { 2444 case RTW_ON: 2445 /* TBD set LEDs */ 2446 break; 2447 case RTW_SLEEP: 2448 /* TBD */ 2449 break; 2450 case RTW_OFF: 2451 /* TBD */ 2452 break; 2453 } 2454 if (rc == 0) 2455 sc->sc_pwrstate = power; 2456 else 2457 sc->sc_pwrstate = RTW_OFF; 2458 return rc; 2459 } 2460 2461 static int 2462 rtw_tune(struct rtw_softc *sc) 2463 { 2464 struct ieee80211com *ic = &sc->sc_ic; 2465 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 2466 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 2467 u_int chan; 2468 int rc; 2469 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2470 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2471 2472 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2473 KASSERT(chan != IEEE80211_CHAN_ANY); 2474 2475 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2476 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2477 2478 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2479 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2480 2481 if (chan == sc->sc_cur_chan) { 2482 RTW_DPRINTF(RTW_DEBUG_TUNE, 2483 ("%s: already tuned chan #%d\n", __func__, chan)); 2484 return 0; 2485 } 2486 2487 rtw_suspend_ticks(sc); 2488 2489 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2490 2491 /* TBD wait for Tx to complete */ 2492 2493 KASSERT(device_has_power(sc->sc_dev)); 2494 2495 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2496 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr, 2497 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) { 2498 /* XXX condition on powersaving */ 2499 aprint_error_dev(sc->sc_dev, "phy init failed\n"); 2500 } 2501 2502 sc->sc_cur_chan = chan; 2503 2504 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2505 2506 rtw_resume_ticks(sc); 2507 2508 return rc; 2509 } 2510 2511 bool 2512 rtw_suspend(device_t self, const pmf_qual_t *qual) 2513 { 2514 int rc; 2515 struct rtw_softc *sc = device_private(self); 2516 2517 sc->sc_flags &= ~RTW_F_DK_VALID; 2518 2519 if (!device_has_power(self)) 2520 return false; 2521 2522 /* turn off PHY */ 2523 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2524 aprint_error_dev(self, "failed to turn off PHY (%d)\n", rc); 2525 return false; 2526 } 2527 2528 rtw_disable_interrupts(&sc->sc_regs); 2529 2530 return true; 2531 } 2532 2533 bool 2534 rtw_resume(device_t self, const pmf_qual_t *qual) 2535 { 2536 struct rtw_softc *sc = device_private(self); 2537 2538 /* Power may have been removed, resetting WEP keys. 2539 */ 2540 sc->sc_flags &= ~RTW_F_DK_VALID; 2541 rtw_enable_interrupts(sc); 2542 2543 return true; 2544 } 2545 2546 static void 2547 rtw_transmit_config(struct rtw_regs *regs) 2548 { 2549 uint32_t tcr; 2550 2551 tcr = RTW_READ(regs, RTW_TCR); 2552 2553 tcr |= RTW_TCR_CWMIN; 2554 tcr &= ~RTW_TCR_MXDMA_MASK; 2555 tcr |= RTW_TCR_MXDMA_256; 2556 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2557 tcr &= ~RTW_TCR_LBK_MASK; 2558 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2559 2560 /* set short/long retry limits */ 2561 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2562 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK); 2563 2564 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2565 2566 RTW_WRITE(regs, RTW_TCR, tcr); 2567 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2568 } 2569 2570 static void 2571 rtw_disable_interrupts(struct rtw_regs *regs) 2572 { 2573 RTW_WRITE16(regs, RTW_IMR, 0); 2574 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2575 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2576 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2577 } 2578 2579 static void 2580 rtw_enable_interrupts(struct rtw_softc *sc) 2581 { 2582 struct rtw_regs *regs = &sc->sc_regs; 2583 2584 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2585 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2586 2587 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2588 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2589 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2590 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2591 2592 /* XXX necessary? */ 2593 if (sc->sc_intr_ack != NULL) 2594 (*sc->sc_intr_ack)(regs); 2595 } 2596 2597 static void 2598 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2599 { 2600 uint8_t msr; 2601 2602 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2603 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2604 2605 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2606 2607 switch (opmode) { 2608 case IEEE80211_M_AHDEMO: 2609 case IEEE80211_M_IBSS: 2610 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2611 break; 2612 case IEEE80211_M_HOSTAP: 2613 msr |= RTW_MSR_NETYPE_AP_OK; 2614 break; 2615 case IEEE80211_M_MONITOR: 2616 /* XXX */ 2617 msr |= RTW_MSR_NETYPE_NOLINK; 2618 break; 2619 case IEEE80211_M_STA: 2620 msr |= RTW_MSR_NETYPE_INFRA_OK; 2621 break; 2622 } 2623 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2624 2625 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2626 } 2627 2628 #define rtw_calchash(addr) \ 2629 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2630 2631 static void 2632 rtw_pktfilt_load(struct rtw_softc *sc) 2633 { 2634 struct rtw_regs *regs = &sc->sc_regs; 2635 struct ieee80211com *ic = &sc->sc_ic; 2636 struct ethercom *ec = &sc->sc_ec; 2637 struct ifnet *ifp = &sc->sc_if; 2638 int hash; 2639 uint32_t hashes[2] = { 0, 0 }; 2640 struct ether_multi *enm; 2641 struct ether_multistep step; 2642 2643 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2644 2645 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2646 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2647 2648 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2649 /* MAC auto-reset PHY (huh?) */ 2650 sc->sc_rcr |= RTW_RCR_ENMARP; 2651 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2652 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2653 2654 switch (ic->ic_opmode) { 2655 case IEEE80211_M_MONITOR: 2656 sc->sc_rcr |= RTW_RCR_MONITOR; 2657 break; 2658 case IEEE80211_M_AHDEMO: 2659 case IEEE80211_M_IBSS: 2660 /* receive broadcasts in our BSS */ 2661 sc->sc_rcr |= RTW_RCR_ADD3; 2662 break; 2663 default: 2664 break; 2665 } 2666 2667 ifp->if_flags &= ~IFF_ALLMULTI; 2668 2669 /* 2670 * Program the 64-bit multicast hash filter. 2671 */ 2672 ETHER_FIRST_MULTI(step, ec, enm); 2673 while (enm != NULL) { 2674 /* XXX */ 2675 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2676 ETHER_ADDR_LEN) != 0) { 2677 ifp->if_flags |= IFF_ALLMULTI; 2678 break; 2679 } 2680 2681 hash = rtw_calchash(enm->enm_addrlo); 2682 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2683 ETHER_NEXT_MULTI(step, enm); 2684 } 2685 2686 /* XXX accept all broadcast if scanning */ 2687 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2688 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2689 2690 if (ifp->if_flags & IFF_PROMISC) { 2691 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2692 sc->sc_rcr |= RTW_RCR_ACRC32; /* accept frames failing CRC */ 2693 sc->sc_rcr |= RTW_RCR_AICV; /* accept frames failing ICV */ 2694 ifp->if_flags |= IFF_ALLMULTI; 2695 } 2696 2697 if (ifp->if_flags & IFF_ALLMULTI) 2698 hashes[0] = hashes[1] = 0xffffffff; 2699 2700 if ((hashes[0] | hashes[1]) != 0) 2701 sc->sc_rcr |= RTW_RCR_AM; /* accept multicast */ 2702 2703 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2704 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2705 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2706 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2707 2708 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2709 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2710 device_xname(sc->sc_dev), RTW_READ(regs, RTW_MAR0), 2711 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2712 } 2713 2714 static struct mbuf * 2715 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2716 { 2717 struct ieee80211com *ic = &sc->sc_ic; 2718 struct mbuf *m; 2719 struct ieee80211_beacon_offsets boff; 2720 2721 if ((m = ieee80211_beacon_alloc(ic, ni, &boff)) != NULL) { 2722 RTW_DPRINTF(RTW_DEBUG_BEACON, 2723 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2724 } 2725 return m; 2726 } 2727 2728 /* Must be called at splnet. */ 2729 static int 2730 rtw_init(struct ifnet *ifp) 2731 { 2732 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2733 struct ieee80211com *ic = &sc->sc_ic; 2734 struct rtw_regs *regs = &sc->sc_regs; 2735 int rc; 2736 2737 if (device_is_active(sc->sc_dev)) { 2738 /* Cancel pending I/O and reset. */ 2739 rtw_stop(ifp, 0); 2740 } else if (!pmf_device_resume(sc->sc_dev, &sc->sc_qual) || 2741 !device_is_active(sc->sc_dev)) 2742 return 0; 2743 2744 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2745 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 2746 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 2747 2748 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2749 goto out; 2750 2751 if ((rc = rtw_swring_setup(sc)) != 0) 2752 goto out; 2753 2754 rtw_transmit_config(regs); 2755 2756 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2757 2758 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2759 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2760 2761 /* long PLCP header, 1Mb/2Mb basic rate */ 2762 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2763 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2764 2765 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2766 rtw_set_access(regs, RTW_ACCESS_NONE); 2767 2768 /* XXX from reference sources */ 2769 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2770 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2771 2772 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev); 2773 2774 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2775 /* from Linux driver */ 2776 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2777 2778 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2779 2780 rtw_enable_interrupts(sc); 2781 2782 rtw_pktfilt_load(sc); 2783 2784 rtw_hwring_setup(sc); 2785 2786 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2787 2788 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2789 2790 ifp->if_flags |= IFF_RUNNING; 2791 ic->ic_state = IEEE80211_S_INIT; 2792 2793 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2794 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2795 2796 rtw_resume_ticks(sc); 2797 2798 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2799 2800 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2801 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2802 else 2803 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2804 2805 out: 2806 aprint_error_dev(sc->sc_dev, "interface not running\n"); 2807 return rc; 2808 } 2809 2810 static inline void 2811 rtw_led_init(struct rtw_regs *regs) 2812 { 2813 uint8_t cfg0, cfg1; 2814 2815 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2816 2817 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2818 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2819 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2820 2821 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2822 RTW_DPRINTF(RTW_DEBUG_LED, 2823 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2824 2825 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2826 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2827 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2828 2829 rtw_set_access(regs, RTW_ACCESS_NONE); 2830 } 2831 2832 /* 2833 * IEEE80211_S_INIT: LED1 off 2834 * 2835 * IEEE80211_S_AUTH, 2836 * IEEE80211_S_ASSOC, 2837 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2838 * 2839 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2840 */ 2841 static void 2842 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2843 { 2844 struct rtw_led_state *ls; 2845 2846 ls = &sc->sc_led_state; 2847 2848 switch (nstate) { 2849 case IEEE80211_S_INIT: 2850 rtw_led_init(&sc->sc_regs); 2851 aprint_debug_dev(sc->sc_dev, "stopping blink\n"); 2852 callout_stop(&ls->ls_slow_ch); 2853 callout_stop(&ls->ls_fast_ch); 2854 ls->ls_slowblink = 0; 2855 ls->ls_actblink = 0; 2856 ls->ls_default = 0; 2857 break; 2858 case IEEE80211_S_SCAN: 2859 aprint_debug_dev(sc->sc_dev, "scheduling blink\n"); 2860 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2861 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2862 /*FALLTHROUGH*/ 2863 case IEEE80211_S_AUTH: 2864 case IEEE80211_S_ASSOC: 2865 ls->ls_default = RTW_LED1; 2866 ls->ls_actblink = RTW_LED1; 2867 ls->ls_slowblink = RTW_LED1; 2868 break; 2869 case IEEE80211_S_RUN: 2870 ls->ls_slowblink = 0; 2871 break; 2872 } 2873 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2874 } 2875 2876 static void 2877 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2878 { 2879 uint8_t led_condition; 2880 bus_size_t ofs; 2881 uint8_t mask, newval, val; 2882 2883 led_condition = ls->ls_default; 2884 2885 if (ls->ls_state & RTW_LED_S_SLOW) 2886 led_condition ^= ls->ls_slowblink; 2887 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2888 led_condition ^= ls->ls_actblink; 2889 2890 RTW_DPRINTF(RTW_DEBUG_LED, 2891 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2892 2893 switch (hwverid) { 2894 default: 2895 case 'F': 2896 ofs = RTW_PSR; 2897 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2898 if (led_condition & RTW_LED0) 2899 newval &= ~RTW_PSR_LEDGPO0; 2900 if (led_condition & RTW_LED1) 2901 newval &= ~RTW_PSR_LEDGPO1; 2902 break; 2903 case 'D': 2904 ofs = RTW_9346CR; 2905 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2906 newval = RTW_9346CR_EEM_PROGRAM; 2907 if (led_condition & RTW_LED0) 2908 newval |= RTW_9346CR_EEDI; 2909 if (led_condition & RTW_LED1) 2910 newval |= RTW_9346CR_EECS; 2911 break; 2912 } 2913 val = RTW_READ8(regs, ofs); 2914 RTW_DPRINTF(RTW_DEBUG_LED, 2915 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2916 (uintptr_t)ofs)); 2917 val &= ~mask; 2918 val |= newval; 2919 RTW_WRITE8(regs, ofs, val); 2920 RTW_DPRINTF(RTW_DEBUG_LED, 2921 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2922 (uintptr_t)ofs)); 2923 RTW_SYNC(regs, ofs, ofs); 2924 } 2925 2926 static void 2927 rtw_led_fastblink(void *arg) 2928 { 2929 int ostate, s; 2930 struct rtw_softc *sc = (struct rtw_softc *)arg; 2931 struct rtw_led_state *ls = &sc->sc_led_state; 2932 2933 s = splnet(); 2934 ostate = ls->ls_state; 2935 ls->ls_state ^= ls->ls_event; 2936 2937 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2938 ls->ls_state &= ~RTW_LED_S_TX; 2939 2940 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2941 ls->ls_state &= ~RTW_LED_S_RX; 2942 2943 ls->ls_event = 0; 2944 2945 if (ostate != ls->ls_state) 2946 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2947 splx(s); 2948 2949 aprint_debug_dev(sc->sc_dev, "scheduling fast blink\n"); 2950 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2951 } 2952 2953 static void 2954 rtw_led_slowblink(void *arg) 2955 { 2956 int s; 2957 struct rtw_softc *sc = (struct rtw_softc *)arg; 2958 struct rtw_led_state *ls = &sc->sc_led_state; 2959 2960 s = splnet(); 2961 ls->ls_state ^= RTW_LED_S_SLOW; 2962 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2963 splx(s); 2964 aprint_debug_dev(sc->sc_dev, "scheduling slow blink\n"); 2965 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2966 } 2967 2968 static void 2969 rtw_led_detach(struct rtw_led_state *ls) 2970 { 2971 callout_destroy(&ls->ls_fast_ch); 2972 callout_destroy(&ls->ls_slow_ch); 2973 } 2974 2975 static void 2976 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2977 { 2978 callout_init(&ls->ls_fast_ch, 0); 2979 callout_init(&ls->ls_slow_ch, 0); 2980 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2981 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2982 } 2983 2984 static int 2985 rtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2986 { 2987 int rc = 0, s; 2988 struct rtw_softc *sc = ifp->if_softc; 2989 2990 s = splnet(); 2991 if (cmd == SIOCSIFFLAGS) { 2992 if ((rc = ifioctl_common(ifp, cmd, data)) != 0) 2993 ; 2994 else switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2995 case IFF_UP: 2996 rc = rtw_init(ifp); 2997 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2998 break; 2999 case IFF_UP|IFF_RUNNING: 3000 if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 3001 rtw_pktfilt_load(sc); 3002 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 3003 break; 3004 case IFF_RUNNING: 3005 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 3006 rtw_stop(ifp, 1); 3007 break; 3008 default: 3009 break; 3010 } 3011 } else if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 3012 ; /* nothing to do */ 3013 else if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 3014 /* reload packet filter if running */ 3015 if (ifp->if_flags & IFF_RUNNING) 3016 rtw_pktfilt_load(sc); 3017 rc = 0; 3018 } else if ((ifp->if_flags & IFF_UP) != 0) 3019 rc = rtw_init(ifp); 3020 else 3021 rc = 0; 3022 splx(s); 3023 return rc; 3024 } 3025 3026 /* Select a transmit ring with at least one h/w and s/w descriptor free. 3027 * Return 0 on success, -1 on failure. 3028 */ 3029 static inline int 3030 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 3031 struct rtw_txdesc_blk **tdbp, int pri) 3032 { 3033 struct rtw_txsoft_blk *tsb; 3034 struct rtw_txdesc_blk *tdb; 3035 3036 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 3037 3038 tsb = &sc->sc_txsoft_blk[pri]; 3039 tdb = &sc->sc_txdesc_blk[pri]; 3040 3041 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 3042 if (tsb->tsb_tx_timer == 0) 3043 tsb->tsb_tx_timer = 5; 3044 *tsbp = NULL; 3045 *tdbp = NULL; 3046 return -1; 3047 } 3048 *tsbp = tsb; 3049 *tdbp = tdb; 3050 return 0; 3051 } 3052 3053 static inline struct mbuf * 3054 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 3055 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 3056 struct ieee80211_node **nip, short *if_flagsp) 3057 { 3058 struct mbuf *m; 3059 3060 if (IF_IS_EMPTY(ifq)) 3061 return NULL; 3062 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3063 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3064 __func__, pri)); 3065 *if_flagsp |= IFF_OACTIVE; 3066 sc->sc_if.if_timer = 1; 3067 return NULL; 3068 } 3069 IF_DEQUEUE(ifq, m); 3070 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3071 m->m_pkthdr.rcvif = NULL; 3072 KASSERT(*nip != NULL); 3073 return m; 3074 } 3075 3076 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 3077 * at the driver's selection of transmit control block for the packet. 3078 */ 3079 static inline int 3080 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 3081 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 3082 struct ieee80211_node **nip) 3083 { 3084 int pri; 3085 struct ether_header *eh; 3086 struct mbuf *m0; 3087 struct rtw_softc *sc; 3088 short *if_flagsp; 3089 3090 *mp = NULL; 3091 3092 sc = (struct rtw_softc *)ifp->if_softc; 3093 3094 DPRINTF(sc, RTW_DEBUG_XMIT, 3095 ("%s: enter %s\n", device_xname(sc->sc_dev), __func__)); 3096 3097 if_flagsp = &ifp->if_flags; 3098 3099 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 3100 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 3101 tdbp, nip, if_flagsp)) != NULL) { 3102 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 3103 __func__)); 3104 return 0; 3105 } 3106 3107 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 3108 tdbp, nip, if_flagsp)) != NULL) { 3109 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 3110 __func__)); 3111 return 0; 3112 } 3113 3114 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 3115 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 3116 return 0; 3117 } 3118 3119 IFQ_POLL(&ifp->if_snd, m0); 3120 if (m0 == NULL) { 3121 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3122 __func__)); 3123 return 0; 3124 } 3125 3126 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 3127 3128 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3129 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3130 __func__, pri)); 3131 *if_flagsp |= IFF_OACTIVE; 3132 sc->sc_if.if_timer = 1; 3133 return 0; 3134 } 3135 3136 IFQ_DEQUEUE(&ifp->if_snd, m0); 3137 if (m0 == NULL) { 3138 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3139 __func__)); 3140 return 0; 3141 } 3142 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 3143 ifp->if_opackets++; 3144 bpf_mtap(ifp, m0); 3145 eh = mtod(m0, struct ether_header *); 3146 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 3147 if (*nip == NULL) { 3148 /* NB: ieee80211_find_txnode does stat+msg */ 3149 m_freem(m0); 3150 return -1; 3151 } 3152 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 3153 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 3154 ifp->if_oerrors++; 3155 return -1; 3156 } 3157 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3158 *mp = m0; 3159 return 0; 3160 } 3161 3162 static int 3163 rtw_seg_too_short(bus_dmamap_t dmamap) 3164 { 3165 int i; 3166 for (i = 0; i < dmamap->dm_nsegs; i++) { 3167 if (dmamap->dm_segs[i].ds_len < 4) 3168 return 1; 3169 } 3170 return 0; 3171 } 3172 3173 /* TBD factor with atw_start */ 3174 static struct mbuf * 3175 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 3176 u_int ndescfree, device_t dev) 3177 { 3178 int first, rc; 3179 struct mbuf *m, *m0; 3180 3181 m0 = chain; 3182 3183 /* 3184 * Load the DMA map. Copy and try (once) again if the packet 3185 * didn't fit in the alloted number of segments. 3186 */ 3187 for (first = 1; 3188 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 3189 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 3190 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 3191 first = 0) { 3192 if (rc == 0) { 3193 #ifdef RTW_DIAGxxx 3194 if (rtw_seg_too_short(dmam)) { 3195 printf("%s: short segment, mbuf lengths:", __func__); 3196 for (m = m0; m; m = m->m_next) 3197 printf(" %d", m->m_len); 3198 printf("\n"); 3199 } 3200 #endif 3201 bus_dmamap_unload(dmat, dmam); 3202 } 3203 MGETHDR(m, M_DONTWAIT, MT_DATA); 3204 if (m == NULL) { 3205 aprint_error_dev(dev, "unable to allocate Tx mbuf\n"); 3206 break; 3207 } 3208 if (m0->m_pkthdr.len > MHLEN) { 3209 MCLGET(m, M_DONTWAIT); 3210 if ((m->m_flags & M_EXT) == 0) { 3211 aprint_error_dev(dev, 3212 "cannot allocate Tx cluster\n"); 3213 m_freem(m); 3214 break; 3215 } 3216 } 3217 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3218 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3219 m_freem(m0); 3220 m0 = m; 3221 m = NULL; 3222 } 3223 if (rc != 0) { 3224 aprint_error_dev(dev, "cannot load Tx buffer, rc = %d\n", rc); 3225 m_freem(m0); 3226 return NULL; 3227 } else if (rtw_seg_too_short(dmam)) { 3228 aprint_error_dev(dev, 3229 "cannot load Tx buffer, segment too short\n"); 3230 bus_dmamap_unload(dmat, dmam); 3231 m_freem(m0); 3232 return NULL; 3233 } else if (dmam->dm_nsegs > ndescfree) { 3234 aprint_error_dev(dev, "too many tx segments\n"); 3235 bus_dmamap_unload(dmat, dmam); 3236 m_freem(m0); 3237 return NULL; 3238 } 3239 return m0; 3240 } 3241 3242 #ifdef RTW_DEBUG 3243 static void 3244 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3245 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3246 { 3247 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3248 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] next %#08x " 3249 "buf %#08x ctl0 %#08x ctl1 %#08x len %#08x\n", 3250 device_xname(sc->sc_dev), ts, action, desc, 3251 le32toh(td->td_buf), le32toh(td->td_next), 3252 le32toh(td->td_ctl0), le32toh(td->td_ctl1), 3253 le32toh(td->td_len))); 3254 } 3255 #endif /* RTW_DEBUG */ 3256 3257 static void 3258 rtw_start(struct ifnet *ifp) 3259 { 3260 int desc, i, lastdesc, npkt, rate; 3261 uint32_t proto_ctl0, ctl0, ctl1; 3262 bus_dmamap_t dmamap; 3263 struct ieee80211com *ic; 3264 struct ieee80211_duration *d0; 3265 struct ieee80211_frame_min *wh; 3266 struct ieee80211_node *ni = NULL; /* XXX: GCC */ 3267 struct mbuf *m0; 3268 struct rtw_softc *sc; 3269 struct rtw_txsoft_blk *tsb = NULL; /* XXX: GCC */ 3270 struct rtw_txdesc_blk *tdb = NULL; /* XXX: GCC */ 3271 struct rtw_txsoft *ts; 3272 struct rtw_txdesc *td; 3273 struct ieee80211_key *k; 3274 3275 sc = (struct rtw_softc *)ifp->if_softc; 3276 ic = &sc->sc_ic; 3277 3278 DPRINTF(sc, RTW_DEBUG_XMIT, 3279 ("%s: enter %s\n", device_xname(sc->sc_dev), __func__)); 3280 3281 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3282 goto out; 3283 3284 /* XXX do real rate control */ 3285 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3286 3287 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3288 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3289 3290 for (;;) { 3291 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3292 continue; 3293 if (m0 == NULL) 3294 break; 3295 3296 wh = mtod(m0, struct ieee80211_frame_min *); 3297 3298 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3299 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3300 m_freem(m0); 3301 break; 3302 } else 3303 k = NULL; 3304 3305 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3306 3307 dmamap = ts->ts_dmamap; 3308 3309 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3310 tdb->tdb_nfree, sc->sc_dev); 3311 3312 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3313 DPRINTF(sc, RTW_DEBUG_XMIT, 3314 ("%s: fail dmamap load\n", __func__)); 3315 goto post_dequeue_err; 3316 } 3317 3318 /* Note well: rtw_dmamap_load_txbuf may have created 3319 * a new chain, so we must find the header once 3320 * more. 3321 */ 3322 wh = mtod(m0, struct ieee80211_frame_min *); 3323 3324 /* XXX do real rate control */ 3325 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3326 IEEE80211_FC0_TYPE_MGT) 3327 rate = 2; 3328 else 3329 rate = MAX(2, ieee80211_get_rate(ni)); 3330 3331 #ifdef RTW_DEBUG 3332 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3333 (IFF_DEBUG|IFF_LINK2)) { 3334 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3335 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3336 : sizeof(wh), 3337 rate, 0); 3338 } 3339 #endif /* RTW_DEBUG */ 3340 ctl0 = proto_ctl0 | 3341 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3342 3343 switch (rate) { 3344 default: 3345 case 2: 3346 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3347 break; 3348 case 4: 3349 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3350 break; 3351 case 11: 3352 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3353 break; 3354 case 22: 3355 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3356 break; 3357 } 3358 /* XXX >= ? Compare after fragmentation? */ 3359 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3360 ctl0 |= RTW_TXCTL0_RTSEN; 3361 3362 /* XXX Sometimes writes a bogus keyid; h/w doesn't 3363 * seem to care, since we don't activate h/w Tx 3364 * encryption. 3365 */ 3366 if (k != NULL && 3367 k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 3368 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3369 RTW_TXCTL0_KEYID_MASK; 3370 } 3371 3372 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3373 IEEE80211_FC0_TYPE_MGT) { 3374 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3375 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3376 IEEE80211_FC0_SUBTYPE_BEACON) 3377 ctl0 |= RTW_TXCTL0_BEACON; 3378 } 3379 3380 if (ieee80211_compute_duration(wh, k, m0->m_pkthdr.len, 3381 ic->ic_flags, ic->ic_fragthreshold, 3382 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3383 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3384 (IFF_DEBUG|IFF_LINK2)) == -1) { 3385 DPRINTF(sc, RTW_DEBUG_XMIT, 3386 ("%s: fail compute duration\n", __func__)); 3387 goto post_load_err; 3388 } 3389 3390 d0 = &ts->ts_d0; 3391 3392 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3393 3394 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3395 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3396 3397 if (d0->d_residue) 3398 ctl1 |= RTW_TXCTL1_LENGEXT; 3399 3400 /* TBD fragmentation */ 3401 3402 ts->ts_first = tdb->tdb_next; 3403 3404 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3405 BUS_DMASYNC_PREWRITE); 3406 3407 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3408 3409 bpf_mtap3(ic->ic_rawbpf, m0); 3410 3411 if (sc->sc_radiobpf != NULL) { 3412 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3413 3414 rt->rt_rate = rate; 3415 3416 bpf_mtap2(sc->sc_radiobpf, rt, sizeof(sc->sc_txtapu), 3417 m0); 3418 } 3419 3420 for (i = 0, lastdesc = desc = ts->ts_first; 3421 i < dmamap->dm_nsegs; 3422 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3423 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3424 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3425 ("%s: seg too long\n", __func__)); 3426 goto post_load_err; 3427 } 3428 td = &tdb->tdb_desc[desc]; 3429 td->td_ctl0 = htole32(ctl0); 3430 td->td_ctl1 = htole32(ctl1); 3431 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3432 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3433 td->td_next = htole32(RTW_NEXT_DESC(tdb, desc)); 3434 if (i != 0) 3435 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3436 lastdesc = desc; 3437 #ifdef RTW_DEBUG 3438 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3439 #endif /* RTW_DEBUG */ 3440 } 3441 3442 KASSERT(desc < tdb->tdb_ndesc); 3443 3444 ts->ts_ni = ni; 3445 KASSERT(ni != NULL); 3446 ts->ts_mbuf = m0; 3447 ts->ts_last = lastdesc; 3448 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3449 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3450 htole32(RTW_TXCTL0_FS); 3451 3452 #ifdef RTW_DEBUG 3453 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3454 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3455 #endif /* RTW_DEBUG */ 3456 3457 tdb->tdb_nfree -= dmamap->dm_nsegs; 3458 tdb->tdb_next = desc; 3459 3460 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3461 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3462 3463 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3464 htole32(RTW_TXCTL0_OWN); 3465 3466 #ifdef RTW_DEBUG 3467 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3468 #endif /* RTW_DEBUG */ 3469 3470 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3471 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3472 3473 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3474 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3475 3476 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) 3477 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3478 tsb->tsb_tx_timer = 5; 3479 ifp->if_timer = 1; 3480 rtw_tx_kick(&sc->sc_regs, tsb->tsb_poll); 3481 } 3482 out: 3483 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3484 return; 3485 post_load_err: 3486 bus_dmamap_unload(sc->sc_dmat, dmamap); 3487 m_freem(m0); 3488 post_dequeue_err: 3489 ieee80211_free_node(ni); 3490 return; 3491 } 3492 3493 static void 3494 rtw_idle(struct rtw_regs *regs) 3495 { 3496 int active; 3497 uint8_t tppoll; 3498 3499 /* request stop DMA; wait for packets to stop transmitting. */ 3500 3501 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3502 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL); 3503 3504 for (active = 0; active < 300 && 3505 (tppoll = RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0; 3506 active++) 3507 DELAY(10); 3508 printf("%s: transmit DMA idle in %dus, tppoll %02" PRIx8 "\n", __func__, 3509 active * 10, tppoll); 3510 } 3511 3512 static void 3513 rtw_watchdog(struct ifnet *ifp) 3514 { 3515 int pri, tx_timeouts = 0; 3516 struct rtw_softc *sc; 3517 struct rtw_txsoft_blk *tsb; 3518 3519 sc = ifp->if_softc; 3520 3521 ifp->if_timer = 0; 3522 3523 if (!device_is_active(sc->sc_dev)) 3524 return; 3525 3526 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3527 tsb = &sc->sc_txsoft_blk[pri]; 3528 3529 if (tsb->tsb_tx_timer == 0) 3530 continue; 3531 else if (--tsb->tsb_tx_timer == 0) { 3532 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3533 continue; 3534 else if (rtw_collect_txring(sc, tsb, 3535 &sc->sc_txdesc_blk[pri], 0)) 3536 continue; 3537 printf("%s: transmit timeout, priority %d\n", 3538 ifp->if_xname, pri); 3539 ifp->if_oerrors++; 3540 if (pri != RTW_TXPRIBCN) 3541 tx_timeouts++; 3542 } else 3543 ifp->if_timer = 1; 3544 } 3545 3546 if (tx_timeouts > 0) { 3547 /* Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr, 3548 * reset s/w tx-ring pointers, and start transmission. 3549 * 3550 * TBD Stop/restart just the broken rings? 3551 */ 3552 rtw_idle(&sc->sc_regs); 3553 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 3554 rtw_txdescs_reset(sc); 3555 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 3556 rtw_start(ifp); 3557 } 3558 ieee80211_watchdog(&sc->sc_ic); 3559 return; 3560 } 3561 3562 static void 3563 rtw_next_scan(void *arg) 3564 { 3565 struct ieee80211com *ic = arg; 3566 int s; 3567 3568 /* don't call rtw_start w/o network interrupts blocked */ 3569 s = splnet(); 3570 if (ic->ic_state == IEEE80211_S_SCAN) 3571 ieee80211_next_scan(ic); 3572 splx(s); 3573 } 3574 3575 static void 3576 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3577 { 3578 uint16_t bcnitv, bintritv, intval; 3579 int i; 3580 struct rtw_regs *regs = &sc->sc_regs; 3581 3582 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3583 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3584 3585 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3586 3587 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3588 3589 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); 3590 3591 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3592 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); 3593 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3594 /* interrupt host 1ms before the TBTT */ 3595 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV; 3596 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV); 3597 RTW_WRITE16(regs, RTW_BINTRITV, bintritv); 3598 /* magic from Linux */ 3599 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND)); 3600 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); 3601 rtw_set_access(regs, RTW_ACCESS_NONE); 3602 3603 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 3604 } 3605 3606 /* Synchronize the hardware state with the software state. */ 3607 static int 3608 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3609 { 3610 struct ifnet *ifp = ic->ic_ifp; 3611 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3612 enum ieee80211_state ostate; 3613 int error; 3614 3615 ostate = ic->ic_state; 3616 3617 aprint_debug_dev(sc->sc_dev, "%s: l.%d\n", __func__, __LINE__); 3618 rtw_led_newstate(sc, nstate); 3619 3620 aprint_debug_dev(sc->sc_dev, "%s: l.%d\n", __func__, __LINE__); 3621 if (nstate == IEEE80211_S_INIT) { 3622 callout_stop(&sc->sc_scan_ch); 3623 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3624 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3625 } 3626 3627 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3628 rtw_pwrstate(sc, RTW_ON); 3629 3630 if ((error = rtw_tune(sc)) != 0) 3631 return error; 3632 3633 switch (nstate) { 3634 case IEEE80211_S_INIT: 3635 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3636 break; 3637 case IEEE80211_S_SCAN: 3638 if (ostate != IEEE80211_S_SCAN) { 3639 (void)memset(ic->ic_bss->ni_bssid, 0, 3640 IEEE80211_ADDR_LEN); 3641 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3642 } 3643 3644 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3645 rtw_next_scan, ic); 3646 3647 break; 3648 case IEEE80211_S_RUN: 3649 switch (ic->ic_opmode) { 3650 case IEEE80211_M_HOSTAP: 3651 case IEEE80211_M_IBSS: 3652 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3653 /*FALLTHROUGH*/ 3654 case IEEE80211_M_AHDEMO: 3655 case IEEE80211_M_STA: 3656 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3657 ic->ic_bss->ni_intval); 3658 break; 3659 case IEEE80211_M_MONITOR: 3660 break; 3661 } 3662 rtw_set_nettype(sc, ic->ic_opmode); 3663 break; 3664 case IEEE80211_S_ASSOC: 3665 case IEEE80211_S_AUTH: 3666 break; 3667 } 3668 3669 if (nstate != IEEE80211_S_SCAN) 3670 callout_stop(&sc->sc_scan_ch); 3671 3672 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3673 } 3674 3675 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3676 static uint64_t 3677 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3678 { 3679 uint32_t tsftl, tsfth; 3680 3681 tsfth = RTW_READ(regs, RTW_TSFTRH); 3682 tsftl = RTW_READ(regs, RTW_TSFTRL); 3683 if (tsftl < rstamp) /* Compensate for rollover. */ 3684 tsfth--; 3685 return ((uint64_t)tsfth << 32) | rstamp; 3686 } 3687 3688 static void 3689 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3690 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3691 { 3692 struct ifnet *ifp = ic->ic_ifp; 3693 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3694 3695 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3696 3697 switch (subtype) { 3698 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3699 case IEEE80211_FC0_SUBTYPE_BEACON: 3700 if (ic->ic_opmode == IEEE80211_M_IBSS && 3701 ic->ic_state == IEEE80211_S_RUN && 3702 device_is_active(sc->sc_dev)) { 3703 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp); 3704 if (le64toh(ni->ni_tstamp.tsf) >= tsf) 3705 (void)ieee80211_ibss_merge(ni); 3706 } 3707 break; 3708 default: 3709 break; 3710 } 3711 return; 3712 } 3713 3714 static struct ieee80211_node * 3715 rtw_node_alloc(struct ieee80211_node_table *nt) 3716 { 3717 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3718 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3719 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3720 3721 DPRINTF(sc, RTW_DEBUG_NODE, 3722 ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 3723 return ni; 3724 } 3725 3726 static void 3727 rtw_node_free(struct ieee80211_node *ni) 3728 { 3729 struct ieee80211com *ic = ni->ni_ic; 3730 struct ifnet *ifp = ic->ic_ifp; 3731 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3732 3733 DPRINTF(sc, RTW_DEBUG_NODE, 3734 ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 3735 ether_sprintf(ni->ni_bssid))); 3736 (*sc->sc_mtbl.mt_node_free)(ni); 3737 } 3738 3739 static int 3740 rtw_media_change(struct ifnet *ifp) 3741 { 3742 int error; 3743 3744 error = ieee80211_media_change(ifp); 3745 if (error == ENETRESET) { 3746 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3747 (IFF_RUNNING|IFF_UP)) 3748 rtw_init(ifp); /* XXX lose error */ 3749 error = 0; 3750 } 3751 return error; 3752 } 3753 3754 static void 3755 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3756 { 3757 struct rtw_softc *sc = ifp->if_softc; 3758 3759 if (!device_is_active(sc->sc_dev)) { 3760 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3761 imr->ifm_status = 0; 3762 return; 3763 } 3764 ieee80211_media_status(ifp, imr); 3765 } 3766 3767 static inline void 3768 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3769 { 3770 (void)strlcpy(ifp->if_xname, dvname, IFNAMSIZ); 3771 ifp->if_softc = softc; 3772 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3773 IFF_NOTRAILERS; 3774 ifp->if_ioctl = rtw_ioctl; 3775 ifp->if_start = rtw_start; 3776 ifp->if_watchdog = rtw_watchdog; 3777 ifp->if_init = rtw_init; 3778 ifp->if_stop = rtw_stop; 3779 } 3780 3781 static inline void 3782 rtw_set80211props(struct ieee80211com *ic) 3783 { 3784 int nrate; 3785 ic->ic_phytype = IEEE80211_T_DS; 3786 ic->ic_opmode = IEEE80211_M_STA; 3787 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3788 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 3789 3790 nrate = 0; 3791 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3792 IEEE80211_RATE_BASIC | 2; 3793 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3794 IEEE80211_RATE_BASIC | 4; 3795 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3796 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3797 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3798 } 3799 3800 static inline void 3801 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3802 { 3803 mtbl->mt_newstate = ic->ic_newstate; 3804 ic->ic_newstate = rtw_newstate; 3805 3806 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3807 ic->ic_recv_mgmt = rtw_recv_mgmt; 3808 3809 mtbl->mt_node_free = ic->ic_node_free; 3810 ic->ic_node_free = rtw_node_free; 3811 3812 mtbl->mt_node_alloc = ic->ic_node_alloc; 3813 ic->ic_node_alloc = rtw_node_alloc; 3814 3815 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3816 ic->ic_crypto.cs_key_set = rtw_key_set; 3817 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3818 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3819 } 3820 3821 static inline void 3822 rtw_init_radiotap(struct rtw_softc *sc) 3823 { 3824 uint32_t present; 3825 3826 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3827 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3828 3829 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 3830 present = htole32(RTW_PHILIPS_RX_RADIOTAP_PRESENT); 3831 else 3832 present = htole32(RTW_RX_RADIOTAP_PRESENT); 3833 sc->sc_rxtap.rr_ihdr.it_present = present; 3834 3835 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3836 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3837 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3838 } 3839 3840 static int 3841 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3842 { 3843 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3844 SIMPLEQ_INIT(&tsb->tsb_freeq); 3845 tsb->tsb_ndesc = qlen; 3846 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3847 M_NOWAIT); 3848 if (tsb->tsb_desc == NULL) 3849 return ENOMEM; 3850 return 0; 3851 } 3852 3853 static void 3854 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3855 { 3856 int pri; 3857 struct rtw_txsoft_blk *tsb; 3858 3859 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3860 tsb = &sc->sc_txsoft_blk[pri]; 3861 free(tsb->tsb_desc, M_DEVBUF); 3862 tsb->tsb_desc = NULL; 3863 } 3864 } 3865 3866 static int 3867 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3868 { 3869 int pri, rc = 0; 3870 int qlen[RTW_NTXPRI] = 3871 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3872 struct rtw_txsoft_blk *tsbs; 3873 3874 tsbs = sc->sc_txsoft_blk; 3875 3876 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3877 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3878 if (rc != 0) 3879 break; 3880 } 3881 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3882 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3883 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3884 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3885 return rc; 3886 } 3887 3888 static void 3889 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3890 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3891 { 3892 tdb->tdb_ndesc = ndesc; 3893 tdb->tdb_desc = desc; 3894 tdb->tdb_physbase = physbase; 3895 tdb->tdb_ofs = ofs; 3896 3897 (void)memset(tdb->tdb_desc, 0, 3898 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3899 3900 rtw_txdesc_blk_init(tdb); 3901 tdb->tdb_next = 0; 3902 } 3903 3904 static void 3905 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3906 { 3907 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3908 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3909 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3910 3911 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3912 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3913 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3914 3915 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3916 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3917 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3918 3919 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3920 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3921 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3922 } 3923 3924 static struct rtw_rf * 3925 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3926 { 3927 rtw_rf_write_t rf_write; 3928 struct rtw_rf *rf; 3929 3930 switch (rfchipid) { 3931 default: 3932 rf_write = rtw_rf_hostwrite; 3933 break; 3934 case RTW_RFCHIPID_INTERSIL: 3935 case RTW_RFCHIPID_PHILIPS: 3936 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3937 case RTW_RFCHIPID_RFMD: 3938 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3939 break; 3940 } 3941 3942 switch (rfchipid) { 3943 case RTW_RFCHIPID_GCT: 3944 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0); 3945 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3946 break; 3947 case RTW_RFCHIPID_MAXIM: 3948 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3949 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3950 break; 3951 case RTW_RFCHIPID_PHILIPS: 3952 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3953 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3954 break; 3955 case RTW_RFCHIPID_RFMD: 3956 /* XXX RFMD has no RF constructor */ 3957 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3958 /*FALLTHROUGH*/ 3959 default: 3960 return NULL; 3961 } 3962 rf->rf_continuous_tx_cb = 3963 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3964 rf->rf_continuous_tx_arg = (void *)sc; 3965 return rf; 3966 } 3967 3968 /* Revision C and later use a different PHY delay setting than 3969 * revisions A and B. 3970 */ 3971 static uint8_t 3972 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 3973 { 3974 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3975 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3976 3977 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); 3978 3979 RTW_WRITE(regs, RTW_RCR, REVAB); 3980 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3981 RTW_WRITE(regs, RTW_RCR, REVC); 3982 3983 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3984 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3985 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3986 3987 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 3988 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3989 3990 return phydelay; 3991 #undef REVC 3992 } 3993 3994 void 3995 rtw_attach(struct rtw_softc *sc) 3996 { 3997 struct ifnet *ifp = &sc->sc_if; 3998 struct ieee80211com *ic = &sc->sc_ic; 3999 struct rtw_txsoft_blk *tsb; 4000 int pri, rc; 4001 4002 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 4003 4004 rtw_cipher_wep = ieee80211_cipher_wep; 4005 rtw_cipher_wep.ic_decap = rtw_wep_decap; 4006 4007 NEXT_ATTACH_STATE(sc, DETACHED); 4008 4009 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 4010 case RTW_TCR_HWVERID_F: 4011 sc->sc_hwverid = 'F'; 4012 break; 4013 case RTW_TCR_HWVERID_D: 4014 sc->sc_hwverid = 'D'; 4015 break; 4016 default: 4017 sc->sc_hwverid = '?'; 4018 break; 4019 } 4020 aprint_verbose_dev(sc->sc_dev, "hardware version %c\n", 4021 sc->sc_hwverid); 4022 4023 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 4024 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 4025 0); 4026 4027 if (rc != 0) { 4028 aprint_error_dev(sc->sc_dev, 4029 "could not allocate hw descriptors, error %d\n", rc); 4030 goto err; 4031 } 4032 4033 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 4034 4035 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 4036 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 4037 (void **)&sc->sc_descs, BUS_DMA_COHERENT); 4038 4039 if (rc != 0) { 4040 aprint_error_dev(sc->sc_dev, 4041 "could not map hw descriptors, error %d\n", rc); 4042 goto err; 4043 } 4044 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 4045 4046 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 4047 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 4048 4049 if (rc != 0) { 4050 aprint_error_dev(sc->sc_dev, 4051 "could not create DMA map for hw descriptors, error %d\n", 4052 rc); 4053 goto err; 4054 } 4055 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 4056 4057 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 4058 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 4059 4060 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4061 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 4062 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 4063 } 4064 4065 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 4066 sizeof(struct rtw_descs), NULL, 0); 4067 4068 if (rc != 0) { 4069 aprint_error_dev(sc->sc_dev, 4070 "could not load DMA map for hw descriptors, error %d\n", 4071 rc); 4072 goto err; 4073 } 4074 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 4075 4076 if (rtw_txsoft_blk_setup_all(sc) != 0) 4077 goto err; 4078 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 4079 4080 rtw_txdesc_blk_setup_all(sc); 4081 4082 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 4083 4084 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 4085 4086 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4087 tsb = &sc->sc_txsoft_blk[pri]; 4088 4089 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 4090 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 4091 aprint_error_dev(sc->sc_dev, 4092 "could not load DMA map for hw tx descriptors, " 4093 "error %d\n", rc); 4094 goto err; 4095 } 4096 } 4097 4098 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 4099 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 4100 RTW_RXQLEN)) != 0) { 4101 aprint_error_dev(sc->sc_dev, 4102 "could not load DMA map for hw rx descriptors, error %d\n", 4103 rc); 4104 goto err; 4105 } 4106 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 4107 4108 /* Reset the chip to a known state. */ 4109 if (rtw_reset(sc) != 0) 4110 goto err; 4111 NEXT_ATTACH_STATE(sc, FINISH_RESET); 4112 4113 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 4114 4115 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 4116 sc->sc_flags |= RTW_F_9356SROM; 4117 4118 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 4119 sc->sc_dev) != 0) 4120 goto err; 4121 4122 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 4123 4124 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 4125 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 4126 sc->sc_dev) != 0) { 4127 aprint_error_dev(sc->sc_dev, 4128 "attach failed, malformed serial ROM\n"); 4129 goto err; 4130 } 4131 4132 aprint_verbose_dev(sc->sc_dev, "%s PHY\n", 4133 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 4134 4135 aprint_verbose_dev(sc->sc_dev, "carrier-sense threshold %u\n", 4136 sc->sc_csthr); 4137 4138 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 4139 4140 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 4141 sc->sc_flags & RTW_F_DIGPHY); 4142 4143 if (sc->sc_rf == NULL) { 4144 aprint_verbose_dev(sc->sc_dev, 4145 "attach failed, could not attach RF\n"); 4146 goto err; 4147 } 4148 4149 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 4150 4151 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4152 4153 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4154 ("%s: PHY delay %d\n", device_xname(sc->sc_dev), sc->sc_phydelay)); 4155 4156 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4157 rtw_identify_country(&sc->sc_regs, &sc->sc_locale); 4158 4159 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, sc->sc_dev); 4160 4161 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4162 sc->sc_dev) != 0) 4163 goto err; 4164 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4165 4166 rtw_setifprops(ifp, device_xname(sc->sc_dev), (void*)sc); 4167 4168 IFQ_SET_READY(&ifp->if_snd); 4169 4170 sc->sc_ic.ic_ifp = ifp; 4171 rtw_set80211props(&sc->sc_ic); 4172 4173 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4174 4175 /* 4176 * Call MI attach routines. 4177 */ 4178 if_attach(ifp); 4179 ieee80211_ifattach(&sc->sc_ic); 4180 4181 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4182 4183 /* possibly we should fill in our own sc_send_prresp, since 4184 * the RTL8180 is probably sending probe responses in ad hoc 4185 * mode. 4186 */ 4187 4188 /* complete initialization */ 4189 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4190 callout_init(&sc->sc_scan_ch, 0); 4191 4192 rtw_init_radiotap(sc); 4193 4194 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 4195 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4196 4197 NEXT_ATTACH_STATE(sc, FINISHED); 4198 4199 ieee80211_announce(ic); 4200 return; 4201 err: 4202 rtw_detach(sc); 4203 return; 4204 } 4205 4206 int 4207 rtw_detach(struct rtw_softc *sc) 4208 { 4209 struct ifnet *ifp = &sc->sc_if; 4210 int pri, s; 4211 4212 s = splnet(); 4213 4214 switch (sc->sc_attach_state) { 4215 case FINISHED: 4216 rtw_stop(ifp, 1); 4217 4218 pmf_device_deregister(sc->sc_dev); 4219 callout_stop(&sc->sc_scan_ch); 4220 ieee80211_ifdetach(&sc->sc_ic); 4221 if_detach(ifp); 4222 rtw_led_detach(&sc->sc_led_state); 4223 /*FALLTHROUGH*/ 4224 case FINISH_ID_STA: 4225 case FINISH_RF_ATTACH: 4226 rtw_rf_destroy(sc->sc_rf); 4227 sc->sc_rf = NULL; 4228 /*FALLTHROUGH*/ 4229 case FINISH_PARSE_SROM: 4230 case FINISH_READ_SROM: 4231 rtw_srom_free(&sc->sc_srom); 4232 /*FALLTHROUGH*/ 4233 case FINISH_RESET: 4234 case FINISH_RXMAPS_CREATE: 4235 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4236 RTW_RXQLEN); 4237 /*FALLTHROUGH*/ 4238 case FINISH_TXMAPS_CREATE: 4239 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4240 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4241 sc->sc_txsoft_blk[pri].tsb_desc, 4242 sc->sc_txsoft_blk[pri].tsb_ndesc); 4243 } 4244 /*FALLTHROUGH*/ 4245 case FINISH_TXDESCBLK_SETUP: 4246 case FINISH_TXCTLBLK_SETUP: 4247 rtw_txsoft_blk_cleanup_all(sc); 4248 /*FALLTHROUGH*/ 4249 case FINISH_DESCMAP_LOAD: 4250 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4251 /*FALLTHROUGH*/ 4252 case FINISH_DESCMAP_CREATE: 4253 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4254 /*FALLTHROUGH*/ 4255 case FINISH_DESC_MAP: 4256 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 4257 sizeof(struct rtw_descs)); 4258 /*FALLTHROUGH*/ 4259 case FINISH_DESC_ALLOC: 4260 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4261 sc->sc_desc_nsegs); 4262 /*FALLTHROUGH*/ 4263 case DETACHED: 4264 NEXT_ATTACH_STATE(sc, DETACHED); 4265 break; 4266 } 4267 splx(s); 4268 return 0; 4269 } 4270
Indexes created Mon Sep 29 15:09:53 GMT 2025