rtw.c revision 1.128.2.2
1 /* $NetBSD: rtw.c,v 1.128.2.2 2020/04/08 14:08:06 martin Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005, 2006, 2007 David Young. All rights 4 * reserved. 5 * 6 * Programmed for NetBSD by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 21 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 28 * OF SUCH DAMAGE. 29 */ 30 /* 31 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.128.2.2 2020/04/08 14:08:06 martin Exp $"); 36 37 38 #include <sys/param.h> 39 #include <sys/sysctl.h> 40 #include <sys/systm.h> 41 #include <sys/callout.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/time.h> 46 #include <sys/types.h> 47 #include <sys/device.h> 48 #include <sys/sockio.h> 49 50 #include <machine/endian.h> 51 #include <sys/bus.h> 52 #include <sys/intr.h> /* splnet */ 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net80211/ieee80211_netbsd.h> 59 #include <net80211/ieee80211_var.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <net/bpf.h> 63 64 #include <dev/ic/rtwreg.h> 65 #include <dev/ic/rtwvar.h> 66 #include <dev/ic/rtwphyio.h> 67 #include <dev/ic/rtwphy.h> 68 69 #include <dev/ic/smc93cx6var.h> 70 71 static int rtw_rfprog_fallback = 0; 72 static int rtw_host_rfio = 0; 73 74 #ifdef RTW_DEBUG 75 int rtw_debug = 0; 76 static int rtw_rxbufs_limit = RTW_RXQLEN; 77 #endif /* RTW_DEBUG */ 78 79 #define NEXT_ATTACH_STATE(sc, state) do { \ 80 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 81 ("%s: attach state %s\n", __func__, #state)); \ 82 sc->sc_attach_state = state; \ 83 } while (0) 84 85 int rtw_dwelltime = 200; /* milliseconds */ 86 static struct ieee80211_cipher rtw_cipher_wep; 87 88 static void rtw_disable_interrupts(struct rtw_regs *); 89 static void rtw_enable_interrupts(struct rtw_softc *); 90 91 static int rtw_init(struct ifnet *); 92 static void rtw_softintr(void *); 93 94 static void rtw_start(struct ifnet *); 95 static void rtw_reset_oactive(struct rtw_softc *); 96 static struct mbuf *rtw_beacon_alloc(struct rtw_softc *, 97 struct ieee80211_node *); 98 static u_int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *); 99 100 static void rtw_io_enable(struct rtw_softc *, uint8_t, int); 101 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 102 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 103 const uint8_t[IEEE80211_ADDR_LEN]); 104 static void rtw_key_update_end(struct ieee80211com *); 105 static void rtw_key_update_begin(struct ieee80211com *); 106 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 107 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 108 109 static void rtw_led_attach(struct rtw_led_state *, void *); 110 static void rtw_led_detach(struct rtw_led_state *); 111 static void rtw_led_init(struct rtw_regs *); 112 static void rtw_led_slowblink(void *); 113 static void rtw_led_fastblink(void *); 114 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 115 116 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 117 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 118 #ifdef RTW_DEBUG 119 static void rtw_dump_rings(struct rtw_softc *sc); 120 static void rtw_print_txdesc(struct rtw_softc *, const char *, 121 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 122 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 123 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 124 #endif /* RTW_DEBUG */ 125 #ifdef RTW_DIAG 126 static void rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln); 127 #endif /* RTW_DIAG */ 128 129 /* 130 * Setup sysctl(3) MIB, hw.rtw.* 131 * 132 * TBD condition CTLFLAG_PERMANENT on being a module or not 133 */ 134 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 135 { 136 int rc; 137 const struct sysctlnode *cnode, *rnode; 138 139 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 140 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 141 "Realtek RTL818x 802.11 controls", 142 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) 143 goto err; 144 145 #ifdef RTW_DEBUG 146 /* control debugging printfs */ 147 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 148 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 149 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 150 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 151 CTL_CREATE, CTL_EOL)) != 0) 152 goto err; 153 154 /* Limit rx buffers, for simulating resource exhaustion. */ 155 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 156 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 157 "rxbufs_limit", 158 SYSCTL_DESCR("Set rx buffers limit"), 159 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 160 CTL_CREATE, CTL_EOL)) != 0) 161 goto err; 162 163 #endif /* RTW_DEBUG */ 164 /* set fallback RF programming method */ 165 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 166 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 167 "rfprog_fallback", 168 SYSCTL_DESCR("Set fallback RF programming method"), 169 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 170 CTL_CREATE, CTL_EOL)) != 0) 171 goto err; 172 173 /* force host to control RF I/O bus */ 174 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 175 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 176 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 177 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 178 CTL_CREATE, CTL_EOL)) != 0) 179 goto err; 180 181 return; 182 err: 183 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 184 } 185 186 static int 187 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 188 { 189 int error, t; 190 struct sysctlnode node; 191 192 node = *rnode; 193 t = *(int*)rnode->sysctl_data; 194 node.sysctl_data = &t; 195 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 196 if (error || newp == NULL) 197 return (error); 198 199 if (t < lower || t > upper) 200 return (EINVAL); 201 202 *(int*)rnode->sysctl_data = t; 203 204 return (0); 205 } 206 207 static int 208 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 209 { 210 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 211 __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 212 } 213 214 static int 215 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 216 { 217 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 218 } 219 220 #ifdef RTW_DEBUG 221 static int 222 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 223 { 224 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 225 0, RTW_DEBUG_MAX); 226 } 227 228 static int 229 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 230 { 231 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 232 0, RTW_RXQLEN); 233 } 234 235 static void 236 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 237 { 238 #define PRINTREG32(sc, reg) \ 239 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 240 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 241 dvname, reg, RTW_READ(regs, reg))) 242 243 #define PRINTREG16(sc, reg) \ 244 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 245 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 246 dvname, reg, RTW_READ16(regs, reg))) 247 248 #define PRINTREG8(sc, reg) \ 249 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 250 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 251 dvname, reg, RTW_READ8(regs, reg))) 252 253 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 254 255 PRINTREG32(regs, RTW_IDR0); 256 PRINTREG32(regs, RTW_IDR1); 257 PRINTREG32(regs, RTW_MAR0); 258 PRINTREG32(regs, RTW_MAR1); 259 PRINTREG32(regs, RTW_TSFTRL); 260 PRINTREG32(regs, RTW_TSFTRH); 261 PRINTREG32(regs, RTW_TLPDA); 262 PRINTREG32(regs, RTW_TNPDA); 263 PRINTREG32(regs, RTW_THPDA); 264 PRINTREG32(regs, RTW_TCR); 265 PRINTREG32(regs, RTW_RCR); 266 PRINTREG32(regs, RTW_TINT); 267 PRINTREG32(regs, RTW_TBDA); 268 PRINTREG32(regs, RTW_ANAPARM); 269 PRINTREG32(regs, RTW_BB); 270 PRINTREG32(regs, RTW_PHYCFG); 271 PRINTREG32(regs, RTW_WAKEUP0L); 272 PRINTREG32(regs, RTW_WAKEUP0H); 273 PRINTREG32(regs, RTW_WAKEUP1L); 274 PRINTREG32(regs, RTW_WAKEUP1H); 275 PRINTREG32(regs, RTW_WAKEUP2LL); 276 PRINTREG32(regs, RTW_WAKEUP2LH); 277 PRINTREG32(regs, RTW_WAKEUP2HL); 278 PRINTREG32(regs, RTW_WAKEUP2HH); 279 PRINTREG32(regs, RTW_WAKEUP3LL); 280 PRINTREG32(regs, RTW_WAKEUP3LH); 281 PRINTREG32(regs, RTW_WAKEUP3HL); 282 PRINTREG32(regs, RTW_WAKEUP3HH); 283 PRINTREG32(regs, RTW_WAKEUP4LL); 284 PRINTREG32(regs, RTW_WAKEUP4LH); 285 PRINTREG32(regs, RTW_WAKEUP4HL); 286 PRINTREG32(regs, RTW_WAKEUP4HH); 287 PRINTREG32(regs, RTW_DK0); 288 PRINTREG32(regs, RTW_DK1); 289 PRINTREG32(regs, RTW_DK2); 290 PRINTREG32(regs, RTW_DK3); 291 PRINTREG32(regs, RTW_RETRYCTR); 292 PRINTREG32(regs, RTW_RDSAR); 293 PRINTREG32(regs, RTW_FER); 294 PRINTREG32(regs, RTW_FEMR); 295 PRINTREG32(regs, RTW_FPSR); 296 PRINTREG32(regs, RTW_FFER); 297 298 /* 16-bit registers */ 299 PRINTREG16(regs, RTW_BRSR); 300 PRINTREG16(regs, RTW_IMR); 301 PRINTREG16(regs, RTW_ISR); 302 PRINTREG16(regs, RTW_BCNITV); 303 PRINTREG16(regs, RTW_ATIMWND); 304 PRINTREG16(regs, RTW_BINTRITV); 305 PRINTREG16(regs, RTW_ATIMTRITV); 306 PRINTREG16(regs, RTW_CRC16ERR); 307 PRINTREG16(regs, RTW_CRC0); 308 PRINTREG16(regs, RTW_CRC1); 309 PRINTREG16(regs, RTW_CRC2); 310 PRINTREG16(regs, RTW_CRC3); 311 PRINTREG16(regs, RTW_CRC4); 312 PRINTREG16(regs, RTW_CWR); 313 314 /* 8-bit registers */ 315 PRINTREG8(regs, RTW_CR); 316 PRINTREG8(regs, RTW_9346CR); 317 PRINTREG8(regs, RTW_CONFIG0); 318 PRINTREG8(regs, RTW_CONFIG1); 319 PRINTREG8(regs, RTW_CONFIG2); 320 PRINTREG8(regs, RTW_MSR); 321 PRINTREG8(regs, RTW_CONFIG3); 322 PRINTREG8(regs, RTW_CONFIG4); 323 PRINTREG8(regs, RTW_TESTR); 324 PRINTREG8(regs, RTW_PSR); 325 PRINTREG8(regs, RTW_SCR); 326 PRINTREG8(regs, RTW_PHYDELAY); 327 PRINTREG8(regs, RTW_CRCOUNT); 328 PRINTREG8(regs, RTW_PHYADDR); 329 PRINTREG8(regs, RTW_PHYDATAW); 330 PRINTREG8(regs, RTW_PHYDATAR); 331 PRINTREG8(regs, RTW_CONFIG5); 332 PRINTREG8(regs, RTW_TPPOLL); 333 334 PRINTREG16(regs, RTW_BSSID16); 335 PRINTREG32(regs, RTW_BSSID32); 336 #undef PRINTREG32 337 #undef PRINTREG16 338 #undef PRINTREG8 339 } 340 #endif /* RTW_DEBUG */ 341 342 void 343 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 344 { 345 struct rtw_regs *regs = &sc->sc_regs; 346 347 uint32_t tcr; 348 tcr = RTW_READ(regs, RTW_TCR); 349 tcr &= ~RTW_TCR_LBK_MASK; 350 if (enable) 351 tcr |= RTW_TCR_LBK_CONT; 352 else 353 tcr |= RTW_TCR_LBK_NORMAL; 354 RTW_WRITE(regs, RTW_TCR, tcr); 355 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 356 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 357 rtw_txdac_enable(sc, !enable); 358 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 359 rtw_set_access(regs, RTW_ACCESS_NONE); 360 } 361 362 #ifdef RTW_DEBUG 363 static const char * 364 rtw_access_string(enum rtw_access access) 365 { 366 switch (access) { 367 case RTW_ACCESS_NONE: 368 return "none"; 369 case RTW_ACCESS_CONFIG: 370 return "config"; 371 case RTW_ACCESS_ANAPARM: 372 return "anaparm"; 373 default: 374 return "unknown"; 375 } 376 } 377 #endif /* RTW_DEBUG */ 378 379 static void 380 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 381 { 382 KASSERT(/* naccess >= RTW_ACCESS_NONE && */ 383 naccess <= RTW_ACCESS_ANAPARM); 384 KASSERT(/* regs->r_access >= RTW_ACCESS_NONE && */ 385 regs->r_access <= RTW_ACCESS_ANAPARM); 386 387 if (naccess == regs->r_access) 388 return; 389 390 switch (naccess) { 391 case RTW_ACCESS_NONE: 392 switch (regs->r_access) { 393 case RTW_ACCESS_ANAPARM: 394 rtw_anaparm_enable(regs, 0); 395 /*FALLTHROUGH*/ 396 case RTW_ACCESS_CONFIG: 397 rtw_config0123_enable(regs, 0); 398 /*FALLTHROUGH*/ 399 case RTW_ACCESS_NONE: 400 break; 401 } 402 break; 403 case RTW_ACCESS_CONFIG: 404 switch (regs->r_access) { 405 case RTW_ACCESS_NONE: 406 rtw_config0123_enable(regs, 1); 407 /*FALLTHROUGH*/ 408 case RTW_ACCESS_CONFIG: 409 break; 410 case RTW_ACCESS_ANAPARM: 411 rtw_anaparm_enable(regs, 0); 412 break; 413 } 414 break; 415 case RTW_ACCESS_ANAPARM: 416 switch (regs->r_access) { 417 case RTW_ACCESS_NONE: 418 rtw_config0123_enable(regs, 1); 419 /*FALLTHROUGH*/ 420 case RTW_ACCESS_CONFIG: 421 rtw_anaparm_enable(regs, 1); 422 /*FALLTHROUGH*/ 423 case RTW_ACCESS_ANAPARM: 424 break; 425 } 426 break; 427 } 428 } 429 430 void 431 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 432 { 433 rtw_set_access1(regs, access); 434 RTW_DPRINTF(RTW_DEBUG_ACCESS, 435 ("%s: access %s -> %s\n", __func__, 436 rtw_access_string(regs->r_access), 437 rtw_access_string(access))); 438 regs->r_access = access; 439 } 440 441 /* 442 * Enable registers, switch register banks. 443 */ 444 void 445 rtw_config0123_enable(struct rtw_regs *regs, int enable) 446 { 447 uint8_t ecr; 448 ecr = RTW_READ8(regs, RTW_9346CR); 449 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 450 if (enable) 451 ecr |= RTW_9346CR_EEM_CONFIG; 452 else { 453 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 454 ecr |= RTW_9346CR_EEM_NORMAL; 455 } 456 RTW_WRITE8(regs, RTW_9346CR, ecr); 457 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 458 } 459 460 /* requires rtw_config0123_enable(, 1) */ 461 void 462 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 463 { 464 uint8_t cfg3; 465 466 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 467 cfg3 |= RTW_CONFIG3_CLKRUNEN; 468 if (enable) 469 cfg3 |= RTW_CONFIG3_PARMEN; 470 else 471 cfg3 &= ~RTW_CONFIG3_PARMEN; 472 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 473 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 474 } 475 476 /* requires rtw_anaparm_enable(, 1) */ 477 void 478 rtw_txdac_enable(struct rtw_softc *sc, int enable) 479 { 480 uint32_t anaparm; 481 struct rtw_regs *regs = &sc->sc_regs; 482 483 anaparm = RTW_READ(regs, RTW_ANAPARM); 484 if (enable) 485 anaparm &= ~RTW_ANAPARM_TXDACOFF; 486 else 487 anaparm |= RTW_ANAPARM_TXDACOFF; 488 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 489 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 490 } 491 492 static inline int 493 rtw_chip_reset1(struct rtw_regs *regs, device_t dev) 494 { 495 uint8_t cr; 496 int i; 497 498 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 499 500 RTW_WBR(regs, RTW_CR, RTW_CR); 501 502 for (i = 0; i < 1000; i++) { 503 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 504 RTW_DPRINTF(RTW_DEBUG_RESET, 505 ("%s: reset in %dus\n", device_xname(dev), i)); 506 return 0; 507 } 508 RTW_RBR(regs, RTW_CR, RTW_CR); 509 DELAY(10); /* 10us */ 510 } 511 512 aprint_error_dev(dev, "reset failed\n"); 513 return ETIMEDOUT; 514 } 515 516 static inline int 517 rtw_chip_reset(struct rtw_regs *regs, device_t dev) 518 { 519 uint32_t tcr; 520 521 /* from Linux driver */ 522 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 523 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK); 524 525 RTW_WRITE(regs, RTW_TCR, tcr); 526 527 RTW_WBW(regs, RTW_CR, RTW_TCR); 528 529 return rtw_chip_reset1(regs, dev); 530 } 531 532 static int 533 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen) 534 { 535 struct ieee80211_key keycopy; 536 537 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 538 539 keycopy = *k; 540 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 541 542 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, hdrlen); 543 } 544 545 static int 546 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 547 { 548 struct rtw_softc *sc = ic->ic_ifp->if_softc; 549 550 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, 551 k->wk_keyix)); 552 553 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID); 554 555 if (k->wk_keylen != 0 && 556 k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 557 sc->sc_flags &= ~RTW_F_DK_VALID; 558 559 return 1; 560 } 561 562 static int 563 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 564 const uint8_t mac[IEEE80211_ADDR_LEN]) 565 { 566 struct rtw_softc *sc = ic->ic_ifp->if_softc; 567 568 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 569 570 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID); 571 572 sc->sc_flags &= ~RTW_F_DK_VALID; 573 574 return 1; 575 } 576 577 static void 578 rtw_key_update_begin(struct ieee80211com *ic) 579 { 580 #ifdef RTW_DEBUG 581 struct ifnet *ifp = ic->ic_ifp; 582 struct rtw_softc *sc = ifp->if_softc; 583 #endif 584 585 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 586 } 587 588 static void 589 rtw_tx_kick(struct rtw_regs *regs, uint8_t ringsel) 590 { 591 uint8_t tppoll; 592 593 tppoll = RTW_READ8(regs, RTW_TPPOLL); 594 tppoll &= ~RTW_TPPOLL_SALL; 595 tppoll |= ringsel & RTW_TPPOLL_ALL; 596 RTW_WRITE8(regs, RTW_TPPOLL, tppoll); 597 RTW_SYNC(regs, RTW_TPPOLL, RTW_TPPOLL); 598 } 599 600 static void 601 rtw_key_update_end(struct ieee80211com *ic) 602 { 603 struct ifnet *ifp = ic->ic_ifp; 604 struct rtw_softc *sc = ifp->if_softc; 605 606 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 607 608 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 || 609 !device_is_active(sc->sc_dev)) 610 return; 611 612 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 613 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 614 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 615 (ifp->if_flags & IFF_RUNNING) != 0); 616 } 617 618 static bool 619 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k) 620 { 621 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 622 return false; 623 624 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) || 625 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13); 626 } 627 628 static void 629 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 630 { 631 uint8_t psr, scr; 632 int i, keylen = 0; 633 struct rtw_regs *regs; 634 union rtw_keys *rk; 635 636 regs = &sc->sc_regs; 637 rk = &sc->sc_keys; 638 639 (void)memset(rk, 0, sizeof(*rk)); 640 641 /* Temporarily use software crypto for all keys. */ 642 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 643 if (wk[i].wk_cipher == &rtw_cipher_wep) 644 wk[i].wk_cipher = &ieee80211_cipher_wep; 645 } 646 647 rtw_set_access(regs, RTW_ACCESS_CONFIG); 648 649 psr = RTW_READ8(regs, RTW_PSR); 650 scr = RTW_READ8(regs, RTW_SCR); 651 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 652 653 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 654 goto out; 655 656 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 657 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i])) 658 continue; 659 if (i == txkey) { 660 keylen = wk[i].wk_keylen; 661 break; 662 } 663 keylen = MAX(keylen, wk[i].wk_keylen); 664 } 665 666 if (keylen == 5) 667 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON; 668 else if (keylen == 13) 669 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON; 670 671 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 672 if (wk[i].wk_keylen != keylen || 673 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 674 continue; 675 /* h/w will decrypt, s/w still strips headers */ 676 wk[i].wk_cipher = &rtw_cipher_wep; 677 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 678 } 679 680 out: 681 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 682 683 bus_space_write_region_stream_4(regs->r_bt, regs->r_bh, 684 RTW_DK0, rk->rk_words, __arraycount(rk->rk_words)); 685 686 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 687 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 688 689 RTW_DPRINTF(RTW_DEBUG_KEY, 690 ("%s.%d: scr %02" PRIx8 ", keylen %d\n", __func__, __LINE__, scr, 691 keylen)); 692 693 RTW_WBW(regs, RTW_DK0, RTW_PSR); 694 RTW_WRITE8(regs, RTW_PSR, psr); 695 RTW_WBW(regs, RTW_PSR, RTW_SCR); 696 RTW_WRITE8(regs, RTW_SCR, scr); 697 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 698 rtw_set_access(regs, RTW_ACCESS_NONE); 699 sc->sc_flags |= RTW_F_DK_VALID; 700 } 701 702 static inline int 703 rtw_recall_eeprom(struct rtw_regs *regs, device_t dev) 704 { 705 int i; 706 uint8_t ecr; 707 708 ecr = RTW_READ8(regs, RTW_9346CR); 709 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 710 RTW_WRITE8(regs, RTW_9346CR, ecr); 711 712 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 713 714 /* wait 25ms for completion */ 715 for (i = 0; i < 250; i++) { 716 ecr = RTW_READ8(regs, RTW_9346CR); 717 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 718 RTW_DPRINTF(RTW_DEBUG_RESET, 719 ("%s: recall EEPROM in %dus\n", device_xname(dev), 720 i * 100)); 721 return 0; 722 } 723 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 724 DELAY(100); 725 } 726 aprint_error_dev(dev, "recall EEPROM failed\n"); 727 return ETIMEDOUT; 728 } 729 730 static inline int 731 rtw_reset(struct rtw_softc *sc) 732 { 733 int rc; 734 uint8_t config1; 735 736 sc->sc_flags &= ~RTW_F_DK_VALID; 737 738 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev)) != 0) 739 return rc; 740 741 rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev); 742 743 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 744 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 745 /* TBD turn off maximum power saving? */ 746 747 return 0; 748 } 749 750 static inline int 751 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 752 u_int ndescs) 753 { 754 int i, rc = 0; 755 for (i = 0; i < ndescs; i++) { 756 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 757 0, 0, &descs[i].ts_dmamap); 758 if (rc != 0) 759 break; 760 } 761 return rc; 762 } 763 764 static inline int 765 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 766 u_int ndescs) 767 { 768 int i, rc = 0; 769 for (i = 0; i < ndescs; i++) { 770 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 771 &descs[i].rs_dmamap); 772 if (rc != 0) 773 break; 774 } 775 return rc; 776 } 777 778 static inline void 779 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 780 u_int ndescs) 781 { 782 int i; 783 for (i = 0; i < ndescs; i++) { 784 if (descs[i].rs_dmamap != NULL) 785 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 786 } 787 } 788 789 static inline void 790 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 791 u_int ndescs) 792 { 793 int i; 794 for (i = 0; i < ndescs; i++) { 795 if (descs[i].ts_dmamap != NULL) 796 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 797 } 798 } 799 800 static inline void 801 rtw_srom_free(struct rtw_srom *sr) 802 { 803 sr->sr_size = 0; 804 if (sr->sr_content == NULL) 805 return; 806 free(sr->sr_content, M_DEVBUF); 807 sr->sr_content = NULL; 808 } 809 810 static void 811 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, 812 uint8_t *cs_threshold, enum rtw_rfchipid *rfchipid, uint32_t *rcr) 813 { 814 *flags |= (RTW_F_DIGPHY | RTW_F_ANTDIV); 815 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 816 *rcr |= RTW_RCR_ENCS1; 817 *rfchipid = RTW_RFCHIPID_PHILIPS; 818 } 819 820 static int 821 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 822 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 823 device_t dev) 824 { 825 int i; 826 const char *rfname, *paname; 827 char scratch[sizeof("unknown 0xXX")]; 828 uint16_t srom_version; 829 830 *flags &= ~(RTW_F_DIGPHY | RTW_F_DFLANTB | RTW_F_ANTDIV); 831 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 832 833 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 834 835 if (srom_version <= 0x0101) { 836 aprint_error_dev(dev, 837 "SROM version %d.%d is not understood, " 838 "limping along with defaults\n", 839 srom_version >> 8, srom_version & 0xff); 840 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 841 return 0; 842 } else { 843 aprint_verbose_dev(dev, "SROM version %d.%d\n", 844 srom_version >> 8, srom_version & 0xff); 845 } 846 847 uint8_t mac[IEEE80211_ADDR_LEN]; 848 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 849 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 850 __USE(mac); 851 852 RTW_DPRINTF(RTW_DEBUG_ATTACH, 853 ("%s: EEPROM MAC %s\n", device_xname(dev), ether_sprintf(mac))); 854 855 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 856 857 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 858 *flags |= RTW_F_ANTDIV; 859 860 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 861 * to be reversed. 862 */ 863 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 864 *flags |= RTW_F_DIGPHY; 865 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 866 *flags |= RTW_F_DFLANTB; 867 868 *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), 869 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 870 871 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0) 872 *flags |= RTW_C_RXWEP_104; 873 874 *flags |= RTW_C_RXWEP_40; /* XXX */ 875 876 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 877 switch (*rfchipid) { 878 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 879 rfname = "GCT GRF5101"; 880 paname = "Winspring WS9901"; 881 break; 882 case RTW_RFCHIPID_MAXIM: 883 rfname = "Maxim MAX2820"; /* guess */ 884 paname = "Maxim MAX2422"; /* guess */ 885 break; 886 case RTW_RFCHIPID_INTERSIL: 887 rfname = "Intersil HFA3873"; /* guess */ 888 paname = "Intersil <unknown>"; 889 break; 890 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 891 rfname = "Philips SA2400A"; 892 paname = "Philips SA2411"; 893 break; 894 case RTW_RFCHIPID_RFMD: 895 /* this is the same front-end as an atw(4)! */ 896 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 897 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 898 "SYN: Silicon Labs Si4126"; /* inferred from 899 * reference driver 900 */ 901 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 902 break; 903 case RTW_RFCHIPID_RESERVED: 904 rfname = paname = "reserved"; 905 break; 906 default: 907 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 908 rfname = paname = scratch; 909 } 910 aprint_normal_dev(dev, "RF: %s, PA: %s\n", rfname, paname); 911 912 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 913 case RTW_CONFIG0_GL_USA: 914 case _RTW_CONFIG0_GL_USA: 915 *locale = RTW_LOCALE_USA; 916 break; 917 case RTW_CONFIG0_GL_EUROPE: 918 *locale = RTW_LOCALE_EUROPE; 919 break; 920 case RTW_CONFIG0_GL_JAPAN: 921 *locale = RTW_LOCALE_JAPAN; 922 break; 923 default: 924 *locale = RTW_LOCALE_UNKNOWN; 925 break; 926 } 927 return 0; 928 } 929 930 /* Returns -1 on failure. */ 931 static int 932 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 933 device_t dev) 934 { 935 int rc; 936 struct seeprom_descriptor sd; 937 uint8_t ecr; 938 939 (void)memset(&sd, 0, sizeof(sd)); 940 941 ecr = RTW_READ8(regs, RTW_9346CR); 942 943 if ((flags & RTW_F_9356SROM) != 0) { 944 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", 945 device_xname(dev))); 946 sr->sr_size = 256; 947 sd.sd_chip = C56_66; 948 } else { 949 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", 950 device_xname(dev))); 951 sr->sr_size = 128; 952 sd.sd_chip = C46; 953 } 954 955 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 956 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 957 ecr |= RTW_9346CR_EEM_PROGRAM; 958 959 RTW_WRITE8(regs, RTW_9346CR, ecr); 960 961 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 962 963 if (sr->sr_content == NULL) { 964 aprint_error_dev(dev, "unable to allocate SROM buffer\n"); 965 return ENOMEM; 966 } 967 968 (void)memset(sr->sr_content, 0, sr->sr_size); 969 970 /* RTL8180 has a single 8-bit register for controlling the 971 * 93cx6 SROM. There is no "ready" bit. The RTL8180 972 * input/output sense is the reverse of read_seeprom's. 973 */ 974 sd.sd_tag = regs->r_bt; 975 sd.sd_bsh = regs->r_bh; 976 sd.sd_regsize = 1; 977 sd.sd_control_offset = RTW_9346CR; 978 sd.sd_status_offset = RTW_9346CR; 979 sd.sd_dataout_offset = RTW_9346CR; 980 sd.sd_CK = RTW_9346CR_EESK; 981 sd.sd_CS = RTW_9346CR_EECS; 982 sd.sd_DI = RTW_9346CR_EEDO; 983 sd.sd_DO = RTW_9346CR_EEDI; 984 /* make read_seeprom enter EEPROM read/write mode */ 985 sd.sd_MS = ecr; 986 sd.sd_RDY = 0; 987 988 /* TBD bus barriers */ 989 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 990 aprint_error_dev(dev, "could not read SROM\n"); 991 free(sr->sr_content, M_DEVBUF); 992 sr->sr_content = NULL; 993 return -1; /* XXX */ 994 } 995 996 /* end EEPROM read/write mode */ 997 RTW_WRITE8(regs, RTW_9346CR, 998 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 999 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 1000 1001 if ((rc = rtw_recall_eeprom(regs, dev)) != 0) 1002 return rc; 1003 1004 #ifdef RTW_DEBUG 1005 { 1006 int i; 1007 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1008 ("\n%s: serial ROM:\n\t", device_xname(dev))); 1009 for (i = 0; i < sr->sr_size/2; i++) { 1010 if (((i % 8) == 0) && (i != 0)) 1011 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 1012 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1013 (" %04x", sr->sr_content[i])); 1014 } 1015 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 1016 } 1017 #endif /* RTW_DEBUG */ 1018 return 0; 1019 } 1020 1021 static void 1022 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 1023 device_t dev) 1024 { 1025 uint8_t cfg4; 1026 const char *method; 1027 1028 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 1029 1030 switch (rfchipid) { 1031 default: 1032 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 1033 method = "fallback"; 1034 break; 1035 case RTW_RFCHIPID_INTERSIL: 1036 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1037 method = "Intersil"; 1038 break; 1039 case RTW_RFCHIPID_PHILIPS: 1040 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1041 method = "Philips"; 1042 break; 1043 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1044 case RTW_RFCHIPID_RFMD: 1045 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1046 method = "RFMD"; 1047 break; 1048 } 1049 1050 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1051 1052 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1053 1054 #ifdef RTW_DEBUG 1055 RTW_DPRINTF(RTW_DEBUG_INIT, 1056 ("%s: %s RF programming method, %#02x\n", device_xname(dev), method, 1057 RTW_READ8(regs, RTW_CONFIG4))); 1058 #else 1059 __USE(method); 1060 #endif 1061 } 1062 1063 static inline void 1064 rtw_init_channels(enum rtw_locale locale, 1065 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], device_t dev) 1066 { 1067 int i; 1068 const char *name = NULL; 1069 #define ADD_CHANNEL(_chans, _chan) do { \ 1070 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1071 (*_chans)[_chan].ic_freq = \ 1072 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1073 } while (0) 1074 1075 switch (locale) { 1076 case RTW_LOCALE_USA: /* 1-11 */ 1077 name = "USA"; 1078 for (i = 1; i <= 11; i++) 1079 ADD_CHANNEL(chans, i); 1080 break; 1081 case RTW_LOCALE_JAPAN: /* 1-14 */ 1082 name = "Japan"; 1083 ADD_CHANNEL(chans, 14); 1084 for (i = 1; i <= 14; i++) 1085 ADD_CHANNEL(chans, i); 1086 break; 1087 case RTW_LOCALE_EUROPE: /* 1-13 */ 1088 name = "Europe"; 1089 for (i = 1; i <= 13; i++) 1090 ADD_CHANNEL(chans, i); 1091 break; 1092 default: /* 10-11 allowed by most countries */ 1093 name = "<unknown>"; 1094 for (i = 10; i <= 11; i++) 1095 ADD_CHANNEL(chans, i); 1096 break; 1097 } 1098 aprint_normal_dev(dev, "Geographic Location %s\n", name); 1099 #undef ADD_CHANNEL 1100 } 1101 1102 1103 static inline void 1104 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale) 1105 { 1106 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1107 1108 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1109 case RTW_CONFIG0_GL_USA: 1110 case _RTW_CONFIG0_GL_USA: 1111 *locale = RTW_LOCALE_USA; 1112 break; 1113 case RTW_CONFIG0_GL_JAPAN: 1114 *locale = RTW_LOCALE_JAPAN; 1115 break; 1116 case RTW_CONFIG0_GL_EUROPE: 1117 *locale = RTW_LOCALE_EUROPE; 1118 break; 1119 default: 1120 *locale = RTW_LOCALE_UNKNOWN; 1121 break; 1122 } 1123 } 1124 1125 static inline int 1126 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1127 device_t dev) 1128 { 1129 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1130 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1131 }; 1132 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1133 idr1 = RTW_READ(regs, RTW_IDR1); 1134 1135 (*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7)); 1136 (*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15)); 1137 (*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23)); 1138 (*addr)[3] = __SHIFTOUT(idr0, __BITS(24, 31)); 1139 1140 (*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7)); 1141 (*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15)); 1142 1143 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1144 aprint_error_dev(dev, 1145 "could not get mac address, attach failed\n"); 1146 return ENXIO; 1147 } 1148 1149 aprint_normal_dev(dev, "802.11 address %s\n", ether_sprintf(*addr)); 1150 1151 return 0; 1152 } 1153 1154 static uint8_t 1155 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1156 struct ieee80211_channel *chan) 1157 { 1158 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1159 KASSERT(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14); 1160 return RTW_SR_GET(sr, idx); 1161 } 1162 1163 static void 1164 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1165 { 1166 int pri; 1167 /* nfree: the number of free descriptors in each ring. 1168 * The beacon ring is a special case: I do not let the 1169 * driver use all of the descriptors on the beacon ring. 1170 * The reasons are two-fold: 1171 * 1172 * (1) A BEACON descriptor's OWN bit is (apparently) not 1173 * updated, so the driver cannot easily know if the descriptor 1174 * belongs to it, or if it is racing the NIC. If the NIC 1175 * does not OWN every descriptor, then the driver can safely 1176 * update the descriptors when RTW_TBDA points at tdb_next. 1177 * 1178 * (2) I hope that the NIC will process more than one BEACON 1179 * descriptor in a single beacon interval, since that will 1180 * enable multiple-BSS support. Since the NIC does not 1181 * clear the OWN bit, there is no natural place for it to 1182 * stop processing BEACON desciptors. Maybe it will *not* 1183 * stop processing them! I do not want to chance the NIC 1184 * looping around and around a saturated beacon ring, so 1185 * I will leave one descriptor unOWNed at all times. 1186 */ 1187 u_int nfree[RTW_NTXPRI] = 1188 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, 1189 RTW_NTXDESCBCN - 1}; 1190 1191 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1192 tdb[pri].tdb_nfree = nfree[pri]; 1193 tdb[pri].tdb_next = 0; 1194 } 1195 } 1196 1197 static int 1198 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1199 { 1200 int i; 1201 struct rtw_txsoft *ts; 1202 1203 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1204 SIMPLEQ_INIT(&tsb->tsb_freeq); 1205 for (i = 0; i < tsb->tsb_ndesc; i++) { 1206 ts = &tsb->tsb_desc[i]; 1207 ts->ts_mbuf = NULL; 1208 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1209 } 1210 tsb->tsb_tx_timer = 0; 1211 return 0; 1212 } 1213 1214 static void 1215 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1216 { 1217 int pri; 1218 for (pri = 0; pri < RTW_NTXPRI; pri++) 1219 rtw_txsoft_blk_init(&tsb[pri]); 1220 } 1221 1222 static inline void 1223 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1224 { 1225 KASSERT(nsync <= rdb->rdb_ndesc); 1226 /* sync to end of ring */ 1227 if (desc0 + nsync > rdb->rdb_ndesc) { 1228 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1229 offsetof(struct rtw_descs, hd_rx[desc0]), 1230 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1231 nsync -= (rdb->rdb_ndesc - desc0); 1232 desc0 = 0; 1233 } 1234 1235 KASSERT(desc0 < rdb->rdb_ndesc); 1236 KASSERT(nsync <= rdb->rdb_ndesc); 1237 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1238 1239 /* sync what remains */ 1240 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1241 offsetof(struct rtw_descs, hd_rx[desc0]), 1242 sizeof(struct rtw_rxdesc) * nsync, ops); 1243 } 1244 1245 static void 1246 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1247 { 1248 /* sync to end of ring */ 1249 if (desc0 + nsync > tdb->tdb_ndesc) { 1250 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1251 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1252 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1253 ops); 1254 nsync -= (tdb->tdb_ndesc - desc0); 1255 desc0 = 0; 1256 } 1257 1258 /* sync what remains */ 1259 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1260 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1261 sizeof(struct rtw_txdesc) * nsync, ops); 1262 } 1263 1264 static void 1265 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1266 { 1267 int pri; 1268 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1269 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1270 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1271 } 1272 } 1273 1274 static void 1275 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1276 { 1277 int i; 1278 struct rtw_rxsoft *rs; 1279 1280 for (i = 0; i < RTW_RXQLEN; i++) { 1281 rs = &desc[i]; 1282 if (rs->rs_mbuf == NULL) 1283 continue; 1284 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1285 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1286 bus_dmamap_unload(dmat, rs->rs_dmamap); 1287 m_freem(rs->rs_mbuf); 1288 rs->rs_mbuf = NULL; 1289 } 1290 } 1291 1292 static inline int 1293 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1294 { 1295 int rc; 1296 struct mbuf *m; 1297 1298 MGETHDR(m, M_DONTWAIT, MT_DATA); 1299 if (m == NULL) 1300 return ENOBUFS; 1301 1302 MCLGET(m, M_DONTWAIT); 1303 if ((m->m_flags & M_EXT) == 0) { 1304 m_freem(m); 1305 return ENOBUFS; 1306 } 1307 1308 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1309 1310 if (rs->rs_mbuf != NULL) 1311 bus_dmamap_unload(dmat, rs->rs_dmamap); 1312 1313 rs->rs_mbuf = NULL; 1314 1315 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1316 if (rc != 0) { 1317 m_freem(m); 1318 return -1; 1319 } 1320 1321 rs->rs_mbuf = m; 1322 1323 return 0; 1324 } 1325 1326 static int 1327 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1328 int *ndesc, device_t dev) 1329 { 1330 int i, rc = 0; 1331 struct rtw_rxsoft *rs; 1332 1333 for (i = 0; i < RTW_RXQLEN; i++) { 1334 rs = &desc[i]; 1335 /* we're in rtw_init, so there should be no mbufs allocated */ 1336 KASSERT(rs->rs_mbuf == NULL); 1337 #ifdef RTW_DEBUG 1338 if (i == rtw_rxbufs_limit) { 1339 aprint_error_dev(dev, "TEST hit %d-buffer limit\n", i); 1340 rc = ENOBUFS; 1341 break; 1342 } 1343 #endif /* RTW_DEBUG */ 1344 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1345 aprint_error_dev(dev, 1346 "rtw_rxsoft_alloc failed, %d buffers, rc %d\n", 1347 i, rc); 1348 break; 1349 } 1350 } 1351 *ndesc = i; 1352 return rc; 1353 } 1354 1355 static inline void 1356 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1357 int idx, int kick) 1358 { 1359 int is_last = (idx == rdb->rdb_ndesc - 1); 1360 uint32_t ctl, octl, obuf; 1361 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1362 1363 /* sync the mbuf before the descriptor */ 1364 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1365 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1366 1367 obuf = rd->rd_buf; 1368 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1369 1370 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1371 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1372 1373 if (is_last) 1374 ctl |= RTW_RXCTL_EOR; 1375 1376 octl = rd->rd_ctl; 1377 rd->rd_ctl = htole32(ctl); 1378 1379 #ifdef RTW_DEBUG 1380 RTW_DPRINTF( 1381 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1382 : RTW_DEBUG_RECV_DESC, 1383 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1384 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1385 le32toh(rd->rd_ctl))); 1386 #else 1387 __USE(octl); 1388 __USE(obuf); 1389 #endif 1390 1391 /* sync the descriptor */ 1392 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1393 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1394 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1395 } 1396 1397 static void 1398 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1399 { 1400 int i; 1401 struct rtw_rxsoft *rs; 1402 1403 for (i = 0; i < rdb->rdb_ndesc; i++) { 1404 rs = &ctl[i]; 1405 rtw_rxdesc_init(rdb, rs, i, kick); 1406 } 1407 } 1408 1409 static void 1410 rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable) 1411 { 1412 struct rtw_regs *regs = &sc->sc_regs; 1413 uint8_t cr; 1414 1415 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1416 enable ? "enable" : "disable", flags)); 1417 1418 cr = RTW_READ8(regs, RTW_CR); 1419 1420 /* XXX reference source does not enable MULRW */ 1421 /* enable PCI Read/Write Multiple */ 1422 cr |= RTW_CR_MULRW; 1423 1424 /* The receive engine will always start at RDSAR. */ 1425 if (enable && (flags & ~cr & RTW_CR_RE)) { 1426 struct rtw_rxdesc_blk *rdb; 1427 rdb = &sc->sc_rxdesc_blk; 1428 rdb->rdb_next = 0; 1429 } 1430 1431 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1432 if (enable) 1433 cr |= flags; 1434 else 1435 cr &= ~flags; 1436 RTW_WRITE8(regs, RTW_CR, cr); 1437 RTW_SYNC(regs, RTW_CR, RTW_CR); 1438 1439 #ifdef RTW_DIAG 1440 if (cr & RTW_CR_TE) 1441 rtw_txring_fixup(sc, __func__, __LINE__); 1442 #endif 1443 if (cr & RTW_CR_TE) { 1444 rtw_tx_kick(&sc->sc_regs, 1445 RTW_TPPOLL_HPQ | RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ); 1446 } 1447 } 1448 1449 static void 1450 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1451 { 1452 #define IS_BEACON(__fc0) \ 1453 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1454 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1455 1456 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1457 * hardware -> net80211 1458 */ 1459 u_int next, nproc = 0; 1460 int hwrate, len, rate, rssi, sq, s; 1461 uint32_t hrssi, hstat, htsfth, htsftl; 1462 struct rtw_rxdesc *rd; 1463 struct rtw_rxsoft *rs; 1464 struct rtw_rxdesc_blk *rdb; 1465 struct mbuf *m; 1466 struct ifnet *ifp = &sc->sc_if; 1467 1468 struct ieee80211_node *ni; 1469 struct ieee80211_frame_min *wh; 1470 1471 rdb = &sc->sc_rxdesc_blk; 1472 1473 for (next = rdb->rdb_next; ; next = rdb->rdb_next) { 1474 KASSERT(next < rdb->rdb_ndesc); 1475 1476 rtw_rxdescs_sync(rdb, next, 1, 1477 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1478 rd = &rdb->rdb_desc[next]; 1479 rs = &sc->sc_rxsoft[next]; 1480 1481 hstat = le32toh(rd->rd_stat); 1482 hrssi = le32toh(rd->rd_rssi); 1483 htsfth = le32toh(rd->rd_tsfth); 1484 htsftl = le32toh(rd->rd_tsftl); 1485 1486 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1487 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1488 __func__, next, hstat, hrssi, htsfth, htsftl)); 1489 1490 ++nproc; 1491 1492 /* still belongs to NIC */ 1493 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1494 rtw_rxdescs_sync(rdb, next, 1, BUS_DMASYNC_PREREAD); 1495 break; 1496 } 1497 1498 /* ieee80211_input() might reset the receive engine 1499 * (e.g. by indirectly calling rtw_tune()), so save 1500 * the next pointer here and retrieve it again on 1501 * the next round. 1502 */ 1503 rdb->rdb_next = (next + 1) % rdb->rdb_ndesc; 1504 1505 #ifdef RTW_DEBUG 1506 #define PRINTSTAT(flag) do { \ 1507 if ((hstat & flag) != 0) { \ 1508 printf("%s" #flag, delim); \ 1509 delim = ","; \ 1510 } \ 1511 } while (0) 1512 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1513 const char *delim = "<"; 1514 printf("%s: ", device_xname(sc->sc_dev)); 1515 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1516 printf("status %08x", hstat); 1517 PRINTSTAT(RTW_RXSTAT_SPLCP); 1518 PRINTSTAT(RTW_RXSTAT_MAR); 1519 PRINTSTAT(RTW_RXSTAT_PAR); 1520 PRINTSTAT(RTW_RXSTAT_BAR); 1521 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1522 PRINTSTAT(RTW_RXSTAT_CRC32); 1523 PRINTSTAT(RTW_RXSTAT_ICV); 1524 printf(">, "); 1525 } 1526 } 1527 #endif /* RTW_DEBUG */ 1528 1529 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1530 aprint_error_dev(sc->sc_dev, 1531 "DMA error/FIFO overflow %08" PRIx32 ", " 1532 "rx descriptor %d\n", hstat, next); 1533 if_statinc(ifp, if_ierrors); 1534 goto next; 1535 } 1536 1537 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); 1538 if (len < IEEE80211_MIN_LEN) { 1539 sc->sc_ic.ic_stats.is_rx_tooshort++; 1540 goto next; 1541 } 1542 if (len > rs->rs_mbuf->m_len) { 1543 aprint_error_dev(sc->sc_dev, 1544 "rx frame too long, %d > %d, %08" PRIx32 1545 ", desc %d\n", 1546 len, rs->rs_mbuf->m_len, hstat, next); 1547 if_statinc(ifp, if_ierrors); 1548 goto next; 1549 } 1550 1551 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); 1552 if (hwrate >= __arraycount(ratetbl)) { 1553 aprint_error_dev(sc->sc_dev, 1554 "unknown rate #%" __PRIuBITS "\n", 1555 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); 1556 if_statinc(ifp, if_ierrors); 1557 goto next; 1558 } 1559 rate = ratetbl[hwrate]; 1560 1561 #ifdef RTW_DEBUG 1562 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1563 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1564 (rate * 5) % 10, htsfth, htsftl)); 1565 #endif /* RTW_DEBUG */ 1566 1567 /* if bad flags, skip descriptor */ 1568 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1569 aprint_error_dev(sc->sc_dev, "too many rx segments, " 1570 "next=%d, %08" PRIx32 "\n", next, hstat); 1571 goto next; 1572 } 1573 1574 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1575 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1576 1577 m = rs->rs_mbuf; 1578 1579 /* if temporarily out of memory, re-use mbuf */ 1580 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1581 case 0: 1582 break; 1583 case ENOBUFS: 1584 aprint_error_dev(sc->sc_dev, 1585 "rtw_rxsoft_alloc(, %d) failed, dropping packet\n", 1586 next); 1587 goto next; 1588 default: 1589 /* XXX shorten rx ring, instead? */ 1590 aprint_error_dev(sc->sc_dev, 1591 "could not load DMA map\n"); 1592 } 1593 1594 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ); 1595 1596 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1597 rssi = UINT8_MAX - sq; 1598 else { 1599 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); 1600 /* TBD find out each front-end's LNA gain in the 1601 * front-end's units 1602 */ 1603 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1604 rssi |= 0x80; 1605 } 1606 1607 /* Note well: now we cannot recycle the rs_mbuf unless 1608 * we restore its original length. 1609 */ 1610 m_set_rcvif(m, ifp); 1611 m->m_pkthdr.len = m->m_len = len; 1612 1613 wh = mtod(m, struct ieee80211_frame_min *); 1614 1615 s = splnet(); 1616 1617 if (!IS_BEACON(wh->i_fc[0])) 1618 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1619 1620 sc->sc_tsfth = htsfth; 1621 1622 #ifdef RTW_DEBUG 1623 if ((ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) == 1624 (IFF_DEBUG | IFF_LINK2)) { 1625 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1626 rate, rssi); 1627 } 1628 #endif /* RTW_DEBUG */ 1629 1630 if (sc->sc_radiobpf != NULL) { 1631 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1632 1633 rr->rr_tsft = 1634 htole64(((uint64_t)htsfth << 32) | htsftl); 1635 1636 rr->rr_flags = IEEE80211_RADIOTAP_F_FCS; 1637 1638 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1639 rr->rr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1640 if ((hstat & RTW_RXSTAT_CRC32) != 0) 1641 rr->rr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 1642 1643 rr->rr_rate = rate; 1644 1645 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1646 rr->rr_u.u_philips.p_antsignal = rssi; 1647 else { 1648 rr->rr_u.u_other.o_antsignal = rssi; 1649 rr->rr_u.u_other.o_barker_lock = 1650 htole16(UINT8_MAX - sq); 1651 } 1652 1653 bpf_mtap2(sc->sc_radiobpf, 1654 rr, sizeof(sc->sc_rxtapu), m, BPF_D_IN); 1655 } 1656 1657 if ((hstat & RTW_RXSTAT_RES) != 0) { 1658 m_freem(m); 1659 splx(s); 1660 goto next; 1661 } 1662 1663 /* CRC is included with the packet; trim it off. */ 1664 m_adj(m, -IEEE80211_CRC_LEN); 1665 1666 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1667 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1668 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1669 ieee80211_free_node(ni); 1670 splx(s); 1671 next: 1672 rtw_rxdesc_init(rdb, rs, next, 0); 1673 } 1674 #undef IS_BEACON 1675 } 1676 1677 static void 1678 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1679 struct rtw_txsoft *ts) 1680 { 1681 struct mbuf *m; 1682 struct ieee80211_node *ni; 1683 1684 m = ts->ts_mbuf; 1685 ni = ts->ts_ni; 1686 KASSERT(m != NULL); 1687 KASSERT(ni != NULL); 1688 ts->ts_mbuf = NULL; 1689 ts->ts_ni = NULL; 1690 1691 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1692 BUS_DMASYNC_POSTWRITE); 1693 bus_dmamap_unload(dmat, ts->ts_dmamap); 1694 m_freem(m); 1695 ieee80211_free_node(ni); 1696 } 1697 1698 static void 1699 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1700 struct rtw_txsoft_blk *tsb) 1701 { 1702 struct rtw_txsoft *ts; 1703 1704 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1705 rtw_txsoft_release(dmat, ic, ts); 1706 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1707 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1708 } 1709 tsb->tsb_tx_timer = 0; 1710 } 1711 1712 static inline void 1713 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1714 struct rtw_txsoft *ts, int ndesc) 1715 { 1716 uint32_t hstat; 1717 int data_retry, rts_retry; 1718 struct rtw_txdesc *tdn; 1719 const char *condstring; 1720 struct ifnet *ifp = &sc->sc_if; 1721 1722 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1723 1724 tdb->tdb_nfree += ndesc; 1725 1726 tdn = &tdb->tdb_desc[ts->ts_last]; 1727 1728 hstat = le32toh(tdn->td_stat); 1729 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1730 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); 1731 1732 if (rts_retry + data_retry) 1733 if_statadd(ifp, if_collisions, rts_retry + data_retry); 1734 1735 if ((hstat & RTW_TXSTAT_TOK) != 0) 1736 condstring = "ok"; 1737 else { 1738 if_statinc(ifp, if_oerrors); 1739 condstring = "error"; 1740 } 1741 1742 #ifdef RTW_DEBUG 1743 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1744 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1745 device_xname(sc->sc_dev), ts, ts->ts_first, ts->ts_last, 1746 condstring, rts_retry, data_retry)); 1747 #else 1748 __USE(condstring); 1749 #endif 1750 } 1751 1752 static void 1753 rtw_reset_oactive(struct rtw_softc *sc) 1754 { 1755 short oflags; 1756 int pri; 1757 struct rtw_txsoft_blk *tsb; 1758 struct rtw_txdesc_blk *tdb; 1759 oflags = sc->sc_if.if_flags; 1760 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1761 tsb = &sc->sc_txsoft_blk[pri]; 1762 tdb = &sc->sc_txdesc_blk[pri]; 1763 if (!SIMPLEQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0) 1764 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1765 } 1766 if (oflags != sc->sc_if.if_flags) { 1767 DPRINTF(sc, RTW_DEBUG_OACTIVE, 1768 ("%s: reset OACTIVE\n", __func__)); 1769 } 1770 } 1771 1772 /* Collect transmitted packets. */ 1773 static bool 1774 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1775 struct rtw_txdesc_blk *tdb, int force) 1776 { 1777 bool collected = false; 1778 int ndesc; 1779 struct rtw_txsoft *ts; 1780 1781 #ifdef RTW_DEBUG 1782 rtw_dump_rings(sc); 1783 #endif 1784 1785 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1786 /* If we're clearing a failed transmission, only clear 1787 up to the last packet the hardware has processed. */ 1788 if (ts->ts_first == rtw_txring_next(&sc->sc_regs, tdb)) 1789 break; 1790 1791 ndesc = 1 + ts->ts_last - ts->ts_first; 1792 if (ts->ts_last < ts->ts_first) 1793 ndesc += tdb->tdb_ndesc; 1794 1795 KASSERT(ndesc > 0); 1796 1797 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1798 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1799 1800 if (force) { 1801 int next; 1802 #ifdef RTW_DIAG 1803 printf("%s: clearing packet, stats", __func__); 1804 #endif 1805 for (next = ts->ts_first; ; 1806 next = RTW_NEXT_IDX(tdb, next)) { 1807 #ifdef RTW_DIAG 1808 printf(" %" PRIx32 "/%" PRIx32 "/%" PRIx32 "/%" PRIu32 "/%" PRIx32, le32toh(tdb->tdb_desc[next].td_stat), le32toh(tdb->tdb_desc[next].td_ctl1), le32toh(tdb->tdb_desc[next].td_buf), le32toh(tdb->tdb_desc[next].td_len), le32toh(tdb->tdb_desc[next].td_next)); 1809 #endif 1810 tdb->tdb_desc[next].td_stat &= 1811 ~htole32(RTW_TXSTAT_OWN); 1812 if (next == ts->ts_last) 1813 break; 1814 } 1815 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1816 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1817 #ifdef RTW_DIAG 1818 next = RTW_NEXT_IDX(tdb, next); 1819 printf(" -> end %u stat %" PRIx32 ", was %u\n", next, 1820 le32toh(tdb->tdb_desc[next].td_stat), 1821 rtw_txring_next(&sc->sc_regs, tdb)); 1822 #endif 1823 } else if ((tdb->tdb_desc[ts->ts_last].td_stat & 1824 htole32(RTW_TXSTAT_OWN)) != 0) { 1825 rtw_txdescs_sync(tdb, ts->ts_last, 1, 1826 BUS_DMASYNC_PREREAD); 1827 break; 1828 } 1829 1830 collected = true; 1831 1832 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1833 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1834 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1835 } 1836 1837 /* no more pending transmissions, cancel watchdog */ 1838 if (ts == NULL) 1839 tsb->tsb_tx_timer = 0; 1840 rtw_reset_oactive(sc); 1841 1842 return collected; 1843 } 1844 1845 static void 1846 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1847 { 1848 int pri, s; 1849 struct rtw_txsoft_blk *tsb; 1850 struct rtw_txdesc_blk *tdb; 1851 struct ifnet *ifp = &sc->sc_if; 1852 1853 s = splnet(); 1854 1855 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1856 tsb = &sc->sc_txsoft_blk[pri]; 1857 tdb = &sc->sc_txdesc_blk[pri]; 1858 rtw_collect_txring(sc, tsb, tdb, 0); 1859 } 1860 1861 if ((isr & RTW_INTR_TX) != 0) 1862 rtw_start(ifp); /* in softint */ 1863 1864 splx(s); 1865 } 1866 1867 static void 1868 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1869 { 1870 u_int next; 1871 uint32_t tsfth, tsftl; 1872 struct ieee80211com *ic; 1873 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN]; 1874 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN]; 1875 struct mbuf *m; 1876 int s; 1877 1878 s = splnet(); 1879 1880 tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH); 1881 tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1882 1883 if ((isr & (RTW_INTR_TBDOK | RTW_INTR_TBDER)) != 0) { 1884 next = rtw_txring_next(&sc->sc_regs, tdb); 1885 #ifdef RTW_DEBUG 1886 RTW_DPRINTF(RTW_DEBUG_BEACON, 1887 ("%s: beacon ring %sprocessed, isr = %#04" PRIx16 1888 ", next %u expected %u, %" PRIu64 "\n", __func__, 1889 (next == tdb->tdb_next) ? "" : "un", isr, next, 1890 tdb->tdb_next, (uint64_t)tsfth << 32 | tsftl)); 1891 #else 1892 __USE(next); 1893 __USE(tsfth); 1894 __USE(tsftl); 1895 #endif 1896 if ((RTW_READ8(&sc->sc_regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0) 1897 rtw_collect_txring(sc, tsb, tdb, 1); 1898 } 1899 /* Start beacon transmission. */ 1900 1901 if ((isr & RTW_INTR_BCNINT) != 0 && 1902 sc->sc_ic.ic_state == IEEE80211_S_RUN && 1903 SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) { 1904 RTW_DPRINTF(RTW_DEBUG_BEACON, 1905 ("%s: beacon prep. time, isr = %#04" PRIx16 1906 ", %16" PRIu64 "\n", __func__, isr, 1907 (uint64_t)tsfth << 32 | tsftl)); 1908 ic = &sc->sc_ic; 1909 m = rtw_beacon_alloc(sc, ic->ic_bss); 1910 1911 if (m == NULL) { 1912 aprint_error_dev(sc->sc_dev, 1913 "could not allocate beacon\n"); 1914 splx(s); 1915 return; 1916 } 1917 M_SETCTX(m, ieee80211_ref_node(ic->ic_bss)); 1918 IF_ENQUEUE(&sc->sc_beaconq, m); 1919 rtw_start(&sc->sc_if); /* in softint */ 1920 } 1921 1922 splx(s); 1923 } 1924 1925 static void 1926 rtw_intr_atim(struct rtw_softc *sc) 1927 { 1928 /* TBD */ 1929 return; 1930 } 1931 1932 #ifdef RTW_DEBUG 1933 static void 1934 rtw_dump_rings(struct rtw_softc *sc) 1935 { 1936 struct rtw_txdesc_blk *tdb; 1937 struct rtw_rxdesc *rd; 1938 struct rtw_rxdesc_blk *rdb; 1939 int desc, pri; 1940 1941 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1942 return; 1943 1944 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1945 tdb = &sc->sc_txdesc_blk[pri]; 1946 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1947 tdb->tdb_ndesc, tdb->tdb_nfree); 1948 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1949 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1950 } 1951 1952 rdb = &sc->sc_rxdesc_blk; 1953 1954 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1955 rd = &rdb->rdb_desc[desc]; 1956 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1957 "rsvd1/tsfth %08x\n", __func__, 1958 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1959 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1960 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1961 } 1962 } 1963 #endif /* RTW_DEBUG */ 1964 1965 static void 1966 rtw_hwring_setup(struct rtw_softc *sc) 1967 { 1968 int pri; 1969 struct rtw_regs *regs = &sc->sc_regs; 1970 struct rtw_txdesc_blk *tdb; 1971 1972 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_basereg = RTW_TLPDA; 1973 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_base = RTW_RING_BASE(sc, hd_txlo); 1974 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_basereg = RTW_TNPDA; 1975 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_base = RTW_RING_BASE(sc, hd_txmd); 1976 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_basereg = RTW_THPDA; 1977 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_base = RTW_RING_BASE(sc, hd_txhi); 1978 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_basereg = RTW_TBDA; 1979 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_base = RTW_RING_BASE(sc, hd_bcn); 1980 1981 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1982 tdb = &sc->sc_txdesc_blk[pri]; 1983 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base); 1984 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1985 ("%s: reg[tdb->tdb_basereg] <- %" PRIxPTR "\n", __func__, 1986 (uintptr_t)tdb->tdb_base)); 1987 } 1988 1989 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1990 1991 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1992 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1993 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1994 1995 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1996 1997 } 1998 1999 static int 2000 rtw_swring_setup(struct rtw_softc *sc) 2001 { 2002 int rc; 2003 struct rtw_rxdesc_blk *rdb; 2004 2005 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 2006 2007 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 2008 2009 rdb = &sc->sc_rxdesc_blk; 2010 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 2011 sc->sc_dev)) != 0 && rdb->rdb_ndesc == 0) { 2012 aprint_error_dev(sc->sc_dev, "could not allocate rx buffers\n"); 2013 return rc; 2014 } 2015 2016 rdb = &sc->sc_rxdesc_blk; 2017 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 2018 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2019 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 2020 rdb->rdb_next = 0; 2021 2022 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 2023 return 0; 2024 } 2025 2026 static void 2027 rtw_txdesc_blk_init(struct rtw_txdesc_blk *tdb) 2028 { 2029 int i; 2030 2031 (void)memset(tdb->tdb_desc, 0, 2032 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 2033 for (i = 0; i < tdb->tdb_ndesc; i++) 2034 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 2035 } 2036 2037 static u_int 2038 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb) 2039 { 2040 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) / 2041 sizeof(struct rtw_txdesc); 2042 } 2043 2044 #ifdef RTW_DIAG 2045 static void 2046 rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln) 2047 { 2048 int pri; 2049 u_int next; 2050 struct rtw_txdesc_blk *tdb; 2051 struct rtw_regs *regs = &sc->sc_regs; 2052 2053 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2054 int i; 2055 tdb = &sc->sc_txdesc_blk[pri]; 2056 next = rtw_txring_next(regs, tdb); 2057 if (tdb->tdb_next == next) 2058 continue; 2059 for (i = 0; next != tdb->tdb_next; 2060 next = RTW_NEXT_IDX(tdb, next), i++) { 2061 if ((tdb->tdb_desc[next].td_stat & htole32(RTW_TXSTAT_OWN)) == 0) 2062 break; 2063 } 2064 printf("%s:%d: tx-ring %d expected next %u, read %u+%d -> %s\n", fn, 2065 ln, pri, tdb->tdb_next, next, i, tdb->tdb_next == next ? "okay" : "BAD"); 2066 if (tdb->tdb_next == next) 2067 continue; 2068 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1); 2069 } 2070 } 2071 #endif 2072 2073 static void 2074 rtw_txdescs_reset(struct rtw_softc *sc) 2075 { 2076 int pri; 2077 struct rtw_txsoft_blk *tsb; 2078 struct rtw_txdesc_blk *tdb; 2079 2080 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2081 tsb = &sc->sc_txsoft_blk[pri]; 2082 tdb = &sc->sc_txdesc_blk[pri]; 2083 rtw_collect_txring(sc, tsb, tdb, 1); 2084 #ifdef RTW_DIAG 2085 if (!SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 2086 printf("%s: packets left in ring %d\n", __func__, pri); 2087 #endif 2088 } 2089 } 2090 2091 static void 2092 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 2093 { 2094 int s; 2095 2096 aprint_error_dev(sc->sc_dev, "tx fifo underflow\n"); 2097 2098 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: cleaning up xmit, isr %" PRIx16 2099 "\n", device_xname(sc->sc_dev), isr)); 2100 2101 s = splnet(); 2102 2103 #ifdef RTW_DEBUG 2104 rtw_dump_rings(sc); 2105 #endif /* RTW_DEBUG */ 2106 2107 /* Collect tx'd packets. XXX let's hope this stops the transmit 2108 * timeouts. 2109 */ 2110 rtw_txdescs_reset(sc); 2111 2112 #ifdef RTW_DEBUG 2113 rtw_dump_rings(sc); 2114 #endif /* RTW_DEBUG */ 2115 2116 splx(s); 2117 } 2118 2119 static inline void 2120 rtw_suspend_ticks(struct rtw_softc *sc) 2121 { 2122 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2123 ("%s: suspending ticks\n", device_xname(sc->sc_dev))); 2124 sc->sc_do_tick = 0; 2125 } 2126 2127 static inline void 2128 rtw_resume_ticks(struct rtw_softc *sc) 2129 { 2130 uint32_t tsftrl0, tsftrl1, next_tint; 2131 2132 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2133 2134 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2135 next_tint = tsftrl1 + 1000000; 2136 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tint); 2137 2138 sc->sc_do_tick = 1; 2139 2140 #ifdef RTW_DEBUG 2141 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2142 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 2143 device_xname(sc->sc_dev), tsftrl1 - tsftrl0, tsftrl1, next_tint)); 2144 #else 2145 __USE(tsftrl0); 2146 #endif 2147 } 2148 2149 static void 2150 rtw_intr_timeout(struct rtw_softc *sc) 2151 { 2152 int s; 2153 2154 s = splnet(); 2155 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", device_xname(sc->sc_dev))); 2156 if (sc->sc_do_tick) 2157 rtw_resume_ticks(sc); 2158 splx(s); 2159 } 2160 2161 int 2162 rtw_intr(void *arg) 2163 { 2164 struct rtw_softc *sc = arg; 2165 struct rtw_regs *regs = &sc->sc_regs; 2166 uint16_t isr; 2167 struct ifnet *ifp = &sc->sc_if; 2168 2169 /* 2170 * If the interface isn't running, the interrupt couldn't 2171 * possibly have come from us. 2172 */ 2173 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2174 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) { 2175 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", 2176 device_xname(sc->sc_dev))); 2177 return (0); 2178 } 2179 2180 isr = RTW_READ16(regs, RTW_ISR); 2181 if (isr == 0) 2182 return (0); 2183 2184 /* Disable interrupts. */ 2185 RTW_WRITE16(regs, RTW_IMR, 0); 2186 RTW_WBW(regs, RTW_IMR, RTW_IMR); 2187 2188 softint_schedule(sc->sc_soft_ih); 2189 return (1); 2190 } 2191 2192 static void 2193 rtw_softintr(void *arg) 2194 { 2195 int i; 2196 struct rtw_softc *sc = arg; 2197 struct rtw_regs *regs = &sc->sc_regs; 2198 uint16_t isr; 2199 struct ifnet *ifp = &sc->sc_if; 2200 2201 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2202 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) { 2203 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", 2204 device_xname(sc->sc_dev))); 2205 return; 2206 } 2207 2208 for (i = 0; i < 10; i++) { 2209 isr = RTW_READ16(regs, RTW_ISR); 2210 2211 RTW_WRITE16(regs, RTW_ISR, isr); 2212 RTW_WBR(regs, RTW_ISR, RTW_ISR); 2213 2214 if (sc->sc_intr_ack != NULL) 2215 (*sc->sc_intr_ack)(regs); 2216 2217 if (isr == 0) 2218 break; 2219 2220 #ifdef RTW_DEBUG 2221 #define PRINTINTR(flag) do { \ 2222 if ((isr & flag) != 0) { \ 2223 printf("%s" #flag, delim); \ 2224 delim = ","; \ 2225 } \ 2226 } while (0) 2227 2228 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 2229 const char *delim = "<"; 2230 2231 printf("%s: reg[ISR] = %x", device_xname(sc->sc_dev), 2232 isr); 2233 2234 PRINTINTR(RTW_INTR_TXFOVW); 2235 PRINTINTR(RTW_INTR_TIMEOUT); 2236 PRINTINTR(RTW_INTR_BCNINT); 2237 PRINTINTR(RTW_INTR_ATIMINT); 2238 PRINTINTR(RTW_INTR_TBDER); 2239 PRINTINTR(RTW_INTR_TBDOK); 2240 PRINTINTR(RTW_INTR_THPDER); 2241 PRINTINTR(RTW_INTR_THPDOK); 2242 PRINTINTR(RTW_INTR_TNPDER); 2243 PRINTINTR(RTW_INTR_TNPDOK); 2244 PRINTINTR(RTW_INTR_RXFOVW); 2245 PRINTINTR(RTW_INTR_RDU); 2246 PRINTINTR(RTW_INTR_TLPDER); 2247 PRINTINTR(RTW_INTR_TLPDOK); 2248 PRINTINTR(RTW_INTR_RER); 2249 PRINTINTR(RTW_INTR_ROK); 2250 2251 printf(">\n"); 2252 } 2253 #undef PRINTINTR 2254 #endif /* RTW_DEBUG */ 2255 2256 if ((isr & RTW_INTR_RX) != 0) 2257 rtw_intr_rx(sc, isr); 2258 if ((isr & RTW_INTR_TX) != 0) 2259 rtw_intr_tx(sc, isr); 2260 if ((isr & RTW_INTR_BEACON) != 0) 2261 rtw_intr_beacon(sc, isr); 2262 if ((isr & RTW_INTR_ATIMINT) != 0) 2263 rtw_intr_atim(sc); 2264 if ((isr & RTW_INTR_IOERROR) != 0) 2265 rtw_intr_ioerror(sc, isr); 2266 if ((isr & RTW_INTR_TIMEOUT) != 0) 2267 rtw_intr_timeout(sc); 2268 } 2269 if (i == 10) 2270 softint_schedule(sc->sc_soft_ih); 2271 2272 /* Re-enable interrupts */ 2273 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2274 RTW_WBW(regs, RTW_IMR, RTW_IMR); 2275 } 2276 2277 /* Must be called at splnet. */ 2278 static void 2279 rtw_stop(struct ifnet *ifp, int disable) 2280 { 2281 int pri; 2282 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2283 struct ieee80211com *ic = &sc->sc_ic; 2284 struct rtw_regs *regs = &sc->sc_regs; 2285 2286 rtw_suspend_ticks(sc); 2287 2288 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2289 2290 if (device_has_power(sc->sc_dev)) { 2291 /* Disable interrupts. */ 2292 RTW_WRITE16(regs, RTW_IMR, 0); 2293 2294 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2295 2296 /* Stop the transmit and receive processes. First stop DMA, 2297 * then disable receiver and transmitter. 2298 */ 2299 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2300 2301 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2302 2303 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2304 } 2305 2306 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2307 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2308 &sc->sc_txsoft_blk[pri]); 2309 } 2310 2311 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2312 2313 /* Mark the interface as not running. Cancel the watchdog timer. */ 2314 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2315 ifp->if_timer = 0; 2316 2317 if (disable) 2318 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 2319 2320 return; 2321 } 2322 2323 const char * 2324 rtw_pwrstate_string(enum rtw_pwrstate power) 2325 { 2326 switch (power) { 2327 case RTW_ON: 2328 return "on"; 2329 case RTW_SLEEP: 2330 return "sleep"; 2331 case RTW_OFF: 2332 return "off"; 2333 default: 2334 return "unknown"; 2335 } 2336 } 2337 2338 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2339 * reference driver, plus a magic Maxim "ON" value that comes from 2340 * the Realtek document "Windows PG for Rtl8180." 2341 */ 2342 static void 2343 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2344 int before_rf, int digphy) 2345 { 2346 uint32_t anaparm; 2347 2348 anaparm = RTW_READ(regs, RTW_ANAPARM); 2349 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2350 2351 switch (power) { 2352 case RTW_OFF: 2353 if (before_rf) 2354 return; 2355 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2356 anaparm |= RTW_ANAPARM_TXDACOFF; 2357 break; 2358 case RTW_SLEEP: 2359 if (!before_rf) 2360 return; 2361 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2362 anaparm |= RTW_ANAPARM_TXDACOFF; 2363 break; 2364 case RTW_ON: 2365 if (!before_rf) 2366 return; 2367 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2368 break; 2369 } 2370 RTW_DPRINTF(RTW_DEBUG_PWR, 2371 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2372 __func__, rtw_pwrstate_string(power), 2373 (before_rf) ? "before" : "after", anaparm)); 2374 2375 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2376 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2377 } 2378 2379 /* XXX I am using the RFMD settings gleaned from the reference 2380 * driver. They agree 2381 */ 2382 static void 2383 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2384 int before_rf, int digphy) 2385 { 2386 uint32_t anaparm; 2387 2388 anaparm = RTW_READ(regs, RTW_ANAPARM); 2389 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2390 2391 switch (power) { 2392 case RTW_OFF: 2393 if (before_rf) 2394 return; 2395 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2396 anaparm |= RTW_ANAPARM_TXDACOFF; 2397 break; 2398 case RTW_SLEEP: 2399 if (!before_rf) 2400 return; 2401 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2402 anaparm |= RTW_ANAPARM_TXDACOFF; 2403 break; 2404 case RTW_ON: 2405 if (!before_rf) 2406 return; 2407 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2408 break; 2409 } 2410 RTW_DPRINTF(RTW_DEBUG_PWR, 2411 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2412 __func__, rtw_pwrstate_string(power), 2413 (before_rf) ? "before" : "after", anaparm)); 2414 2415 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2416 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2417 } 2418 2419 static void 2420 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2421 int before_rf, int digphy) 2422 { 2423 uint32_t anaparm; 2424 2425 anaparm = RTW_READ(regs, RTW_ANAPARM); 2426 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2427 2428 switch (power) { 2429 case RTW_OFF: 2430 if (before_rf) 2431 return; 2432 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2433 anaparm |= RTW_ANAPARM_TXDACOFF; 2434 break; 2435 case RTW_SLEEP: 2436 if (!before_rf) 2437 return; 2438 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2439 anaparm |= RTW_ANAPARM_TXDACOFF; 2440 break; 2441 case RTW_ON: 2442 if (!before_rf) 2443 return; 2444 if (digphy) { 2445 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2446 /* XXX guess */ 2447 anaparm |= RTW_ANAPARM_TXDACOFF; 2448 } else 2449 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2450 break; 2451 } 2452 RTW_DPRINTF(RTW_DEBUG_PWR, 2453 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2454 __func__, rtw_pwrstate_string(power), 2455 (before_rf) ? "before" : "after", anaparm)); 2456 2457 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2458 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2459 } 2460 2461 static void 2462 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2463 int digphy) 2464 { 2465 struct rtw_regs *regs = &sc->sc_regs; 2466 2467 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2468 2469 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2470 2471 rtw_set_access(regs, RTW_ACCESS_NONE); 2472 2473 return; 2474 } 2475 2476 static int 2477 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2478 { 2479 int rc; 2480 2481 RTW_DPRINTF(RTW_DEBUG_PWR, 2482 ("%s: %s->%s\n", __func__, 2483 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2484 2485 if (sc->sc_pwrstate == power) 2486 return 0; 2487 2488 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2489 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2490 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2491 2492 switch (power) { 2493 case RTW_ON: 2494 /* TBD set LEDs */ 2495 break; 2496 case RTW_SLEEP: 2497 /* TBD */ 2498 break; 2499 case RTW_OFF: 2500 /* TBD */ 2501 break; 2502 } 2503 if (rc == 0) 2504 sc->sc_pwrstate = power; 2505 else 2506 sc->sc_pwrstate = RTW_OFF; 2507 return rc; 2508 } 2509 2510 static int 2511 rtw_tune(struct rtw_softc *sc) 2512 { 2513 struct ieee80211com *ic = &sc->sc_ic; 2514 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 2515 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 2516 u_int chan; 2517 int rc; 2518 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2519 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2520 2521 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2522 KASSERT(chan != IEEE80211_CHAN_ANY); 2523 2524 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2525 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2526 2527 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2528 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2529 2530 if (chan == sc->sc_cur_chan) { 2531 RTW_DPRINTF(RTW_DEBUG_TUNE, 2532 ("%s: already tuned chan #%d\n", __func__, chan)); 2533 return 0; 2534 } 2535 2536 rtw_suspend_ticks(sc); 2537 2538 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2539 2540 /* TBD wait for Tx to complete */ 2541 2542 KASSERT(device_has_power(sc->sc_dev)); 2543 2544 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2545 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr, 2546 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) { 2547 /* XXX condition on powersaving */ 2548 aprint_error_dev(sc->sc_dev, "phy init failed\n"); 2549 } 2550 2551 sc->sc_cur_chan = chan; 2552 2553 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2554 2555 rtw_resume_ticks(sc); 2556 2557 return rc; 2558 } 2559 2560 bool 2561 rtw_suspend(device_t self, const pmf_qual_t *qual) 2562 { 2563 int rc; 2564 struct rtw_softc *sc = device_private(self); 2565 2566 sc->sc_flags &= ~RTW_F_DK_VALID; 2567 2568 if (!device_has_power(self)) 2569 return false; 2570 2571 /* turn off PHY */ 2572 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2573 aprint_error_dev(self, "failed to turn off PHY (%d)\n", rc); 2574 return false; 2575 } 2576 2577 rtw_disable_interrupts(&sc->sc_regs); 2578 2579 return true; 2580 } 2581 2582 bool 2583 rtw_resume(device_t self, const pmf_qual_t *qual) 2584 { 2585 struct rtw_softc *sc = device_private(self); 2586 2587 /* Power may have been removed, resetting WEP keys. 2588 */ 2589 sc->sc_flags &= ~RTW_F_DK_VALID; 2590 rtw_enable_interrupts(sc); 2591 2592 return true; 2593 } 2594 2595 static void 2596 rtw_transmit_config(struct rtw_regs *regs) 2597 { 2598 uint32_t tcr; 2599 2600 tcr = RTW_READ(regs, RTW_TCR); 2601 2602 tcr |= RTW_TCR_CWMIN; 2603 tcr &= ~RTW_TCR_MXDMA_MASK; 2604 tcr |= RTW_TCR_MXDMA_256; 2605 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2606 tcr &= ~RTW_TCR_LBK_MASK; 2607 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2608 2609 /* set short/long retry limits */ 2610 tcr &= ~(RTW_TCR_SRL_MASK | RTW_TCR_LRL_MASK); 2611 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK); 2612 2613 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2614 2615 RTW_WRITE(regs, RTW_TCR, tcr); 2616 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2617 } 2618 2619 static void 2620 rtw_disable_interrupts(struct rtw_regs *regs) 2621 { 2622 RTW_WRITE16(regs, RTW_IMR, 0); 2623 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2624 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2625 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2626 } 2627 2628 static void 2629 rtw_enable_interrupts(struct rtw_softc *sc) 2630 { 2631 struct rtw_regs *regs = &sc->sc_regs; 2632 2633 sc->sc_inten = RTW_INTR_RX | RTW_INTR_TX | RTW_INTR_BEACON 2634 | RTW_INTR_ATIMINT; 2635 sc->sc_inten |= RTW_INTR_IOERROR | RTW_INTR_TIMEOUT; 2636 2637 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2638 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2639 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2640 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2641 2642 /* XXX necessary? */ 2643 if (sc->sc_intr_ack != NULL) 2644 (*sc->sc_intr_ack)(regs); 2645 } 2646 2647 static void 2648 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2649 { 2650 uint8_t msr; 2651 2652 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2653 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2654 2655 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2656 2657 switch (opmode) { 2658 case IEEE80211_M_AHDEMO: 2659 case IEEE80211_M_IBSS: 2660 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2661 break; 2662 case IEEE80211_M_HOSTAP: 2663 msr |= RTW_MSR_NETYPE_AP_OK; 2664 break; 2665 case IEEE80211_M_MONITOR: 2666 /* XXX */ 2667 msr |= RTW_MSR_NETYPE_NOLINK; 2668 break; 2669 case IEEE80211_M_STA: 2670 msr |= RTW_MSR_NETYPE_INFRA_OK; 2671 break; 2672 } 2673 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2674 2675 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2676 } 2677 2678 #define rtw_calchash(addr) \ 2679 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2680 2681 static void 2682 rtw_pktfilt_load(struct rtw_softc *sc) 2683 { 2684 struct rtw_regs *regs = &sc->sc_regs; 2685 struct ieee80211com *ic = &sc->sc_ic; 2686 struct ethercom *ec = &sc->sc_ec; 2687 struct ifnet *ifp = &sc->sc_if; 2688 int hash; 2689 uint32_t hashes[2] = { 0, 0 }; 2690 struct ether_multi *enm; 2691 struct ether_multistep step; 2692 2693 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2694 2695 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2696 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2697 2698 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2699 /* MAC auto-reset PHY (huh?) */ 2700 sc->sc_rcr |= RTW_RCR_ENMARP; 2701 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2702 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2703 2704 switch (ic->ic_opmode) { 2705 case IEEE80211_M_MONITOR: 2706 sc->sc_rcr |= RTW_RCR_MONITOR; 2707 break; 2708 case IEEE80211_M_AHDEMO: 2709 case IEEE80211_M_IBSS: 2710 /* receive broadcasts in our BSS */ 2711 sc->sc_rcr |= RTW_RCR_ADD3; 2712 break; 2713 default: 2714 break; 2715 } 2716 2717 ifp->if_flags &= ~IFF_ALLMULTI; 2718 2719 /* 2720 * Program the 64-bit multicast hash filter. 2721 */ 2722 ETHER_LOCK(ec); 2723 ETHER_FIRST_MULTI(step, ec, enm); 2724 while (enm != NULL) { 2725 /* XXX */ 2726 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2727 ETHER_ADDR_LEN) != 0) { 2728 ifp->if_flags |= IFF_ALLMULTI; 2729 break; 2730 } 2731 2732 hash = rtw_calchash(enm->enm_addrlo); 2733 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2734 ETHER_NEXT_MULTI(step, enm); 2735 } 2736 ETHER_UNLOCK(ec); 2737 2738 /* XXX accept all broadcast if scanning */ 2739 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2740 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2741 2742 if (ifp->if_flags & IFF_PROMISC) { 2743 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2744 sc->sc_rcr |= RTW_RCR_ACRC32; /* accept frames failing CRC */ 2745 sc->sc_rcr |= RTW_RCR_AICV; /* accept frames failing ICV */ 2746 ifp->if_flags |= IFF_ALLMULTI; 2747 } 2748 2749 if (ifp->if_flags & IFF_ALLMULTI) 2750 hashes[0] = hashes[1] = 0xffffffff; 2751 2752 if ((hashes[0] | hashes[1]) != 0) 2753 sc->sc_rcr |= RTW_RCR_AM; /* accept multicast */ 2754 2755 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2756 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2757 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2758 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2759 2760 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2761 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2762 device_xname(sc->sc_dev), RTW_READ(regs, RTW_MAR0), 2763 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2764 } 2765 2766 static struct mbuf * 2767 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2768 { 2769 struct ieee80211com *ic = &sc->sc_ic; 2770 struct mbuf *m; 2771 struct ieee80211_beacon_offsets boff; 2772 2773 if ((m = ieee80211_beacon_alloc(ic, ni, &boff)) != NULL) { 2774 RTW_DPRINTF(RTW_DEBUG_BEACON, 2775 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2776 } 2777 return m; 2778 } 2779 2780 /* Must be called at splnet. */ 2781 static int 2782 rtw_init(struct ifnet *ifp) 2783 { 2784 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2785 struct ieee80211com *ic = &sc->sc_ic; 2786 struct rtw_regs *regs = &sc->sc_regs; 2787 int rc; 2788 2789 if (device_is_active(sc->sc_dev)) { 2790 /* Cancel pending I/O and reset. */ 2791 rtw_stop(ifp, 0); 2792 } else if (!pmf_device_resume(sc->sc_dev, &sc->sc_qual) || 2793 !device_is_active(sc->sc_dev)) 2794 return 0; 2795 2796 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2797 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 2798 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 2799 2800 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2801 goto out; 2802 2803 if ((rc = rtw_swring_setup(sc)) != 0) 2804 goto out; 2805 2806 rtw_transmit_config(regs); 2807 2808 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2809 2810 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2811 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2812 2813 /* long PLCP header, 1Mb/2Mb basic rate */ 2814 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2815 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2816 2817 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2818 rtw_set_access(regs, RTW_ACCESS_NONE); 2819 2820 /* XXX from reference sources */ 2821 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2822 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2823 2824 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev); 2825 2826 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2827 /* from Linux driver */ 2828 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2829 2830 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2831 2832 rtw_enable_interrupts(sc); 2833 2834 rtw_pktfilt_load(sc); 2835 2836 rtw_hwring_setup(sc); 2837 2838 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2839 2840 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2841 2842 ifp->if_flags |= IFF_RUNNING; 2843 ic->ic_state = IEEE80211_S_INIT; 2844 2845 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2846 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2847 2848 rtw_resume_ticks(sc); 2849 2850 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2851 2852 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2853 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2854 else 2855 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2856 2857 out: 2858 aprint_error_dev(sc->sc_dev, "interface not running\n"); 2859 return rc; 2860 } 2861 2862 static inline void 2863 rtw_led_init(struct rtw_regs *regs) 2864 { 2865 uint8_t cfg0, cfg1; 2866 2867 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2868 2869 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2870 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2871 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2872 2873 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2874 RTW_DPRINTF(RTW_DEBUG_LED, 2875 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2876 2877 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2878 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2879 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2880 2881 rtw_set_access(regs, RTW_ACCESS_NONE); 2882 } 2883 2884 /* 2885 * IEEE80211_S_INIT: LED1 off 2886 * 2887 * IEEE80211_S_AUTH, 2888 * IEEE80211_S_ASSOC, 2889 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2890 * 2891 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2892 */ 2893 static void 2894 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2895 { 2896 struct rtw_led_state *ls; 2897 2898 ls = &sc->sc_led_state; 2899 2900 switch (nstate) { 2901 case IEEE80211_S_INIT: 2902 rtw_led_init(&sc->sc_regs); 2903 aprint_debug_dev(sc->sc_dev, "stopping blink\n"); 2904 callout_stop(&ls->ls_slow_ch); 2905 callout_stop(&ls->ls_fast_ch); 2906 ls->ls_slowblink = 0; 2907 ls->ls_actblink = 0; 2908 ls->ls_default = 0; 2909 break; 2910 case IEEE80211_S_SCAN: 2911 aprint_debug_dev(sc->sc_dev, "scheduling blink\n"); 2912 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2913 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2914 /*FALLTHROUGH*/ 2915 case IEEE80211_S_AUTH: 2916 case IEEE80211_S_ASSOC: 2917 ls->ls_default = RTW_LED1; 2918 ls->ls_actblink = RTW_LED1; 2919 ls->ls_slowblink = RTW_LED1; 2920 break; 2921 case IEEE80211_S_RUN: 2922 ls->ls_slowblink = 0; 2923 break; 2924 } 2925 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2926 } 2927 2928 static void 2929 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2930 { 2931 uint8_t led_condition; 2932 bus_size_t ofs; 2933 uint8_t mask, newval, val; 2934 2935 led_condition = ls->ls_default; 2936 2937 if (ls->ls_state & RTW_LED_S_SLOW) 2938 led_condition ^= ls->ls_slowblink; 2939 if (ls->ls_state & (RTW_LED_S_RX | RTW_LED_S_TX)) 2940 led_condition ^= ls->ls_actblink; 2941 2942 RTW_DPRINTF(RTW_DEBUG_LED, 2943 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2944 2945 switch (hwverid) { 2946 default: 2947 case 'F': 2948 ofs = RTW_PSR; 2949 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2950 if (led_condition & RTW_LED0) 2951 newval &= ~RTW_PSR_LEDGPO0; 2952 if (led_condition & RTW_LED1) 2953 newval &= ~RTW_PSR_LEDGPO1; 2954 break; 2955 case 'D': 2956 ofs = RTW_9346CR; 2957 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2958 newval = RTW_9346CR_EEM_PROGRAM; 2959 if (led_condition & RTW_LED0) 2960 newval |= RTW_9346CR_EEDI; 2961 if (led_condition & RTW_LED1) 2962 newval |= RTW_9346CR_EECS; 2963 break; 2964 } 2965 val = RTW_READ8(regs, ofs); 2966 RTW_DPRINTF(RTW_DEBUG_LED, 2967 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2968 (uintptr_t)ofs)); 2969 val &= ~mask; 2970 val |= newval; 2971 RTW_WRITE8(regs, ofs, val); 2972 RTW_DPRINTF(RTW_DEBUG_LED, 2973 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2974 (uintptr_t)ofs)); 2975 RTW_SYNC(regs, ofs, ofs); 2976 } 2977 2978 static void 2979 rtw_led_fastblink(void *arg) 2980 { 2981 int ostate, s; 2982 struct rtw_softc *sc = (struct rtw_softc *)arg; 2983 struct rtw_led_state *ls = &sc->sc_led_state; 2984 2985 s = splnet(); 2986 ostate = ls->ls_state; 2987 ls->ls_state ^= ls->ls_event; 2988 2989 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2990 ls->ls_state &= ~RTW_LED_S_TX; 2991 2992 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2993 ls->ls_state &= ~RTW_LED_S_RX; 2994 2995 ls->ls_event = 0; 2996 2997 if (ostate != ls->ls_state) 2998 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2999 splx(s); 3000 3001 aprint_debug_dev(sc->sc_dev, "scheduling fast blink\n"); 3002 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 3003 } 3004 3005 static void 3006 rtw_led_slowblink(void *arg) 3007 { 3008 int s; 3009 struct rtw_softc *sc = (struct rtw_softc *)arg; 3010 struct rtw_led_state *ls = &sc->sc_led_state; 3011 3012 s = splnet(); 3013 ls->ls_state ^= RTW_LED_S_SLOW; 3014 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 3015 splx(s); 3016 aprint_debug_dev(sc->sc_dev, "scheduling slow blink\n"); 3017 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 3018 } 3019 3020 static void 3021 rtw_led_detach(struct rtw_led_state *ls) 3022 { 3023 callout_destroy(&ls->ls_fast_ch); 3024 callout_destroy(&ls->ls_slow_ch); 3025 } 3026 3027 static void 3028 rtw_led_attach(struct rtw_led_state *ls, void *arg) 3029 { 3030 callout_init(&ls->ls_fast_ch, 0); 3031 callout_init(&ls->ls_slow_ch, 0); 3032 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 3033 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 3034 } 3035 3036 static int 3037 rtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3038 { 3039 int rc = 0, s; 3040 struct rtw_softc *sc = ifp->if_softc; 3041 3042 s = splnet(); 3043 if (cmd == SIOCSIFFLAGS) { 3044 if ((rc = ifioctl_common(ifp, cmd, data)) != 0) 3045 ; 3046 else switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3047 case IFF_UP: 3048 rc = rtw_init(ifp); 3049 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 3050 break; 3051 case IFF_UP | IFF_RUNNING: 3052 if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 3053 rtw_pktfilt_load(sc); 3054 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 3055 break; 3056 case IFF_RUNNING: 3057 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 3058 rtw_stop(ifp, 1); 3059 break; 3060 default: 3061 break; 3062 } 3063 } else if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 3064 ; /* nothing to do */ 3065 else if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 3066 /* reload packet filter if running */ 3067 if (ifp->if_flags & IFF_RUNNING) 3068 rtw_pktfilt_load(sc); 3069 rc = 0; 3070 } else if ((ifp->if_flags & IFF_UP) != 0) 3071 rc = rtw_init(ifp); 3072 else 3073 rc = 0; 3074 splx(s); 3075 return rc; 3076 } 3077 3078 /* Select a transmit ring with at least one h/w and s/w descriptor free. 3079 * Return 0 on success, -1 on failure. 3080 */ 3081 static inline int 3082 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 3083 struct rtw_txdesc_blk **tdbp, int pri) 3084 { 3085 struct rtw_txsoft_blk *tsb; 3086 struct rtw_txdesc_blk *tdb; 3087 3088 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 3089 3090 tsb = &sc->sc_txsoft_blk[pri]; 3091 tdb = &sc->sc_txdesc_blk[pri]; 3092 3093 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 3094 if (tsb->tsb_tx_timer == 0) 3095 tsb->tsb_tx_timer = 5; 3096 *tsbp = NULL; 3097 *tdbp = NULL; 3098 return -1; 3099 } 3100 *tsbp = tsb; 3101 *tdbp = tdb; 3102 return 0; 3103 } 3104 3105 static inline struct mbuf * 3106 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 3107 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 3108 struct ieee80211_node **nip, short *if_flagsp) 3109 { 3110 struct mbuf *m; 3111 3112 if (IF_IS_EMPTY(ifq)) 3113 return NULL; 3114 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3115 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3116 __func__, pri)); 3117 *if_flagsp |= IFF_OACTIVE; 3118 sc->sc_if.if_timer = 1; 3119 return NULL; 3120 } 3121 IF_DEQUEUE(ifq, m); 3122 *nip = M_GETCTX(m, struct ieee80211_node *); 3123 M_SETCTX(m, NULL); 3124 KASSERT(*nip != NULL); 3125 return m; 3126 } 3127 3128 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 3129 * at the driver's selection of transmit control block for the packet. 3130 */ 3131 static inline int 3132 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 3133 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 3134 struct ieee80211_node **nip) 3135 { 3136 int pri; 3137 struct ether_header *eh; 3138 struct mbuf *m0; 3139 struct rtw_softc *sc; 3140 short *if_flagsp; 3141 3142 *mp = NULL; 3143 3144 sc = (struct rtw_softc *)ifp->if_softc; 3145 3146 DPRINTF(sc, RTW_DEBUG_XMIT, 3147 ("%s: enter %s\n", device_xname(sc->sc_dev), __func__)); 3148 3149 if_flagsp = &ifp->if_flags; 3150 3151 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 3152 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 3153 tdbp, nip, if_flagsp)) != NULL) { 3154 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 3155 __func__)); 3156 return 0; 3157 } 3158 3159 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 3160 tdbp, nip, if_flagsp)) != NULL) { 3161 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 3162 __func__)); 3163 return 0; 3164 } 3165 3166 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 3167 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 3168 return 0; 3169 } 3170 3171 IFQ_POLL(&ifp->if_snd, m0); 3172 if (m0 == NULL) { 3173 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3174 __func__)); 3175 return 0; 3176 } 3177 3178 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 3179 3180 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3181 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3182 __func__, pri)); 3183 *if_flagsp |= IFF_OACTIVE; 3184 sc->sc_if.if_timer = 1; 3185 return 0; 3186 } 3187 3188 IFQ_DEQUEUE(&ifp->if_snd, m0); 3189 if (m0 == NULL) { 3190 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3191 __func__)); 3192 return 0; 3193 } 3194 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 3195 if_statinc(ifp, if_opackets); 3196 bpf_mtap(ifp, m0, BPF_D_OUT); 3197 eh = mtod(m0, struct ether_header *); 3198 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 3199 if (*nip == NULL) { 3200 /* NB: ieee80211_find_txnode does stat+msg */ 3201 m_freem(m0); 3202 return -1; 3203 } 3204 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 3205 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 3206 if_statinc(ifp, if_oerrors); 3207 return -1; 3208 } 3209 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3210 *mp = m0; 3211 return 0; 3212 } 3213 3214 static int 3215 rtw_seg_too_short(bus_dmamap_t dmamap) 3216 { 3217 int i; 3218 for (i = 0; i < dmamap->dm_nsegs; i++) { 3219 if (dmamap->dm_segs[i].ds_len < 4) 3220 return 1; 3221 } 3222 return 0; 3223 } 3224 3225 /* TBD factor with atw_start */ 3226 static struct mbuf * 3227 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 3228 u_int ndescfree, device_t dev) 3229 { 3230 int first, rc; 3231 struct mbuf *m, *m0; 3232 3233 m0 = chain; 3234 3235 /* 3236 * Load the DMA map. Copy and try (once) again if the packet 3237 * didn't fit in the alloted number of segments. 3238 */ 3239 for (first = 1; 3240 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 3241 BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0 || 3242 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 3243 first = 0) { 3244 if (rc == 0) { 3245 #ifdef RTW_DIAGxxx 3246 if (rtw_seg_too_short(dmam)) { 3247 printf("%s: short segment, mbuf lengths:", __func__); 3248 for (m = m0; m; m = m->m_next) 3249 printf(" %d", m->m_len); 3250 printf("\n"); 3251 } 3252 #endif 3253 bus_dmamap_unload(dmat, dmam); 3254 } 3255 MGETHDR(m, M_DONTWAIT, MT_DATA); 3256 if (m == NULL) { 3257 aprint_error_dev(dev, "unable to allocate Tx mbuf\n"); 3258 break; 3259 } 3260 if (m0->m_pkthdr.len > MHLEN) { 3261 MCLGET(m, M_DONTWAIT); 3262 if ((m->m_flags & M_EXT) == 0) { 3263 aprint_error_dev(dev, 3264 "cannot allocate Tx cluster\n"); 3265 m_freem(m); 3266 break; 3267 } 3268 } 3269 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3270 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3271 m_freem(m0); 3272 m0 = m; 3273 m = NULL; 3274 } 3275 if (rc != 0) { 3276 aprint_error_dev(dev, "cannot load Tx buffer, rc = %d\n", rc); 3277 m_freem(m0); 3278 return NULL; 3279 } else if (rtw_seg_too_short(dmam)) { 3280 aprint_error_dev(dev, 3281 "cannot load Tx buffer, segment too short\n"); 3282 bus_dmamap_unload(dmat, dmam); 3283 m_freem(m0); 3284 return NULL; 3285 } else if (dmam->dm_nsegs > ndescfree) { 3286 aprint_error_dev(dev, "too many tx segments\n"); 3287 bus_dmamap_unload(dmat, dmam); 3288 m_freem(m0); 3289 return NULL; 3290 } 3291 return m0; 3292 } 3293 3294 #ifdef RTW_DEBUG 3295 static void 3296 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3297 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3298 { 3299 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3300 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] next %#08x " 3301 "buf %#08x ctl0 %#08x ctl1 %#08x len %#08x\n", 3302 device_xname(sc->sc_dev), ts, action, desc, 3303 le32toh(td->td_buf), le32toh(td->td_next), 3304 le32toh(td->td_ctl0), le32toh(td->td_ctl1), 3305 le32toh(td->td_len))); 3306 } 3307 #endif /* RTW_DEBUG */ 3308 3309 static void 3310 rtw_start(struct ifnet *ifp) 3311 { 3312 int desc, i, lastdesc, npkt, rate; 3313 uint32_t proto_ctl0, ctl0, ctl1; 3314 bus_dmamap_t dmamap; 3315 struct ieee80211com *ic; 3316 struct ieee80211_duration *d0; 3317 struct ieee80211_frame_min *wh; 3318 struct ieee80211_node *ni = NULL; /* XXX: GCC */ 3319 struct mbuf *m0; 3320 struct rtw_softc *sc; 3321 struct rtw_txsoft_blk *tsb = NULL; /* XXX: GCC */ 3322 struct rtw_txdesc_blk *tdb = NULL; /* XXX: GCC */ 3323 struct rtw_txsoft *ts; 3324 struct rtw_txdesc *td; 3325 struct ieee80211_key *k; 3326 3327 sc = (struct rtw_softc *)ifp->if_softc; 3328 ic = &sc->sc_ic; 3329 3330 DPRINTF(sc, RTW_DEBUG_XMIT, 3331 ("%s: enter %s\n", device_xname(sc->sc_dev), __func__)); 3332 3333 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3334 goto out; 3335 3336 /* XXX do real rate control */ 3337 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3338 3339 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3340 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3341 3342 for (;;) { 3343 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3344 continue; 3345 if (m0 == NULL) 3346 break; 3347 3348 wh = mtod(m0, struct ieee80211_frame_min *); 3349 3350 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3351 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3352 m_freem(m0); 3353 break; 3354 } else 3355 k = NULL; 3356 3357 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3358 3359 dmamap = ts->ts_dmamap; 3360 3361 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3362 tdb->tdb_nfree, sc->sc_dev); 3363 3364 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3365 DPRINTF(sc, RTW_DEBUG_XMIT, 3366 ("%s: fail dmamap load\n", __func__)); 3367 goto post_dequeue_err; 3368 } 3369 3370 /* Note well: rtw_dmamap_load_txbuf may have created 3371 * a new chain, so we must find the header once 3372 * more. 3373 */ 3374 wh = mtod(m0, struct ieee80211_frame_min *); 3375 3376 /* XXX do real rate control */ 3377 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3378 IEEE80211_FC0_TYPE_MGT) 3379 rate = 2; 3380 else 3381 rate = MAX(2, ieee80211_get_rate(ni)); 3382 3383 #ifdef RTW_DEBUG 3384 if ((ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) == 3385 (IFF_DEBUG | IFF_LINK2)) { 3386 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3387 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3388 : sizeof(wh), 3389 rate, 0); 3390 } 3391 #endif /* RTW_DEBUG */ 3392 ctl0 = proto_ctl0 | 3393 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3394 3395 switch (rate) { 3396 default: 3397 case 2: 3398 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3399 break; 3400 case 4: 3401 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3402 break; 3403 case 11: 3404 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3405 break; 3406 case 22: 3407 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3408 break; 3409 } 3410 /* XXX >= ? Compare after fragmentation? */ 3411 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3412 ctl0 |= RTW_TXCTL0_RTSEN; 3413 3414 /* XXX Sometimes writes a bogus keyid; h/w doesn't 3415 * seem to care, since we don't activate h/w Tx 3416 * encryption. 3417 */ 3418 if (k != NULL && 3419 k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 3420 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3421 RTW_TXCTL0_KEYID_MASK; 3422 } 3423 3424 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3425 IEEE80211_FC0_TYPE_MGT) { 3426 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3427 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3428 IEEE80211_FC0_SUBTYPE_BEACON) 3429 ctl0 |= RTW_TXCTL0_BEACON; 3430 } 3431 3432 if (ieee80211_compute_duration(wh, k, m0->m_pkthdr.len, 3433 ic->ic_flags, ic->ic_fragthreshold, 3434 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3435 (ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) == 3436 (IFF_DEBUG | IFF_LINK2)) == -1) { 3437 DPRINTF(sc, RTW_DEBUG_XMIT, 3438 ("%s: fail compute duration\n", __func__)); 3439 goto post_load_err; 3440 } 3441 3442 d0 = &ts->ts_d0; 3443 3444 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3445 3446 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3447 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3448 3449 if (d0->d_residue) 3450 ctl1 |= RTW_TXCTL1_LENGEXT; 3451 3452 /* TBD fragmentation */ 3453 3454 ts->ts_first = tdb->tdb_next; 3455 3456 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3457 BUS_DMASYNC_PREWRITE); 3458 3459 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3460 3461 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 3462 3463 if (sc->sc_radiobpf != NULL) { 3464 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3465 3466 rt->rt_rate = rate; 3467 3468 bpf_mtap2(sc->sc_radiobpf, rt, sizeof(sc->sc_txtapu), 3469 m0, BPF_D_OUT); 3470 } 3471 3472 for (i = 0, lastdesc = desc = ts->ts_first; 3473 i < dmamap->dm_nsegs; 3474 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3475 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3476 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3477 ("%s: seg too long\n", __func__)); 3478 goto post_load_err; 3479 } 3480 td = &tdb->tdb_desc[desc]; 3481 td->td_ctl0 = htole32(ctl0); 3482 td->td_ctl1 = htole32(ctl1); 3483 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3484 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3485 td->td_next = htole32(RTW_NEXT_DESC(tdb, desc)); 3486 if (i != 0) 3487 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3488 lastdesc = desc; 3489 #ifdef RTW_DEBUG 3490 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3491 #endif /* RTW_DEBUG */ 3492 } 3493 3494 KASSERT(desc < tdb->tdb_ndesc); 3495 3496 ts->ts_ni = ni; 3497 KASSERT(ni != NULL); 3498 ts->ts_mbuf = m0; 3499 ts->ts_last = lastdesc; 3500 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3501 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3502 htole32(RTW_TXCTL0_FS); 3503 3504 #ifdef RTW_DEBUG 3505 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3506 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3507 #endif /* RTW_DEBUG */ 3508 3509 tdb->tdb_nfree -= dmamap->dm_nsegs; 3510 tdb->tdb_next = desc; 3511 3512 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3513 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3514 3515 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3516 htole32(RTW_TXCTL0_OWN); 3517 3518 #ifdef RTW_DEBUG 3519 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3520 #endif /* RTW_DEBUG */ 3521 3522 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3523 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3524 3525 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3526 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3527 3528 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) 3529 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3530 tsb->tsb_tx_timer = 5; 3531 ifp->if_timer = 1; 3532 rtw_tx_kick(&sc->sc_regs, tsb->tsb_poll); 3533 } 3534 out: 3535 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3536 return; 3537 post_load_err: 3538 bus_dmamap_unload(sc->sc_dmat, dmamap); 3539 m_freem(m0); 3540 post_dequeue_err: 3541 ieee80211_free_node(ni); 3542 return; 3543 } 3544 3545 static void 3546 rtw_idle(struct rtw_regs *regs) 3547 { 3548 int active; 3549 uint8_t tppoll; 3550 3551 /* request stop DMA; wait for packets to stop transmitting. */ 3552 3553 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3554 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL); 3555 3556 for (active = 0; active < 300 && 3557 (tppoll = RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0; 3558 active++) 3559 DELAY(10); 3560 printf("%s: transmit DMA idle in %dus, tppoll %02" PRIx8 "\n", __func__, 3561 active * 10, tppoll); 3562 } 3563 3564 static void 3565 rtw_watchdog(struct ifnet *ifp) 3566 { 3567 int pri, tx_timeouts = 0; 3568 struct rtw_softc *sc; 3569 struct rtw_txsoft_blk *tsb; 3570 3571 sc = ifp->if_softc; 3572 3573 ifp->if_timer = 0; 3574 3575 if (!device_is_active(sc->sc_dev)) 3576 return; 3577 3578 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3579 tsb = &sc->sc_txsoft_blk[pri]; 3580 3581 if (tsb->tsb_tx_timer == 0) 3582 continue; 3583 else if (--tsb->tsb_tx_timer == 0) { 3584 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3585 continue; 3586 else if (rtw_collect_txring(sc, tsb, 3587 &sc->sc_txdesc_blk[pri], 0)) 3588 continue; 3589 printf("%s: transmit timeout, priority %d\n", 3590 ifp->if_xname, pri); 3591 if_statinc(ifp, if_oerrors); 3592 if (pri != RTW_TXPRIBCN) 3593 tx_timeouts++; 3594 } else 3595 ifp->if_timer = 1; 3596 } 3597 3598 if (tx_timeouts > 0) { 3599 /* Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr, 3600 * reset s/w tx-ring pointers, and start transmission. 3601 * 3602 * TBD Stop/restart just the broken rings? 3603 */ 3604 rtw_idle(&sc->sc_regs); 3605 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 3606 rtw_txdescs_reset(sc); 3607 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 3608 rtw_start(ifp); 3609 } 3610 ieee80211_watchdog(&sc->sc_ic); 3611 return; 3612 } 3613 3614 static void 3615 rtw_next_scan(void *arg) 3616 { 3617 struct ieee80211com *ic = arg; 3618 int s; 3619 3620 /* don't call rtw_start w/o network interrupts blocked */ 3621 s = splnet(); 3622 if (ic->ic_state == IEEE80211_S_SCAN) 3623 ieee80211_next_scan(ic); 3624 splx(s); 3625 } 3626 3627 static void 3628 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3629 { 3630 uint16_t bcnitv, bintritv, intval; 3631 int i; 3632 struct rtw_regs *regs = &sc->sc_regs; 3633 3634 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3635 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3636 3637 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3638 3639 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3640 3641 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); 3642 3643 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3644 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); 3645 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3646 /* interrupt host 1ms before the TBTT */ 3647 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV; 3648 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV); 3649 RTW_WRITE16(regs, RTW_BINTRITV, bintritv); 3650 /* magic from Linux */ 3651 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND)); 3652 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); 3653 rtw_set_access(regs, RTW_ACCESS_NONE); 3654 3655 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 3656 } 3657 3658 /* Synchronize the hardware state with the software state. */ 3659 static int 3660 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3661 { 3662 struct ifnet *ifp = ic->ic_ifp; 3663 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3664 enum ieee80211_state ostate; 3665 int error; 3666 3667 ostate = ic->ic_state; 3668 3669 aprint_debug_dev(sc->sc_dev, "%s: l.%d\n", __func__, __LINE__); 3670 rtw_led_newstate(sc, nstate); 3671 3672 aprint_debug_dev(sc->sc_dev, "%s: l.%d\n", __func__, __LINE__); 3673 if (nstate == IEEE80211_S_INIT) { 3674 callout_stop(&sc->sc_scan_ch); 3675 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3676 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3677 } 3678 3679 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3680 rtw_pwrstate(sc, RTW_ON); 3681 3682 if ((error = rtw_tune(sc)) != 0) 3683 return error; 3684 3685 switch (nstate) { 3686 case IEEE80211_S_INIT: 3687 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3688 break; 3689 case IEEE80211_S_SCAN: 3690 if (ostate != IEEE80211_S_SCAN) { 3691 (void)memset(ic->ic_bss->ni_bssid, 0, 3692 IEEE80211_ADDR_LEN); 3693 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3694 } 3695 3696 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3697 rtw_next_scan, ic); 3698 3699 break; 3700 case IEEE80211_S_RUN: 3701 switch (ic->ic_opmode) { 3702 case IEEE80211_M_HOSTAP: 3703 case IEEE80211_M_IBSS: 3704 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3705 /*FALLTHROUGH*/ 3706 case IEEE80211_M_AHDEMO: 3707 case IEEE80211_M_STA: 3708 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3709 ic->ic_bss->ni_intval); 3710 break; 3711 case IEEE80211_M_MONITOR: 3712 break; 3713 } 3714 rtw_set_nettype(sc, ic->ic_opmode); 3715 break; 3716 case IEEE80211_S_ASSOC: 3717 case IEEE80211_S_AUTH: 3718 break; 3719 } 3720 3721 if (nstate != IEEE80211_S_SCAN) 3722 callout_stop(&sc->sc_scan_ch); 3723 3724 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3725 } 3726 3727 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3728 static uint64_t 3729 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3730 { 3731 uint32_t tsftl, tsfth; 3732 3733 tsfth = RTW_READ(regs, RTW_TSFTRH); 3734 tsftl = RTW_READ(regs, RTW_TSFTRL); 3735 if (tsftl < rstamp) /* Compensate for rollover. */ 3736 tsfth--; 3737 return ((uint64_t)tsfth << 32) | rstamp; 3738 } 3739 3740 static void 3741 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3742 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3743 { 3744 struct ifnet *ifp = ic->ic_ifp; 3745 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3746 3747 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3748 3749 switch (subtype) { 3750 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3751 case IEEE80211_FC0_SUBTYPE_BEACON: 3752 if (ic->ic_opmode == IEEE80211_M_IBSS && 3753 ic->ic_state == IEEE80211_S_RUN && 3754 device_is_active(sc->sc_dev)) { 3755 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp); 3756 if (le64toh(ni->ni_tstamp.tsf) >= tsf) 3757 (void)ieee80211_ibss_merge(ni); 3758 } 3759 break; 3760 default: 3761 break; 3762 } 3763 return; 3764 } 3765 3766 static struct ieee80211_node * 3767 rtw_node_alloc(struct ieee80211_node_table *nt) 3768 { 3769 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3770 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3771 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3772 3773 DPRINTF(sc, RTW_DEBUG_NODE, 3774 ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 3775 return ni; 3776 } 3777 3778 static void 3779 rtw_node_free(struct ieee80211_node *ni) 3780 { 3781 struct ieee80211com *ic = ni->ni_ic; 3782 struct ifnet *ifp = ic->ic_ifp; 3783 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3784 3785 DPRINTF(sc, RTW_DEBUG_NODE, 3786 ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 3787 ether_sprintf(ni->ni_bssid))); 3788 (*sc->sc_mtbl.mt_node_free)(ni); 3789 } 3790 3791 static int 3792 rtw_media_change(struct ifnet *ifp) 3793 { 3794 int error; 3795 3796 error = ieee80211_media_change(ifp); 3797 if (error == ENETRESET) { 3798 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == 3799 (IFF_RUNNING | IFF_UP)) 3800 rtw_init(ifp); /* XXX lose error */ 3801 error = 0; 3802 } 3803 return error; 3804 } 3805 3806 static void 3807 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3808 { 3809 struct rtw_softc *sc = ifp->if_softc; 3810 3811 if (!device_is_active(sc->sc_dev)) { 3812 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3813 imr->ifm_status = 0; 3814 return; 3815 } 3816 ieee80211_media_status(ifp, imr); 3817 } 3818 3819 static inline void 3820 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3821 { 3822 (void)strlcpy(ifp->if_xname, dvname, IFNAMSIZ); 3823 ifp->if_softc = softc; 3824 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 3825 ifp->if_ioctl = rtw_ioctl; 3826 ifp->if_start = rtw_start; 3827 ifp->if_watchdog = rtw_watchdog; 3828 ifp->if_init = rtw_init; 3829 ifp->if_stop = rtw_stop; 3830 } 3831 3832 static inline void 3833 rtw_set80211props(struct ieee80211com *ic) 3834 { 3835 int nrate; 3836 ic->ic_phytype = IEEE80211_T_DS; 3837 ic->ic_opmode = IEEE80211_M_STA; 3838 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3839 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 3840 3841 nrate = 0; 3842 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3843 IEEE80211_RATE_BASIC | 2; 3844 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3845 IEEE80211_RATE_BASIC | 4; 3846 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3847 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3848 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3849 } 3850 3851 static inline void 3852 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3853 { 3854 mtbl->mt_newstate = ic->ic_newstate; 3855 ic->ic_newstate = rtw_newstate; 3856 3857 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3858 ic->ic_recv_mgmt = rtw_recv_mgmt; 3859 3860 mtbl->mt_node_free = ic->ic_node_free; 3861 ic->ic_node_free = rtw_node_free; 3862 3863 mtbl->mt_node_alloc = ic->ic_node_alloc; 3864 ic->ic_node_alloc = rtw_node_alloc; 3865 3866 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3867 ic->ic_crypto.cs_key_set = rtw_key_set; 3868 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3869 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3870 } 3871 3872 static inline void 3873 rtw_init_radiotap(struct rtw_softc *sc) 3874 { 3875 uint32_t present; 3876 3877 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3878 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3879 3880 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 3881 present = htole32(RTW_PHILIPS_RX_RADIOTAP_PRESENT); 3882 else 3883 present = htole32(RTW_RX_RADIOTAP_PRESENT); 3884 sc->sc_rxtap.rr_ihdr.it_present = present; 3885 3886 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3887 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3888 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3889 } 3890 3891 static int 3892 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3893 { 3894 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3895 SIMPLEQ_INIT(&tsb->tsb_freeq); 3896 tsb->tsb_ndesc = qlen; 3897 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3898 M_NOWAIT); 3899 if (tsb->tsb_desc == NULL) 3900 return ENOMEM; 3901 return 0; 3902 } 3903 3904 static void 3905 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3906 { 3907 int pri; 3908 struct rtw_txsoft_blk *tsb; 3909 3910 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3911 tsb = &sc->sc_txsoft_blk[pri]; 3912 free(tsb->tsb_desc, M_DEVBUF); 3913 tsb->tsb_desc = NULL; 3914 } 3915 } 3916 3917 static int 3918 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3919 { 3920 int pri, rc = 0; 3921 int qlen[RTW_NTXPRI] = 3922 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3923 struct rtw_txsoft_blk *tsbs; 3924 3925 tsbs = sc->sc_txsoft_blk; 3926 3927 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3928 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3929 if (rc != 0) 3930 break; 3931 } 3932 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3933 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3934 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3935 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3936 return rc; 3937 } 3938 3939 static void 3940 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3941 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3942 { 3943 tdb->tdb_ndesc = ndesc; 3944 tdb->tdb_desc = desc; 3945 tdb->tdb_physbase = physbase; 3946 tdb->tdb_ofs = ofs; 3947 3948 (void)memset(tdb->tdb_desc, 0, 3949 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3950 3951 rtw_txdesc_blk_init(tdb); 3952 tdb->tdb_next = 0; 3953 } 3954 3955 static void 3956 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3957 { 3958 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3959 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3960 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3961 3962 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3963 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3964 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3965 3966 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3967 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3968 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3969 3970 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3971 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3972 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3973 } 3974 3975 static struct rtw_rf * 3976 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3977 { 3978 rtw_rf_write_t rf_write; 3979 struct rtw_rf *rf; 3980 3981 switch (rfchipid) { 3982 default: 3983 rf_write = rtw_rf_hostwrite; 3984 break; 3985 case RTW_RFCHIPID_INTERSIL: 3986 case RTW_RFCHIPID_PHILIPS: 3987 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3988 case RTW_RFCHIPID_RFMD: 3989 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3990 break; 3991 } 3992 3993 switch (rfchipid) { 3994 case RTW_RFCHIPID_GCT: 3995 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0); 3996 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3997 break; 3998 case RTW_RFCHIPID_MAXIM: 3999 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 4000 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 4001 break; 4002 case RTW_RFCHIPID_PHILIPS: 4003 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 4004 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 4005 break; 4006 case RTW_RFCHIPID_RFMD: 4007 /* XXX RFMD has no RF constructor */ 4008 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 4009 /*FALLTHROUGH*/ 4010 default: 4011 return NULL; 4012 } 4013 rf->rf_continuous_tx_cb = 4014 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 4015 rf->rf_continuous_tx_arg = (void *)sc; 4016 return rf; 4017 } 4018 4019 /* Revision C and later use a different PHY delay setting than 4020 * revisions A and B. 4021 */ 4022 static uint8_t 4023 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 4024 { 4025 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 4026 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 4027 4028 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); 4029 4030 RTW_WRITE(regs, RTW_RCR, REVAB); 4031 RTW_WBW(regs, RTW_RCR, RTW_RCR); 4032 RTW_WRITE(regs, RTW_RCR, REVC); 4033 4034 RTW_WBR(regs, RTW_RCR, RTW_RCR); 4035 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 4036 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 4037 4038 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 4039 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 4040 4041 return phydelay; 4042 #undef REVC 4043 } 4044 4045 void 4046 rtw_attach(struct rtw_softc *sc) 4047 { 4048 struct ifnet *ifp = &sc->sc_if; 4049 struct ieee80211com *ic = &sc->sc_ic; 4050 struct rtw_txsoft_blk *tsb; 4051 int pri, rc; 4052 4053 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 4054 4055 rtw_cipher_wep = ieee80211_cipher_wep; 4056 rtw_cipher_wep.ic_decap = rtw_wep_decap; 4057 4058 NEXT_ATTACH_STATE(sc, DETACHED); 4059 4060 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rtw_softintr, sc); 4061 if (sc->sc_soft_ih == NULL) { 4062 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 4063 goto err; 4064 } 4065 4066 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 4067 case RTW_TCR_HWVERID_F: 4068 sc->sc_hwverid = 'F'; 4069 break; 4070 case RTW_TCR_HWVERID_D: 4071 sc->sc_hwverid = 'D'; 4072 break; 4073 default: 4074 sc->sc_hwverid = '?'; 4075 break; 4076 } 4077 aprint_verbose_dev(sc->sc_dev, "hardware version %c\n", 4078 sc->sc_hwverid); 4079 4080 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 4081 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 4082 0); 4083 4084 if (rc != 0) { 4085 aprint_error_dev(sc->sc_dev, 4086 "could not allocate hw descriptors, error %d\n", rc); 4087 goto err; 4088 } 4089 4090 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 4091 4092 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 4093 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 4094 (void **)&sc->sc_descs, BUS_DMA_COHERENT); 4095 4096 if (rc != 0) { 4097 aprint_error_dev(sc->sc_dev, 4098 "could not map hw descriptors, error %d\n", rc); 4099 goto err; 4100 } 4101 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 4102 4103 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 4104 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 4105 4106 if (rc != 0) { 4107 aprint_error_dev(sc->sc_dev, 4108 "could not create DMA map for hw descriptors, error %d\n", 4109 rc); 4110 goto err; 4111 } 4112 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 4113 4114 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 4115 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 4116 4117 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4118 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 4119 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 4120 } 4121 4122 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 4123 sizeof(struct rtw_descs), NULL, 0); 4124 4125 if (rc != 0) { 4126 aprint_error_dev(sc->sc_dev, 4127 "could not load DMA map for hw descriptors, error %d\n", 4128 rc); 4129 goto err; 4130 } 4131 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 4132 4133 if (rtw_txsoft_blk_setup_all(sc) != 0) 4134 goto err; 4135 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 4136 4137 rtw_txdesc_blk_setup_all(sc); 4138 4139 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 4140 4141 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 4142 4143 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4144 tsb = &sc->sc_txsoft_blk[pri]; 4145 4146 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 4147 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 4148 aprint_error_dev(sc->sc_dev, 4149 "could not load DMA map for hw tx descriptors, " 4150 "error %d\n", rc); 4151 goto err; 4152 } 4153 } 4154 4155 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 4156 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 4157 RTW_RXQLEN)) != 0) { 4158 aprint_error_dev(sc->sc_dev, 4159 "could not load DMA map for hw rx descriptors, error %d\n", 4160 rc); 4161 goto err; 4162 } 4163 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 4164 4165 /* Reset the chip to a known state. */ 4166 if (rtw_reset(sc) != 0) 4167 goto err; 4168 NEXT_ATTACH_STATE(sc, FINISH_RESET); 4169 4170 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 4171 4172 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 4173 sc->sc_flags |= RTW_F_9356SROM; 4174 4175 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 4176 sc->sc_dev) != 0) 4177 goto err; 4178 4179 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 4180 4181 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 4182 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 4183 sc->sc_dev) != 0) { 4184 aprint_error_dev(sc->sc_dev, 4185 "attach failed, malformed serial ROM\n"); 4186 goto err; 4187 } 4188 4189 aprint_verbose_dev(sc->sc_dev, "%s PHY\n", 4190 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 4191 4192 aprint_verbose_dev(sc->sc_dev, "carrier-sense threshold %u\n", 4193 sc->sc_csthr); 4194 4195 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 4196 4197 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 4198 sc->sc_flags & RTW_F_DIGPHY); 4199 4200 if (sc->sc_rf == NULL) { 4201 aprint_verbose_dev(sc->sc_dev, 4202 "attach failed, could not attach RF\n"); 4203 goto err; 4204 } 4205 4206 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 4207 4208 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4209 4210 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4211 ("%s: PHY delay %d\n", device_xname(sc->sc_dev), sc->sc_phydelay)); 4212 4213 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4214 rtw_identify_country(&sc->sc_regs, &sc->sc_locale); 4215 4216 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, sc->sc_dev); 4217 4218 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4219 sc->sc_dev) != 0) 4220 goto err; 4221 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4222 4223 rtw_setifprops(ifp, device_xname(sc->sc_dev), (void*)sc); 4224 4225 IFQ_SET_READY(&ifp->if_snd); 4226 4227 sc->sc_ic.ic_ifp = ifp; 4228 rtw_set80211props(&sc->sc_ic); 4229 4230 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4231 NEXT_ATTACH_STATE(sc, FINISH_LED_ATTACH); 4232 4233 /* 4234 * Call MI attach routines. 4235 */ 4236 rc = if_initialize(ifp); 4237 if (rc != 0) { 4238 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", rc); 4239 goto err; 4240 } 4241 ieee80211_ifattach(ic); 4242 /* Use common softint-based if_input */ 4243 ifp->if_percpuq = if_percpuq_create(ifp); 4244 if_register(ifp); 4245 4246 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4247 4248 /* possibly we should fill in our own sc_send_prresp, since 4249 * the RTL8180 is probably sending probe responses in ad hoc 4250 * mode. 4251 */ 4252 4253 /* complete initialization */ 4254 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4255 callout_init(&sc->sc_scan_ch, 0); 4256 4257 rtw_init_radiotap(sc); 4258 4259 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 4260 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4261 4262 NEXT_ATTACH_STATE(sc, FINISHED); 4263 4264 ieee80211_announce(ic); 4265 return; 4266 err: 4267 rtw_detach(sc); 4268 return; 4269 } 4270 4271 int 4272 rtw_detach(struct rtw_softc *sc) 4273 { 4274 struct ifnet *ifp = &sc->sc_if; 4275 int pri, s; 4276 4277 s = splnet(); 4278 4279 switch (sc->sc_attach_state) { 4280 case FINISHED: 4281 rtw_stop(ifp, 1); 4282 4283 pmf_device_deregister(sc->sc_dev); 4284 callout_stop(&sc->sc_scan_ch); 4285 ieee80211_ifdetach(&sc->sc_ic); 4286 if_detach(ifp); 4287 /*FALLTHROUGH*/ 4288 case FINISH_LED_ATTACH: 4289 rtw_led_detach(&sc->sc_led_state); 4290 /*FALLTHROUGH*/ 4291 case FINISH_ID_STA: 4292 case FINISH_RF_ATTACH: 4293 rtw_rf_destroy(sc->sc_rf); 4294 sc->sc_rf = NULL; 4295 /*FALLTHROUGH*/ 4296 case FINISH_PARSE_SROM: 4297 case FINISH_READ_SROM: 4298 rtw_srom_free(&sc->sc_srom); 4299 /*FALLTHROUGH*/ 4300 case FINISH_RESET: 4301 case FINISH_RXMAPS_CREATE: 4302 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4303 RTW_RXQLEN); 4304 /*FALLTHROUGH*/ 4305 case FINISH_TXMAPS_CREATE: 4306 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4307 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4308 sc->sc_txsoft_blk[pri].tsb_desc, 4309 sc->sc_txsoft_blk[pri].tsb_ndesc); 4310 } 4311 /*FALLTHROUGH*/ 4312 case FINISH_TXDESCBLK_SETUP: 4313 case FINISH_TXCTLBLK_SETUP: 4314 rtw_txsoft_blk_cleanup_all(sc); 4315 /*FALLTHROUGH*/ 4316 case FINISH_DESCMAP_LOAD: 4317 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4318 /*FALLTHROUGH*/ 4319 case FINISH_DESCMAP_CREATE: 4320 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4321 /*FALLTHROUGH*/ 4322 case FINISH_DESC_MAP: 4323 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 4324 sizeof(struct rtw_descs)); 4325 /*FALLTHROUGH*/ 4326 case FINISH_DESC_ALLOC: 4327 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4328 sc->sc_desc_nsegs); 4329 /*FALLTHROUGH*/ 4330 case DETACHED: 4331 if (sc->sc_soft_ih != NULL) { 4332 softint_disestablish(sc->sc_soft_ih); 4333 sc->sc_soft_ih = NULL; 4334 } 4335 NEXT_ATTACH_STATE(sc, DETACHED); 4336 break; 4337 } 4338 splx(s); 4339 return 0; 4340 } 4341
Indexes created Mon Oct 27 08:10:08 GMT 2025