rtw.c revision 1.17
1 /* $NetBSD: rtw.c,v 1.17 2004/12/23 06:00:35 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.17 2004/12/23 06:00:35 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #if 0 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #endif 54 #include <sys/time.h> 55 #include <sys/types.h> 56 57 #include <machine/endian.h> 58 #include <machine/bus.h> 59 #include <machine/intr.h> /* splnet */ 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_compat.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <dev/ic/rtwreg.h> 76 #include <dev/ic/rtwvar.h> 77 #include <dev/ic/rtwphyio.h> 78 #include <dev/ic/rtwphy.h> 79 80 #include <dev/ic/smc93cx6var.h> 81 82 #define KASSERT2(__cond, __msg) \ 83 do { \ 84 if (!(__cond)) \ 85 panic __msg ; \ 86 } while (0) 87 88 int rtw_rfprog_fallback = 0; 89 int rtw_host_rfio = 0; 90 int rtw_flush_rfio = 1; 91 int rtw_rfio_delay = 0; 92 93 #ifdef RTW_DEBUG 94 int rtw_debug = 2; 95 #endif /* RTW_DEBUG */ 96 97 #define NEXT_ATTACH_STATE(sc, state) do { \ 98 DPRINTF(sc, ("%s: attach state %s\n", __func__, #state)); \ 99 sc->sc_attach_state = state; \ 100 } while (0) 101 102 int rtw_dwelltime = 1000; /* milliseconds */ 103 104 static void rtw_start(struct ifnet *); 105 106 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 107 static int rtw_sysctl_verify_rfio_delay(SYSCTLFN_PROTO); 108 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 109 #ifdef RTW_DEBUG 110 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 111 #endif /* RTW_DEBUG */ 112 113 /* 114 * Setup sysctl(3) MIB, hw.rtw.* 115 * 116 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 117 */ 118 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 119 { 120 int rc; 121 struct sysctlnode *cnode, *rnode; 122 123 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 124 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 125 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 126 goto err; 127 128 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 129 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 130 "Realtek RTL818x 802.11 controls", 131 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 132 goto err; 133 134 #ifdef RTW_DEBUG 135 /* control debugging printfs */ 136 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 137 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 138 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 139 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 140 CTL_CREATE, CTL_EOL)) != 0) 141 goto err; 142 #endif /* RTW_DEBUG */ 143 /* set fallback RF programming method */ 144 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 145 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 146 "rfprog_fallback", 147 SYSCTL_DESCR("Set fallback RF programming method"), 148 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 149 CTL_CREATE, CTL_EOL)) != 0) 150 goto err; 151 152 /* force host to flush I/O by reading RTW_PHYADDR */ 153 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 154 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 155 "flush_rfio", SYSCTL_DESCR("Enable RF I/O flushing"), 156 rtw_sysctl_verify_rfio, 0, &rtw_flush_rfio, 0, 157 CTL_CREATE, CTL_EOL)) != 0) 158 goto err; 159 160 /* force host to control RF I/O bus */ 161 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 162 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 163 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 164 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 165 CTL_CREATE, CTL_EOL)) != 0) 166 goto err; 167 168 /* control RF I/O delay */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfio_delay", SYSCTL_DESCR("Set RF I/O delay"), 172 rtw_sysctl_verify_rfio_delay, 0, &rtw_rfio_delay, 0, 173 CTL_CREATE, CTL_EOL)) != 0) 174 goto err; 175 176 return; 177 err: 178 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 179 } 180 181 static int 182 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 183 { 184 int error, t; 185 struct sysctlnode node; 186 187 node = *rnode; 188 t = *(int*)rnode->sysctl_data; 189 node.sysctl_data = &t; 190 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 191 if (error || newp == NULL) 192 return (error); 193 194 if (t < lower || t > upper) 195 return (EINVAL); 196 197 *(int*)rnode->sysctl_data = t; 198 199 return (0); 200 } 201 202 static int 203 rtw_sysctl_verify_rfio_delay(SYSCTLFN_ARGS) 204 { 205 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1000000); 206 } 207 208 static int 209 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 210 { 211 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 212 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 213 } 214 215 static int 216 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 217 { 218 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1); 219 } 220 221 #ifdef RTW_DEBUG 222 static int 223 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 224 { 225 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 2); 226 } 227 228 static void 229 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 230 { 231 #define PRINTREG32(sc, reg) \ 232 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 233 dvname, reg, RTW_READ(regs, reg))) 234 235 #define PRINTREG16(sc, reg) \ 236 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %04x\n", \ 237 dvname, reg, RTW_READ16(regs, reg))) 238 239 #define PRINTREG8(sc, reg) \ 240 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %02x\n", \ 241 dvname, reg, RTW_READ8(regs, reg))) 242 243 RTW_DPRINTF2(("%s: %s\n", dvname, where)); 244 245 PRINTREG32(regs, RTW_IDR0); 246 PRINTREG32(regs, RTW_IDR1); 247 PRINTREG32(regs, RTW_MAR0); 248 PRINTREG32(regs, RTW_MAR1); 249 PRINTREG32(regs, RTW_TSFTRL); 250 PRINTREG32(regs, RTW_TSFTRH); 251 PRINTREG32(regs, RTW_TLPDA); 252 PRINTREG32(regs, RTW_TNPDA); 253 PRINTREG32(regs, RTW_THPDA); 254 PRINTREG32(regs, RTW_TCR); 255 PRINTREG32(regs, RTW_RCR); 256 PRINTREG32(regs, RTW_TINT); 257 PRINTREG32(regs, RTW_TBDA); 258 PRINTREG32(regs, RTW_ANAPARM); 259 PRINTREG32(regs, RTW_BB); 260 PRINTREG32(regs, RTW_PHYCFG); 261 PRINTREG32(regs, RTW_WAKEUP0L); 262 PRINTREG32(regs, RTW_WAKEUP0H); 263 PRINTREG32(regs, RTW_WAKEUP1L); 264 PRINTREG32(regs, RTW_WAKEUP1H); 265 PRINTREG32(regs, RTW_WAKEUP2LL); 266 PRINTREG32(regs, RTW_WAKEUP2LH); 267 PRINTREG32(regs, RTW_WAKEUP2HL); 268 PRINTREG32(regs, RTW_WAKEUP2HH); 269 PRINTREG32(regs, RTW_WAKEUP3LL); 270 PRINTREG32(regs, RTW_WAKEUP3LH); 271 PRINTREG32(regs, RTW_WAKEUP3HL); 272 PRINTREG32(regs, RTW_WAKEUP3HH); 273 PRINTREG32(regs, RTW_WAKEUP4LL); 274 PRINTREG32(regs, RTW_WAKEUP4LH); 275 PRINTREG32(regs, RTW_WAKEUP4HL); 276 PRINTREG32(regs, RTW_WAKEUP4HH); 277 PRINTREG32(regs, RTW_DK0); 278 PRINTREG32(regs, RTW_DK1); 279 PRINTREG32(regs, RTW_DK2); 280 PRINTREG32(regs, RTW_DK3); 281 PRINTREG32(regs, RTW_RETRYCTR); 282 PRINTREG32(regs, RTW_RDSAR); 283 PRINTREG32(regs, RTW_FER); 284 PRINTREG32(regs, RTW_FEMR); 285 PRINTREG32(regs, RTW_FPSR); 286 PRINTREG32(regs, RTW_FFER); 287 288 /* 16-bit registers */ 289 PRINTREG16(regs, RTW_BRSR); 290 PRINTREG16(regs, RTW_IMR); 291 PRINTREG16(regs, RTW_ISR); 292 PRINTREG16(regs, RTW_BCNITV); 293 PRINTREG16(regs, RTW_ATIMWND); 294 PRINTREG16(regs, RTW_BINTRITV); 295 PRINTREG16(regs, RTW_ATIMTRITV); 296 PRINTREG16(regs, RTW_CRC16ERR); 297 PRINTREG16(regs, RTW_CRC0); 298 PRINTREG16(regs, RTW_CRC1); 299 PRINTREG16(regs, RTW_CRC2); 300 PRINTREG16(regs, RTW_CRC3); 301 PRINTREG16(regs, RTW_CRC4); 302 PRINTREG16(regs, RTW_CWR); 303 304 /* 8-bit registers */ 305 PRINTREG8(regs, RTW_CR); 306 PRINTREG8(regs, RTW_9346CR); 307 PRINTREG8(regs, RTW_CONFIG0); 308 PRINTREG8(regs, RTW_CONFIG1); 309 PRINTREG8(regs, RTW_CONFIG2); 310 PRINTREG8(regs, RTW_MSR); 311 PRINTREG8(regs, RTW_CONFIG3); 312 PRINTREG8(regs, RTW_CONFIG4); 313 PRINTREG8(regs, RTW_TESTR); 314 PRINTREG8(regs, RTW_PSR); 315 PRINTREG8(regs, RTW_SCR); 316 PRINTREG8(regs, RTW_PHYDELAY); 317 PRINTREG8(regs, RTW_CRCOUNT); 318 PRINTREG8(regs, RTW_PHYADDR); 319 PRINTREG8(regs, RTW_PHYDATAW); 320 PRINTREG8(regs, RTW_PHYDATAR); 321 PRINTREG8(regs, RTW_CONFIG5); 322 PRINTREG8(regs, RTW_TPPOLL); 323 324 PRINTREG16(regs, RTW_BSSID16); 325 PRINTREG32(regs, RTW_BSSID32); 326 #undef PRINTREG32 327 #undef PRINTREG16 328 #undef PRINTREG8 329 } 330 #endif /* RTW_DEBUG */ 331 332 void 333 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 334 { 335 struct rtw_regs *regs = &sc->sc_regs; 336 337 u_int32_t tcr; 338 tcr = RTW_READ(regs, RTW_TCR); 339 tcr &= ~RTW_TCR_LBK_MASK; 340 if (enable) 341 tcr |= RTW_TCR_LBK_CONT; 342 else 343 tcr |= RTW_TCR_LBK_NORMAL; 344 RTW_WRITE(regs, RTW_TCR, tcr); 345 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 346 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 347 rtw_txdac_enable(sc, !enable); 348 rtw_set_access(sc, RTW_ACCESS_ANAPARM); /* XXX Voodoo from Linux. */ 349 rtw_set_access(sc, RTW_ACCESS_NONE); 350 } 351 352 static const char * 353 rtw_access_string(enum rtw_access access) 354 { 355 switch (access) { 356 case RTW_ACCESS_NONE: 357 return "none"; 358 case RTW_ACCESS_CONFIG: 359 return "config"; 360 case RTW_ACCESS_ANAPARM: 361 return "anaparm"; 362 default: 363 return "unknown"; 364 } 365 } 366 367 static void 368 rtw_set_access1(struct rtw_regs *regs, 369 enum rtw_access oaccess, enum rtw_access naccess) 370 { 371 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 372 KASSERT(oaccess >= RTW_ACCESS_NONE && oaccess <= RTW_ACCESS_ANAPARM); 373 374 if (naccess == oaccess) 375 return; 376 377 switch (naccess) { 378 case RTW_ACCESS_NONE: 379 switch (oaccess) { 380 case RTW_ACCESS_ANAPARM: 381 rtw_anaparm_enable(regs, 0); 382 /*FALLTHROUGH*/ 383 case RTW_ACCESS_CONFIG: 384 rtw_config0123_enable(regs, 0); 385 /*FALLTHROUGH*/ 386 case RTW_ACCESS_NONE: 387 break; 388 } 389 break; 390 case RTW_ACCESS_CONFIG: 391 switch (oaccess) { 392 case RTW_ACCESS_NONE: 393 rtw_config0123_enable(regs, 1); 394 /*FALLTHROUGH*/ 395 case RTW_ACCESS_CONFIG: 396 break; 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 break; 400 } 401 break; 402 case RTW_ACCESS_ANAPARM: 403 switch (oaccess) { 404 case RTW_ACCESS_NONE: 405 rtw_config0123_enable(regs, 1); 406 /*FALLTHROUGH*/ 407 case RTW_ACCESS_CONFIG: 408 rtw_anaparm_enable(regs, 1); 409 /*FALLTHROUGH*/ 410 case RTW_ACCESS_ANAPARM: 411 break; 412 } 413 break; 414 } 415 } 416 417 void 418 rtw_set_access(struct rtw_softc *sc, enum rtw_access access) 419 { 420 rtw_set_access1(&sc->sc_regs, sc->sc_access, access); 421 RTW_DPRINTF(("%s: access %s -> %s\n", sc->sc_dev.dv_xname, 422 rtw_access_string(sc->sc_access), 423 rtw_access_string(access))); 424 sc->sc_access = access; 425 } 426 427 /* 428 * Enable registers, switch register banks. 429 */ 430 void 431 rtw_config0123_enable(struct rtw_regs *regs, int enable) 432 { 433 u_int8_t ecr; 434 ecr = RTW_READ8(regs, RTW_9346CR); 435 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 436 if (enable) 437 ecr |= RTW_9346CR_EEM_CONFIG; 438 else { 439 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 440 ecr |= RTW_9346CR_EEM_NORMAL; 441 } 442 RTW_WRITE8(regs, RTW_9346CR, ecr); 443 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 444 } 445 446 /* requires rtw_config0123_enable(, 1) */ 447 void 448 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 449 { 450 u_int8_t cfg3; 451 452 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 453 cfg3 |= RTW_CONFIG3_CLKRUNEN; 454 if (enable) 455 cfg3 |= RTW_CONFIG3_PARMEN; 456 else 457 cfg3 &= ~RTW_CONFIG3_PARMEN; 458 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 459 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 460 } 461 462 /* requires rtw_anaparm_enable(, 1) */ 463 void 464 rtw_txdac_enable(struct rtw_softc *sc, int enable) 465 { 466 u_int32_t anaparm; 467 struct rtw_regs *regs = &sc->sc_regs; 468 469 anaparm = RTW_READ(regs, RTW_ANAPARM); 470 if (enable) 471 anaparm &= ~RTW_ANAPARM_TXDACOFF; 472 else 473 anaparm |= RTW_ANAPARM_TXDACOFF; 474 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 475 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 476 } 477 478 static __inline int 479 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 480 { 481 u_int8_t cr; 482 int i; 483 484 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 485 486 RTW_WBR(regs, RTW_CR, RTW_CR); 487 488 for (i = 0; i < 10000; i++) { 489 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 490 RTW_DPRINTF(("%s: reset in %dus\n", dvname, i)); 491 return 0; 492 } 493 RTW_RBR(regs, RTW_CR, RTW_CR); 494 DELAY(1); /* 1us */ 495 } 496 497 printf("%s: reset failed\n", dvname); 498 return ETIMEDOUT; 499 } 500 501 static __inline int 502 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 503 { 504 uint32_t tcr; 505 506 /* from Linux driver */ 507 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 508 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 509 510 RTW_WRITE(regs, RTW_TCR, tcr); 511 512 RTW_WBW(regs, RTW_CR, RTW_TCR); 513 514 return rtw_chip_reset1(regs, dvname); 515 } 516 517 static __inline int 518 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 519 { 520 int i; 521 u_int8_t ecr; 522 523 ecr = RTW_READ8(regs, RTW_9346CR); 524 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 525 RTW_WRITE8(regs, RTW_9346CR, ecr); 526 527 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 528 529 /* wait 2.5ms for completion */ 530 for (i = 0; i < 25; i++) { 531 ecr = RTW_READ8(regs, RTW_9346CR); 532 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 533 RTW_DPRINTF(("%s: recall EEPROM in %dus\n", dvname, 534 i * 100)); 535 return 0; 536 } 537 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 538 DELAY(100); 539 } 540 printf("%s: recall EEPROM failed\n", dvname); 541 return ETIMEDOUT; 542 } 543 544 static __inline int 545 rtw_reset(struct rtw_softc *sc) 546 { 547 int rc; 548 uint8_t config1; 549 550 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 551 return rc; 552 553 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 554 ; 555 556 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 557 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 558 /* TBD turn off maximum power saving? */ 559 560 return 0; 561 } 562 563 static __inline int 564 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txctl *descs, 565 u_int ndescs) 566 { 567 int i, rc = 0; 568 for (i = 0; i < ndescs; i++) { 569 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 570 0, 0, &descs[i].stx_dmamap); 571 if (rc != 0) 572 break; 573 } 574 return rc; 575 } 576 577 static __inline int 578 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 579 u_int ndescs) 580 { 581 int i, rc = 0; 582 for (i = 0; i < ndescs; i++) { 583 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 584 &descs[i].srx_dmamap); 585 if (rc != 0) 586 break; 587 } 588 return rc; 589 } 590 591 static __inline void 592 rtw_rxctls_setup(struct rtw_rxctl *descs) 593 { 594 int i; 595 for (i = 0; i < RTW_RXQLEN; i++) 596 descs[i].srx_mbuf = NULL; 597 } 598 599 static __inline void 600 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 601 u_int ndescs) 602 { 603 int i; 604 for (i = 0; i < ndescs; i++) { 605 if (descs[i].srx_dmamap != NULL) 606 bus_dmamap_destroy(dmat, descs[i].srx_dmamap); 607 } 608 } 609 610 static __inline void 611 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txctl *descs, 612 u_int ndescs) 613 { 614 int i; 615 for (i = 0; i < ndescs; i++) { 616 if (descs[i].stx_dmamap != NULL) 617 bus_dmamap_destroy(dmat, descs[i].stx_dmamap); 618 } 619 } 620 621 static __inline void 622 rtw_srom_free(struct rtw_srom *sr) 623 { 624 sr->sr_size = 0; 625 if (sr->sr_content == NULL) 626 return; 627 free(sr->sr_content, M_DEVBUF); 628 sr->sr_content = NULL; 629 } 630 631 static void 632 rtw_srom_defaults(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 633 enum rtw_rfchipid *rfchipid, u_int32_t *rcr) 634 { 635 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 636 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 637 *rcr |= RTW_RCR_ENCS1; 638 *rfchipid = RTW_RFCHIPID_PHILIPS; 639 } 640 641 static int 642 rtw_srom_parse(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 643 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, enum rtw_locale *locale, 644 const char *dvname) 645 { 646 int i; 647 const char *rfname, *paname; 648 char scratch[sizeof("unknown 0xXX")]; 649 u_int16_t version; 650 u_int8_t mac[IEEE80211_ADDR_LEN]; 651 652 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 653 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 654 655 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 656 printf("%s: SROM version %d.%d", dvname, version >> 8, version & 0xff); 657 658 if (version <= 0x0101) { 659 printf(" is not understood, limping along with defaults\n"); 660 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 661 return 0; 662 } 663 printf("\n"); 664 665 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 666 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 667 668 RTW_DPRINTF(("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 669 670 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 671 672 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 673 *flags |= RTW_F_ANTDIV; 674 675 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 676 * to be reversed. 677 */ 678 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 679 *flags |= RTW_F_DIGPHY; 680 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 681 *flags |= RTW_F_DFLANTB; 682 683 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 684 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 685 686 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 687 switch (*rfchipid) { 688 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 689 rfname = "GCT GRF5101"; 690 paname = "Winspring WS9901"; 691 break; 692 case RTW_RFCHIPID_MAXIM: 693 rfname = "Maxim MAX2820"; /* guess */ 694 paname = "Maxim MAX2422"; /* guess */ 695 break; 696 case RTW_RFCHIPID_INTERSIL: 697 rfname = "Intersil HFA3873"; /* guess */ 698 paname = "Intersil <unknown>"; 699 break; 700 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 701 rfname = "Philips SA2400A"; 702 paname = "Philips SA2411"; 703 break; 704 case RTW_RFCHIPID_RFMD: 705 /* this is the same front-end as an atw(4)! */ 706 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 707 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 708 "SYN: Silicon Labs Si4126"; /* inferred from 709 * reference driver 710 */ 711 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 712 break; 713 case RTW_RFCHIPID_RESERVED: 714 rfname = paname = "reserved"; 715 break; 716 default: 717 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 718 rfname = paname = scratch; 719 } 720 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 721 722 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 723 case RTW_CONFIG0_GL_USA: 724 *locale = RTW_LOCALE_USA; 725 break; 726 case RTW_CONFIG0_GL_EUROPE: 727 *locale = RTW_LOCALE_EUROPE; 728 break; 729 case RTW_CONFIG0_GL_JAPAN: 730 *locale = RTW_LOCALE_JAPAN; 731 break; 732 default: 733 *locale = RTW_LOCALE_UNKNOWN; 734 break; 735 } 736 return 0; 737 } 738 739 /* Returns -1 on failure. */ 740 static int 741 rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr, 742 const char *dvname) 743 { 744 int rc; 745 struct seeprom_descriptor sd; 746 u_int8_t ecr; 747 748 (void)memset(&sd, 0, sizeof(sd)); 749 750 ecr = RTW_READ8(regs, RTW_9346CR); 751 752 if ((flags & RTW_F_9356SROM) != 0) { 753 RTW_DPRINTF(("%s: 93c56 SROM\n", dvname)); 754 sr->sr_size = 256; 755 sd.sd_chip = C56_66; 756 } else { 757 RTW_DPRINTF(("%s: 93c46 SROM\n", dvname)); 758 sr->sr_size = 128; 759 sd.sd_chip = C46; 760 } 761 762 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 763 RTW_9346CR_EEM_MASK); 764 ecr |= RTW_9346CR_EEM_PROGRAM; 765 766 RTW_WRITE8(regs, RTW_9346CR, ecr); 767 768 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 769 770 if (sr->sr_content == NULL) { 771 printf("%s: unable to allocate SROM buffer\n", dvname); 772 return ENOMEM; 773 } 774 775 (void)memset(sr->sr_content, 0, sr->sr_size); 776 777 /* RTL8180 has a single 8-bit register for controlling the 778 * 93cx6 SROM. There is no "ready" bit. The RTL8180 779 * input/output sense is the reverse of read_seeprom's. 780 */ 781 sd.sd_tag = regs->r_bt; 782 sd.sd_bsh = regs->r_bh; 783 sd.sd_regsize = 1; 784 sd.sd_control_offset = RTW_9346CR; 785 sd.sd_status_offset = RTW_9346CR; 786 sd.sd_dataout_offset = RTW_9346CR; 787 sd.sd_CK = RTW_9346CR_EESK; 788 sd.sd_CS = RTW_9346CR_EECS; 789 sd.sd_DI = RTW_9346CR_EEDO; 790 sd.sd_DO = RTW_9346CR_EEDI; 791 /* make read_seeprom enter EEPROM read/write mode */ 792 sd.sd_MS = ecr; 793 sd.sd_RDY = 0; 794 #if 0 795 sd.sd_clkdelay = 50; 796 #endif 797 798 /* TBD bus barriers */ 799 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 800 printf("%s: could not read SROM\n", dvname); 801 free(sr->sr_content, M_DEVBUF); 802 sr->sr_content = NULL; 803 return -1; /* XXX */ 804 } 805 806 /* end EEPROM read/write mode */ 807 RTW_WRITE8(regs, RTW_9346CR, 808 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 809 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 810 811 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 812 return rc; 813 814 #ifdef RTW_DEBUG 815 { 816 int i; 817 RTW_DPRINTF(("\n%s: serial ROM:\n\t", dvname)); 818 for (i = 0; i < sr->sr_size/2; i++) { 819 if (((i % 8) == 0) && (i != 0)) 820 RTW_DPRINTF(("\n\t")); 821 RTW_DPRINTF((" %04x", sr->sr_content[i])); 822 } 823 RTW_DPRINTF(("\n")); 824 } 825 #endif /* RTW_DEBUG */ 826 return 0; 827 } 828 829 static void 830 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 831 const char *dvname) 832 { 833 u_int8_t cfg4; 834 const char *method; 835 836 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 837 838 switch (rfchipid) { 839 default: 840 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 841 method = "fallback"; 842 break; 843 case RTW_RFCHIPID_INTERSIL: 844 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 845 method = "Intersil"; 846 break; 847 case RTW_RFCHIPID_PHILIPS: 848 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 849 method = "Philips"; 850 break; 851 case RTW_RFCHIPID_RFMD: 852 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 853 method = "RFMD"; 854 break; 855 } 856 857 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 858 859 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 860 861 RTW_DPRINTF(("%s: %s RF programming method, %#02x\n", dvname, method, 862 RTW_READ8(regs, RTW_CONFIG4))); 863 } 864 865 #if 0 866 static __inline int 867 rtw_identify_rf(struct rtw_regs *regs, enum rtw_rftype *rftype, 868 const char *dvname) 869 { 870 u_int8_t cfg4; 871 const char *name; 872 873 cfg4 = RTW_READ8(regs, RTW_CONFIG4); 874 875 switch (cfg4 & RTW_CONFIG4_RFTYPE_MASK) { 876 case RTW_CONFIG4_RFTYPE_PHILIPS: 877 *rftype = RTW_RFTYPE_PHILIPS; 878 name = "Philips"; 879 break; 880 case RTW_CONFIG4_RFTYPE_INTERSIL: 881 *rftype = RTW_RFTYPE_INTERSIL; 882 name = "Intersil"; 883 break; 884 case RTW_CONFIG4_RFTYPE_RFMD: 885 *rftype = RTW_RFTYPE_RFMD; 886 name = "RFMD"; 887 break; 888 default: 889 name = "<unknown>"; 890 return ENXIO; 891 } 892 893 printf("%s: RF prog type %s\n", dvname, name); 894 return 0; 895 } 896 #endif 897 898 static __inline void 899 rtw_init_channels(enum rtw_locale locale, 900 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 901 const char *dvname) 902 { 903 int i; 904 const char *name = NULL; 905 #define ADD_CHANNEL(_chans, _chan) do { \ 906 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 907 (*_chans)[_chan].ic_freq = \ 908 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 909 } while (0) 910 911 switch (locale) { 912 case RTW_LOCALE_USA: /* 1-11 */ 913 name = "USA"; 914 for (i = 1; i <= 11; i++) 915 ADD_CHANNEL(chans, i); 916 break; 917 case RTW_LOCALE_JAPAN: /* 1-14 */ 918 name = "Japan"; 919 ADD_CHANNEL(chans, 14); 920 for (i = 1; i <= 14; i++) 921 ADD_CHANNEL(chans, i); 922 break; 923 case RTW_LOCALE_EUROPE: /* 1-13 */ 924 name = "Europe"; 925 for (i = 1; i <= 13; i++) 926 ADD_CHANNEL(chans, i); 927 break; 928 default: /* 10-11 allowed by most countries */ 929 name = "<unknown>"; 930 for (i = 10; i <= 11; i++) 931 ADD_CHANNEL(chans, i); 932 break; 933 } 934 printf("%s: Geographic Location %s\n", dvname, name); 935 #undef ADD_CHANNEL 936 } 937 938 static __inline void 939 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 940 const char *dvname) 941 { 942 u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 943 944 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 945 case RTW_CONFIG0_GL_USA: 946 *locale = RTW_LOCALE_USA; 947 break; 948 case RTW_CONFIG0_GL_JAPAN: 949 *locale = RTW_LOCALE_JAPAN; 950 break; 951 case RTW_CONFIG0_GL_EUROPE: 952 *locale = RTW_LOCALE_EUROPE; 953 break; 954 default: 955 *locale = RTW_LOCALE_UNKNOWN; 956 break; 957 } 958 } 959 960 static __inline int 961 rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN], 962 const char *dvname) 963 { 964 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 966 }; 967 u_int32_t idr0 = RTW_READ(regs, RTW_IDR0), 968 idr1 = RTW_READ(regs, RTW_IDR1); 969 970 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 971 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 972 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 973 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 974 975 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 976 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 977 978 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 979 printf("%s: could not get mac address, attach failed\n", 980 dvname); 981 return ENXIO; 982 } 983 984 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 985 986 return 0; 987 } 988 989 static u_int8_t 990 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 991 struct ieee80211_channel *chan) 992 { 993 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 994 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 995 ("%s: channel %d out of range", __func__, 996 idx - RTW_SR_TXPOWER1 + 1)); 997 return RTW_SR_GET(sr, idx); 998 } 999 1000 static void 1001 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *htcs) 1002 { 1003 int pri; 1004 u_int ndesc[RTW_NTXPRI] = 1005 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 1006 1007 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1008 htcs[pri].htc_nfree = ndesc[pri]; 1009 htcs[pri].htc_next = 0; 1010 } 1011 } 1012 1013 static int 1014 rtw_txctl_blk_init(struct rtw_txctl_blk *stc) 1015 { 1016 int i; 1017 struct rtw_txctl *stx; 1018 1019 SIMPLEQ_INIT(&stc->stc_dirtyq); 1020 SIMPLEQ_INIT(&stc->stc_freeq); 1021 for (i = 0; i < stc->stc_ndesc; i++) { 1022 stx = &stc->stc_desc[i]; 1023 stx->stx_mbuf = NULL; 1024 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1025 } 1026 return 0; 1027 } 1028 1029 static void 1030 rtw_txctl_blk_init_all(struct rtw_txctl_blk *stcs) 1031 { 1032 int pri; 1033 for (pri = 0; pri < RTW_NTXPRI; pri++) 1034 rtw_txctl_blk_init(&stcs[pri]); 1035 } 1036 1037 static __inline void 1038 rtw_rxdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, u_int desc0, u_int 1039 nsync, int ops) 1040 { 1041 /* sync to end of ring */ 1042 if (desc0 + nsync > RTW_NRXDESC) { 1043 bus_dmamap_sync(dmat, dmap, 1044 offsetof(struct rtw_descs, hd_rx[desc0]), 1045 sizeof(struct rtw_rxdesc) * (RTW_NRXDESC - desc0), ops); 1046 nsync -= (RTW_NRXDESC - desc0); 1047 desc0 = 0; 1048 } 1049 1050 /* sync what remains */ 1051 bus_dmamap_sync(dmat, dmap, 1052 offsetof(struct rtw_descs, hd_rx[desc0]), 1053 sizeof(struct rtw_rxdesc) * nsync, ops); 1054 } 1055 1056 static void 1057 rtw_txdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1058 struct rtw_txdesc_blk *htc, u_int desc0, u_int nsync, int ops) 1059 { 1060 /* sync to end of ring */ 1061 if (desc0 + nsync > htc->htc_ndesc) { 1062 bus_dmamap_sync(dmat, dmap, 1063 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1064 sizeof(struct rtw_txdesc) * (htc->htc_ndesc - desc0), 1065 ops); 1066 nsync -= (htc->htc_ndesc - desc0); 1067 desc0 = 0; 1068 } 1069 1070 /* sync what remains */ 1071 bus_dmamap_sync(dmat, dmap, 1072 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1073 sizeof(struct rtw_txdesc) * nsync, ops); 1074 } 1075 1076 static void 1077 rtw_txdescs_sync_all(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1078 struct rtw_txdesc_blk *htcs) 1079 { 1080 int pri; 1081 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1082 rtw_txdescs_sync(dmat, dmap, 1083 &htcs[pri], 0, htcs[pri].htc_ndesc, 1084 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1085 } 1086 } 1087 1088 static void 1089 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxctl *desc) 1090 { 1091 int i; 1092 struct rtw_rxctl *srx; 1093 1094 for (i = 0; i < RTW_NRXDESC; i++) { 1095 srx = &desc[i]; 1096 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, 1097 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1098 bus_dmamap_unload(dmat, srx->srx_dmamap); 1099 m_freem(srx->srx_mbuf); 1100 srx->srx_mbuf = NULL; 1101 } 1102 } 1103 1104 static __inline int 1105 rtw_rxbuf_alloc(bus_dma_tag_t dmat, struct rtw_rxctl *srx) 1106 { 1107 int rc; 1108 struct mbuf *m; 1109 1110 MGETHDR(m, M_DONTWAIT, MT_DATA); 1111 if (m == NULL) 1112 return ENOMEM; 1113 1114 MCLGET(m, M_DONTWAIT); 1115 if (m == NULL) 1116 return ENOMEM; 1117 1118 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1119 1120 rc = bus_dmamap_load_mbuf(dmat, srx->srx_dmamap, m, BUS_DMA_NOWAIT); 1121 if (rc != 0) 1122 return rc; 1123 1124 srx->srx_mbuf = m; 1125 1126 return 0; 1127 } 1128 1129 static int 1130 rtw_rxctl_init_all(bus_dma_tag_t dmat, struct rtw_rxctl *desc, 1131 u_int *next, const char *dvname) 1132 { 1133 int i, rc; 1134 struct rtw_rxctl *srx; 1135 1136 for (i = 0; i < RTW_NRXDESC; i++) { 1137 srx = &desc[i]; 1138 if ((rc = rtw_rxbuf_alloc(dmat, srx)) == 0) 1139 continue; 1140 printf("%s: failed rtw_rxbuf_alloc after %d buffers, rc = %d\n", 1141 dvname, i, rc); 1142 if (i == 0) { 1143 rtw_rxbufs_release(dmat, desc); 1144 return rc; 1145 } 1146 } 1147 *next = 0; 1148 return 0; 1149 } 1150 1151 static __inline void 1152 rtw_rxdesc_init(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1153 struct rtw_rxdesc *hrx, struct rtw_rxctl *srx, int idx) 1154 { 1155 int is_last = (idx == RTW_NRXDESC - 1); 1156 uint32_t ctl; 1157 1158 hrx->hrx_buf = htole32(srx->srx_dmamap->dm_segs[0].ds_addr); 1159 1160 ctl = LSHIFT(srx->srx_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1161 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1162 1163 if (is_last) 1164 ctl |= RTW_RXCTL_EOR; 1165 1166 hrx->hrx_ctl = htole32(ctl); 1167 1168 /* sync the mbuf */ 1169 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, srx->srx_dmamap->dm_mapsize, 1170 BUS_DMASYNC_PREREAD); 1171 1172 /* sync the descriptor */ 1173 bus_dmamap_sync(dmat, dmam, RTW_DESC_OFFSET(hd_rx, idx), 1174 sizeof(struct rtw_rxdesc), 1175 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1176 } 1177 1178 static void 1179 rtw_rxdesc_init_all(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1180 struct rtw_rxdesc *desc, struct rtw_rxctl *ctl) 1181 { 1182 int i; 1183 struct rtw_rxdesc *hrx; 1184 struct rtw_rxctl *srx; 1185 1186 for (i = 0; i < RTW_NRXDESC; i++) { 1187 hrx = &desc[i]; 1188 srx = &ctl[i]; 1189 rtw_rxdesc_init(dmat, dmam, hrx, srx, i); 1190 } 1191 } 1192 1193 static void 1194 rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable) 1195 { 1196 u_int8_t cr; 1197 1198 RTW_DPRINTF(("%s: %s 0x%02x\n", __func__, 1199 enable ? "enable" : "disable", flags)); 1200 1201 cr = RTW_READ8(regs, RTW_CR); 1202 1203 /* XXX reference source does not enable MULRW */ 1204 #if 0 1205 /* enable PCI Read/Write Multiple */ 1206 cr |= RTW_CR_MULRW; 1207 #endif 1208 1209 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1210 if (enable) 1211 cr |= flags; 1212 else 1213 cr &= ~flags; 1214 RTW_WRITE8(regs, RTW_CR, cr); 1215 RTW_SYNC(regs, RTW_CR, RTW_CR); 1216 } 1217 1218 static void 1219 rtw_intr_rx(struct rtw_softc *sc, u_int16_t isr) 1220 { 1221 u_int next; 1222 int rate, rssi; 1223 u_int32_t hrssi, hstat, htsfth, htsftl; 1224 struct rtw_rxdesc *hrx; 1225 struct rtw_rxctl *srx; 1226 struct mbuf *m; 1227 1228 struct ieee80211_node *ni; 1229 struct ieee80211_frame *wh; 1230 1231 for (next = sc->sc_rxnext; ; next = (next + 1) % RTW_RXQLEN) { 1232 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1233 next, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1234 hrx = &sc->sc_rxdesc[next]; 1235 srx = &sc->sc_rxctl[next]; 1236 1237 hstat = le32toh(hrx->hrx_stat); 1238 hrssi = le32toh(hrx->hrx_rssi); 1239 htsfth = le32toh(hrx->hrx_tsfth); 1240 htsftl = le32toh(hrx->hrx_tsftl); 1241 1242 RTW_DPRINTF2(("%s: rxdesc[%d] hstat %08x hrssi %08x " 1243 "htsft %08x%08x\n", __func__, next, 1244 hstat, hrssi, htsfth, htsftl)); 1245 1246 if ((hstat & RTW_RXSTAT_OWN) != 0) /* belongs to NIC */ 1247 break; 1248 1249 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1250 printf("%s: DMA error/FIFO overflow %08x, " 1251 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1252 hstat & RTW_RXSTAT_IOERROR, next); 1253 goto next; 1254 } 1255 1256 switch (hstat & RTW_RXSTAT_RATE_MASK) { 1257 case RTW_RXSTAT_RATE_1MBPS: 1258 rate = 2; 1259 break; 1260 case RTW_RXSTAT_RATE_2MBPS: 1261 rate = 4; 1262 break; 1263 case RTW_RXSTAT_RATE_5MBPS: 1264 rate = 11; 1265 break; 1266 default: 1267 #ifdef RTW_DEBUG 1268 if (rtw_debug > 1) 1269 printf("%s: interpreting rate #%d as 11 MB/s\n", 1270 sc->sc_dev.dv_xname, 1271 MASK_AND_RSHIFT(hstat, 1272 RTW_RXSTAT_RATE_MASK)); 1273 #endif /* RTW_DEBUG */ 1274 /*FALLTHROUGH*/ 1275 case RTW_RXSTAT_RATE_11MBPS: 1276 rate = 22; 1277 break; 1278 } 1279 1280 #ifdef RTW_DEBUG 1281 #define PRINTSTAT(flag) do { \ 1282 if ((hstat & flag) != 0) { \ 1283 printf("%s" #flag, delim); \ 1284 delim = ","; \ 1285 } \ 1286 } while (0) 1287 if (rtw_debug > 1) { 1288 const char *delim = "<"; 1289 printf("%s: ", sc->sc_dev.dv_xname); 1290 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1291 printf("status %08x", hstat); 1292 PRINTSTAT(RTW_RXSTAT_SPLCP); 1293 PRINTSTAT(RTW_RXSTAT_MAR); 1294 PRINTSTAT(RTW_RXSTAT_PAR); 1295 PRINTSTAT(RTW_RXSTAT_BAR); 1296 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1297 PRINTSTAT(RTW_RXSTAT_CRC32); 1298 PRINTSTAT(RTW_RXSTAT_ICV); 1299 printf(">, "); 1300 } 1301 printf("rate %d.%d Mb/s, time %08x%08x\n", 1302 (rate * 5) / 10, (rate * 5) % 10, htsfth, htsftl); 1303 } 1304 #endif /* RTW_DEBUG */ 1305 1306 if ((hstat & RTW_RXSTAT_RES) != 0 && 1307 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1308 goto next; 1309 1310 /* if bad flags, skip descriptor */ 1311 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1312 printf("%s: too many rx segments\n", 1313 sc->sc_dev.dv_xname); 1314 goto next; 1315 } 1316 1317 m = srx->srx_mbuf; 1318 1319 /* if temporarily out of memory, re-use mbuf */ 1320 if (rtw_rxbuf_alloc(sc->sc_dmat, srx) != 0) { 1321 printf("%s: rtw_rxbuf_alloc(, %d) failed, " 1322 "dropping this packet\n", sc->sc_dev.dv_xname, 1323 next); 1324 goto next; 1325 } 1326 1327 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1328 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1329 else { 1330 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1331 /* TBD find out each front-end's LNA gain in the 1332 * front-end's units 1333 */ 1334 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1335 rssi |= 0x80; 1336 } 1337 1338 m->m_pkthdr.len = m->m_len = 1339 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1340 m->m_flags |= M_HASFCS; 1341 1342 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 1343 sc->sc_ic.ic_stats.is_rx_tooshort++; 1344 goto next; 1345 } 1346 wh = mtod(m, struct ieee80211_frame *); 1347 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1348 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1349 1350 sc->sc_tsfth = htsfth; 1351 1352 #ifdef RTW_DEBUG 1353 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 1354 (IFF_DEBUG|IFF_LINK2)) { 1355 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1356 rate, rssi); 1357 } 1358 #endif /* RTW_DEBUG */ 1359 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1360 ieee80211_release_node(&sc->sc_ic, ni); 1361 next: 1362 rtw_rxdesc_init(sc->sc_dmat, sc->sc_desc_dmamap, 1363 hrx, srx, next); 1364 } 1365 sc->sc_rxnext = next; 1366 1367 return; 1368 } 1369 1370 static void 1371 rtw_txbuf_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1372 struct rtw_txctl *stx) 1373 { 1374 struct mbuf *m; 1375 struct ieee80211_node *ni; 1376 bus_dmamap_t dmamap; 1377 1378 dmamap = stx->stx_dmamap; 1379 m = stx->stx_mbuf; 1380 ni = stx->stx_ni; 1381 stx->stx_dmamap = NULL; 1382 stx->stx_mbuf = NULL; 1383 stx->stx_ni = NULL; 1384 1385 bus_dmamap_sync(dmat, dmamap, 0, dmamap->dm_mapsize, 1386 BUS_DMASYNC_POSTWRITE); 1387 bus_dmamap_unload(dmat, dmamap); 1388 m_freem(m); 1389 ieee80211_release_node(ic, ni); 1390 } 1391 1392 static void 1393 rtw_txbufs_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1394 struct rtw_txctl_blk *stc) 1395 { 1396 struct rtw_txctl *stx; 1397 1398 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1399 rtw_txbuf_release(dmat, ic, stx); 1400 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1401 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1402 } 1403 } 1404 1405 static __inline void 1406 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *htc, 1407 struct rtw_txctl *stx, int ndesc) 1408 { 1409 uint32_t hstat; 1410 int data_retry, rts_retry; 1411 struct rtw_txdesc *htx0, *htxn; 1412 const char *condstring; 1413 1414 rtw_txbuf_release(sc->sc_dmat, &sc->sc_ic, stx); 1415 1416 htc->htc_nfree += ndesc; 1417 1418 htx0 = &htc->htc_desc[stx->stx_first]; 1419 htxn = &htc->htc_desc[stx->stx_last]; 1420 1421 hstat = le32toh(htx0->htx_stat); 1422 rts_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1423 data_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_DRC_MASK); 1424 1425 sc->sc_if.if_collisions += rts_retry + data_retry; 1426 1427 if ((hstat & RTW_TXSTAT_TOK) != 0) 1428 condstring = "ok"; 1429 else { 1430 sc->sc_if.if_oerrors++; 1431 condstring = "error"; 1432 } 1433 1434 DPRINTF2(sc, ("%s: stx %p txdesc[%d, %d] %s tries rts %u data %u\n", 1435 sc->sc_dev.dv_xname, stx, stx->stx_first, stx->stx_last, 1436 condstring, rts_retry, data_retry)); 1437 } 1438 1439 /* Collect transmitted packets. */ 1440 static __inline void 1441 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txctl_blk *stc, 1442 struct rtw_txdesc_blk *htc) 1443 { 1444 int ndesc; 1445 struct rtw_txctl *stx; 1446 1447 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1448 ndesc = 1 + stx->stx_last - stx->stx_first; 1449 if (stx->stx_last < stx->stx_first) 1450 ndesc += htc->htc_ndesc; 1451 1452 KASSERT(ndesc > 0); 1453 1454 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, htc, 1455 stx->stx_first, ndesc, 1456 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1457 1458 if ((htc->htc_desc[stx->stx_first].htx_stat & 1459 htole32(RTW_TXSTAT_OWN)) != 0) 1460 break; 1461 1462 rtw_collect_txpkt(sc, htc, stx, ndesc); 1463 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1464 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1465 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1466 } 1467 if (stx == NULL) 1468 stc->stc_tx_timer = 0; 1469 } 1470 1471 static void 1472 rtw_intr_tx(struct rtw_softc *sc, u_int16_t isr) 1473 { 1474 int pri; 1475 struct rtw_txctl_blk *stc; 1476 struct rtw_txdesc_blk *htc; 1477 1478 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1479 stc = &sc->sc_txctl_blk[pri]; 1480 htc = &sc->sc_txdesc_blk[pri]; 1481 1482 rtw_collect_txring(sc, stc, htc); 1483 1484 rtw_start(&sc->sc_if); 1485 } 1486 1487 /* TBD */ 1488 return; 1489 } 1490 1491 static void 1492 rtw_intr_beacon(struct rtw_softc *sc, u_int16_t isr) 1493 { 1494 /* TBD */ 1495 return; 1496 } 1497 1498 static void 1499 rtw_intr_atim(struct rtw_softc *sc) 1500 { 1501 /* TBD */ 1502 return; 1503 } 1504 1505 static void 1506 rtw_hwring_setup(struct rtw_softc *sc) 1507 { 1508 struct rtw_regs *regs = &sc->sc_regs; 1509 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1510 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1511 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1512 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1513 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1514 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1515 } 1516 1517 static void 1518 rtw_swring_setup(struct rtw_softc *sc) 1519 { 1520 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1521 1522 rtw_txctl_blk_init_all(&sc->sc_txctl_blk[0]); 1523 1524 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1525 0, RTW_NRXDESC, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1526 rtw_rxctl_init_all(sc->sc_dmat, sc->sc_rxctl, &sc->sc_rxnext, 1527 sc->sc_dev.dv_xname); 1528 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, 1529 sc->sc_rxdesc, sc->sc_rxctl); 1530 1531 rtw_txdescs_sync_all(sc->sc_dmat, sc->sc_desc_dmamap, 1532 &sc->sc_txdesc_blk[0]); 1533 #if 0 /* redundant with rtw_rxdesc_init_all */ 1534 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1535 0, RTW_NRXDESC, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1536 #endif 1537 } 1538 1539 static void 1540 rtw_kick(struct rtw_softc *sc) 1541 { 1542 int pri; 1543 struct rtw_regs *regs = &sc->sc_regs; 1544 1545 RTW_WRITE16(regs, RTW_IMR, 0); 1546 RTW_WBW(regs, RTW_IMR, RTW_TPPOLL); 1547 1548 RTW_WRITE8(regs, RTW_TPPOLL, 1549 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ|RTW_TPPOLL_SLPQ); 1550 1551 RTW_SYNC(regs, RTW_TPPOLL, RTW_TPPOLL); 1552 1553 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1554 1555 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1556 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1557 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1558 &sc->sc_txctl_blk[pri]); 1559 } 1560 rtw_swring_setup(sc); 1561 rtw_hwring_setup(sc); 1562 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1563 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1564 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1565 } 1566 1567 static void 1568 rtw_intr_ioerror(struct rtw_softc *sc, u_int16_t isr) 1569 { 1570 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) 1571 rtw_kick(sc); 1572 if ((isr & RTW_INTR_TXFOVW) != 0) 1573 ; /* TBD restart transmit engine */ 1574 return; 1575 } 1576 1577 static __inline void 1578 rtw_suspend_ticks(struct rtw_softc *sc) 1579 { 1580 RTW_DPRINTF2(("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 1581 sc->sc_do_tick = 0; 1582 } 1583 1584 static __inline void 1585 rtw_resume_ticks(struct rtw_softc *sc) 1586 { 1587 u_int32_t tsftrl0, tsftrl1, next_tick; 1588 1589 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1590 1591 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1592 next_tick = tsftrl1 + 1000000; 1593 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1594 1595 sc->sc_do_tick = 1; 1596 1597 RTW_DPRINTF2(("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1598 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 1599 } 1600 1601 static void 1602 rtw_intr_timeout(struct rtw_softc *sc) 1603 { 1604 RTW_DPRINTF2(("%s: timeout\n", sc->sc_dev.dv_xname)); 1605 if (sc->sc_do_tick) 1606 rtw_resume_ticks(sc); 1607 return; 1608 } 1609 1610 int 1611 rtw_intr(void *arg) 1612 { 1613 int i; 1614 struct rtw_softc *sc = arg; 1615 struct rtw_regs *regs = &sc->sc_regs; 1616 u_int16_t isr; 1617 1618 /* 1619 * If the interface isn't running, the interrupt couldn't 1620 * possibly have come from us. 1621 */ 1622 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1623 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1624 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1625 RTW_DPRINTF2(("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1626 return (0); 1627 } 1628 1629 for (i = 0; i < 10; i++) { 1630 isr = RTW_READ16(regs, RTW_ISR); 1631 1632 RTW_WRITE16(regs, RTW_ISR, isr); 1633 RTW_WBR(regs, RTW_ISR, RTW_ISR); 1634 1635 if (sc->sc_intr_ack != NULL) 1636 (*sc->sc_intr_ack)(regs); 1637 1638 if (isr == 0) 1639 break; 1640 1641 #ifdef RTW_DEBUG 1642 #define PRINTINTR(flag) do { \ 1643 if ((isr & flag) != 0) { \ 1644 printf("%s" #flag, delim); \ 1645 delim = ","; \ 1646 } \ 1647 } while (0) 1648 1649 if (rtw_debug > 1 && isr != 0) { 1650 const char *delim = "<"; 1651 1652 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1653 1654 PRINTINTR(RTW_INTR_TXFOVW); 1655 PRINTINTR(RTW_INTR_TIMEOUT); 1656 PRINTINTR(RTW_INTR_BCNINT); 1657 PRINTINTR(RTW_INTR_ATIMINT); 1658 PRINTINTR(RTW_INTR_TBDER); 1659 PRINTINTR(RTW_INTR_TBDOK); 1660 PRINTINTR(RTW_INTR_THPDER); 1661 PRINTINTR(RTW_INTR_THPDOK); 1662 PRINTINTR(RTW_INTR_TNPDER); 1663 PRINTINTR(RTW_INTR_TNPDOK); 1664 PRINTINTR(RTW_INTR_RXFOVW); 1665 PRINTINTR(RTW_INTR_RDU); 1666 PRINTINTR(RTW_INTR_TLPDER); 1667 PRINTINTR(RTW_INTR_TLPDOK); 1668 PRINTINTR(RTW_INTR_RER); 1669 PRINTINTR(RTW_INTR_ROK); 1670 1671 printf(">\n"); 1672 } 1673 #undef PRINTINTR 1674 #endif /* RTW_DEBUG */ 1675 1676 if ((isr & RTW_INTR_RX) != 0) 1677 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1678 if ((isr & RTW_INTR_TX) != 0) 1679 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1680 if ((isr & RTW_INTR_BEACON) != 0) 1681 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1682 if ((isr & RTW_INTR_ATIMINT) != 0) 1683 rtw_intr_atim(sc); 1684 if ((isr & RTW_INTR_IOERROR) != 0) 1685 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1686 if ((isr & RTW_INTR_TIMEOUT) != 0) 1687 rtw_intr_timeout(sc); 1688 } 1689 1690 return 1; 1691 } 1692 1693 static void 1694 rtw_stop(struct ifnet *ifp, int disable) 1695 { 1696 int pri, s; 1697 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1698 struct ieee80211com *ic = &sc->sc_ic; 1699 struct rtw_regs *regs = &sc->sc_regs; 1700 1701 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1702 return; 1703 1704 rtw_suspend_ticks(sc); 1705 1706 s = splnet(); 1707 1708 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1709 1710 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1711 /* Disable interrupts. */ 1712 RTW_WRITE16(regs, RTW_IMR, 0); 1713 1714 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 1715 1716 /* Stop the transmit and receive processes. First stop DMA, 1717 * then disable receiver and transmitter. 1718 */ 1719 RTW_WRITE8(regs, RTW_TPPOLL, 1720 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ| 1721 RTW_TPPOLL_SLPQ); 1722 1723 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 1724 1725 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1726 } 1727 1728 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1729 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1730 &sc->sc_txctl_blk[pri]); 1731 } 1732 1733 if (disable) { 1734 rtw_disable(sc); 1735 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1736 } 1737 1738 /* Mark the interface as not running. Cancel the watchdog timer. */ 1739 ifp->if_flags &= ~IFF_RUNNING; 1740 ifp->if_timer = 0; 1741 1742 splx(s); 1743 1744 return; 1745 } 1746 1747 const char * 1748 rtw_pwrstate_string(enum rtw_pwrstate power) 1749 { 1750 switch (power) { 1751 case RTW_ON: 1752 return "on"; 1753 case RTW_SLEEP: 1754 return "sleep"; 1755 case RTW_OFF: 1756 return "off"; 1757 default: 1758 return "unknown"; 1759 } 1760 } 1761 1762 /* XXX For Maxim, I am using the RFMD settings gleaned from the 1763 * reference driver, plus a magic Maxim "ON" value that comes from 1764 * the Realtek document "Windows PG for Rtl8180." 1765 */ 1766 static void 1767 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1768 int before_rf, int digphy) 1769 { 1770 u_int32_t anaparm; 1771 1772 anaparm = RTW_READ(regs, RTW_ANAPARM); 1773 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1774 1775 switch (power) { 1776 case RTW_OFF: 1777 if (before_rf) 1778 return; 1779 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 1780 anaparm |= RTW_ANAPARM_TXDACOFF; 1781 break; 1782 case RTW_SLEEP: 1783 if (!before_rf) 1784 return; 1785 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 1786 anaparm |= RTW_ANAPARM_TXDACOFF; 1787 break; 1788 case RTW_ON: 1789 if (!before_rf) 1790 return; 1791 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 1792 break; 1793 } 1794 RTW_DPRINTF(("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 1795 __func__, rtw_pwrstate_string(power), 1796 (before_rf) ? "before" : "after", anaparm)); 1797 1798 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1799 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1800 } 1801 1802 /* XXX I am using the RFMD settings gleaned from the reference 1803 * driver. They agree 1804 */ 1805 static void 1806 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1807 int before_rf, int digphy) 1808 { 1809 u_int32_t anaparm; 1810 1811 anaparm = RTW_READ(regs, RTW_ANAPARM); 1812 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1813 1814 switch (power) { 1815 case RTW_OFF: 1816 if (before_rf) 1817 return; 1818 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 1819 anaparm |= RTW_ANAPARM_TXDACOFF; 1820 break; 1821 case RTW_SLEEP: 1822 if (!before_rf) 1823 return; 1824 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 1825 anaparm |= RTW_ANAPARM_TXDACOFF; 1826 break; 1827 case RTW_ON: 1828 if (!before_rf) 1829 return; 1830 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 1831 break; 1832 } 1833 RTW_DPRINTF(("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 1834 __func__, rtw_pwrstate_string(power), 1835 (before_rf) ? "before" : "after", anaparm)); 1836 1837 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1838 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1839 } 1840 1841 static void 1842 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1843 int before_rf, int digphy) 1844 { 1845 u_int32_t anaparm; 1846 1847 anaparm = RTW_READ(regs, RTW_ANAPARM); 1848 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1849 1850 switch (power) { 1851 case RTW_OFF: 1852 if (before_rf) 1853 return; 1854 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 1855 anaparm |= RTW_ANAPARM_TXDACOFF; 1856 break; 1857 case RTW_SLEEP: 1858 if (!before_rf) 1859 return; 1860 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 1861 anaparm |= RTW_ANAPARM_TXDACOFF; 1862 break; 1863 case RTW_ON: 1864 if (!before_rf) 1865 return; 1866 if (digphy) { 1867 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 1868 /* XXX guess */ 1869 anaparm |= RTW_ANAPARM_TXDACOFF; 1870 } else 1871 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 1872 break; 1873 } 1874 RTW_DPRINTF(("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 1875 __func__, rtw_pwrstate_string(power), 1876 (before_rf) ? "before" : "after", anaparm)); 1877 1878 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1879 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1880 } 1881 1882 static void 1883 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 1884 int digphy) 1885 { 1886 struct rtw_regs *regs = &sc->sc_regs; 1887 1888 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 1889 1890 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 1891 1892 rtw_set_access(sc, RTW_ACCESS_NONE); 1893 1894 return; 1895 } 1896 1897 static int 1898 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 1899 { 1900 int rc; 1901 1902 RTW_DPRINTF2(("%s: %s->%s\n", __func__, 1903 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 1904 1905 if (sc->sc_pwrstate == power) 1906 return 0; 1907 1908 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 1909 rc = rtw_rf_pwrstate(sc->sc_rf, power); 1910 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 1911 1912 switch (power) { 1913 case RTW_ON: 1914 /* TBD set LEDs */ 1915 break; 1916 case RTW_SLEEP: 1917 /* TBD */ 1918 break; 1919 case RTW_OFF: 1920 /* TBD */ 1921 break; 1922 } 1923 if (rc == 0) 1924 sc->sc_pwrstate = power; 1925 else 1926 sc->sc_pwrstate = RTW_OFF; 1927 return rc; 1928 } 1929 1930 static int 1931 rtw_tune(struct rtw_softc *sc) 1932 { 1933 struct ieee80211com *ic = &sc->sc_ic; 1934 u_int chan; 1935 int rc; 1936 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 1937 dflantb = sc->sc_flags & RTW_F_DFLANTB; 1938 1939 KASSERT(ic->ic_bss->ni_chan != NULL); 1940 1941 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1942 if (chan == IEEE80211_CHAN_ANY) 1943 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1944 1945 if (chan == sc->sc_cur_chan) { 1946 RTW_DPRINTF(("%s: already tuned chan #%d\n", __func__, chan)); 1947 return 0; 1948 } 1949 1950 rtw_suspend_ticks(sc); 1951 1952 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 1953 1954 /* TBD wait for Tx to complete */ 1955 1956 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 1957 1958 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 1959 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 1960 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 1961 dflantb, RTW_ON)) != 0) { 1962 /* XXX condition on powersaving */ 1963 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 1964 } 1965 1966 sc->sc_cur_chan = chan; 1967 1968 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 1969 1970 rtw_resume_ticks(sc); 1971 1972 return rc; 1973 } 1974 1975 void 1976 rtw_disable(struct rtw_softc *sc) 1977 { 1978 int rc; 1979 1980 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1981 return; 1982 1983 /* turn off PHY */ 1984 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 1985 printf("%s: failed to turn off PHY (%d)\n", 1986 sc->sc_dev.dv_xname, rc); 1987 1988 if (sc->sc_disable != NULL) 1989 (*sc->sc_disable)(sc); 1990 1991 sc->sc_flags &= ~RTW_F_ENABLED; 1992 } 1993 1994 int 1995 rtw_enable(struct rtw_softc *sc) 1996 { 1997 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 1998 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 1999 printf("%s: device enable failed\n", 2000 sc->sc_dev.dv_xname); 2001 return (EIO); 2002 } 2003 sc->sc_flags |= RTW_F_ENABLED; 2004 } 2005 return (0); 2006 } 2007 2008 static void 2009 rtw_transmit_config(struct rtw_regs *regs) 2010 { 2011 u_int32_t tcr; 2012 2013 tcr = RTW_READ(regs, RTW_TCR); 2014 2015 tcr |= RTW_TCR_CWMIN; 2016 tcr &= ~RTW_TCR_MXDMA_MASK; 2017 tcr |= RTW_TCR_MXDMA_256; 2018 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2019 tcr &= ~RTW_TCR_LBK_MASK; 2020 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2021 2022 /* set short/long retry limits */ 2023 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2024 tcr |= LSHIFT(4, RTW_TCR_SRL_MASK) | LSHIFT(4, RTW_TCR_LRL_MASK); 2025 2026 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2027 2028 RTW_WRITE(regs, RTW_TCR, tcr); 2029 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2030 } 2031 2032 static __inline void 2033 rtw_enable_interrupts(struct rtw_softc *sc) 2034 { 2035 struct rtw_regs *regs = &sc->sc_regs; 2036 2037 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2038 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2039 2040 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2041 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2042 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2043 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2044 2045 /* XXX necessary? */ 2046 if (sc->sc_intr_ack != NULL) 2047 (*sc->sc_intr_ack)(regs); 2048 } 2049 2050 static void 2051 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2052 { 2053 uint8_t msr; 2054 2055 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2056 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2057 2058 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2059 2060 switch (opmode) { 2061 case IEEE80211_M_AHDEMO: 2062 case IEEE80211_M_IBSS: 2063 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2064 break; 2065 case IEEE80211_M_HOSTAP: 2066 msr |= RTW_MSR_NETYPE_AP_OK; 2067 break; 2068 case IEEE80211_M_MONITOR: 2069 /* XXX */ 2070 msr |= RTW_MSR_NETYPE_NOLINK; 2071 break; 2072 case IEEE80211_M_STA: 2073 msr |= RTW_MSR_NETYPE_INFRA_OK; 2074 break; 2075 } 2076 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2077 2078 rtw_set_access(sc, RTW_ACCESS_NONE); 2079 } 2080 2081 /* XXX is the endianness correct? test. */ 2082 #define rtw_calchash(addr) \ 2083 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 2084 2085 static void 2086 rtw_pktfilt_load(struct rtw_softc *sc) 2087 { 2088 struct rtw_regs *regs = &sc->sc_regs; 2089 struct ieee80211com *ic = &sc->sc_ic; 2090 struct ethercom *ec = &ic->ic_ec; 2091 struct ifnet *ifp = &sc->sc_ic.ic_if; 2092 int hash; 2093 u_int32_t hashes[2] = { 0, 0 }; 2094 struct ether_multi *enm; 2095 struct ether_multistep step; 2096 2097 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2098 2099 #define RTW_RCR_MONITOR (RTW_RCR_ACRC32|RTW_RCR_APM|RTW_RCR_AAP|RTW_RCR_AB|RTW_RCR_ACF | RTW_RCR_AICV | RTW_RCR_ACRC32) 2100 2101 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2102 sc->sc_rcr |= RTW_RCR_MONITOR; 2103 else 2104 sc->sc_rcr &= ~RTW_RCR_MONITOR; 2105 2106 /* XXX reference sources BEGIN */ 2107 sc->sc_rcr |= RTW_RCR_ENMARP; 2108 sc->sc_rcr |= RTW_RCR_AB | RTW_RCR_AM | RTW_RCR_APM; 2109 #if 0 2110 /* receive broadcasts in our BSS */ 2111 sc->sc_rcr |= RTW_RCR_ADD3; 2112 #endif 2113 /* XXX reference sources END */ 2114 2115 /* receive pwrmgmt frames. */ 2116 sc->sc_rcr |= RTW_RCR_APWRMGT; 2117 /* receive mgmt/ctrl/data frames. */ 2118 sc->sc_rcr |= RTW_RCR_ADF | RTW_RCR_AMF; 2119 /* initialize Rx DMA threshold, Tx DMA burst size */ 2120 sc->sc_rcr |= RTW_RCR_RXFTH_WHOLE | RTW_RCR_MXDMA_1024; 2121 2122 ifp->if_flags &= ~IFF_ALLMULTI; 2123 2124 if (ifp->if_flags & IFF_PROMISC) { 2125 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2126 allmulti: 2127 ifp->if_flags |= IFF_ALLMULTI; 2128 goto setit; 2129 } 2130 2131 /* 2132 * Program the 64-bit multicast hash filter. 2133 */ 2134 ETHER_FIRST_MULTI(step, ec, enm); 2135 while (enm != NULL) { 2136 /* XXX */ 2137 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2138 ETHER_ADDR_LEN) != 0) 2139 goto allmulti; 2140 2141 hash = rtw_calchash(enm->enm_addrlo); 2142 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2143 ETHER_NEXT_MULTI(step, enm); 2144 } 2145 2146 if (ifp->if_flags & IFF_BROADCAST) { 2147 hash = rtw_calchash(etherbroadcastaddr); 2148 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2149 } 2150 2151 /* all bits set => hash is useless */ 2152 if (~(hashes[0] & hashes[1]) == 0) 2153 goto allmulti; 2154 2155 setit: 2156 if (ifp->if_flags & IFF_ALLMULTI) 2157 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2158 2159 if (ic->ic_state == IEEE80211_S_SCAN) 2160 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2161 2162 hashes[0] = hashes[1] = 0xffffffff; 2163 2164 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2165 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2166 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2167 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2168 2169 DPRINTF(sc, ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2170 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2171 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2172 2173 return; 2174 } 2175 2176 static int 2177 rtw_init(struct ifnet *ifp) 2178 { 2179 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2180 struct ieee80211com *ic = &sc->sc_ic; 2181 struct rtw_regs *regs = &sc->sc_regs; 2182 int rc = 0; 2183 2184 if ((rc = rtw_enable(sc)) != 0) 2185 goto out; 2186 2187 /* Cancel pending I/O and reset. */ 2188 rtw_stop(ifp, 0); 2189 2190 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2191 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 2192 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2193 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2194 2195 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2196 goto out; 2197 2198 rtw_swring_setup(sc); 2199 2200 rtw_transmit_config(regs); 2201 2202 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2203 2204 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2205 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2206 2207 /* long PLCP header, 1Mbps basic rate */ 2208 RTW_WRITE16(regs, RTW_BRSR, 0x0f); 2209 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2210 2211 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 2212 rtw_set_access(sc, RTW_ACCESS_NONE); 2213 2214 #if 0 2215 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_GWAKE|RTW_FEMR_WKUP|RTW_FEMR_INTR); 2216 #endif 2217 /* XXX from reference sources */ 2218 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2219 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2220 2221 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2222 2223 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2224 /* from Linux driver */ 2225 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2226 2227 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2228 2229 rtw_enable_interrupts(sc); 2230 2231 rtw_pktfilt_load(sc); 2232 2233 rtw_hwring_setup(sc); 2234 2235 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2236 2237 ifp->if_flags |= IFF_RUNNING; 2238 ic->ic_state = IEEE80211_S_INIT; 2239 2240 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2241 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2242 2243 rtw_resume_ticks(sc); 2244 2245 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2246 2247 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2248 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2249 else 2250 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2251 2252 out: 2253 return rc; 2254 } 2255 2256 static int 2257 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2258 { 2259 int rc = 0; 2260 struct rtw_softc *sc = ifp->if_softc; 2261 struct ifreq *ifr = (struct ifreq *)data; 2262 2263 switch (cmd) { 2264 case SIOCSIFFLAGS: 2265 if ((ifp->if_flags & IFF_UP) != 0) { 2266 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2267 rtw_pktfilt_load(sc); 2268 } else 2269 rc = rtw_init(ifp); 2270 #ifdef RTW_DEBUG 2271 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2272 #endif /* RTW_DEBUG */ 2273 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2274 #ifdef RTW_DEBUG 2275 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2276 #endif /* RTW_DEBUG */ 2277 rtw_stop(ifp, 1); 2278 } 2279 break; 2280 case SIOCADDMULTI: 2281 case SIOCDELMULTI: 2282 if (cmd == SIOCADDMULTI) 2283 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2284 else 2285 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2286 if (rc == ENETRESET) { 2287 if (ifp->if_flags & IFF_RUNNING) 2288 rtw_pktfilt_load(sc); 2289 rc = 0; 2290 } 2291 break; 2292 default: 2293 if ((rc = ieee80211_ioctl(ifp, cmd, data)) == ENETRESET) { 2294 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2295 rc = rtw_init(ifp); 2296 else 2297 rc = 0; 2298 } 2299 break; 2300 } 2301 return rc; 2302 } 2303 2304 /* Point *mp at the next 802.11 frame to transmit. Point *stcp 2305 * at the driver's selection of transmit control block for the packet. 2306 */ 2307 static __inline int 2308 rtw_dequeue(struct ifnet *ifp, struct rtw_txctl_blk **stcp, 2309 struct rtw_txdesc_blk **htcp, struct mbuf **mp, 2310 struct ieee80211_node **nip) 2311 { 2312 struct rtw_txctl_blk *stc; 2313 struct rtw_txdesc_blk *htc; 2314 struct mbuf *m0; 2315 struct rtw_softc *sc; 2316 struct ieee80211com *ic; 2317 2318 sc = (struct rtw_softc *)ifp->if_softc; 2319 2320 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2321 *mp = NULL; 2322 2323 stc = &sc->sc_txctl_blk[RTW_TXPRIMD]; 2324 htc = &sc->sc_txdesc_blk[RTW_TXPRIMD]; 2325 2326 if (SIMPLEQ_EMPTY(&stc->stc_freeq) || htc->htc_nfree == 0) { 2327 DPRINTF2(sc, ("%s: out of descriptors\n", __func__)); 2328 ifp->if_flags |= IFF_OACTIVE; 2329 return 0; 2330 } 2331 2332 ic = &sc->sc_ic; 2333 2334 if (!IF_IS_EMPTY(&ic->ic_mgtq)) { 2335 IF_DEQUEUE(&ic->ic_mgtq, m0); 2336 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2337 m0->m_pkthdr.rcvif = NULL; 2338 DPRINTF2(sc, ("%s: dequeue mgt frame\n", __func__)); 2339 } else if (ic->ic_state != IEEE80211_S_RUN) { 2340 DPRINTF2(sc, ("%s: not running\n", __func__)); 2341 return 0; 2342 } else if (!IF_IS_EMPTY(&ic->ic_pwrsaveq)) { 2343 IF_DEQUEUE(&ic->ic_pwrsaveq, m0); 2344 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2345 m0->m_pkthdr.rcvif = NULL; 2346 DPRINTF2(sc, ("%s: dequeue pwrsave frame\n", __func__)); 2347 } else { 2348 IFQ_POLL(&ifp->if_snd, m0); 2349 if (m0 == NULL) { 2350 DPRINTF2(sc, ("%s: no frame\n", __func__)); 2351 return 0; 2352 } 2353 DPRINTF2(sc, ("%s: dequeue data frame\n", __func__)); 2354 IFQ_DEQUEUE(&ifp->if_snd, m0); 2355 ifp->if_opackets++; 2356 #if NBPFILTER > 0 2357 if (ifp->if_bpf) 2358 bpf_mtap(ifp->if_bpf, m0); 2359 #endif 2360 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2361 DPRINTF2(sc, ("%s: encap error\n", __func__)); 2362 ifp->if_oerrors++; 2363 return -1; 2364 } 2365 } 2366 DPRINTF2(sc, ("%s: leave\n", __func__)); 2367 *stcp = stc; 2368 *htcp = htc; 2369 *mp = m0; 2370 return 0; 2371 } 2372 2373 /* TBD factor with atw_start */ 2374 static struct mbuf * 2375 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2376 u_int ndescfree, short *ifflagsp, const char *dvname) 2377 { 2378 int first, rc; 2379 struct mbuf *m, *m0; 2380 2381 m0 = chain; 2382 2383 /* 2384 * Load the DMA map. Copy and try (once) again if the packet 2385 * didn't fit in the alloted number of segments. 2386 */ 2387 for (first = 1; 2388 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2389 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2390 dmam->dm_nsegs > ndescfree) && first; 2391 first = 0) { 2392 if (rc == 0) 2393 bus_dmamap_unload(dmat, dmam); 2394 MGETHDR(m, M_DONTWAIT, MT_DATA); 2395 if (m == NULL) { 2396 printf("%s: unable to allocate Tx mbuf\n", 2397 dvname); 2398 break; 2399 } 2400 if (m0->m_pkthdr.len > MHLEN) { 2401 MCLGET(m, M_DONTWAIT); 2402 if ((m->m_flags & M_EXT) == 0) { 2403 printf("%s: cannot allocate Tx cluster\n", 2404 dvname); 2405 m_freem(m); 2406 break; 2407 } 2408 } 2409 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2410 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 2411 m_freem(m0); 2412 m0 = m; 2413 m = NULL; 2414 } 2415 if (rc != 0) { 2416 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 2417 m_freem(m0); 2418 return NULL; 2419 } else if (dmam->dm_nsegs > ndescfree) { 2420 *ifflagsp |= IFF_OACTIVE; 2421 bus_dmamap_unload(dmat, dmam); 2422 m_freem(m0); 2423 return NULL; 2424 } 2425 return m0; 2426 } 2427 2428 static void 2429 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 2430 struct rtw_txctl *stx, struct rtw_txdesc_blk *htc, int desc) 2431 { 2432 struct rtw_txdesc *htx = &htc->htc_desc[desc]; 2433 DPRINTF2(sc, ("%s: stx %p %s txdesc[%d] ctl0 %#08x " 2434 "ctl1 %#08x buf %#08x len %#08x\n", 2435 sc->sc_dev.dv_xname, stx, action, desc, 2436 le32toh(htx->htx_ctl0), 2437 le32toh(htx->htx_ctl1), le32toh(htx->htx_buf), 2438 le32toh(htx->htx_len))); 2439 } 2440 2441 static void 2442 rtw_start(struct ifnet *ifp) 2443 { 2444 uint8_t tppoll; 2445 int desc, i, lastdesc, npkt, rate; 2446 uint32_t proto_ctl0, ctl0, ctl1; 2447 bus_dmamap_t dmamap; 2448 struct ieee80211com *ic; 2449 struct ieee80211_duration *d0; 2450 struct ieee80211_frame *wh; 2451 struct ieee80211_node *ni; 2452 struct mbuf *m0; 2453 struct rtw_softc *sc; 2454 struct rtw_txctl_blk *stc; 2455 struct rtw_txdesc_blk *htc; 2456 struct rtw_txctl *stx; 2457 struct rtw_txdesc *htx; 2458 2459 sc = (struct rtw_softc *)ifp->if_softc; 2460 ic = &sc->sc_ic; 2461 2462 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2463 2464 /* XXX do real rate control */ 2465 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 2466 2467 switch (rate = MAX(2, ieee80211_get_rate(ic))) { 2468 case 2: 2469 proto_ctl0 |= RTW_TXCTL0_RATE_1MBPS; 2470 break; 2471 case 4: 2472 proto_ctl0 |= RTW_TXCTL0_RATE_2MBPS; 2473 break; 2474 case 11: 2475 proto_ctl0 |= RTW_TXCTL0_RATE_5MBPS; 2476 break; 2477 case 22: 2478 proto_ctl0 |= RTW_TXCTL0_RATE_11MBPS; 2479 break; 2480 } 2481 2482 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 2483 proto_ctl0 |= RTW_TXCTL0_SPLCP; 2484 2485 for (;;) { 2486 if (rtw_dequeue(ifp, &stc, &htc, &m0, &ni) == -1) 2487 continue; 2488 if (m0 == NULL) 2489 break; 2490 stx = SIMPLEQ_FIRST(&stc->stc_freeq); 2491 2492 dmamap = stx->stx_dmamap; 2493 2494 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 2495 htc->htc_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 2496 2497 if (m0 == NULL || dmamap->dm_nsegs == 0) { 2498 DPRINTF2(sc, ("%s: fail dmamap load\n", __func__)); 2499 goto post_dequeue_err; 2500 } 2501 2502 #ifdef RTW_DEBUG 2503 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 2504 (IFF_DEBUG|IFF_LINK2)) { 2505 ieee80211_dump_pkt(mtod(m0, uint8_t *), 2506 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 2507 : sizeof(wh), 2508 rate, 0); 2509 } 2510 #endif /* RTW_DEBUG */ 2511 ctl0 = proto_ctl0 | 2512 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 2513 2514 wh = mtod(m0, struct ieee80211_frame *); 2515 2516 if (ieee80211_compute_duration(wh, 2517 m0->m_pkthdr.len - sizeof(wh), 2518 ic->ic_flags, ic->ic_fragthreshold, 2519 rate, &stx->stx_d0, &stx->stx_dn, &npkt) == -1) { 2520 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 2521 goto post_load_err; 2522 } 2523 2524 /* XXX >= ? */ 2525 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 2526 ctl0 |= RTW_TXCTL0_RTSEN; 2527 2528 d0 = &stx->stx_d0; 2529 2530 ctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 2531 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 2532 2533 if ((d0->d_plcp_svc & IEEE80211_PLCP_SERVICE_LENEXT) != 0) 2534 ctl1 |= RTW_TXCTL1_LENGEXT; 2535 2536 /* TBD fragmentation */ 2537 2538 stx->stx_first = htc->htc_next; 2539 2540 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2541 htc, stx->stx_first, dmamap->dm_nsegs, 2542 BUS_DMASYNC_PREWRITE); 2543 2544 for (i = 0, lastdesc = desc = stx->stx_first; 2545 i < dmamap->dm_nsegs; 2546 i++, desc = RTW_NEXT_IDX(htc, desc)) { 2547 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 2548 DPRINTF2(sc, ("%s: seg too long\n", __func__)); 2549 goto post_load_err; 2550 } 2551 htx = &htc->htc_desc[desc]; 2552 htx->htx_ctl0 = htole32(ctl0); 2553 if (i != 0) 2554 htx->htx_ctl0 |= htole32(RTW_TXCTL0_OWN); 2555 htx->htx_ctl1 = htole32(ctl1); 2556 htx->htx_buf = htole32(dmamap->dm_segs[i].ds_addr); 2557 htx->htx_len = htole32(dmamap->dm_segs[i].ds_len); 2558 lastdesc = desc; 2559 #ifdef RTW_DEBUG 2560 rtw_print_txdesc(sc, "load", stx, htc, desc); 2561 #endif /* RTW_DEBUG */ 2562 } 2563 2564 stx->stx_ni = ni; 2565 stx->stx_mbuf = m0; 2566 stx->stx_last = lastdesc; 2567 htc->htc_desc[stx->stx_last].htx_ctl0 |= htole32(RTW_TXCTL0_LS); 2568 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2569 htole32(RTW_TXCTL0_FS); 2570 2571 #ifdef RTW_DEBUG 2572 rtw_print_txdesc(sc, "FS on", stx, htc, stx->stx_first); 2573 #endif /* RTW_DEBUG */ 2574 #ifdef RTW_DEBUG 2575 rtw_print_txdesc(sc, "LS on", stx, htc, stx->stx_last); 2576 #endif /* RTW_DEBUG */ 2577 2578 htc->htc_nfree -= dmamap->dm_nsegs; 2579 htc->htc_next = desc; 2580 2581 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2582 htc, stx->stx_first, dmamap->dm_nsegs, 2583 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2584 2585 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2586 htole32(RTW_TXCTL0_OWN); 2587 2588 #ifdef RTW_DEBUG 2589 rtw_print_txdesc(sc, "OWN on", stx, htc, stx->stx_first); 2590 #endif /* RTW_DEBUG */ 2591 2592 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2593 htc, stx->stx_first, 1, 2594 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2595 2596 SIMPLEQ_REMOVE_HEAD(&stc->stc_freeq, stx_q); 2597 SIMPLEQ_INSERT_TAIL(&stc->stc_dirtyq, stx, stx_q); 2598 2599 stc->stc_tx_timer = 5; 2600 ifp->if_timer = 1; 2601 2602 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 2603 2604 /* TBD poke other queues. */ 2605 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll | RTW_TPPOLL_NPQ); 2606 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 2607 } 2608 DPRINTF2(sc, ("%s: leave\n", __func__)); 2609 return; 2610 post_load_err: 2611 bus_dmamap_unload(sc->sc_dmat, dmamap); 2612 m_freem(m0); 2613 post_dequeue_err: 2614 ieee80211_release_node(&sc->sc_ic, ni); 2615 return; 2616 } 2617 2618 static void 2619 rtw_watchdog(struct ifnet *ifp) 2620 { 2621 int pri; 2622 struct rtw_softc *sc; 2623 struct rtw_txctl_blk *stc; 2624 2625 sc = ifp->if_softc; 2626 2627 ifp->if_timer = 0; 2628 2629 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2630 return; 2631 2632 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2633 stc = &sc->sc_txctl_blk[pri]; 2634 2635 if (stc->stc_tx_timer == 0) 2636 continue; 2637 2638 if (--stc->stc_tx_timer == 0) { 2639 if (SIMPLEQ_EMPTY(&stc->stc_dirtyq)) 2640 continue; 2641 printf("%s: transmit timeout, priority %d\n", 2642 ifp->if_xname, pri); 2643 ifp->if_oerrors++; 2644 /* XXX be gentle */ 2645 (void)rtw_init(ifp); 2646 rtw_start(ifp); 2647 } else 2648 ifp->if_timer = 1; 2649 } 2650 ieee80211_watchdog(ifp); 2651 return; 2652 } 2653 2654 static void 2655 rtw_start_beacon(struct rtw_softc *sc, int enable) 2656 { 2657 /* TBD */ 2658 return; 2659 } 2660 2661 static void 2662 rtw_next_scan(void *arg) 2663 { 2664 struct ieee80211com *ic = arg; 2665 int s; 2666 2667 /* don't call rtw_start w/o network interrupts blocked */ 2668 s = splnet(); 2669 if (ic->ic_state == IEEE80211_S_SCAN) 2670 ieee80211_next_scan(ic); 2671 splx(s); 2672 } 2673 2674 static void 2675 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, enum ieee80211_opmode opmode, 2676 uint16_t intval0) 2677 { 2678 uint16_t bcnitv, intval; 2679 int i; 2680 struct rtw_regs *regs = &sc->sc_regs; 2681 2682 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 2683 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 2684 2685 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 2686 2687 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2688 2689 intval = MIN(intval0, PRESHIFT(RTW_BCNITV_BCNITV_MASK)); 2690 2691 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 2692 bcnitv |= LSHIFT(intval, RTW_BCNITV_BCNITV_MASK); 2693 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 2694 /* magic from Linux */ 2695 RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND)); 2696 RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV)); 2697 2698 rtw_set_nettype(sc, opmode); 2699 2700 rtw_set_access(sc, RTW_ACCESS_NONE); 2701 2702 /* TBD WEP */ 2703 RTW_WRITE8(regs, RTW_SCR, 0); 2704 2705 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 2706 } 2707 2708 /* Synchronize the hardware state with the software state. */ 2709 static int 2710 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2711 { 2712 struct ifnet *ifp = &ic->ic_if; 2713 struct rtw_softc *sc = ifp->if_softc; 2714 enum ieee80211_state ostate; 2715 int error; 2716 2717 ostate = ic->ic_state; 2718 2719 if (nstate == IEEE80211_S_INIT) { 2720 callout_stop(&sc->sc_scan_ch); 2721 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2722 rtw_start_beacon(sc, 0); 2723 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2724 } 2725 2726 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 2727 rtw_pwrstate(sc, RTW_ON); 2728 2729 if ((error = rtw_tune(sc)) != 0) 2730 return error; 2731 2732 switch (nstate) { 2733 case IEEE80211_S_ASSOC: 2734 rtw_join_bss(sc, ic->ic_bss->ni_bssid, ic->ic_opmode, 2735 ic->ic_bss->ni_intval); 2736 break; 2737 case IEEE80211_S_INIT: 2738 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2739 break; 2740 case IEEE80211_S_SCAN: 2741 #if 0 2742 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2743 rtw_write_bssid(sc); 2744 #endif 2745 2746 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 2747 rtw_next_scan, ic); 2748 2749 break; 2750 case IEEE80211_S_RUN: 2751 if (ic->ic_opmode == IEEE80211_M_STA) 2752 break; 2753 /*FALLTHROUGH*/ 2754 case IEEE80211_S_AUTH: 2755 #if 0 2756 rtw_write_bcn_thresh(sc); 2757 rtw_write_ssid(sc); 2758 rtw_write_sup_rates(sc); 2759 #endif 2760 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2761 ic->ic_opmode == IEEE80211_M_MONITOR) 2762 break; 2763 2764 /* TBD set listen interval */ 2765 2766 #if 0 2767 rtw_tsf(sc); 2768 #endif 2769 break; 2770 } 2771 2772 if (nstate != IEEE80211_S_SCAN) 2773 callout_stop(&sc->sc_scan_ch); 2774 2775 if (nstate == IEEE80211_S_RUN && 2776 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2777 ic->ic_opmode == IEEE80211_M_IBSS)) 2778 rtw_start_beacon(sc, 1); 2779 else 2780 rtw_start_beacon(sc, 0); 2781 2782 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2783 } 2784 2785 static void 2786 rtw_recv_beacon(struct rtw_softc *sc, struct mbuf *m, 2787 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2788 { 2789 (*sc->sc_mtbl.mt_recv_mgmt)(&sc->sc_ic, m, ni, subtype, rssi, rstamp); 2790 return; 2791 } 2792 2793 static void 2794 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2795 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2796 { 2797 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 2798 2799 switch (subtype) { 2800 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2801 /* do nothing: hardware answers probe request XXX */ 2802 break; 2803 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2804 case IEEE80211_FC0_SUBTYPE_BEACON: 2805 rtw_recv_beacon(sc, m, ni, subtype, rssi, rstamp); 2806 break; 2807 default: 2808 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2809 break; 2810 } 2811 return; 2812 } 2813 2814 static struct ieee80211_node * 2815 rtw_node_alloc(struct ieee80211com *ic) 2816 { 2817 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2818 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 2819 2820 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 2821 return ni; 2822 } 2823 2824 static void 2825 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 2826 { 2827 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2828 2829 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 2830 ether_sprintf(ni->ni_bssid))); 2831 (*sc->sc_mtbl.mt_node_free)(ic, ni); 2832 } 2833 2834 static int 2835 rtw_media_change(struct ifnet *ifp) 2836 { 2837 int error; 2838 2839 error = ieee80211_media_change(ifp); 2840 if (error == ENETRESET) { 2841 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 2842 (IFF_RUNNING|IFF_UP)) 2843 rtw_init(ifp); /* XXX lose error */ 2844 error = 0; 2845 } 2846 return error; 2847 } 2848 2849 static void 2850 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 2851 { 2852 struct rtw_softc *sc = ifp->if_softc; 2853 2854 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2855 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 2856 imr->ifm_status = 0; 2857 return; 2858 } 2859 ieee80211_media_status(ifp, imr); 2860 } 2861 2862 void 2863 rtw_power(int why, void *arg) 2864 { 2865 struct rtw_softc *sc = arg; 2866 struct ifnet *ifp = &sc->sc_ic.ic_if; 2867 int s; 2868 2869 DPRINTF(sc, ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 2870 2871 s = splnet(); 2872 switch (why) { 2873 case PWR_STANDBY: 2874 /* XXX do nothing. */ 2875 break; 2876 case PWR_SUSPEND: 2877 rtw_stop(ifp, 0); 2878 if (sc->sc_power != NULL) 2879 (*sc->sc_power)(sc, why); 2880 break; 2881 case PWR_RESUME: 2882 if (ifp->if_flags & IFF_UP) { 2883 if (sc->sc_power != NULL) 2884 (*sc->sc_power)(sc, why); 2885 rtw_init(ifp); 2886 } 2887 break; 2888 case PWR_SOFTSUSPEND: 2889 case PWR_SOFTSTANDBY: 2890 case PWR_SOFTRESUME: 2891 break; 2892 } 2893 splx(s); 2894 } 2895 2896 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 2897 void 2898 rtw_shutdown(void *arg) 2899 { 2900 struct rtw_softc *sc = arg; 2901 2902 rtw_stop(&sc->sc_ic.ic_if, 1); 2903 } 2904 2905 static __inline void 2906 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 2907 { 2908 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 2909 ifp->if_softc = softc; 2910 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 2911 IFF_NOTRAILERS; 2912 ifp->if_ioctl = rtw_ioctl; 2913 ifp->if_start = rtw_start; 2914 ifp->if_watchdog = rtw_watchdog; 2915 ifp->if_init = rtw_init; 2916 ifp->if_stop = rtw_stop; 2917 } 2918 2919 static __inline void 2920 rtw_set80211props(struct ieee80211com *ic) 2921 { 2922 int nrate; 2923 ic->ic_phytype = IEEE80211_T_DS; 2924 ic->ic_opmode = IEEE80211_M_STA; 2925 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 2926 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 2927 2928 nrate = 0; 2929 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2930 IEEE80211_RATE_BASIC | 2; 2931 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2932 IEEE80211_RATE_BASIC | 4; 2933 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 2934 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 2935 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 2936 } 2937 2938 static __inline void 2939 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 2940 { 2941 mtbl->mt_newstate = ic->ic_newstate; 2942 ic->ic_newstate = rtw_newstate; 2943 2944 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 2945 ic->ic_recv_mgmt = rtw_recv_mgmt; 2946 2947 mtbl->mt_node_free = ic->ic_node_free; 2948 ic->ic_node_free = rtw_node_free; 2949 2950 mtbl->mt_node_alloc = ic->ic_node_alloc; 2951 ic->ic_node_alloc = rtw_node_alloc; 2952 } 2953 2954 static __inline void 2955 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 2956 void *arg) 2957 { 2958 /* 2959 * Make sure the interface is shutdown during reboot. 2960 */ 2961 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 2962 if (hooks->rh_shutdown == NULL) 2963 printf("%s: WARNING: unable to establish shutdown hook\n", 2964 dvname); 2965 2966 /* 2967 * Add a suspend hook to make sure we come back up after a 2968 * resume. 2969 */ 2970 hooks->rh_power = powerhook_establish(rtw_power, arg); 2971 if (hooks->rh_power == NULL) 2972 printf("%s: WARNING: unable to establish power hook\n", 2973 dvname); 2974 } 2975 2976 static __inline void 2977 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 2978 void *arg) 2979 { 2980 if (hooks->rh_shutdown != NULL) 2981 shutdownhook_disestablish(hooks->rh_shutdown); 2982 2983 if (hooks->rh_power != NULL) 2984 powerhook_disestablish(hooks->rh_power); 2985 } 2986 2987 static __inline void 2988 rtw_init_radiotap(struct rtw_softc *sc) 2989 { 2990 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 2991 sc->sc_rxtap.rr_ihdr.it_len = sizeof(sc->sc_rxtapu); 2992 sc->sc_rxtap.rr_ihdr.it_present = RTW_RX_RADIOTAP_PRESENT; 2993 2994 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 2995 sc->sc_txtap.rt_ihdr.it_len = sizeof(sc->sc_txtapu); 2996 sc->sc_txtap.rt_ihdr.it_present = RTW_TX_RADIOTAP_PRESENT; 2997 } 2998 2999 static int 3000 rtw_txctl_blk_setup(struct rtw_txctl_blk *stc, u_int qlen) 3001 { 3002 SIMPLEQ_INIT(&stc->stc_dirtyq); 3003 SIMPLEQ_INIT(&stc->stc_freeq); 3004 stc->stc_ndesc = qlen; 3005 stc->stc_desc = malloc(qlen * sizeof(*stc->stc_desc), M_DEVBUF, 3006 M_NOWAIT); 3007 if (stc->stc_desc == NULL) 3008 return ENOMEM; 3009 return 0; 3010 } 3011 3012 static void 3013 rtw_txctl_blk_cleanup_all(struct rtw_softc *sc) 3014 { 3015 struct rtw_txctl_blk *stc; 3016 int qlen[RTW_NTXPRI] = 3017 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3018 int pri; 3019 3020 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 3021 stc = &sc->sc_txctl_blk[pri]; 3022 free(stc->stc_desc, M_DEVBUF); 3023 stc->stc_desc = NULL; 3024 } 3025 } 3026 3027 static int 3028 rtw_txctl_blk_setup_all(struct rtw_softc *sc) 3029 { 3030 int pri, rc = 0; 3031 int qlen[RTW_NTXPRI] = 3032 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3033 3034 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 3035 rc = rtw_txctl_blk_setup(&sc->sc_txctl_blk[pri], qlen[pri]); 3036 if (rc != 0) 3037 break; 3038 } 3039 return rc; 3040 } 3041 3042 static void 3043 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *htc, struct rtw_txdesc *desc, 3044 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3045 { 3046 int i; 3047 3048 htc->htc_ndesc = ndesc; 3049 htc->htc_desc = desc; 3050 htc->htc_physbase = physbase; 3051 htc->htc_ofs = ofs; 3052 3053 (void)memset(htc->htc_desc, 0, 3054 sizeof(htc->htc_desc[0]) * htc->htc_ndesc); 3055 3056 for (i = 0; i < htc->htc_ndesc; i++) { 3057 htc->htc_desc[i].htx_next = htole32(RTW_NEXT_DESC(htc, i)); 3058 } 3059 } 3060 3061 static void 3062 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3063 { 3064 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3065 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3066 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3067 3068 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3069 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3070 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3071 3072 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3073 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3074 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3075 3076 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3077 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3078 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3079 } 3080 3081 static struct rtw_rf * 3082 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, 3083 rtw_rf_write_t rf_write, int digphy) 3084 { 3085 struct rtw_rf *rf; 3086 3087 switch (rfchipid) { 3088 case RTW_RFCHIPID_MAXIM: 3089 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3090 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3091 break; 3092 case RTW_RFCHIPID_PHILIPS: 3093 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3094 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3095 break; 3096 case RTW_RFCHIPID_RFMD: 3097 /* XXX RFMD has no RF constructor */ 3098 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3099 /*FALLTHROUGH*/ 3100 default: 3101 return NULL; 3102 } 3103 rf->rf_continuous_tx_cb = 3104 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3105 rf->rf_continuous_tx_arg = (void *)sc; 3106 return rf; 3107 } 3108 3109 /* Revision C and later use a different PHY delay setting than 3110 * revisions A and B. 3111 */ 3112 static u_int8_t 3113 rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0) 3114 { 3115 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3116 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3117 3118 u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 3119 3120 RTW_WRITE(regs, RTW_RCR, REVAB); 3121 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3122 RTW_WRITE(regs, RTW_RCR, REVC); 3123 3124 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3125 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3126 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3127 3128 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 3129 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3130 3131 return phydelay; 3132 #undef REVC 3133 } 3134 3135 void 3136 rtw_attach(struct rtw_softc *sc) 3137 { 3138 rtw_rf_write_t rf_write; 3139 struct rtw_txctl_blk *stc; 3140 int pri, rc, vers; 3141 3142 #if 0 3143 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_txdesc) == 0, 3144 "RTW_DESC_ALIGNMENT is not a multiple of " 3145 "sizeof(struct rtw_txdesc)"); 3146 3147 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_rxdesc) == 0, 3148 "RTW_DESC_ALIGNMENT is not a multiple of " 3149 "sizeof(struct rtw_rxdesc)"); 3150 3151 CASSERT(RTW_DESC_ALIGNMENT % RTW_MAXPKTSEGS == 0, 3152 "RTW_DESC_ALIGNMENT is not a multiple of RTW_MAXPKTSEGS"); 3153 #endif 3154 3155 NEXT_ATTACH_STATE(sc, DETACHED); 3156 3157 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3158 case RTW_TCR_HWVERID_F: 3159 vers = 'F'; 3160 rf_write = rtw_rf_hostwrite; 3161 break; 3162 case RTW_TCR_HWVERID_D: 3163 vers = 'D'; 3164 if (rtw_host_rfio) 3165 rf_write = rtw_rf_hostwrite; 3166 else 3167 rf_write = rtw_rf_macwrite; 3168 break; 3169 default: 3170 vers = '?'; 3171 rf_write = rtw_rf_macwrite; 3172 break; 3173 } 3174 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, vers); 3175 3176 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3177 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3178 0); 3179 3180 if (rc != 0) { 3181 printf("%s: could not allocate hw descriptors, error %d\n", 3182 sc->sc_dev.dv_xname, rc); 3183 goto err; 3184 } 3185 3186 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3187 3188 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3189 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3190 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3191 3192 if (rc != 0) { 3193 printf("%s: could not map hw descriptors, error %d\n", 3194 sc->sc_dev.dv_xname, rc); 3195 goto err; 3196 } 3197 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3198 3199 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3200 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3201 3202 if (rc != 0) { 3203 printf("%s: could not create DMA map for hw descriptors, " 3204 "error %d\n", sc->sc_dev.dv_xname, rc); 3205 goto err; 3206 } 3207 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3208 3209 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3210 sizeof(struct rtw_descs), NULL, 0); 3211 3212 if (rc != 0) { 3213 printf("%s: could not load DMA map for hw descriptors, " 3214 "error %d\n", sc->sc_dev.dv_xname, rc); 3215 goto err; 3216 } 3217 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3218 3219 if (rtw_txctl_blk_setup_all(sc) != 0) 3220 goto err; 3221 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3222 3223 rtw_txdesc_blk_setup_all(sc); 3224 3225 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3226 3227 sc->sc_rxdesc = &sc->sc_descs->hd_rx[0]; 3228 3229 rtw_rxctls_setup(&sc->sc_rxctl[0]); 3230 3231 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3232 stc = &sc->sc_txctl_blk[pri]; 3233 3234 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3235 &stc->stc_desc[0], stc->stc_ndesc)) != 0) { 3236 printf("%s: could not load DMA map for " 3237 "hw tx descriptors, error %d\n", 3238 sc->sc_dev.dv_xname, rc); 3239 goto err; 3240 } 3241 } 3242 3243 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3244 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxctl[0], 3245 RTW_RXQLEN)) != 0) { 3246 printf("%s: could not load DMA map for hw rx descriptors, " 3247 "error %d\n", sc->sc_dev.dv_xname, rc); 3248 goto err; 3249 } 3250 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3251 3252 /* Reset the chip to a known state. */ 3253 if (rtw_reset(sc) != 0) 3254 goto err; 3255 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3256 3257 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3258 3259 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3260 sc->sc_flags |= RTW_F_9356SROM; 3261 3262 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3263 sc->sc_dev.dv_xname) != 0) 3264 goto err; 3265 3266 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3267 3268 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3269 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3270 sc->sc_dev.dv_xname) != 0) { 3271 printf("%s: attach failed, malformed serial ROM\n", 3272 sc->sc_dev.dv_xname); 3273 goto err; 3274 } 3275 3276 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 3277 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 3278 3279 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 3280 3281 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3282 3283 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, rf_write, 3284 sc->sc_flags & RTW_F_DIGPHY); 3285 3286 if (sc->sc_rf == NULL) { 3287 printf("%s: attach failed, could not attach RF\n", 3288 sc->sc_dev.dv_xname); 3289 goto err; 3290 } 3291 3292 #if 0 3293 if (rtw_identify_rf(&sc->sc_regs, &sc->sc_rftype, 3294 sc->sc_dev.dv_xname) != 0) { 3295 printf("%s: attach failed, unknown RF unidentified\n", 3296 sc->sc_dev.dv_xname); 3297 goto err; 3298 } 3299 #endif 3300 3301 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3302 3303 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 3304 3305 RTW_DPRINTF(("%s: PHY delay %d\n", sc->sc_dev.dv_xname, 3306 sc->sc_phydelay)); 3307 3308 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 3309 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 3310 sc->sc_dev.dv_xname); 3311 3312 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 3313 sc->sc_dev.dv_xname); 3314 3315 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 3316 sc->sc_dev.dv_xname) != 0) 3317 goto err; 3318 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 3319 3320 rtw_setifprops(&sc->sc_if, sc->sc_dev.dv_xname, (void*)sc); 3321 3322 IFQ_SET_READY(&sc->sc_if.if_snd); 3323 3324 rtw_set80211props(&sc->sc_ic); 3325 3326 /* 3327 * Call MI attach routines. 3328 */ 3329 if_attach(&sc->sc_if); 3330 ieee80211_ifattach(&sc->sc_if); 3331 3332 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 3333 3334 /* possibly we should fill in our own sc_send_prresp, since 3335 * the RTL8180 is probably sending probe responses in ad hoc 3336 * mode. 3337 */ 3338 3339 /* complete initialization */ 3340 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 3341 callout_init(&sc->sc_scan_ch); 3342 3343 #if NBPFILTER > 0 3344 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 3345 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 3346 #endif 3347 3348 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 3349 3350 rtw_init_radiotap(sc); 3351 3352 NEXT_ATTACH_STATE(sc, FINISHED); 3353 3354 return; 3355 err: 3356 rtw_detach(sc); 3357 return; 3358 } 3359 3360 int 3361 rtw_detach(struct rtw_softc *sc) 3362 { 3363 int pri; 3364 3365 switch (sc->sc_attach_state) { 3366 case FINISHED: 3367 rtw_stop(&sc->sc_if, 1); 3368 3369 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 3370 (void*)sc); 3371 callout_stop(&sc->sc_scan_ch); 3372 ieee80211_ifdetach(&sc->sc_if); 3373 if_detach(&sc->sc_if); 3374 break; 3375 case FINISH_ID_STA: 3376 case FINISH_RF_ATTACH: 3377 rtw_rf_destroy(sc->sc_rf); 3378 sc->sc_rf = NULL; 3379 /*FALLTHROUGH*/ 3380 case FINISH_PARSE_SROM: 3381 case FINISH_READ_SROM: 3382 rtw_srom_free(&sc->sc_srom); 3383 /*FALLTHROUGH*/ 3384 case FINISH_RESET: 3385 case FINISH_RXMAPS_CREATE: 3386 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxctl[0], 3387 RTW_RXQLEN); 3388 /*FALLTHROUGH*/ 3389 case FINISH_TXMAPS_CREATE: 3390 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3391 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 3392 sc->sc_txctl_blk[pri].stc_desc, 3393 sc->sc_txctl_blk[pri].stc_ndesc); 3394 } 3395 /*FALLTHROUGH*/ 3396 case FINISH_TXDESCBLK_SETUP: 3397 case FINISH_TXCTLBLK_SETUP: 3398 rtw_txctl_blk_cleanup_all(sc); 3399 /*FALLTHROUGH*/ 3400 case FINISH_DESCMAP_LOAD: 3401 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 3402 /*FALLTHROUGH*/ 3403 case FINISH_DESCMAP_CREATE: 3404 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 3405 /*FALLTHROUGH*/ 3406 case FINISH_DESC_MAP: 3407 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 3408 sizeof(struct rtw_descs)); 3409 /*FALLTHROUGH*/ 3410 case FINISH_DESC_ALLOC: 3411 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 3412 sc->sc_desc_nsegs); 3413 /*FALLTHROUGH*/ 3414 case DETACHED: 3415 NEXT_ATTACH_STATE(sc, DETACHED); 3416 break; 3417 } 3418 return 0; 3419 } 3420 3421 int 3422 rtw_activate(struct device *self, enum devact act) 3423 { 3424 struct rtw_softc *sc = (struct rtw_softc *)self; 3425 int rc = 0, s; 3426 3427 s = splnet(); 3428 switch (act) { 3429 case DVACT_ACTIVATE: 3430 rc = EOPNOTSUPP; 3431 break; 3432 3433 case DVACT_DEACTIVATE: 3434 if_deactivate(&sc->sc_ic.ic_if); 3435 break; 3436 } 3437 splx(s); 3438 return rc; 3439 } 3440
Indexes created Fri Sep 26 20:09:58 GMT 2025