rtw.c revision 1.18
1 /* $NetBSD: rtw.c,v 1.18 2004/12/23 06:03:09 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.18 2004/12/23 06:03:09 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #if 0 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #endif 54 #include <sys/time.h> 55 #include <sys/types.h> 56 57 #include <machine/endian.h> 58 #include <machine/bus.h> 59 #include <machine/intr.h> /* splnet */ 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_compat.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <dev/ic/rtwreg.h> 76 #include <dev/ic/rtwvar.h> 77 #include <dev/ic/rtwphyio.h> 78 #include <dev/ic/rtwphy.h> 79 80 #include <dev/ic/smc93cx6var.h> 81 82 #define KASSERT2(__cond, __msg) \ 83 do { \ 84 if (!(__cond)) \ 85 panic __msg ; \ 86 } while (0) 87 88 int rtw_rfprog_fallback = 0; 89 int rtw_host_rfio = 0; 90 int rtw_flush_rfio = 1; 91 int rtw_rfio_delay = 0; 92 93 #ifdef RTW_DEBUG 94 int rtw_debug = 2; 95 #endif /* RTW_DEBUG */ 96 97 #define NEXT_ATTACH_STATE(sc, state) do { \ 98 DPRINTF(sc, ("%s: attach state %s\n", __func__, #state)); \ 99 sc->sc_attach_state = state; \ 100 } while (0) 101 102 int rtw_dwelltime = 1000; /* milliseconds */ 103 104 static void rtw_start(struct ifnet *); 105 106 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 107 static int rtw_sysctl_verify_rfio_delay(SYSCTLFN_PROTO); 108 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 109 #ifdef RTW_DEBUG 110 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 111 #endif /* RTW_DEBUG */ 112 113 /* 114 * Setup sysctl(3) MIB, hw.rtw.* 115 * 116 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 117 */ 118 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 119 { 120 int rc; 121 struct sysctlnode *cnode, *rnode; 122 123 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 124 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 125 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 126 goto err; 127 128 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 129 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 130 "Realtek RTL818x 802.11 controls", 131 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 132 goto err; 133 134 #ifdef RTW_DEBUG 135 /* control debugging printfs */ 136 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 137 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 138 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 139 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 140 CTL_CREATE, CTL_EOL)) != 0) 141 goto err; 142 #endif /* RTW_DEBUG */ 143 /* set fallback RF programming method */ 144 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 145 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 146 "rfprog_fallback", 147 SYSCTL_DESCR("Set fallback RF programming method"), 148 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 149 CTL_CREATE, CTL_EOL)) != 0) 150 goto err; 151 152 /* force host to flush I/O by reading RTW_PHYADDR */ 153 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 154 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 155 "flush_rfio", SYSCTL_DESCR("Enable RF I/O flushing"), 156 rtw_sysctl_verify_rfio, 0, &rtw_flush_rfio, 0, 157 CTL_CREATE, CTL_EOL)) != 0) 158 goto err; 159 160 /* force host to control RF I/O bus */ 161 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 162 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 163 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 164 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 165 CTL_CREATE, CTL_EOL)) != 0) 166 goto err; 167 168 /* control RF I/O delay */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfio_delay", SYSCTL_DESCR("Set RF I/O delay"), 172 rtw_sysctl_verify_rfio_delay, 0, &rtw_rfio_delay, 0, 173 CTL_CREATE, CTL_EOL)) != 0) 174 goto err; 175 176 return; 177 err: 178 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 179 } 180 181 static int 182 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 183 { 184 int error, t; 185 struct sysctlnode node; 186 187 node = *rnode; 188 t = *(int*)rnode->sysctl_data; 189 node.sysctl_data = &t; 190 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 191 if (error || newp == NULL) 192 return (error); 193 194 if (t < lower || t > upper) 195 return (EINVAL); 196 197 *(int*)rnode->sysctl_data = t; 198 199 return (0); 200 } 201 202 static int 203 rtw_sysctl_verify_rfio_delay(SYSCTLFN_ARGS) 204 { 205 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1000000); 206 } 207 208 static int 209 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 210 { 211 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 212 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 213 } 214 215 static int 216 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 217 { 218 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1); 219 } 220 221 #ifdef RTW_DEBUG 222 static int 223 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 224 { 225 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 2); 226 } 227 228 static void 229 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 230 { 231 #define PRINTREG32(sc, reg) \ 232 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 233 dvname, reg, RTW_READ(regs, reg))) 234 235 #define PRINTREG16(sc, reg) \ 236 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %04x\n", \ 237 dvname, reg, RTW_READ16(regs, reg))) 238 239 #define PRINTREG8(sc, reg) \ 240 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %02x\n", \ 241 dvname, reg, RTW_READ8(regs, reg))) 242 243 RTW_DPRINTF2(("%s: %s\n", dvname, where)); 244 245 PRINTREG32(regs, RTW_IDR0); 246 PRINTREG32(regs, RTW_IDR1); 247 PRINTREG32(regs, RTW_MAR0); 248 PRINTREG32(regs, RTW_MAR1); 249 PRINTREG32(regs, RTW_TSFTRL); 250 PRINTREG32(regs, RTW_TSFTRH); 251 PRINTREG32(regs, RTW_TLPDA); 252 PRINTREG32(regs, RTW_TNPDA); 253 PRINTREG32(regs, RTW_THPDA); 254 PRINTREG32(regs, RTW_TCR); 255 PRINTREG32(regs, RTW_RCR); 256 PRINTREG32(regs, RTW_TINT); 257 PRINTREG32(regs, RTW_TBDA); 258 PRINTREG32(regs, RTW_ANAPARM); 259 PRINTREG32(regs, RTW_BB); 260 PRINTREG32(regs, RTW_PHYCFG); 261 PRINTREG32(regs, RTW_WAKEUP0L); 262 PRINTREG32(regs, RTW_WAKEUP0H); 263 PRINTREG32(regs, RTW_WAKEUP1L); 264 PRINTREG32(regs, RTW_WAKEUP1H); 265 PRINTREG32(regs, RTW_WAKEUP2LL); 266 PRINTREG32(regs, RTW_WAKEUP2LH); 267 PRINTREG32(regs, RTW_WAKEUP2HL); 268 PRINTREG32(regs, RTW_WAKEUP2HH); 269 PRINTREG32(regs, RTW_WAKEUP3LL); 270 PRINTREG32(regs, RTW_WAKEUP3LH); 271 PRINTREG32(regs, RTW_WAKEUP3HL); 272 PRINTREG32(regs, RTW_WAKEUP3HH); 273 PRINTREG32(regs, RTW_WAKEUP4LL); 274 PRINTREG32(regs, RTW_WAKEUP4LH); 275 PRINTREG32(regs, RTW_WAKEUP4HL); 276 PRINTREG32(regs, RTW_WAKEUP4HH); 277 PRINTREG32(regs, RTW_DK0); 278 PRINTREG32(regs, RTW_DK1); 279 PRINTREG32(regs, RTW_DK2); 280 PRINTREG32(regs, RTW_DK3); 281 PRINTREG32(regs, RTW_RETRYCTR); 282 PRINTREG32(regs, RTW_RDSAR); 283 PRINTREG32(regs, RTW_FER); 284 PRINTREG32(regs, RTW_FEMR); 285 PRINTREG32(regs, RTW_FPSR); 286 PRINTREG32(regs, RTW_FFER); 287 288 /* 16-bit registers */ 289 PRINTREG16(regs, RTW_BRSR); 290 PRINTREG16(regs, RTW_IMR); 291 PRINTREG16(regs, RTW_ISR); 292 PRINTREG16(regs, RTW_BCNITV); 293 PRINTREG16(regs, RTW_ATIMWND); 294 PRINTREG16(regs, RTW_BINTRITV); 295 PRINTREG16(regs, RTW_ATIMTRITV); 296 PRINTREG16(regs, RTW_CRC16ERR); 297 PRINTREG16(regs, RTW_CRC0); 298 PRINTREG16(regs, RTW_CRC1); 299 PRINTREG16(regs, RTW_CRC2); 300 PRINTREG16(regs, RTW_CRC3); 301 PRINTREG16(regs, RTW_CRC4); 302 PRINTREG16(regs, RTW_CWR); 303 304 /* 8-bit registers */ 305 PRINTREG8(regs, RTW_CR); 306 PRINTREG8(regs, RTW_9346CR); 307 PRINTREG8(regs, RTW_CONFIG0); 308 PRINTREG8(regs, RTW_CONFIG1); 309 PRINTREG8(regs, RTW_CONFIG2); 310 PRINTREG8(regs, RTW_MSR); 311 PRINTREG8(regs, RTW_CONFIG3); 312 PRINTREG8(regs, RTW_CONFIG4); 313 PRINTREG8(regs, RTW_TESTR); 314 PRINTREG8(regs, RTW_PSR); 315 PRINTREG8(regs, RTW_SCR); 316 PRINTREG8(regs, RTW_PHYDELAY); 317 PRINTREG8(regs, RTW_CRCOUNT); 318 PRINTREG8(regs, RTW_PHYADDR); 319 PRINTREG8(regs, RTW_PHYDATAW); 320 PRINTREG8(regs, RTW_PHYDATAR); 321 PRINTREG8(regs, RTW_CONFIG5); 322 PRINTREG8(regs, RTW_TPPOLL); 323 324 PRINTREG16(regs, RTW_BSSID16); 325 PRINTREG32(regs, RTW_BSSID32); 326 #undef PRINTREG32 327 #undef PRINTREG16 328 #undef PRINTREG8 329 } 330 #endif /* RTW_DEBUG */ 331 332 void 333 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 334 { 335 struct rtw_regs *regs = &sc->sc_regs; 336 337 u_int32_t tcr; 338 tcr = RTW_READ(regs, RTW_TCR); 339 tcr &= ~RTW_TCR_LBK_MASK; 340 if (enable) 341 tcr |= RTW_TCR_LBK_CONT; 342 else 343 tcr |= RTW_TCR_LBK_NORMAL; 344 RTW_WRITE(regs, RTW_TCR, tcr); 345 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 346 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 347 rtw_txdac_enable(sc, !enable); 348 rtw_set_access(sc, RTW_ACCESS_ANAPARM); /* XXX Voodoo from Linux. */ 349 rtw_set_access(sc, RTW_ACCESS_NONE); 350 } 351 352 static const char * 353 rtw_access_string(enum rtw_access access) 354 { 355 switch (access) { 356 case RTW_ACCESS_NONE: 357 return "none"; 358 case RTW_ACCESS_CONFIG: 359 return "config"; 360 case RTW_ACCESS_ANAPARM: 361 return "anaparm"; 362 default: 363 return "unknown"; 364 } 365 } 366 367 static void 368 rtw_set_access1(struct rtw_regs *regs, 369 enum rtw_access oaccess, enum rtw_access naccess) 370 { 371 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 372 KASSERT(oaccess >= RTW_ACCESS_NONE && oaccess <= RTW_ACCESS_ANAPARM); 373 374 if (naccess == oaccess) 375 return; 376 377 switch (naccess) { 378 case RTW_ACCESS_NONE: 379 switch (oaccess) { 380 case RTW_ACCESS_ANAPARM: 381 rtw_anaparm_enable(regs, 0); 382 /*FALLTHROUGH*/ 383 case RTW_ACCESS_CONFIG: 384 rtw_config0123_enable(regs, 0); 385 /*FALLTHROUGH*/ 386 case RTW_ACCESS_NONE: 387 break; 388 } 389 break; 390 case RTW_ACCESS_CONFIG: 391 switch (oaccess) { 392 case RTW_ACCESS_NONE: 393 rtw_config0123_enable(regs, 1); 394 /*FALLTHROUGH*/ 395 case RTW_ACCESS_CONFIG: 396 break; 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 break; 400 } 401 break; 402 case RTW_ACCESS_ANAPARM: 403 switch (oaccess) { 404 case RTW_ACCESS_NONE: 405 rtw_config0123_enable(regs, 1); 406 /*FALLTHROUGH*/ 407 case RTW_ACCESS_CONFIG: 408 rtw_anaparm_enable(regs, 1); 409 /*FALLTHROUGH*/ 410 case RTW_ACCESS_ANAPARM: 411 break; 412 } 413 break; 414 } 415 } 416 417 void 418 rtw_set_access(struct rtw_softc *sc, enum rtw_access access) 419 { 420 rtw_set_access1(&sc->sc_regs, sc->sc_access, access); 421 RTW_DPRINTF(("%s: access %s -> %s\n", sc->sc_dev.dv_xname, 422 rtw_access_string(sc->sc_access), 423 rtw_access_string(access))); 424 sc->sc_access = access; 425 } 426 427 /* 428 * Enable registers, switch register banks. 429 */ 430 void 431 rtw_config0123_enable(struct rtw_regs *regs, int enable) 432 { 433 u_int8_t ecr; 434 ecr = RTW_READ8(regs, RTW_9346CR); 435 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 436 if (enable) 437 ecr |= RTW_9346CR_EEM_CONFIG; 438 else { 439 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 440 ecr |= RTW_9346CR_EEM_NORMAL; 441 } 442 RTW_WRITE8(regs, RTW_9346CR, ecr); 443 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 444 } 445 446 /* requires rtw_config0123_enable(, 1) */ 447 void 448 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 449 { 450 u_int8_t cfg3; 451 452 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 453 cfg3 |= RTW_CONFIG3_CLKRUNEN; 454 if (enable) 455 cfg3 |= RTW_CONFIG3_PARMEN; 456 else 457 cfg3 &= ~RTW_CONFIG3_PARMEN; 458 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 459 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 460 } 461 462 /* requires rtw_anaparm_enable(, 1) */ 463 void 464 rtw_txdac_enable(struct rtw_softc *sc, int enable) 465 { 466 u_int32_t anaparm; 467 struct rtw_regs *regs = &sc->sc_regs; 468 469 anaparm = RTW_READ(regs, RTW_ANAPARM); 470 if (enable) 471 anaparm &= ~RTW_ANAPARM_TXDACOFF; 472 else 473 anaparm |= RTW_ANAPARM_TXDACOFF; 474 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 475 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 476 } 477 478 static __inline int 479 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 480 { 481 u_int8_t cr; 482 int i; 483 484 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 485 486 RTW_WBR(regs, RTW_CR, RTW_CR); 487 488 for (i = 0; i < 10000; i++) { 489 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 490 RTW_DPRINTF(("%s: reset in %dus\n", dvname, i)); 491 return 0; 492 } 493 RTW_RBR(regs, RTW_CR, RTW_CR); 494 DELAY(1); /* 1us */ 495 } 496 497 printf("%s: reset failed\n", dvname); 498 return ETIMEDOUT; 499 } 500 501 static __inline int 502 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 503 { 504 uint32_t tcr; 505 506 /* from Linux driver */ 507 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 508 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 509 510 RTW_WRITE(regs, RTW_TCR, tcr); 511 512 RTW_WBW(regs, RTW_CR, RTW_TCR); 513 514 return rtw_chip_reset1(regs, dvname); 515 } 516 517 static __inline int 518 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 519 { 520 int i; 521 u_int8_t ecr; 522 523 ecr = RTW_READ8(regs, RTW_9346CR); 524 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 525 RTW_WRITE8(regs, RTW_9346CR, ecr); 526 527 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 528 529 /* wait 2.5ms for completion */ 530 for (i = 0; i < 25; i++) { 531 ecr = RTW_READ8(regs, RTW_9346CR); 532 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 533 RTW_DPRINTF(("%s: recall EEPROM in %dus\n", dvname, 534 i * 100)); 535 return 0; 536 } 537 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 538 DELAY(100); 539 } 540 printf("%s: recall EEPROM failed\n", dvname); 541 return ETIMEDOUT; 542 } 543 544 static __inline int 545 rtw_reset(struct rtw_softc *sc) 546 { 547 int rc; 548 uint8_t config1; 549 550 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 551 return rc; 552 553 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 554 ; 555 556 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 557 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 558 /* TBD turn off maximum power saving? */ 559 560 return 0; 561 } 562 563 static __inline int 564 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txctl *descs, 565 u_int ndescs) 566 { 567 int i, rc = 0; 568 for (i = 0; i < ndescs; i++) { 569 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 570 0, 0, &descs[i].stx_dmamap); 571 if (rc != 0) 572 break; 573 } 574 return rc; 575 } 576 577 static __inline int 578 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 579 u_int ndescs) 580 { 581 int i, rc = 0; 582 for (i = 0; i < ndescs; i++) { 583 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 584 &descs[i].srx_dmamap); 585 if (rc != 0) 586 break; 587 } 588 return rc; 589 } 590 591 static __inline void 592 rtw_rxctls_setup(struct rtw_rxctl *descs) 593 { 594 int i; 595 for (i = 0; i < RTW_RXQLEN; i++) 596 descs[i].srx_mbuf = NULL; 597 } 598 599 static __inline void 600 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 601 u_int ndescs) 602 { 603 int i; 604 for (i = 0; i < ndescs; i++) { 605 if (descs[i].srx_dmamap != NULL) 606 bus_dmamap_destroy(dmat, descs[i].srx_dmamap); 607 } 608 } 609 610 static __inline void 611 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txctl *descs, 612 u_int ndescs) 613 { 614 int i; 615 for (i = 0; i < ndescs; i++) { 616 if (descs[i].stx_dmamap != NULL) 617 bus_dmamap_destroy(dmat, descs[i].stx_dmamap); 618 } 619 } 620 621 static __inline void 622 rtw_srom_free(struct rtw_srom *sr) 623 { 624 sr->sr_size = 0; 625 if (sr->sr_content == NULL) 626 return; 627 free(sr->sr_content, M_DEVBUF); 628 sr->sr_content = NULL; 629 } 630 631 static void 632 rtw_srom_defaults(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 633 enum rtw_rfchipid *rfchipid, u_int32_t *rcr) 634 { 635 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 636 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 637 *rcr |= RTW_RCR_ENCS1; 638 *rfchipid = RTW_RFCHIPID_PHILIPS; 639 } 640 641 static int 642 rtw_srom_parse(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 643 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, enum rtw_locale *locale, 644 const char *dvname) 645 { 646 int i; 647 const char *rfname, *paname; 648 char scratch[sizeof("unknown 0xXX")]; 649 u_int16_t version; 650 u_int8_t mac[IEEE80211_ADDR_LEN]; 651 652 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 653 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 654 655 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 656 printf("%s: SROM version %d.%d", dvname, version >> 8, version & 0xff); 657 658 if (version <= 0x0101) { 659 printf(" is not understood, limping along with defaults\n"); 660 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 661 return 0; 662 } 663 printf("\n"); 664 665 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 666 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 667 668 RTW_DPRINTF(("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 669 670 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 671 672 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 673 *flags |= RTW_F_ANTDIV; 674 675 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 676 * to be reversed. 677 */ 678 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 679 *flags |= RTW_F_DIGPHY; 680 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 681 *flags |= RTW_F_DFLANTB; 682 683 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 684 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 685 686 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 687 switch (*rfchipid) { 688 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 689 rfname = "GCT GRF5101"; 690 paname = "Winspring WS9901"; 691 break; 692 case RTW_RFCHIPID_MAXIM: 693 rfname = "Maxim MAX2820"; /* guess */ 694 paname = "Maxim MAX2422"; /* guess */ 695 break; 696 case RTW_RFCHIPID_INTERSIL: 697 rfname = "Intersil HFA3873"; /* guess */ 698 paname = "Intersil <unknown>"; 699 break; 700 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 701 rfname = "Philips SA2400A"; 702 paname = "Philips SA2411"; 703 break; 704 case RTW_RFCHIPID_RFMD: 705 /* this is the same front-end as an atw(4)! */ 706 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 707 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 708 "SYN: Silicon Labs Si4126"; /* inferred from 709 * reference driver 710 */ 711 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 712 break; 713 case RTW_RFCHIPID_RESERVED: 714 rfname = paname = "reserved"; 715 break; 716 default: 717 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 718 rfname = paname = scratch; 719 } 720 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 721 722 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 723 case RTW_CONFIG0_GL_USA: 724 *locale = RTW_LOCALE_USA; 725 break; 726 case RTW_CONFIG0_GL_EUROPE: 727 *locale = RTW_LOCALE_EUROPE; 728 break; 729 case RTW_CONFIG0_GL_JAPAN: 730 *locale = RTW_LOCALE_JAPAN; 731 break; 732 default: 733 *locale = RTW_LOCALE_UNKNOWN; 734 break; 735 } 736 return 0; 737 } 738 739 /* Returns -1 on failure. */ 740 static int 741 rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr, 742 const char *dvname) 743 { 744 int rc; 745 struct seeprom_descriptor sd; 746 u_int8_t ecr; 747 748 (void)memset(&sd, 0, sizeof(sd)); 749 750 ecr = RTW_READ8(regs, RTW_9346CR); 751 752 if ((flags & RTW_F_9356SROM) != 0) { 753 RTW_DPRINTF(("%s: 93c56 SROM\n", dvname)); 754 sr->sr_size = 256; 755 sd.sd_chip = C56_66; 756 } else { 757 RTW_DPRINTF(("%s: 93c46 SROM\n", dvname)); 758 sr->sr_size = 128; 759 sd.sd_chip = C46; 760 } 761 762 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 763 RTW_9346CR_EEM_MASK); 764 ecr |= RTW_9346CR_EEM_PROGRAM; 765 766 RTW_WRITE8(regs, RTW_9346CR, ecr); 767 768 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 769 770 if (sr->sr_content == NULL) { 771 printf("%s: unable to allocate SROM buffer\n", dvname); 772 return ENOMEM; 773 } 774 775 (void)memset(sr->sr_content, 0, sr->sr_size); 776 777 /* RTL8180 has a single 8-bit register for controlling the 778 * 93cx6 SROM. There is no "ready" bit. The RTL8180 779 * input/output sense is the reverse of read_seeprom's. 780 */ 781 sd.sd_tag = regs->r_bt; 782 sd.sd_bsh = regs->r_bh; 783 sd.sd_regsize = 1; 784 sd.sd_control_offset = RTW_9346CR; 785 sd.sd_status_offset = RTW_9346CR; 786 sd.sd_dataout_offset = RTW_9346CR; 787 sd.sd_CK = RTW_9346CR_EESK; 788 sd.sd_CS = RTW_9346CR_EECS; 789 sd.sd_DI = RTW_9346CR_EEDO; 790 sd.sd_DO = RTW_9346CR_EEDI; 791 /* make read_seeprom enter EEPROM read/write mode */ 792 sd.sd_MS = ecr; 793 sd.sd_RDY = 0; 794 #if 0 795 sd.sd_clkdelay = 50; 796 #endif 797 798 /* TBD bus barriers */ 799 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 800 printf("%s: could not read SROM\n", dvname); 801 free(sr->sr_content, M_DEVBUF); 802 sr->sr_content = NULL; 803 return -1; /* XXX */ 804 } 805 806 /* end EEPROM read/write mode */ 807 RTW_WRITE8(regs, RTW_9346CR, 808 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 809 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 810 811 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 812 return rc; 813 814 #ifdef RTW_DEBUG 815 { 816 int i; 817 RTW_DPRINTF(("\n%s: serial ROM:\n\t", dvname)); 818 for (i = 0; i < sr->sr_size/2; i++) { 819 if (((i % 8) == 0) && (i != 0)) 820 RTW_DPRINTF(("\n\t")); 821 RTW_DPRINTF((" %04x", sr->sr_content[i])); 822 } 823 RTW_DPRINTF(("\n")); 824 } 825 #endif /* RTW_DEBUG */ 826 return 0; 827 } 828 829 static void 830 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 831 const char *dvname) 832 { 833 u_int8_t cfg4; 834 const char *method; 835 836 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 837 838 switch (rfchipid) { 839 default: 840 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 841 method = "fallback"; 842 break; 843 case RTW_RFCHIPID_INTERSIL: 844 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 845 method = "Intersil"; 846 break; 847 case RTW_RFCHIPID_PHILIPS: 848 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 849 method = "Philips"; 850 break; 851 case RTW_RFCHIPID_RFMD: 852 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 853 method = "RFMD"; 854 break; 855 } 856 857 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 858 859 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 860 861 RTW_DPRINTF(("%s: %s RF programming method, %#02x\n", dvname, method, 862 RTW_READ8(regs, RTW_CONFIG4))); 863 } 864 865 #if 0 866 static __inline int 867 rtw_identify_rf(struct rtw_regs *regs, enum rtw_rftype *rftype, 868 const char *dvname) 869 { 870 u_int8_t cfg4; 871 const char *name; 872 873 cfg4 = RTW_READ8(regs, RTW_CONFIG4); 874 875 switch (cfg4 & RTW_CONFIG4_RFTYPE_MASK) { 876 case RTW_CONFIG4_RFTYPE_PHILIPS: 877 *rftype = RTW_RFTYPE_PHILIPS; 878 name = "Philips"; 879 break; 880 case RTW_CONFIG4_RFTYPE_INTERSIL: 881 *rftype = RTW_RFTYPE_INTERSIL; 882 name = "Intersil"; 883 break; 884 case RTW_CONFIG4_RFTYPE_RFMD: 885 *rftype = RTW_RFTYPE_RFMD; 886 name = "RFMD"; 887 break; 888 default: 889 name = "<unknown>"; 890 return ENXIO; 891 } 892 893 printf("%s: RF prog type %s\n", dvname, name); 894 return 0; 895 } 896 #endif 897 898 static __inline void 899 rtw_init_channels(enum rtw_locale locale, 900 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 901 const char *dvname) 902 { 903 int i; 904 const char *name = NULL; 905 #define ADD_CHANNEL(_chans, _chan) do { \ 906 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 907 (*_chans)[_chan].ic_freq = \ 908 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 909 } while (0) 910 911 switch (locale) { 912 case RTW_LOCALE_USA: /* 1-11 */ 913 name = "USA"; 914 for (i = 1; i <= 11; i++) 915 ADD_CHANNEL(chans, i); 916 break; 917 case RTW_LOCALE_JAPAN: /* 1-14 */ 918 name = "Japan"; 919 ADD_CHANNEL(chans, 14); 920 for (i = 1; i <= 14; i++) 921 ADD_CHANNEL(chans, i); 922 break; 923 case RTW_LOCALE_EUROPE: /* 1-13 */ 924 name = "Europe"; 925 for (i = 1; i <= 13; i++) 926 ADD_CHANNEL(chans, i); 927 break; 928 default: /* 10-11 allowed by most countries */ 929 name = "<unknown>"; 930 for (i = 10; i <= 11; i++) 931 ADD_CHANNEL(chans, i); 932 break; 933 } 934 printf("%s: Geographic Location %s\n", dvname, name); 935 #undef ADD_CHANNEL 936 } 937 938 static __inline void 939 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 940 const char *dvname) 941 { 942 u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 943 944 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 945 case RTW_CONFIG0_GL_USA: 946 *locale = RTW_LOCALE_USA; 947 break; 948 case RTW_CONFIG0_GL_JAPAN: 949 *locale = RTW_LOCALE_JAPAN; 950 break; 951 case RTW_CONFIG0_GL_EUROPE: 952 *locale = RTW_LOCALE_EUROPE; 953 break; 954 default: 955 *locale = RTW_LOCALE_UNKNOWN; 956 break; 957 } 958 } 959 960 static __inline int 961 rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN], 962 const char *dvname) 963 { 964 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 966 }; 967 u_int32_t idr0 = RTW_READ(regs, RTW_IDR0), 968 idr1 = RTW_READ(regs, RTW_IDR1); 969 970 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 971 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 972 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 973 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 974 975 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 976 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 977 978 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 979 printf("%s: could not get mac address, attach failed\n", 980 dvname); 981 return ENXIO; 982 } 983 984 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 985 986 return 0; 987 } 988 989 static u_int8_t 990 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 991 struct ieee80211_channel *chan) 992 { 993 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 994 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 995 ("%s: channel %d out of range", __func__, 996 idx - RTW_SR_TXPOWER1 + 1)); 997 return RTW_SR_GET(sr, idx); 998 } 999 1000 static void 1001 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *htcs) 1002 { 1003 int pri; 1004 u_int ndesc[RTW_NTXPRI] = 1005 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 1006 1007 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1008 htcs[pri].htc_nfree = ndesc[pri]; 1009 htcs[pri].htc_next = 0; 1010 } 1011 } 1012 1013 static int 1014 rtw_txctl_blk_init(struct rtw_txctl_blk *stc) 1015 { 1016 int i; 1017 struct rtw_txctl *stx; 1018 1019 SIMPLEQ_INIT(&stc->stc_dirtyq); 1020 SIMPLEQ_INIT(&stc->stc_freeq); 1021 for (i = 0; i < stc->stc_ndesc; i++) { 1022 stx = &stc->stc_desc[i]; 1023 stx->stx_mbuf = NULL; 1024 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1025 } 1026 return 0; 1027 } 1028 1029 static void 1030 rtw_txctl_blk_init_all(struct rtw_txctl_blk *stcs) 1031 { 1032 int pri; 1033 for (pri = 0; pri < RTW_NTXPRI; pri++) 1034 rtw_txctl_blk_init(&stcs[pri]); 1035 } 1036 1037 static __inline void 1038 rtw_rxdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, u_int desc0, u_int 1039 nsync, int ops) 1040 { 1041 /* sync to end of ring */ 1042 if (desc0 + nsync > RTW_NRXDESC) { 1043 bus_dmamap_sync(dmat, dmap, 1044 offsetof(struct rtw_descs, hd_rx[desc0]), 1045 sizeof(struct rtw_rxdesc) * (RTW_NRXDESC - desc0), ops); 1046 nsync -= (RTW_NRXDESC - desc0); 1047 desc0 = 0; 1048 } 1049 1050 /* sync what remains */ 1051 bus_dmamap_sync(dmat, dmap, 1052 offsetof(struct rtw_descs, hd_rx[desc0]), 1053 sizeof(struct rtw_rxdesc) * nsync, ops); 1054 } 1055 1056 static void 1057 rtw_txdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1058 struct rtw_txdesc_blk *htc, u_int desc0, u_int nsync, int ops) 1059 { 1060 /* sync to end of ring */ 1061 if (desc0 + nsync > htc->htc_ndesc) { 1062 bus_dmamap_sync(dmat, dmap, 1063 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1064 sizeof(struct rtw_txdesc) * (htc->htc_ndesc - desc0), 1065 ops); 1066 nsync -= (htc->htc_ndesc - desc0); 1067 desc0 = 0; 1068 } 1069 1070 /* sync what remains */ 1071 bus_dmamap_sync(dmat, dmap, 1072 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1073 sizeof(struct rtw_txdesc) * nsync, ops); 1074 } 1075 1076 static void 1077 rtw_txdescs_sync_all(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1078 struct rtw_txdesc_blk *htcs) 1079 { 1080 int pri; 1081 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1082 rtw_txdescs_sync(dmat, dmap, 1083 &htcs[pri], 0, htcs[pri].htc_ndesc, 1084 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1085 } 1086 } 1087 1088 static void 1089 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxctl *desc) 1090 { 1091 int i; 1092 struct rtw_rxctl *srx; 1093 1094 for (i = 0; i < RTW_NRXDESC; i++) { 1095 srx = &desc[i]; 1096 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, 1097 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1098 bus_dmamap_unload(dmat, srx->srx_dmamap); 1099 m_freem(srx->srx_mbuf); 1100 srx->srx_mbuf = NULL; 1101 } 1102 } 1103 1104 static __inline int 1105 rtw_rxbuf_alloc(bus_dma_tag_t dmat, struct rtw_rxctl *srx) 1106 { 1107 int rc; 1108 struct mbuf *m; 1109 1110 MGETHDR(m, M_DONTWAIT, MT_DATA); 1111 if (m == NULL) 1112 return ENOBUFS; 1113 1114 MCLGET(m, M_DONTWAIT); 1115 if (m == NULL) 1116 return ENOBUFS; 1117 1118 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1119 1120 if (srx->srx_mbuf != NULL) 1121 bus_dmamap_unload(dmat, srx->srx_dmamap); 1122 1123 srx->srx_mbuf = NULL; 1124 1125 rc = bus_dmamap_load_mbuf(dmat, srx->srx_dmamap, m, BUS_DMA_NOWAIT); 1126 if (rc != 0) { 1127 m_freem(m); 1128 return -1; 1129 } 1130 1131 srx->srx_mbuf = m; 1132 1133 return 0; 1134 } 1135 1136 static int 1137 rtw_rxctl_init_all(bus_dma_tag_t dmat, struct rtw_rxctl *desc, 1138 u_int *next, const char *dvname) 1139 { 1140 int i, rc; 1141 struct rtw_rxctl *srx; 1142 1143 for (i = 0; i < RTW_NRXDESC; i++) { 1144 srx = &desc[i]; 1145 if ((rc = rtw_rxbuf_alloc(dmat, srx)) == 0) 1146 continue; 1147 printf("%s: failed rtw_rxbuf_alloc after %d buffers, rc = %d\n", 1148 dvname, i, rc); 1149 if (i == 0) { 1150 rtw_rxbufs_release(dmat, desc); 1151 return rc; 1152 } 1153 } 1154 *next = 0; 1155 return 0; 1156 } 1157 1158 static __inline void 1159 rtw_rxdesc_init(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1160 struct rtw_rxdesc *hrx, struct rtw_rxctl *srx, int idx) 1161 { 1162 int is_last = (idx == RTW_NRXDESC - 1); 1163 uint32_t ctl; 1164 1165 hrx->hrx_buf = htole32(srx->srx_dmamap->dm_segs[0].ds_addr); 1166 1167 ctl = LSHIFT(srx->srx_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1168 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1169 1170 if (is_last) 1171 ctl |= RTW_RXCTL_EOR; 1172 1173 hrx->hrx_ctl = htole32(ctl); 1174 1175 /* sync the mbuf */ 1176 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, srx->srx_dmamap->dm_mapsize, 1177 BUS_DMASYNC_PREREAD); 1178 1179 /* sync the descriptor */ 1180 bus_dmamap_sync(dmat, dmam, RTW_DESC_OFFSET(hd_rx, idx), 1181 sizeof(struct rtw_rxdesc), 1182 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1183 } 1184 1185 static void 1186 rtw_rxdesc_init_all(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1187 struct rtw_rxdesc *desc, struct rtw_rxctl *ctl) 1188 { 1189 int i; 1190 struct rtw_rxdesc *hrx; 1191 struct rtw_rxctl *srx; 1192 1193 for (i = 0; i < RTW_NRXDESC; i++) { 1194 hrx = &desc[i]; 1195 srx = &ctl[i]; 1196 rtw_rxdesc_init(dmat, dmam, hrx, srx, i); 1197 } 1198 } 1199 1200 static void 1201 rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable) 1202 { 1203 u_int8_t cr; 1204 1205 RTW_DPRINTF(("%s: %s 0x%02x\n", __func__, 1206 enable ? "enable" : "disable", flags)); 1207 1208 cr = RTW_READ8(regs, RTW_CR); 1209 1210 /* XXX reference source does not enable MULRW */ 1211 #if 0 1212 /* enable PCI Read/Write Multiple */ 1213 cr |= RTW_CR_MULRW; 1214 #endif 1215 1216 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1217 if (enable) 1218 cr |= flags; 1219 else 1220 cr &= ~flags; 1221 RTW_WRITE8(regs, RTW_CR, cr); 1222 RTW_SYNC(regs, RTW_CR, RTW_CR); 1223 } 1224 1225 static void 1226 rtw_intr_rx(struct rtw_softc *sc, u_int16_t isr) 1227 { 1228 u_int next; 1229 int rate, rssi; 1230 u_int32_t hrssi, hstat, htsfth, htsftl; 1231 struct rtw_rxdesc *hrx; 1232 struct rtw_rxctl *srx; 1233 struct mbuf *m; 1234 1235 struct ieee80211_node *ni; 1236 struct ieee80211_frame *wh; 1237 1238 for (next = sc->sc_rxnext; ; next = (next + 1) % RTW_RXQLEN) { 1239 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1240 next, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1241 hrx = &sc->sc_rxdesc[next]; 1242 srx = &sc->sc_rxctl[next]; 1243 1244 hstat = le32toh(hrx->hrx_stat); 1245 hrssi = le32toh(hrx->hrx_rssi); 1246 htsfth = le32toh(hrx->hrx_tsfth); 1247 htsftl = le32toh(hrx->hrx_tsftl); 1248 1249 RTW_DPRINTF2(("%s: rxdesc[%d] hstat %08x hrssi %08x " 1250 "htsft %08x%08x\n", __func__, next, 1251 hstat, hrssi, htsfth, htsftl)); 1252 1253 if ((hstat & RTW_RXSTAT_OWN) != 0) /* belongs to NIC */ 1254 break; 1255 1256 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1257 printf("%s: DMA error/FIFO overflow %08x, " 1258 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1259 hstat & RTW_RXSTAT_IOERROR, next); 1260 goto next; 1261 } 1262 1263 switch (hstat & RTW_RXSTAT_RATE_MASK) { 1264 case RTW_RXSTAT_RATE_1MBPS: 1265 rate = 2; 1266 break; 1267 case RTW_RXSTAT_RATE_2MBPS: 1268 rate = 4; 1269 break; 1270 case RTW_RXSTAT_RATE_5MBPS: 1271 rate = 11; 1272 break; 1273 default: 1274 #ifdef RTW_DEBUG 1275 if (rtw_debug > 1) 1276 printf("%s: interpreting rate #%d as 11 MB/s\n", 1277 sc->sc_dev.dv_xname, 1278 MASK_AND_RSHIFT(hstat, 1279 RTW_RXSTAT_RATE_MASK)); 1280 #endif /* RTW_DEBUG */ 1281 /*FALLTHROUGH*/ 1282 case RTW_RXSTAT_RATE_11MBPS: 1283 rate = 22; 1284 break; 1285 } 1286 1287 #ifdef RTW_DEBUG 1288 #define PRINTSTAT(flag) do { \ 1289 if ((hstat & flag) != 0) { \ 1290 printf("%s" #flag, delim); \ 1291 delim = ","; \ 1292 } \ 1293 } while (0) 1294 if (rtw_debug > 1) { 1295 const char *delim = "<"; 1296 printf("%s: ", sc->sc_dev.dv_xname); 1297 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1298 printf("status %08x", hstat); 1299 PRINTSTAT(RTW_RXSTAT_SPLCP); 1300 PRINTSTAT(RTW_RXSTAT_MAR); 1301 PRINTSTAT(RTW_RXSTAT_PAR); 1302 PRINTSTAT(RTW_RXSTAT_BAR); 1303 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1304 PRINTSTAT(RTW_RXSTAT_CRC32); 1305 PRINTSTAT(RTW_RXSTAT_ICV); 1306 printf(">, "); 1307 } 1308 printf("rate %d.%d Mb/s, time %08x%08x\n", 1309 (rate * 5) / 10, (rate * 5) % 10, htsfth, htsftl); 1310 } 1311 #endif /* RTW_DEBUG */ 1312 1313 if ((hstat & RTW_RXSTAT_RES) != 0 && 1314 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1315 goto next; 1316 1317 /* if bad flags, skip descriptor */ 1318 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1319 printf("%s: too many rx segments\n", 1320 sc->sc_dev.dv_xname); 1321 goto next; 1322 } 1323 1324 bus_dmamap_sync(sc->sc_dmat, srx->srx_dmamap, 0, 1325 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1326 1327 m = srx->srx_mbuf; 1328 1329 /* if temporarily out of memory, re-use mbuf */ 1330 switch (rtw_rxbuf_alloc(sc->sc_dmat, srx)) { 1331 case 0: 1332 break; 1333 case ENOBUFS: 1334 printf("%s: rtw_rxbuf_alloc(, %d) failed, " 1335 "dropping this packet\n", sc->sc_dev.dv_xname, 1336 next); 1337 goto next; 1338 default: 1339 /* XXX shorten rx ring, instead? */ 1340 panic("%s: could not load DMA map\n", 1341 sc->sc_dev.dv_xname); 1342 } 1343 1344 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1345 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1346 else { 1347 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1348 /* TBD find out each front-end's LNA gain in the 1349 * front-end's units 1350 */ 1351 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1352 rssi |= 0x80; 1353 } 1354 1355 m->m_pkthdr.len = m->m_len = 1356 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1357 m->m_flags |= M_HASFCS; 1358 1359 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 1360 sc->sc_ic.ic_stats.is_rx_tooshort++; 1361 goto next; 1362 } 1363 wh = mtod(m, struct ieee80211_frame *); 1364 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1365 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1366 1367 sc->sc_tsfth = htsfth; 1368 1369 #ifdef RTW_DEBUG 1370 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 1371 (IFF_DEBUG|IFF_LINK2)) { 1372 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1373 rate, rssi); 1374 } 1375 #endif /* RTW_DEBUG */ 1376 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1377 ieee80211_release_node(&sc->sc_ic, ni); 1378 next: 1379 rtw_rxdesc_init(sc->sc_dmat, sc->sc_desc_dmamap, 1380 hrx, srx, next); 1381 } 1382 sc->sc_rxnext = next; 1383 1384 return; 1385 } 1386 1387 static void 1388 rtw_txbuf_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1389 struct rtw_txctl *stx) 1390 { 1391 struct mbuf *m; 1392 struct ieee80211_node *ni; 1393 bus_dmamap_t dmamap; 1394 1395 dmamap = stx->stx_dmamap; 1396 m = stx->stx_mbuf; 1397 ni = stx->stx_ni; 1398 stx->stx_dmamap = NULL; 1399 stx->stx_mbuf = NULL; 1400 stx->stx_ni = NULL; 1401 1402 bus_dmamap_sync(dmat, dmamap, 0, dmamap->dm_mapsize, 1403 BUS_DMASYNC_POSTWRITE); 1404 bus_dmamap_unload(dmat, dmamap); 1405 m_freem(m); 1406 ieee80211_release_node(ic, ni); 1407 } 1408 1409 static void 1410 rtw_txbufs_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1411 struct rtw_txctl_blk *stc) 1412 { 1413 struct rtw_txctl *stx; 1414 1415 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1416 rtw_txbuf_release(dmat, ic, stx); 1417 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1418 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1419 } 1420 } 1421 1422 static __inline void 1423 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *htc, 1424 struct rtw_txctl *stx, int ndesc) 1425 { 1426 uint32_t hstat; 1427 int data_retry, rts_retry; 1428 struct rtw_txdesc *htx0, *htxn; 1429 const char *condstring; 1430 1431 rtw_txbuf_release(sc->sc_dmat, &sc->sc_ic, stx); 1432 1433 htc->htc_nfree += ndesc; 1434 1435 htx0 = &htc->htc_desc[stx->stx_first]; 1436 htxn = &htc->htc_desc[stx->stx_last]; 1437 1438 hstat = le32toh(htx0->htx_stat); 1439 rts_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1440 data_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_DRC_MASK); 1441 1442 sc->sc_if.if_collisions += rts_retry + data_retry; 1443 1444 if ((hstat & RTW_TXSTAT_TOK) != 0) 1445 condstring = "ok"; 1446 else { 1447 sc->sc_if.if_oerrors++; 1448 condstring = "error"; 1449 } 1450 1451 DPRINTF2(sc, ("%s: stx %p txdesc[%d, %d] %s tries rts %u data %u\n", 1452 sc->sc_dev.dv_xname, stx, stx->stx_first, stx->stx_last, 1453 condstring, rts_retry, data_retry)); 1454 } 1455 1456 /* Collect transmitted packets. */ 1457 static __inline void 1458 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txctl_blk *stc, 1459 struct rtw_txdesc_blk *htc) 1460 { 1461 int ndesc; 1462 struct rtw_txctl *stx; 1463 1464 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1465 ndesc = 1 + stx->stx_last - stx->stx_first; 1466 if (stx->stx_last < stx->stx_first) 1467 ndesc += htc->htc_ndesc; 1468 1469 KASSERT(ndesc > 0); 1470 1471 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, htc, 1472 stx->stx_first, ndesc, 1473 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1474 1475 if ((htc->htc_desc[stx->stx_first].htx_stat & 1476 htole32(RTW_TXSTAT_OWN)) != 0) 1477 break; 1478 1479 rtw_collect_txpkt(sc, htc, stx, ndesc); 1480 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1481 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1482 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1483 } 1484 if (stx == NULL) 1485 stc->stc_tx_timer = 0; 1486 } 1487 1488 static void 1489 rtw_intr_tx(struct rtw_softc *sc, u_int16_t isr) 1490 { 1491 int pri; 1492 struct rtw_txctl_blk *stc; 1493 struct rtw_txdesc_blk *htc; 1494 1495 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1496 stc = &sc->sc_txctl_blk[pri]; 1497 htc = &sc->sc_txdesc_blk[pri]; 1498 1499 rtw_collect_txring(sc, stc, htc); 1500 1501 rtw_start(&sc->sc_if); 1502 } 1503 1504 /* TBD */ 1505 return; 1506 } 1507 1508 static void 1509 rtw_intr_beacon(struct rtw_softc *sc, u_int16_t isr) 1510 { 1511 /* TBD */ 1512 return; 1513 } 1514 1515 static void 1516 rtw_intr_atim(struct rtw_softc *sc) 1517 { 1518 /* TBD */ 1519 return; 1520 } 1521 1522 static void 1523 rtw_hwring_setup(struct rtw_softc *sc) 1524 { 1525 struct rtw_regs *regs = &sc->sc_regs; 1526 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1527 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1528 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1529 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1530 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1531 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1532 } 1533 1534 static void 1535 rtw_swring_setup(struct rtw_softc *sc) 1536 { 1537 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1538 1539 rtw_txctl_blk_init_all(&sc->sc_txctl_blk[0]); 1540 1541 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1542 0, RTW_NRXDESC, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1543 rtw_rxctl_init_all(sc->sc_dmat, sc->sc_rxctl, &sc->sc_rxnext, 1544 sc->sc_dev.dv_xname); 1545 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, 1546 sc->sc_rxdesc, sc->sc_rxctl); 1547 1548 rtw_txdescs_sync_all(sc->sc_dmat, sc->sc_desc_dmamap, 1549 &sc->sc_txdesc_blk[0]); 1550 #if 0 /* redundant with rtw_rxdesc_init_all */ 1551 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1552 0, RTW_NRXDESC, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1553 #endif 1554 } 1555 1556 static void 1557 rtw_kick(struct rtw_softc *sc) 1558 { 1559 int pri; 1560 struct rtw_regs *regs = &sc->sc_regs; 1561 1562 RTW_WRITE16(regs, RTW_IMR, 0); 1563 RTW_WBW(regs, RTW_IMR, RTW_TPPOLL); 1564 1565 RTW_WRITE8(regs, RTW_TPPOLL, 1566 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ|RTW_TPPOLL_SLPQ); 1567 1568 RTW_SYNC(regs, RTW_TPPOLL, RTW_TPPOLL); 1569 1570 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1571 1572 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1573 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1574 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1575 &sc->sc_txctl_blk[pri]); 1576 } 1577 rtw_swring_setup(sc); 1578 rtw_hwring_setup(sc); 1579 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1580 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1581 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1582 } 1583 1584 static void 1585 rtw_intr_ioerror(struct rtw_softc *sc, u_int16_t isr) 1586 { 1587 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) 1588 rtw_kick(sc); 1589 if ((isr & RTW_INTR_TXFOVW) != 0) 1590 ; /* TBD restart transmit engine */ 1591 return; 1592 } 1593 1594 static __inline void 1595 rtw_suspend_ticks(struct rtw_softc *sc) 1596 { 1597 RTW_DPRINTF2(("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 1598 sc->sc_do_tick = 0; 1599 } 1600 1601 static __inline void 1602 rtw_resume_ticks(struct rtw_softc *sc) 1603 { 1604 u_int32_t tsftrl0, tsftrl1, next_tick; 1605 1606 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1607 1608 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1609 next_tick = tsftrl1 + 1000000; 1610 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1611 1612 sc->sc_do_tick = 1; 1613 1614 RTW_DPRINTF2(("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1615 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 1616 } 1617 1618 static void 1619 rtw_intr_timeout(struct rtw_softc *sc) 1620 { 1621 RTW_DPRINTF2(("%s: timeout\n", sc->sc_dev.dv_xname)); 1622 if (sc->sc_do_tick) 1623 rtw_resume_ticks(sc); 1624 return; 1625 } 1626 1627 int 1628 rtw_intr(void *arg) 1629 { 1630 int i; 1631 struct rtw_softc *sc = arg; 1632 struct rtw_regs *regs = &sc->sc_regs; 1633 u_int16_t isr; 1634 1635 /* 1636 * If the interface isn't running, the interrupt couldn't 1637 * possibly have come from us. 1638 */ 1639 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1640 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1641 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1642 RTW_DPRINTF2(("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1643 return (0); 1644 } 1645 1646 for (i = 0; i < 10; i++) { 1647 isr = RTW_READ16(regs, RTW_ISR); 1648 1649 RTW_WRITE16(regs, RTW_ISR, isr); 1650 RTW_WBR(regs, RTW_ISR, RTW_ISR); 1651 1652 if (sc->sc_intr_ack != NULL) 1653 (*sc->sc_intr_ack)(regs); 1654 1655 if (isr == 0) 1656 break; 1657 1658 #ifdef RTW_DEBUG 1659 #define PRINTINTR(flag) do { \ 1660 if ((isr & flag) != 0) { \ 1661 printf("%s" #flag, delim); \ 1662 delim = ","; \ 1663 } \ 1664 } while (0) 1665 1666 if (rtw_debug > 1 && isr != 0) { 1667 const char *delim = "<"; 1668 1669 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1670 1671 PRINTINTR(RTW_INTR_TXFOVW); 1672 PRINTINTR(RTW_INTR_TIMEOUT); 1673 PRINTINTR(RTW_INTR_BCNINT); 1674 PRINTINTR(RTW_INTR_ATIMINT); 1675 PRINTINTR(RTW_INTR_TBDER); 1676 PRINTINTR(RTW_INTR_TBDOK); 1677 PRINTINTR(RTW_INTR_THPDER); 1678 PRINTINTR(RTW_INTR_THPDOK); 1679 PRINTINTR(RTW_INTR_TNPDER); 1680 PRINTINTR(RTW_INTR_TNPDOK); 1681 PRINTINTR(RTW_INTR_RXFOVW); 1682 PRINTINTR(RTW_INTR_RDU); 1683 PRINTINTR(RTW_INTR_TLPDER); 1684 PRINTINTR(RTW_INTR_TLPDOK); 1685 PRINTINTR(RTW_INTR_RER); 1686 PRINTINTR(RTW_INTR_ROK); 1687 1688 printf(">\n"); 1689 } 1690 #undef PRINTINTR 1691 #endif /* RTW_DEBUG */ 1692 1693 if ((isr & RTW_INTR_RX) != 0) 1694 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1695 if ((isr & RTW_INTR_TX) != 0) 1696 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1697 if ((isr & RTW_INTR_BEACON) != 0) 1698 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1699 if ((isr & RTW_INTR_ATIMINT) != 0) 1700 rtw_intr_atim(sc); 1701 if ((isr & RTW_INTR_IOERROR) != 0) 1702 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1703 if ((isr & RTW_INTR_TIMEOUT) != 0) 1704 rtw_intr_timeout(sc); 1705 } 1706 1707 return 1; 1708 } 1709 1710 static void 1711 rtw_stop(struct ifnet *ifp, int disable) 1712 { 1713 int pri, s; 1714 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1715 struct ieee80211com *ic = &sc->sc_ic; 1716 struct rtw_regs *regs = &sc->sc_regs; 1717 1718 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1719 return; 1720 1721 rtw_suspend_ticks(sc); 1722 1723 s = splnet(); 1724 1725 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1726 1727 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1728 /* Disable interrupts. */ 1729 RTW_WRITE16(regs, RTW_IMR, 0); 1730 1731 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 1732 1733 /* Stop the transmit and receive processes. First stop DMA, 1734 * then disable receiver and transmitter. 1735 */ 1736 RTW_WRITE8(regs, RTW_TPPOLL, 1737 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ| 1738 RTW_TPPOLL_SLPQ); 1739 1740 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 1741 1742 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1743 } 1744 1745 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1746 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1747 &sc->sc_txctl_blk[pri]); 1748 } 1749 1750 if (disable) { 1751 rtw_disable(sc); 1752 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1753 } 1754 1755 /* Mark the interface as not running. Cancel the watchdog timer. */ 1756 ifp->if_flags &= ~IFF_RUNNING; 1757 ifp->if_timer = 0; 1758 1759 splx(s); 1760 1761 return; 1762 } 1763 1764 const char * 1765 rtw_pwrstate_string(enum rtw_pwrstate power) 1766 { 1767 switch (power) { 1768 case RTW_ON: 1769 return "on"; 1770 case RTW_SLEEP: 1771 return "sleep"; 1772 case RTW_OFF: 1773 return "off"; 1774 default: 1775 return "unknown"; 1776 } 1777 } 1778 1779 /* XXX For Maxim, I am using the RFMD settings gleaned from the 1780 * reference driver, plus a magic Maxim "ON" value that comes from 1781 * the Realtek document "Windows PG for Rtl8180." 1782 */ 1783 static void 1784 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1785 int before_rf, int digphy) 1786 { 1787 u_int32_t anaparm; 1788 1789 anaparm = RTW_READ(regs, RTW_ANAPARM); 1790 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1791 1792 switch (power) { 1793 case RTW_OFF: 1794 if (before_rf) 1795 return; 1796 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 1797 anaparm |= RTW_ANAPARM_TXDACOFF; 1798 break; 1799 case RTW_SLEEP: 1800 if (!before_rf) 1801 return; 1802 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 1803 anaparm |= RTW_ANAPARM_TXDACOFF; 1804 break; 1805 case RTW_ON: 1806 if (!before_rf) 1807 return; 1808 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 1809 break; 1810 } 1811 RTW_DPRINTF(("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 1812 __func__, rtw_pwrstate_string(power), 1813 (before_rf) ? "before" : "after", anaparm)); 1814 1815 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1816 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1817 } 1818 1819 /* XXX I am using the RFMD settings gleaned from the reference 1820 * driver. They agree 1821 */ 1822 static void 1823 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1824 int before_rf, int digphy) 1825 { 1826 u_int32_t anaparm; 1827 1828 anaparm = RTW_READ(regs, RTW_ANAPARM); 1829 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1830 1831 switch (power) { 1832 case RTW_OFF: 1833 if (before_rf) 1834 return; 1835 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 1836 anaparm |= RTW_ANAPARM_TXDACOFF; 1837 break; 1838 case RTW_SLEEP: 1839 if (!before_rf) 1840 return; 1841 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 1842 anaparm |= RTW_ANAPARM_TXDACOFF; 1843 break; 1844 case RTW_ON: 1845 if (!before_rf) 1846 return; 1847 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 1848 break; 1849 } 1850 RTW_DPRINTF(("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 1851 __func__, rtw_pwrstate_string(power), 1852 (before_rf) ? "before" : "after", anaparm)); 1853 1854 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1855 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1856 } 1857 1858 static void 1859 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1860 int before_rf, int digphy) 1861 { 1862 u_int32_t anaparm; 1863 1864 anaparm = RTW_READ(regs, RTW_ANAPARM); 1865 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1866 1867 switch (power) { 1868 case RTW_OFF: 1869 if (before_rf) 1870 return; 1871 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 1872 anaparm |= RTW_ANAPARM_TXDACOFF; 1873 break; 1874 case RTW_SLEEP: 1875 if (!before_rf) 1876 return; 1877 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 1878 anaparm |= RTW_ANAPARM_TXDACOFF; 1879 break; 1880 case RTW_ON: 1881 if (!before_rf) 1882 return; 1883 if (digphy) { 1884 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 1885 /* XXX guess */ 1886 anaparm |= RTW_ANAPARM_TXDACOFF; 1887 } else 1888 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 1889 break; 1890 } 1891 RTW_DPRINTF(("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 1892 __func__, rtw_pwrstate_string(power), 1893 (before_rf) ? "before" : "after", anaparm)); 1894 1895 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1896 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1897 } 1898 1899 static void 1900 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 1901 int digphy) 1902 { 1903 struct rtw_regs *regs = &sc->sc_regs; 1904 1905 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 1906 1907 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 1908 1909 rtw_set_access(sc, RTW_ACCESS_NONE); 1910 1911 return; 1912 } 1913 1914 static int 1915 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 1916 { 1917 int rc; 1918 1919 RTW_DPRINTF2(("%s: %s->%s\n", __func__, 1920 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 1921 1922 if (sc->sc_pwrstate == power) 1923 return 0; 1924 1925 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 1926 rc = rtw_rf_pwrstate(sc->sc_rf, power); 1927 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 1928 1929 switch (power) { 1930 case RTW_ON: 1931 /* TBD set LEDs */ 1932 break; 1933 case RTW_SLEEP: 1934 /* TBD */ 1935 break; 1936 case RTW_OFF: 1937 /* TBD */ 1938 break; 1939 } 1940 if (rc == 0) 1941 sc->sc_pwrstate = power; 1942 else 1943 sc->sc_pwrstate = RTW_OFF; 1944 return rc; 1945 } 1946 1947 static int 1948 rtw_tune(struct rtw_softc *sc) 1949 { 1950 struct ieee80211com *ic = &sc->sc_ic; 1951 u_int chan; 1952 int rc; 1953 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 1954 dflantb = sc->sc_flags & RTW_F_DFLANTB; 1955 1956 KASSERT(ic->ic_bss->ni_chan != NULL); 1957 1958 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1959 if (chan == IEEE80211_CHAN_ANY) 1960 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1961 1962 if (chan == sc->sc_cur_chan) { 1963 RTW_DPRINTF(("%s: already tuned chan #%d\n", __func__, chan)); 1964 return 0; 1965 } 1966 1967 rtw_suspend_ticks(sc); 1968 1969 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 1970 1971 /* TBD wait for Tx to complete */ 1972 1973 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 1974 1975 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 1976 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 1977 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 1978 dflantb, RTW_ON)) != 0) { 1979 /* XXX condition on powersaving */ 1980 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 1981 } 1982 1983 sc->sc_cur_chan = chan; 1984 1985 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 1986 1987 rtw_resume_ticks(sc); 1988 1989 return rc; 1990 } 1991 1992 void 1993 rtw_disable(struct rtw_softc *sc) 1994 { 1995 int rc; 1996 1997 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1998 return; 1999 2000 /* turn off PHY */ 2001 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2002 printf("%s: failed to turn off PHY (%d)\n", 2003 sc->sc_dev.dv_xname, rc); 2004 2005 if (sc->sc_disable != NULL) 2006 (*sc->sc_disable)(sc); 2007 2008 sc->sc_flags &= ~RTW_F_ENABLED; 2009 } 2010 2011 int 2012 rtw_enable(struct rtw_softc *sc) 2013 { 2014 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2015 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2016 printf("%s: device enable failed\n", 2017 sc->sc_dev.dv_xname); 2018 return (EIO); 2019 } 2020 sc->sc_flags |= RTW_F_ENABLED; 2021 } 2022 return (0); 2023 } 2024 2025 static void 2026 rtw_transmit_config(struct rtw_regs *regs) 2027 { 2028 u_int32_t tcr; 2029 2030 tcr = RTW_READ(regs, RTW_TCR); 2031 2032 tcr |= RTW_TCR_CWMIN; 2033 tcr &= ~RTW_TCR_MXDMA_MASK; 2034 tcr |= RTW_TCR_MXDMA_256; 2035 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2036 tcr &= ~RTW_TCR_LBK_MASK; 2037 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2038 2039 /* set short/long retry limits */ 2040 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2041 tcr |= LSHIFT(4, RTW_TCR_SRL_MASK) | LSHIFT(4, RTW_TCR_LRL_MASK); 2042 2043 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2044 2045 RTW_WRITE(regs, RTW_TCR, tcr); 2046 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2047 } 2048 2049 static __inline void 2050 rtw_enable_interrupts(struct rtw_softc *sc) 2051 { 2052 struct rtw_regs *regs = &sc->sc_regs; 2053 2054 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2055 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2056 2057 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2058 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2059 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2060 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2061 2062 /* XXX necessary? */ 2063 if (sc->sc_intr_ack != NULL) 2064 (*sc->sc_intr_ack)(regs); 2065 } 2066 2067 static void 2068 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2069 { 2070 uint8_t msr; 2071 2072 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2073 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2074 2075 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2076 2077 switch (opmode) { 2078 case IEEE80211_M_AHDEMO: 2079 case IEEE80211_M_IBSS: 2080 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2081 break; 2082 case IEEE80211_M_HOSTAP: 2083 msr |= RTW_MSR_NETYPE_AP_OK; 2084 break; 2085 case IEEE80211_M_MONITOR: 2086 /* XXX */ 2087 msr |= RTW_MSR_NETYPE_NOLINK; 2088 break; 2089 case IEEE80211_M_STA: 2090 msr |= RTW_MSR_NETYPE_INFRA_OK; 2091 break; 2092 } 2093 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2094 2095 rtw_set_access(sc, RTW_ACCESS_NONE); 2096 } 2097 2098 /* XXX is the endianness correct? test. */ 2099 #define rtw_calchash(addr) \ 2100 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 2101 2102 static void 2103 rtw_pktfilt_load(struct rtw_softc *sc) 2104 { 2105 struct rtw_regs *regs = &sc->sc_regs; 2106 struct ieee80211com *ic = &sc->sc_ic; 2107 struct ethercom *ec = &ic->ic_ec; 2108 struct ifnet *ifp = &sc->sc_ic.ic_if; 2109 int hash; 2110 u_int32_t hashes[2] = { 0, 0 }; 2111 struct ether_multi *enm; 2112 struct ether_multistep step; 2113 2114 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2115 2116 #define RTW_RCR_MONITOR (RTW_RCR_ACRC32|RTW_RCR_APM|RTW_RCR_AAP|RTW_RCR_AB|RTW_RCR_ACF | RTW_RCR_AICV | RTW_RCR_ACRC32) 2117 2118 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2119 sc->sc_rcr |= RTW_RCR_MONITOR; 2120 else 2121 sc->sc_rcr &= ~RTW_RCR_MONITOR; 2122 2123 /* XXX reference sources BEGIN */ 2124 sc->sc_rcr |= RTW_RCR_ENMARP; 2125 sc->sc_rcr |= RTW_RCR_AB | RTW_RCR_AM | RTW_RCR_APM; 2126 #if 0 2127 /* receive broadcasts in our BSS */ 2128 sc->sc_rcr |= RTW_RCR_ADD3; 2129 #endif 2130 /* XXX reference sources END */ 2131 2132 /* receive pwrmgmt frames. */ 2133 sc->sc_rcr |= RTW_RCR_APWRMGT; 2134 /* receive mgmt/ctrl/data frames. */ 2135 sc->sc_rcr |= RTW_RCR_ADF | RTW_RCR_AMF; 2136 /* initialize Rx DMA threshold, Tx DMA burst size */ 2137 sc->sc_rcr |= RTW_RCR_RXFTH_WHOLE | RTW_RCR_MXDMA_1024; 2138 2139 ifp->if_flags &= ~IFF_ALLMULTI; 2140 2141 if (ifp->if_flags & IFF_PROMISC) { 2142 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2143 allmulti: 2144 ifp->if_flags |= IFF_ALLMULTI; 2145 goto setit; 2146 } 2147 2148 /* 2149 * Program the 64-bit multicast hash filter. 2150 */ 2151 ETHER_FIRST_MULTI(step, ec, enm); 2152 while (enm != NULL) { 2153 /* XXX */ 2154 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2155 ETHER_ADDR_LEN) != 0) 2156 goto allmulti; 2157 2158 hash = rtw_calchash(enm->enm_addrlo); 2159 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2160 ETHER_NEXT_MULTI(step, enm); 2161 } 2162 2163 if (ifp->if_flags & IFF_BROADCAST) { 2164 hash = rtw_calchash(etherbroadcastaddr); 2165 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2166 } 2167 2168 /* all bits set => hash is useless */ 2169 if (~(hashes[0] & hashes[1]) == 0) 2170 goto allmulti; 2171 2172 setit: 2173 if (ifp->if_flags & IFF_ALLMULTI) 2174 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2175 2176 if (ic->ic_state == IEEE80211_S_SCAN) 2177 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2178 2179 hashes[0] = hashes[1] = 0xffffffff; 2180 2181 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2182 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2183 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2184 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2185 2186 DPRINTF(sc, ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2187 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2188 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2189 2190 return; 2191 } 2192 2193 static int 2194 rtw_init(struct ifnet *ifp) 2195 { 2196 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2197 struct ieee80211com *ic = &sc->sc_ic; 2198 struct rtw_regs *regs = &sc->sc_regs; 2199 int rc = 0; 2200 2201 if ((rc = rtw_enable(sc)) != 0) 2202 goto out; 2203 2204 /* Cancel pending I/O and reset. */ 2205 rtw_stop(ifp, 0); 2206 2207 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2208 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 2209 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2210 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2211 2212 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2213 goto out; 2214 2215 rtw_swring_setup(sc); 2216 2217 rtw_transmit_config(regs); 2218 2219 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2220 2221 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2222 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2223 2224 /* long PLCP header, 1Mbps basic rate */ 2225 RTW_WRITE16(regs, RTW_BRSR, 0x0f); 2226 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2227 2228 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 2229 rtw_set_access(sc, RTW_ACCESS_NONE); 2230 2231 #if 0 2232 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_GWAKE|RTW_FEMR_WKUP|RTW_FEMR_INTR); 2233 #endif 2234 /* XXX from reference sources */ 2235 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2236 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2237 2238 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2239 2240 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2241 /* from Linux driver */ 2242 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2243 2244 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2245 2246 rtw_enable_interrupts(sc); 2247 2248 rtw_pktfilt_load(sc); 2249 2250 rtw_hwring_setup(sc); 2251 2252 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2253 2254 ifp->if_flags |= IFF_RUNNING; 2255 ic->ic_state = IEEE80211_S_INIT; 2256 2257 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2258 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2259 2260 rtw_resume_ticks(sc); 2261 2262 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2263 2264 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2265 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2266 else 2267 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2268 2269 out: 2270 return rc; 2271 } 2272 2273 static int 2274 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2275 { 2276 int rc = 0; 2277 struct rtw_softc *sc = ifp->if_softc; 2278 struct ifreq *ifr = (struct ifreq *)data; 2279 2280 switch (cmd) { 2281 case SIOCSIFFLAGS: 2282 if ((ifp->if_flags & IFF_UP) != 0) { 2283 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2284 rtw_pktfilt_load(sc); 2285 } else 2286 rc = rtw_init(ifp); 2287 #ifdef RTW_DEBUG 2288 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2289 #endif /* RTW_DEBUG */ 2290 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2291 #ifdef RTW_DEBUG 2292 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2293 #endif /* RTW_DEBUG */ 2294 rtw_stop(ifp, 1); 2295 } 2296 break; 2297 case SIOCADDMULTI: 2298 case SIOCDELMULTI: 2299 if (cmd == SIOCADDMULTI) 2300 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2301 else 2302 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2303 if (rc == ENETRESET) { 2304 if (ifp->if_flags & IFF_RUNNING) 2305 rtw_pktfilt_load(sc); 2306 rc = 0; 2307 } 2308 break; 2309 default: 2310 if ((rc = ieee80211_ioctl(ifp, cmd, data)) == ENETRESET) { 2311 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2312 rc = rtw_init(ifp); 2313 else 2314 rc = 0; 2315 } 2316 break; 2317 } 2318 return rc; 2319 } 2320 2321 /* Point *mp at the next 802.11 frame to transmit. Point *stcp 2322 * at the driver's selection of transmit control block for the packet. 2323 */ 2324 static __inline int 2325 rtw_dequeue(struct ifnet *ifp, struct rtw_txctl_blk **stcp, 2326 struct rtw_txdesc_blk **htcp, struct mbuf **mp, 2327 struct ieee80211_node **nip) 2328 { 2329 struct rtw_txctl_blk *stc; 2330 struct rtw_txdesc_blk *htc; 2331 struct mbuf *m0; 2332 struct rtw_softc *sc; 2333 struct ieee80211com *ic; 2334 2335 sc = (struct rtw_softc *)ifp->if_softc; 2336 2337 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2338 *mp = NULL; 2339 2340 stc = &sc->sc_txctl_blk[RTW_TXPRIMD]; 2341 htc = &sc->sc_txdesc_blk[RTW_TXPRIMD]; 2342 2343 if (SIMPLEQ_EMPTY(&stc->stc_freeq) || htc->htc_nfree == 0) { 2344 DPRINTF2(sc, ("%s: out of descriptors\n", __func__)); 2345 ifp->if_flags |= IFF_OACTIVE; 2346 return 0; 2347 } 2348 2349 ic = &sc->sc_ic; 2350 2351 if (!IF_IS_EMPTY(&ic->ic_mgtq)) { 2352 IF_DEQUEUE(&ic->ic_mgtq, m0); 2353 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2354 m0->m_pkthdr.rcvif = NULL; 2355 DPRINTF2(sc, ("%s: dequeue mgt frame\n", __func__)); 2356 } else if (ic->ic_state != IEEE80211_S_RUN) { 2357 DPRINTF2(sc, ("%s: not running\n", __func__)); 2358 return 0; 2359 } else if (!IF_IS_EMPTY(&ic->ic_pwrsaveq)) { 2360 IF_DEQUEUE(&ic->ic_pwrsaveq, m0); 2361 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2362 m0->m_pkthdr.rcvif = NULL; 2363 DPRINTF2(sc, ("%s: dequeue pwrsave frame\n", __func__)); 2364 } else { 2365 IFQ_POLL(&ifp->if_snd, m0); 2366 if (m0 == NULL) { 2367 DPRINTF2(sc, ("%s: no frame\n", __func__)); 2368 return 0; 2369 } 2370 DPRINTF2(sc, ("%s: dequeue data frame\n", __func__)); 2371 IFQ_DEQUEUE(&ifp->if_snd, m0); 2372 ifp->if_opackets++; 2373 #if NBPFILTER > 0 2374 if (ifp->if_bpf) 2375 bpf_mtap(ifp->if_bpf, m0); 2376 #endif 2377 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2378 DPRINTF2(sc, ("%s: encap error\n", __func__)); 2379 ifp->if_oerrors++; 2380 return -1; 2381 } 2382 } 2383 DPRINTF2(sc, ("%s: leave\n", __func__)); 2384 *stcp = stc; 2385 *htcp = htc; 2386 *mp = m0; 2387 return 0; 2388 } 2389 2390 /* TBD factor with atw_start */ 2391 static struct mbuf * 2392 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2393 u_int ndescfree, short *ifflagsp, const char *dvname) 2394 { 2395 int first, rc; 2396 struct mbuf *m, *m0; 2397 2398 m0 = chain; 2399 2400 /* 2401 * Load the DMA map. Copy and try (once) again if the packet 2402 * didn't fit in the alloted number of segments. 2403 */ 2404 for (first = 1; 2405 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2406 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2407 dmam->dm_nsegs > ndescfree) && first; 2408 first = 0) { 2409 if (rc == 0) 2410 bus_dmamap_unload(dmat, dmam); 2411 MGETHDR(m, M_DONTWAIT, MT_DATA); 2412 if (m == NULL) { 2413 printf("%s: unable to allocate Tx mbuf\n", 2414 dvname); 2415 break; 2416 } 2417 if (m0->m_pkthdr.len > MHLEN) { 2418 MCLGET(m, M_DONTWAIT); 2419 if ((m->m_flags & M_EXT) == 0) { 2420 printf("%s: cannot allocate Tx cluster\n", 2421 dvname); 2422 m_freem(m); 2423 break; 2424 } 2425 } 2426 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2427 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 2428 m_freem(m0); 2429 m0 = m; 2430 m = NULL; 2431 } 2432 if (rc != 0) { 2433 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 2434 m_freem(m0); 2435 return NULL; 2436 } else if (dmam->dm_nsegs > ndescfree) { 2437 *ifflagsp |= IFF_OACTIVE; 2438 bus_dmamap_unload(dmat, dmam); 2439 m_freem(m0); 2440 return NULL; 2441 } 2442 return m0; 2443 } 2444 2445 static void 2446 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 2447 struct rtw_txctl *stx, struct rtw_txdesc_blk *htc, int desc) 2448 { 2449 struct rtw_txdesc *htx = &htc->htc_desc[desc]; 2450 DPRINTF2(sc, ("%s: stx %p %s txdesc[%d] ctl0 %#08x " 2451 "ctl1 %#08x buf %#08x len %#08x\n", 2452 sc->sc_dev.dv_xname, stx, action, desc, 2453 le32toh(htx->htx_ctl0), 2454 le32toh(htx->htx_ctl1), le32toh(htx->htx_buf), 2455 le32toh(htx->htx_len))); 2456 } 2457 2458 static void 2459 rtw_start(struct ifnet *ifp) 2460 { 2461 uint8_t tppoll; 2462 int desc, i, lastdesc, npkt, rate; 2463 uint32_t proto_ctl0, ctl0, ctl1; 2464 bus_dmamap_t dmamap; 2465 struct ieee80211com *ic; 2466 struct ieee80211_duration *d0; 2467 struct ieee80211_frame *wh; 2468 struct ieee80211_node *ni; 2469 struct mbuf *m0; 2470 struct rtw_softc *sc; 2471 struct rtw_txctl_blk *stc; 2472 struct rtw_txdesc_blk *htc; 2473 struct rtw_txctl *stx; 2474 struct rtw_txdesc *htx; 2475 2476 sc = (struct rtw_softc *)ifp->if_softc; 2477 ic = &sc->sc_ic; 2478 2479 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2480 2481 /* XXX do real rate control */ 2482 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 2483 2484 switch (rate = MAX(2, ieee80211_get_rate(ic))) { 2485 case 2: 2486 proto_ctl0 |= RTW_TXCTL0_RATE_1MBPS; 2487 break; 2488 case 4: 2489 proto_ctl0 |= RTW_TXCTL0_RATE_2MBPS; 2490 break; 2491 case 11: 2492 proto_ctl0 |= RTW_TXCTL0_RATE_5MBPS; 2493 break; 2494 case 22: 2495 proto_ctl0 |= RTW_TXCTL0_RATE_11MBPS; 2496 break; 2497 } 2498 2499 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 2500 proto_ctl0 |= RTW_TXCTL0_SPLCP; 2501 2502 for (;;) { 2503 if (rtw_dequeue(ifp, &stc, &htc, &m0, &ni) == -1) 2504 continue; 2505 if (m0 == NULL) 2506 break; 2507 stx = SIMPLEQ_FIRST(&stc->stc_freeq); 2508 2509 dmamap = stx->stx_dmamap; 2510 2511 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 2512 htc->htc_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 2513 2514 if (m0 == NULL || dmamap->dm_nsegs == 0) { 2515 DPRINTF2(sc, ("%s: fail dmamap load\n", __func__)); 2516 goto post_dequeue_err; 2517 } 2518 2519 #ifdef RTW_DEBUG 2520 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 2521 (IFF_DEBUG|IFF_LINK2)) { 2522 ieee80211_dump_pkt(mtod(m0, uint8_t *), 2523 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 2524 : sizeof(wh), 2525 rate, 0); 2526 } 2527 #endif /* RTW_DEBUG */ 2528 ctl0 = proto_ctl0 | 2529 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 2530 2531 wh = mtod(m0, struct ieee80211_frame *); 2532 2533 if (ieee80211_compute_duration(wh, 2534 m0->m_pkthdr.len - sizeof(wh), 2535 ic->ic_flags, ic->ic_fragthreshold, 2536 rate, &stx->stx_d0, &stx->stx_dn, &npkt) == -1) { 2537 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 2538 goto post_load_err; 2539 } 2540 2541 /* XXX >= ? */ 2542 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 2543 ctl0 |= RTW_TXCTL0_RTSEN; 2544 2545 d0 = &stx->stx_d0; 2546 2547 ctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 2548 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 2549 2550 if ((d0->d_plcp_svc & IEEE80211_PLCP_SERVICE_LENEXT) != 0) 2551 ctl1 |= RTW_TXCTL1_LENGEXT; 2552 2553 /* TBD fragmentation */ 2554 2555 stx->stx_first = htc->htc_next; 2556 2557 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2558 htc, stx->stx_first, dmamap->dm_nsegs, 2559 BUS_DMASYNC_PREWRITE); 2560 2561 for (i = 0, lastdesc = desc = stx->stx_first; 2562 i < dmamap->dm_nsegs; 2563 i++, desc = RTW_NEXT_IDX(htc, desc)) { 2564 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 2565 DPRINTF2(sc, ("%s: seg too long\n", __func__)); 2566 goto post_load_err; 2567 } 2568 htx = &htc->htc_desc[desc]; 2569 htx->htx_ctl0 = htole32(ctl0); 2570 if (i != 0) 2571 htx->htx_ctl0 |= htole32(RTW_TXCTL0_OWN); 2572 htx->htx_ctl1 = htole32(ctl1); 2573 htx->htx_buf = htole32(dmamap->dm_segs[i].ds_addr); 2574 htx->htx_len = htole32(dmamap->dm_segs[i].ds_len); 2575 lastdesc = desc; 2576 #ifdef RTW_DEBUG 2577 rtw_print_txdesc(sc, "load", stx, htc, desc); 2578 #endif /* RTW_DEBUG */ 2579 } 2580 2581 stx->stx_ni = ni; 2582 stx->stx_mbuf = m0; 2583 stx->stx_last = lastdesc; 2584 htc->htc_desc[stx->stx_last].htx_ctl0 |= htole32(RTW_TXCTL0_LS); 2585 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2586 htole32(RTW_TXCTL0_FS); 2587 2588 #ifdef RTW_DEBUG 2589 rtw_print_txdesc(sc, "FS on", stx, htc, stx->stx_first); 2590 #endif /* RTW_DEBUG */ 2591 #ifdef RTW_DEBUG 2592 rtw_print_txdesc(sc, "LS on", stx, htc, stx->stx_last); 2593 #endif /* RTW_DEBUG */ 2594 2595 htc->htc_nfree -= dmamap->dm_nsegs; 2596 htc->htc_next = desc; 2597 2598 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2599 htc, stx->stx_first, dmamap->dm_nsegs, 2600 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2601 2602 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2603 htole32(RTW_TXCTL0_OWN); 2604 2605 #ifdef RTW_DEBUG 2606 rtw_print_txdesc(sc, "OWN on", stx, htc, stx->stx_first); 2607 #endif /* RTW_DEBUG */ 2608 2609 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2610 htc, stx->stx_first, 1, 2611 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2612 2613 SIMPLEQ_REMOVE_HEAD(&stc->stc_freeq, stx_q); 2614 SIMPLEQ_INSERT_TAIL(&stc->stc_dirtyq, stx, stx_q); 2615 2616 stc->stc_tx_timer = 5; 2617 ifp->if_timer = 1; 2618 2619 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 2620 2621 /* TBD poke other queues. */ 2622 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll | RTW_TPPOLL_NPQ); 2623 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 2624 } 2625 DPRINTF2(sc, ("%s: leave\n", __func__)); 2626 return; 2627 post_load_err: 2628 bus_dmamap_unload(sc->sc_dmat, dmamap); 2629 m_freem(m0); 2630 post_dequeue_err: 2631 ieee80211_release_node(&sc->sc_ic, ni); 2632 return; 2633 } 2634 2635 static void 2636 rtw_watchdog(struct ifnet *ifp) 2637 { 2638 int pri; 2639 struct rtw_softc *sc; 2640 struct rtw_txctl_blk *stc; 2641 2642 sc = ifp->if_softc; 2643 2644 ifp->if_timer = 0; 2645 2646 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2647 return; 2648 2649 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2650 stc = &sc->sc_txctl_blk[pri]; 2651 2652 if (stc->stc_tx_timer == 0) 2653 continue; 2654 2655 if (--stc->stc_tx_timer == 0) { 2656 if (SIMPLEQ_EMPTY(&stc->stc_dirtyq)) 2657 continue; 2658 printf("%s: transmit timeout, priority %d\n", 2659 ifp->if_xname, pri); 2660 ifp->if_oerrors++; 2661 /* XXX be gentle */ 2662 (void)rtw_init(ifp); 2663 rtw_start(ifp); 2664 } else 2665 ifp->if_timer = 1; 2666 } 2667 ieee80211_watchdog(ifp); 2668 return; 2669 } 2670 2671 static void 2672 rtw_start_beacon(struct rtw_softc *sc, int enable) 2673 { 2674 /* TBD */ 2675 return; 2676 } 2677 2678 static void 2679 rtw_next_scan(void *arg) 2680 { 2681 struct ieee80211com *ic = arg; 2682 int s; 2683 2684 /* don't call rtw_start w/o network interrupts blocked */ 2685 s = splnet(); 2686 if (ic->ic_state == IEEE80211_S_SCAN) 2687 ieee80211_next_scan(ic); 2688 splx(s); 2689 } 2690 2691 static void 2692 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, enum ieee80211_opmode opmode, 2693 uint16_t intval0) 2694 { 2695 uint16_t bcnitv, intval; 2696 int i; 2697 struct rtw_regs *regs = &sc->sc_regs; 2698 2699 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 2700 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 2701 2702 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 2703 2704 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2705 2706 intval = MIN(intval0, PRESHIFT(RTW_BCNITV_BCNITV_MASK)); 2707 2708 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 2709 bcnitv |= LSHIFT(intval, RTW_BCNITV_BCNITV_MASK); 2710 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 2711 /* magic from Linux */ 2712 RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND)); 2713 RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV)); 2714 2715 rtw_set_nettype(sc, opmode); 2716 2717 rtw_set_access(sc, RTW_ACCESS_NONE); 2718 2719 /* TBD WEP */ 2720 RTW_WRITE8(regs, RTW_SCR, 0); 2721 2722 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 2723 } 2724 2725 /* Synchronize the hardware state with the software state. */ 2726 static int 2727 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2728 { 2729 struct ifnet *ifp = &ic->ic_if; 2730 struct rtw_softc *sc = ifp->if_softc; 2731 enum ieee80211_state ostate; 2732 int error; 2733 2734 ostate = ic->ic_state; 2735 2736 if (nstate == IEEE80211_S_INIT) { 2737 callout_stop(&sc->sc_scan_ch); 2738 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2739 rtw_start_beacon(sc, 0); 2740 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2741 } 2742 2743 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 2744 rtw_pwrstate(sc, RTW_ON); 2745 2746 if ((error = rtw_tune(sc)) != 0) 2747 return error; 2748 2749 switch (nstate) { 2750 case IEEE80211_S_ASSOC: 2751 rtw_join_bss(sc, ic->ic_bss->ni_bssid, ic->ic_opmode, 2752 ic->ic_bss->ni_intval); 2753 break; 2754 case IEEE80211_S_INIT: 2755 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2756 break; 2757 case IEEE80211_S_SCAN: 2758 #if 0 2759 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2760 rtw_write_bssid(sc); 2761 #endif 2762 2763 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 2764 rtw_next_scan, ic); 2765 2766 break; 2767 case IEEE80211_S_RUN: 2768 if (ic->ic_opmode == IEEE80211_M_STA) 2769 break; 2770 /*FALLTHROUGH*/ 2771 case IEEE80211_S_AUTH: 2772 #if 0 2773 rtw_write_bcn_thresh(sc); 2774 rtw_write_ssid(sc); 2775 rtw_write_sup_rates(sc); 2776 #endif 2777 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2778 ic->ic_opmode == IEEE80211_M_MONITOR) 2779 break; 2780 2781 /* TBD set listen interval */ 2782 2783 #if 0 2784 rtw_tsf(sc); 2785 #endif 2786 break; 2787 } 2788 2789 if (nstate != IEEE80211_S_SCAN) 2790 callout_stop(&sc->sc_scan_ch); 2791 2792 if (nstate == IEEE80211_S_RUN && 2793 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2794 ic->ic_opmode == IEEE80211_M_IBSS)) 2795 rtw_start_beacon(sc, 1); 2796 else 2797 rtw_start_beacon(sc, 0); 2798 2799 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2800 } 2801 2802 static void 2803 rtw_recv_beacon(struct rtw_softc *sc, struct mbuf *m, 2804 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2805 { 2806 (*sc->sc_mtbl.mt_recv_mgmt)(&sc->sc_ic, m, ni, subtype, rssi, rstamp); 2807 return; 2808 } 2809 2810 static void 2811 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2812 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2813 { 2814 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 2815 2816 switch (subtype) { 2817 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2818 /* do nothing: hardware answers probe request XXX */ 2819 break; 2820 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2821 case IEEE80211_FC0_SUBTYPE_BEACON: 2822 rtw_recv_beacon(sc, m, ni, subtype, rssi, rstamp); 2823 break; 2824 default: 2825 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2826 break; 2827 } 2828 return; 2829 } 2830 2831 static struct ieee80211_node * 2832 rtw_node_alloc(struct ieee80211com *ic) 2833 { 2834 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2835 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 2836 2837 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 2838 return ni; 2839 } 2840 2841 static void 2842 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 2843 { 2844 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2845 2846 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 2847 ether_sprintf(ni->ni_bssid))); 2848 (*sc->sc_mtbl.mt_node_free)(ic, ni); 2849 } 2850 2851 static int 2852 rtw_media_change(struct ifnet *ifp) 2853 { 2854 int error; 2855 2856 error = ieee80211_media_change(ifp); 2857 if (error == ENETRESET) { 2858 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 2859 (IFF_RUNNING|IFF_UP)) 2860 rtw_init(ifp); /* XXX lose error */ 2861 error = 0; 2862 } 2863 return error; 2864 } 2865 2866 static void 2867 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 2868 { 2869 struct rtw_softc *sc = ifp->if_softc; 2870 2871 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2872 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 2873 imr->ifm_status = 0; 2874 return; 2875 } 2876 ieee80211_media_status(ifp, imr); 2877 } 2878 2879 void 2880 rtw_power(int why, void *arg) 2881 { 2882 struct rtw_softc *sc = arg; 2883 struct ifnet *ifp = &sc->sc_ic.ic_if; 2884 int s; 2885 2886 DPRINTF(sc, ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 2887 2888 s = splnet(); 2889 switch (why) { 2890 case PWR_STANDBY: 2891 /* XXX do nothing. */ 2892 break; 2893 case PWR_SUSPEND: 2894 rtw_stop(ifp, 0); 2895 if (sc->sc_power != NULL) 2896 (*sc->sc_power)(sc, why); 2897 break; 2898 case PWR_RESUME: 2899 if (ifp->if_flags & IFF_UP) { 2900 if (sc->sc_power != NULL) 2901 (*sc->sc_power)(sc, why); 2902 rtw_init(ifp); 2903 } 2904 break; 2905 case PWR_SOFTSUSPEND: 2906 case PWR_SOFTSTANDBY: 2907 case PWR_SOFTRESUME: 2908 break; 2909 } 2910 splx(s); 2911 } 2912 2913 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 2914 void 2915 rtw_shutdown(void *arg) 2916 { 2917 struct rtw_softc *sc = arg; 2918 2919 rtw_stop(&sc->sc_ic.ic_if, 1); 2920 } 2921 2922 static __inline void 2923 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 2924 { 2925 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 2926 ifp->if_softc = softc; 2927 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 2928 IFF_NOTRAILERS; 2929 ifp->if_ioctl = rtw_ioctl; 2930 ifp->if_start = rtw_start; 2931 ifp->if_watchdog = rtw_watchdog; 2932 ifp->if_init = rtw_init; 2933 ifp->if_stop = rtw_stop; 2934 } 2935 2936 static __inline void 2937 rtw_set80211props(struct ieee80211com *ic) 2938 { 2939 int nrate; 2940 ic->ic_phytype = IEEE80211_T_DS; 2941 ic->ic_opmode = IEEE80211_M_STA; 2942 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 2943 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 2944 2945 nrate = 0; 2946 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2947 IEEE80211_RATE_BASIC | 2; 2948 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2949 IEEE80211_RATE_BASIC | 4; 2950 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 2951 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 2952 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 2953 } 2954 2955 static __inline void 2956 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 2957 { 2958 mtbl->mt_newstate = ic->ic_newstate; 2959 ic->ic_newstate = rtw_newstate; 2960 2961 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 2962 ic->ic_recv_mgmt = rtw_recv_mgmt; 2963 2964 mtbl->mt_node_free = ic->ic_node_free; 2965 ic->ic_node_free = rtw_node_free; 2966 2967 mtbl->mt_node_alloc = ic->ic_node_alloc; 2968 ic->ic_node_alloc = rtw_node_alloc; 2969 } 2970 2971 static __inline void 2972 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 2973 void *arg) 2974 { 2975 /* 2976 * Make sure the interface is shutdown during reboot. 2977 */ 2978 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 2979 if (hooks->rh_shutdown == NULL) 2980 printf("%s: WARNING: unable to establish shutdown hook\n", 2981 dvname); 2982 2983 /* 2984 * Add a suspend hook to make sure we come back up after a 2985 * resume. 2986 */ 2987 hooks->rh_power = powerhook_establish(rtw_power, arg); 2988 if (hooks->rh_power == NULL) 2989 printf("%s: WARNING: unable to establish power hook\n", 2990 dvname); 2991 } 2992 2993 static __inline void 2994 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 2995 void *arg) 2996 { 2997 if (hooks->rh_shutdown != NULL) 2998 shutdownhook_disestablish(hooks->rh_shutdown); 2999 3000 if (hooks->rh_power != NULL) 3001 powerhook_disestablish(hooks->rh_power); 3002 } 3003 3004 static __inline void 3005 rtw_init_radiotap(struct rtw_softc *sc) 3006 { 3007 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3008 sc->sc_rxtap.rr_ihdr.it_len = sizeof(sc->sc_rxtapu); 3009 sc->sc_rxtap.rr_ihdr.it_present = RTW_RX_RADIOTAP_PRESENT; 3010 3011 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3012 sc->sc_txtap.rt_ihdr.it_len = sizeof(sc->sc_txtapu); 3013 sc->sc_txtap.rt_ihdr.it_present = RTW_TX_RADIOTAP_PRESENT; 3014 } 3015 3016 static int 3017 rtw_txctl_blk_setup(struct rtw_txctl_blk *stc, u_int qlen) 3018 { 3019 SIMPLEQ_INIT(&stc->stc_dirtyq); 3020 SIMPLEQ_INIT(&stc->stc_freeq); 3021 stc->stc_ndesc = qlen; 3022 stc->stc_desc = malloc(qlen * sizeof(*stc->stc_desc), M_DEVBUF, 3023 M_NOWAIT); 3024 if (stc->stc_desc == NULL) 3025 return ENOMEM; 3026 return 0; 3027 } 3028 3029 static void 3030 rtw_txctl_blk_cleanup_all(struct rtw_softc *sc) 3031 { 3032 struct rtw_txctl_blk *stc; 3033 int qlen[RTW_NTXPRI] = 3034 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3035 int pri; 3036 3037 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 3038 stc = &sc->sc_txctl_blk[pri]; 3039 free(stc->stc_desc, M_DEVBUF); 3040 stc->stc_desc = NULL; 3041 } 3042 } 3043 3044 static int 3045 rtw_txctl_blk_setup_all(struct rtw_softc *sc) 3046 { 3047 int pri, rc = 0; 3048 int qlen[RTW_NTXPRI] = 3049 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3050 3051 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 3052 rc = rtw_txctl_blk_setup(&sc->sc_txctl_blk[pri], qlen[pri]); 3053 if (rc != 0) 3054 break; 3055 } 3056 return rc; 3057 } 3058 3059 static void 3060 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *htc, struct rtw_txdesc *desc, 3061 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3062 { 3063 int i; 3064 3065 htc->htc_ndesc = ndesc; 3066 htc->htc_desc = desc; 3067 htc->htc_physbase = physbase; 3068 htc->htc_ofs = ofs; 3069 3070 (void)memset(htc->htc_desc, 0, 3071 sizeof(htc->htc_desc[0]) * htc->htc_ndesc); 3072 3073 for (i = 0; i < htc->htc_ndesc; i++) { 3074 htc->htc_desc[i].htx_next = htole32(RTW_NEXT_DESC(htc, i)); 3075 } 3076 } 3077 3078 static void 3079 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3080 { 3081 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3082 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3083 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3084 3085 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3086 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3087 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3088 3089 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3090 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3091 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3092 3093 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3094 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3095 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3096 } 3097 3098 static struct rtw_rf * 3099 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, 3100 rtw_rf_write_t rf_write, int digphy) 3101 { 3102 struct rtw_rf *rf; 3103 3104 switch (rfchipid) { 3105 case RTW_RFCHIPID_MAXIM: 3106 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3107 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3108 break; 3109 case RTW_RFCHIPID_PHILIPS: 3110 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3111 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3112 break; 3113 case RTW_RFCHIPID_RFMD: 3114 /* XXX RFMD has no RF constructor */ 3115 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3116 /*FALLTHROUGH*/ 3117 default: 3118 return NULL; 3119 } 3120 rf->rf_continuous_tx_cb = 3121 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3122 rf->rf_continuous_tx_arg = (void *)sc; 3123 return rf; 3124 } 3125 3126 /* Revision C and later use a different PHY delay setting than 3127 * revisions A and B. 3128 */ 3129 static u_int8_t 3130 rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0) 3131 { 3132 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3133 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3134 3135 u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 3136 3137 RTW_WRITE(regs, RTW_RCR, REVAB); 3138 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3139 RTW_WRITE(regs, RTW_RCR, REVC); 3140 3141 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3142 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3143 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3144 3145 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 3146 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3147 3148 return phydelay; 3149 #undef REVC 3150 } 3151 3152 void 3153 rtw_attach(struct rtw_softc *sc) 3154 { 3155 rtw_rf_write_t rf_write; 3156 struct rtw_txctl_blk *stc; 3157 int pri, rc, vers; 3158 3159 #if 0 3160 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_txdesc) == 0, 3161 "RTW_DESC_ALIGNMENT is not a multiple of " 3162 "sizeof(struct rtw_txdesc)"); 3163 3164 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_rxdesc) == 0, 3165 "RTW_DESC_ALIGNMENT is not a multiple of " 3166 "sizeof(struct rtw_rxdesc)"); 3167 3168 CASSERT(RTW_DESC_ALIGNMENT % RTW_MAXPKTSEGS == 0, 3169 "RTW_DESC_ALIGNMENT is not a multiple of RTW_MAXPKTSEGS"); 3170 #endif 3171 3172 NEXT_ATTACH_STATE(sc, DETACHED); 3173 3174 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3175 case RTW_TCR_HWVERID_F: 3176 vers = 'F'; 3177 rf_write = rtw_rf_hostwrite; 3178 break; 3179 case RTW_TCR_HWVERID_D: 3180 vers = 'D'; 3181 if (rtw_host_rfio) 3182 rf_write = rtw_rf_hostwrite; 3183 else 3184 rf_write = rtw_rf_macwrite; 3185 break; 3186 default: 3187 vers = '?'; 3188 rf_write = rtw_rf_macwrite; 3189 break; 3190 } 3191 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, vers); 3192 3193 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3194 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3195 0); 3196 3197 if (rc != 0) { 3198 printf("%s: could not allocate hw descriptors, error %d\n", 3199 sc->sc_dev.dv_xname, rc); 3200 goto err; 3201 } 3202 3203 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3204 3205 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3206 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3207 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3208 3209 if (rc != 0) { 3210 printf("%s: could not map hw descriptors, error %d\n", 3211 sc->sc_dev.dv_xname, rc); 3212 goto err; 3213 } 3214 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3215 3216 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3217 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3218 3219 if (rc != 0) { 3220 printf("%s: could not create DMA map for hw descriptors, " 3221 "error %d\n", sc->sc_dev.dv_xname, rc); 3222 goto err; 3223 } 3224 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3225 3226 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3227 sizeof(struct rtw_descs), NULL, 0); 3228 3229 if (rc != 0) { 3230 printf("%s: could not load DMA map for hw descriptors, " 3231 "error %d\n", sc->sc_dev.dv_xname, rc); 3232 goto err; 3233 } 3234 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3235 3236 if (rtw_txctl_blk_setup_all(sc) != 0) 3237 goto err; 3238 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3239 3240 rtw_txdesc_blk_setup_all(sc); 3241 3242 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3243 3244 sc->sc_rxdesc = &sc->sc_descs->hd_rx[0]; 3245 3246 rtw_rxctls_setup(&sc->sc_rxctl[0]); 3247 3248 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3249 stc = &sc->sc_txctl_blk[pri]; 3250 3251 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3252 &stc->stc_desc[0], stc->stc_ndesc)) != 0) { 3253 printf("%s: could not load DMA map for " 3254 "hw tx descriptors, error %d\n", 3255 sc->sc_dev.dv_xname, rc); 3256 goto err; 3257 } 3258 } 3259 3260 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3261 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxctl[0], 3262 RTW_RXQLEN)) != 0) { 3263 printf("%s: could not load DMA map for hw rx descriptors, " 3264 "error %d\n", sc->sc_dev.dv_xname, rc); 3265 goto err; 3266 } 3267 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3268 3269 /* Reset the chip to a known state. */ 3270 if (rtw_reset(sc) != 0) 3271 goto err; 3272 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3273 3274 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3275 3276 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3277 sc->sc_flags |= RTW_F_9356SROM; 3278 3279 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3280 sc->sc_dev.dv_xname) != 0) 3281 goto err; 3282 3283 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3284 3285 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3286 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3287 sc->sc_dev.dv_xname) != 0) { 3288 printf("%s: attach failed, malformed serial ROM\n", 3289 sc->sc_dev.dv_xname); 3290 goto err; 3291 } 3292 3293 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 3294 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 3295 3296 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 3297 3298 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3299 3300 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, rf_write, 3301 sc->sc_flags & RTW_F_DIGPHY); 3302 3303 if (sc->sc_rf == NULL) { 3304 printf("%s: attach failed, could not attach RF\n", 3305 sc->sc_dev.dv_xname); 3306 goto err; 3307 } 3308 3309 #if 0 3310 if (rtw_identify_rf(&sc->sc_regs, &sc->sc_rftype, 3311 sc->sc_dev.dv_xname) != 0) { 3312 printf("%s: attach failed, unknown RF unidentified\n", 3313 sc->sc_dev.dv_xname); 3314 goto err; 3315 } 3316 #endif 3317 3318 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3319 3320 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 3321 3322 RTW_DPRINTF(("%s: PHY delay %d\n", sc->sc_dev.dv_xname, 3323 sc->sc_phydelay)); 3324 3325 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 3326 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 3327 sc->sc_dev.dv_xname); 3328 3329 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 3330 sc->sc_dev.dv_xname); 3331 3332 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 3333 sc->sc_dev.dv_xname) != 0) 3334 goto err; 3335 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 3336 3337 rtw_setifprops(&sc->sc_if, sc->sc_dev.dv_xname, (void*)sc); 3338 3339 IFQ_SET_READY(&sc->sc_if.if_snd); 3340 3341 rtw_set80211props(&sc->sc_ic); 3342 3343 /* 3344 * Call MI attach routines. 3345 */ 3346 if_attach(&sc->sc_if); 3347 ieee80211_ifattach(&sc->sc_if); 3348 3349 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 3350 3351 /* possibly we should fill in our own sc_send_prresp, since 3352 * the RTL8180 is probably sending probe responses in ad hoc 3353 * mode. 3354 */ 3355 3356 /* complete initialization */ 3357 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 3358 callout_init(&sc->sc_scan_ch); 3359 3360 #if NBPFILTER > 0 3361 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 3362 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 3363 #endif 3364 3365 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 3366 3367 rtw_init_radiotap(sc); 3368 3369 NEXT_ATTACH_STATE(sc, FINISHED); 3370 3371 return; 3372 err: 3373 rtw_detach(sc); 3374 return; 3375 } 3376 3377 int 3378 rtw_detach(struct rtw_softc *sc) 3379 { 3380 int pri; 3381 3382 switch (sc->sc_attach_state) { 3383 case FINISHED: 3384 rtw_stop(&sc->sc_if, 1); 3385 3386 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 3387 (void*)sc); 3388 callout_stop(&sc->sc_scan_ch); 3389 ieee80211_ifdetach(&sc->sc_if); 3390 if_detach(&sc->sc_if); 3391 break; 3392 case FINISH_ID_STA: 3393 case FINISH_RF_ATTACH: 3394 rtw_rf_destroy(sc->sc_rf); 3395 sc->sc_rf = NULL; 3396 /*FALLTHROUGH*/ 3397 case FINISH_PARSE_SROM: 3398 case FINISH_READ_SROM: 3399 rtw_srom_free(&sc->sc_srom); 3400 /*FALLTHROUGH*/ 3401 case FINISH_RESET: 3402 case FINISH_RXMAPS_CREATE: 3403 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxctl[0], 3404 RTW_RXQLEN); 3405 /*FALLTHROUGH*/ 3406 case FINISH_TXMAPS_CREATE: 3407 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3408 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 3409 sc->sc_txctl_blk[pri].stc_desc, 3410 sc->sc_txctl_blk[pri].stc_ndesc); 3411 } 3412 /*FALLTHROUGH*/ 3413 case FINISH_TXDESCBLK_SETUP: 3414 case FINISH_TXCTLBLK_SETUP: 3415 rtw_txctl_blk_cleanup_all(sc); 3416 /*FALLTHROUGH*/ 3417 case FINISH_DESCMAP_LOAD: 3418 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 3419 /*FALLTHROUGH*/ 3420 case FINISH_DESCMAP_CREATE: 3421 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 3422 /*FALLTHROUGH*/ 3423 case FINISH_DESC_MAP: 3424 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 3425 sizeof(struct rtw_descs)); 3426 /*FALLTHROUGH*/ 3427 case FINISH_DESC_ALLOC: 3428 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 3429 sc->sc_desc_nsegs); 3430 /*FALLTHROUGH*/ 3431 case DETACHED: 3432 NEXT_ATTACH_STATE(sc, DETACHED); 3433 break; 3434 } 3435 return 0; 3436 } 3437 3438 int 3439 rtw_activate(struct device *self, enum devact act) 3440 { 3441 struct rtw_softc *sc = (struct rtw_softc *)self; 3442 int rc = 0, s; 3443 3444 s = splnet(); 3445 switch (act) { 3446 case DVACT_ACTIVATE: 3447 rc = EOPNOTSUPP; 3448 break; 3449 3450 case DVACT_DEACTIVATE: 3451 if_deactivate(&sc->sc_ic.ic_if); 3452 break; 3453 } 3454 splx(s); 3455 return rc; 3456 } 3457
Indexes created Fri Sep 26 20:09:58 GMT 2025