rtw.c revision 1.22
1 /* $NetBSD: rtw.c,v 1.22 2004/12/25 07:24:17 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.22 2004/12/25 07:24:17 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #if 0 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #endif 54 #include <sys/time.h> 55 #include <sys/types.h> 56 57 #include <machine/endian.h> 58 #include <machine/bus.h> 59 #include <machine/intr.h> /* splnet */ 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_compat.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <dev/ic/rtwreg.h> 76 #include <dev/ic/rtwvar.h> 77 #include <dev/ic/rtwphyio.h> 78 #include <dev/ic/rtwphy.h> 79 80 #include <dev/ic/smc93cx6var.h> 81 82 #define KASSERT2(__cond, __msg) \ 83 do { \ 84 if (!(__cond)) \ 85 panic __msg ; \ 86 } while (0) 87 88 int rtw_rfprog_fallback = 0; 89 int rtw_host_rfio = 0; 90 int rtw_flush_rfio = 1; 91 int rtw_rfio_delay = 0; 92 93 #ifdef RTW_DEBUG 94 int rtw_debug = 0; 95 #endif /* RTW_DEBUG */ 96 97 #define NEXT_ATTACH_STATE(sc, state) do { \ 98 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 99 ("%s: attach state %s\n", __func__, #state)); \ 100 sc->sc_attach_state = state; \ 101 } while (0) 102 103 int rtw_dwelltime = 1000; /* milliseconds */ 104 105 static void rtw_start(struct ifnet *); 106 107 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 108 static int rtw_sysctl_verify_rfio_delay(SYSCTLFN_PROTO); 109 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 110 #ifdef RTW_DEBUG 111 static void rtw_print_txdesc(struct rtw_softc *, const char *, 112 struct rtw_txctl *, struct rtw_txdesc_blk *, int); 113 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 114 #endif /* RTW_DEBUG */ 115 116 /* 117 * Setup sysctl(3) MIB, hw.rtw.* 118 * 119 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 120 */ 121 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 122 { 123 int rc; 124 struct sysctlnode *cnode, *rnode; 125 126 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 127 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 128 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 129 goto err; 130 131 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 132 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 133 "Realtek RTL818x 802.11 controls", 134 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 135 goto err; 136 137 #ifdef RTW_DEBUG 138 /* control debugging printfs */ 139 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 140 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 141 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 142 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 143 CTL_CREATE, CTL_EOL)) != 0) 144 goto err; 145 #endif /* RTW_DEBUG */ 146 /* set fallback RF programming method */ 147 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 148 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 149 "rfprog_fallback", 150 SYSCTL_DESCR("Set fallback RF programming method"), 151 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 152 CTL_CREATE, CTL_EOL)) != 0) 153 goto err; 154 155 /* force host to flush I/O by reading RTW_PHYADDR */ 156 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 157 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 158 "flush_rfio", SYSCTL_DESCR("Enable RF I/O flushing"), 159 rtw_sysctl_verify_rfio, 0, &rtw_flush_rfio, 0, 160 CTL_CREATE, CTL_EOL)) != 0) 161 goto err; 162 163 /* force host to control RF I/O bus */ 164 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 165 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 166 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 167 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 168 CTL_CREATE, CTL_EOL)) != 0) 169 goto err; 170 171 /* control RF I/O delay */ 172 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 173 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 174 "rfio_delay", SYSCTL_DESCR("Set RF I/O delay"), 175 rtw_sysctl_verify_rfio_delay, 0, &rtw_rfio_delay, 0, 176 CTL_CREATE, CTL_EOL)) != 0) 177 goto err; 178 179 return; 180 err: 181 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 182 } 183 184 static int 185 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 186 { 187 int error, t; 188 struct sysctlnode node; 189 190 node = *rnode; 191 t = *(int*)rnode->sysctl_data; 192 node.sysctl_data = &t; 193 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 194 if (error || newp == NULL) 195 return (error); 196 197 if (t < lower || t > upper) 198 return (EINVAL); 199 200 *(int*)rnode->sysctl_data = t; 201 202 return (0); 203 } 204 205 static int 206 rtw_sysctl_verify_rfio_delay(SYSCTLFN_ARGS) 207 { 208 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1000000); 209 } 210 211 static int 212 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 213 { 214 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 215 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 216 } 217 218 static int 219 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 220 { 221 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1); 222 } 223 224 #ifdef RTW_DEBUG 225 static int 226 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 227 { 228 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, RTW_DEBUG_MAX); 229 } 230 231 static void 232 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 233 { 234 #define PRINTREG32(sc, reg) \ 235 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 236 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 237 dvname, reg, RTW_READ(regs, reg))) 238 239 #define PRINTREG16(sc, reg) \ 240 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 241 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 242 dvname, reg, RTW_READ16(regs, reg))) 243 244 #define PRINTREG8(sc, reg) \ 245 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 246 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 247 dvname, reg, RTW_READ8(regs, reg))) 248 249 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 250 251 PRINTREG32(regs, RTW_IDR0); 252 PRINTREG32(regs, RTW_IDR1); 253 PRINTREG32(regs, RTW_MAR0); 254 PRINTREG32(regs, RTW_MAR1); 255 PRINTREG32(regs, RTW_TSFTRL); 256 PRINTREG32(regs, RTW_TSFTRH); 257 PRINTREG32(regs, RTW_TLPDA); 258 PRINTREG32(regs, RTW_TNPDA); 259 PRINTREG32(regs, RTW_THPDA); 260 PRINTREG32(regs, RTW_TCR); 261 PRINTREG32(regs, RTW_RCR); 262 PRINTREG32(regs, RTW_TINT); 263 PRINTREG32(regs, RTW_TBDA); 264 PRINTREG32(regs, RTW_ANAPARM); 265 PRINTREG32(regs, RTW_BB); 266 PRINTREG32(regs, RTW_PHYCFG); 267 PRINTREG32(regs, RTW_WAKEUP0L); 268 PRINTREG32(regs, RTW_WAKEUP0H); 269 PRINTREG32(regs, RTW_WAKEUP1L); 270 PRINTREG32(regs, RTW_WAKEUP1H); 271 PRINTREG32(regs, RTW_WAKEUP2LL); 272 PRINTREG32(regs, RTW_WAKEUP2LH); 273 PRINTREG32(regs, RTW_WAKEUP2HL); 274 PRINTREG32(regs, RTW_WAKEUP2HH); 275 PRINTREG32(regs, RTW_WAKEUP3LL); 276 PRINTREG32(regs, RTW_WAKEUP3LH); 277 PRINTREG32(regs, RTW_WAKEUP3HL); 278 PRINTREG32(regs, RTW_WAKEUP3HH); 279 PRINTREG32(regs, RTW_WAKEUP4LL); 280 PRINTREG32(regs, RTW_WAKEUP4LH); 281 PRINTREG32(regs, RTW_WAKEUP4HL); 282 PRINTREG32(regs, RTW_WAKEUP4HH); 283 PRINTREG32(regs, RTW_DK0); 284 PRINTREG32(regs, RTW_DK1); 285 PRINTREG32(regs, RTW_DK2); 286 PRINTREG32(regs, RTW_DK3); 287 PRINTREG32(regs, RTW_RETRYCTR); 288 PRINTREG32(regs, RTW_RDSAR); 289 PRINTREG32(regs, RTW_FER); 290 PRINTREG32(regs, RTW_FEMR); 291 PRINTREG32(regs, RTW_FPSR); 292 PRINTREG32(regs, RTW_FFER); 293 294 /* 16-bit registers */ 295 PRINTREG16(regs, RTW_BRSR); 296 PRINTREG16(regs, RTW_IMR); 297 PRINTREG16(regs, RTW_ISR); 298 PRINTREG16(regs, RTW_BCNITV); 299 PRINTREG16(regs, RTW_ATIMWND); 300 PRINTREG16(regs, RTW_BINTRITV); 301 PRINTREG16(regs, RTW_ATIMTRITV); 302 PRINTREG16(regs, RTW_CRC16ERR); 303 PRINTREG16(regs, RTW_CRC0); 304 PRINTREG16(regs, RTW_CRC1); 305 PRINTREG16(regs, RTW_CRC2); 306 PRINTREG16(regs, RTW_CRC3); 307 PRINTREG16(regs, RTW_CRC4); 308 PRINTREG16(regs, RTW_CWR); 309 310 /* 8-bit registers */ 311 PRINTREG8(regs, RTW_CR); 312 PRINTREG8(regs, RTW_9346CR); 313 PRINTREG8(regs, RTW_CONFIG0); 314 PRINTREG8(regs, RTW_CONFIG1); 315 PRINTREG8(regs, RTW_CONFIG2); 316 PRINTREG8(regs, RTW_MSR); 317 PRINTREG8(regs, RTW_CONFIG3); 318 PRINTREG8(regs, RTW_CONFIG4); 319 PRINTREG8(regs, RTW_TESTR); 320 PRINTREG8(regs, RTW_PSR); 321 PRINTREG8(regs, RTW_SCR); 322 PRINTREG8(regs, RTW_PHYDELAY); 323 PRINTREG8(regs, RTW_CRCOUNT); 324 PRINTREG8(regs, RTW_PHYADDR); 325 PRINTREG8(regs, RTW_PHYDATAW); 326 PRINTREG8(regs, RTW_PHYDATAR); 327 PRINTREG8(regs, RTW_CONFIG5); 328 PRINTREG8(regs, RTW_TPPOLL); 329 330 PRINTREG16(regs, RTW_BSSID16); 331 PRINTREG32(regs, RTW_BSSID32); 332 #undef PRINTREG32 333 #undef PRINTREG16 334 #undef PRINTREG8 335 } 336 #endif /* RTW_DEBUG */ 337 338 void 339 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 340 { 341 struct rtw_regs *regs = &sc->sc_regs; 342 343 u_int32_t tcr; 344 tcr = RTW_READ(regs, RTW_TCR); 345 tcr &= ~RTW_TCR_LBK_MASK; 346 if (enable) 347 tcr |= RTW_TCR_LBK_CONT; 348 else 349 tcr |= RTW_TCR_LBK_NORMAL; 350 RTW_WRITE(regs, RTW_TCR, tcr); 351 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 352 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 353 rtw_txdac_enable(sc, !enable); 354 rtw_set_access(sc, RTW_ACCESS_ANAPARM); /* XXX Voodoo from Linux. */ 355 rtw_set_access(sc, RTW_ACCESS_NONE); 356 } 357 358 static const char * 359 rtw_access_string(enum rtw_access access) 360 { 361 switch (access) { 362 case RTW_ACCESS_NONE: 363 return "none"; 364 case RTW_ACCESS_CONFIG: 365 return "config"; 366 case RTW_ACCESS_ANAPARM: 367 return "anaparm"; 368 default: 369 return "unknown"; 370 } 371 } 372 373 static void 374 rtw_set_access1(struct rtw_regs *regs, 375 enum rtw_access oaccess, enum rtw_access naccess) 376 { 377 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 378 KASSERT(oaccess >= RTW_ACCESS_NONE && oaccess <= RTW_ACCESS_ANAPARM); 379 380 if (naccess == oaccess) 381 return; 382 383 switch (naccess) { 384 case RTW_ACCESS_NONE: 385 switch (oaccess) { 386 case RTW_ACCESS_ANAPARM: 387 rtw_anaparm_enable(regs, 0); 388 /*FALLTHROUGH*/ 389 case RTW_ACCESS_CONFIG: 390 rtw_config0123_enable(regs, 0); 391 /*FALLTHROUGH*/ 392 case RTW_ACCESS_NONE: 393 break; 394 } 395 break; 396 case RTW_ACCESS_CONFIG: 397 switch (oaccess) { 398 case RTW_ACCESS_NONE: 399 rtw_config0123_enable(regs, 1); 400 /*FALLTHROUGH*/ 401 case RTW_ACCESS_CONFIG: 402 break; 403 case RTW_ACCESS_ANAPARM: 404 rtw_anaparm_enable(regs, 0); 405 break; 406 } 407 break; 408 case RTW_ACCESS_ANAPARM: 409 switch (oaccess) { 410 case RTW_ACCESS_NONE: 411 rtw_config0123_enable(regs, 1); 412 /*FALLTHROUGH*/ 413 case RTW_ACCESS_CONFIG: 414 rtw_anaparm_enable(regs, 1); 415 /*FALLTHROUGH*/ 416 case RTW_ACCESS_ANAPARM: 417 break; 418 } 419 break; 420 } 421 } 422 423 void 424 rtw_set_access(struct rtw_softc *sc, enum rtw_access access) 425 { 426 rtw_set_access1(&sc->sc_regs, sc->sc_access, access); 427 RTW_DPRINTF(RTW_DEBUG_ACCESS, 428 ("%s: access %s -> %s\n", sc->sc_dev.dv_xname, 429 rtw_access_string(sc->sc_access), 430 rtw_access_string(access))); 431 sc->sc_access = access; 432 } 433 434 /* 435 * Enable registers, switch register banks. 436 */ 437 void 438 rtw_config0123_enable(struct rtw_regs *regs, int enable) 439 { 440 u_int8_t ecr; 441 ecr = RTW_READ8(regs, RTW_9346CR); 442 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 443 if (enable) 444 ecr |= RTW_9346CR_EEM_CONFIG; 445 else { 446 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 447 ecr |= RTW_9346CR_EEM_NORMAL; 448 } 449 RTW_WRITE8(regs, RTW_9346CR, ecr); 450 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 451 } 452 453 /* requires rtw_config0123_enable(, 1) */ 454 void 455 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 456 { 457 u_int8_t cfg3; 458 459 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 460 cfg3 |= RTW_CONFIG3_CLKRUNEN; 461 if (enable) 462 cfg3 |= RTW_CONFIG3_PARMEN; 463 else 464 cfg3 &= ~RTW_CONFIG3_PARMEN; 465 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 466 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 467 } 468 469 /* requires rtw_anaparm_enable(, 1) */ 470 void 471 rtw_txdac_enable(struct rtw_softc *sc, int enable) 472 { 473 u_int32_t anaparm; 474 struct rtw_regs *regs = &sc->sc_regs; 475 476 anaparm = RTW_READ(regs, RTW_ANAPARM); 477 if (enable) 478 anaparm &= ~RTW_ANAPARM_TXDACOFF; 479 else 480 anaparm |= RTW_ANAPARM_TXDACOFF; 481 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 482 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 483 } 484 485 static __inline int 486 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 487 { 488 u_int8_t cr; 489 int i; 490 491 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 492 493 RTW_WBR(regs, RTW_CR, RTW_CR); 494 495 for (i = 0; i < 1000; i++) { 496 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 497 RTW_DPRINTF(RTW_DEBUG_RESET, 498 ("%s: reset in %dus\n", dvname, i)); 499 return 0; 500 } 501 RTW_RBR(regs, RTW_CR, RTW_CR); 502 DELAY(10); /* 10us */ 503 } 504 505 printf("%s: reset failed\n", dvname); 506 return ETIMEDOUT; 507 } 508 509 static __inline int 510 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 511 { 512 uint32_t tcr; 513 514 /* from Linux driver */ 515 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 516 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 517 518 RTW_WRITE(regs, RTW_TCR, tcr); 519 520 RTW_WBW(regs, RTW_CR, RTW_TCR); 521 522 return rtw_chip_reset1(regs, dvname); 523 } 524 525 static __inline int 526 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 527 { 528 int i; 529 u_int8_t ecr; 530 531 ecr = RTW_READ8(regs, RTW_9346CR); 532 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 533 RTW_WRITE8(regs, RTW_9346CR, ecr); 534 535 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 536 537 /* wait 2.5ms for completion */ 538 for (i = 0; i < 25; i++) { 539 ecr = RTW_READ8(regs, RTW_9346CR); 540 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 541 RTW_DPRINTF(RTW_DEBUG_RESET, 542 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 543 return 0; 544 } 545 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 546 DELAY(100); 547 } 548 printf("%s: recall EEPROM failed\n", dvname); 549 return ETIMEDOUT; 550 } 551 552 static __inline int 553 rtw_reset(struct rtw_softc *sc) 554 { 555 int rc; 556 uint8_t config1; 557 558 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 559 return rc; 560 561 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 562 ; 563 564 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 565 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 566 /* TBD turn off maximum power saving? */ 567 568 return 0; 569 } 570 571 static __inline int 572 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txctl *descs, 573 u_int ndescs) 574 { 575 int i, rc = 0; 576 for (i = 0; i < ndescs; i++) { 577 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 578 0, 0, &descs[i].stx_dmamap); 579 if (rc != 0) 580 break; 581 } 582 return rc; 583 } 584 585 static __inline int 586 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 587 u_int ndescs) 588 { 589 int i, rc = 0; 590 for (i = 0; i < ndescs; i++) { 591 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 592 &descs[i].srx_dmamap); 593 if (rc != 0) 594 break; 595 } 596 return rc; 597 } 598 599 static __inline void 600 rtw_rxctls_setup(struct rtw_rxctl *descs) 601 { 602 int i; 603 for (i = 0; i < RTW_RXQLEN; i++) 604 descs[i].srx_mbuf = NULL; 605 } 606 607 static __inline void 608 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 609 u_int ndescs) 610 { 611 int i; 612 for (i = 0; i < ndescs; i++) { 613 if (descs[i].srx_dmamap != NULL) 614 bus_dmamap_destroy(dmat, descs[i].srx_dmamap); 615 } 616 } 617 618 static __inline void 619 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txctl *descs, 620 u_int ndescs) 621 { 622 int i; 623 for (i = 0; i < ndescs; i++) { 624 if (descs[i].stx_dmamap != NULL) 625 bus_dmamap_destroy(dmat, descs[i].stx_dmamap); 626 } 627 } 628 629 static __inline void 630 rtw_srom_free(struct rtw_srom *sr) 631 { 632 sr->sr_size = 0; 633 if (sr->sr_content == NULL) 634 return; 635 free(sr->sr_content, M_DEVBUF); 636 sr->sr_content = NULL; 637 } 638 639 static void 640 rtw_srom_defaults(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 641 enum rtw_rfchipid *rfchipid, u_int32_t *rcr) 642 { 643 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 644 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 645 *rcr |= RTW_RCR_ENCS1; 646 *rfchipid = RTW_RFCHIPID_PHILIPS; 647 } 648 649 static int 650 rtw_srom_parse(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 651 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, enum rtw_locale *locale, 652 const char *dvname) 653 { 654 int i; 655 const char *rfname, *paname; 656 char scratch[sizeof("unknown 0xXX")]; 657 u_int16_t version; 658 u_int8_t mac[IEEE80211_ADDR_LEN]; 659 660 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 661 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 662 663 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 664 printf("%s: SROM version %d.%d", dvname, version >> 8, version & 0xff); 665 666 if (version <= 0x0101) { 667 printf(" is not understood, limping along with defaults\n"); 668 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 669 return 0; 670 } 671 printf("\n"); 672 673 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 674 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 675 676 RTW_DPRINTF(RTW_DEBUG_ATTACH, 677 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 678 679 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 680 681 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 682 *flags |= RTW_F_ANTDIV; 683 684 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 685 * to be reversed. 686 */ 687 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 688 *flags |= RTW_F_DIGPHY; 689 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 690 *flags |= RTW_F_DFLANTB; 691 692 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 693 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 694 695 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 696 switch (*rfchipid) { 697 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 698 rfname = "GCT GRF5101"; 699 paname = "Winspring WS9901"; 700 break; 701 case RTW_RFCHIPID_MAXIM: 702 rfname = "Maxim MAX2820"; /* guess */ 703 paname = "Maxim MAX2422"; /* guess */ 704 break; 705 case RTW_RFCHIPID_INTERSIL: 706 rfname = "Intersil HFA3873"; /* guess */ 707 paname = "Intersil <unknown>"; 708 break; 709 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 710 rfname = "Philips SA2400A"; 711 paname = "Philips SA2411"; 712 break; 713 case RTW_RFCHIPID_RFMD: 714 /* this is the same front-end as an atw(4)! */ 715 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 716 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 717 "SYN: Silicon Labs Si4126"; /* inferred from 718 * reference driver 719 */ 720 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 721 break; 722 case RTW_RFCHIPID_RESERVED: 723 rfname = paname = "reserved"; 724 break; 725 default: 726 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 727 rfname = paname = scratch; 728 } 729 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 730 731 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 732 case RTW_CONFIG0_GL_USA: 733 *locale = RTW_LOCALE_USA; 734 break; 735 case RTW_CONFIG0_GL_EUROPE: 736 *locale = RTW_LOCALE_EUROPE; 737 break; 738 case RTW_CONFIG0_GL_JAPAN: 739 *locale = RTW_LOCALE_JAPAN; 740 break; 741 default: 742 *locale = RTW_LOCALE_UNKNOWN; 743 break; 744 } 745 return 0; 746 } 747 748 /* Returns -1 on failure. */ 749 static int 750 rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr, 751 const char *dvname) 752 { 753 int rc; 754 struct seeprom_descriptor sd; 755 u_int8_t ecr; 756 757 (void)memset(&sd, 0, sizeof(sd)); 758 759 ecr = RTW_READ8(regs, RTW_9346CR); 760 761 if ((flags & RTW_F_9356SROM) != 0) { 762 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 763 sr->sr_size = 256; 764 sd.sd_chip = C56_66; 765 } else { 766 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 767 sr->sr_size = 128; 768 sd.sd_chip = C46; 769 } 770 771 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 772 RTW_9346CR_EEM_MASK); 773 ecr |= RTW_9346CR_EEM_PROGRAM; 774 775 RTW_WRITE8(regs, RTW_9346CR, ecr); 776 777 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 778 779 if (sr->sr_content == NULL) { 780 printf("%s: unable to allocate SROM buffer\n", dvname); 781 return ENOMEM; 782 } 783 784 (void)memset(sr->sr_content, 0, sr->sr_size); 785 786 /* RTL8180 has a single 8-bit register for controlling the 787 * 93cx6 SROM. There is no "ready" bit. The RTL8180 788 * input/output sense is the reverse of read_seeprom's. 789 */ 790 sd.sd_tag = regs->r_bt; 791 sd.sd_bsh = regs->r_bh; 792 sd.sd_regsize = 1; 793 sd.sd_control_offset = RTW_9346CR; 794 sd.sd_status_offset = RTW_9346CR; 795 sd.sd_dataout_offset = RTW_9346CR; 796 sd.sd_CK = RTW_9346CR_EESK; 797 sd.sd_CS = RTW_9346CR_EECS; 798 sd.sd_DI = RTW_9346CR_EEDO; 799 sd.sd_DO = RTW_9346CR_EEDI; 800 /* make read_seeprom enter EEPROM read/write mode */ 801 sd.sd_MS = ecr; 802 sd.sd_RDY = 0; 803 #if 0 804 sd.sd_clkdelay = 50; 805 #endif 806 807 /* TBD bus barriers */ 808 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 809 printf("%s: could not read SROM\n", dvname); 810 free(sr->sr_content, M_DEVBUF); 811 sr->sr_content = NULL; 812 return -1; /* XXX */ 813 } 814 815 /* end EEPROM read/write mode */ 816 RTW_WRITE8(regs, RTW_9346CR, 817 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 818 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 819 820 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 821 return rc; 822 823 #ifdef RTW_DEBUG 824 { 825 int i; 826 RTW_DPRINTF(RTW_DEBUG_ATTACH, 827 ("\n%s: serial ROM:\n\t", dvname)); 828 for (i = 0; i < sr->sr_size/2; i++) { 829 if (((i % 8) == 0) && (i != 0)) 830 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 831 RTW_DPRINTF(RTW_DEBUG_ATTACH, 832 (" %04x", sr->sr_content[i])); 833 } 834 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 835 } 836 #endif /* RTW_DEBUG */ 837 return 0; 838 } 839 840 static void 841 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 842 const char *dvname) 843 { 844 u_int8_t cfg4; 845 const char *method; 846 847 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 848 849 switch (rfchipid) { 850 default: 851 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 852 method = "fallback"; 853 break; 854 case RTW_RFCHIPID_INTERSIL: 855 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 856 method = "Intersil"; 857 break; 858 case RTW_RFCHIPID_PHILIPS: 859 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 860 method = "Philips"; 861 break; 862 case RTW_RFCHIPID_RFMD: 863 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 864 method = "RFMD"; 865 break; 866 } 867 868 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 869 870 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 871 872 RTW_DPRINTF(RTW_DEBUG_INIT, 873 ("%s: %s RF programming method, %#02x\n", dvname, method, 874 RTW_READ8(regs, RTW_CONFIG4))); 875 } 876 877 #if 0 878 static __inline int 879 rtw_identify_rf(struct rtw_regs *regs, enum rtw_rftype *rftype, 880 const char *dvname) 881 { 882 u_int8_t cfg4; 883 const char *name; 884 885 cfg4 = RTW_READ8(regs, RTW_CONFIG4); 886 887 switch (cfg4 & RTW_CONFIG4_RFTYPE_MASK) { 888 case RTW_CONFIG4_RFTYPE_PHILIPS: 889 *rftype = RTW_RFTYPE_PHILIPS; 890 name = "Philips"; 891 break; 892 case RTW_CONFIG4_RFTYPE_INTERSIL: 893 *rftype = RTW_RFTYPE_INTERSIL; 894 name = "Intersil"; 895 break; 896 case RTW_CONFIG4_RFTYPE_RFMD: 897 *rftype = RTW_RFTYPE_RFMD; 898 name = "RFMD"; 899 break; 900 default: 901 name = "<unknown>"; 902 return ENXIO; 903 } 904 905 printf("%s: RF prog type %s\n", dvname, name); 906 return 0; 907 } 908 #endif 909 910 static __inline void 911 rtw_init_channels(enum rtw_locale locale, 912 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 913 const char *dvname) 914 { 915 int i; 916 const char *name = NULL; 917 #define ADD_CHANNEL(_chans, _chan) do { \ 918 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 919 (*_chans)[_chan].ic_freq = \ 920 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 921 } while (0) 922 923 switch (locale) { 924 case RTW_LOCALE_USA: /* 1-11 */ 925 name = "USA"; 926 for (i = 1; i <= 11; i++) 927 ADD_CHANNEL(chans, i); 928 break; 929 case RTW_LOCALE_JAPAN: /* 1-14 */ 930 name = "Japan"; 931 ADD_CHANNEL(chans, 14); 932 for (i = 1; i <= 14; i++) 933 ADD_CHANNEL(chans, i); 934 break; 935 case RTW_LOCALE_EUROPE: /* 1-13 */ 936 name = "Europe"; 937 for (i = 1; i <= 13; i++) 938 ADD_CHANNEL(chans, i); 939 break; 940 default: /* 10-11 allowed by most countries */ 941 name = "<unknown>"; 942 for (i = 10; i <= 11; i++) 943 ADD_CHANNEL(chans, i); 944 break; 945 } 946 printf("%s: Geographic Location %s\n", dvname, name); 947 #undef ADD_CHANNEL 948 } 949 950 static __inline void 951 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 952 const char *dvname) 953 { 954 u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 955 956 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 957 case RTW_CONFIG0_GL_USA: 958 *locale = RTW_LOCALE_USA; 959 break; 960 case RTW_CONFIG0_GL_JAPAN: 961 *locale = RTW_LOCALE_JAPAN; 962 break; 963 case RTW_CONFIG0_GL_EUROPE: 964 *locale = RTW_LOCALE_EUROPE; 965 break; 966 default: 967 *locale = RTW_LOCALE_UNKNOWN; 968 break; 969 } 970 } 971 972 static __inline int 973 rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN], 974 const char *dvname) 975 { 976 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 977 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 978 }; 979 u_int32_t idr0 = RTW_READ(regs, RTW_IDR0), 980 idr1 = RTW_READ(regs, RTW_IDR1); 981 982 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 983 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 984 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 985 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 986 987 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 988 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 989 990 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 991 printf("%s: could not get mac address, attach failed\n", 992 dvname); 993 return ENXIO; 994 } 995 996 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 997 998 return 0; 999 } 1000 1001 static u_int8_t 1002 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1003 struct ieee80211_channel *chan) 1004 { 1005 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1006 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 1007 ("%s: channel %d out of range", __func__, 1008 idx - RTW_SR_TXPOWER1 + 1)); 1009 return RTW_SR_GET(sr, idx); 1010 } 1011 1012 static void 1013 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *htcs) 1014 { 1015 int pri; 1016 u_int ndesc[RTW_NTXPRI] = 1017 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 1018 1019 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1020 htcs[pri].htc_nfree = ndesc[pri]; 1021 htcs[pri].htc_next = 0; 1022 } 1023 } 1024 1025 static int 1026 rtw_txctl_blk_init(struct rtw_txctl_blk *stc) 1027 { 1028 int i; 1029 struct rtw_txctl *stx; 1030 1031 SIMPLEQ_INIT(&stc->stc_dirtyq); 1032 SIMPLEQ_INIT(&stc->stc_freeq); 1033 for (i = 0; i < stc->stc_ndesc; i++) { 1034 stx = &stc->stc_desc[i]; 1035 stx->stx_mbuf = NULL; 1036 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1037 } 1038 return 0; 1039 } 1040 1041 static void 1042 rtw_txctl_blk_init_all(struct rtw_txctl_blk *stcs) 1043 { 1044 int pri; 1045 for (pri = 0; pri < RTW_NTXPRI; pri++) 1046 rtw_txctl_blk_init(&stcs[pri]); 1047 } 1048 1049 static __inline void 1050 rtw_rxdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, u_int desc0, u_int 1051 nsync, int ops) 1052 { 1053 KASSERT(nsync <= RTW_RXQLEN); 1054 /* sync to end of ring */ 1055 if (desc0 + nsync > RTW_RXQLEN) { 1056 bus_dmamap_sync(dmat, dmap, 1057 offsetof(struct rtw_descs, hd_rx[desc0]), 1058 sizeof(struct rtw_rxdesc) * (RTW_RXQLEN - desc0), ops); 1059 nsync -= (RTW_RXQLEN - desc0); 1060 desc0 = 0; 1061 } 1062 1063 KASSERT(desc0 < RTW_RXQLEN); 1064 KASSERT(nsync <= RTW_RXQLEN); 1065 KASSERT(desc0 + nsync <= RTW_RXQLEN); 1066 1067 /* sync what remains */ 1068 bus_dmamap_sync(dmat, dmap, 1069 offsetof(struct rtw_descs, hd_rx[desc0]), 1070 sizeof(struct rtw_rxdesc) * nsync, ops); 1071 } 1072 1073 static void 1074 rtw_txdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1075 struct rtw_txdesc_blk *htc, u_int desc0, u_int nsync, int ops) 1076 { 1077 /* sync to end of ring */ 1078 if (desc0 + nsync > htc->htc_ndesc) { 1079 bus_dmamap_sync(dmat, dmap, 1080 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1081 sizeof(struct rtw_txdesc) * (htc->htc_ndesc - desc0), 1082 ops); 1083 nsync -= (htc->htc_ndesc - desc0); 1084 desc0 = 0; 1085 } 1086 1087 /* sync what remains */ 1088 bus_dmamap_sync(dmat, dmap, 1089 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1090 sizeof(struct rtw_txdesc) * nsync, ops); 1091 } 1092 1093 static void 1094 rtw_txdescs_sync_all(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1095 struct rtw_txdesc_blk *htcs) 1096 { 1097 int pri; 1098 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1099 rtw_txdescs_sync(dmat, dmap, 1100 &htcs[pri], 0, htcs[pri].htc_ndesc, 1101 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1102 } 1103 } 1104 1105 static void 1106 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxctl *desc) 1107 { 1108 int i; 1109 struct rtw_rxctl *srx; 1110 1111 for (i = 0; i < RTW_RXQLEN; i++) { 1112 srx = &desc[i]; 1113 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, 1114 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1115 bus_dmamap_unload(dmat, srx->srx_dmamap); 1116 m_freem(srx->srx_mbuf); 1117 srx->srx_mbuf = NULL; 1118 } 1119 } 1120 1121 static __inline int 1122 rtw_rxbuf_alloc(bus_dma_tag_t dmat, struct rtw_rxctl *srx) 1123 { 1124 int rc; 1125 struct mbuf *m; 1126 1127 MGETHDR(m, M_DONTWAIT, MT_DATA); 1128 if (m == NULL) 1129 return ENOBUFS; 1130 1131 MCLGET(m, M_DONTWAIT); 1132 if (m == NULL) 1133 return ENOBUFS; 1134 1135 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1136 1137 if (srx->srx_mbuf != NULL) 1138 bus_dmamap_unload(dmat, srx->srx_dmamap); 1139 1140 srx->srx_mbuf = NULL; 1141 1142 rc = bus_dmamap_load_mbuf(dmat, srx->srx_dmamap, m, BUS_DMA_NOWAIT); 1143 if (rc != 0) { 1144 m_freem(m); 1145 return -1; 1146 } 1147 1148 srx->srx_mbuf = m; 1149 1150 return 0; 1151 } 1152 1153 static int 1154 rtw_rxctl_init_all(bus_dma_tag_t dmat, struct rtw_rxctl *desc, 1155 u_int *next, const char *dvname) 1156 { 1157 int i, rc; 1158 struct rtw_rxctl *srx; 1159 1160 for (i = 0; i < RTW_RXQLEN; i++) { 1161 srx = &desc[i]; 1162 if ((rc = rtw_rxbuf_alloc(dmat, srx)) == 0) 1163 continue; 1164 printf("%s: failed rtw_rxbuf_alloc after %d buffers, rc = %d\n", 1165 dvname, i, rc); 1166 if (i == 0) { 1167 rtw_rxbufs_release(dmat, desc); 1168 return rc; 1169 } 1170 } 1171 *next = 0; 1172 return 0; 1173 } 1174 1175 static __inline void 1176 rtw_rxdesc_init(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1177 struct rtw_rxdesc *hrx, struct rtw_rxctl *srx, int idx, int flags) 1178 { 1179 int is_last = (idx == RTW_RXQLEN - 1); 1180 uint32_t ctl, octl, obuf; 1181 1182 obuf = hrx->hrx_buf; 1183 hrx->hrx_buf = htole32(srx->srx_dmamap->dm_segs[0].ds_addr); 1184 1185 ctl = LSHIFT(srx->srx_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1186 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1187 1188 if (is_last) 1189 ctl |= RTW_RXCTL_EOR; 1190 1191 octl = hrx->hrx_ctl; 1192 hrx->hrx_ctl = htole32(ctl); 1193 1194 RTW_DPRINTF(flags, 1195 ("%s: hrx %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, hrx, 1196 le32toh(obuf), le32toh(hrx->hrx_buf), le32toh(octl), 1197 le32toh(hrx->hrx_ctl))); 1198 1199 /* sync the mbuf */ 1200 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, srx->srx_dmamap->dm_mapsize, 1201 BUS_DMASYNC_PREREAD); 1202 1203 /* sync the descriptor */ 1204 bus_dmamap_sync(dmat, dmam, RTW_DESC_OFFSET(hd_rx, idx), 1205 sizeof(struct rtw_rxdesc), 1206 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1207 } 1208 1209 static void 1210 rtw_rxdesc_init_all(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1211 struct rtw_rxdesc *desc, struct rtw_rxctl *ctl, int flags) 1212 { 1213 int i; 1214 struct rtw_rxdesc *hrx; 1215 struct rtw_rxctl *srx; 1216 1217 for (i = 0; i < RTW_RXQLEN; i++) { 1218 hrx = &desc[i]; 1219 srx = &ctl[i]; 1220 rtw_rxdesc_init(dmat, dmam, hrx, srx, i, flags); 1221 } 1222 } 1223 1224 static void 1225 rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable) 1226 { 1227 u_int8_t cr; 1228 1229 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1230 enable ? "enable" : "disable", flags)); 1231 1232 cr = RTW_READ8(regs, RTW_CR); 1233 1234 /* XXX reference source does not enable MULRW */ 1235 #if 0 1236 /* enable PCI Read/Write Multiple */ 1237 cr |= RTW_CR_MULRW; 1238 #endif 1239 1240 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1241 if (enable) 1242 cr |= flags; 1243 else 1244 cr &= ~flags; 1245 RTW_WRITE8(regs, RTW_CR, cr); 1246 RTW_SYNC(regs, RTW_CR, RTW_CR); 1247 } 1248 1249 static void 1250 rtw_intr_rx(struct rtw_softc *sc, u_int16_t isr) 1251 { 1252 u_int next, nproc = 0; 1253 int len, rate, rssi; 1254 u_int32_t hrssi, hstat, htsfth, htsftl; 1255 struct rtw_rxdesc *hrx; 1256 struct rtw_rxctl *srx; 1257 struct mbuf *m; 1258 1259 struct ieee80211_node *ni; 1260 struct ieee80211_frame *wh; 1261 1262 KASSERT(sc->sc_rxnext < RTW_RXQLEN); 1263 1264 for (next = sc->sc_rxnext; ; next = (next + 1) % RTW_RXQLEN) { 1265 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1266 next, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1267 hrx = &sc->sc_rxdesc[next]; 1268 srx = &sc->sc_rxctl[next]; 1269 1270 hstat = le32toh(hrx->hrx_stat); 1271 hrssi = le32toh(hrx->hrx_rssi); 1272 htsfth = le32toh(hrx->hrx_tsfth); 1273 htsftl = le32toh(hrx->hrx_tsftl); 1274 1275 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1276 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1277 __func__, next, hstat, hrssi, htsfth, htsftl)); 1278 1279 KASSERT((hstat & (RTW_RXSTAT_FS|RTW_RXSTAT_LS)) == 1280 (RTW_RXSTAT_FS|RTW_RXSTAT_LS)); 1281 1282 ++nproc; 1283 1284 /* still belongs to NIC */ 1285 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1286 if (nproc > 1) 1287 break; 1288 1289 /* sometimes the NIC skips to the 0th descriptor */ 1290 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1291 0, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1292 hrx = &sc->sc_rxdesc[0]; 1293 if ((hrx->hrx_stat & htole32(RTW_RXSTAT_OWN)) != 0) 1294 break; 1295 printf("%s: NIC skipped to rxdesc[0]\n", 1296 sc->sc_dev.dv_xname); 1297 next = 0; 1298 continue; 1299 } 1300 1301 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1302 printf("%s: DMA error/FIFO overflow %08x, " 1303 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1304 hstat & RTW_RXSTAT_IOERROR, next); 1305 goto next; 1306 } 1307 1308 len = MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1309 if (len < IEEE80211_MIN_LEN) { 1310 sc->sc_ic.ic_stats.is_rx_tooshort++; 1311 goto next; 1312 } 1313 1314 switch (hstat & RTW_RXSTAT_RATE_MASK) { 1315 case RTW_RXSTAT_RATE_1MBPS: 1316 rate = 2; 1317 break; 1318 case RTW_RXSTAT_RATE_2MBPS: 1319 rate = 4; 1320 break; 1321 case RTW_RXSTAT_RATE_5MBPS: 1322 rate = 11; 1323 break; 1324 case RTW_RXSTAT_RATE_11MBPS: 1325 rate = 22; 1326 break; 1327 default: 1328 printf("%s: unknown rate #%d\n", sc->sc_dev.dv_xname, 1329 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_RATE_MASK)); 1330 goto next; 1331 } 1332 1333 #ifdef RTW_DEBUG 1334 #define PRINTSTAT(flag) do { \ 1335 if ((hstat & flag) != 0) { \ 1336 printf("%s" #flag, delim); \ 1337 delim = ","; \ 1338 } \ 1339 } while (0) 1340 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1341 const char *delim = "<"; 1342 printf("%s: ", sc->sc_dev.dv_xname); 1343 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1344 printf("status %08x", hstat); 1345 PRINTSTAT(RTW_RXSTAT_SPLCP); 1346 PRINTSTAT(RTW_RXSTAT_MAR); 1347 PRINTSTAT(RTW_RXSTAT_PAR); 1348 PRINTSTAT(RTW_RXSTAT_BAR); 1349 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1350 PRINTSTAT(RTW_RXSTAT_CRC32); 1351 PRINTSTAT(RTW_RXSTAT_ICV); 1352 printf(">, "); 1353 } 1354 printf("rate %d.%d Mb/s, time %08x%08x\n", 1355 (rate * 5) / 10, (rate * 5) % 10, htsfth, htsftl); 1356 } 1357 #endif /* RTW_DEBUG */ 1358 1359 if ((hstat & RTW_RXSTAT_RES) != 0 && 1360 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1361 goto next; 1362 1363 /* if bad flags, skip descriptor */ 1364 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1365 printf("%s: too many rx segments\n", 1366 sc->sc_dev.dv_xname); 1367 goto next; 1368 } 1369 1370 bus_dmamap_sync(sc->sc_dmat, srx->srx_dmamap, 0, 1371 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1372 1373 m = srx->srx_mbuf; 1374 1375 /* if temporarily out of memory, re-use mbuf */ 1376 switch (rtw_rxbuf_alloc(sc->sc_dmat, srx)) { 1377 case 0: 1378 break; 1379 case ENOBUFS: 1380 printf("%s: rtw_rxbuf_alloc(, %d) failed, " 1381 "dropping this packet\n", sc->sc_dev.dv_xname, 1382 next); 1383 goto next; 1384 default: 1385 /* XXX shorten rx ring, instead? */ 1386 panic("%s: could not load DMA map\n", 1387 sc->sc_dev.dv_xname); 1388 } 1389 1390 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1391 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1392 else { 1393 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1394 /* TBD find out each front-end's LNA gain in the 1395 * front-end's units 1396 */ 1397 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1398 rssi |= 0x80; 1399 } 1400 1401 m->m_pkthdr.rcvif = &sc->sc_if; 1402 m->m_pkthdr.len = m->m_len = len; 1403 m->m_flags |= M_HASFCS; 1404 1405 wh = mtod(m, struct ieee80211_frame *); 1406 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1407 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1408 1409 sc->sc_tsfth = htsfth; 1410 1411 #ifdef RTW_DEBUG 1412 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 1413 (IFF_DEBUG|IFF_LINK2)) { 1414 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1415 rate, rssi); 1416 } 1417 #endif /* RTW_DEBUG */ 1418 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1419 ieee80211_release_node(&sc->sc_ic, ni); 1420 next: 1421 rtw_rxdesc_init(sc->sc_dmat, sc->sc_desc_dmamap, 1422 hrx, srx, next, RTW_DEBUG_RECV_DESC); 1423 } 1424 KASSERT(sc->sc_rxnext < RTW_RXQLEN); 1425 1426 sc->sc_rxnext = next; 1427 1428 return; 1429 } 1430 1431 static void 1432 rtw_txbuf_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1433 struct rtw_txctl *stx) 1434 { 1435 struct mbuf *m; 1436 struct ieee80211_node *ni; 1437 1438 m = stx->stx_mbuf; 1439 ni = stx->stx_ni; 1440 KASSERT(m != NULL); 1441 KASSERT(ni != NULL); 1442 stx->stx_mbuf = NULL; 1443 stx->stx_ni = NULL; 1444 1445 bus_dmamap_sync(dmat, stx->stx_dmamap, 0, stx->stx_dmamap->dm_mapsize, 1446 BUS_DMASYNC_POSTWRITE); 1447 bus_dmamap_unload(dmat, stx->stx_dmamap); 1448 m_freem(m); 1449 ieee80211_release_node(ic, ni); 1450 } 1451 1452 static void 1453 rtw_txbufs_release(bus_dma_tag_t dmat, bus_dmamap_t desc_dmamap, 1454 struct ieee80211com *ic, struct rtw_txctl_blk *stc, 1455 struct rtw_txdesc_blk *htc) 1456 { 1457 int desc, i; 1458 struct rtw_txctl *stx; 1459 1460 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1461 rtw_txdescs_sync(dmat, desc_dmamap, htc, stx->stx_first, 1462 stx->stx_dmamap->dm_nsegs, 1463 BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 1464 for (i = 0, desc = stx->stx_first; 1465 i < stx->stx_dmamap->dm_nsegs; 1466 i++, desc = RTW_NEXT_IDX(htc, desc)) { 1467 htc->htc_desc[desc].htx_ctl0 &= 1468 ~htole32(RTW_TXCTL0_OWN); 1469 } 1470 rtw_txdescs_sync(dmat, desc_dmamap, htc, stx->stx_first, 1471 stx->stx_dmamap->dm_nsegs, 1472 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1473 htc->htc_nfree += stx->stx_dmamap->dm_nsegs; 1474 rtw_txbuf_release(dmat, ic, stx); 1475 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1476 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1477 } 1478 htc->htc_next = 0; 1479 } 1480 1481 static __inline void 1482 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *htc, 1483 struct rtw_txctl *stx, int ndesc) 1484 { 1485 uint32_t hstat; 1486 int data_retry, rts_retry; 1487 struct rtw_txdesc *htx0, *htxn; 1488 const char *condstring; 1489 1490 rtw_txbuf_release(sc->sc_dmat, &sc->sc_ic, stx); 1491 1492 htc->htc_nfree += ndesc; 1493 1494 htx0 = &htc->htc_desc[stx->stx_first]; 1495 htxn = &htc->htc_desc[stx->stx_last]; 1496 1497 hstat = le32toh(htx0->htx_stat); 1498 rts_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1499 data_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_DRC_MASK); 1500 1501 sc->sc_if.if_collisions += rts_retry + data_retry; 1502 1503 if ((hstat & RTW_TXSTAT_TOK) != 0) 1504 condstring = "ok"; 1505 else { 1506 sc->sc_if.if_oerrors++; 1507 condstring = "error"; 1508 } 1509 1510 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1511 ("%s: stx %p txdesc[%d, %d] %s tries rts %u data %u\n", 1512 sc->sc_dev.dv_xname, stx, stx->stx_first, stx->stx_last, 1513 condstring, rts_retry, data_retry)); 1514 } 1515 1516 /* Collect transmitted packets. */ 1517 static __inline void 1518 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txctl_blk *stc, 1519 struct rtw_txdesc_blk *htc) 1520 { 1521 int ndesc; 1522 struct rtw_txctl *stx; 1523 1524 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1525 ndesc = 1 + stx->stx_last - stx->stx_first; 1526 if (stx->stx_last < stx->stx_first) 1527 ndesc += htc->htc_ndesc; 1528 1529 KASSERT(ndesc > 0); 1530 1531 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, htc, 1532 stx->stx_first, ndesc, 1533 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1534 1535 if ((htc->htc_desc[stx->stx_first].htx_stat & 1536 htole32(RTW_TXSTAT_OWN)) != 0) 1537 break; 1538 1539 rtw_collect_txpkt(sc, htc, stx, ndesc); 1540 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1541 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1542 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1543 } 1544 if (stx == NULL) 1545 stc->stc_tx_timer = 0; 1546 } 1547 1548 static void 1549 rtw_intr_tx(struct rtw_softc *sc, u_int16_t isr) 1550 { 1551 int pri; 1552 struct rtw_txctl_blk *stc; 1553 struct rtw_txdesc_blk *htc; 1554 1555 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1556 stc = &sc->sc_txctl_blk[pri]; 1557 htc = &sc->sc_txdesc_blk[pri]; 1558 1559 rtw_collect_txring(sc, stc, htc); 1560 1561 if ((isr & RTW_INTR_TX) != 0) 1562 rtw_start(&sc->sc_if); 1563 } 1564 1565 /* TBD */ 1566 return; 1567 } 1568 1569 static void 1570 rtw_intr_beacon(struct rtw_softc *sc, u_int16_t isr) 1571 { 1572 /* TBD */ 1573 return; 1574 } 1575 1576 static void 1577 rtw_intr_atim(struct rtw_softc *sc) 1578 { 1579 /* TBD */ 1580 return; 1581 } 1582 1583 #ifdef RTW_DEBUG 1584 static void 1585 rtw_dump_rings(struct rtw_softc *sc) 1586 { 1587 struct rtw_txdesc_blk *htc; 1588 struct rtw_rxdesc *hrx; 1589 int desc, pri; 1590 1591 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1592 return; 1593 1594 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1595 htc = &sc->sc_txdesc_blk[pri]; 1596 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1597 htc->htc_ndesc, htc->htc_nfree); 1598 for (desc = 0; desc < htc->htc_ndesc; desc++) 1599 rtw_print_txdesc(sc, ".", NULL, htc, desc); 1600 } 1601 1602 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1603 hrx = &sc->sc_rxdesc[desc]; 1604 printf("%s: ctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1605 "rsvd1/tsfth %08x\n", __func__, 1606 le32toh(hrx->hrx_ctl), le32toh(hrx->hrx_rssi), 1607 le32toh(hrx->hrx_buf), le32toh(hrx->hrx_tsfth)); 1608 } 1609 } 1610 #endif /* RTW_DEBUG */ 1611 1612 static void 1613 rtw_hwring_setup(struct rtw_softc *sc) 1614 { 1615 struct rtw_regs *regs = &sc->sc_regs; 1616 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1617 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1618 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1619 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1620 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1621 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1622 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1623 ("%s: reg[TLPDA] <- %" PRIxPTR "\n", __func__, 1624 (uintptr_t)RTW_RING_BASE(sc, hd_txlo))); 1625 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1626 ("%s: reg[TNPDA] <- %" PRIxPTR "\n", __func__, 1627 (uintptr_t)RTW_RING_BASE(sc, hd_txmd))); 1628 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1629 ("%s: reg[THPDA] <- %" PRIxPTR "\n", __func__, 1630 (uintptr_t)RTW_RING_BASE(sc, hd_txhi))); 1631 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1632 ("%s: reg[TBDA] <- %" PRIxPTR "\n", __func__, 1633 (uintptr_t)RTW_RING_BASE(sc, hd_bcn))); 1634 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1635 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1636 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1637 } 1638 1639 static void 1640 rtw_swring_setup(struct rtw_softc *sc) 1641 { 1642 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1643 1644 rtw_txctl_blk_init_all(&sc->sc_txctl_blk[0]); 1645 1646 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1647 0, RTW_RXQLEN, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1648 rtw_rxctl_init_all(sc->sc_dmat, sc->sc_rxctl, &sc->sc_rxnext, 1649 sc->sc_dev.dv_xname); 1650 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, 1651 sc->sc_rxdesc, sc->sc_rxctl, 1652 RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK); 1653 1654 rtw_txdescs_sync_all(sc->sc_dmat, sc->sc_desc_dmamap, 1655 &sc->sc_txdesc_blk[0]); 1656 #if 0 /* redundant with rtw_rxdesc_init_all */ 1657 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1658 0, RTW_RXQLEN, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1659 #endif 1660 } 1661 1662 static void 1663 rtw_txdesc_blk_reset(struct rtw_txdesc_blk *htc) 1664 { 1665 int i; 1666 1667 for (i = 0; i < htc->htc_ndesc; i++) 1668 htc->htc_desc[i].htx_next = htole32(RTW_NEXT_DESC(htc, i)); 1669 } 1670 1671 static void 1672 rtw_txdescs_reset(struct rtw_softc *sc) 1673 { 1674 int pri; 1675 struct rtw_txdesc_blk *htc; 1676 1677 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1678 htc = &sc->sc_txdesc_blk[pri]; 1679 rtw_txbufs_release(sc->sc_dmat, sc->sc_desc_dmamap, &sc->sc_ic, 1680 &sc->sc_txctl_blk[pri], htc); 1681 rtw_txdesc_blk_reset(htc); 1682 KASSERT(htc->htc_nfree == htc->htc_ndesc); 1683 } 1684 } 1685 1686 static void 1687 rtw_rxdescs_reset(struct rtw_softc *sc) 1688 { 1689 /* Re-initialize descriptors, just in case. */ 1690 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_rxdesc, 1691 &sc->sc_rxctl[0], RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK); 1692 1693 /* Reset to start of ring. */ 1694 sc->sc_rxnext = 0; 1695 } 1696 1697 static void 1698 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 1699 { 1700 struct rtw_regs *regs = &sc->sc_regs; 1701 1702 if ((isr & RTW_INTR_TXFOVW) != 0) 1703 printf("%s: tx fifo overflow\n", sc->sc_dev.dv_xname); 1704 1705 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) == 0) 1706 return; 1707 1708 printf("%s: restarting xmit/recv\n", sc->sc_dev.dv_xname); 1709 1710 rtw_dump_rings(sc); 1711 1712 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1713 1714 /* Collect rx'd packets. Refresh rx buffers. */ 1715 rtw_intr_rx(sc, 0); 1716 /* Collect tx'd packets. */ 1717 rtw_intr_tx(sc, 0); 1718 1719 RTW_WRITE16(regs, RTW_IMR, 0); 1720 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1721 1722 rtw_chip_reset1(regs, sc->sc_dev.dv_xname); 1723 1724 rtw_rxdescs_reset(sc); 1725 rtw_txdescs_reset(sc); 1726 1727 rtw_hwring_setup(sc); 1728 1729 rtw_dump_rings(sc); 1730 1731 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1732 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1733 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1734 } 1735 1736 static __inline void 1737 rtw_suspend_ticks(struct rtw_softc *sc) 1738 { 1739 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1740 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 1741 sc->sc_do_tick = 0; 1742 } 1743 1744 static __inline void 1745 rtw_resume_ticks(struct rtw_softc *sc) 1746 { 1747 u_int32_t tsftrl0, tsftrl1, next_tick; 1748 1749 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1750 1751 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1752 next_tick = tsftrl1 + 1000000; 1753 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1754 1755 sc->sc_do_tick = 1; 1756 1757 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1758 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1759 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 1760 } 1761 1762 static void 1763 rtw_intr_timeout(struct rtw_softc *sc) 1764 { 1765 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 1766 if (sc->sc_do_tick) 1767 rtw_resume_ticks(sc); 1768 return; 1769 } 1770 1771 int 1772 rtw_intr(void *arg) 1773 { 1774 int i; 1775 struct rtw_softc *sc = arg; 1776 struct rtw_regs *regs = &sc->sc_regs; 1777 u_int16_t isr; 1778 1779 /* 1780 * If the interface isn't running, the interrupt couldn't 1781 * possibly have come from us. 1782 */ 1783 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1784 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1785 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1786 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1787 return (0); 1788 } 1789 1790 for (i = 0; i < 10; i++) { 1791 isr = RTW_READ16(regs, RTW_ISR); 1792 1793 RTW_WRITE16(regs, RTW_ISR, isr); 1794 RTW_WBR(regs, RTW_ISR, RTW_ISR); 1795 1796 if (sc->sc_intr_ack != NULL) 1797 (*sc->sc_intr_ack)(regs); 1798 1799 if (isr == 0) 1800 break; 1801 1802 #ifdef RTW_DEBUG 1803 #define PRINTINTR(flag) do { \ 1804 if ((isr & flag) != 0) { \ 1805 printf("%s" #flag, delim); \ 1806 delim = ","; \ 1807 } \ 1808 } while (0) 1809 1810 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 1811 const char *delim = "<"; 1812 1813 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1814 1815 PRINTINTR(RTW_INTR_TXFOVW); 1816 PRINTINTR(RTW_INTR_TIMEOUT); 1817 PRINTINTR(RTW_INTR_BCNINT); 1818 PRINTINTR(RTW_INTR_ATIMINT); 1819 PRINTINTR(RTW_INTR_TBDER); 1820 PRINTINTR(RTW_INTR_TBDOK); 1821 PRINTINTR(RTW_INTR_THPDER); 1822 PRINTINTR(RTW_INTR_THPDOK); 1823 PRINTINTR(RTW_INTR_TNPDER); 1824 PRINTINTR(RTW_INTR_TNPDOK); 1825 PRINTINTR(RTW_INTR_RXFOVW); 1826 PRINTINTR(RTW_INTR_RDU); 1827 PRINTINTR(RTW_INTR_TLPDER); 1828 PRINTINTR(RTW_INTR_TLPDOK); 1829 PRINTINTR(RTW_INTR_RER); 1830 PRINTINTR(RTW_INTR_ROK); 1831 1832 printf(">\n"); 1833 } 1834 #undef PRINTINTR 1835 #endif /* RTW_DEBUG */ 1836 1837 if ((isr & RTW_INTR_RX) != 0) 1838 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1839 if ((isr & RTW_INTR_TX) != 0) 1840 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1841 if ((isr & RTW_INTR_BEACON) != 0) 1842 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1843 if ((isr & RTW_INTR_ATIMINT) != 0) 1844 rtw_intr_atim(sc); 1845 if ((isr & RTW_INTR_IOERROR) != 0) 1846 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1847 if ((isr & RTW_INTR_TIMEOUT) != 0) 1848 rtw_intr_timeout(sc); 1849 } 1850 1851 return 1; 1852 } 1853 1854 /* Must be called at splnet. */ 1855 static void 1856 rtw_stop(struct ifnet *ifp, int disable) 1857 { 1858 int pri; 1859 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1860 struct ieee80211com *ic = &sc->sc_ic; 1861 struct rtw_regs *regs = &sc->sc_regs; 1862 1863 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1864 return; 1865 1866 rtw_suspend_ticks(sc); 1867 1868 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1869 1870 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1871 /* Disable interrupts. */ 1872 RTW_WRITE16(regs, RTW_IMR, 0); 1873 1874 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 1875 1876 /* Stop the transmit and receive processes. First stop DMA, 1877 * then disable receiver and transmitter. 1878 */ 1879 RTW_WRITE8(regs, RTW_TPPOLL, 1880 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ| 1881 RTW_TPPOLL_SLPQ); 1882 1883 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 1884 1885 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1886 } 1887 1888 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1889 rtw_txbufs_release(sc->sc_dmat, sc->sc_desc_dmamap, &sc->sc_ic, 1890 &sc->sc_txctl_blk[pri], &sc->sc_txdesc_blk[pri]); 1891 } 1892 1893 if (disable) { 1894 rtw_disable(sc); 1895 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1896 } 1897 1898 /* Mark the interface as not running. Cancel the watchdog timer. */ 1899 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1900 ifp->if_timer = 0; 1901 1902 return; 1903 } 1904 1905 const char * 1906 rtw_pwrstate_string(enum rtw_pwrstate power) 1907 { 1908 switch (power) { 1909 case RTW_ON: 1910 return "on"; 1911 case RTW_SLEEP: 1912 return "sleep"; 1913 case RTW_OFF: 1914 return "off"; 1915 default: 1916 return "unknown"; 1917 } 1918 } 1919 1920 /* XXX For Maxim, I am using the RFMD settings gleaned from the 1921 * reference driver, plus a magic Maxim "ON" value that comes from 1922 * the Realtek document "Windows PG for Rtl8180." 1923 */ 1924 static void 1925 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1926 int before_rf, int digphy) 1927 { 1928 u_int32_t anaparm; 1929 1930 anaparm = RTW_READ(regs, RTW_ANAPARM); 1931 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1932 1933 switch (power) { 1934 case RTW_OFF: 1935 if (before_rf) 1936 return; 1937 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 1938 anaparm |= RTW_ANAPARM_TXDACOFF; 1939 break; 1940 case RTW_SLEEP: 1941 if (!before_rf) 1942 return; 1943 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 1944 anaparm |= RTW_ANAPARM_TXDACOFF; 1945 break; 1946 case RTW_ON: 1947 if (!before_rf) 1948 return; 1949 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 1950 break; 1951 } 1952 RTW_DPRINTF(RTW_DEBUG_PWR, 1953 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 1954 __func__, rtw_pwrstate_string(power), 1955 (before_rf) ? "before" : "after", anaparm)); 1956 1957 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1958 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1959 } 1960 1961 /* XXX I am using the RFMD settings gleaned from the reference 1962 * driver. They agree 1963 */ 1964 static void 1965 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1966 int before_rf, int digphy) 1967 { 1968 u_int32_t anaparm; 1969 1970 anaparm = RTW_READ(regs, RTW_ANAPARM); 1971 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1972 1973 switch (power) { 1974 case RTW_OFF: 1975 if (before_rf) 1976 return; 1977 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 1978 anaparm |= RTW_ANAPARM_TXDACOFF; 1979 break; 1980 case RTW_SLEEP: 1981 if (!before_rf) 1982 return; 1983 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 1984 anaparm |= RTW_ANAPARM_TXDACOFF; 1985 break; 1986 case RTW_ON: 1987 if (!before_rf) 1988 return; 1989 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 1990 break; 1991 } 1992 RTW_DPRINTF(RTW_DEBUG_PWR, 1993 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 1994 __func__, rtw_pwrstate_string(power), 1995 (before_rf) ? "before" : "after", anaparm)); 1996 1997 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1998 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1999 } 2000 2001 static void 2002 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2003 int before_rf, int digphy) 2004 { 2005 u_int32_t anaparm; 2006 2007 anaparm = RTW_READ(regs, RTW_ANAPARM); 2008 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2009 2010 switch (power) { 2011 case RTW_OFF: 2012 if (before_rf) 2013 return; 2014 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2015 anaparm |= RTW_ANAPARM_TXDACOFF; 2016 break; 2017 case RTW_SLEEP: 2018 if (!before_rf) 2019 return; 2020 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2021 anaparm |= RTW_ANAPARM_TXDACOFF; 2022 break; 2023 case RTW_ON: 2024 if (!before_rf) 2025 return; 2026 if (digphy) { 2027 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2028 /* XXX guess */ 2029 anaparm |= RTW_ANAPARM_TXDACOFF; 2030 } else 2031 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2032 break; 2033 } 2034 RTW_DPRINTF(RTW_DEBUG_PWR, 2035 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2036 __func__, rtw_pwrstate_string(power), 2037 (before_rf) ? "before" : "after", anaparm)); 2038 2039 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2040 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2041 } 2042 2043 static void 2044 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2045 int digphy) 2046 { 2047 struct rtw_regs *regs = &sc->sc_regs; 2048 2049 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 2050 2051 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2052 2053 rtw_set_access(sc, RTW_ACCESS_NONE); 2054 2055 return; 2056 } 2057 2058 static int 2059 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2060 { 2061 int rc; 2062 2063 RTW_DPRINTF(RTW_DEBUG_PWR, 2064 ("%s: %s->%s\n", __func__, 2065 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2066 2067 if (sc->sc_pwrstate == power) 2068 return 0; 2069 2070 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2071 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2072 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2073 2074 switch (power) { 2075 case RTW_ON: 2076 /* TBD set LEDs */ 2077 break; 2078 case RTW_SLEEP: 2079 /* TBD */ 2080 break; 2081 case RTW_OFF: 2082 /* TBD */ 2083 break; 2084 } 2085 if (rc == 0) 2086 sc->sc_pwrstate = power; 2087 else 2088 sc->sc_pwrstate = RTW_OFF; 2089 return rc; 2090 } 2091 2092 static int 2093 rtw_tune(struct rtw_softc *sc) 2094 { 2095 struct ieee80211com *ic = &sc->sc_ic; 2096 u_int chan; 2097 int rc; 2098 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2099 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2100 2101 KASSERT(ic->ic_bss->ni_chan != NULL); 2102 2103 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2104 if (chan == IEEE80211_CHAN_ANY) 2105 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 2106 2107 if (chan == sc->sc_cur_chan) { 2108 RTW_DPRINTF(RTW_DEBUG_TUNE, 2109 ("%s: already tuned chan #%d\n", __func__, chan)); 2110 return 0; 2111 } 2112 2113 rtw_suspend_ticks(sc); 2114 2115 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 2116 2117 /* TBD wait for Tx to complete */ 2118 2119 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2120 2121 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2122 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 2123 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 2124 dflantb, RTW_ON)) != 0) { 2125 /* XXX condition on powersaving */ 2126 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2127 } 2128 2129 sc->sc_cur_chan = chan; 2130 2131 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 2132 2133 rtw_resume_ticks(sc); 2134 2135 return rc; 2136 } 2137 2138 void 2139 rtw_disable(struct rtw_softc *sc) 2140 { 2141 int rc; 2142 2143 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2144 return; 2145 2146 /* turn off PHY */ 2147 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2148 printf("%s: failed to turn off PHY (%d)\n", 2149 sc->sc_dev.dv_xname, rc); 2150 2151 if (sc->sc_disable != NULL) 2152 (*sc->sc_disable)(sc); 2153 2154 sc->sc_flags &= ~RTW_F_ENABLED; 2155 } 2156 2157 int 2158 rtw_enable(struct rtw_softc *sc) 2159 { 2160 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2161 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2162 printf("%s: device enable failed\n", 2163 sc->sc_dev.dv_xname); 2164 return (EIO); 2165 } 2166 sc->sc_flags |= RTW_F_ENABLED; 2167 } 2168 return (0); 2169 } 2170 2171 static void 2172 rtw_transmit_config(struct rtw_regs *regs) 2173 { 2174 u_int32_t tcr; 2175 2176 tcr = RTW_READ(regs, RTW_TCR); 2177 2178 tcr |= RTW_TCR_CWMIN; 2179 tcr &= ~RTW_TCR_MXDMA_MASK; 2180 tcr |= RTW_TCR_MXDMA_256; 2181 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2182 tcr &= ~RTW_TCR_LBK_MASK; 2183 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2184 2185 /* set short/long retry limits */ 2186 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2187 tcr |= LSHIFT(4, RTW_TCR_SRL_MASK) | LSHIFT(4, RTW_TCR_LRL_MASK); 2188 2189 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2190 2191 RTW_WRITE(regs, RTW_TCR, tcr); 2192 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2193 } 2194 2195 static __inline void 2196 rtw_enable_interrupts(struct rtw_softc *sc) 2197 { 2198 struct rtw_regs *regs = &sc->sc_regs; 2199 2200 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2201 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2202 2203 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2204 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2205 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2206 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2207 2208 /* XXX necessary? */ 2209 if (sc->sc_intr_ack != NULL) 2210 (*sc->sc_intr_ack)(regs); 2211 } 2212 2213 static void 2214 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2215 { 2216 uint8_t msr; 2217 2218 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2219 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2220 2221 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2222 2223 switch (opmode) { 2224 case IEEE80211_M_AHDEMO: 2225 case IEEE80211_M_IBSS: 2226 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2227 break; 2228 case IEEE80211_M_HOSTAP: 2229 msr |= RTW_MSR_NETYPE_AP_OK; 2230 break; 2231 case IEEE80211_M_MONITOR: 2232 /* XXX */ 2233 msr |= RTW_MSR_NETYPE_NOLINK; 2234 break; 2235 case IEEE80211_M_STA: 2236 msr |= RTW_MSR_NETYPE_INFRA_OK; 2237 break; 2238 } 2239 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2240 2241 rtw_set_access(sc, RTW_ACCESS_NONE); 2242 } 2243 2244 /* XXX is the endianness correct? test. */ 2245 #define rtw_calchash(addr) \ 2246 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 2247 2248 static void 2249 rtw_pktfilt_load(struct rtw_softc *sc) 2250 { 2251 struct rtw_regs *regs = &sc->sc_regs; 2252 struct ieee80211com *ic = &sc->sc_ic; 2253 struct ethercom *ec = &ic->ic_ec; 2254 struct ifnet *ifp = &sc->sc_ic.ic_if; 2255 int hash; 2256 u_int32_t hashes[2] = { 0, 0 }; 2257 struct ether_multi *enm; 2258 struct ether_multistep step; 2259 2260 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2261 2262 #define RTW_RCR_MONITOR (RTW_RCR_ACRC32|RTW_RCR_APM|RTW_RCR_AAP|RTW_RCR_AB|RTW_RCR_ACF | RTW_RCR_AICV | RTW_RCR_ACRC32) 2263 2264 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2265 sc->sc_rcr |= RTW_RCR_MONITOR; 2266 else 2267 sc->sc_rcr &= ~RTW_RCR_MONITOR; 2268 2269 /* XXX reference sources BEGIN */ 2270 sc->sc_rcr |= RTW_RCR_ENMARP; 2271 sc->sc_rcr |= RTW_RCR_AB | RTW_RCR_AM | RTW_RCR_APM; 2272 #if 0 2273 /* receive broadcasts in our BSS */ 2274 sc->sc_rcr |= RTW_RCR_ADD3; 2275 #endif 2276 /* XXX reference sources END */ 2277 2278 /* receive pwrmgmt frames. */ 2279 sc->sc_rcr |= RTW_RCR_APWRMGT; 2280 /* receive mgmt/ctrl/data frames. */ 2281 sc->sc_rcr |= RTW_RCR_ADF | RTW_RCR_AMF; 2282 /* initialize Rx DMA threshold, Tx DMA burst size */ 2283 sc->sc_rcr |= RTW_RCR_RXFTH_WHOLE | RTW_RCR_MXDMA_1024; 2284 2285 ifp->if_flags &= ~IFF_ALLMULTI; 2286 2287 if (ifp->if_flags & IFF_PROMISC) { 2288 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2289 allmulti: 2290 ifp->if_flags |= IFF_ALLMULTI; 2291 goto setit; 2292 } 2293 2294 /* 2295 * Program the 64-bit multicast hash filter. 2296 */ 2297 ETHER_FIRST_MULTI(step, ec, enm); 2298 while (enm != NULL) { 2299 /* XXX */ 2300 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2301 ETHER_ADDR_LEN) != 0) 2302 goto allmulti; 2303 2304 hash = rtw_calchash(enm->enm_addrlo); 2305 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2306 ETHER_NEXT_MULTI(step, enm); 2307 } 2308 2309 if (ifp->if_flags & IFF_BROADCAST) { 2310 hash = rtw_calchash(etherbroadcastaddr); 2311 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2312 } 2313 2314 /* all bits set => hash is useless */ 2315 if (~(hashes[0] & hashes[1]) == 0) 2316 goto allmulti; 2317 2318 setit: 2319 if (ifp->if_flags & IFF_ALLMULTI) 2320 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2321 2322 if (ic->ic_state == IEEE80211_S_SCAN) 2323 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2324 2325 hashes[0] = hashes[1] = 0xffffffff; 2326 2327 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2328 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2329 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2330 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2331 2332 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2333 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2334 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2335 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2336 2337 return; 2338 } 2339 2340 /* Must be called at splnet. */ 2341 static int 2342 rtw_init(struct ifnet *ifp) 2343 { 2344 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2345 struct ieee80211com *ic = &sc->sc_ic; 2346 struct rtw_regs *regs = &sc->sc_regs; 2347 int rc = 0; 2348 2349 if ((rc = rtw_enable(sc)) != 0) 2350 goto out; 2351 2352 /* Cancel pending I/O and reset. */ 2353 rtw_stop(ifp, 0); 2354 2355 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2356 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2357 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2358 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2359 2360 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2361 goto out; 2362 2363 rtw_swring_setup(sc); 2364 2365 rtw_transmit_config(regs); 2366 2367 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2368 2369 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2370 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2371 2372 /* long PLCP header, 1Mbps basic rate */ 2373 RTW_WRITE16(regs, RTW_BRSR, 0x0f); 2374 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2375 2376 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 2377 rtw_set_access(sc, RTW_ACCESS_NONE); 2378 2379 #if 0 2380 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_GWAKE|RTW_FEMR_WKUP|RTW_FEMR_INTR); 2381 #endif 2382 /* XXX from reference sources */ 2383 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2384 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2385 2386 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2387 2388 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2389 /* from Linux driver */ 2390 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2391 2392 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2393 2394 rtw_enable_interrupts(sc); 2395 2396 rtw_pktfilt_load(sc); 2397 2398 rtw_hwring_setup(sc); 2399 2400 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2401 2402 ifp->if_flags |= IFF_RUNNING; 2403 ic->ic_state = IEEE80211_S_INIT; 2404 2405 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2406 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2407 2408 rtw_resume_ticks(sc); 2409 2410 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2411 2412 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2413 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2414 else 2415 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2416 2417 out: 2418 return rc; 2419 } 2420 2421 static int 2422 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2423 { 2424 int rc = 0, s; 2425 struct rtw_softc *sc = ifp->if_softc; 2426 struct ifreq *ifr = (struct ifreq *)data; 2427 2428 s = splnet(); 2429 switch (cmd) { 2430 case SIOCSIFFLAGS: 2431 if ((ifp->if_flags & IFF_UP) != 0) { 2432 if (0 && (sc->sc_flags & RTW_F_ENABLED) != 0) { 2433 rtw_pktfilt_load(sc); 2434 } else 2435 rc = rtw_init(ifp); 2436 #ifdef RTW_DEBUG 2437 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2438 #endif /* RTW_DEBUG */ 2439 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2440 #ifdef RTW_DEBUG 2441 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2442 #endif /* RTW_DEBUG */ 2443 rtw_stop(ifp, 1); 2444 } 2445 break; 2446 case SIOCADDMULTI: 2447 case SIOCDELMULTI: 2448 if (cmd == SIOCADDMULTI) 2449 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2450 else 2451 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2452 if (rc == ENETRESET) { 2453 if (ifp->if_flags & IFF_RUNNING) 2454 rtw_pktfilt_load(sc); 2455 rc = 0; 2456 } 2457 break; 2458 default: 2459 if ((rc = ieee80211_ioctl(ifp, cmd, data)) == ENETRESET) { 2460 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2461 rc = rtw_init(ifp); 2462 else 2463 rc = 0; 2464 } 2465 break; 2466 } 2467 splx(s); 2468 return rc; 2469 } 2470 2471 /* Point *mp at the next 802.11 frame to transmit. Point *stcp 2472 * at the driver's selection of transmit control block for the packet. 2473 */ 2474 static __inline int 2475 rtw_dequeue(struct ifnet *ifp, struct rtw_txctl_blk **stcp, 2476 struct rtw_txdesc_blk **htcp, struct mbuf **mp, 2477 struct ieee80211_node **nip) 2478 { 2479 struct rtw_txctl_blk *stc; 2480 struct rtw_txdesc_blk *htc; 2481 struct mbuf *m0; 2482 struct rtw_softc *sc; 2483 struct ieee80211com *ic; 2484 2485 sc = (struct rtw_softc *)ifp->if_softc; 2486 2487 DPRINTF(sc, RTW_DEBUG_XMIT, 2488 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2489 *mp = NULL; 2490 2491 stc = &sc->sc_txctl_blk[RTW_TXPRIMD]; 2492 htc = &sc->sc_txdesc_blk[RTW_TXPRIMD]; 2493 2494 if (SIMPLEQ_EMPTY(&stc->stc_freeq) || htc->htc_nfree == 0) { 2495 DPRINTF(sc, RTW_DEBUG_XMIT, 2496 ("%s: out of descriptors\n", __func__)); 2497 ifp->if_flags |= IFF_OACTIVE; 2498 return 0; 2499 } 2500 2501 ic = &sc->sc_ic; 2502 2503 if (!IF_IS_EMPTY(&ic->ic_mgtq)) { 2504 IF_DEQUEUE(&ic->ic_mgtq, m0); 2505 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2506 m0->m_pkthdr.rcvif = NULL; 2507 DPRINTF(sc, RTW_DEBUG_XMIT, 2508 ("%s: dequeue mgt frame\n", __func__)); 2509 } else if (ic->ic_state != IEEE80211_S_RUN) { 2510 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 2511 return 0; 2512 } else if (!IF_IS_EMPTY(&ic->ic_pwrsaveq)) { 2513 IF_DEQUEUE(&ic->ic_pwrsaveq, m0); 2514 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2515 m0->m_pkthdr.rcvif = NULL; 2516 DPRINTF(sc, RTW_DEBUG_XMIT, 2517 ("%s: dequeue pwrsave frame\n", __func__)); 2518 } else { 2519 IFQ_POLL(&ifp->if_snd, m0); 2520 if (m0 == NULL) { 2521 DPRINTF(sc, RTW_DEBUG_XMIT, 2522 ("%s: no frame\n", __func__)); 2523 return 0; 2524 } 2525 DPRINTF(sc, RTW_DEBUG_XMIT, 2526 ("%s: dequeue data frame\n", __func__)); 2527 IFQ_DEQUEUE(&ifp->if_snd, m0); 2528 ifp->if_opackets++; 2529 #if NBPFILTER > 0 2530 if (ifp->if_bpf) 2531 bpf_mtap(ifp->if_bpf, m0); 2532 #endif 2533 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2534 DPRINTF(sc, RTW_DEBUG_XMIT, 2535 ("%s: encap error\n", __func__)); 2536 ifp->if_oerrors++; 2537 return -1; 2538 } 2539 } 2540 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 2541 *stcp = stc; 2542 *htcp = htc; 2543 *mp = m0; 2544 return 0; 2545 } 2546 2547 static int 2548 rtw_seg_too_short(bus_dmamap_t dmamap) 2549 { 2550 int i; 2551 for (i = 0; i < dmamap->dm_nsegs; i++) { 2552 if (dmamap->dm_segs[i].ds_len < 4) { 2553 printf("%s: segment too short\n", __func__); 2554 return 1; 2555 } 2556 } 2557 return 0; 2558 } 2559 2560 /* TBD factor with atw_start */ 2561 static struct mbuf * 2562 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2563 u_int ndescfree, short *ifflagsp, const char *dvname) 2564 { 2565 int first, rc; 2566 struct mbuf *m, *m0; 2567 2568 m0 = chain; 2569 2570 /* 2571 * Load the DMA map. Copy and try (once) again if the packet 2572 * didn't fit in the alloted number of segments. 2573 */ 2574 for (first = 1; 2575 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2576 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2577 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 2578 first = 0) { 2579 if (rc == 0) 2580 bus_dmamap_unload(dmat, dmam); 2581 MGETHDR(m, M_DONTWAIT, MT_DATA); 2582 if (m == NULL) { 2583 printf("%s: unable to allocate Tx mbuf\n", 2584 dvname); 2585 break; 2586 } 2587 if (m0->m_pkthdr.len > MHLEN) { 2588 MCLGET(m, M_DONTWAIT); 2589 if ((m->m_flags & M_EXT) == 0) { 2590 printf("%s: cannot allocate Tx cluster\n", 2591 dvname); 2592 m_freem(m); 2593 break; 2594 } 2595 } 2596 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2597 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 2598 m_freem(m0); 2599 m0 = m; 2600 m = NULL; 2601 } 2602 if (rc != 0) { 2603 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 2604 m_freem(m0); 2605 return NULL; 2606 } else if (rtw_seg_too_short(dmam)) { 2607 printf("%s: cannot load Tx buffer, segment too short\n", 2608 dvname); 2609 bus_dmamap_unload(dmat, dmam); 2610 m_freem(m0); 2611 return NULL; 2612 } else if (dmam->dm_nsegs > ndescfree) { 2613 *ifflagsp |= IFF_OACTIVE; 2614 bus_dmamap_unload(dmat, dmam); 2615 m_freem(m0); 2616 return NULL; 2617 } 2618 return m0; 2619 } 2620 2621 #ifdef RTW_DEBUG 2622 static void 2623 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 2624 struct rtw_txctl *stx, struct rtw_txdesc_blk *htc, int desc) 2625 { 2626 struct rtw_txdesc *htx = &htc->htc_desc[desc]; 2627 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] ctl0 %#08x " 2628 "ctl1 %#08x buf %#08x len %#08x\n", 2629 sc->sc_dev.dv_xname, stx, action, desc, 2630 le32toh(htx->htx_ctl0), 2631 le32toh(htx->htx_ctl1), le32toh(htx->htx_buf), 2632 le32toh(htx->htx_len))); 2633 } 2634 #endif /* RTW_DEBUG */ 2635 2636 static void 2637 rtw_start(struct ifnet *ifp) 2638 { 2639 uint8_t tppoll; 2640 int desc, i, lastdesc, npkt, rate; 2641 uint32_t proto_ctl0, ctl0, ctl1; 2642 bus_dmamap_t dmamap; 2643 struct ieee80211com *ic; 2644 struct ieee80211_duration *d0; 2645 struct ieee80211_frame *wh; 2646 struct ieee80211_node *ni; 2647 struct mbuf *m0; 2648 struct rtw_softc *sc; 2649 struct rtw_txctl_blk *stc; 2650 struct rtw_txdesc_blk *htc; 2651 struct rtw_txctl *stx; 2652 struct rtw_txdesc *htx; 2653 2654 sc = (struct rtw_softc *)ifp->if_softc; 2655 ic = &sc->sc_ic; 2656 2657 DPRINTF(sc, RTW_DEBUG_XMIT, 2658 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2659 2660 /* XXX do real rate control */ 2661 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 2662 2663 switch (rate = MAX(2, ieee80211_get_rate(ic))) { 2664 case 2: 2665 proto_ctl0 |= RTW_TXCTL0_RATE_1MBPS; 2666 break; 2667 case 4: 2668 proto_ctl0 |= RTW_TXCTL0_RATE_2MBPS; 2669 break; 2670 case 11: 2671 proto_ctl0 |= RTW_TXCTL0_RATE_5MBPS; 2672 break; 2673 case 22: 2674 proto_ctl0 |= RTW_TXCTL0_RATE_11MBPS; 2675 break; 2676 } 2677 2678 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 2679 proto_ctl0 |= RTW_TXCTL0_SPLCP; 2680 2681 for (;;) { 2682 if (rtw_dequeue(ifp, &stc, &htc, &m0, &ni) == -1) 2683 continue; 2684 if (m0 == NULL) 2685 break; 2686 stx = SIMPLEQ_FIRST(&stc->stc_freeq); 2687 2688 dmamap = stx->stx_dmamap; 2689 2690 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 2691 htc->htc_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 2692 2693 if (m0 == NULL || dmamap->dm_nsegs == 0) { 2694 DPRINTF(sc, RTW_DEBUG_XMIT, 2695 ("%s: fail dmamap load\n", __func__)); 2696 goto post_dequeue_err; 2697 } 2698 2699 #ifdef RTW_DEBUG 2700 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 2701 (IFF_DEBUG|IFF_LINK2)) { 2702 ieee80211_dump_pkt(mtod(m0, uint8_t *), 2703 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 2704 : sizeof(wh), 2705 rate, 0); 2706 } 2707 #endif /* RTW_DEBUG */ 2708 ctl0 = proto_ctl0 | 2709 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 2710 2711 wh = mtod(m0, struct ieee80211_frame *); 2712 2713 if (ieee80211_compute_duration(wh, m0->m_pkthdr.len, 2714 ic->ic_flags, ic->ic_fragthreshold, 2715 rate, &stx->stx_d0, &stx->stx_dn, &npkt, 2716 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 2717 (IFF_DEBUG|IFF_LINK2)) == -1) { 2718 DPRINTF(sc, RTW_DEBUG_XMIT, 2719 ("%s: fail compute duration\n", __func__)); 2720 goto post_load_err; 2721 } 2722 2723 /* XXX >= ? */ 2724 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 2725 ctl0 |= RTW_TXCTL0_RTSEN; 2726 2727 d0 = &stx->stx_d0; 2728 2729 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 2730 2731 ctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 2732 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 2733 2734 if ((d0->d_plcp_svc & IEEE80211_PLCP_SERVICE_LENEXT) != 0) 2735 ctl1 |= RTW_TXCTL1_LENGEXT; 2736 2737 /* TBD fragmentation */ 2738 2739 stx->stx_first = htc->htc_next; 2740 2741 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2742 htc, stx->stx_first, dmamap->dm_nsegs, 2743 BUS_DMASYNC_PREWRITE); 2744 2745 KASSERT(stx->stx_first < htc->htc_ndesc); 2746 2747 for (i = 0, lastdesc = desc = stx->stx_first; 2748 i < dmamap->dm_nsegs; 2749 i++, desc = RTW_NEXT_IDX(htc, desc)) { 2750 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 2751 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 2752 ("%s: seg too long\n", __func__)); 2753 goto post_load_err; 2754 } 2755 htx = &htc->htc_desc[desc]; 2756 htx->htx_ctl0 = htole32(ctl0); 2757 if (i != 0) 2758 htx->htx_ctl0 |= htole32(RTW_TXCTL0_OWN); 2759 htx->htx_ctl1 = htole32(ctl1); 2760 htx->htx_buf = htole32(dmamap->dm_segs[i].ds_addr); 2761 htx->htx_len = htole32(dmamap->dm_segs[i].ds_len); 2762 lastdesc = desc; 2763 #ifdef RTW_DEBUG 2764 rtw_print_txdesc(sc, "load", stx, htc, desc); 2765 #endif /* RTW_DEBUG */ 2766 } 2767 2768 KASSERT(desc < htc->htc_ndesc); 2769 2770 stx->stx_ni = ni; 2771 stx->stx_mbuf = m0; 2772 stx->stx_last = lastdesc; 2773 htc->htc_desc[stx->stx_last].htx_ctl0 |= htole32(RTW_TXCTL0_LS); 2774 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2775 htole32(RTW_TXCTL0_FS); 2776 2777 #ifdef RTW_DEBUG 2778 rtw_print_txdesc(sc, "FS on", stx, htc, stx->stx_first); 2779 rtw_print_txdesc(sc, "LS on", stx, htc, stx->stx_last); 2780 #endif /* RTW_DEBUG */ 2781 2782 htc->htc_nfree -= dmamap->dm_nsegs; 2783 htc->htc_next = desc; 2784 2785 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2786 htc, stx->stx_first, dmamap->dm_nsegs, 2787 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2788 2789 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2790 htole32(RTW_TXCTL0_OWN); 2791 2792 #ifdef RTW_DEBUG 2793 rtw_print_txdesc(sc, "OWN on", stx, htc, stx->stx_first); 2794 #endif /* RTW_DEBUG */ 2795 2796 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2797 htc, stx->stx_first, 1, 2798 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2799 2800 SIMPLEQ_REMOVE_HEAD(&stc->stc_freeq, stx_q); 2801 SIMPLEQ_INSERT_TAIL(&stc->stc_dirtyq, stx, stx_q); 2802 2803 stc->stc_tx_timer = 5; 2804 ifp->if_timer = 1; 2805 2806 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 2807 2808 /* TBD poke other queues. */ 2809 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll | RTW_TPPOLL_NPQ); 2810 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 2811 } 2812 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 2813 return; 2814 post_load_err: 2815 bus_dmamap_unload(sc->sc_dmat, dmamap); 2816 m_freem(m0); 2817 post_dequeue_err: 2818 ieee80211_release_node(&sc->sc_ic, ni); 2819 return; 2820 } 2821 2822 static void 2823 rtw_watchdog(struct ifnet *ifp) 2824 { 2825 int pri; 2826 struct rtw_softc *sc; 2827 struct rtw_txctl_blk *stc; 2828 2829 sc = ifp->if_softc; 2830 2831 ifp->if_timer = 0; 2832 2833 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2834 return; 2835 2836 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2837 stc = &sc->sc_txctl_blk[pri]; 2838 2839 if (stc->stc_tx_timer == 0) 2840 continue; 2841 2842 if (--stc->stc_tx_timer == 0) { 2843 if (SIMPLEQ_EMPTY(&stc->stc_dirtyq)) 2844 continue; 2845 printf("%s: transmit timeout, priority %d\n", 2846 ifp->if_xname, pri); 2847 ifp->if_oerrors++; 2848 /* XXX do more? */ 2849 rtw_intr_tx(sc, 0); 2850 rtw_txdescs_reset(sc); 2851 rtw_start(ifp); 2852 } else 2853 ifp->if_timer = 1; 2854 } 2855 ieee80211_watchdog(ifp); 2856 return; 2857 } 2858 2859 static void 2860 rtw_start_beacon(struct rtw_softc *sc, int enable) 2861 { 2862 /* TBD */ 2863 return; 2864 } 2865 2866 static void 2867 rtw_next_scan(void *arg) 2868 { 2869 struct ieee80211com *ic = arg; 2870 int s; 2871 2872 /* don't call rtw_start w/o network interrupts blocked */ 2873 s = splnet(); 2874 if (ic->ic_state == IEEE80211_S_SCAN) 2875 ieee80211_next_scan(ic); 2876 splx(s); 2877 } 2878 2879 static void 2880 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, enum ieee80211_opmode opmode, 2881 uint16_t intval0) 2882 { 2883 uint16_t bcnitv, intval; 2884 int i; 2885 struct rtw_regs *regs = &sc->sc_regs; 2886 2887 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 2888 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 2889 2890 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 2891 2892 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2893 2894 intval = MIN(intval0, PRESHIFT(RTW_BCNITV_BCNITV_MASK)); 2895 2896 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 2897 bcnitv |= LSHIFT(intval, RTW_BCNITV_BCNITV_MASK); 2898 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 2899 /* magic from Linux */ 2900 RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND)); 2901 RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV)); 2902 2903 rtw_set_nettype(sc, opmode); 2904 2905 rtw_set_access(sc, RTW_ACCESS_NONE); 2906 2907 /* TBD WEP */ 2908 RTW_WRITE8(regs, RTW_SCR, 0); 2909 2910 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 2911 } 2912 2913 /* Synchronize the hardware state with the software state. */ 2914 static int 2915 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2916 { 2917 struct ifnet *ifp = &ic->ic_if; 2918 struct rtw_softc *sc = ifp->if_softc; 2919 enum ieee80211_state ostate; 2920 int error; 2921 2922 ostate = ic->ic_state; 2923 2924 if (nstate == IEEE80211_S_INIT) { 2925 callout_stop(&sc->sc_scan_ch); 2926 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2927 rtw_start_beacon(sc, 0); 2928 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2929 } 2930 2931 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 2932 rtw_pwrstate(sc, RTW_ON); 2933 2934 if ((error = rtw_tune(sc)) != 0) 2935 return error; 2936 2937 switch (nstate) { 2938 case IEEE80211_S_ASSOC: 2939 rtw_join_bss(sc, ic->ic_bss->ni_bssid, ic->ic_opmode, 2940 ic->ic_bss->ni_intval); 2941 break; 2942 case IEEE80211_S_INIT: 2943 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2944 break; 2945 case IEEE80211_S_SCAN: 2946 if (ostate != IEEE80211_S_SCAN) { 2947 (void)memset(ic->ic_bss->ni_bssid, 0, 2948 IEEE80211_ADDR_LEN); 2949 rtw_join_bss(sc, ic->ic_bss->ni_bssid, ic->ic_opmode, 2950 ic->ic_bss->ni_intval); 2951 } 2952 2953 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 2954 rtw_next_scan, ic); 2955 2956 break; 2957 case IEEE80211_S_RUN: 2958 if (ic->ic_opmode == IEEE80211_M_STA) 2959 break; 2960 /*FALLTHROUGH*/ 2961 case IEEE80211_S_AUTH: 2962 #if 0 2963 rtw_write_bcn_thresh(sc); 2964 rtw_write_ssid(sc); 2965 rtw_write_sup_rates(sc); 2966 #endif 2967 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2968 ic->ic_opmode == IEEE80211_M_MONITOR) 2969 break; 2970 2971 /* TBD set listen interval */ 2972 2973 #if 0 2974 rtw_tsf(sc); 2975 #endif 2976 break; 2977 } 2978 2979 if (nstate != IEEE80211_S_SCAN) 2980 callout_stop(&sc->sc_scan_ch); 2981 2982 if (nstate == IEEE80211_S_RUN && 2983 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2984 ic->ic_opmode == IEEE80211_M_IBSS)) 2985 rtw_start_beacon(sc, 1); 2986 else 2987 rtw_start_beacon(sc, 0); 2988 2989 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2990 } 2991 2992 static void 2993 rtw_recv_beacon(struct rtw_softc *sc, struct mbuf *m, 2994 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2995 { 2996 (*sc->sc_mtbl.mt_recv_mgmt)(&sc->sc_ic, m, ni, subtype, rssi, rstamp); 2997 return; 2998 } 2999 3000 static void 3001 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3002 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 3003 { 3004 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 3005 3006 switch (subtype) { 3007 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 3008 /* do nothing: hardware answers probe request XXX */ 3009 break; 3010 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3011 case IEEE80211_FC0_SUBTYPE_BEACON: 3012 rtw_recv_beacon(sc, m, ni, subtype, rssi, rstamp); 3013 break; 3014 default: 3015 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3016 break; 3017 } 3018 return; 3019 } 3020 3021 static struct ieee80211_node * 3022 rtw_node_alloc(struct ieee80211com *ic) 3023 { 3024 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 3025 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 3026 3027 DPRINTF(sc, RTW_DEBUG_NODE, 3028 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3029 return ni; 3030 } 3031 3032 static void 3033 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 3034 { 3035 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 3036 3037 DPRINTF(sc, RTW_DEBUG_NODE, 3038 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3039 ether_sprintf(ni->ni_bssid))); 3040 (*sc->sc_mtbl.mt_node_free)(ic, ni); 3041 } 3042 3043 static int 3044 rtw_media_change(struct ifnet *ifp) 3045 { 3046 int error; 3047 3048 error = ieee80211_media_change(ifp); 3049 if (error == ENETRESET) { 3050 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3051 (IFF_RUNNING|IFF_UP)) 3052 rtw_init(ifp); /* XXX lose error */ 3053 error = 0; 3054 } 3055 return error; 3056 } 3057 3058 static void 3059 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3060 { 3061 struct rtw_softc *sc = ifp->if_softc; 3062 3063 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3064 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3065 imr->ifm_status = 0; 3066 return; 3067 } 3068 ieee80211_media_status(ifp, imr); 3069 } 3070 3071 void 3072 rtw_power(int why, void *arg) 3073 { 3074 struct rtw_softc *sc = arg; 3075 struct ifnet *ifp = &sc->sc_ic.ic_if; 3076 int s; 3077 3078 DPRINTF(sc, RTW_DEBUG_PWR, 3079 ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3080 3081 s = splnet(); 3082 switch (why) { 3083 case PWR_STANDBY: 3084 /* XXX do nothing. */ 3085 break; 3086 case PWR_SUSPEND: 3087 rtw_stop(ifp, 0); 3088 if (sc->sc_power != NULL) 3089 (*sc->sc_power)(sc, why); 3090 break; 3091 case PWR_RESUME: 3092 if (ifp->if_flags & IFF_UP) { 3093 if (sc->sc_power != NULL) 3094 (*sc->sc_power)(sc, why); 3095 rtw_init(ifp); 3096 } 3097 break; 3098 case PWR_SOFTSUSPEND: 3099 case PWR_SOFTSTANDBY: 3100 case PWR_SOFTRESUME: 3101 break; 3102 } 3103 splx(s); 3104 } 3105 3106 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 3107 void 3108 rtw_shutdown(void *arg) 3109 { 3110 struct rtw_softc *sc = arg; 3111 3112 rtw_stop(&sc->sc_ic.ic_if, 1); 3113 } 3114 3115 static __inline void 3116 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3117 { 3118 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3119 ifp->if_softc = softc; 3120 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3121 IFF_NOTRAILERS; 3122 ifp->if_ioctl = rtw_ioctl; 3123 ifp->if_start = rtw_start; 3124 ifp->if_watchdog = rtw_watchdog; 3125 ifp->if_init = rtw_init; 3126 ifp->if_stop = rtw_stop; 3127 } 3128 3129 static __inline void 3130 rtw_set80211props(struct ieee80211com *ic) 3131 { 3132 int nrate; 3133 ic->ic_phytype = IEEE80211_T_DS; 3134 ic->ic_opmode = IEEE80211_M_STA; 3135 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3136 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 3137 3138 nrate = 0; 3139 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3140 IEEE80211_RATE_BASIC | 2; 3141 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3142 IEEE80211_RATE_BASIC | 4; 3143 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3144 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3145 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3146 } 3147 3148 static __inline void 3149 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3150 { 3151 mtbl->mt_newstate = ic->ic_newstate; 3152 ic->ic_newstate = rtw_newstate; 3153 3154 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3155 ic->ic_recv_mgmt = rtw_recv_mgmt; 3156 3157 mtbl->mt_node_free = ic->ic_node_free; 3158 ic->ic_node_free = rtw_node_free; 3159 3160 mtbl->mt_node_alloc = ic->ic_node_alloc; 3161 ic->ic_node_alloc = rtw_node_alloc; 3162 } 3163 3164 static __inline void 3165 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 3166 void *arg) 3167 { 3168 /* 3169 * Make sure the interface is shutdown during reboot. 3170 */ 3171 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 3172 if (hooks->rh_shutdown == NULL) 3173 printf("%s: WARNING: unable to establish shutdown hook\n", 3174 dvname); 3175 3176 /* 3177 * Add a suspend hook to make sure we come back up after a 3178 * resume. 3179 */ 3180 hooks->rh_power = powerhook_establish(rtw_power, arg); 3181 if (hooks->rh_power == NULL) 3182 printf("%s: WARNING: unable to establish power hook\n", 3183 dvname); 3184 } 3185 3186 static __inline void 3187 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 3188 void *arg) 3189 { 3190 if (hooks->rh_shutdown != NULL) 3191 shutdownhook_disestablish(hooks->rh_shutdown); 3192 3193 if (hooks->rh_power != NULL) 3194 powerhook_disestablish(hooks->rh_power); 3195 } 3196 3197 static __inline void 3198 rtw_init_radiotap(struct rtw_softc *sc) 3199 { 3200 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3201 sc->sc_rxtap.rr_ihdr.it_len = sizeof(sc->sc_rxtapu); 3202 sc->sc_rxtap.rr_ihdr.it_present = RTW_RX_RADIOTAP_PRESENT; 3203 3204 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3205 sc->sc_txtap.rt_ihdr.it_len = sizeof(sc->sc_txtapu); 3206 sc->sc_txtap.rt_ihdr.it_present = RTW_TX_RADIOTAP_PRESENT; 3207 } 3208 3209 static int 3210 rtw_txctl_blk_setup(struct rtw_txctl_blk *stc, u_int qlen) 3211 { 3212 SIMPLEQ_INIT(&stc->stc_dirtyq); 3213 SIMPLEQ_INIT(&stc->stc_freeq); 3214 stc->stc_ndesc = qlen; 3215 stc->stc_desc = malloc(qlen * sizeof(*stc->stc_desc), M_DEVBUF, 3216 M_NOWAIT); 3217 if (stc->stc_desc == NULL) 3218 return ENOMEM; 3219 return 0; 3220 } 3221 3222 static void 3223 rtw_txctl_blk_cleanup_all(struct rtw_softc *sc) 3224 { 3225 int pri; 3226 struct rtw_txctl_blk *stc; 3227 3228 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3229 stc = &sc->sc_txctl_blk[pri]; 3230 free(stc->stc_desc, M_DEVBUF); 3231 stc->stc_desc = NULL; 3232 } 3233 } 3234 3235 static int 3236 rtw_txctl_blk_setup_all(struct rtw_softc *sc) 3237 { 3238 int pri, rc = 0; 3239 int qlen[RTW_NTXPRI] = 3240 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3241 3242 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3243 rc = rtw_txctl_blk_setup(&sc->sc_txctl_blk[pri], qlen[pri]); 3244 if (rc != 0) 3245 break; 3246 } 3247 return rc; 3248 } 3249 3250 static void 3251 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *htc, struct rtw_txdesc *desc, 3252 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3253 { 3254 htc->htc_ndesc = ndesc; 3255 htc->htc_desc = desc; 3256 htc->htc_physbase = physbase; 3257 htc->htc_ofs = ofs; 3258 3259 (void)memset(htc->htc_desc, 0, 3260 sizeof(htc->htc_desc[0]) * htc->htc_ndesc); 3261 3262 rtw_txdesc_blk_reset(htc); 3263 } 3264 3265 static void 3266 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3267 { 3268 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3269 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3270 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3271 3272 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3273 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3274 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3275 3276 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3277 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3278 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3279 3280 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3281 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3282 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3283 } 3284 3285 static struct rtw_rf * 3286 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, 3287 rtw_rf_write_t rf_write, int digphy) 3288 { 3289 struct rtw_rf *rf; 3290 3291 switch (rfchipid) { 3292 case RTW_RFCHIPID_MAXIM: 3293 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3294 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3295 break; 3296 case RTW_RFCHIPID_PHILIPS: 3297 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3298 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3299 break; 3300 case RTW_RFCHIPID_RFMD: 3301 /* XXX RFMD has no RF constructor */ 3302 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3303 /*FALLTHROUGH*/ 3304 default: 3305 return NULL; 3306 } 3307 rf->rf_continuous_tx_cb = 3308 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3309 rf->rf_continuous_tx_arg = (void *)sc; 3310 return rf; 3311 } 3312 3313 /* Revision C and later use a different PHY delay setting than 3314 * revisions A and B. 3315 */ 3316 static u_int8_t 3317 rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0) 3318 { 3319 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3320 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3321 3322 u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 3323 3324 RTW_WRITE(regs, RTW_RCR, REVAB); 3325 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3326 RTW_WRITE(regs, RTW_RCR, REVC); 3327 3328 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3329 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3330 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3331 3332 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 3333 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3334 3335 return phydelay; 3336 #undef REVC 3337 } 3338 3339 void 3340 rtw_attach(struct rtw_softc *sc) 3341 { 3342 rtw_rf_write_t rf_write; 3343 struct rtw_txctl_blk *stc; 3344 int pri, rc, vers; 3345 3346 #if 0 3347 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_txdesc) == 0, 3348 "RTW_DESC_ALIGNMENT is not a multiple of " 3349 "sizeof(struct rtw_txdesc)"); 3350 3351 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_rxdesc) == 0, 3352 "RTW_DESC_ALIGNMENT is not a multiple of " 3353 "sizeof(struct rtw_rxdesc)"); 3354 3355 CASSERT(RTW_DESC_ALIGNMENT % RTW_MAXPKTSEGS == 0, 3356 "RTW_DESC_ALIGNMENT is not a multiple of RTW_MAXPKTSEGS"); 3357 #endif 3358 3359 NEXT_ATTACH_STATE(sc, DETACHED); 3360 3361 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3362 case RTW_TCR_HWVERID_F: 3363 vers = 'F'; 3364 rf_write = rtw_rf_hostwrite; 3365 break; 3366 case RTW_TCR_HWVERID_D: 3367 vers = 'D'; 3368 if (rtw_host_rfio) 3369 rf_write = rtw_rf_hostwrite; 3370 else 3371 rf_write = rtw_rf_macwrite; 3372 break; 3373 default: 3374 vers = '?'; 3375 rf_write = rtw_rf_macwrite; 3376 break; 3377 } 3378 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, vers); 3379 3380 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3381 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3382 0); 3383 3384 if (rc != 0) { 3385 printf("%s: could not allocate hw descriptors, error %d\n", 3386 sc->sc_dev.dv_xname, rc); 3387 goto err; 3388 } 3389 3390 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3391 3392 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3393 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3394 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3395 3396 if (rc != 0) { 3397 printf("%s: could not map hw descriptors, error %d\n", 3398 sc->sc_dev.dv_xname, rc); 3399 goto err; 3400 } 3401 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3402 3403 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3404 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3405 3406 if (rc != 0) { 3407 printf("%s: could not create DMA map for hw descriptors, " 3408 "error %d\n", sc->sc_dev.dv_xname, rc); 3409 goto err; 3410 } 3411 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3412 3413 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3414 sizeof(struct rtw_descs), NULL, 0); 3415 3416 if (rc != 0) { 3417 printf("%s: could not load DMA map for hw descriptors, " 3418 "error %d\n", sc->sc_dev.dv_xname, rc); 3419 goto err; 3420 } 3421 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3422 3423 if (rtw_txctl_blk_setup_all(sc) != 0) 3424 goto err; 3425 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3426 3427 rtw_txdesc_blk_setup_all(sc); 3428 3429 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3430 3431 sc->sc_rxdesc = &sc->sc_descs->hd_rx[0]; 3432 3433 rtw_rxctls_setup(&sc->sc_rxctl[0]); 3434 3435 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3436 stc = &sc->sc_txctl_blk[pri]; 3437 3438 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3439 &stc->stc_desc[0], stc->stc_ndesc)) != 0) { 3440 printf("%s: could not load DMA map for " 3441 "hw tx descriptors, error %d\n", 3442 sc->sc_dev.dv_xname, rc); 3443 goto err; 3444 } 3445 } 3446 3447 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3448 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxctl[0], 3449 RTW_RXQLEN)) != 0) { 3450 printf("%s: could not load DMA map for hw rx descriptors, " 3451 "error %d\n", sc->sc_dev.dv_xname, rc); 3452 goto err; 3453 } 3454 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3455 3456 /* Reset the chip to a known state. */ 3457 if (rtw_reset(sc) != 0) 3458 goto err; 3459 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3460 3461 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3462 3463 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3464 sc->sc_flags |= RTW_F_9356SROM; 3465 3466 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3467 sc->sc_dev.dv_xname) != 0) 3468 goto err; 3469 3470 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3471 3472 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3473 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3474 sc->sc_dev.dv_xname) != 0) { 3475 printf("%s: attach failed, malformed serial ROM\n", 3476 sc->sc_dev.dv_xname); 3477 goto err; 3478 } 3479 3480 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 3481 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 3482 3483 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 3484 3485 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3486 3487 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, rf_write, 3488 sc->sc_flags & RTW_F_DIGPHY); 3489 3490 if (sc->sc_rf == NULL) { 3491 printf("%s: attach failed, could not attach RF\n", 3492 sc->sc_dev.dv_xname); 3493 goto err; 3494 } 3495 3496 #if 0 3497 if (rtw_identify_rf(&sc->sc_regs, &sc->sc_rftype, 3498 sc->sc_dev.dv_xname) != 0) { 3499 printf("%s: attach failed, unknown RF unidentified\n", 3500 sc->sc_dev.dv_xname); 3501 goto err; 3502 } 3503 #endif 3504 3505 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3506 3507 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 3508 3509 RTW_DPRINTF(RTW_DEBUG_ATTACH, 3510 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 3511 3512 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 3513 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 3514 sc->sc_dev.dv_xname); 3515 3516 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 3517 sc->sc_dev.dv_xname); 3518 3519 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 3520 sc->sc_dev.dv_xname) != 0) 3521 goto err; 3522 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 3523 3524 rtw_setifprops(&sc->sc_if, sc->sc_dev.dv_xname, (void*)sc); 3525 3526 IFQ_SET_READY(&sc->sc_if.if_snd); 3527 3528 rtw_set80211props(&sc->sc_ic); 3529 3530 /* 3531 * Call MI attach routines. 3532 */ 3533 if_attach(&sc->sc_if); 3534 ieee80211_ifattach(&sc->sc_if); 3535 3536 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 3537 3538 /* possibly we should fill in our own sc_send_prresp, since 3539 * the RTL8180 is probably sending probe responses in ad hoc 3540 * mode. 3541 */ 3542 3543 /* complete initialization */ 3544 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 3545 callout_init(&sc->sc_scan_ch); 3546 3547 #if NBPFILTER > 0 3548 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 3549 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 3550 #endif 3551 3552 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 3553 3554 rtw_init_radiotap(sc); 3555 3556 NEXT_ATTACH_STATE(sc, FINISHED); 3557 3558 return; 3559 err: 3560 rtw_detach(sc); 3561 return; 3562 } 3563 3564 int 3565 rtw_detach(struct rtw_softc *sc) 3566 { 3567 int pri; 3568 3569 switch (sc->sc_attach_state) { 3570 case FINISHED: 3571 rtw_stop(&sc->sc_if, 1); 3572 3573 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 3574 (void*)sc); 3575 callout_stop(&sc->sc_scan_ch); 3576 ieee80211_ifdetach(&sc->sc_if); 3577 if_detach(&sc->sc_if); 3578 break; 3579 case FINISH_ID_STA: 3580 case FINISH_RF_ATTACH: 3581 rtw_rf_destroy(sc->sc_rf); 3582 sc->sc_rf = NULL; 3583 /*FALLTHROUGH*/ 3584 case FINISH_PARSE_SROM: 3585 case FINISH_READ_SROM: 3586 rtw_srom_free(&sc->sc_srom); 3587 /*FALLTHROUGH*/ 3588 case FINISH_RESET: 3589 case FINISH_RXMAPS_CREATE: 3590 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxctl[0], 3591 RTW_RXQLEN); 3592 /*FALLTHROUGH*/ 3593 case FINISH_TXMAPS_CREATE: 3594 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3595 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 3596 sc->sc_txctl_blk[pri].stc_desc, 3597 sc->sc_txctl_blk[pri].stc_ndesc); 3598 } 3599 /*FALLTHROUGH*/ 3600 case FINISH_TXDESCBLK_SETUP: 3601 case FINISH_TXCTLBLK_SETUP: 3602 rtw_txctl_blk_cleanup_all(sc); 3603 /*FALLTHROUGH*/ 3604 case FINISH_DESCMAP_LOAD: 3605 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 3606 /*FALLTHROUGH*/ 3607 case FINISH_DESCMAP_CREATE: 3608 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 3609 /*FALLTHROUGH*/ 3610 case FINISH_DESC_MAP: 3611 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 3612 sizeof(struct rtw_descs)); 3613 /*FALLTHROUGH*/ 3614 case FINISH_DESC_ALLOC: 3615 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 3616 sc->sc_desc_nsegs); 3617 /*FALLTHROUGH*/ 3618 case DETACHED: 3619 NEXT_ATTACH_STATE(sc, DETACHED); 3620 break; 3621 } 3622 return 0; 3623 } 3624 3625 int 3626 rtw_activate(struct device *self, enum devact act) 3627 { 3628 struct rtw_softc *sc = (struct rtw_softc *)self; 3629 int rc = 0, s; 3630 3631 s = splnet(); 3632 switch (act) { 3633 case DVACT_ACTIVATE: 3634 rc = EOPNOTSUPP; 3635 break; 3636 3637 case DVACT_DEACTIVATE: 3638 if_deactivate(&sc->sc_ic.ic_if); 3639 break; 3640 } 3641 splx(s); 3642 return rc; 3643 } 3644
Indexes created Fri Sep 26 08:10:20 GMT 2025