rtw.c revision 1.28
1 /* $NetBSD: rtw.c,v 1.28 2004/12/27 10:17:38 mycroft Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.28 2004/12/27 10:17:38 mycroft Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #if 0 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #endif 54 #include <sys/time.h> 55 #include <sys/types.h> 56 57 #include <machine/endian.h> 58 #include <machine/bus.h> 59 #include <machine/intr.h> /* splnet */ 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_compat.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <dev/ic/rtwreg.h> 76 #include <dev/ic/rtwvar.h> 77 #include <dev/ic/rtwphyio.h> 78 #include <dev/ic/rtwphy.h> 79 80 #include <dev/ic/smc93cx6var.h> 81 82 #define KASSERT2(__cond, __msg) \ 83 do { \ 84 if (!(__cond)) \ 85 panic __msg ; \ 86 } while (0) 87 88 int rtw_rfprog_fallback = 0; 89 int rtw_host_rfio = 0; 90 91 #ifdef RTW_DEBUG 92 int rtw_debug = 0; 93 #endif /* RTW_DEBUG */ 94 95 #define NEXT_ATTACH_STATE(sc, state) do { \ 96 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 97 ("%s: attach state %s\n", __func__, #state)); \ 98 sc->sc_attach_state = state; \ 99 } while (0) 100 101 int rtw_dwelltime = 200; /* milliseconds */ 102 103 static void rtw_start(struct ifnet *); 104 105 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 106 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 107 #ifdef RTW_DEBUG 108 static void rtw_print_txdesc(struct rtw_softc *, const char *, 109 struct rtw_txctl *, struct rtw_txdesc_blk *, int); 110 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 111 #endif /* RTW_DEBUG */ 112 113 /* 114 * Setup sysctl(3) MIB, hw.rtw.* 115 * 116 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 117 */ 118 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 119 { 120 int rc; 121 struct sysctlnode *cnode, *rnode; 122 123 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 124 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 125 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 126 goto err; 127 128 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 129 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 130 "Realtek RTL818x 802.11 controls", 131 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 132 goto err; 133 134 #ifdef RTW_DEBUG 135 /* control debugging printfs */ 136 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 137 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 138 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 139 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 140 CTL_CREATE, CTL_EOL)) != 0) 141 goto err; 142 #endif /* RTW_DEBUG */ 143 /* set fallback RF programming method */ 144 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 145 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 146 "rfprog_fallback", 147 SYSCTL_DESCR("Set fallback RF programming method"), 148 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 149 CTL_CREATE, CTL_EOL)) != 0) 150 goto err; 151 152 /* force host to control RF I/O bus */ 153 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 154 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 155 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 156 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 157 CTL_CREATE, CTL_EOL)) != 0) 158 goto err; 159 160 return; 161 err: 162 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 163 } 164 165 static int 166 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 167 { 168 int error, t; 169 struct sysctlnode node; 170 171 node = *rnode; 172 t = *(int*)rnode->sysctl_data; 173 node.sysctl_data = &t; 174 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 175 if (error || newp == NULL) 176 return (error); 177 178 if (t < lower || t > upper) 179 return (EINVAL); 180 181 *(int*)rnode->sysctl_data = t; 182 183 return (0); 184 } 185 186 static int 187 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 188 { 189 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 190 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 191 } 192 193 static int 194 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 195 { 196 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1); 197 } 198 199 #ifdef RTW_DEBUG 200 static int 201 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 202 { 203 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, RTW_DEBUG_MAX); 204 } 205 206 static void 207 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 208 { 209 #define PRINTREG32(sc, reg) \ 210 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 211 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 212 dvname, reg, RTW_READ(regs, reg))) 213 214 #define PRINTREG16(sc, reg) \ 215 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 216 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 217 dvname, reg, RTW_READ16(regs, reg))) 218 219 #define PRINTREG8(sc, reg) \ 220 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 221 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 222 dvname, reg, RTW_READ8(regs, reg))) 223 224 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 225 226 PRINTREG32(regs, RTW_IDR0); 227 PRINTREG32(regs, RTW_IDR1); 228 PRINTREG32(regs, RTW_MAR0); 229 PRINTREG32(regs, RTW_MAR1); 230 PRINTREG32(regs, RTW_TSFTRL); 231 PRINTREG32(regs, RTW_TSFTRH); 232 PRINTREG32(regs, RTW_TLPDA); 233 PRINTREG32(regs, RTW_TNPDA); 234 PRINTREG32(regs, RTW_THPDA); 235 PRINTREG32(regs, RTW_TCR); 236 PRINTREG32(regs, RTW_RCR); 237 PRINTREG32(regs, RTW_TINT); 238 PRINTREG32(regs, RTW_TBDA); 239 PRINTREG32(regs, RTW_ANAPARM); 240 PRINTREG32(regs, RTW_BB); 241 PRINTREG32(regs, RTW_PHYCFG); 242 PRINTREG32(regs, RTW_WAKEUP0L); 243 PRINTREG32(regs, RTW_WAKEUP0H); 244 PRINTREG32(regs, RTW_WAKEUP1L); 245 PRINTREG32(regs, RTW_WAKEUP1H); 246 PRINTREG32(regs, RTW_WAKEUP2LL); 247 PRINTREG32(regs, RTW_WAKEUP2LH); 248 PRINTREG32(regs, RTW_WAKEUP2HL); 249 PRINTREG32(regs, RTW_WAKEUP2HH); 250 PRINTREG32(regs, RTW_WAKEUP3LL); 251 PRINTREG32(regs, RTW_WAKEUP3LH); 252 PRINTREG32(regs, RTW_WAKEUP3HL); 253 PRINTREG32(regs, RTW_WAKEUP3HH); 254 PRINTREG32(regs, RTW_WAKEUP4LL); 255 PRINTREG32(regs, RTW_WAKEUP4LH); 256 PRINTREG32(regs, RTW_WAKEUP4HL); 257 PRINTREG32(regs, RTW_WAKEUP4HH); 258 PRINTREG32(regs, RTW_DK0); 259 PRINTREG32(regs, RTW_DK1); 260 PRINTREG32(regs, RTW_DK2); 261 PRINTREG32(regs, RTW_DK3); 262 PRINTREG32(regs, RTW_RETRYCTR); 263 PRINTREG32(regs, RTW_RDSAR); 264 PRINTREG32(regs, RTW_FER); 265 PRINTREG32(regs, RTW_FEMR); 266 PRINTREG32(regs, RTW_FPSR); 267 PRINTREG32(regs, RTW_FFER); 268 269 /* 16-bit registers */ 270 PRINTREG16(regs, RTW_BRSR); 271 PRINTREG16(regs, RTW_IMR); 272 PRINTREG16(regs, RTW_ISR); 273 PRINTREG16(regs, RTW_BCNITV); 274 PRINTREG16(regs, RTW_ATIMWND); 275 PRINTREG16(regs, RTW_BINTRITV); 276 PRINTREG16(regs, RTW_ATIMTRITV); 277 PRINTREG16(regs, RTW_CRC16ERR); 278 PRINTREG16(regs, RTW_CRC0); 279 PRINTREG16(regs, RTW_CRC1); 280 PRINTREG16(regs, RTW_CRC2); 281 PRINTREG16(regs, RTW_CRC3); 282 PRINTREG16(regs, RTW_CRC4); 283 PRINTREG16(regs, RTW_CWR); 284 285 /* 8-bit registers */ 286 PRINTREG8(regs, RTW_CR); 287 PRINTREG8(regs, RTW_9346CR); 288 PRINTREG8(regs, RTW_CONFIG0); 289 PRINTREG8(regs, RTW_CONFIG1); 290 PRINTREG8(regs, RTW_CONFIG2); 291 PRINTREG8(regs, RTW_MSR); 292 PRINTREG8(regs, RTW_CONFIG3); 293 PRINTREG8(regs, RTW_CONFIG4); 294 PRINTREG8(regs, RTW_TESTR); 295 PRINTREG8(regs, RTW_PSR); 296 PRINTREG8(regs, RTW_SCR); 297 PRINTREG8(regs, RTW_PHYDELAY); 298 PRINTREG8(regs, RTW_CRCOUNT); 299 PRINTREG8(regs, RTW_PHYADDR); 300 PRINTREG8(regs, RTW_PHYDATAW); 301 PRINTREG8(regs, RTW_PHYDATAR); 302 PRINTREG8(regs, RTW_CONFIG5); 303 PRINTREG8(regs, RTW_TPPOLL); 304 305 PRINTREG16(regs, RTW_BSSID16); 306 PRINTREG32(regs, RTW_BSSID32); 307 #undef PRINTREG32 308 #undef PRINTREG16 309 #undef PRINTREG8 310 } 311 #endif /* RTW_DEBUG */ 312 313 void 314 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 315 { 316 struct rtw_regs *regs = &sc->sc_regs; 317 318 u_int32_t tcr; 319 tcr = RTW_READ(regs, RTW_TCR); 320 tcr &= ~RTW_TCR_LBK_MASK; 321 if (enable) 322 tcr |= RTW_TCR_LBK_CONT; 323 else 324 tcr |= RTW_TCR_LBK_NORMAL; 325 RTW_WRITE(regs, RTW_TCR, tcr); 326 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 327 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 328 rtw_txdac_enable(sc, !enable); 329 rtw_set_access(sc, RTW_ACCESS_ANAPARM); /* XXX Voodoo from Linux. */ 330 rtw_set_access(sc, RTW_ACCESS_NONE); 331 } 332 333 #ifdef RTW_DEBUG 334 static const char * 335 rtw_access_string(enum rtw_access access) 336 { 337 switch (access) { 338 case RTW_ACCESS_NONE: 339 return "none"; 340 case RTW_ACCESS_CONFIG: 341 return "config"; 342 case RTW_ACCESS_ANAPARM: 343 return "anaparm"; 344 default: 345 return "unknown"; 346 } 347 } 348 #endif /* RTW_DEBUG */ 349 350 static void 351 rtw_set_access1(struct rtw_regs *regs, 352 enum rtw_access oaccess, enum rtw_access naccess) 353 { 354 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 355 KASSERT(oaccess >= RTW_ACCESS_NONE && oaccess <= RTW_ACCESS_ANAPARM); 356 357 if (naccess == oaccess) 358 return; 359 360 switch (naccess) { 361 case RTW_ACCESS_NONE: 362 switch (oaccess) { 363 case RTW_ACCESS_ANAPARM: 364 rtw_anaparm_enable(regs, 0); 365 /*FALLTHROUGH*/ 366 case RTW_ACCESS_CONFIG: 367 rtw_config0123_enable(regs, 0); 368 /*FALLTHROUGH*/ 369 case RTW_ACCESS_NONE: 370 break; 371 } 372 break; 373 case RTW_ACCESS_CONFIG: 374 switch (oaccess) { 375 case RTW_ACCESS_NONE: 376 rtw_config0123_enable(regs, 1); 377 /*FALLTHROUGH*/ 378 case RTW_ACCESS_CONFIG: 379 break; 380 case RTW_ACCESS_ANAPARM: 381 rtw_anaparm_enable(regs, 0); 382 break; 383 } 384 break; 385 case RTW_ACCESS_ANAPARM: 386 switch (oaccess) { 387 case RTW_ACCESS_NONE: 388 rtw_config0123_enable(regs, 1); 389 /*FALLTHROUGH*/ 390 case RTW_ACCESS_CONFIG: 391 rtw_anaparm_enable(regs, 1); 392 /*FALLTHROUGH*/ 393 case RTW_ACCESS_ANAPARM: 394 break; 395 } 396 break; 397 } 398 } 399 400 void 401 rtw_set_access(struct rtw_softc *sc, enum rtw_access access) 402 { 403 rtw_set_access1(&sc->sc_regs, sc->sc_access, access); 404 RTW_DPRINTF(RTW_DEBUG_ACCESS, 405 ("%s: access %s -> %s\n", sc->sc_dev.dv_xname, 406 rtw_access_string(sc->sc_access), 407 rtw_access_string(access))); 408 sc->sc_access = access; 409 } 410 411 /* 412 * Enable registers, switch register banks. 413 */ 414 void 415 rtw_config0123_enable(struct rtw_regs *regs, int enable) 416 { 417 u_int8_t ecr; 418 ecr = RTW_READ8(regs, RTW_9346CR); 419 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 420 if (enable) 421 ecr |= RTW_9346CR_EEM_CONFIG; 422 else { 423 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 424 ecr |= RTW_9346CR_EEM_NORMAL; 425 } 426 RTW_WRITE8(regs, RTW_9346CR, ecr); 427 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 428 } 429 430 /* requires rtw_config0123_enable(, 1) */ 431 void 432 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 433 { 434 u_int8_t cfg3; 435 436 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 437 cfg3 |= RTW_CONFIG3_CLKRUNEN; 438 if (enable) 439 cfg3 |= RTW_CONFIG3_PARMEN; 440 else 441 cfg3 &= ~RTW_CONFIG3_PARMEN; 442 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 443 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 444 } 445 446 /* requires rtw_anaparm_enable(, 1) */ 447 void 448 rtw_txdac_enable(struct rtw_softc *sc, int enable) 449 { 450 u_int32_t anaparm; 451 struct rtw_regs *regs = &sc->sc_regs; 452 453 anaparm = RTW_READ(regs, RTW_ANAPARM); 454 if (enable) 455 anaparm &= ~RTW_ANAPARM_TXDACOFF; 456 else 457 anaparm |= RTW_ANAPARM_TXDACOFF; 458 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 459 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 460 } 461 462 static __inline int 463 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 464 { 465 u_int8_t cr; 466 int i; 467 468 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 469 470 RTW_WBR(regs, RTW_CR, RTW_CR); 471 472 for (i = 0; i < 1000; i++) { 473 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 474 RTW_DPRINTF(RTW_DEBUG_RESET, 475 ("%s: reset in %dus\n", dvname, i)); 476 return 0; 477 } 478 RTW_RBR(regs, RTW_CR, RTW_CR); 479 DELAY(10); /* 10us */ 480 } 481 482 printf("%s: reset failed\n", dvname); 483 return ETIMEDOUT; 484 } 485 486 static __inline int 487 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 488 { 489 uint32_t tcr; 490 491 /* from Linux driver */ 492 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 493 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 494 495 RTW_WRITE(regs, RTW_TCR, tcr); 496 497 RTW_WBW(regs, RTW_CR, RTW_TCR); 498 499 return rtw_chip_reset1(regs, dvname); 500 } 501 502 static __inline int 503 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 504 { 505 int i; 506 u_int8_t ecr; 507 508 ecr = RTW_READ8(regs, RTW_9346CR); 509 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 510 RTW_WRITE8(regs, RTW_9346CR, ecr); 511 512 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 513 514 /* wait 2.5ms for completion */ 515 for (i = 0; i < 25; i++) { 516 ecr = RTW_READ8(regs, RTW_9346CR); 517 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 518 RTW_DPRINTF(RTW_DEBUG_RESET, 519 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 520 return 0; 521 } 522 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 523 DELAY(100); 524 } 525 printf("%s: recall EEPROM failed\n", dvname); 526 return ETIMEDOUT; 527 } 528 529 static __inline int 530 rtw_reset(struct rtw_softc *sc) 531 { 532 int rc; 533 uint8_t config1; 534 535 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 536 return rc; 537 538 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 539 ; 540 541 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 542 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 543 /* TBD turn off maximum power saving? */ 544 545 return 0; 546 } 547 548 static __inline int 549 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txctl *descs, 550 u_int ndescs) 551 { 552 int i, rc = 0; 553 for (i = 0; i < ndescs; i++) { 554 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 555 0, 0, &descs[i].stx_dmamap); 556 if (rc != 0) 557 break; 558 } 559 return rc; 560 } 561 562 static __inline int 563 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 564 u_int ndescs) 565 { 566 int i, rc = 0; 567 for (i = 0; i < ndescs; i++) { 568 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 569 &descs[i].srx_dmamap); 570 if (rc != 0) 571 break; 572 } 573 return rc; 574 } 575 576 static __inline void 577 rtw_rxctls_setup(struct rtw_rxctl *descs) 578 { 579 int i; 580 for (i = 0; i < RTW_RXQLEN; i++) 581 descs[i].srx_mbuf = NULL; 582 } 583 584 static __inline void 585 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 586 u_int ndescs) 587 { 588 int i; 589 for (i = 0; i < ndescs; i++) { 590 if (descs[i].srx_dmamap != NULL) 591 bus_dmamap_destroy(dmat, descs[i].srx_dmamap); 592 } 593 } 594 595 static __inline void 596 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txctl *descs, 597 u_int ndescs) 598 { 599 int i; 600 for (i = 0; i < ndescs; i++) { 601 if (descs[i].stx_dmamap != NULL) 602 bus_dmamap_destroy(dmat, descs[i].stx_dmamap); 603 } 604 } 605 606 static __inline void 607 rtw_srom_free(struct rtw_srom *sr) 608 { 609 sr->sr_size = 0; 610 if (sr->sr_content == NULL) 611 return; 612 free(sr->sr_content, M_DEVBUF); 613 sr->sr_content = NULL; 614 } 615 616 static void 617 rtw_srom_defaults(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 618 enum rtw_rfchipid *rfchipid, u_int32_t *rcr) 619 { 620 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 621 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 622 *rcr |= RTW_RCR_ENCS1; 623 *rfchipid = RTW_RFCHIPID_PHILIPS; 624 } 625 626 static int 627 rtw_srom_parse(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 628 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, enum rtw_locale *locale, 629 const char *dvname) 630 { 631 int i; 632 const char *rfname, *paname; 633 char scratch[sizeof("unknown 0xXX")]; 634 u_int16_t version; 635 u_int8_t mac[IEEE80211_ADDR_LEN]; 636 637 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 638 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 639 640 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 641 printf("%s: SROM version %d.%d", dvname, version >> 8, version & 0xff); 642 643 if (version <= 0x0101) { 644 printf(" is not understood, limping along with defaults\n"); 645 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 646 return 0; 647 } 648 printf("\n"); 649 650 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 651 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 652 653 RTW_DPRINTF(RTW_DEBUG_ATTACH, 654 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 655 656 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 657 658 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 659 *flags |= RTW_F_ANTDIV; 660 661 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 662 * to be reversed. 663 */ 664 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 665 *flags |= RTW_F_DIGPHY; 666 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 667 *flags |= RTW_F_DFLANTB; 668 669 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 670 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 671 672 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 673 switch (*rfchipid) { 674 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 675 rfname = "GCT GRF5101"; 676 paname = "Winspring WS9901"; 677 break; 678 case RTW_RFCHIPID_MAXIM: 679 rfname = "Maxim MAX2820"; /* guess */ 680 paname = "Maxim MAX2422"; /* guess */ 681 break; 682 case RTW_RFCHIPID_INTERSIL: 683 rfname = "Intersil HFA3873"; /* guess */ 684 paname = "Intersil <unknown>"; 685 break; 686 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 687 rfname = "Philips SA2400A"; 688 paname = "Philips SA2411"; 689 break; 690 case RTW_RFCHIPID_RFMD: 691 /* this is the same front-end as an atw(4)! */ 692 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 693 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 694 "SYN: Silicon Labs Si4126"; /* inferred from 695 * reference driver 696 */ 697 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 698 break; 699 case RTW_RFCHIPID_RESERVED: 700 rfname = paname = "reserved"; 701 break; 702 default: 703 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 704 rfname = paname = scratch; 705 } 706 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 707 708 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 709 case RTW_CONFIG0_GL_USA: 710 *locale = RTW_LOCALE_USA; 711 break; 712 case RTW_CONFIG0_GL_EUROPE: 713 *locale = RTW_LOCALE_EUROPE; 714 break; 715 case RTW_CONFIG0_GL_JAPAN: 716 *locale = RTW_LOCALE_JAPAN; 717 break; 718 default: 719 *locale = RTW_LOCALE_UNKNOWN; 720 break; 721 } 722 return 0; 723 } 724 725 /* Returns -1 on failure. */ 726 static int 727 rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr, 728 const char *dvname) 729 { 730 int rc; 731 struct seeprom_descriptor sd; 732 u_int8_t ecr; 733 734 (void)memset(&sd, 0, sizeof(sd)); 735 736 ecr = RTW_READ8(regs, RTW_9346CR); 737 738 if ((flags & RTW_F_9356SROM) != 0) { 739 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 740 sr->sr_size = 256; 741 sd.sd_chip = C56_66; 742 } else { 743 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 744 sr->sr_size = 128; 745 sd.sd_chip = C46; 746 } 747 748 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 749 RTW_9346CR_EEM_MASK); 750 ecr |= RTW_9346CR_EEM_PROGRAM; 751 752 RTW_WRITE8(regs, RTW_9346CR, ecr); 753 754 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 755 756 if (sr->sr_content == NULL) { 757 printf("%s: unable to allocate SROM buffer\n", dvname); 758 return ENOMEM; 759 } 760 761 (void)memset(sr->sr_content, 0, sr->sr_size); 762 763 /* RTL8180 has a single 8-bit register for controlling the 764 * 93cx6 SROM. There is no "ready" bit. The RTL8180 765 * input/output sense is the reverse of read_seeprom's. 766 */ 767 sd.sd_tag = regs->r_bt; 768 sd.sd_bsh = regs->r_bh; 769 sd.sd_regsize = 1; 770 sd.sd_control_offset = RTW_9346CR; 771 sd.sd_status_offset = RTW_9346CR; 772 sd.sd_dataout_offset = RTW_9346CR; 773 sd.sd_CK = RTW_9346CR_EESK; 774 sd.sd_CS = RTW_9346CR_EECS; 775 sd.sd_DI = RTW_9346CR_EEDO; 776 sd.sd_DO = RTW_9346CR_EEDI; 777 /* make read_seeprom enter EEPROM read/write mode */ 778 sd.sd_MS = ecr; 779 sd.sd_RDY = 0; 780 #if 0 781 sd.sd_clkdelay = 50; 782 #endif 783 784 /* TBD bus barriers */ 785 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 786 printf("%s: could not read SROM\n", dvname); 787 free(sr->sr_content, M_DEVBUF); 788 sr->sr_content = NULL; 789 return -1; /* XXX */ 790 } 791 792 /* end EEPROM read/write mode */ 793 RTW_WRITE8(regs, RTW_9346CR, 794 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 795 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 796 797 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 798 return rc; 799 800 #ifdef RTW_DEBUG 801 { 802 int i; 803 RTW_DPRINTF(RTW_DEBUG_ATTACH, 804 ("\n%s: serial ROM:\n\t", dvname)); 805 for (i = 0; i < sr->sr_size/2; i++) { 806 if (((i % 8) == 0) && (i != 0)) 807 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 808 RTW_DPRINTF(RTW_DEBUG_ATTACH, 809 (" %04x", sr->sr_content[i])); 810 } 811 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 812 } 813 #endif /* RTW_DEBUG */ 814 return 0; 815 } 816 817 static void 818 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 819 const char *dvname) 820 { 821 u_int8_t cfg4; 822 const char *method; 823 824 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 825 826 switch (rfchipid) { 827 default: 828 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 829 method = "fallback"; 830 break; 831 case RTW_RFCHIPID_INTERSIL: 832 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 833 method = "Intersil"; 834 break; 835 case RTW_RFCHIPID_PHILIPS: 836 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 837 method = "Philips"; 838 break; 839 case RTW_RFCHIPID_RFMD: 840 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 841 method = "RFMD"; 842 break; 843 } 844 845 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 846 847 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 848 849 RTW_DPRINTF(RTW_DEBUG_INIT, 850 ("%s: %s RF programming method, %#02x\n", dvname, method, 851 RTW_READ8(regs, RTW_CONFIG4))); 852 } 853 854 #if 0 855 static __inline int 856 rtw_identify_rf(struct rtw_regs *regs, enum rtw_rftype *rftype, 857 const char *dvname) 858 { 859 u_int8_t cfg4; 860 const char *name; 861 862 cfg4 = RTW_READ8(regs, RTW_CONFIG4); 863 864 switch (cfg4 & RTW_CONFIG4_RFTYPE_MASK) { 865 case RTW_CONFIG4_RFTYPE_PHILIPS: 866 *rftype = RTW_RFTYPE_PHILIPS; 867 name = "Philips"; 868 break; 869 case RTW_CONFIG4_RFTYPE_INTERSIL: 870 *rftype = RTW_RFTYPE_INTERSIL; 871 name = "Intersil"; 872 break; 873 case RTW_CONFIG4_RFTYPE_RFMD: 874 *rftype = RTW_RFTYPE_RFMD; 875 name = "RFMD"; 876 break; 877 default: 878 name = "<unknown>"; 879 return ENXIO; 880 } 881 882 printf("%s: RF prog type %s\n", dvname, name); 883 return 0; 884 } 885 #endif 886 887 static __inline void 888 rtw_init_channels(enum rtw_locale locale, 889 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 890 const char *dvname) 891 { 892 int i; 893 const char *name = NULL; 894 #define ADD_CHANNEL(_chans, _chan) do { \ 895 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 896 (*_chans)[_chan].ic_freq = \ 897 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 898 } while (0) 899 900 switch (locale) { 901 case RTW_LOCALE_USA: /* 1-11 */ 902 name = "USA"; 903 for (i = 1; i <= 11; i++) 904 ADD_CHANNEL(chans, i); 905 break; 906 case RTW_LOCALE_JAPAN: /* 1-14 */ 907 name = "Japan"; 908 ADD_CHANNEL(chans, 14); 909 for (i = 1; i <= 14; i++) 910 ADD_CHANNEL(chans, i); 911 break; 912 case RTW_LOCALE_EUROPE: /* 1-13 */ 913 name = "Europe"; 914 for (i = 1; i <= 13; i++) 915 ADD_CHANNEL(chans, i); 916 break; 917 default: /* 10-11 allowed by most countries */ 918 name = "<unknown>"; 919 for (i = 10; i <= 11; i++) 920 ADD_CHANNEL(chans, i); 921 break; 922 } 923 printf("%s: Geographic Location %s\n", dvname, name); 924 #undef ADD_CHANNEL 925 } 926 927 static __inline void 928 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 929 const char *dvname) 930 { 931 u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 932 933 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 934 case RTW_CONFIG0_GL_USA: 935 *locale = RTW_LOCALE_USA; 936 break; 937 case RTW_CONFIG0_GL_JAPAN: 938 *locale = RTW_LOCALE_JAPAN; 939 break; 940 case RTW_CONFIG0_GL_EUROPE: 941 *locale = RTW_LOCALE_EUROPE; 942 break; 943 default: 944 *locale = RTW_LOCALE_UNKNOWN; 945 break; 946 } 947 } 948 949 static __inline int 950 rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN], 951 const char *dvname) 952 { 953 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 954 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 955 }; 956 u_int32_t idr0 = RTW_READ(regs, RTW_IDR0), 957 idr1 = RTW_READ(regs, RTW_IDR1); 958 959 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 960 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 961 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 962 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 963 964 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 965 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 966 967 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 968 printf("%s: could not get mac address, attach failed\n", 969 dvname); 970 return ENXIO; 971 } 972 973 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 974 975 return 0; 976 } 977 978 static u_int8_t 979 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 980 struct ieee80211_channel *chan) 981 { 982 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 983 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 984 ("%s: channel %d out of range", __func__, 985 idx - RTW_SR_TXPOWER1 + 1)); 986 return RTW_SR_GET(sr, idx); 987 } 988 989 static void 990 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *htcs) 991 { 992 int pri; 993 u_int ndesc[RTW_NTXPRI] = 994 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 995 996 for (pri = 0; pri < RTW_NTXPRI; pri++) { 997 htcs[pri].htc_nfree = ndesc[pri]; 998 htcs[pri].htc_next = 0; 999 } 1000 } 1001 1002 static int 1003 rtw_txctl_blk_init(struct rtw_txctl_blk *stc) 1004 { 1005 int i; 1006 struct rtw_txctl *stx; 1007 1008 SIMPLEQ_INIT(&stc->stc_dirtyq); 1009 SIMPLEQ_INIT(&stc->stc_freeq); 1010 for (i = 0; i < stc->stc_ndesc; i++) { 1011 stx = &stc->stc_desc[i]; 1012 stx->stx_mbuf = NULL; 1013 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1014 } 1015 return 0; 1016 } 1017 1018 static void 1019 rtw_txctl_blk_init_all(struct rtw_txctl_blk *stcs) 1020 { 1021 int pri; 1022 for (pri = 0; pri < RTW_NTXPRI; pri++) 1023 rtw_txctl_blk_init(&stcs[pri]); 1024 } 1025 1026 static __inline void 1027 rtw_rxdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, u_int desc0, u_int 1028 nsync, int ops) 1029 { 1030 KASSERT(nsync <= RTW_RXQLEN); 1031 /* sync to end of ring */ 1032 if (desc0 + nsync > RTW_RXQLEN) { 1033 bus_dmamap_sync(dmat, dmap, 1034 offsetof(struct rtw_descs, hd_rx[desc0]), 1035 sizeof(struct rtw_rxdesc) * (RTW_RXQLEN - desc0), ops); 1036 nsync -= (RTW_RXQLEN - desc0); 1037 desc0 = 0; 1038 } 1039 1040 KASSERT(desc0 < RTW_RXQLEN); 1041 KASSERT(nsync <= RTW_RXQLEN); 1042 KASSERT(desc0 + nsync <= RTW_RXQLEN); 1043 1044 /* sync what remains */ 1045 bus_dmamap_sync(dmat, dmap, 1046 offsetof(struct rtw_descs, hd_rx[desc0]), 1047 sizeof(struct rtw_rxdesc) * nsync, ops); 1048 } 1049 1050 static void 1051 rtw_txdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1052 struct rtw_txdesc_blk *htc, u_int desc0, u_int nsync, int ops) 1053 { 1054 /* sync to end of ring */ 1055 if (desc0 + nsync > htc->htc_ndesc) { 1056 bus_dmamap_sync(dmat, dmap, 1057 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1058 sizeof(struct rtw_txdesc) * (htc->htc_ndesc - desc0), 1059 ops); 1060 nsync -= (htc->htc_ndesc - desc0); 1061 desc0 = 0; 1062 } 1063 1064 /* sync what remains */ 1065 bus_dmamap_sync(dmat, dmap, 1066 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1067 sizeof(struct rtw_txdesc) * nsync, ops); 1068 } 1069 1070 static void 1071 rtw_txdescs_sync_all(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1072 struct rtw_txdesc_blk *htcs) 1073 { 1074 int pri; 1075 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1076 rtw_txdescs_sync(dmat, dmap, 1077 &htcs[pri], 0, htcs[pri].htc_ndesc, 1078 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1079 } 1080 } 1081 1082 static void 1083 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxctl *desc) 1084 { 1085 int i; 1086 struct rtw_rxctl *srx; 1087 1088 for (i = 0; i < RTW_RXQLEN; i++) { 1089 srx = &desc[i]; 1090 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, 1091 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1092 bus_dmamap_unload(dmat, srx->srx_dmamap); 1093 m_freem(srx->srx_mbuf); 1094 srx->srx_mbuf = NULL; 1095 } 1096 } 1097 1098 static __inline int 1099 rtw_rxbuf_alloc(bus_dma_tag_t dmat, struct rtw_rxctl *srx) 1100 { 1101 int rc; 1102 struct mbuf *m; 1103 1104 MGETHDR(m, M_DONTWAIT, MT_DATA); 1105 if (m == NULL) 1106 return ENOBUFS; 1107 1108 MCLGET(m, M_DONTWAIT); 1109 if (m == NULL) 1110 return ENOBUFS; 1111 1112 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1113 1114 if (srx->srx_mbuf != NULL) 1115 bus_dmamap_unload(dmat, srx->srx_dmamap); 1116 1117 srx->srx_mbuf = NULL; 1118 1119 rc = bus_dmamap_load_mbuf(dmat, srx->srx_dmamap, m, BUS_DMA_NOWAIT); 1120 if (rc != 0) { 1121 m_freem(m); 1122 return -1; 1123 } 1124 1125 srx->srx_mbuf = m; 1126 1127 return 0; 1128 } 1129 1130 static int 1131 rtw_rxctl_init_all(bus_dma_tag_t dmat, struct rtw_rxctl *desc, 1132 u_int *next, const char *dvname) 1133 { 1134 int i, rc; 1135 struct rtw_rxctl *srx; 1136 1137 for (i = 0; i < RTW_RXQLEN; i++) { 1138 srx = &desc[i]; 1139 if ((rc = rtw_rxbuf_alloc(dmat, srx)) == 0) 1140 continue; 1141 printf("%s: failed rtw_rxbuf_alloc after %d buffers, rc = %d\n", 1142 dvname, i, rc); 1143 if (i == 0) { 1144 rtw_rxbufs_release(dmat, desc); 1145 return rc; 1146 } 1147 } 1148 *next = 0; 1149 return 0; 1150 } 1151 1152 static __inline void 1153 rtw_rxdesc_init(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1154 struct rtw_rxdesc *hrx, struct rtw_rxctl *srx, int idx, int kick) 1155 { 1156 int is_last = (idx == RTW_RXQLEN - 1); 1157 uint32_t ctl, octl, obuf; 1158 1159 obuf = hrx->hrx_buf; 1160 hrx->hrx_buf = htole32(srx->srx_dmamap->dm_segs[0].ds_addr); 1161 1162 ctl = LSHIFT(srx->srx_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1163 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1164 1165 if (is_last) 1166 ctl |= RTW_RXCTL_EOR; 1167 1168 octl = hrx->hrx_ctl; 1169 hrx->hrx_ctl = htole32(ctl); 1170 1171 RTW_DPRINTF( 1172 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1173 : RTW_DEBUG_RECV_DESC, 1174 ("%s: hrx %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, hrx, 1175 le32toh(obuf), le32toh(hrx->hrx_buf), le32toh(octl), 1176 le32toh(hrx->hrx_ctl))); 1177 1178 /* sync the mbuf */ 1179 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, srx->srx_dmamap->dm_mapsize, 1180 BUS_DMASYNC_PREREAD); 1181 1182 /* sync the descriptor */ 1183 bus_dmamap_sync(dmat, dmam, RTW_DESC_OFFSET(hd_rx, idx), 1184 sizeof(struct rtw_rxdesc), 1185 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1186 } 1187 1188 static void 1189 rtw_rxdesc_init_all(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1190 struct rtw_rxdesc *desc, struct rtw_rxctl *ctl, int kick) 1191 { 1192 int i; 1193 struct rtw_rxdesc *hrx; 1194 struct rtw_rxctl *srx; 1195 1196 for (i = 0; i < RTW_RXQLEN; i++) { 1197 hrx = &desc[i]; 1198 srx = &ctl[i]; 1199 rtw_rxdesc_init(dmat, dmam, hrx, srx, i, kick); 1200 } 1201 } 1202 1203 static void 1204 rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable) 1205 { 1206 u_int8_t cr; 1207 1208 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1209 enable ? "enable" : "disable", flags)); 1210 1211 cr = RTW_READ8(regs, RTW_CR); 1212 1213 /* XXX reference source does not enable MULRW */ 1214 #if 0 1215 /* enable PCI Read/Write Multiple */ 1216 cr |= RTW_CR_MULRW; 1217 #endif 1218 1219 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1220 if (enable) 1221 cr |= flags; 1222 else 1223 cr &= ~flags; 1224 RTW_WRITE8(regs, RTW_CR, cr); 1225 RTW_SYNC(regs, RTW_CR, RTW_CR); 1226 } 1227 1228 static void 1229 rtw_intr_rx(struct rtw_softc *sc, u_int16_t isr) 1230 { 1231 u_int next, nproc = 0; 1232 int len, rate, rssi; 1233 u_int32_t hrssi, hstat, htsfth, htsftl; 1234 struct rtw_rxdesc *hrx; 1235 struct rtw_rxctl *srx; 1236 struct mbuf *m; 1237 1238 struct ieee80211_node *ni; 1239 struct ieee80211_frame *wh; 1240 1241 KASSERT(sc->sc_rxnext < RTW_RXQLEN); 1242 1243 for (next = sc->sc_rxnext; ; next = (next + 1) % RTW_RXQLEN) { 1244 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1245 next, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1246 hrx = &sc->sc_rxdesc[next]; 1247 srx = &sc->sc_rxctl[next]; 1248 1249 hstat = le32toh(hrx->hrx_stat); 1250 hrssi = le32toh(hrx->hrx_rssi); 1251 htsfth = le32toh(hrx->hrx_tsfth); 1252 htsftl = le32toh(hrx->hrx_tsftl); 1253 1254 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1255 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1256 __func__, next, hstat, hrssi, htsfth, htsftl)); 1257 1258 KASSERT((hstat & (RTW_RXSTAT_FS|RTW_RXSTAT_LS)) == 1259 (RTW_RXSTAT_FS|RTW_RXSTAT_LS)); 1260 1261 ++nproc; 1262 1263 /* still belongs to NIC */ 1264 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1265 if (nproc > 1) 1266 break; 1267 1268 /* sometimes the NIC skips to the 0th descriptor */ 1269 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1270 0, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1271 hrx = &sc->sc_rxdesc[0]; 1272 if ((hrx->hrx_stat & htole32(RTW_RXSTAT_OWN)) != 0) 1273 break; 1274 RTW_DPRINTF(RTW_DEBUG_BUGS, 1275 ("%s: NIC skipped to rxdesc[0]\n", 1276 sc->sc_dev.dv_xname)); 1277 next = 0; 1278 continue; 1279 } 1280 1281 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1282 printf("%s: DMA error/FIFO overflow %08x, " 1283 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1284 hstat & RTW_RXSTAT_IOERROR, next); 1285 goto next; 1286 } 1287 1288 len = MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1289 if (len < IEEE80211_MIN_LEN) { 1290 sc->sc_ic.ic_stats.is_rx_tooshort++; 1291 goto next; 1292 } 1293 1294 switch (hstat & RTW_RXSTAT_RATE_MASK) { 1295 case RTW_RXSTAT_RATE_1MBPS: 1296 rate = 2; 1297 break; 1298 case RTW_RXSTAT_RATE_2MBPS: 1299 rate = 4; 1300 break; 1301 case RTW_RXSTAT_RATE_5MBPS: 1302 rate = 11; 1303 break; 1304 case RTW_RXSTAT_RATE_11MBPS: 1305 rate = 22; 1306 break; 1307 default: 1308 printf("%s: unknown rate #%d\n", sc->sc_dev.dv_xname, 1309 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_RATE_MASK)); 1310 goto next; 1311 } 1312 1313 #ifdef RTW_DEBUG 1314 #define PRINTSTAT(flag) do { \ 1315 if ((hstat & flag) != 0) { \ 1316 printf("%s" #flag, delim); \ 1317 delim = ","; \ 1318 } \ 1319 } while (0) 1320 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1321 const char *delim = "<"; 1322 printf("%s: ", sc->sc_dev.dv_xname); 1323 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1324 printf("status %08x", hstat); 1325 PRINTSTAT(RTW_RXSTAT_SPLCP); 1326 PRINTSTAT(RTW_RXSTAT_MAR); 1327 PRINTSTAT(RTW_RXSTAT_PAR); 1328 PRINTSTAT(RTW_RXSTAT_BAR); 1329 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1330 PRINTSTAT(RTW_RXSTAT_CRC32); 1331 PRINTSTAT(RTW_RXSTAT_ICV); 1332 printf(">, "); 1333 } 1334 printf("rate %d.%d Mb/s, time %08x%08x\n", 1335 (rate * 5) / 10, (rate * 5) % 10, htsfth, htsftl); 1336 } 1337 #endif /* RTW_DEBUG */ 1338 1339 if ((hstat & RTW_RXSTAT_RES) != 0 && 1340 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1341 goto next; 1342 1343 /* if bad flags, skip descriptor */ 1344 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1345 printf("%s: too many rx segments\n", 1346 sc->sc_dev.dv_xname); 1347 goto next; 1348 } 1349 1350 bus_dmamap_sync(sc->sc_dmat, srx->srx_dmamap, 0, 1351 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1352 1353 m = srx->srx_mbuf; 1354 1355 /* if temporarily out of memory, re-use mbuf */ 1356 switch (rtw_rxbuf_alloc(sc->sc_dmat, srx)) { 1357 case 0: 1358 break; 1359 case ENOBUFS: 1360 printf("%s: rtw_rxbuf_alloc(, %d) failed, " 1361 "dropping this packet\n", sc->sc_dev.dv_xname, 1362 next); 1363 goto next; 1364 default: 1365 /* XXX shorten rx ring, instead? */ 1366 panic("%s: could not load DMA map\n", 1367 sc->sc_dev.dv_xname); 1368 } 1369 1370 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1371 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1372 else { 1373 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1374 /* TBD find out each front-end's LNA gain in the 1375 * front-end's units 1376 */ 1377 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1378 rssi |= 0x80; 1379 } 1380 1381 m->m_pkthdr.rcvif = &sc->sc_if; 1382 m->m_pkthdr.len = m->m_len = len; 1383 m->m_flags |= M_HASFCS; 1384 1385 wh = mtod(m, struct ieee80211_frame *); 1386 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1387 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1388 1389 sc->sc_tsfth = htsfth; 1390 1391 #ifdef RTW_DEBUG 1392 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 1393 (IFF_DEBUG|IFF_LINK2)) { 1394 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1395 rate, rssi); 1396 } 1397 #endif /* RTW_DEBUG */ 1398 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1399 ieee80211_release_node(&sc->sc_ic, ni); 1400 next: 1401 rtw_rxdesc_init(sc->sc_dmat, sc->sc_desc_dmamap, 1402 hrx, srx, next, 0); 1403 } 1404 KASSERT(sc->sc_rxnext < RTW_RXQLEN); 1405 1406 sc->sc_rxnext = next; 1407 1408 return; 1409 } 1410 1411 static void 1412 rtw_txbuf_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1413 struct rtw_txctl *stx) 1414 { 1415 struct mbuf *m; 1416 struct ieee80211_node *ni; 1417 1418 m = stx->stx_mbuf; 1419 ni = stx->stx_ni; 1420 KASSERT(m != NULL); 1421 KASSERT(ni != NULL); 1422 stx->stx_mbuf = NULL; 1423 stx->stx_ni = NULL; 1424 1425 bus_dmamap_sync(dmat, stx->stx_dmamap, 0, stx->stx_dmamap->dm_mapsize, 1426 BUS_DMASYNC_POSTWRITE); 1427 bus_dmamap_unload(dmat, stx->stx_dmamap); 1428 m_freem(m); 1429 ieee80211_release_node(ic, ni); 1430 } 1431 1432 static void 1433 rtw_txbufs_release(bus_dma_tag_t dmat, bus_dmamap_t desc_dmamap, 1434 struct ieee80211com *ic, struct rtw_txctl_blk *stc, 1435 struct rtw_txdesc_blk *htc) 1436 { 1437 int desc, i; 1438 struct rtw_txctl *stx; 1439 1440 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1441 rtw_txdescs_sync(dmat, desc_dmamap, htc, stx->stx_first, 1442 stx->stx_dmamap->dm_nsegs, 1443 BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 1444 for (i = 0, desc = stx->stx_first; 1445 i < stx->stx_dmamap->dm_nsegs; 1446 i++, desc = RTW_NEXT_IDX(htc, desc)) { 1447 htc->htc_desc[desc].htx_ctl0 &= 1448 ~htole32(RTW_TXCTL0_OWN); 1449 } 1450 rtw_txdescs_sync(dmat, desc_dmamap, htc, stx->stx_first, 1451 stx->stx_dmamap->dm_nsegs, 1452 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1453 htc->htc_nfree += stx->stx_dmamap->dm_nsegs; 1454 rtw_txbuf_release(dmat, ic, stx); 1455 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1456 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1457 } 1458 htc->htc_next = 0; 1459 } 1460 1461 static __inline void 1462 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *htc, 1463 struct rtw_txctl *stx, int ndesc) 1464 { 1465 uint32_t hstat; 1466 int data_retry, rts_retry; 1467 struct rtw_txdesc *htxn; 1468 const char *condstring; 1469 1470 rtw_txbuf_release(sc->sc_dmat, &sc->sc_ic, stx); 1471 1472 htc->htc_nfree += ndesc; 1473 1474 htxn = &htc->htc_desc[stx->stx_last]; 1475 1476 hstat = le32toh(htxn->htx_stat); 1477 rts_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1478 data_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_DRC_MASK); 1479 1480 sc->sc_if.if_collisions += rts_retry + data_retry; 1481 1482 if ((hstat & RTW_TXSTAT_TOK) != 0) 1483 condstring = "ok"; 1484 else { 1485 sc->sc_if.if_oerrors++; 1486 condstring = "error"; 1487 } 1488 1489 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1490 ("%s: stx %p txdesc[%d, %d] %s tries rts %u data %u\n", 1491 sc->sc_dev.dv_xname, stx, stx->stx_first, stx->stx_last, 1492 condstring, rts_retry, data_retry)); 1493 } 1494 1495 /* Collect transmitted packets. */ 1496 static __inline void 1497 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txctl_blk *stc, 1498 struct rtw_txdesc_blk *htc) 1499 { 1500 int ndesc; 1501 struct rtw_txctl *stx; 1502 1503 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1504 ndesc = 1 + stx->stx_last - stx->stx_first; 1505 if (stx->stx_last < stx->stx_first) 1506 ndesc += htc->htc_ndesc; 1507 1508 KASSERT(ndesc > 0); 1509 1510 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, htc, 1511 stx->stx_first, ndesc, 1512 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1513 1514 if ((htc->htc_desc[stx->stx_last].htx_stat & 1515 htole32(RTW_TXSTAT_OWN)) != 0) 1516 break; 1517 1518 rtw_collect_txpkt(sc, htc, stx, ndesc); 1519 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1520 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1521 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1522 } 1523 if (stx == NULL) 1524 stc->stc_tx_timer = 0; 1525 } 1526 1527 static void 1528 rtw_intr_tx(struct rtw_softc *sc, u_int16_t isr) 1529 { 1530 int pri; 1531 struct rtw_txctl_blk *stc; 1532 struct rtw_txdesc_blk *htc; 1533 1534 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1535 stc = &sc->sc_txctl_blk[pri]; 1536 htc = &sc->sc_txdesc_blk[pri]; 1537 1538 rtw_collect_txring(sc, stc, htc); 1539 1540 if ((isr & RTW_INTR_TX) != 0) 1541 rtw_start(&sc->sc_if); 1542 } 1543 1544 /* TBD */ 1545 return; 1546 } 1547 1548 static void 1549 rtw_intr_beacon(struct rtw_softc *sc, u_int16_t isr) 1550 { 1551 /* TBD */ 1552 return; 1553 } 1554 1555 static void 1556 rtw_intr_atim(struct rtw_softc *sc) 1557 { 1558 /* TBD */ 1559 return; 1560 } 1561 1562 #ifdef RTW_DEBUG 1563 static void 1564 rtw_dump_rings(struct rtw_softc *sc) 1565 { 1566 struct rtw_txdesc_blk *htc; 1567 struct rtw_rxdesc *hrx; 1568 int desc, pri; 1569 1570 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1571 return; 1572 1573 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1574 htc = &sc->sc_txdesc_blk[pri]; 1575 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1576 htc->htc_ndesc, htc->htc_nfree); 1577 for (desc = 0; desc < htc->htc_ndesc; desc++) 1578 rtw_print_txdesc(sc, ".", NULL, htc, desc); 1579 } 1580 1581 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1582 hrx = &sc->sc_rxdesc[desc]; 1583 printf("%s: ctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1584 "rsvd1/tsfth %08x\n", __func__, 1585 le32toh(hrx->hrx_ctl), le32toh(hrx->hrx_rssi), 1586 le32toh(hrx->hrx_buf), le32toh(hrx->hrx_tsfth)); 1587 } 1588 } 1589 #endif /* RTW_DEBUG */ 1590 1591 static void 1592 rtw_hwring_setup(struct rtw_softc *sc) 1593 { 1594 struct rtw_regs *regs = &sc->sc_regs; 1595 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1596 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1597 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1598 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1599 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1600 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1601 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1602 ("%s: reg[TLPDA] <- %" PRIxPTR "\n", __func__, 1603 (uintptr_t)RTW_RING_BASE(sc, hd_txlo))); 1604 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1605 ("%s: reg[TNPDA] <- %" PRIxPTR "\n", __func__, 1606 (uintptr_t)RTW_RING_BASE(sc, hd_txmd))); 1607 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1608 ("%s: reg[THPDA] <- %" PRIxPTR "\n", __func__, 1609 (uintptr_t)RTW_RING_BASE(sc, hd_txhi))); 1610 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1611 ("%s: reg[TBDA] <- %" PRIxPTR "\n", __func__, 1612 (uintptr_t)RTW_RING_BASE(sc, hd_bcn))); 1613 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1614 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1615 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1616 } 1617 1618 static void 1619 rtw_swring_setup(struct rtw_softc *sc) 1620 { 1621 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1622 1623 rtw_txctl_blk_init_all(&sc->sc_txctl_blk[0]); 1624 1625 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1626 0, RTW_RXQLEN, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1627 rtw_rxctl_init_all(sc->sc_dmat, sc->sc_rxctl, &sc->sc_rxnext, 1628 sc->sc_dev.dv_xname); 1629 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, 1630 sc->sc_rxdesc, sc->sc_rxctl, 1); 1631 1632 rtw_txdescs_sync_all(sc->sc_dmat, sc->sc_desc_dmamap, 1633 &sc->sc_txdesc_blk[0]); 1634 #if 0 /* redundant with rtw_rxdesc_init_all */ 1635 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1636 0, RTW_RXQLEN, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1637 #endif 1638 } 1639 1640 static void 1641 rtw_txdesc_blk_reset(struct rtw_txdesc_blk *htc) 1642 { 1643 int i; 1644 1645 for (i = 0; i < htc->htc_ndesc; i++) 1646 htc->htc_desc[i].htx_next = htole32(RTW_NEXT_DESC(htc, i)); 1647 } 1648 1649 static void 1650 rtw_txdescs_reset(struct rtw_softc *sc) 1651 { 1652 int pri; 1653 struct rtw_txdesc_blk *htc; 1654 1655 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1656 htc = &sc->sc_txdesc_blk[pri]; 1657 rtw_txbufs_release(sc->sc_dmat, sc->sc_desc_dmamap, &sc->sc_ic, 1658 &sc->sc_txctl_blk[pri], htc); 1659 rtw_txdesc_blk_reset(htc); 1660 KASSERT(htc->htc_nfree == htc->htc_ndesc); 1661 } 1662 } 1663 1664 static void 1665 rtw_rxdescs_reset(struct rtw_softc *sc) 1666 { 1667 /* Re-initialize descriptors, just in case. */ 1668 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_rxdesc, 1669 &sc->sc_rxctl[0], 1); 1670 1671 /* Reset to start of ring. */ 1672 sc->sc_rxnext = 0; 1673 } 1674 1675 static void 1676 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 1677 { 1678 struct rtw_regs *regs = &sc->sc_regs; 1679 1680 if ((isr & RTW_INTR_TXFOVW) != 0) 1681 printf("%s: tx fifo overflow\n", sc->sc_dev.dv_xname); 1682 1683 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) == 0) 1684 return; 1685 1686 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: restarting xmit/recv\n", 1687 sc->sc_dev.dv_xname)); 1688 1689 #ifdef RTW_DEBUG 1690 rtw_dump_rings(sc); 1691 #endif /* RTW_DEBUG */ 1692 1693 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1694 1695 /* Collect rx'd packets. Refresh rx buffers. */ 1696 rtw_intr_rx(sc, 0); 1697 /* Collect tx'd packets. */ 1698 rtw_intr_tx(sc, 0); 1699 1700 RTW_WRITE16(regs, RTW_IMR, 0); 1701 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1702 1703 rtw_chip_reset1(regs, sc->sc_dev.dv_xname); 1704 1705 rtw_rxdescs_reset(sc); 1706 rtw_txdescs_reset(sc); 1707 1708 rtw_hwring_setup(sc); 1709 1710 #ifdef RTW_DEBUG 1711 rtw_dump_rings(sc); 1712 #endif /* RTW_DEBUG */ 1713 1714 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1715 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1716 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1717 } 1718 1719 static __inline void 1720 rtw_suspend_ticks(struct rtw_softc *sc) 1721 { 1722 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1723 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 1724 sc->sc_do_tick = 0; 1725 } 1726 1727 static __inline void 1728 rtw_resume_ticks(struct rtw_softc *sc) 1729 { 1730 u_int32_t tsftrl0, tsftrl1, next_tick; 1731 1732 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1733 1734 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1735 next_tick = tsftrl1 + 1000000; 1736 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1737 1738 sc->sc_do_tick = 1; 1739 1740 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1741 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1742 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 1743 } 1744 1745 static void 1746 rtw_intr_timeout(struct rtw_softc *sc) 1747 { 1748 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 1749 if (sc->sc_do_tick) 1750 rtw_resume_ticks(sc); 1751 return; 1752 } 1753 1754 int 1755 rtw_intr(void *arg) 1756 { 1757 int i; 1758 struct rtw_softc *sc = arg; 1759 struct rtw_regs *regs = &sc->sc_regs; 1760 u_int16_t isr; 1761 1762 /* 1763 * If the interface isn't running, the interrupt couldn't 1764 * possibly have come from us. 1765 */ 1766 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1767 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1768 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1769 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1770 return (0); 1771 } 1772 1773 for (i = 0; i < 10; i++) { 1774 isr = RTW_READ16(regs, RTW_ISR); 1775 1776 RTW_WRITE16(regs, RTW_ISR, isr); 1777 RTW_WBR(regs, RTW_ISR, RTW_ISR); 1778 1779 if (sc->sc_intr_ack != NULL) 1780 (*sc->sc_intr_ack)(regs); 1781 1782 if (isr == 0) 1783 break; 1784 1785 #ifdef RTW_DEBUG 1786 #define PRINTINTR(flag) do { \ 1787 if ((isr & flag) != 0) { \ 1788 printf("%s" #flag, delim); \ 1789 delim = ","; \ 1790 } \ 1791 } while (0) 1792 1793 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 1794 const char *delim = "<"; 1795 1796 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1797 1798 PRINTINTR(RTW_INTR_TXFOVW); 1799 PRINTINTR(RTW_INTR_TIMEOUT); 1800 PRINTINTR(RTW_INTR_BCNINT); 1801 PRINTINTR(RTW_INTR_ATIMINT); 1802 PRINTINTR(RTW_INTR_TBDER); 1803 PRINTINTR(RTW_INTR_TBDOK); 1804 PRINTINTR(RTW_INTR_THPDER); 1805 PRINTINTR(RTW_INTR_THPDOK); 1806 PRINTINTR(RTW_INTR_TNPDER); 1807 PRINTINTR(RTW_INTR_TNPDOK); 1808 PRINTINTR(RTW_INTR_RXFOVW); 1809 PRINTINTR(RTW_INTR_RDU); 1810 PRINTINTR(RTW_INTR_TLPDER); 1811 PRINTINTR(RTW_INTR_TLPDOK); 1812 PRINTINTR(RTW_INTR_RER); 1813 PRINTINTR(RTW_INTR_ROK); 1814 1815 printf(">\n"); 1816 } 1817 #undef PRINTINTR 1818 #endif /* RTW_DEBUG */ 1819 1820 if ((isr & RTW_INTR_RX) != 0) 1821 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1822 if ((isr & RTW_INTR_TX) != 0) 1823 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1824 if ((isr & RTW_INTR_BEACON) != 0) 1825 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1826 if ((isr & RTW_INTR_ATIMINT) != 0) 1827 rtw_intr_atim(sc); 1828 if ((isr & RTW_INTR_IOERROR) != 0) 1829 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1830 if ((isr & RTW_INTR_TIMEOUT) != 0) 1831 rtw_intr_timeout(sc); 1832 } 1833 1834 return 1; 1835 } 1836 1837 /* Must be called at splnet. */ 1838 static void 1839 rtw_stop(struct ifnet *ifp, int disable) 1840 { 1841 int pri; 1842 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1843 struct ieee80211com *ic = &sc->sc_ic; 1844 struct rtw_regs *regs = &sc->sc_regs; 1845 1846 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1847 return; 1848 1849 rtw_suspend_ticks(sc); 1850 1851 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1852 1853 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1854 /* Disable interrupts. */ 1855 RTW_WRITE16(regs, RTW_IMR, 0); 1856 1857 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 1858 1859 /* Stop the transmit and receive processes. First stop DMA, 1860 * then disable receiver and transmitter. 1861 */ 1862 RTW_WRITE8(regs, RTW_TPPOLL, 1863 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ| 1864 RTW_TPPOLL_SLPQ); 1865 1866 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 1867 1868 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1869 } 1870 1871 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1872 rtw_txbufs_release(sc->sc_dmat, sc->sc_desc_dmamap, &sc->sc_ic, 1873 &sc->sc_txctl_blk[pri], &sc->sc_txdesc_blk[pri]); 1874 } 1875 1876 if (disable) { 1877 rtw_disable(sc); 1878 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1879 } 1880 1881 /* Mark the interface as not running. Cancel the watchdog timer. */ 1882 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1883 ifp->if_timer = 0; 1884 1885 return; 1886 } 1887 1888 const char * 1889 rtw_pwrstate_string(enum rtw_pwrstate power) 1890 { 1891 switch (power) { 1892 case RTW_ON: 1893 return "on"; 1894 case RTW_SLEEP: 1895 return "sleep"; 1896 case RTW_OFF: 1897 return "off"; 1898 default: 1899 return "unknown"; 1900 } 1901 } 1902 1903 /* XXX For Maxim, I am using the RFMD settings gleaned from the 1904 * reference driver, plus a magic Maxim "ON" value that comes from 1905 * the Realtek document "Windows PG for Rtl8180." 1906 */ 1907 static void 1908 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1909 int before_rf, int digphy) 1910 { 1911 u_int32_t anaparm; 1912 1913 anaparm = RTW_READ(regs, RTW_ANAPARM); 1914 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1915 1916 switch (power) { 1917 case RTW_OFF: 1918 if (before_rf) 1919 return; 1920 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 1921 anaparm |= RTW_ANAPARM_TXDACOFF; 1922 break; 1923 case RTW_SLEEP: 1924 if (!before_rf) 1925 return; 1926 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 1927 anaparm |= RTW_ANAPARM_TXDACOFF; 1928 break; 1929 case RTW_ON: 1930 if (!before_rf) 1931 return; 1932 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 1933 break; 1934 } 1935 RTW_DPRINTF(RTW_DEBUG_PWR, 1936 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 1937 __func__, rtw_pwrstate_string(power), 1938 (before_rf) ? "before" : "after", anaparm)); 1939 1940 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1941 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1942 } 1943 1944 /* XXX I am using the RFMD settings gleaned from the reference 1945 * driver. They agree 1946 */ 1947 static void 1948 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1949 int before_rf, int digphy) 1950 { 1951 u_int32_t anaparm; 1952 1953 anaparm = RTW_READ(regs, RTW_ANAPARM); 1954 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1955 1956 switch (power) { 1957 case RTW_OFF: 1958 if (before_rf) 1959 return; 1960 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 1961 anaparm |= RTW_ANAPARM_TXDACOFF; 1962 break; 1963 case RTW_SLEEP: 1964 if (!before_rf) 1965 return; 1966 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 1967 anaparm |= RTW_ANAPARM_TXDACOFF; 1968 break; 1969 case RTW_ON: 1970 if (!before_rf) 1971 return; 1972 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 1973 break; 1974 } 1975 RTW_DPRINTF(RTW_DEBUG_PWR, 1976 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 1977 __func__, rtw_pwrstate_string(power), 1978 (before_rf) ? "before" : "after", anaparm)); 1979 1980 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1981 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1982 } 1983 1984 static void 1985 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1986 int before_rf, int digphy) 1987 { 1988 u_int32_t anaparm; 1989 1990 anaparm = RTW_READ(regs, RTW_ANAPARM); 1991 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1992 1993 switch (power) { 1994 case RTW_OFF: 1995 if (before_rf) 1996 return; 1997 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 1998 anaparm |= RTW_ANAPARM_TXDACOFF; 1999 break; 2000 case RTW_SLEEP: 2001 if (!before_rf) 2002 return; 2003 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2004 anaparm |= RTW_ANAPARM_TXDACOFF; 2005 break; 2006 case RTW_ON: 2007 if (!before_rf) 2008 return; 2009 if (digphy) { 2010 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2011 /* XXX guess */ 2012 anaparm |= RTW_ANAPARM_TXDACOFF; 2013 } else 2014 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2015 break; 2016 } 2017 RTW_DPRINTF(RTW_DEBUG_PWR, 2018 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2019 __func__, rtw_pwrstate_string(power), 2020 (before_rf) ? "before" : "after", anaparm)); 2021 2022 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2023 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2024 } 2025 2026 static void 2027 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2028 int digphy) 2029 { 2030 struct rtw_regs *regs = &sc->sc_regs; 2031 2032 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 2033 2034 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2035 2036 rtw_set_access(sc, RTW_ACCESS_NONE); 2037 2038 return; 2039 } 2040 2041 static int 2042 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2043 { 2044 int rc; 2045 2046 RTW_DPRINTF(RTW_DEBUG_PWR, 2047 ("%s: %s->%s\n", __func__, 2048 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2049 2050 if (sc->sc_pwrstate == power) 2051 return 0; 2052 2053 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2054 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2055 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2056 2057 switch (power) { 2058 case RTW_ON: 2059 /* TBD set LEDs */ 2060 break; 2061 case RTW_SLEEP: 2062 /* TBD */ 2063 break; 2064 case RTW_OFF: 2065 /* TBD */ 2066 break; 2067 } 2068 if (rc == 0) 2069 sc->sc_pwrstate = power; 2070 else 2071 sc->sc_pwrstate = RTW_OFF; 2072 return rc; 2073 } 2074 2075 static int 2076 rtw_tune(struct rtw_softc *sc) 2077 { 2078 struct ieee80211com *ic = &sc->sc_ic; 2079 u_int chan; 2080 int rc; 2081 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2082 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2083 2084 KASSERT(ic->ic_bss->ni_chan != NULL); 2085 2086 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2087 if (chan == IEEE80211_CHAN_ANY) 2088 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 2089 2090 if (chan == sc->sc_cur_chan) { 2091 RTW_DPRINTF(RTW_DEBUG_TUNE, 2092 ("%s: already tuned chan #%d\n", __func__, chan)); 2093 return 0; 2094 } 2095 2096 rtw_suspend_ticks(sc); 2097 2098 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 2099 2100 /* TBD wait for Tx to complete */ 2101 2102 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2103 2104 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2105 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 2106 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 2107 dflantb, RTW_ON)) != 0) { 2108 /* XXX condition on powersaving */ 2109 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2110 } 2111 2112 sc->sc_cur_chan = chan; 2113 2114 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 2115 2116 rtw_resume_ticks(sc); 2117 2118 return rc; 2119 } 2120 2121 void 2122 rtw_disable(struct rtw_softc *sc) 2123 { 2124 int rc; 2125 2126 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2127 return; 2128 2129 /* turn off PHY */ 2130 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2131 printf("%s: failed to turn off PHY (%d)\n", 2132 sc->sc_dev.dv_xname, rc); 2133 2134 if (sc->sc_disable != NULL) 2135 (*sc->sc_disable)(sc); 2136 2137 sc->sc_flags &= ~RTW_F_ENABLED; 2138 } 2139 2140 int 2141 rtw_enable(struct rtw_softc *sc) 2142 { 2143 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2144 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2145 printf("%s: device enable failed\n", 2146 sc->sc_dev.dv_xname); 2147 return (EIO); 2148 } 2149 sc->sc_flags |= RTW_F_ENABLED; 2150 } 2151 return (0); 2152 } 2153 2154 static void 2155 rtw_transmit_config(struct rtw_regs *regs) 2156 { 2157 u_int32_t tcr; 2158 2159 tcr = RTW_READ(regs, RTW_TCR); 2160 2161 tcr |= RTW_TCR_CWMIN; 2162 tcr &= ~RTW_TCR_MXDMA_MASK; 2163 tcr |= RTW_TCR_MXDMA_256; 2164 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2165 tcr &= ~RTW_TCR_LBK_MASK; 2166 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2167 2168 /* set short/long retry limits */ 2169 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2170 tcr |= LSHIFT(4, RTW_TCR_SRL_MASK) | LSHIFT(4, RTW_TCR_LRL_MASK); 2171 2172 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2173 2174 RTW_WRITE(regs, RTW_TCR, tcr); 2175 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2176 } 2177 2178 static __inline void 2179 rtw_enable_interrupts(struct rtw_softc *sc) 2180 { 2181 struct rtw_regs *regs = &sc->sc_regs; 2182 2183 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2184 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2185 2186 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2187 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2188 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2189 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2190 2191 /* XXX necessary? */ 2192 if (sc->sc_intr_ack != NULL) 2193 (*sc->sc_intr_ack)(regs); 2194 } 2195 2196 static void 2197 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2198 { 2199 uint8_t msr; 2200 2201 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2202 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2203 2204 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2205 2206 switch (opmode) { 2207 case IEEE80211_M_AHDEMO: 2208 case IEEE80211_M_IBSS: 2209 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2210 break; 2211 case IEEE80211_M_HOSTAP: 2212 msr |= RTW_MSR_NETYPE_AP_OK; 2213 break; 2214 case IEEE80211_M_MONITOR: 2215 /* XXX */ 2216 msr |= RTW_MSR_NETYPE_NOLINK; 2217 break; 2218 case IEEE80211_M_STA: 2219 msr |= RTW_MSR_NETYPE_INFRA_OK; 2220 break; 2221 } 2222 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2223 2224 rtw_set_access(sc, RTW_ACCESS_NONE); 2225 } 2226 2227 /* XXX is the endianness correct? test. */ 2228 #define rtw_calchash(addr) \ 2229 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 2230 2231 static void 2232 rtw_pktfilt_load(struct rtw_softc *sc) 2233 { 2234 struct rtw_regs *regs = &sc->sc_regs; 2235 struct ieee80211com *ic = &sc->sc_ic; 2236 struct ethercom *ec = &ic->ic_ec; 2237 struct ifnet *ifp = &sc->sc_ic.ic_if; 2238 int hash; 2239 u_int32_t hashes[2] = { 0, 0 }; 2240 struct ether_multi *enm; 2241 struct ether_multistep step; 2242 2243 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2244 2245 #define RTW_RCR_MONITOR (RTW_RCR_ACRC32|RTW_RCR_APM|RTW_RCR_AAP|RTW_RCR_AB|RTW_RCR_ACF | RTW_RCR_AICV | RTW_RCR_ACRC32) 2246 2247 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2248 sc->sc_rcr |= RTW_RCR_MONITOR; 2249 else 2250 sc->sc_rcr &= ~RTW_RCR_MONITOR; 2251 2252 /* XXX reference sources BEGIN */ 2253 sc->sc_rcr |= RTW_RCR_ENMARP; 2254 sc->sc_rcr |= RTW_RCR_AB | RTW_RCR_AM | RTW_RCR_APM; 2255 #if 0 2256 /* receive broadcasts in our BSS */ 2257 sc->sc_rcr |= RTW_RCR_ADD3; 2258 #endif 2259 /* XXX reference sources END */ 2260 2261 /* receive pwrmgmt frames. */ 2262 sc->sc_rcr |= RTW_RCR_APWRMGT; 2263 /* receive mgmt/ctrl/data frames. */ 2264 sc->sc_rcr |= RTW_RCR_ADF | RTW_RCR_AMF; 2265 /* initialize Rx DMA threshold, Tx DMA burst size */ 2266 sc->sc_rcr |= RTW_RCR_RXFTH_WHOLE | RTW_RCR_MXDMA_1024; 2267 2268 ifp->if_flags &= ~IFF_ALLMULTI; 2269 2270 if (ifp->if_flags & IFF_PROMISC) { 2271 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2272 allmulti: 2273 ifp->if_flags |= IFF_ALLMULTI; 2274 goto setit; 2275 } 2276 2277 /* 2278 * Program the 64-bit multicast hash filter. 2279 */ 2280 ETHER_FIRST_MULTI(step, ec, enm); 2281 while (enm != NULL) { 2282 /* XXX */ 2283 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2284 ETHER_ADDR_LEN) != 0) 2285 goto allmulti; 2286 2287 hash = rtw_calchash(enm->enm_addrlo); 2288 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2289 ETHER_NEXT_MULTI(step, enm); 2290 } 2291 2292 if (ifp->if_flags & IFF_BROADCAST) { 2293 hash = rtw_calchash(etherbroadcastaddr); 2294 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2295 } 2296 2297 /* all bits set => hash is useless */ 2298 if (~(hashes[0] & hashes[1]) == 0) 2299 goto allmulti; 2300 2301 setit: 2302 if (ifp->if_flags & IFF_ALLMULTI) 2303 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2304 2305 if (ic->ic_state == IEEE80211_S_SCAN) 2306 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2307 2308 hashes[0] = hashes[1] = 0xffffffff; 2309 2310 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2311 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2312 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2313 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2314 2315 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2316 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2317 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2318 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2319 2320 return; 2321 } 2322 2323 /* Must be called at splnet. */ 2324 static int 2325 rtw_init(struct ifnet *ifp) 2326 { 2327 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2328 struct ieee80211com *ic = &sc->sc_ic; 2329 struct rtw_regs *regs = &sc->sc_regs; 2330 int rc = 0; 2331 2332 if ((rc = rtw_enable(sc)) != 0) 2333 goto out; 2334 2335 /* Cancel pending I/O and reset. */ 2336 rtw_stop(ifp, 0); 2337 2338 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2339 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2340 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2341 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2342 2343 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2344 goto out; 2345 2346 rtw_swring_setup(sc); 2347 2348 rtw_transmit_config(regs); 2349 2350 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2351 2352 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2353 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2354 2355 /* long PLCP header, 1Mb/2Mb basic rate */ 2356 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2357 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2358 2359 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 2360 rtw_set_access(sc, RTW_ACCESS_NONE); 2361 2362 #if 0 2363 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_GWAKE|RTW_FEMR_WKUP|RTW_FEMR_INTR); 2364 #endif 2365 /* XXX from reference sources */ 2366 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2367 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2368 2369 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2370 2371 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2372 /* from Linux driver */ 2373 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2374 2375 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2376 2377 rtw_enable_interrupts(sc); 2378 2379 rtw_pktfilt_load(sc); 2380 2381 rtw_hwring_setup(sc); 2382 2383 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2384 2385 ifp->if_flags |= IFF_RUNNING; 2386 ic->ic_state = IEEE80211_S_INIT; 2387 2388 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2389 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2390 2391 rtw_resume_ticks(sc); 2392 2393 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2394 2395 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2396 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2397 else 2398 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2399 2400 out: 2401 return rc; 2402 } 2403 2404 static int 2405 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2406 { 2407 int rc = 0, s; 2408 struct rtw_softc *sc = ifp->if_softc; 2409 struct ifreq *ifr = (struct ifreq *)data; 2410 2411 s = splnet(); 2412 switch (cmd) { 2413 case SIOCSIFFLAGS: 2414 if ((ifp->if_flags & IFF_UP) != 0) { 2415 if (0 && (sc->sc_flags & RTW_F_ENABLED) != 0) { 2416 rtw_pktfilt_load(sc); 2417 } else 2418 rc = rtw_init(ifp); 2419 #ifdef RTW_DEBUG 2420 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2421 #endif /* RTW_DEBUG */ 2422 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2423 #ifdef RTW_DEBUG 2424 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2425 #endif /* RTW_DEBUG */ 2426 rtw_stop(ifp, 1); 2427 } 2428 break; 2429 case SIOCADDMULTI: 2430 case SIOCDELMULTI: 2431 if (cmd == SIOCADDMULTI) 2432 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2433 else 2434 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2435 if (rc == ENETRESET) { 2436 if (ifp->if_flags & IFF_RUNNING) 2437 rtw_pktfilt_load(sc); 2438 rc = 0; 2439 } 2440 break; 2441 default: 2442 if ((rc = ieee80211_ioctl(ifp, cmd, data)) == ENETRESET) { 2443 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2444 rc = rtw_init(ifp); 2445 else 2446 rc = 0; 2447 } 2448 break; 2449 } 2450 splx(s); 2451 return rc; 2452 } 2453 2454 /* Point *mp at the next 802.11 frame to transmit. Point *stcp 2455 * at the driver's selection of transmit control block for the packet. 2456 */ 2457 static __inline int 2458 rtw_dequeue(struct ifnet *ifp, struct rtw_txctl_blk **stcp, 2459 struct rtw_txdesc_blk **htcp, struct mbuf **mp, 2460 struct ieee80211_node **nip) 2461 { 2462 struct rtw_txctl_blk *stc; 2463 struct rtw_txdesc_blk *htc; 2464 struct mbuf *m0; 2465 struct rtw_softc *sc; 2466 struct ieee80211com *ic; 2467 2468 sc = (struct rtw_softc *)ifp->if_softc; 2469 2470 DPRINTF(sc, RTW_DEBUG_XMIT, 2471 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2472 *mp = NULL; 2473 2474 stc = &sc->sc_txctl_blk[RTW_TXPRIMD]; 2475 htc = &sc->sc_txdesc_blk[RTW_TXPRIMD]; 2476 2477 if (SIMPLEQ_EMPTY(&stc->stc_freeq) || htc->htc_nfree == 0) { 2478 DPRINTF(sc, RTW_DEBUG_XMIT, 2479 ("%s: out of descriptors\n", __func__)); 2480 ifp->if_flags |= IFF_OACTIVE; 2481 return 0; 2482 } 2483 2484 ic = &sc->sc_ic; 2485 2486 if (!IF_IS_EMPTY(&ic->ic_mgtq)) { 2487 IF_DEQUEUE(&ic->ic_mgtq, m0); 2488 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2489 m0->m_pkthdr.rcvif = NULL; 2490 DPRINTF(sc, RTW_DEBUG_XMIT, 2491 ("%s: dequeue mgt frame\n", __func__)); 2492 } else if (ic->ic_state != IEEE80211_S_RUN) { 2493 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 2494 return 0; 2495 } else if (!IF_IS_EMPTY(&ic->ic_pwrsaveq)) { 2496 IF_DEQUEUE(&ic->ic_pwrsaveq, m0); 2497 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2498 m0->m_pkthdr.rcvif = NULL; 2499 DPRINTF(sc, RTW_DEBUG_XMIT, 2500 ("%s: dequeue pwrsave frame\n", __func__)); 2501 } else { 2502 IFQ_DEQUEUE(&ifp->if_snd, m0); 2503 if (m0 == NULL) { 2504 DPRINTF(sc, RTW_DEBUG_XMIT, 2505 ("%s: no frame\n", __func__)); 2506 return 0; 2507 } 2508 DPRINTF(sc, RTW_DEBUG_XMIT, 2509 ("%s: dequeue data frame\n", __func__)); 2510 ifp->if_opackets++; 2511 #if NBPFILTER > 0 2512 if (ifp->if_bpf) 2513 bpf_mtap(ifp->if_bpf, m0); 2514 #endif 2515 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2516 DPRINTF(sc, RTW_DEBUG_XMIT, 2517 ("%s: encap error\n", __func__)); 2518 ifp->if_oerrors++; 2519 return -1; 2520 } 2521 } 2522 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 2523 *stcp = stc; 2524 *htcp = htc; 2525 *mp = m0; 2526 return 0; 2527 } 2528 2529 static int 2530 rtw_seg_too_short(bus_dmamap_t dmamap) 2531 { 2532 int i; 2533 for (i = 0; i < dmamap->dm_nsegs; i++) { 2534 if (dmamap->dm_segs[i].ds_len < 4) { 2535 printf("%s: segment too short\n", __func__); 2536 return 1; 2537 } 2538 } 2539 return 0; 2540 } 2541 2542 /* TBD factor with atw_start */ 2543 static struct mbuf * 2544 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2545 u_int ndescfree, short *ifflagsp, const char *dvname) 2546 { 2547 int first, rc; 2548 struct mbuf *m, *m0; 2549 2550 m0 = chain; 2551 2552 /* 2553 * Load the DMA map. Copy and try (once) again if the packet 2554 * didn't fit in the alloted number of segments. 2555 */ 2556 for (first = 1; 2557 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2558 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2559 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 2560 first = 0) { 2561 if (rc == 0) 2562 bus_dmamap_unload(dmat, dmam); 2563 MGETHDR(m, M_DONTWAIT, MT_DATA); 2564 if (m == NULL) { 2565 printf("%s: unable to allocate Tx mbuf\n", 2566 dvname); 2567 break; 2568 } 2569 if (m0->m_pkthdr.len > MHLEN) { 2570 MCLGET(m, M_DONTWAIT); 2571 if ((m->m_flags & M_EXT) == 0) { 2572 printf("%s: cannot allocate Tx cluster\n", 2573 dvname); 2574 m_freem(m); 2575 break; 2576 } 2577 } 2578 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2579 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 2580 m_freem(m0); 2581 m0 = m; 2582 m = NULL; 2583 } 2584 if (rc != 0) { 2585 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 2586 m_freem(m0); 2587 return NULL; 2588 } else if (rtw_seg_too_short(dmam)) { 2589 printf("%s: cannot load Tx buffer, segment too short\n", 2590 dvname); 2591 bus_dmamap_unload(dmat, dmam); 2592 m_freem(m0); 2593 return NULL; 2594 } else if (dmam->dm_nsegs > ndescfree) { 2595 *ifflagsp |= IFF_OACTIVE; 2596 bus_dmamap_unload(dmat, dmam); 2597 m_freem(m0); 2598 return NULL; 2599 } 2600 return m0; 2601 } 2602 2603 #ifdef RTW_DEBUG 2604 static void 2605 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 2606 struct rtw_txctl *stx, struct rtw_txdesc_blk *htc, int desc) 2607 { 2608 struct rtw_txdesc *htx = &htc->htc_desc[desc]; 2609 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] ctl0 %#08x " 2610 "ctl1 %#08x buf %#08x len %#08x\n", 2611 sc->sc_dev.dv_xname, stx, action, desc, 2612 le32toh(htx->htx_ctl0), 2613 le32toh(htx->htx_ctl1), le32toh(htx->htx_buf), 2614 le32toh(htx->htx_len))); 2615 } 2616 #endif /* RTW_DEBUG */ 2617 2618 static void 2619 rtw_start(struct ifnet *ifp) 2620 { 2621 uint8_t tppoll; 2622 int desc, i, lastdesc, npkt, rate; 2623 uint32_t proto_ctl0, ctl0, ctl1; 2624 bus_dmamap_t dmamap; 2625 struct ieee80211com *ic; 2626 struct ieee80211_duration *d0; 2627 struct ieee80211_frame *wh; 2628 struct ieee80211_node *ni; 2629 struct mbuf *m0; 2630 struct rtw_softc *sc; 2631 struct rtw_txctl_blk *stc; 2632 struct rtw_txdesc_blk *htc; 2633 struct rtw_txctl *stx; 2634 struct rtw_txdesc *htx; 2635 2636 sc = (struct rtw_softc *)ifp->if_softc; 2637 ic = &sc->sc_ic; 2638 2639 DPRINTF(sc, RTW_DEBUG_XMIT, 2640 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2641 2642 /* XXX do real rate control */ 2643 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 2644 2645 switch (rate = MAX(2, ieee80211_get_rate(ic))) { 2646 case 2: 2647 proto_ctl0 |= RTW_TXCTL0_RATE_1MBPS; 2648 break; 2649 case 4: 2650 proto_ctl0 |= RTW_TXCTL0_RATE_2MBPS; 2651 break; 2652 case 11: 2653 proto_ctl0 |= RTW_TXCTL0_RATE_5MBPS; 2654 break; 2655 case 22: 2656 proto_ctl0 |= RTW_TXCTL0_RATE_11MBPS; 2657 break; 2658 } 2659 2660 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 2661 proto_ctl0 |= RTW_TXCTL0_SPLCP; 2662 2663 for (;;) { 2664 if (rtw_dequeue(ifp, &stc, &htc, &m0, &ni) == -1) 2665 continue; 2666 if (m0 == NULL) 2667 break; 2668 stx = SIMPLEQ_FIRST(&stc->stc_freeq); 2669 2670 dmamap = stx->stx_dmamap; 2671 2672 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 2673 htc->htc_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 2674 2675 if (m0 == NULL || dmamap->dm_nsegs == 0) { 2676 DPRINTF(sc, RTW_DEBUG_XMIT, 2677 ("%s: fail dmamap load\n", __func__)); 2678 goto post_dequeue_err; 2679 } 2680 2681 #ifdef RTW_DEBUG 2682 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 2683 (IFF_DEBUG|IFF_LINK2)) { 2684 ieee80211_dump_pkt(mtod(m0, uint8_t *), 2685 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 2686 : sizeof(wh), 2687 rate, 0); 2688 } 2689 #endif /* RTW_DEBUG */ 2690 ctl0 = proto_ctl0 | 2691 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 2692 2693 wh = mtod(m0, struct ieee80211_frame *); 2694 2695 if (ieee80211_compute_duration(wh, m0->m_pkthdr.len, 2696 ic->ic_flags, ic->ic_fragthreshold, 2697 rate, &stx->stx_d0, &stx->stx_dn, &npkt, 2698 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 2699 (IFF_DEBUG|IFF_LINK2)) == -1) { 2700 DPRINTF(sc, RTW_DEBUG_XMIT, 2701 ("%s: fail compute duration\n", __func__)); 2702 goto post_load_err; 2703 } 2704 2705 /* XXX >= ? */ 2706 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 2707 ctl0 |= RTW_TXCTL0_RTSEN; 2708 2709 d0 = &stx->stx_d0; 2710 2711 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 2712 2713 ctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 2714 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 2715 2716 if (d0->d_residue) 2717 ctl1 |= RTW_TXCTL1_LENGEXT; 2718 2719 /* TBD fragmentation */ 2720 2721 stx->stx_first = htc->htc_next; 2722 2723 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2724 htc, stx->stx_first, dmamap->dm_nsegs, 2725 BUS_DMASYNC_PREWRITE); 2726 2727 KASSERT(stx->stx_first < htc->htc_ndesc); 2728 2729 for (i = 0, lastdesc = desc = stx->stx_first; 2730 i < dmamap->dm_nsegs; 2731 i++, desc = RTW_NEXT_IDX(htc, desc)) { 2732 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 2733 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 2734 ("%s: seg too long\n", __func__)); 2735 goto post_load_err; 2736 } 2737 htx = &htc->htc_desc[desc]; 2738 htx->htx_ctl0 = htole32(ctl0); 2739 if (i != 0) 2740 htx->htx_ctl0 |= htole32(RTW_TXCTL0_OWN); 2741 htx->htx_ctl1 = htole32(ctl1); 2742 htx->htx_buf = htole32(dmamap->dm_segs[i].ds_addr); 2743 htx->htx_len = htole32(dmamap->dm_segs[i].ds_len); 2744 lastdesc = desc; 2745 #ifdef RTW_DEBUG 2746 rtw_print_txdesc(sc, "load", stx, htc, desc); 2747 #endif /* RTW_DEBUG */ 2748 } 2749 2750 KASSERT(desc < htc->htc_ndesc); 2751 2752 stx->stx_ni = ni; 2753 stx->stx_mbuf = m0; 2754 stx->stx_last = lastdesc; 2755 htc->htc_desc[stx->stx_last].htx_ctl0 |= htole32(RTW_TXCTL0_LS); 2756 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2757 htole32(RTW_TXCTL0_FS); 2758 2759 #ifdef RTW_DEBUG 2760 rtw_print_txdesc(sc, "FS on", stx, htc, stx->stx_first); 2761 rtw_print_txdesc(sc, "LS on", stx, htc, stx->stx_last); 2762 #endif /* RTW_DEBUG */ 2763 2764 htc->htc_nfree -= dmamap->dm_nsegs; 2765 htc->htc_next = desc; 2766 2767 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2768 htc, stx->stx_first, dmamap->dm_nsegs, 2769 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2770 2771 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2772 htole32(RTW_TXCTL0_OWN); 2773 2774 #ifdef RTW_DEBUG 2775 rtw_print_txdesc(sc, "OWN on", stx, htc, stx->stx_first); 2776 #endif /* RTW_DEBUG */ 2777 2778 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2779 htc, stx->stx_first, 1, 2780 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2781 2782 SIMPLEQ_REMOVE_HEAD(&stc->stc_freeq, stx_q); 2783 SIMPLEQ_INSERT_TAIL(&stc->stc_dirtyq, stx, stx_q); 2784 2785 stc->stc_tx_timer = 5; 2786 ifp->if_timer = 1; 2787 2788 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 2789 2790 /* TBD poke other queues. */ 2791 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll | RTW_TPPOLL_NPQ); 2792 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 2793 } 2794 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 2795 return; 2796 post_load_err: 2797 bus_dmamap_unload(sc->sc_dmat, dmamap); 2798 m_freem(m0); 2799 post_dequeue_err: 2800 ieee80211_release_node(&sc->sc_ic, ni); 2801 return; 2802 } 2803 2804 static void 2805 rtw_watchdog(struct ifnet *ifp) 2806 { 2807 int pri; 2808 struct rtw_softc *sc; 2809 struct rtw_txctl_blk *stc; 2810 2811 sc = ifp->if_softc; 2812 2813 ifp->if_timer = 0; 2814 2815 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2816 return; 2817 2818 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2819 stc = &sc->sc_txctl_blk[pri]; 2820 2821 if (stc->stc_tx_timer == 0) 2822 continue; 2823 2824 if (--stc->stc_tx_timer == 0) { 2825 if (SIMPLEQ_EMPTY(&stc->stc_dirtyq)) 2826 continue; 2827 printf("%s: transmit timeout, priority %d\n", 2828 ifp->if_xname, pri); 2829 ifp->if_oerrors++; 2830 /* XXX do more? */ 2831 rtw_intr_tx(sc, 0); 2832 rtw_txdescs_reset(sc); 2833 rtw_start(ifp); 2834 } else 2835 ifp->if_timer = 1; 2836 } 2837 ieee80211_watchdog(ifp); 2838 return; 2839 } 2840 2841 static void 2842 rtw_start_beacon(struct rtw_softc *sc, int enable) 2843 { 2844 /* TBD */ 2845 return; 2846 } 2847 2848 static void 2849 rtw_next_scan(void *arg) 2850 { 2851 struct ieee80211com *ic = arg; 2852 int s; 2853 2854 /* don't call rtw_start w/o network interrupts blocked */ 2855 s = splnet(); 2856 if (ic->ic_state == IEEE80211_S_SCAN) 2857 ieee80211_next_scan(ic); 2858 splx(s); 2859 } 2860 2861 static void 2862 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, enum ieee80211_opmode opmode, 2863 uint16_t intval0) 2864 { 2865 uint16_t bcnitv, intval; 2866 int i; 2867 struct rtw_regs *regs = &sc->sc_regs; 2868 2869 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 2870 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 2871 2872 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 2873 2874 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2875 2876 intval = MIN(intval0, PRESHIFT(RTW_BCNITV_BCNITV_MASK)); 2877 2878 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 2879 bcnitv |= LSHIFT(intval, RTW_BCNITV_BCNITV_MASK); 2880 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 2881 /* magic from Linux */ 2882 RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND)); 2883 RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV)); 2884 2885 rtw_set_nettype(sc, opmode); 2886 2887 rtw_set_access(sc, RTW_ACCESS_NONE); 2888 2889 /* TBD WEP */ 2890 RTW_WRITE8(regs, RTW_SCR, 0); 2891 2892 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 2893 } 2894 2895 /* Synchronize the hardware state with the software state. */ 2896 static int 2897 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2898 { 2899 struct ifnet *ifp = &ic->ic_if; 2900 struct rtw_softc *sc = ifp->if_softc; 2901 enum ieee80211_state ostate; 2902 int error; 2903 2904 ostate = ic->ic_state; 2905 2906 if (nstate == IEEE80211_S_INIT) { 2907 callout_stop(&sc->sc_scan_ch); 2908 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2909 rtw_start_beacon(sc, 0); 2910 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2911 } 2912 2913 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 2914 rtw_pwrstate(sc, RTW_ON); 2915 2916 if ((error = rtw_tune(sc)) != 0) 2917 return error; 2918 2919 switch (nstate) { 2920 case IEEE80211_S_ASSOC: 2921 rtw_join_bss(sc, ic->ic_bss->ni_bssid, ic->ic_opmode, 2922 ic->ic_bss->ni_intval); 2923 break; 2924 case IEEE80211_S_INIT: 2925 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2926 break; 2927 case IEEE80211_S_SCAN: 2928 if (ostate != IEEE80211_S_SCAN) { 2929 (void)memset(ic->ic_bss->ni_bssid, 0, 2930 IEEE80211_ADDR_LEN); 2931 rtw_join_bss(sc, ic->ic_bss->ni_bssid, ic->ic_opmode, 2932 ic->ic_bss->ni_intval); 2933 } 2934 2935 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 2936 rtw_next_scan, ic); 2937 2938 break; 2939 case IEEE80211_S_RUN: 2940 if (ic->ic_opmode == IEEE80211_M_STA) 2941 break; 2942 /*FALLTHROUGH*/ 2943 case IEEE80211_S_AUTH: 2944 #if 0 2945 rtw_write_bcn_thresh(sc); 2946 rtw_write_ssid(sc); 2947 rtw_write_sup_rates(sc); 2948 #endif 2949 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2950 ic->ic_opmode == IEEE80211_M_MONITOR) 2951 break; 2952 2953 /* TBD set listen interval */ 2954 2955 #if 0 2956 rtw_tsf(sc); 2957 #endif 2958 break; 2959 } 2960 2961 if (nstate != IEEE80211_S_SCAN) 2962 callout_stop(&sc->sc_scan_ch); 2963 2964 if (nstate == IEEE80211_S_RUN && 2965 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2966 ic->ic_opmode == IEEE80211_M_IBSS)) 2967 rtw_start_beacon(sc, 1); 2968 else 2969 rtw_start_beacon(sc, 0); 2970 2971 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2972 } 2973 2974 static void 2975 rtw_recv_beacon(struct rtw_softc *sc, struct mbuf *m, 2976 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2977 { 2978 (*sc->sc_mtbl.mt_recv_mgmt)(&sc->sc_ic, m, ni, subtype, rssi, rstamp); 2979 return; 2980 } 2981 2982 static void 2983 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2984 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2985 { 2986 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 2987 2988 switch (subtype) { 2989 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2990 /* do nothing: hardware answers probe request XXX */ 2991 break; 2992 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2993 case IEEE80211_FC0_SUBTYPE_BEACON: 2994 rtw_recv_beacon(sc, m, ni, subtype, rssi, rstamp); 2995 break; 2996 default: 2997 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2998 break; 2999 } 3000 return; 3001 } 3002 3003 static struct ieee80211_node * 3004 rtw_node_alloc(struct ieee80211com *ic) 3005 { 3006 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 3007 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 3008 3009 DPRINTF(sc, RTW_DEBUG_NODE, 3010 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3011 return ni; 3012 } 3013 3014 static void 3015 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 3016 { 3017 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 3018 3019 DPRINTF(sc, RTW_DEBUG_NODE, 3020 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3021 ether_sprintf(ni->ni_bssid))); 3022 (*sc->sc_mtbl.mt_node_free)(ic, ni); 3023 } 3024 3025 static int 3026 rtw_media_change(struct ifnet *ifp) 3027 { 3028 int error; 3029 3030 error = ieee80211_media_change(ifp); 3031 if (error == ENETRESET) { 3032 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3033 (IFF_RUNNING|IFF_UP)) 3034 rtw_init(ifp); /* XXX lose error */ 3035 error = 0; 3036 } 3037 return error; 3038 } 3039 3040 static void 3041 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3042 { 3043 struct rtw_softc *sc = ifp->if_softc; 3044 3045 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3046 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3047 imr->ifm_status = 0; 3048 return; 3049 } 3050 ieee80211_media_status(ifp, imr); 3051 } 3052 3053 void 3054 rtw_power(int why, void *arg) 3055 { 3056 struct rtw_softc *sc = arg; 3057 struct ifnet *ifp = &sc->sc_ic.ic_if; 3058 int s; 3059 3060 DPRINTF(sc, RTW_DEBUG_PWR, 3061 ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3062 3063 s = splnet(); 3064 switch (why) { 3065 case PWR_STANDBY: 3066 /* XXX do nothing. */ 3067 break; 3068 case PWR_SUSPEND: 3069 rtw_stop(ifp, 0); 3070 if (sc->sc_power != NULL) 3071 (*sc->sc_power)(sc, why); 3072 break; 3073 case PWR_RESUME: 3074 if (ifp->if_flags & IFF_UP) { 3075 if (sc->sc_power != NULL) 3076 (*sc->sc_power)(sc, why); 3077 rtw_init(ifp); 3078 } 3079 break; 3080 case PWR_SOFTSUSPEND: 3081 case PWR_SOFTSTANDBY: 3082 case PWR_SOFTRESUME: 3083 break; 3084 } 3085 splx(s); 3086 } 3087 3088 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 3089 void 3090 rtw_shutdown(void *arg) 3091 { 3092 struct rtw_softc *sc = arg; 3093 3094 rtw_stop(&sc->sc_ic.ic_if, 1); 3095 } 3096 3097 static __inline void 3098 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3099 { 3100 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3101 ifp->if_softc = softc; 3102 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3103 IFF_NOTRAILERS; 3104 ifp->if_ioctl = rtw_ioctl; 3105 ifp->if_start = rtw_start; 3106 ifp->if_watchdog = rtw_watchdog; 3107 ifp->if_init = rtw_init; 3108 ifp->if_stop = rtw_stop; 3109 } 3110 3111 static __inline void 3112 rtw_set80211props(struct ieee80211com *ic) 3113 { 3114 int nrate; 3115 ic->ic_phytype = IEEE80211_T_DS; 3116 ic->ic_opmode = IEEE80211_M_STA; 3117 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3118 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 3119 3120 nrate = 0; 3121 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3122 IEEE80211_RATE_BASIC | 2; 3123 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3124 IEEE80211_RATE_BASIC | 4; 3125 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3126 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3127 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3128 } 3129 3130 static __inline void 3131 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3132 { 3133 mtbl->mt_newstate = ic->ic_newstate; 3134 ic->ic_newstate = rtw_newstate; 3135 3136 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3137 ic->ic_recv_mgmt = rtw_recv_mgmt; 3138 3139 mtbl->mt_node_free = ic->ic_node_free; 3140 ic->ic_node_free = rtw_node_free; 3141 3142 mtbl->mt_node_alloc = ic->ic_node_alloc; 3143 ic->ic_node_alloc = rtw_node_alloc; 3144 } 3145 3146 static __inline void 3147 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 3148 void *arg) 3149 { 3150 /* 3151 * Make sure the interface is shutdown during reboot. 3152 */ 3153 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 3154 if (hooks->rh_shutdown == NULL) 3155 printf("%s: WARNING: unable to establish shutdown hook\n", 3156 dvname); 3157 3158 /* 3159 * Add a suspend hook to make sure we come back up after a 3160 * resume. 3161 */ 3162 hooks->rh_power = powerhook_establish(rtw_power, arg); 3163 if (hooks->rh_power == NULL) 3164 printf("%s: WARNING: unable to establish power hook\n", 3165 dvname); 3166 } 3167 3168 static __inline void 3169 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 3170 void *arg) 3171 { 3172 if (hooks->rh_shutdown != NULL) 3173 shutdownhook_disestablish(hooks->rh_shutdown); 3174 3175 if (hooks->rh_power != NULL) 3176 powerhook_disestablish(hooks->rh_power); 3177 } 3178 3179 static __inline void 3180 rtw_init_radiotap(struct rtw_softc *sc) 3181 { 3182 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3183 sc->sc_rxtap.rr_ihdr.it_len = sizeof(sc->sc_rxtapu); 3184 sc->sc_rxtap.rr_ihdr.it_present = RTW_RX_RADIOTAP_PRESENT; 3185 3186 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3187 sc->sc_txtap.rt_ihdr.it_len = sizeof(sc->sc_txtapu); 3188 sc->sc_txtap.rt_ihdr.it_present = RTW_TX_RADIOTAP_PRESENT; 3189 } 3190 3191 static int 3192 rtw_txctl_blk_setup(struct rtw_txctl_blk *stc, u_int qlen) 3193 { 3194 SIMPLEQ_INIT(&stc->stc_dirtyq); 3195 SIMPLEQ_INIT(&stc->stc_freeq); 3196 stc->stc_ndesc = qlen; 3197 stc->stc_desc = malloc(qlen * sizeof(*stc->stc_desc), M_DEVBUF, 3198 M_NOWAIT); 3199 if (stc->stc_desc == NULL) 3200 return ENOMEM; 3201 return 0; 3202 } 3203 3204 static void 3205 rtw_txctl_blk_cleanup_all(struct rtw_softc *sc) 3206 { 3207 int pri; 3208 struct rtw_txctl_blk *stc; 3209 3210 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3211 stc = &sc->sc_txctl_blk[pri]; 3212 free(stc->stc_desc, M_DEVBUF); 3213 stc->stc_desc = NULL; 3214 } 3215 } 3216 3217 static int 3218 rtw_txctl_blk_setup_all(struct rtw_softc *sc) 3219 { 3220 int pri, rc = 0; 3221 int qlen[RTW_NTXPRI] = 3222 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3223 3224 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3225 rc = rtw_txctl_blk_setup(&sc->sc_txctl_blk[pri], qlen[pri]); 3226 if (rc != 0) 3227 break; 3228 } 3229 return rc; 3230 } 3231 3232 static void 3233 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *htc, struct rtw_txdesc *desc, 3234 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3235 { 3236 htc->htc_ndesc = ndesc; 3237 htc->htc_desc = desc; 3238 htc->htc_physbase = physbase; 3239 htc->htc_ofs = ofs; 3240 3241 (void)memset(htc->htc_desc, 0, 3242 sizeof(htc->htc_desc[0]) * htc->htc_ndesc); 3243 3244 rtw_txdesc_blk_reset(htc); 3245 } 3246 3247 static void 3248 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3249 { 3250 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3251 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3252 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3253 3254 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3255 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3256 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3257 3258 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3259 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3260 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3261 3262 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3263 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3264 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3265 } 3266 3267 static struct rtw_rf * 3268 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, 3269 rtw_rf_write_t rf_write, int digphy) 3270 { 3271 struct rtw_rf *rf; 3272 3273 switch (rfchipid) { 3274 case RTW_RFCHIPID_MAXIM: 3275 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3276 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3277 break; 3278 case RTW_RFCHIPID_PHILIPS: 3279 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3280 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3281 break; 3282 case RTW_RFCHIPID_RFMD: 3283 /* XXX RFMD has no RF constructor */ 3284 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3285 /*FALLTHROUGH*/ 3286 default: 3287 return NULL; 3288 } 3289 rf->rf_continuous_tx_cb = 3290 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3291 rf->rf_continuous_tx_arg = (void *)sc; 3292 return rf; 3293 } 3294 3295 /* Revision C and later use a different PHY delay setting than 3296 * revisions A and B. 3297 */ 3298 static u_int8_t 3299 rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0) 3300 { 3301 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3302 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3303 3304 u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 3305 3306 RTW_WRITE(regs, RTW_RCR, REVAB); 3307 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3308 RTW_WRITE(regs, RTW_RCR, REVC); 3309 3310 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3311 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3312 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3313 3314 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 3315 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3316 3317 return phydelay; 3318 #undef REVC 3319 } 3320 3321 void 3322 rtw_attach(struct rtw_softc *sc) 3323 { 3324 rtw_rf_write_t rf_write; 3325 struct rtw_txctl_blk *stc; 3326 int pri, rc, vers; 3327 3328 #if 0 3329 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_txdesc) == 0, 3330 "RTW_DESC_ALIGNMENT is not a multiple of " 3331 "sizeof(struct rtw_txdesc)"); 3332 3333 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_rxdesc) == 0, 3334 "RTW_DESC_ALIGNMENT is not a multiple of " 3335 "sizeof(struct rtw_rxdesc)"); 3336 3337 CASSERT(RTW_DESC_ALIGNMENT % RTW_MAXPKTSEGS == 0, 3338 "RTW_DESC_ALIGNMENT is not a multiple of RTW_MAXPKTSEGS"); 3339 #endif 3340 3341 NEXT_ATTACH_STATE(sc, DETACHED); 3342 3343 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3344 case RTW_TCR_HWVERID_F: 3345 vers = 'F'; 3346 rf_write = rtw_rf_hostwrite; 3347 break; 3348 case RTW_TCR_HWVERID_D: 3349 vers = 'D'; 3350 if (rtw_host_rfio) 3351 rf_write = rtw_rf_hostwrite; 3352 else 3353 rf_write = rtw_rf_macwrite; 3354 break; 3355 default: 3356 vers = '?'; 3357 rf_write = rtw_rf_macwrite; 3358 break; 3359 } 3360 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, vers); 3361 3362 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3363 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3364 0); 3365 3366 if (rc != 0) { 3367 printf("%s: could not allocate hw descriptors, error %d\n", 3368 sc->sc_dev.dv_xname, rc); 3369 goto err; 3370 } 3371 3372 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3373 3374 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3375 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3376 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3377 3378 if (rc != 0) { 3379 printf("%s: could not map hw descriptors, error %d\n", 3380 sc->sc_dev.dv_xname, rc); 3381 goto err; 3382 } 3383 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3384 3385 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3386 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3387 3388 if (rc != 0) { 3389 printf("%s: could not create DMA map for hw descriptors, " 3390 "error %d\n", sc->sc_dev.dv_xname, rc); 3391 goto err; 3392 } 3393 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3394 3395 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3396 sizeof(struct rtw_descs), NULL, 0); 3397 3398 if (rc != 0) { 3399 printf("%s: could not load DMA map for hw descriptors, " 3400 "error %d\n", sc->sc_dev.dv_xname, rc); 3401 goto err; 3402 } 3403 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3404 3405 if (rtw_txctl_blk_setup_all(sc) != 0) 3406 goto err; 3407 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3408 3409 rtw_txdesc_blk_setup_all(sc); 3410 3411 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3412 3413 sc->sc_rxdesc = &sc->sc_descs->hd_rx[0]; 3414 3415 rtw_rxctls_setup(&sc->sc_rxctl[0]); 3416 3417 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3418 stc = &sc->sc_txctl_blk[pri]; 3419 3420 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3421 &stc->stc_desc[0], stc->stc_ndesc)) != 0) { 3422 printf("%s: could not load DMA map for " 3423 "hw tx descriptors, error %d\n", 3424 sc->sc_dev.dv_xname, rc); 3425 goto err; 3426 } 3427 } 3428 3429 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3430 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxctl[0], 3431 RTW_RXQLEN)) != 0) { 3432 printf("%s: could not load DMA map for hw rx descriptors, " 3433 "error %d\n", sc->sc_dev.dv_xname, rc); 3434 goto err; 3435 } 3436 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3437 3438 /* Reset the chip to a known state. */ 3439 if (rtw_reset(sc) != 0) 3440 goto err; 3441 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3442 3443 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3444 3445 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3446 sc->sc_flags |= RTW_F_9356SROM; 3447 3448 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3449 sc->sc_dev.dv_xname) != 0) 3450 goto err; 3451 3452 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3453 3454 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3455 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3456 sc->sc_dev.dv_xname) != 0) { 3457 printf("%s: attach failed, malformed serial ROM\n", 3458 sc->sc_dev.dv_xname); 3459 goto err; 3460 } 3461 3462 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 3463 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 3464 3465 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 3466 3467 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3468 3469 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, rf_write, 3470 sc->sc_flags & RTW_F_DIGPHY); 3471 3472 if (sc->sc_rf == NULL) { 3473 printf("%s: attach failed, could not attach RF\n", 3474 sc->sc_dev.dv_xname); 3475 goto err; 3476 } 3477 3478 #if 0 3479 if (rtw_identify_rf(&sc->sc_regs, &sc->sc_rftype, 3480 sc->sc_dev.dv_xname) != 0) { 3481 printf("%s: attach failed, unknown RF unidentified\n", 3482 sc->sc_dev.dv_xname); 3483 goto err; 3484 } 3485 #endif 3486 3487 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3488 3489 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 3490 3491 RTW_DPRINTF(RTW_DEBUG_ATTACH, 3492 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 3493 3494 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 3495 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 3496 sc->sc_dev.dv_xname); 3497 3498 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 3499 sc->sc_dev.dv_xname); 3500 3501 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 3502 sc->sc_dev.dv_xname) != 0) 3503 goto err; 3504 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 3505 3506 rtw_setifprops(&sc->sc_if, sc->sc_dev.dv_xname, (void*)sc); 3507 3508 IFQ_SET_READY(&sc->sc_if.if_snd); 3509 3510 rtw_set80211props(&sc->sc_ic); 3511 3512 /* 3513 * Call MI attach routines. 3514 */ 3515 if_attach(&sc->sc_if); 3516 ieee80211_ifattach(&sc->sc_if); 3517 3518 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 3519 3520 /* possibly we should fill in our own sc_send_prresp, since 3521 * the RTL8180 is probably sending probe responses in ad hoc 3522 * mode. 3523 */ 3524 3525 /* complete initialization */ 3526 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 3527 callout_init(&sc->sc_scan_ch); 3528 3529 #if NBPFILTER > 0 3530 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 3531 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 3532 #endif 3533 3534 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 3535 3536 rtw_init_radiotap(sc); 3537 3538 NEXT_ATTACH_STATE(sc, FINISHED); 3539 3540 return; 3541 err: 3542 rtw_detach(sc); 3543 return; 3544 } 3545 3546 int 3547 rtw_detach(struct rtw_softc *sc) 3548 { 3549 int pri; 3550 3551 switch (sc->sc_attach_state) { 3552 case FINISHED: 3553 rtw_stop(&sc->sc_if, 1); 3554 3555 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 3556 (void*)sc); 3557 callout_stop(&sc->sc_scan_ch); 3558 ieee80211_ifdetach(&sc->sc_if); 3559 if_detach(&sc->sc_if); 3560 break; 3561 case FINISH_ID_STA: 3562 case FINISH_RF_ATTACH: 3563 rtw_rf_destroy(sc->sc_rf); 3564 sc->sc_rf = NULL; 3565 /*FALLTHROUGH*/ 3566 case FINISH_PARSE_SROM: 3567 case FINISH_READ_SROM: 3568 rtw_srom_free(&sc->sc_srom); 3569 /*FALLTHROUGH*/ 3570 case FINISH_RESET: 3571 case FINISH_RXMAPS_CREATE: 3572 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxctl[0], 3573 RTW_RXQLEN); 3574 /*FALLTHROUGH*/ 3575 case FINISH_TXMAPS_CREATE: 3576 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3577 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 3578 sc->sc_txctl_blk[pri].stc_desc, 3579 sc->sc_txctl_blk[pri].stc_ndesc); 3580 } 3581 /*FALLTHROUGH*/ 3582 case FINISH_TXDESCBLK_SETUP: 3583 case FINISH_TXCTLBLK_SETUP: 3584 rtw_txctl_blk_cleanup_all(sc); 3585 /*FALLTHROUGH*/ 3586 case FINISH_DESCMAP_LOAD: 3587 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 3588 /*FALLTHROUGH*/ 3589 case FINISH_DESCMAP_CREATE: 3590 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 3591 /*FALLTHROUGH*/ 3592 case FINISH_DESC_MAP: 3593 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 3594 sizeof(struct rtw_descs)); 3595 /*FALLTHROUGH*/ 3596 case FINISH_DESC_ALLOC: 3597 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 3598 sc->sc_desc_nsegs); 3599 /*FALLTHROUGH*/ 3600 case DETACHED: 3601 NEXT_ATTACH_STATE(sc, DETACHED); 3602 break; 3603 } 3604 return 0; 3605 } 3606 3607 int 3608 rtw_activate(struct device *self, enum devact act) 3609 { 3610 struct rtw_softc *sc = (struct rtw_softc *)self; 3611 int rc = 0, s; 3612 3613 s = splnet(); 3614 switch (act) { 3615 case DVACT_ACTIVATE: 3616 rc = EOPNOTSUPP; 3617 break; 3618 3619 case DVACT_DEACTIVATE: 3620 if_deactivate(&sc->sc_ic.ic_if); 3621 break; 3622 } 3623 splx(s); 3624 return rc; 3625 } 3626
Indexes created Mon Sep 29 21:09:56 GMT 2025