rtw.c revision 1.3
1 /* $NetBSD: rtw.c,v 1.3 2004/12/12 06:37:59 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.3 2004/12/12 06:37:59 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #if 0 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 #endif 53 #include <sys/time.h> 54 #include <sys/types.h> 55 56 #include <machine/endian.h> 57 #include <machine/bus.h> 58 #include <machine/intr.h> /* splnet */ 59 60 #include <uvm/uvm_extern.h> 61 62 #include <net/if.h> 63 #include <net/if_media.h> 64 #include <net/if_ether.h> 65 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_compat.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <dev/ic/rtwreg.h> 75 #include <dev/ic/rtwvar.h> 76 #include <dev/ic/rtwphyio.h> 77 #include <dev/ic/rtwphy.h> 78 79 #include <dev/ic/smc93cx6var.h> 80 81 #define KASSERT2(__cond, __msg) \ 82 do { \ 83 if (!(__cond)) \ 84 panic __msg ; \ 85 } while (0) 86 87 #ifdef RTW_DEBUG 88 int rtw_debug = 2; 89 #endif /* RTW_DEBUG */ 90 91 #define NEXT_ATTACH_STATE(sc, state) do { \ 92 DPRINTF(sc, ("%s: attach state %s\n", __func__, #state)); \ 93 sc->sc_attach_state = state; \ 94 } while (0) 95 96 int rtw_dwelltime = 1000; /* milliseconds */ 97 98 #ifdef RTW_DEBUG 99 static void 100 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 101 { 102 #define PRINTREG32(sc, reg) \ 103 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 104 dvname, reg, RTW_READ(regs, reg))) 105 106 #define PRINTREG16(sc, reg) \ 107 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %04x\n", \ 108 dvname, reg, RTW_READ16(regs, reg))) 109 110 #define PRINTREG8(sc, reg) \ 111 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %02x\n", \ 112 dvname, reg, RTW_READ8(regs, reg))) 113 114 RTW_DPRINTF2(("%s: %s\n", dvname, where)); 115 116 PRINTREG32(regs, RTW_IDR0); 117 PRINTREG32(regs, RTW_IDR1); 118 PRINTREG32(regs, RTW_MAR0); 119 PRINTREG32(regs, RTW_MAR1); 120 PRINTREG32(regs, RTW_TSFTRL); 121 PRINTREG32(regs, RTW_TSFTRH); 122 PRINTREG32(regs, RTW_TLPDA); 123 PRINTREG32(regs, RTW_TNPDA); 124 PRINTREG32(regs, RTW_THPDA); 125 PRINTREG32(regs, RTW_TCR); 126 PRINTREG32(regs, RTW_RCR); 127 PRINTREG32(regs, RTW_TINT); 128 PRINTREG32(regs, RTW_TBDA); 129 PRINTREG32(regs, RTW_ANAPARM); 130 PRINTREG32(regs, RTW_BB); 131 PRINTREG32(regs, RTW_PHYCFG); 132 PRINTREG32(regs, RTW_WAKEUP0L); 133 PRINTREG32(regs, RTW_WAKEUP0H); 134 PRINTREG32(regs, RTW_WAKEUP1L); 135 PRINTREG32(regs, RTW_WAKEUP1H); 136 PRINTREG32(regs, RTW_WAKEUP2LL); 137 PRINTREG32(regs, RTW_WAKEUP2LH); 138 PRINTREG32(regs, RTW_WAKEUP2HL); 139 PRINTREG32(regs, RTW_WAKEUP2HH); 140 PRINTREG32(regs, RTW_WAKEUP3LL); 141 PRINTREG32(regs, RTW_WAKEUP3LH); 142 PRINTREG32(regs, RTW_WAKEUP3HL); 143 PRINTREG32(regs, RTW_WAKEUP3HH); 144 PRINTREG32(regs, RTW_WAKEUP4LL); 145 PRINTREG32(regs, RTW_WAKEUP4LH); 146 PRINTREG32(regs, RTW_WAKEUP4HL); 147 PRINTREG32(regs, RTW_WAKEUP4HH); 148 PRINTREG32(regs, RTW_DK0); 149 PRINTREG32(regs, RTW_DK1); 150 PRINTREG32(regs, RTW_DK2); 151 PRINTREG32(regs, RTW_DK3); 152 PRINTREG32(regs, RTW_RETRYCTR); 153 PRINTREG32(regs, RTW_RDSAR); 154 PRINTREG32(regs, RTW_FER); 155 PRINTREG32(regs, RTW_FEMR); 156 PRINTREG32(regs, RTW_FPSR); 157 PRINTREG32(regs, RTW_FFER); 158 159 /* 16-bit registers */ 160 PRINTREG16(regs, RTW_BRSR); 161 PRINTREG16(regs, RTW_IMR); 162 PRINTREG16(regs, RTW_ISR); 163 PRINTREG16(regs, RTW_BCNITV); 164 PRINTREG16(regs, RTW_ATIMWND); 165 PRINTREG16(regs, RTW_BINTRITV); 166 PRINTREG16(regs, RTW_ATIMTRITV); 167 PRINTREG16(regs, RTW_CRC16ERR); 168 PRINTREG16(regs, RTW_CRC0); 169 PRINTREG16(regs, RTW_CRC1); 170 PRINTREG16(regs, RTW_CRC2); 171 PRINTREG16(regs, RTW_CRC3); 172 PRINTREG16(regs, RTW_CRC4); 173 PRINTREG16(regs, RTW_CWR); 174 175 /* 8-bit registers */ 176 PRINTREG8(regs, RTW_CR); 177 PRINTREG8(regs, RTW_9346CR); 178 PRINTREG8(regs, RTW_CONFIG0); 179 PRINTREG8(regs, RTW_CONFIG1); 180 PRINTREG8(regs, RTW_CONFIG2); 181 PRINTREG8(regs, RTW_MSR); 182 PRINTREG8(regs, RTW_CONFIG3); 183 PRINTREG8(regs, RTW_CONFIG4); 184 PRINTREG8(regs, RTW_TESTR); 185 PRINTREG8(regs, RTW_PSR); 186 PRINTREG8(regs, RTW_SCR); 187 PRINTREG8(regs, RTW_PHYDELAY); 188 PRINTREG8(regs, RTW_CRCOUNT); 189 PRINTREG8(regs, RTW_PHYADDR); 190 PRINTREG8(regs, RTW_PHYDATAW); 191 PRINTREG8(regs, RTW_PHYDATAR); 192 PRINTREG8(regs, RTW_CONFIG5); 193 PRINTREG8(regs, RTW_TPPOLL); 194 195 PRINTREG16(regs, RTW_BSSID16); 196 PRINTREG32(regs, RTW_BSSID32); 197 #undef PRINTREG32 198 #undef PRINTREG16 199 #undef PRINTREG8 200 } 201 #endif /* RTW_DEBUG */ 202 203 void 204 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 205 { 206 struct rtw_regs *regs = &sc->sc_regs; 207 208 u_int32_t tcr; 209 tcr = RTW_READ(regs, RTW_TCR); 210 tcr &= ~RTW_TCR_LBK_MASK; 211 if (enable) 212 tcr |= RTW_TCR_LBK_CONT; 213 else 214 tcr |= RTW_TCR_LBK_NORMAL; 215 RTW_WRITE(regs, RTW_TCR, tcr); 216 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 217 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 218 rtw_txdac_enable(regs, !enable); 219 #if 0 220 /* XXX voodoo. from linux. */ 221 rtw_anaparm_enable(regs, 1); 222 rtw_anaparm_enable(regs, 0); 223 #endif 224 rtw_set_access(sc, RTW_ACCESS_NONE); 225 } 226 227 static const char * 228 rtw_access_string(enum rtw_access access) 229 { 230 switch (access) { 231 case RTW_ACCESS_NONE: 232 return "none"; 233 case RTW_ACCESS_CONFIG: 234 return "config"; 235 case RTW_ACCESS_ANAPARM: 236 return "anaparm"; 237 default: 238 return "unknown"; 239 } 240 } 241 242 static void 243 rtw_set_access1(struct rtw_regs *regs, 244 enum rtw_access oaccess, enum rtw_access naccess) 245 { 246 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 247 KASSERT(oaccess >= RTW_ACCESS_NONE && oaccess <= RTW_ACCESS_ANAPARM); 248 249 if (naccess == oaccess) 250 return; 251 252 switch (naccess) { 253 case RTW_ACCESS_NONE: 254 switch (oaccess) { 255 case RTW_ACCESS_ANAPARM: 256 rtw_anaparm_enable(regs, 0); 257 /*FALLTHROUGH*/ 258 case RTW_ACCESS_CONFIG: 259 rtw_config0123_enable(regs, 0); 260 /*FALLTHROUGH*/ 261 case RTW_ACCESS_NONE: 262 break; 263 } 264 break; 265 case RTW_ACCESS_CONFIG: 266 switch (oaccess) { 267 case RTW_ACCESS_NONE: 268 rtw_config0123_enable(regs, 1); 269 /*FALLTHROUGH*/ 270 case RTW_ACCESS_CONFIG: 271 break; 272 case RTW_ACCESS_ANAPARM: 273 rtw_anaparm_enable(regs, 0); 274 break; 275 } 276 break; 277 case RTW_ACCESS_ANAPARM: 278 switch (oaccess) { 279 case RTW_ACCESS_NONE: 280 rtw_config0123_enable(regs, 1); 281 /*FALLTHROUGH*/ 282 case RTW_ACCESS_CONFIG: 283 rtw_anaparm_enable(regs, 1); 284 /*FALLTHROUGH*/ 285 case RTW_ACCESS_ANAPARM: 286 break; 287 } 288 break; 289 } 290 } 291 292 void 293 rtw_set_access(struct rtw_softc *sc, enum rtw_access access) 294 { 295 rtw_set_access1(&sc->sc_regs, sc->sc_access, access); 296 RTW_DPRINTF(("%s: access %s -> %s\n", sc->sc_dev.dv_xname, 297 rtw_access_string(sc->sc_access), 298 rtw_access_string(access))); 299 sc->sc_access = access; 300 } 301 302 /* 303 * Enable registers, switch register banks. 304 */ 305 void 306 rtw_config0123_enable(struct rtw_regs *regs, int enable) 307 { 308 u_int8_t ecr; 309 ecr = RTW_READ8(regs, RTW_9346CR); 310 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 311 if (enable) 312 ecr |= RTW_9346CR_EEM_CONFIG; 313 else 314 ecr |= RTW_9346CR_EEM_NORMAL; 315 RTW_WRITE8(regs, RTW_9346CR, ecr); 316 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 317 } 318 319 /* requires rtw_config0123_enable(, 1) */ 320 void 321 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 322 { 323 u_int8_t cfg3; 324 325 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 326 cfg3 |= RTW_CONFIG3_CLKRUNEN; 327 if (enable) 328 cfg3 |= RTW_CONFIG3_PARMEN; 329 else 330 cfg3 &= ~RTW_CONFIG3_PARMEN; 331 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 332 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 333 } 334 335 /* requires rtw_anaparm_enable(, 1) */ 336 void 337 rtw_txdac_enable(struct rtw_regs *regs, int enable) 338 { 339 u_int32_t anaparm; 340 341 anaparm = RTW_READ(regs, RTW_ANAPARM); 342 if (enable) 343 anaparm &= ~RTW_ANAPARM_TXDACOFF; 344 else 345 anaparm |= RTW_ANAPARM_TXDACOFF; 346 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 347 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 348 } 349 350 static __inline int 351 rtw_chip_reset1(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 352 { 353 u_int8_t cr; 354 int i; 355 356 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 357 358 RTW_WBR(regs, RTW_CR, RTW_CR); 359 360 for (i = 0; i < 10000; i++) { 361 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 362 RTW_DPRINTF(("%s: reset in %dus\n", *dvname, i)); 363 return 0; 364 } 365 RTW_RBR(regs, RTW_CR, RTW_CR); 366 DELAY(1); /* 1us */ 367 } 368 369 printf("%s: reset failed\n", *dvname); 370 return ETIMEDOUT; 371 } 372 373 static __inline int 374 rtw_chip_reset(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 375 { 376 uint32_t tcr; 377 378 /* from Linux driver */ 379 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 380 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 381 382 RTW_WRITE(regs, RTW_TCR, tcr); 383 384 RTW_WBW(regs, RTW_CR, RTW_TCR); 385 386 return rtw_chip_reset1(regs, dvname); 387 } 388 389 static __inline int 390 rtw_recall_eeprom(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 391 { 392 int i; 393 u_int8_t ecr; 394 395 ecr = RTW_READ8(regs, RTW_9346CR); 396 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 397 RTW_WRITE8(regs, RTW_9346CR, ecr); 398 399 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 400 401 /* wait 2.5ms for completion */ 402 for (i = 0; i < 25; i++) { 403 ecr = RTW_READ8(regs, RTW_9346CR); 404 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 405 RTW_DPRINTF(("%s: recall EEPROM in %dus\n", *dvname, 406 i * 100)); 407 return 0; 408 } 409 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 410 DELAY(100); 411 } 412 printf("%s: recall EEPROM failed\n", *dvname); 413 return ETIMEDOUT; 414 } 415 416 static __inline int 417 rtw_reset(struct rtw_softc *sc) 418 { 419 int rc; 420 uint32_t config1; 421 422 if ((rc = rtw_chip_reset(&sc->sc_regs, &sc->sc_dev.dv_xname)) != 0) 423 return rc; 424 425 if ((rc = rtw_recall_eeprom(&sc->sc_regs, &sc->sc_dev.dv_xname)) != 0) 426 ; 427 428 config1 = RTW_READ(&sc->sc_regs, RTW_CONFIG1); 429 RTW_WRITE(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 430 /* TBD turn off maximum power saving? */ 431 432 return 0; 433 } 434 435 static __inline int 436 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txctl *descs, 437 u_int ndescs) 438 { 439 int i, rc = 0; 440 for (i = 0; i < ndescs; i++) { 441 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 442 0, 0, &descs[i].stx_dmamap); 443 if (rc != 0) 444 break; 445 } 446 return rc; 447 } 448 449 static __inline int 450 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 451 u_int ndescs) 452 { 453 int i, rc = 0; 454 for (i = 0; i < ndescs; i++) { 455 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 456 &descs[i].srx_dmamap); 457 if (rc != 0) 458 break; 459 } 460 return rc; 461 } 462 463 static __inline void 464 rtw_rxctls_setup(struct rtw_rxctl *descs) 465 { 466 int i; 467 for (i = 0; i < RTW_RXQLEN; i++) 468 descs[i].srx_mbuf = NULL; 469 } 470 471 static __inline void 472 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 473 u_int ndescs) 474 { 475 int i; 476 for (i = 0; i < ndescs; i++) { 477 if (descs[i].srx_dmamap != NULL) 478 bus_dmamap_destroy(dmat, descs[i].srx_dmamap); 479 } 480 } 481 482 static __inline void 483 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txctl *descs, 484 u_int ndescs) 485 { 486 int i; 487 for (i = 0; i < ndescs; i++) { 488 if (descs[i].stx_dmamap != NULL) 489 bus_dmamap_destroy(dmat, descs[i].stx_dmamap); 490 } 491 } 492 493 static __inline void 494 rtw_srom_free(struct rtw_srom *sr) 495 { 496 sr->sr_size = 0; 497 if (sr->sr_content == NULL) 498 return; 499 free(sr->sr_content, M_DEVBUF); 500 sr->sr_content = NULL; 501 } 502 503 static void 504 rtw_srom_defaults(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 505 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, char (*dvname)[IFNAMSIZ]) 506 { 507 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 508 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 509 *rcr |= RTW_RCR_ENCS1; 510 *rfchipid = RTW_RFCHIPID_PHILIPS; 511 } 512 513 static int 514 rtw_srom_parse(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 515 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, enum rtw_locale *locale, 516 char (*dvname)[IFNAMSIZ]) 517 { 518 int i; 519 const char *rfname, *paname; 520 char scratch[sizeof("unknown 0xXX")]; 521 u_int16_t version; 522 u_int8_t mac[IEEE80211_ADDR_LEN]; 523 524 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 525 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 526 527 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 528 printf("%s: SROM version %d.%d", *dvname, version >> 8, version & 0xff); 529 530 if (version <= 0x0101) { 531 printf(" is not understood, limping along with defaults\n"); 532 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr, 533 dvname); 534 return 0; 535 } 536 printf("\n"); 537 538 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 539 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 540 541 RTW_DPRINTF(("%s: EEPROM MAC %s\n", *dvname, ether_sprintf(mac))); 542 543 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 544 545 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 546 *flags |= RTW_F_ANTDIV; 547 548 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) != 0) 549 *flags |= RTW_F_DIGPHY; 550 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 551 *flags |= RTW_F_DFLANTB; 552 553 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 554 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 555 556 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 557 switch (*rfchipid) { 558 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 559 rfname = "GCT GRF5101"; 560 paname = "Winspring WS9901"; 561 break; 562 case RTW_RFCHIPID_MAXIM: 563 rfname = "Maxim MAX2820"; /* guess */ 564 paname = "Maxim MAX2422"; /* guess */ 565 break; 566 case RTW_RFCHIPID_INTERSIL: 567 rfname = "Intersil HFA3873"; /* guess */ 568 paname = "Intersil <unknown>"; 569 break; 570 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 571 rfname = "Philips SA2400A"; 572 paname = "Philips SA2411"; 573 break; 574 case RTW_RFCHIPID_RFMD: 575 /* this is the same front-end as an atw(4)! */ 576 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 577 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 578 "SYN: Silicon Labs Si4126"; /* inferred from 579 * reference driver 580 */ 581 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 582 break; 583 case RTW_RFCHIPID_RESERVED: 584 rfname = paname = "reserved"; 585 break; 586 default: 587 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 588 rfname = paname = scratch; 589 } 590 printf("%s: RF: %s, PA: %s\n", *dvname, rfname, paname); 591 592 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 593 case RTW_CONFIG0_GL_USA: 594 *locale = RTW_LOCALE_USA; 595 break; 596 case RTW_CONFIG0_GL_EUROPE: 597 *locale = RTW_LOCALE_EUROPE; 598 break; 599 case RTW_CONFIG0_GL_JAPAN: 600 *locale = RTW_LOCALE_JAPAN; 601 break; 602 default: 603 *locale = RTW_LOCALE_UNKNOWN; 604 break; 605 } 606 return 0; 607 } 608 609 /* Returns -1 on failure. */ 610 static int 611 rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr, 612 char (*dvname)[IFNAMSIZ]) 613 { 614 int rc; 615 struct seeprom_descriptor sd; 616 u_int8_t ecr; 617 618 (void)memset(&sd, 0, sizeof(sd)); 619 620 ecr = RTW_READ8(regs, RTW_9346CR); 621 622 if ((flags & RTW_F_9356SROM) != 0) { 623 RTW_DPRINTF(("%s: 93c56 SROM\n", *dvname)); 624 sr->sr_size = 256; 625 sd.sd_chip = C56_66; 626 } else { 627 RTW_DPRINTF(("%s: 93c46 SROM\n", *dvname)); 628 sr->sr_size = 128; 629 sd.sd_chip = C46; 630 } 631 632 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 633 RTW_9346CR_EEM_MASK); 634 ecr |= RTW_9346CR_EEM_PROGRAM; 635 636 RTW_WRITE8(regs, RTW_9346CR, ecr); 637 638 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 639 640 if (sr->sr_content == NULL) { 641 printf("%s: unable to allocate SROM buffer\n", *dvname); 642 return ENOMEM; 643 } 644 645 (void)memset(sr->sr_content, 0, sr->sr_size); 646 647 /* RTL8180 has a single 8-bit register for controlling the 648 * 93cx6 SROM. There is no "ready" bit. The RTL8180 649 * input/output sense is the reverse of read_seeprom's. 650 */ 651 sd.sd_tag = regs->r_bt; 652 sd.sd_bsh = regs->r_bh; 653 sd.sd_regsize = 1; 654 sd.sd_control_offset = RTW_9346CR; 655 sd.sd_status_offset = RTW_9346CR; 656 sd.sd_dataout_offset = RTW_9346CR; 657 sd.sd_CK = RTW_9346CR_EESK; 658 sd.sd_CS = RTW_9346CR_EECS; 659 sd.sd_DI = RTW_9346CR_EEDO; 660 sd.sd_DO = RTW_9346CR_EEDI; 661 /* make read_seeprom enter EEPROM read/write mode */ 662 sd.sd_MS = ecr; 663 sd.sd_RDY = 0; 664 #if 0 665 sd.sd_clkdelay = 50; 666 #endif 667 668 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 669 printf("%s: could not read SROM\n", *dvname); 670 free(sr->sr_content, M_DEVBUF); 671 sr->sr_content = NULL; 672 return -1; /* XXX */ 673 } 674 675 /* end EEPROM read/write mode */ 676 RTW_WRITE8(regs, RTW_9346CR, 677 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 678 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 679 680 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 681 return rc; 682 683 #ifdef RTW_DEBUG 684 { 685 int i; 686 RTW_DPRINTF(("\n%s: serial ROM:\n\t", *dvname)); 687 for (i = 0; i < sr->sr_size/2; i++) { 688 if (((i % 8) == 0) && (i != 0)) 689 RTW_DPRINTF(("\n\t")); 690 RTW_DPRINTF((" %04x", sr->sr_content[i])); 691 } 692 RTW_DPRINTF(("\n")); 693 } 694 #endif /* RTW_DEBUG */ 695 return 0; 696 } 697 698 #if 0 699 static __inline int 700 rtw_identify_rf(struct rtw_regs *regs, enum rtw_rftype *rftype, 701 char (*dvname)[IFNAMSIZ]) 702 { 703 u_int8_t cfg4; 704 const char *name; 705 706 cfg4 = RTW_READ8(regs, RTW_CONFIG4); 707 708 switch (cfg4 & RTW_CONFIG4_RFTYPE_MASK) { 709 case RTW_CONFIG4_RFTYPE_PHILIPS: 710 *rftype = RTW_RFTYPE_PHILIPS; 711 name = "Philips"; 712 break; 713 case RTW_CONFIG4_RFTYPE_INTERSIL: 714 *rftype = RTW_RFTYPE_INTERSIL; 715 name = "Intersil"; 716 break; 717 case RTW_CONFIG4_RFTYPE_RFMD: 718 *rftype = RTW_RFTYPE_RFMD; 719 name = "RFMD"; 720 break; 721 default: 722 name = "<unknown>"; 723 return ENXIO; 724 } 725 726 printf("%s: RF prog type %s\n", *dvname, name); 727 return 0; 728 } 729 #endif 730 731 static __inline void 732 rtw_init_channels(enum rtw_locale locale, 733 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 734 char (*dvname)[IFNAMSIZ]) 735 { 736 int i; 737 const char *name = NULL; 738 #define ADD_CHANNEL(_chans, _chan) do { \ 739 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 740 (*_chans)[_chan].ic_freq = \ 741 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 742 } while (0) 743 744 switch (locale) { 745 case RTW_LOCALE_USA: /* 1-11 */ 746 name = "USA"; 747 for (i = 1; i <= 11; i++) 748 ADD_CHANNEL(chans, i); 749 break; 750 case RTW_LOCALE_JAPAN: /* 1-14 */ 751 name = "Japan"; 752 ADD_CHANNEL(chans, 14); 753 for (i = 1; i <= 14; i++) 754 ADD_CHANNEL(chans, i); 755 break; 756 case RTW_LOCALE_EUROPE: /* 1-13 */ 757 name = "Europe"; 758 for (i = 1; i <= 13; i++) 759 ADD_CHANNEL(chans, i); 760 break; 761 default: /* 10-11 allowed by most countries */ 762 name = "<unknown>"; 763 for (i = 10; i <= 11; i++) 764 ADD_CHANNEL(chans, i); 765 break; 766 } 767 printf("%s: Geographic Location %s\n", *dvname, name); 768 #undef ADD_CHANNEL 769 } 770 771 static __inline void 772 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 773 char (*dvname)[IFNAMSIZ]) 774 { 775 u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 776 777 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 778 case RTW_CONFIG0_GL_USA: 779 *locale = RTW_LOCALE_USA; 780 break; 781 case RTW_CONFIG0_GL_JAPAN: 782 *locale = RTW_LOCALE_JAPAN; 783 break; 784 case RTW_CONFIG0_GL_EUROPE: 785 *locale = RTW_LOCALE_EUROPE; 786 break; 787 default: 788 *locale = RTW_LOCALE_UNKNOWN; 789 break; 790 } 791 } 792 793 static __inline int 794 rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN], 795 char (*dvname)[IFNAMSIZ]) 796 { 797 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 798 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 799 }; 800 u_int32_t idr0 = RTW_READ(regs, RTW_IDR0), 801 idr1 = RTW_READ(regs, RTW_IDR1); 802 803 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 804 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 805 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 806 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 807 808 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 809 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 810 811 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 812 printf("%s: could not get mac address, attach failed\n", 813 *dvname); 814 return ENXIO; 815 } 816 817 printf("%s: 802.11 address %s\n", *dvname, ether_sprintf(*addr)); 818 819 return 0; 820 } 821 822 static u_int8_t 823 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 824 struct ieee80211_channel *chan) 825 { 826 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 827 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 828 ("%s: channel %d out of range", __func__, 829 idx - RTW_SR_TXPOWER1 + 1)); 830 return RTW_SR_GET(sr, idx); 831 } 832 833 static void 834 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *htcs) 835 { 836 int pri; 837 u_int ndesc[RTW_NTXPRI] = 838 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 839 840 for (pri = 0; pri < RTW_NTXPRI; pri++) { 841 htcs[pri].htc_nfree = ndesc[pri]; 842 htcs[pri].htc_next = 0; 843 } 844 } 845 846 static int 847 rtw_txctl_blk_init(struct rtw_txctl_blk *stc) 848 { 849 int i; 850 struct rtw_txctl *stx; 851 852 SIMPLEQ_INIT(&stc->stc_dirtyq); 853 SIMPLEQ_INIT(&stc->stc_freeq); 854 for (i = 0; i < stc->stc_ndesc; i++) { 855 stx = &stc->stc_desc[i]; 856 stx->stx_mbuf = NULL; 857 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 858 } 859 return 0; 860 } 861 862 static void 863 rtw_txctl_blk_init_all(struct rtw_txctl_blk *stcs) 864 { 865 int pri; 866 for (pri = 0; pri < RTW_NTXPRI; pri++) 867 rtw_txctl_blk_init(&stcs[pri]); 868 } 869 870 static __inline void 871 rtw_rxdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, u_int desc0, u_int 872 nsync, int ops) 873 { 874 /* sync to end of ring */ 875 if (desc0 + nsync > RTW_NRXDESC) { 876 bus_dmamap_sync(dmat, dmap, 877 offsetof(struct rtw_descs, hd_rx[desc0]), 878 sizeof(struct rtw_rxdesc) * (RTW_NRXDESC - desc0), ops); 879 nsync -= (RTW_NRXDESC - desc0); 880 desc0 = 0; 881 } 882 883 /* sync what remains */ 884 bus_dmamap_sync(dmat, dmap, 885 offsetof(struct rtw_descs, hd_rx[desc0]), 886 sizeof(struct rtw_rxdesc) * nsync, ops); 887 } 888 889 static void 890 rtw_txdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, 891 struct rtw_txdesc_blk *htc, u_int desc0, u_int nsync, int ops) 892 { 893 /* sync to end of ring */ 894 if (desc0 + nsync > htc->htc_ndesc) { 895 bus_dmamap_sync(dmat, dmap, 896 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 897 sizeof(struct rtw_txdesc) * (htc->htc_ndesc - desc0), 898 ops); 899 nsync -= (htc->htc_ndesc - desc0); 900 desc0 = 0; 901 } 902 903 /* sync what remains */ 904 bus_dmamap_sync(dmat, dmap, 905 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 906 sizeof(struct rtw_txdesc) * nsync, ops); 907 } 908 909 static void 910 rtw_txdescs_sync_all(bus_dma_tag_t dmat, bus_dmamap_t dmap, 911 struct rtw_txdesc_blk *htcs) 912 { 913 int pri; 914 for (pri = 0; pri < RTW_NTXPRI; pri++) { 915 rtw_txdescs_sync(dmat, dmap, 916 &htcs[pri], 0, htcs[pri].htc_ndesc, 917 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 918 } 919 } 920 921 static void 922 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxctl *desc) 923 { 924 int i; 925 struct rtw_rxctl *srx; 926 927 for (i = 0; i < RTW_NRXDESC; i++) { 928 srx = &desc[i]; 929 bus_dmamap_unload(dmat, srx->srx_dmamap); 930 m_freem(srx->srx_mbuf); 931 srx->srx_mbuf = NULL; 932 } 933 } 934 935 static __inline int 936 rtw_rxbuf_alloc(bus_dma_tag_t dmat, struct rtw_rxctl *srx) 937 { 938 int rc; 939 struct mbuf *m; 940 941 MGETHDR(m, M_DONTWAIT, MT_DATA); 942 if (m == NULL) 943 return ENOMEM; 944 945 MCLGET(m, M_DONTWAIT); 946 if (m == NULL) 947 return ENOMEM; 948 949 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 950 951 rc = bus_dmamap_load_mbuf(dmat, srx->srx_dmamap, m, BUS_DMA_NOWAIT); 952 if (rc != 0) 953 return rc; 954 955 srx->srx_mbuf = m; 956 957 return 0; 958 } 959 960 static int 961 rtw_rxctl_init_all(bus_dma_tag_t dmat, struct rtw_rxctl *desc, 962 u_int *next, char (*dvname)[IFNAMSIZ]) 963 { 964 int i, rc; 965 struct rtw_rxctl *srx; 966 967 for (i = 0; i < RTW_NRXDESC; i++) { 968 srx = &desc[i]; 969 if ((rc = rtw_rxbuf_alloc(dmat, srx)) == 0) 970 continue; 971 printf("%s: failed rtw_rxbuf_alloc after %d buffers, rc = %d\n", 972 *dvname, i, rc); 973 if (i == 0) { 974 rtw_rxbufs_release(dmat, desc); 975 return rc; 976 } 977 } 978 *next = 0; 979 return 0; 980 } 981 982 static __inline void 983 rtw_rxdesc_init(bus_dma_tag_t dmat, bus_dmamap_t dmam, 984 struct rtw_rxdesc *hrx, struct rtw_rxctl *srx, int idx) 985 { 986 int is_last = (idx == RTW_NRXDESC - 1); 987 uint32_t ctl; 988 989 hrx->hrx_buf = htole32(srx->srx_dmamap->dm_segs[0].ds_addr); 990 991 ctl = LSHIFT(srx->srx_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 992 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 993 994 if (is_last) 995 ctl |= RTW_RXCTL_EOR; 996 997 hrx->hrx_ctl = htole32(ctl); 998 999 /* sync the mbuf */ 1000 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, srx->srx_dmamap->dm_mapsize, 1001 BUS_DMASYNC_PREREAD); 1002 1003 /* sync the descriptor */ 1004 bus_dmamap_sync(dmat, dmam, RTW_DESC_OFFSET(hd_rx, idx), 1005 sizeof(struct rtw_rxdesc), 1006 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1007 } 1008 1009 static void 1010 rtw_rxdesc_init_all(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1011 struct rtw_rxdesc *desc, struct rtw_rxctl *ctl) 1012 { 1013 int i; 1014 struct rtw_rxdesc *hrx; 1015 struct rtw_rxctl *srx; 1016 1017 for (i = 0; i < RTW_NRXDESC; i++) { 1018 hrx = &desc[i]; 1019 srx = &ctl[i]; 1020 rtw_rxdesc_init(dmat, dmam, hrx, srx, i); 1021 } 1022 } 1023 1024 static void 1025 rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable) 1026 { 1027 u_int8_t cr; 1028 1029 RTW_DPRINTF(("%s: %s 0x%02x\n", __func__, 1030 enable ? "enable" : "disable", flags)); 1031 1032 cr = RTW_READ8(regs, RTW_CR); 1033 1034 /* XXX reference source does not enable MULRW */ 1035 #if 0 1036 /* enable PCI Read/Write Multiple */ 1037 cr |= RTW_CR_MULRW; 1038 #endif 1039 1040 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1041 if (enable) 1042 cr |= flags; 1043 else 1044 cr &= ~flags; 1045 RTW_WRITE8(regs, RTW_CR, cr); 1046 RTW_SYNC(regs, RTW_CR, RTW_CR); 1047 } 1048 1049 static void 1050 rtw_intr_rx(struct rtw_softc *sc, u_int16_t isr) 1051 { 1052 u_int next; 1053 int rate, rssi; 1054 u_int32_t hrssi, hstat, htsfth, htsftl; 1055 struct rtw_rxdesc *hrx; 1056 struct rtw_rxctl *srx; 1057 struct mbuf *m; 1058 1059 struct ieee80211_node *ni; 1060 struct ieee80211_frame *wh; 1061 1062 for (next = sc->sc_rxnext; ; next = (next + 1) % RTW_RXQLEN) { 1063 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1064 next, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1065 hrx = &sc->sc_rxdesc[next]; 1066 srx = &sc->sc_rxctl[next]; 1067 1068 hstat = le32toh(hrx->hrx_stat); 1069 hrssi = le32toh(hrx->hrx_rssi); 1070 htsfth = le32toh(hrx->hrx_tsfth); 1071 htsftl = le32toh(hrx->hrx_tsftl); 1072 1073 RTW_DPRINTF2(("%s: rxdesc[%d] hstat %#08x hrssi %#08x " 1074 "htsft %#08x%08x\n", __func__, next, 1075 hstat, hrssi, htsfth, htsftl)); 1076 1077 if ((hstat & RTW_RXSTAT_OWN) != 0) /* belongs to NIC */ 1078 break; 1079 1080 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1081 printf("%s: DMA error/FIFO overflow %08x, " 1082 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1083 hstat & RTW_RXSTAT_IOERROR, next); 1084 goto next; 1085 } 1086 1087 switch (hstat & RTW_RXSTAT_RATE_MASK) { 1088 case RTW_RXSTAT_RATE_1MBPS: 1089 rate = 10; 1090 break; 1091 case RTW_RXSTAT_RATE_2MBPS: 1092 rate = 20; 1093 break; 1094 case RTW_RXSTAT_RATE_5MBPS: 1095 rate = 55; 1096 break; 1097 default: 1098 #ifdef RTW_DEBUG 1099 if (rtw_debug > 1) 1100 printf("%s: interpreting rate #%d as 11 MB/s\n", 1101 sc->sc_dev.dv_xname, 1102 MASK_AND_RSHIFT(hstat, 1103 RTW_RXSTAT_RATE_MASK)); 1104 #endif /* RTW_DEBUG */ 1105 /*FALLTHROUGH*/ 1106 case RTW_RXSTAT_RATE_11MBPS: 1107 rate = 110; 1108 break; 1109 } 1110 1111 RTW_DPRINTF2(("%s: rate %d\n", __func__, rate)); 1112 1113 #ifdef RTW_DEBUG 1114 #define PRINTSTAT(flag) do { \ 1115 if ((hstat & flag) != 0) { \ 1116 printf("%s" #flag, delim); \ 1117 delim = ","; \ 1118 } \ 1119 } while (0) 1120 if (rtw_debug > 1) { 1121 const char *delim = "<"; 1122 printf("%s: ", sc->sc_dev.dv_xname); 1123 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1124 printf("status %08x<", hstat); 1125 PRINTSTAT(RTW_RXSTAT_SPLCP); 1126 PRINTSTAT(RTW_RXSTAT_MAR); 1127 PRINTSTAT(RTW_RXSTAT_PAR); 1128 PRINTSTAT(RTW_RXSTAT_BAR); 1129 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1130 PRINTSTAT(RTW_RXSTAT_CRC32); 1131 PRINTSTAT(RTW_RXSTAT_ICV); 1132 printf(">, "); 1133 } 1134 printf("rate %d.%d Mb/s, time %08x%08x\n", 1135 rate / 10, rate % 10, htsfth, htsftl); 1136 } 1137 #endif /* RTW_DEBUG */ 1138 1139 if ((hstat & RTW_RXSTAT_RES) != 0 && 1140 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1141 goto next; 1142 1143 /* if bad flags, skip descriptor */ 1144 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1145 printf("%s: too many rx segments\n", 1146 sc->sc_dev.dv_xname); 1147 goto next; 1148 } 1149 1150 m = srx->srx_mbuf; 1151 1152 /* if temporarily out of memory, re-use mbuf */ 1153 if (rtw_rxbuf_alloc(sc->sc_dmat, srx) != 0) { 1154 printf("%s: rtw_rxbuf_alloc(, %d) failed, " 1155 "dropping this packet\n", sc->sc_dev.dv_xname, 1156 next); 1157 goto next; 1158 } 1159 1160 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1161 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1162 else { 1163 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1164 /* TBD find out each front-end's LNA gain in the 1165 * front-end's units 1166 */ 1167 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1168 rssi |= 0x80; 1169 } 1170 1171 m->m_pkthdr.len = m->m_len = 1172 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1173 m->m_flags |= M_HASFCS; 1174 1175 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 1176 sc->sc_ic.ic_stats.is_rx_tooshort++; 1177 goto next; 1178 } 1179 wh = mtod(m, struct ieee80211_frame *); 1180 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1181 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1182 1183 sc->sc_tsfth = htsfth; 1184 1185 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1186 ieee80211_release_node(&sc->sc_ic, ni); 1187 next: 1188 rtw_rxdesc_init(sc->sc_dmat, sc->sc_desc_dmamap, 1189 hrx, srx, next); 1190 } 1191 sc->sc_rxnext = next; 1192 1193 return; 1194 } 1195 1196 static void 1197 rtw_intr_tx(struct rtw_softc *sc, u_int16_t isr) 1198 { 1199 /* TBD */ 1200 return; 1201 } 1202 1203 static void 1204 rtw_intr_beacon(struct rtw_softc *sc, u_int16_t isr) 1205 { 1206 /* TBD */ 1207 return; 1208 } 1209 1210 static void 1211 rtw_intr_atim(struct rtw_softc *sc) 1212 { 1213 /* TBD */ 1214 return; 1215 } 1216 1217 static void 1218 rtw_hwring_setup(struct rtw_softc *sc) 1219 { 1220 struct rtw_regs *regs = &sc->sc_regs; 1221 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1222 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1223 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1224 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1225 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1226 } 1227 1228 static void 1229 rtw_swring_setup(struct rtw_softc *sc) 1230 { 1231 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1232 1233 rtw_txctl_blk_init_all(&sc->sc_txctl_blk[0]); 1234 1235 rtw_rxctl_init_all(sc->sc_dmat, sc->sc_rxctl, &sc->sc_rxnext, 1236 &sc->sc_dev.dv_xname); 1237 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, 1238 sc->sc_rxdesc, sc->sc_rxctl); 1239 1240 rtw_txdescs_sync_all(sc->sc_dmat, sc->sc_desc_dmamap, 1241 &sc->sc_txdesc_blk[0]); 1242 #if 0 /* redundant with rtw_rxdesc_init_all */ 1243 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1244 0, RTW_NRXDESC, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1245 #endif 1246 } 1247 1248 static void 1249 rtw_kick(struct rtw_softc *sc) 1250 { 1251 struct rtw_regs *regs = &sc->sc_regs; 1252 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1253 RTW_WRITE16(regs, RTW_IMR, 0); 1254 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1255 /* TBD free tx bufs */ 1256 rtw_swring_setup(sc); 1257 rtw_hwring_setup(sc); 1258 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1259 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1260 } 1261 1262 static void 1263 rtw_intr_ioerror(struct rtw_softc *sc, u_int16_t isr) 1264 { 1265 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) { 1266 rtw_kick(sc); 1267 } 1268 if ((isr & RTW_INTR_TXFOVW) != 0) 1269 ; /* TBD restart transmit engine */ 1270 return; 1271 } 1272 1273 static __inline void 1274 rtw_suspend_ticks(struct rtw_softc *sc) 1275 { 1276 printf("%s: suspending ticks\n", sc->sc_dev.dv_xname); 1277 sc->sc_do_tick = 0; 1278 } 1279 1280 static __inline void 1281 rtw_resume_ticks(struct rtw_softc *sc) 1282 { 1283 int s; 1284 struct timeval tv; 1285 u_int32_t tsftrl0, tsftrl1, next_tick; 1286 1287 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1288 1289 s = splclock(); 1290 timersub(&mono_time, &sc->sc_tick0, &tv); 1291 splx(s); 1292 1293 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1294 next_tick = tsftrl1 + 1000000 * (1 + tv.tv_sec) - tv.tv_usec; 1295 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1296 1297 sc->sc_do_tick = 1; 1298 1299 printf("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1300 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick); 1301 } 1302 1303 static void 1304 rtw_intr_timeout(struct rtw_softc *sc) 1305 { 1306 printf("%s: timeout\n", sc->sc_dev.dv_xname); 1307 if (sc->sc_do_tick) 1308 rtw_resume_ticks(sc); 1309 return; 1310 } 1311 1312 int 1313 rtw_intr(void *arg) 1314 { 1315 int i; 1316 struct rtw_softc *sc = arg; 1317 struct rtw_regs *regs = &sc->sc_regs; 1318 u_int16_t isr; 1319 1320 /* 1321 * If the interface isn't running, the interrupt couldn't 1322 * possibly have come from us. 1323 */ 1324 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1325 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1326 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1327 RTW_DPRINTF2(("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1328 return (0); 1329 } 1330 1331 for (i = 0; i < 10; i++) { 1332 isr = RTW_READ16(regs, RTW_ISR); 1333 1334 RTW_WRITE16(regs, RTW_ISR, isr); 1335 1336 if (sc->sc_intr_ack != NULL) 1337 (*sc->sc_intr_ack)(regs); 1338 1339 if (isr == 0) 1340 break; 1341 1342 #ifdef RTW_DEBUG 1343 #define PRINTINTR(flag) do { \ 1344 if ((isr & flag) != 0) { \ 1345 printf("%s" #flag, delim); \ 1346 delim = ","; \ 1347 } \ 1348 } while (0) 1349 1350 if (rtw_debug > 1 && isr != 0) { 1351 const char *delim = "<"; 1352 1353 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1354 1355 PRINTINTR(RTW_INTR_TXFOVW); 1356 PRINTINTR(RTW_INTR_TIMEOUT); 1357 PRINTINTR(RTW_INTR_BCNINT); 1358 PRINTINTR(RTW_INTR_ATIMINT); 1359 PRINTINTR(RTW_INTR_TBDER); 1360 PRINTINTR(RTW_INTR_TBDOK); 1361 PRINTINTR(RTW_INTR_THPDER); 1362 PRINTINTR(RTW_INTR_THPDOK); 1363 PRINTINTR(RTW_INTR_TNPDER); 1364 PRINTINTR(RTW_INTR_TNPDOK); 1365 PRINTINTR(RTW_INTR_RXFOVW); 1366 PRINTINTR(RTW_INTR_RDU); 1367 PRINTINTR(RTW_INTR_TLPDER); 1368 PRINTINTR(RTW_INTR_TLPDOK); 1369 PRINTINTR(RTW_INTR_RER); 1370 PRINTINTR(RTW_INTR_ROK); 1371 1372 printf(">\n"); 1373 } 1374 #undef PRINTINTR 1375 #endif /* RTW_DEBUG */ 1376 1377 if ((isr & RTW_INTR_RX) != 0) 1378 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1379 if ((isr & RTW_INTR_TX) != 0) 1380 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1381 if ((isr & RTW_INTR_BEACON) != 0) 1382 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1383 if ((isr & RTW_INTR_ATIMINT) != 0) 1384 rtw_intr_atim(sc); 1385 if ((isr & RTW_INTR_IOERROR) != 0) 1386 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1387 if ((isr & RTW_INTR_TIMEOUT) != 0) 1388 rtw_intr_timeout(sc); 1389 } 1390 1391 return 1; 1392 } 1393 1394 static void 1395 rtw_stop(struct ifnet *ifp, int disable) 1396 { 1397 int s; 1398 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1399 struct ieee80211com *ic = &sc->sc_ic; 1400 struct rtw_regs *regs = &sc->sc_regs; 1401 1402 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1403 return; 1404 1405 rtw_suspend_ticks(sc); 1406 1407 s = splnet(); 1408 1409 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1410 1411 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1412 /* Disable interrupts. */ 1413 RTW_WRITE16(regs, RTW_IMR, 0); 1414 1415 /* Stop the transmit and receive processes. First stop DMA, 1416 * then disable receiver and transmitter. 1417 */ 1418 RTW_WRITE8(regs, RTW_TPPOLL, 1419 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ| 1420 RTW_TPPOLL_SLPQ); 1421 1422 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1423 } 1424 1425 /* TBD Release transmit buffers. */ 1426 1427 if (disable) { 1428 rtw_disable(sc); 1429 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1430 } 1431 1432 /* Mark the interface as not running. Cancel the watchdog timer. */ 1433 ifp->if_flags &= ~IFF_RUNNING; 1434 ifp->if_timer = 0; 1435 1436 splx(s); 1437 1438 return; 1439 } 1440 1441 const char * 1442 rtw_pwrstate_string(enum rtw_pwrstate power) 1443 { 1444 switch (power) { 1445 case RTW_ON: 1446 return "on"; 1447 case RTW_SLEEP: 1448 return "sleep"; 1449 case RTW_OFF: 1450 return "off"; 1451 default: 1452 return "unknown"; 1453 } 1454 } 1455 1456 /* XXX I am using the RFMD settings gleaned from the reference 1457 * driver. 1458 */ 1459 static void 1460 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1461 int before_rf) 1462 { 1463 u_int32_t anaparm; 1464 1465 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1466 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1467 1468 anaparm = RTW_READ(regs, RTW_ANAPARM); 1469 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1470 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1471 1472 switch (power) { 1473 case RTW_OFF: 1474 if (before_rf) 1475 return; 1476 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_OFF; 1477 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_OFF; 1478 anaparm |= RTW_ANAPARM_TXDACOFF; 1479 break; 1480 case RTW_SLEEP: 1481 if (!before_rf) 1482 return; 1483 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_SLEEP; 1484 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_SLEEP; 1485 anaparm |= RTW_ANAPARM_TXDACOFF; 1486 break; 1487 case RTW_ON: 1488 if (!before_rf) 1489 return; 1490 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_ON; 1491 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_ON; 1492 break; 1493 } 1494 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1495 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1496 } 1497 1498 static void 1499 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1500 int before_rf) 1501 { 1502 u_int32_t anaparm; 1503 1504 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1505 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1506 1507 anaparm = RTW_READ(regs, RTW_ANAPARM); 1508 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1509 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1510 1511 switch (power) { 1512 case RTW_OFF: 1513 if (before_rf) 1514 return; 1515 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_OFF; 1516 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_OFF; 1517 anaparm |= RTW_ANAPARM_TXDACOFF; 1518 break; 1519 case RTW_SLEEP: 1520 if (!before_rf) 1521 return; 1522 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_SLEEP; 1523 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_SLEEP; 1524 anaparm |= RTW_ANAPARM_TXDACOFF; 1525 break; 1526 case RTW_ON: 1527 if (!before_rf) 1528 return; 1529 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_ON; 1530 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_ON; 1531 break; 1532 } 1533 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1534 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1535 } 1536 1537 static void 1538 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf) 1539 { 1540 struct rtw_regs *regs = &sc->sc_regs; 1541 1542 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 1543 1544 (*sc->sc_pwrstate_cb)(regs, power, before_rf); 1545 1546 rtw_set_access(sc, RTW_ACCESS_NONE); 1547 1548 return; 1549 } 1550 1551 static int 1552 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 1553 { 1554 int rc; 1555 1556 RTW_DPRINTF2(("%s: %s->%s\n", __func__, 1557 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 1558 1559 if (sc->sc_pwrstate == power) 1560 return 0; 1561 1562 rtw_pwrstate0(sc, power, 1); 1563 rc = rtw_rf_pwrstate(sc->sc_rf, power); 1564 rtw_pwrstate0(sc, power, 0); 1565 1566 switch (power) { 1567 case RTW_ON: 1568 /* TBD */ 1569 break; 1570 case RTW_SLEEP: 1571 /* TBD */ 1572 break; 1573 case RTW_OFF: 1574 /* TBD */ 1575 break; 1576 } 1577 if (rc == 0) 1578 sc->sc_pwrstate = power; 1579 else 1580 sc->sc_pwrstate = RTW_OFF; 1581 return rc; 1582 } 1583 1584 static int 1585 rtw_tune(struct rtw_softc *sc) 1586 { 1587 struct ieee80211com *ic = &sc->sc_ic; 1588 u_int chan; 1589 int rc; 1590 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 1591 dflantb = sc->sc_flags & RTW_F_DFLANTB; 1592 1593 KASSERT(ic->ic_bss->ni_chan != NULL); 1594 1595 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1596 if (chan == IEEE80211_CHAN_ANY) 1597 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1598 1599 if (chan == sc->sc_cur_chan) { 1600 RTW_DPRINTF(("%s: already tuned chan #%d\n", __func__, chan)); 1601 return 0; 1602 } 1603 1604 rtw_suspend_ticks(sc); 1605 1606 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 1607 1608 /* TBD wait for Tx to complete */ 1609 1610 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 1611 1612 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 1613 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 1614 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 1615 dflantb, RTW_ON)) != 0) { 1616 /* XXX condition on powersaving */ 1617 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 1618 } 1619 1620 sc->sc_cur_chan = chan; 1621 1622 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 1623 1624 rtw_resume_ticks(sc); 1625 1626 return rc; 1627 } 1628 1629 void 1630 rtw_disable(struct rtw_softc *sc) 1631 { 1632 int rc; 1633 1634 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1635 return; 1636 1637 /* turn off PHY */ 1638 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 1639 printf("%s: failed to turn off PHY (%d)\n", 1640 sc->sc_dev.dv_xname, rc); 1641 1642 if (sc->sc_disable != NULL) 1643 (*sc->sc_disable)(sc); 1644 1645 sc->sc_flags &= ~RTW_F_ENABLED; 1646 } 1647 1648 int 1649 rtw_enable(struct rtw_softc *sc) 1650 { 1651 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 1652 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 1653 printf("%s: device enable failed\n", 1654 sc->sc_dev.dv_xname); 1655 return (EIO); 1656 } 1657 sc->sc_flags |= RTW_F_ENABLED; 1658 } 1659 return (0); 1660 } 1661 1662 static void 1663 rtw_transmit_config(struct rtw_regs *regs) 1664 { 1665 u_int32_t tcr; 1666 1667 tcr = RTW_READ(regs, RTW_TCR); 1668 1669 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 1670 tcr &= ~RTW_TCR_LBK_MASK; 1671 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 1672 1673 /* set short/long retry limits */ 1674 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 1675 tcr |= LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 1676 1677 tcr |= RTW_TCR_CRC; /* NIC appends CRC32 */ 1678 1679 RTW_WRITE(regs, RTW_TCR, tcr); 1680 } 1681 1682 static __inline void 1683 rtw_enable_interrupts(struct rtw_softc *sc) 1684 { 1685 struct rtw_regs *regs = &sc->sc_regs; 1686 1687 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 1688 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 1689 1690 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1691 RTW_WRITE16(regs, RTW_ISR, 0xffff); 1692 1693 /* XXX necessary? */ 1694 if (sc->sc_intr_ack != NULL) 1695 (*sc->sc_intr_ack)(regs); 1696 } 1697 1698 /* XXX is the endianness correct? test. */ 1699 #define rtw_calchash(addr) \ 1700 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1701 1702 static void 1703 rtw_pktfilt_load(struct rtw_softc *sc) 1704 { 1705 struct rtw_regs *regs = &sc->sc_regs; 1706 struct ieee80211com *ic = &sc->sc_ic; 1707 struct ethercom *ec = &ic->ic_ec; 1708 struct ifnet *ifp = &sc->sc_ic.ic_if; 1709 int hash; 1710 u_int32_t hashes[2] = { 0, 0 }; 1711 struct ether_multi *enm; 1712 struct ether_multistep step; 1713 1714 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 1715 1716 #define RTW_RCR_MONITOR (RTW_RCR_ACRC32|RTW_RCR_APM|RTW_RCR_AAP|RTW_RCR_AB) 1717 1718 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1719 sc->sc_rcr |= RTW_RCR_MONITOR; 1720 else 1721 sc->sc_rcr &= ~RTW_RCR_MONITOR; 1722 1723 /* XXX reference sources BEGIN */ 1724 sc->sc_rcr |= RTW_RCR_ENMARP | RTW_RCR_AICV | RTW_RCR_ACRC32; 1725 sc->sc_rcr |= RTW_RCR_AB | RTW_RCR_AM | RTW_RCR_APM; 1726 #if 0 1727 /* receive broadcasts in our BSS */ 1728 sc->sc_rcr |= RTW_RCR_ADD3; 1729 #endif 1730 /* XXX reference sources END */ 1731 1732 /* receive pwrmgmt frames. */ 1733 sc->sc_rcr |= RTW_RCR_APWRMGT; 1734 /* receive mgmt/ctrl/data frames. */ 1735 sc->sc_rcr |= RTW_RCR_AMF | RTW_RCR_ACF | RTW_RCR_ADF; 1736 /* initialize Rx DMA threshold, Tx DMA burst size */ 1737 sc->sc_rcr |= RTW_RCR_RXFTH_WHOLE | RTW_RCR_MXDMA_1024; 1738 1739 ifp->if_flags &= ~IFF_ALLMULTI; 1740 1741 if (ifp->if_flags & IFF_PROMISC) { 1742 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 1743 allmulti: 1744 ifp->if_flags |= IFF_ALLMULTI; 1745 goto setit; 1746 } 1747 1748 /* 1749 * Program the 64-bit multicast hash filter. 1750 */ 1751 ETHER_FIRST_MULTI(step, ec, enm); 1752 while (enm != NULL) { 1753 /* XXX */ 1754 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1755 ETHER_ADDR_LEN) != 0) 1756 goto allmulti; 1757 1758 hash = rtw_calchash(enm->enm_addrlo); 1759 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1760 ETHER_NEXT_MULTI(step, enm); 1761 } 1762 1763 if (ifp->if_flags & IFF_BROADCAST) { 1764 hash = rtw_calchash(etherbroadcastaddr); 1765 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1766 } 1767 1768 /* all bits set => hash is useless */ 1769 if (~(hashes[0] & hashes[1]) == 0) 1770 goto allmulti; 1771 1772 setit: 1773 if (ifp->if_flags & IFF_ALLMULTI) 1774 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 1775 1776 if (ic->ic_state == IEEE80211_S_SCAN) 1777 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 1778 1779 hashes[0] = hashes[1] = 0xffffffff; 1780 1781 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 1782 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 1783 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 1784 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 1785 1786 DPRINTF(sc, ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 1787 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 1788 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 1789 1790 return; 1791 } 1792 1793 static int 1794 rtw_init(struct ifnet *ifp) 1795 { 1796 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1797 struct ieee80211com *ic = &sc->sc_ic; 1798 struct rtw_regs *regs = &sc->sc_regs; 1799 int rc = 0, s; 1800 1801 if ((rc = rtw_enable(sc)) != 0) 1802 goto out; 1803 1804 /* Cancel pending I/O and reset. */ 1805 rtw_stop(ifp, 0); 1806 1807 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 1808 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1809 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 1810 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 1811 1812 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 1813 goto out; 1814 1815 rtw_swring_setup(sc); 1816 1817 rtw_transmit_config(regs); 1818 1819 rtw_set_access(sc, RTW_ACCESS_CONFIG); 1820 1821 RTW_WRITE(regs, RTW_MSR, 0x0); /* no link */ 1822 1823 RTW_WRITE(regs, RTW_BRSR, 0x0); /* long PLCP header, 1Mbps basic rate */ 1824 1825 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 1826 rtw_set_access(sc, RTW_ACCESS_NONE); 1827 1828 #if 0 1829 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_GWAKE|RTW_FEMR_WKUP|RTW_FEMR_INTR); 1830 #endif 1831 /* XXX from reference sources */ 1832 RTW_WRITE(regs, RTW_FEMR, 0xffff); 1833 1834 RTW_WRITE(regs, RTW_PHYDELAY, sc->sc_phydelay); 1835 /* from Linux driver */ 1836 RTW_WRITE(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 1837 1838 rtw_enable_interrupts(sc); 1839 1840 rtw_pktfilt_load(sc); 1841 1842 rtw_hwring_setup(sc); 1843 1844 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 1845 1846 ifp->if_flags |= IFF_RUNNING; 1847 ic->ic_state = IEEE80211_S_INIT; 1848 1849 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 1850 RTW_WRITE(regs, RTW_BSSID32, 0x0); 1851 1852 s = splclock(); 1853 sc->sc_tick0 = mono_time; 1854 splx(s); 1855 1856 rtw_resume_ticks(sc); 1857 1858 switch (ic->ic_opmode) { 1859 case IEEE80211_M_AHDEMO: 1860 case IEEE80211_M_IBSS: 1861 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_ADHOC_OK); 1862 break; 1863 case IEEE80211_M_HOSTAP: 1864 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_AP_OK); 1865 case IEEE80211_M_MONITOR: 1866 /* XXX */ 1867 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_NOLINK); 1868 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1869 case IEEE80211_M_STA: 1870 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_INFRA_OK); 1871 break; 1872 } 1873 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1874 out: 1875 return rc; 1876 } 1877 1878 static int 1879 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1880 { 1881 int rc = 0; 1882 struct rtw_softc *sc = ifp->if_softc; 1883 struct ifreq *ifr = (struct ifreq *)data; 1884 1885 switch (cmd) { 1886 case SIOCSIFFLAGS: 1887 if ((ifp->if_flags & IFF_UP) != 0) { 1888 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 1889 rtw_pktfilt_load(sc); 1890 } else 1891 rc = rtw_init(ifp); 1892 #ifdef RTW_DEBUG 1893 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 1894 #endif /* RTW_DEBUG */ 1895 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 1896 #ifdef RTW_DEBUG 1897 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 1898 #endif /* RTW_DEBUG */ 1899 rtw_stop(ifp, 1); 1900 } 1901 break; 1902 case SIOCADDMULTI: 1903 case SIOCDELMULTI: 1904 if (cmd == SIOCADDMULTI) 1905 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 1906 else 1907 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 1908 if (rc == ENETRESET) { 1909 if (ifp->if_flags & IFF_RUNNING) 1910 rtw_pktfilt_load(sc); 1911 rc = 0; 1912 } 1913 break; 1914 default: 1915 if ((rc = ieee80211_ioctl(ifp, cmd, data)) == ENETRESET) { 1916 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 1917 rc = rtw_init(ifp); 1918 else 1919 rc = 0; 1920 } 1921 break; 1922 } 1923 return rc; 1924 } 1925 1926 /* Point *mp at the next 802.11 frame to transmit. Point *stcp 1927 * at the driver's selection of transmit control block for the packet. 1928 */ 1929 static __inline int 1930 rtw_dequeue(struct ifnet *ifp, struct rtw_txctl_blk **stcp, struct mbuf **mp, 1931 struct ieee80211_node **nip) 1932 { 1933 struct mbuf *m0; 1934 struct rtw_softc *sc; 1935 struct ieee80211com *ic; 1936 1937 sc = (struct rtw_softc *)ifp->if_softc; 1938 ic = &sc->sc_ic; 1939 1940 *mp = NULL; 1941 1942 if (!IF_IS_EMPTY(&ic->ic_mgtq)) { 1943 IF_DEQUEUE(&ic->ic_mgtq, m0); 1944 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1945 m0->m_pkthdr.rcvif = NULL; 1946 } else if (ic->ic_state != IEEE80211_S_RUN) 1947 return 0; 1948 else if (!IF_IS_EMPTY(&ic->ic_pwrsaveq)) { 1949 IF_DEQUEUE(&ic->ic_pwrsaveq, m0); 1950 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1951 m0->m_pkthdr.rcvif = NULL; 1952 } else { 1953 IFQ_POLL(&ifp->if_snd, m0); 1954 if (m0 == NULL) 1955 return 0; 1956 IFQ_DEQUEUE(&ifp->if_snd, m0); 1957 ifp->if_opackets++; 1958 #if NBPFILTER > 0 1959 if (ifp->if_bpf) 1960 bpf_mtap(ifp->if_bpf, m0); 1961 #endif 1962 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 1963 ifp->if_oerrors++; 1964 return -1; 1965 } 1966 } 1967 *stcp = &sc->sc_txctl_blk[RTW_TXPRIMD]; 1968 *mp = m0; 1969 return 0; 1970 } 1971 1972 static void 1973 rtw_start(struct ifnet *ifp) 1974 { 1975 struct mbuf *m0; 1976 struct rtw_softc *sc; 1977 struct rtw_txctl_blk *stc; 1978 struct ieee80211_node *ni; 1979 1980 sc = (struct rtw_softc *)ifp->if_softc; 1981 1982 #if 0 1983 struct ifqueue ic_mgtq; 1984 struct ifqueue ic_pwrsaveq; 1985 struct rtw_txctl_blk { 1986 /* dirty/free s/w descriptors */ 1987 struct rtw_txq stc_dirtyq; 1988 struct rtw_txq stc_freeq; 1989 u_int stc_ndesc; 1990 struct rtw_txctl *stc_desc; 1991 }; 1992 #endif 1993 while (!SIMPLEQ_EMPTY(&stc->stc_freeq)) { 1994 if (rtw_dequeue(ifp, &stc, &m0, &ni) == -1) 1995 continue; 1996 if (m0 == NULL) 1997 break; 1998 ieee80211_release_node(&sc->sc_ic, ni); 1999 } 2000 return; 2001 } 2002 2003 static void 2004 rtw_watchdog(struct ifnet *ifp) 2005 { 2006 /* TBD */ 2007 return; 2008 } 2009 2010 static void 2011 rtw_start_beacon(struct rtw_softc *sc, int enable) 2012 { 2013 /* TBD */ 2014 return; 2015 } 2016 2017 static void 2018 rtw_next_scan(void *arg) 2019 { 2020 struct ieee80211com *ic = arg; 2021 int s; 2022 2023 /* don't call rtw_start w/o network interrupts blocked */ 2024 s = splnet(); 2025 if (ic->ic_state == IEEE80211_S_SCAN) 2026 ieee80211_next_scan(ic); 2027 splx(s); 2028 } 2029 2030 /* Synchronize the hardware state with the software state. */ 2031 static int 2032 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2033 { 2034 struct ifnet *ifp = &ic->ic_if; 2035 struct rtw_softc *sc = ifp->if_softc; 2036 enum ieee80211_state ostate; 2037 int error; 2038 2039 ostate = ic->ic_state; 2040 2041 if (nstate == IEEE80211_S_INIT) { 2042 callout_stop(&sc->sc_scan_ch); 2043 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2044 rtw_start_beacon(sc, 0); 2045 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2046 } 2047 2048 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 2049 rtw_pwrstate(sc, RTW_ON); 2050 2051 if ((error = rtw_tune(sc)) != 0) 2052 return error; 2053 2054 switch (nstate) { 2055 case IEEE80211_S_ASSOC: 2056 break; 2057 case IEEE80211_S_INIT: 2058 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2059 break; 2060 case IEEE80211_S_SCAN: 2061 #if 0 2062 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2063 rtw_write_bssid(sc); 2064 #endif 2065 2066 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 2067 rtw_next_scan, ic); 2068 2069 break; 2070 case IEEE80211_S_RUN: 2071 if (ic->ic_opmode == IEEE80211_M_STA) 2072 break; 2073 /*FALLTHROUGH*/ 2074 case IEEE80211_S_AUTH: 2075 #if 0 2076 rtw_write_bssid(sc); 2077 rtw_write_bcn_thresh(sc); 2078 rtw_write_ssid(sc); 2079 rtw_write_sup_rates(sc); 2080 #endif 2081 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2082 ic->ic_opmode == IEEE80211_M_MONITOR) 2083 break; 2084 2085 /* TBD set listen interval, beacon interval */ 2086 2087 #if 0 2088 rtw_tsf(sc); 2089 #endif 2090 break; 2091 } 2092 2093 if (nstate != IEEE80211_S_SCAN) 2094 callout_stop(&sc->sc_scan_ch); 2095 2096 if (nstate == IEEE80211_S_RUN && 2097 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2098 ic->ic_opmode == IEEE80211_M_IBSS)) 2099 rtw_start_beacon(sc, 1); 2100 else 2101 rtw_start_beacon(sc, 0); 2102 2103 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2104 } 2105 2106 static void 2107 rtw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2108 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2109 { 2110 /* TBD */ 2111 return; 2112 } 2113 2114 static void 2115 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2116 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2117 { 2118 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 2119 2120 switch (subtype) { 2121 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2122 /* do nothing: hardware answers probe request XXX */ 2123 break; 2124 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2125 case IEEE80211_FC0_SUBTYPE_BEACON: 2126 rtw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2127 break; 2128 default: 2129 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2130 break; 2131 } 2132 return; 2133 } 2134 2135 static struct ieee80211_node * 2136 rtw_node_alloc(struct ieee80211com *ic) 2137 { 2138 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2139 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 2140 2141 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 2142 return ni; 2143 } 2144 2145 static void 2146 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 2147 { 2148 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2149 2150 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 2151 ether_sprintf(ni->ni_bssid))); 2152 (*sc->sc_mtbl.mt_node_free)(ic, ni); 2153 } 2154 2155 static int 2156 rtw_media_change(struct ifnet *ifp) 2157 { 2158 int error; 2159 2160 error = ieee80211_media_change(ifp); 2161 if (error == ENETRESET) { 2162 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 2163 (IFF_RUNNING|IFF_UP)) 2164 rtw_init(ifp); /* XXX lose error */ 2165 error = 0; 2166 } 2167 return error; 2168 } 2169 2170 static void 2171 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 2172 { 2173 struct rtw_softc *sc = ifp->if_softc; 2174 2175 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2176 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 2177 imr->ifm_status = 0; 2178 return; 2179 } 2180 ieee80211_media_status(ifp, imr); 2181 } 2182 2183 void 2184 rtw_power(int why, void *arg) 2185 { 2186 struct rtw_softc *sc = arg; 2187 struct ifnet *ifp = &sc->sc_ic.ic_if; 2188 int s; 2189 2190 DPRINTF(sc, ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 2191 2192 s = splnet(); 2193 switch (why) { 2194 case PWR_STANDBY: 2195 /* XXX do nothing. */ 2196 break; 2197 case PWR_SUSPEND: 2198 rtw_stop(ifp, 0); 2199 if (sc->sc_power != NULL) 2200 (*sc->sc_power)(sc, why); 2201 break; 2202 case PWR_RESUME: 2203 if (ifp->if_flags & IFF_UP) { 2204 if (sc->sc_power != NULL) 2205 (*sc->sc_power)(sc, why); 2206 rtw_init(ifp); 2207 } 2208 break; 2209 case PWR_SOFTSUSPEND: 2210 case PWR_SOFTSTANDBY: 2211 case PWR_SOFTRESUME: 2212 break; 2213 } 2214 splx(s); 2215 } 2216 2217 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 2218 void 2219 rtw_shutdown(void *arg) 2220 { 2221 struct rtw_softc *sc = arg; 2222 2223 rtw_stop(&sc->sc_ic.ic_if, 1); 2224 } 2225 2226 static __inline void 2227 rtw_setifprops(struct ifnet *ifp, char (*dvname)[IFNAMSIZ], void *softc) 2228 { 2229 (void)memcpy(ifp->if_xname, *dvname, IFNAMSIZ); 2230 ifp->if_softc = softc; 2231 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 2232 IFF_NOTRAILERS; 2233 ifp->if_ioctl = rtw_ioctl; 2234 ifp->if_start = rtw_start; 2235 ifp->if_watchdog = rtw_watchdog; 2236 ifp->if_init = rtw_init; 2237 ifp->if_stop = rtw_stop; 2238 } 2239 2240 static __inline void 2241 rtw_set80211props(struct ieee80211com *ic) 2242 { 2243 int nrate; 2244 ic->ic_phytype = IEEE80211_T_DS; 2245 ic->ic_opmode = IEEE80211_M_STA; 2246 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 2247 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 2248 2249 nrate = 0; 2250 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 2251 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 2252 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 2253 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 2254 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 2255 } 2256 2257 static __inline void 2258 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 2259 { 2260 mtbl->mt_newstate = ic->ic_newstate; 2261 ic->ic_newstate = rtw_newstate; 2262 2263 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 2264 ic->ic_recv_mgmt = rtw_recv_mgmt; 2265 2266 mtbl->mt_node_free = ic->ic_node_free; 2267 ic->ic_node_free = rtw_node_free; 2268 2269 mtbl->mt_node_alloc = ic->ic_node_alloc; 2270 ic->ic_node_alloc = rtw_node_alloc; 2271 } 2272 2273 static __inline void 2274 rtw_establish_hooks(struct rtw_hooks *hooks, char (*dvname)[IFNAMSIZ], 2275 void *arg) 2276 { 2277 /* 2278 * Make sure the interface is shutdown during reboot. 2279 */ 2280 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 2281 if (hooks->rh_shutdown == NULL) 2282 printf("%s: WARNING: unable to establish shutdown hook\n", 2283 *dvname); 2284 2285 /* 2286 * Add a suspend hook to make sure we come back up after a 2287 * resume. 2288 */ 2289 hooks->rh_power = powerhook_establish(rtw_power, arg); 2290 if (hooks->rh_power == NULL) 2291 printf("%s: WARNING: unable to establish power hook\n", 2292 *dvname); 2293 } 2294 2295 static __inline void 2296 rtw_disestablish_hooks(struct rtw_hooks *hooks, char (*dvname)[IFNAMSIZ], 2297 void *arg) 2298 { 2299 if (hooks->rh_shutdown != NULL) 2300 shutdownhook_disestablish(hooks->rh_shutdown); 2301 2302 if (hooks->rh_power != NULL) 2303 powerhook_disestablish(hooks->rh_power); 2304 } 2305 2306 static __inline void 2307 rtw_init_radiotap(struct rtw_softc *sc) 2308 { 2309 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 2310 sc->sc_rxtap.rr_ihdr.it_len = sizeof(sc->sc_rxtapu); 2311 sc->sc_rxtap.rr_ihdr.it_present = RTW_RX_RADIOTAP_PRESENT; 2312 2313 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 2314 sc->sc_txtap.rt_ihdr.it_len = sizeof(sc->sc_txtapu); 2315 sc->sc_txtap.rt_ihdr.it_present = RTW_TX_RADIOTAP_PRESENT; 2316 } 2317 2318 static int 2319 rtw_txctl_blk_setup(struct rtw_txctl_blk *stc, u_int qlen) 2320 { 2321 SIMPLEQ_INIT(&stc->stc_dirtyq); 2322 SIMPLEQ_INIT(&stc->stc_freeq); 2323 stc->stc_ndesc = qlen; 2324 stc->stc_desc = malloc(qlen * sizeof(*stc->stc_desc), M_DEVBUF, 2325 M_NOWAIT); 2326 if (stc->stc_desc == NULL) 2327 return ENOMEM; 2328 return 0; 2329 } 2330 2331 static void 2332 rtw_txctl_blk_cleanup_all(struct rtw_softc *sc) 2333 { 2334 struct rtw_txctl_blk *stc; 2335 int qlen[RTW_NTXPRI] = 2336 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2337 int pri; 2338 2339 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2340 stc = &sc->sc_txctl_blk[pri]; 2341 free(stc->stc_desc, M_DEVBUF); 2342 stc->stc_desc = NULL; 2343 } 2344 } 2345 2346 static int 2347 rtw_txctl_blk_setup_all(struct rtw_softc *sc) 2348 { 2349 int pri, rc = 0; 2350 int qlen[RTW_NTXPRI] = 2351 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2352 2353 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2354 rc = rtw_txctl_blk_setup(&sc->sc_txctl_blk[pri], qlen[pri]); 2355 if (rc != 0) 2356 break; 2357 } 2358 return rc; 2359 } 2360 2361 static void 2362 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *htc, struct rtw_txdesc *desc, 2363 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 2364 { 2365 int i; 2366 2367 htc->htc_ndesc = ndesc; 2368 htc->htc_desc = desc; 2369 htc->htc_physbase = physbase; 2370 htc->htc_ofs = ofs; 2371 2372 (void)memset(htc->htc_desc, 0, 2373 sizeof(htc->htc_desc[0]) * htc->htc_ndesc); 2374 2375 for (i = 0; i < htc->htc_ndesc; i++) { 2376 htc->htc_desc[i].htx_next = htole32(RTW_NEXT_DESC(htc, i)); 2377 } 2378 } 2379 2380 static void 2381 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 2382 { 2383 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 2384 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 2385 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 2386 2387 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 2388 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 2389 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 2390 2391 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 2392 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 2393 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 2394 2395 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 2396 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 2397 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 2398 } 2399 2400 static struct rtw_rf * 2401 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, 2402 rtw_rf_write_t rf_write, int digphy) 2403 { 2404 struct rtw_rf *rf; 2405 2406 switch (rfchipid) { 2407 case RTW_RFCHIPID_MAXIM: 2408 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 2409 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 2410 break; 2411 case RTW_RFCHIPID_PHILIPS: 2412 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 2413 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 2414 break; 2415 default: 2416 return NULL; 2417 } 2418 rf->rf_continuous_tx_cb = 2419 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 2420 rf->rf_continuous_tx_arg = (void *)sc; 2421 return rf; 2422 } 2423 2424 /* Revision C and later use a different PHY delay setting than 2425 * revisions A and B. 2426 */ 2427 static u_int8_t 2428 rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0) 2429 { 2430 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 2431 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 2432 2433 u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 2434 2435 RTW_WRITE(regs, RTW_RCR, REVAB); 2436 RTW_WRITE(regs, RTW_RCR, REVC); 2437 2438 RTW_WBR(regs, RTW_RCR, RTW_RCR); 2439 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 2440 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 2441 2442 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 2443 2444 return phydelay; 2445 #undef REVC 2446 } 2447 2448 void 2449 rtw_attach(struct rtw_softc *sc) 2450 { 2451 rtw_rf_write_t rf_write; 2452 struct rtw_txctl_blk *stc; 2453 int pri, rc, vers; 2454 2455 #if 0 2456 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_txdesc) == 0, 2457 "RTW_DESC_ALIGNMENT is not a multiple of " 2458 "sizeof(struct rtw_txdesc)"); 2459 2460 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_rxdesc) == 0, 2461 "RTW_DESC_ALIGNMENT is not a multiple of " 2462 "sizeof(struct rtw_rxdesc)"); 2463 2464 CASSERT(RTW_DESC_ALIGNMENT % RTW_MAXPKTSEGS == 0, 2465 "RTW_DESC_ALIGNMENT is not a multiple of RTW_MAXPKTSEGS"); 2466 #endif 2467 2468 NEXT_ATTACH_STATE(sc, DETACHED); 2469 2470 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 2471 case RTW_TCR_HWVERID_F: 2472 vers = 'F'; 2473 rf_write = rtw_rf_hostwrite; 2474 break; 2475 case RTW_TCR_HWVERID_D: 2476 vers = 'D'; 2477 rf_write = rtw_rf_macwrite; 2478 break; 2479 default: 2480 vers = '?'; 2481 rf_write = rtw_rf_macwrite; 2482 break; 2483 } 2484 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, vers); 2485 2486 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 2487 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 2488 0); 2489 2490 if (rc != 0) { 2491 printf("%s: could not allocate hw descriptors, error %d\n", 2492 sc->sc_dev.dv_xname, rc); 2493 goto err; 2494 } 2495 2496 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 2497 2498 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 2499 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 2500 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 2501 2502 if (rc != 0) { 2503 printf("%s: could not map hw descriptors, error %d\n", 2504 sc->sc_dev.dv_xname, rc); 2505 goto err; 2506 } 2507 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 2508 2509 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 2510 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 2511 2512 if (rc != 0) { 2513 printf("%s: could not create DMA map for hw descriptors, " 2514 "error %d\n", sc->sc_dev.dv_xname, rc); 2515 goto err; 2516 } 2517 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 2518 2519 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 2520 sizeof(struct rtw_descs), NULL, 0); 2521 2522 if (rc != 0) { 2523 printf("%s: could not load DMA map for hw descriptors, " 2524 "error %d\n", sc->sc_dev.dv_xname, rc); 2525 goto err; 2526 } 2527 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 2528 2529 if (rtw_txctl_blk_setup_all(sc) != 0) 2530 goto err; 2531 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 2532 2533 rtw_txdesc_blk_setup_all(sc); 2534 2535 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 2536 2537 sc->sc_rxdesc = &sc->sc_descs->hd_rx[0]; 2538 2539 rtw_rxctls_setup(&sc->sc_rxctl[0]); 2540 2541 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2542 stc = &sc->sc_txctl_blk[pri]; 2543 2544 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 2545 &stc->stc_desc[0], stc->stc_ndesc)) != 0) { 2546 printf("%s: could not load DMA map for " 2547 "hw tx descriptors, error %d\n", 2548 sc->sc_dev.dv_xname, rc); 2549 goto err; 2550 } 2551 } 2552 2553 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 2554 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxctl[0], 2555 RTW_RXQLEN)) != 0) { 2556 printf("%s: could not load DMA map for hw rx descriptors, " 2557 "error %d\n", sc->sc_dev.dv_xname, rc); 2558 goto err; 2559 } 2560 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 2561 2562 /* Reset the chip to a known state. */ 2563 if (rtw_reset(sc) != 0) 2564 goto err; 2565 NEXT_ATTACH_STATE(sc, FINISH_RESET); 2566 2567 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 2568 2569 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 2570 sc->sc_flags |= RTW_F_9356SROM; 2571 2572 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 2573 &sc->sc_dev.dv_xname) != 0) 2574 goto err; 2575 2576 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 2577 2578 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 2579 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 2580 &sc->sc_dev.dv_xname) != 0) { 2581 printf("%s: attach failed, malformed serial ROM\n", 2582 sc->sc_dev.dv_xname); 2583 goto err; 2584 } 2585 2586 RTW_DPRINTF(("%s: CS threshold %u\n", sc->sc_dev.dv_xname, 2587 sc->sc_csthr)); 2588 2589 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 2590 2591 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, rf_write, 2592 sc->sc_flags & RTW_F_DIGPHY); 2593 2594 if (sc->sc_rf == NULL) { 2595 printf("%s: attach failed, could not attach RF\n", 2596 sc->sc_dev.dv_xname); 2597 goto err; 2598 } 2599 2600 #if 0 2601 if (rtw_identify_rf(&sc->sc_regs, &sc->sc_rftype, 2602 &sc->sc_dev.dv_xname) != 0) { 2603 printf("%s: attach failed, unknown RF unidentified\n", 2604 sc->sc_dev.dv_xname); 2605 goto err; 2606 } 2607 #endif 2608 2609 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 2610 2611 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 2612 2613 RTW_DPRINTF(("%s: PHY delay %d\n", sc->sc_dev.dv_xname, 2614 sc->sc_phydelay)); 2615 2616 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 2617 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 2618 &sc->sc_dev.dv_xname); 2619 2620 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 2621 &sc->sc_dev.dv_xname); 2622 2623 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 2624 &sc->sc_dev.dv_xname) != 0) 2625 goto err; 2626 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 2627 2628 rtw_setifprops(&sc->sc_if, &sc->sc_dev.dv_xname, (void*)sc); 2629 2630 IFQ_SET_READY(&sc->sc_if.if_snd); 2631 2632 rtw_set80211props(&sc->sc_ic); 2633 2634 /* 2635 * Call MI attach routines. 2636 */ 2637 if_attach(&sc->sc_if); 2638 ieee80211_ifattach(&sc->sc_if); 2639 2640 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 2641 2642 /* possibly we should fill in our own sc_send_prresp, since 2643 * the RTL8180 is probably sending probe responses in ad hoc 2644 * mode. 2645 */ 2646 2647 /* complete initialization */ 2648 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 2649 callout_init(&sc->sc_scan_ch); 2650 2651 #if NBPFILTER > 0 2652 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 2653 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 2654 #endif 2655 2656 rtw_establish_hooks(&sc->sc_hooks, &sc->sc_dev.dv_xname, (void*)sc); 2657 2658 rtw_init_radiotap(sc); 2659 2660 NEXT_ATTACH_STATE(sc, FINISHED); 2661 2662 return; 2663 err: 2664 rtw_detach(sc); 2665 return; 2666 } 2667 2668 int 2669 rtw_detach(struct rtw_softc *sc) 2670 { 2671 int pri; 2672 2673 switch (sc->sc_attach_state) { 2674 case FINISHED: 2675 rtw_stop(&sc->sc_if, 1); 2676 2677 rtw_disestablish_hooks(&sc->sc_hooks, &sc->sc_dev.dv_xname, 2678 (void*)sc); 2679 callout_stop(&sc->sc_scan_ch); 2680 ieee80211_ifdetach(&sc->sc_if); 2681 if_detach(&sc->sc_if); 2682 break; 2683 case FINISH_ID_STA: 2684 case FINISH_RF_ATTACH: 2685 rtw_rf_destroy(sc->sc_rf); 2686 sc->sc_rf = NULL; 2687 /*FALLTHROUGH*/ 2688 case FINISH_PARSE_SROM: 2689 case FINISH_READ_SROM: 2690 rtw_srom_free(&sc->sc_srom); 2691 /*FALLTHROUGH*/ 2692 case FINISH_RESET: 2693 case FINISH_RXMAPS_CREATE: 2694 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxctl[0], 2695 RTW_RXQLEN); 2696 /*FALLTHROUGH*/ 2697 case FINISH_TXMAPS_CREATE: 2698 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2699 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 2700 sc->sc_txctl_blk[pri].stc_desc, 2701 sc->sc_txctl_blk[pri].stc_ndesc); 2702 } 2703 /*FALLTHROUGH*/ 2704 case FINISH_TXDESCBLK_SETUP: 2705 case FINISH_TXCTLBLK_SETUP: 2706 rtw_txctl_blk_cleanup_all(sc); 2707 /*FALLTHROUGH*/ 2708 case FINISH_DESCMAP_LOAD: 2709 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 2710 /*FALLTHROUGH*/ 2711 case FINISH_DESCMAP_CREATE: 2712 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 2713 /*FALLTHROUGH*/ 2714 case FINISH_DESC_MAP: 2715 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 2716 sizeof(struct rtw_descs)); 2717 /*FALLTHROUGH*/ 2718 case FINISH_DESC_ALLOC: 2719 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 2720 sc->sc_desc_nsegs); 2721 /*FALLTHROUGH*/ 2722 case DETACHED: 2723 NEXT_ATTACH_STATE(sc, DETACHED); 2724 break; 2725 } 2726 return 0; 2727 } 2728 2729 int 2730 rtw_activate(struct device *self, enum devact act) 2731 { 2732 struct rtw_softc *sc = (struct rtw_softc *)self; 2733 int rc = 0, s; 2734 2735 s = splnet(); 2736 switch (act) { 2737 case DVACT_ACTIVATE: 2738 rc = EOPNOTSUPP; 2739 break; 2740 2741 case DVACT_DEACTIVATE: 2742 if_deactivate(&sc->sc_ic.ic_if); 2743 break; 2744 } 2745 splx(s); 2746 return rc; 2747 } 2748
Indexes created Thu Sep 25 16:09:42 GMT 2025