rtw.c revision 1.47
1 /* $NetBSD: rtw.c,v 1.47 2005/06/20 02:49:18 atatat Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.47 2005/06/20 02:49:18 atatat Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/time.h> 49 #include <sys/types.h> 50 51 #include <machine/endian.h> 52 #include <machine/bus.h> 53 #include <machine/intr.h> /* splnet */ 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #include <net80211/ieee80211_var.h> 62 #include <net80211/ieee80211_compat.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <dev/ic/rtwreg.h> 70 #include <dev/ic/rtwvar.h> 71 #include <dev/ic/rtwphyio.h> 72 #include <dev/ic/rtwphy.h> 73 74 #include <dev/ic/smc93cx6var.h> 75 76 #define KASSERT2(__cond, __msg) \ 77 do { \ 78 if (!(__cond)) \ 79 panic __msg ; \ 80 } while (0) 81 82 int rtw_rfprog_fallback = 0; 83 int rtw_host_rfio = 0; 84 85 #ifdef RTW_DEBUG 86 int rtw_debug = 0; 87 int rtw_rxbufs_limit = RTW_RXQLEN; 88 #endif /* RTW_DEBUG */ 89 90 #define NEXT_ATTACH_STATE(sc, state) do { \ 91 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 92 ("%s: attach state %s\n", __func__, #state)); \ 93 sc->sc_attach_state = state; \ 94 } while (0) 95 96 int rtw_dwelltime = 200; /* milliseconds */ 97 98 static void rtw_start(struct ifnet *); 99 100 static void rtw_led_attach(struct rtw_led_state *, void *); 101 static void rtw_led_init(struct rtw_regs *); 102 static void rtw_led_slowblink(void *); 103 static void rtw_led_fastblink(void *); 104 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 105 106 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 107 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 108 #ifdef RTW_DEBUG 109 static void rtw_print_txdesc(struct rtw_softc *, const char *, 110 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 111 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 112 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 113 #endif /* RTW_DEBUG */ 114 115 /* 116 * Setup sysctl(3) MIB, hw.rtw.* 117 * 118 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 119 */ 120 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 121 { 122 int rc; 123 const struct sysctlnode *cnode, *rnode; 124 125 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 126 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 127 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 128 goto err; 129 130 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 131 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 132 "Realtek RTL818x 802.11 controls", 133 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 134 goto err; 135 136 #ifdef RTW_DEBUG 137 /* control debugging printfs */ 138 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 139 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 140 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 141 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 142 CTL_CREATE, CTL_EOL)) != 0) 143 goto err; 144 145 /* Limit rx buffers, for simulating resource exhaustion. */ 146 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 147 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 148 "rxbufs_limit", 149 SYSCTL_DESCR("Set rx buffers limit"), 150 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 151 CTL_CREATE, CTL_EOL)) != 0) 152 goto err; 153 154 #endif /* RTW_DEBUG */ 155 /* set fallback RF programming method */ 156 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 157 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 158 "rfprog_fallback", 159 SYSCTL_DESCR("Set fallback RF programming method"), 160 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 161 CTL_CREATE, CTL_EOL)) != 0) 162 goto err; 163 164 /* force host to control RF I/O bus */ 165 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 166 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 167 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 168 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 169 CTL_CREATE, CTL_EOL)) != 0) 170 goto err; 171 172 return; 173 err: 174 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 175 } 176 177 static int 178 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 179 { 180 int error, t; 181 struct sysctlnode node; 182 183 node = *rnode; 184 t = *(int*)rnode->sysctl_data; 185 node.sysctl_data = &t; 186 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 187 if (error || newp == NULL) 188 return (error); 189 190 if (t < lower || t > upper) 191 return (EINVAL); 192 193 *(int*)rnode->sysctl_data = t; 194 195 return (0); 196 } 197 198 static int 199 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 200 { 201 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 202 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 203 } 204 205 static int 206 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 207 { 208 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 209 } 210 211 #ifdef RTW_DEBUG 212 static int 213 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 214 { 215 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 216 0, RTW_DEBUG_MAX); 217 } 218 219 static int 220 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 221 { 222 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 223 0, RTW_RXQLEN); 224 } 225 226 static void 227 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 228 { 229 #define PRINTREG32(sc, reg) \ 230 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 231 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 232 dvname, reg, RTW_READ(regs, reg))) 233 234 #define PRINTREG16(sc, reg) \ 235 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 236 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 237 dvname, reg, RTW_READ16(regs, reg))) 238 239 #define PRINTREG8(sc, reg) \ 240 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 241 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 242 dvname, reg, RTW_READ8(regs, reg))) 243 244 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 245 246 PRINTREG32(regs, RTW_IDR0); 247 PRINTREG32(regs, RTW_IDR1); 248 PRINTREG32(regs, RTW_MAR0); 249 PRINTREG32(regs, RTW_MAR1); 250 PRINTREG32(regs, RTW_TSFTRL); 251 PRINTREG32(regs, RTW_TSFTRH); 252 PRINTREG32(regs, RTW_TLPDA); 253 PRINTREG32(regs, RTW_TNPDA); 254 PRINTREG32(regs, RTW_THPDA); 255 PRINTREG32(regs, RTW_TCR); 256 PRINTREG32(regs, RTW_RCR); 257 PRINTREG32(regs, RTW_TINT); 258 PRINTREG32(regs, RTW_TBDA); 259 PRINTREG32(regs, RTW_ANAPARM); 260 PRINTREG32(regs, RTW_BB); 261 PRINTREG32(regs, RTW_PHYCFG); 262 PRINTREG32(regs, RTW_WAKEUP0L); 263 PRINTREG32(regs, RTW_WAKEUP0H); 264 PRINTREG32(regs, RTW_WAKEUP1L); 265 PRINTREG32(regs, RTW_WAKEUP1H); 266 PRINTREG32(regs, RTW_WAKEUP2LL); 267 PRINTREG32(regs, RTW_WAKEUP2LH); 268 PRINTREG32(regs, RTW_WAKEUP2HL); 269 PRINTREG32(regs, RTW_WAKEUP2HH); 270 PRINTREG32(regs, RTW_WAKEUP3LL); 271 PRINTREG32(regs, RTW_WAKEUP3LH); 272 PRINTREG32(regs, RTW_WAKEUP3HL); 273 PRINTREG32(regs, RTW_WAKEUP3HH); 274 PRINTREG32(regs, RTW_WAKEUP4LL); 275 PRINTREG32(regs, RTW_WAKEUP4LH); 276 PRINTREG32(regs, RTW_WAKEUP4HL); 277 PRINTREG32(regs, RTW_WAKEUP4HH); 278 PRINTREG32(regs, RTW_DK0); 279 PRINTREG32(regs, RTW_DK1); 280 PRINTREG32(regs, RTW_DK2); 281 PRINTREG32(regs, RTW_DK3); 282 PRINTREG32(regs, RTW_RETRYCTR); 283 PRINTREG32(regs, RTW_RDSAR); 284 PRINTREG32(regs, RTW_FER); 285 PRINTREG32(regs, RTW_FEMR); 286 PRINTREG32(regs, RTW_FPSR); 287 PRINTREG32(regs, RTW_FFER); 288 289 /* 16-bit registers */ 290 PRINTREG16(regs, RTW_BRSR); 291 PRINTREG16(regs, RTW_IMR); 292 PRINTREG16(regs, RTW_ISR); 293 PRINTREG16(regs, RTW_BCNITV); 294 PRINTREG16(regs, RTW_ATIMWND); 295 PRINTREG16(regs, RTW_BINTRITV); 296 PRINTREG16(regs, RTW_ATIMTRITV); 297 PRINTREG16(regs, RTW_CRC16ERR); 298 PRINTREG16(regs, RTW_CRC0); 299 PRINTREG16(regs, RTW_CRC1); 300 PRINTREG16(regs, RTW_CRC2); 301 PRINTREG16(regs, RTW_CRC3); 302 PRINTREG16(regs, RTW_CRC4); 303 PRINTREG16(regs, RTW_CWR); 304 305 /* 8-bit registers */ 306 PRINTREG8(regs, RTW_CR); 307 PRINTREG8(regs, RTW_9346CR); 308 PRINTREG8(regs, RTW_CONFIG0); 309 PRINTREG8(regs, RTW_CONFIG1); 310 PRINTREG8(regs, RTW_CONFIG2); 311 PRINTREG8(regs, RTW_MSR); 312 PRINTREG8(regs, RTW_CONFIG3); 313 PRINTREG8(regs, RTW_CONFIG4); 314 PRINTREG8(regs, RTW_TESTR); 315 PRINTREG8(regs, RTW_PSR); 316 PRINTREG8(regs, RTW_SCR); 317 PRINTREG8(regs, RTW_PHYDELAY); 318 PRINTREG8(regs, RTW_CRCOUNT); 319 PRINTREG8(regs, RTW_PHYADDR); 320 PRINTREG8(regs, RTW_PHYDATAW); 321 PRINTREG8(regs, RTW_PHYDATAR); 322 PRINTREG8(regs, RTW_CONFIG5); 323 PRINTREG8(regs, RTW_TPPOLL); 324 325 PRINTREG16(regs, RTW_BSSID16); 326 PRINTREG32(regs, RTW_BSSID32); 327 #undef PRINTREG32 328 #undef PRINTREG16 329 #undef PRINTREG8 330 } 331 #endif /* RTW_DEBUG */ 332 333 void 334 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 335 { 336 struct rtw_regs *regs = &sc->sc_regs; 337 338 uint32_t tcr; 339 tcr = RTW_READ(regs, RTW_TCR); 340 tcr &= ~RTW_TCR_LBK_MASK; 341 if (enable) 342 tcr |= RTW_TCR_LBK_CONT; 343 else 344 tcr |= RTW_TCR_LBK_NORMAL; 345 RTW_WRITE(regs, RTW_TCR, tcr); 346 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 347 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 348 rtw_txdac_enable(sc, !enable); 349 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 350 rtw_set_access(regs, RTW_ACCESS_NONE); 351 } 352 353 #ifdef RTW_DEBUG 354 static const char * 355 rtw_access_string(enum rtw_access access) 356 { 357 switch (access) { 358 case RTW_ACCESS_NONE: 359 return "none"; 360 case RTW_ACCESS_CONFIG: 361 return "config"; 362 case RTW_ACCESS_ANAPARM: 363 return "anaparm"; 364 default: 365 return "unknown"; 366 } 367 } 368 #endif /* RTW_DEBUG */ 369 370 static void 371 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 372 { 373 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 374 KASSERT(regs->r_access >= RTW_ACCESS_NONE && 375 regs->r_access <= RTW_ACCESS_ANAPARM); 376 377 if (naccess == regs->r_access) 378 return; 379 380 switch (naccess) { 381 case RTW_ACCESS_NONE: 382 switch (regs->r_access) { 383 case RTW_ACCESS_ANAPARM: 384 rtw_anaparm_enable(regs, 0); 385 /*FALLTHROUGH*/ 386 case RTW_ACCESS_CONFIG: 387 rtw_config0123_enable(regs, 0); 388 /*FALLTHROUGH*/ 389 case RTW_ACCESS_NONE: 390 break; 391 } 392 break; 393 case RTW_ACCESS_CONFIG: 394 switch (regs->r_access) { 395 case RTW_ACCESS_NONE: 396 rtw_config0123_enable(regs, 1); 397 /*FALLTHROUGH*/ 398 case RTW_ACCESS_CONFIG: 399 break; 400 case RTW_ACCESS_ANAPARM: 401 rtw_anaparm_enable(regs, 0); 402 break; 403 } 404 break; 405 case RTW_ACCESS_ANAPARM: 406 switch (regs->r_access) { 407 case RTW_ACCESS_NONE: 408 rtw_config0123_enable(regs, 1); 409 /*FALLTHROUGH*/ 410 case RTW_ACCESS_CONFIG: 411 rtw_anaparm_enable(regs, 1); 412 /*FALLTHROUGH*/ 413 case RTW_ACCESS_ANAPARM: 414 break; 415 } 416 break; 417 } 418 } 419 420 void 421 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 422 { 423 rtw_set_access1(regs, access); 424 RTW_DPRINTF(RTW_DEBUG_ACCESS, 425 ("%s: access %s -> %s\n", __func__, 426 rtw_access_string(regs->r_access), 427 rtw_access_string(access))); 428 regs->r_access = access; 429 } 430 431 /* 432 * Enable registers, switch register banks. 433 */ 434 void 435 rtw_config0123_enable(struct rtw_regs *regs, int enable) 436 { 437 uint8_t ecr; 438 ecr = RTW_READ8(regs, RTW_9346CR); 439 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 440 if (enable) 441 ecr |= RTW_9346CR_EEM_CONFIG; 442 else { 443 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 444 ecr |= RTW_9346CR_EEM_NORMAL; 445 } 446 RTW_WRITE8(regs, RTW_9346CR, ecr); 447 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 448 } 449 450 /* requires rtw_config0123_enable(, 1) */ 451 void 452 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 453 { 454 uint8_t cfg3; 455 456 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 457 cfg3 |= RTW_CONFIG3_CLKRUNEN; 458 if (enable) 459 cfg3 |= RTW_CONFIG3_PARMEN; 460 else 461 cfg3 &= ~RTW_CONFIG3_PARMEN; 462 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 463 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 464 } 465 466 /* requires rtw_anaparm_enable(, 1) */ 467 void 468 rtw_txdac_enable(struct rtw_softc *sc, int enable) 469 { 470 uint32_t anaparm; 471 struct rtw_regs *regs = &sc->sc_regs; 472 473 anaparm = RTW_READ(regs, RTW_ANAPARM); 474 if (enable) 475 anaparm &= ~RTW_ANAPARM_TXDACOFF; 476 else 477 anaparm |= RTW_ANAPARM_TXDACOFF; 478 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 479 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 480 } 481 482 static __inline int 483 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 484 { 485 uint8_t cr; 486 int i; 487 488 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 489 490 RTW_WBR(regs, RTW_CR, RTW_CR); 491 492 for (i = 0; i < 1000; i++) { 493 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 494 RTW_DPRINTF(RTW_DEBUG_RESET, 495 ("%s: reset in %dus\n", dvname, i)); 496 return 0; 497 } 498 RTW_RBR(regs, RTW_CR, RTW_CR); 499 DELAY(10); /* 10us */ 500 } 501 502 printf("%s: reset failed\n", dvname); 503 return ETIMEDOUT; 504 } 505 506 static __inline int 507 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 508 { 509 uint32_t tcr; 510 511 /* from Linux driver */ 512 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 513 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 514 515 RTW_WRITE(regs, RTW_TCR, tcr); 516 517 RTW_WBW(regs, RTW_CR, RTW_TCR); 518 519 return rtw_chip_reset1(regs, dvname); 520 } 521 522 static void 523 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_wepkey *wk, int txkey) 524 { 525 uint8_t cfg0, scr; 526 int i, j, tx_key_len; 527 struct rtw_regs *regs; 528 union rtw_keys *rk; 529 530 regs = &sc->sc_regs; 531 rk = &sc->sc_keys; 532 533 (void)memset(rk->rk_keys, 0, sizeof(rk->rk_keys)); 534 535 scr = RTW_READ8(regs, RTW_SCR); 536 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 537 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 538 cfg0 &= ~(RTW_CONFIG0_WEP104 | RTW_CONFIG0_WEP40); 539 540 rtw_set_access(regs, RTW_ACCESS_CONFIG); 541 542 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 543 goto out; 544 545 tx_key_len = wk[txkey].wk_len; 546 547 switch (tx_key_len) { 548 case 5: 549 scr |= RTW_SCR_TXSECON | RTW_SCR_RXSECON | RTW_SCR_KM_WEP40; 550 break; 551 case 13: 552 scr |= RTW_SCR_TXSECON | RTW_SCR_RXSECON | RTW_SCR_KM_WEP104; 553 break; 554 default: 555 goto out; 556 } 557 558 cfg0 |= RTW_CONFIG0_WEP104 | RTW_CONFIG0_WEP40; 559 560 for (i = j = 0; i < IEEE80211_WEP_NKID; i++) { 561 if (i == txkey) 562 sc->sc_txkey = j; 563 else if (wk[i].wk_len != tx_key_len) 564 continue; 565 (void)memcpy(rk->rk_keys[j++], wk[i].wk_key, wk[i].wk_len); 566 } 567 568 out: 569 bus_space_write_region_4(regs->r_bt, regs->r_bh, 570 RTW_DK0, rk->rk_words, 571 sizeof(rk->rk_words) / sizeof(rk->rk_words[0])); 572 573 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, 574 sizeof(rk->rk_words) / sizeof(rk->rk_words[0]), 575 BUS_SPACE_BARRIER_SYNC); 576 577 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 578 RTW_WBW(regs, RTW_CONFIG0, RTW_SCR); 579 RTW_WRITE8(regs, RTW_SCR, scr); 580 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 581 rtw_set_access(regs, RTW_ACCESS_NONE); 582 } 583 584 static __inline int 585 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 586 { 587 int i; 588 uint8_t ecr; 589 590 ecr = RTW_READ8(regs, RTW_9346CR); 591 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 592 RTW_WRITE8(regs, RTW_9346CR, ecr); 593 594 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 595 596 /* wait 2.5ms for completion */ 597 for (i = 0; i < 25; i++) { 598 ecr = RTW_READ8(regs, RTW_9346CR); 599 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 600 RTW_DPRINTF(RTW_DEBUG_RESET, 601 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 602 return 0; 603 } 604 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 605 DELAY(100); 606 } 607 printf("%s: recall EEPROM failed\n", dvname); 608 return ETIMEDOUT; 609 } 610 611 static __inline int 612 rtw_reset(struct rtw_softc *sc) 613 { 614 int rc; 615 uint8_t config1; 616 617 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 618 return rc; 619 620 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 621 ; 622 623 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 624 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 625 /* TBD turn off maximum power saving? */ 626 627 return 0; 628 } 629 630 static __inline int 631 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 632 u_int ndescs) 633 { 634 int i, rc = 0; 635 for (i = 0; i < ndescs; i++) { 636 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 637 0, 0, &descs[i].ts_dmamap); 638 if (rc != 0) 639 break; 640 } 641 return rc; 642 } 643 644 static __inline int 645 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 646 u_int ndescs) 647 { 648 int i, rc = 0; 649 for (i = 0; i < ndescs; i++) { 650 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 651 &descs[i].rs_dmamap); 652 if (rc != 0) 653 break; 654 } 655 return rc; 656 } 657 658 static __inline void 659 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 660 u_int ndescs) 661 { 662 int i; 663 for (i = 0; i < ndescs; i++) { 664 if (descs[i].rs_dmamap != NULL) 665 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 666 } 667 } 668 669 static __inline void 670 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 671 u_int ndescs) 672 { 673 int i; 674 for (i = 0; i < ndescs; i++) { 675 if (descs[i].ts_dmamap != NULL) 676 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 677 } 678 } 679 680 static __inline void 681 rtw_srom_free(struct rtw_srom *sr) 682 { 683 sr->sr_size = 0; 684 if (sr->sr_content == NULL) 685 return; 686 free(sr->sr_content, M_DEVBUF); 687 sr->sr_content = NULL; 688 } 689 690 static void 691 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 692 enum rtw_rfchipid *rfchipid, uint32_t *rcr) 693 { 694 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 695 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 696 *rcr |= RTW_RCR_ENCS1; 697 *rfchipid = RTW_RFCHIPID_PHILIPS; 698 } 699 700 static int 701 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 702 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 703 const char *dvname) 704 { 705 int i; 706 const char *rfname, *paname; 707 char scratch[sizeof("unknown 0xXX")]; 708 uint16_t srom_version; 709 uint8_t mac[IEEE80211_ADDR_LEN]; 710 711 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 712 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 713 714 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 715 printf("%s: SROM version %d.%d", dvname, 716 srom_version >> 8, srom_version & 0xff); 717 718 if (srom_version <= 0x0101) { 719 printf(" is not understood, limping along with defaults\n"); 720 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 721 return 0; 722 } 723 printf("\n"); 724 725 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 726 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 727 728 RTW_DPRINTF(RTW_DEBUG_ATTACH, 729 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 730 731 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 732 733 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 734 *flags |= RTW_F_ANTDIV; 735 736 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 737 * to be reversed. 738 */ 739 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 740 *flags |= RTW_F_DIGPHY; 741 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 742 *flags |= RTW_F_DFLANTB; 743 744 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 745 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 746 747 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 748 switch (*rfchipid) { 749 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 750 rfname = "GCT GRF5101"; 751 paname = "Winspring WS9901"; 752 break; 753 case RTW_RFCHIPID_MAXIM: 754 rfname = "Maxim MAX2820"; /* guess */ 755 paname = "Maxim MAX2422"; /* guess */ 756 break; 757 case RTW_RFCHIPID_INTERSIL: 758 rfname = "Intersil HFA3873"; /* guess */ 759 paname = "Intersil <unknown>"; 760 break; 761 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 762 rfname = "Philips SA2400A"; 763 paname = "Philips SA2411"; 764 break; 765 case RTW_RFCHIPID_RFMD: 766 /* this is the same front-end as an atw(4)! */ 767 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 768 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 769 "SYN: Silicon Labs Si4126"; /* inferred from 770 * reference driver 771 */ 772 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 773 break; 774 case RTW_RFCHIPID_RESERVED: 775 rfname = paname = "reserved"; 776 break; 777 default: 778 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 779 rfname = paname = scratch; 780 } 781 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 782 783 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 784 case RTW_CONFIG0_GL_USA: 785 *locale = RTW_LOCALE_USA; 786 break; 787 case RTW_CONFIG0_GL_EUROPE: 788 *locale = RTW_LOCALE_EUROPE; 789 break; 790 case RTW_CONFIG0_GL_JAPAN: 791 *locale = RTW_LOCALE_JAPAN; 792 break; 793 default: 794 *locale = RTW_LOCALE_UNKNOWN; 795 break; 796 } 797 return 0; 798 } 799 800 /* Returns -1 on failure. */ 801 static int 802 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 803 const char *dvname) 804 { 805 int rc; 806 struct seeprom_descriptor sd; 807 uint8_t ecr; 808 809 (void)memset(&sd, 0, sizeof(sd)); 810 811 ecr = RTW_READ8(regs, RTW_9346CR); 812 813 if ((flags & RTW_F_9356SROM) != 0) { 814 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 815 sr->sr_size = 256; 816 sd.sd_chip = C56_66; 817 } else { 818 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 819 sr->sr_size = 128; 820 sd.sd_chip = C46; 821 } 822 823 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 824 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 825 ecr |= RTW_9346CR_EEM_PROGRAM; 826 827 RTW_WRITE8(regs, RTW_9346CR, ecr); 828 829 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 830 831 if (sr->sr_content == NULL) { 832 printf("%s: unable to allocate SROM buffer\n", dvname); 833 return ENOMEM; 834 } 835 836 (void)memset(sr->sr_content, 0, sr->sr_size); 837 838 /* RTL8180 has a single 8-bit register for controlling the 839 * 93cx6 SROM. There is no "ready" bit. The RTL8180 840 * input/output sense is the reverse of read_seeprom's. 841 */ 842 sd.sd_tag = regs->r_bt; 843 sd.sd_bsh = regs->r_bh; 844 sd.sd_regsize = 1; 845 sd.sd_control_offset = RTW_9346CR; 846 sd.sd_status_offset = RTW_9346CR; 847 sd.sd_dataout_offset = RTW_9346CR; 848 sd.sd_CK = RTW_9346CR_EESK; 849 sd.sd_CS = RTW_9346CR_EECS; 850 sd.sd_DI = RTW_9346CR_EEDO; 851 sd.sd_DO = RTW_9346CR_EEDI; 852 /* make read_seeprom enter EEPROM read/write mode */ 853 sd.sd_MS = ecr; 854 sd.sd_RDY = 0; 855 856 /* TBD bus barriers */ 857 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 858 printf("%s: could not read SROM\n", dvname); 859 free(sr->sr_content, M_DEVBUF); 860 sr->sr_content = NULL; 861 return -1; /* XXX */ 862 } 863 864 /* end EEPROM read/write mode */ 865 RTW_WRITE8(regs, RTW_9346CR, 866 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 867 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 868 869 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 870 return rc; 871 872 #ifdef RTW_DEBUG 873 { 874 int i; 875 RTW_DPRINTF(RTW_DEBUG_ATTACH, 876 ("\n%s: serial ROM:\n\t", dvname)); 877 for (i = 0; i < sr->sr_size/2; i++) { 878 if (((i % 8) == 0) && (i != 0)) 879 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 880 RTW_DPRINTF(RTW_DEBUG_ATTACH, 881 (" %04x", sr->sr_content[i])); 882 } 883 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 884 } 885 #endif /* RTW_DEBUG */ 886 return 0; 887 } 888 889 static void 890 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 891 const char *dvname) 892 { 893 uint8_t cfg4; 894 const char *method; 895 896 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 897 898 switch (rfchipid) { 899 default: 900 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 901 method = "fallback"; 902 break; 903 case RTW_RFCHIPID_INTERSIL: 904 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 905 method = "Intersil"; 906 break; 907 case RTW_RFCHIPID_PHILIPS: 908 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 909 method = "Philips"; 910 break; 911 case RTW_RFCHIPID_GCT: /* XXX a guess */ 912 case RTW_RFCHIPID_RFMD: 913 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 914 method = "RFMD"; 915 break; 916 } 917 918 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 919 920 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 921 922 RTW_DPRINTF(RTW_DEBUG_INIT, 923 ("%s: %s RF programming method, %#02x\n", dvname, method, 924 RTW_READ8(regs, RTW_CONFIG4))); 925 } 926 927 static __inline void 928 rtw_init_channels(enum rtw_locale locale, 929 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 930 const char *dvname) 931 { 932 int i; 933 const char *name = NULL; 934 #define ADD_CHANNEL(_chans, _chan) do { \ 935 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 936 (*_chans)[_chan].ic_freq = \ 937 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 938 } while (0) 939 940 switch (locale) { 941 case RTW_LOCALE_USA: /* 1-11 */ 942 name = "USA"; 943 for (i = 1; i <= 11; i++) 944 ADD_CHANNEL(chans, i); 945 break; 946 case RTW_LOCALE_JAPAN: /* 1-14 */ 947 name = "Japan"; 948 ADD_CHANNEL(chans, 14); 949 for (i = 1; i <= 14; i++) 950 ADD_CHANNEL(chans, i); 951 break; 952 case RTW_LOCALE_EUROPE: /* 1-13 */ 953 name = "Europe"; 954 for (i = 1; i <= 13; i++) 955 ADD_CHANNEL(chans, i); 956 break; 957 default: /* 10-11 allowed by most countries */ 958 name = "<unknown>"; 959 for (i = 10; i <= 11; i++) 960 ADD_CHANNEL(chans, i); 961 break; 962 } 963 printf("%s: Geographic Location %s\n", dvname, name); 964 #undef ADD_CHANNEL 965 } 966 967 static __inline void 968 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 969 const char *dvname) 970 { 971 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 972 973 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 974 case RTW_CONFIG0_GL_USA: 975 *locale = RTW_LOCALE_USA; 976 break; 977 case RTW_CONFIG0_GL_JAPAN: 978 *locale = RTW_LOCALE_JAPAN; 979 break; 980 case RTW_CONFIG0_GL_EUROPE: 981 *locale = RTW_LOCALE_EUROPE; 982 break; 983 default: 984 *locale = RTW_LOCALE_UNKNOWN; 985 break; 986 } 987 } 988 989 static __inline int 990 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 991 const char *dvname) 992 { 993 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 994 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 995 }; 996 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 997 idr1 = RTW_READ(regs, RTW_IDR1); 998 999 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 1000 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 1001 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 1002 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 1003 1004 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 1005 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 1006 1007 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1008 printf("%s: could not get mac address, attach failed\n", 1009 dvname); 1010 return ENXIO; 1011 } 1012 1013 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 1014 1015 return 0; 1016 } 1017 1018 static uint8_t 1019 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1020 struct ieee80211_channel *chan) 1021 { 1022 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1023 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 1024 ("%s: channel %d out of range", __func__, 1025 idx - RTW_SR_TXPOWER1 + 1)); 1026 return RTW_SR_GET(sr, idx); 1027 } 1028 1029 static void 1030 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1031 { 1032 int pri; 1033 u_int ndesc[RTW_NTXPRI] = 1034 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 1035 1036 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1037 tdb[pri].tdb_nfree = ndesc[pri]; 1038 tdb[pri].tdb_next = 0; 1039 } 1040 } 1041 1042 static int 1043 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1044 { 1045 int i; 1046 struct rtw_txsoft *ts; 1047 1048 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1049 SIMPLEQ_INIT(&tsb->tsb_freeq); 1050 for (i = 0; i < tsb->tsb_ndesc; i++) { 1051 ts = &tsb->tsb_desc[i]; 1052 ts->ts_mbuf = NULL; 1053 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1054 } 1055 return 0; 1056 } 1057 1058 static void 1059 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1060 { 1061 int pri; 1062 for (pri = 0; pri < RTW_NTXPRI; pri++) 1063 rtw_txsoft_blk_init(&tsb[pri]); 1064 } 1065 1066 static __inline void 1067 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1068 { 1069 KASSERT(nsync <= rdb->rdb_ndesc); 1070 /* sync to end of ring */ 1071 if (desc0 + nsync > rdb->rdb_ndesc) { 1072 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1073 offsetof(struct rtw_descs, hd_rx[desc0]), 1074 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1075 nsync -= (rdb->rdb_ndesc - desc0); 1076 desc0 = 0; 1077 } 1078 1079 KASSERT(desc0 < rdb->rdb_ndesc); 1080 KASSERT(nsync <= rdb->rdb_ndesc); 1081 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1082 1083 /* sync what remains */ 1084 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1085 offsetof(struct rtw_descs, hd_rx[desc0]), 1086 sizeof(struct rtw_rxdesc) * nsync, ops); 1087 } 1088 1089 static void 1090 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1091 { 1092 /* sync to end of ring */ 1093 if (desc0 + nsync > tdb->tdb_ndesc) { 1094 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1095 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1096 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1097 ops); 1098 nsync -= (tdb->tdb_ndesc - desc0); 1099 desc0 = 0; 1100 } 1101 1102 /* sync what remains */ 1103 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1104 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1105 sizeof(struct rtw_txdesc) * nsync, ops); 1106 } 1107 1108 static void 1109 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1110 { 1111 int pri; 1112 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1113 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1114 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1115 } 1116 } 1117 1118 static void 1119 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1120 { 1121 int i; 1122 struct rtw_rxsoft *rs; 1123 1124 for (i = 0; i < RTW_RXQLEN; i++) { 1125 rs = &desc[i]; 1126 if (rs->rs_mbuf == NULL) 1127 continue; 1128 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1129 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1130 bus_dmamap_unload(dmat, rs->rs_dmamap); 1131 m_freem(rs->rs_mbuf); 1132 rs->rs_mbuf = NULL; 1133 } 1134 } 1135 1136 static __inline int 1137 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1138 { 1139 int rc; 1140 struct mbuf *m; 1141 1142 MGETHDR(m, M_DONTWAIT, MT_DATA); 1143 if (m == NULL) 1144 return ENOBUFS; 1145 1146 MCLGET(m, M_DONTWAIT); 1147 if ((m->m_flags & M_EXT) == 0) { 1148 m_freem(m); 1149 return ENOBUFS; 1150 } 1151 1152 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1153 1154 if (rs->rs_mbuf != NULL) 1155 bus_dmamap_unload(dmat, rs->rs_dmamap); 1156 1157 rs->rs_mbuf = NULL; 1158 1159 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1160 if (rc != 0) { 1161 m_freem(m); 1162 return -1; 1163 } 1164 1165 rs->rs_mbuf = m; 1166 1167 return 0; 1168 } 1169 1170 static int 1171 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1172 int *ndesc, const char *dvname) 1173 { 1174 int i, rc = 0; 1175 struct rtw_rxsoft *rs; 1176 1177 for (i = 0; i < RTW_RXQLEN; i++) { 1178 rs = &desc[i]; 1179 /* we're in rtw_init, so there should be no mbufs allocated */ 1180 KASSERT(rs->rs_mbuf == NULL); 1181 #ifdef RTW_DEBUG 1182 if (i == rtw_rxbufs_limit) { 1183 printf("%s: TEST hit %d-buffer limit\n", dvname, i); 1184 rc = ENOBUFS; 1185 break; 1186 } 1187 #endif /* RTW_DEBUG */ 1188 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1189 printf("%s: rtw_rxsoft_alloc failed, %d buffers, " 1190 "rc %d\n", dvname, i, rc); 1191 break; 1192 } 1193 } 1194 *ndesc = i; 1195 return rc; 1196 } 1197 1198 static __inline void 1199 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1200 int idx, int kick) 1201 { 1202 int is_last = (idx == rdb->rdb_ndesc - 1); 1203 uint32_t ctl, octl, obuf; 1204 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1205 1206 obuf = rd->rd_buf; 1207 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1208 1209 ctl = LSHIFT(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1210 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1211 1212 if (is_last) 1213 ctl |= RTW_RXCTL_EOR; 1214 1215 octl = rd->rd_ctl; 1216 rd->rd_ctl = htole32(ctl); 1217 1218 RTW_DPRINTF( 1219 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1220 : RTW_DEBUG_RECV_DESC, 1221 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1222 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1223 le32toh(rd->rd_ctl))); 1224 1225 /* sync the mbuf */ 1226 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1227 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1228 1229 /* sync the descriptor */ 1230 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1231 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1232 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1233 } 1234 1235 static void 1236 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1237 { 1238 int i; 1239 struct rtw_rxdesc *rd; 1240 struct rtw_rxsoft *rs; 1241 1242 for (i = 0; i < rdb->rdb_ndesc; i++) { 1243 rd = &rdb->rdb_desc[i]; 1244 rs = &ctl[i]; 1245 rtw_rxdesc_init(rdb, rs, i, kick); 1246 } 1247 rdb->rdb_next = 0; 1248 } 1249 1250 static void 1251 rtw_io_enable(struct rtw_regs *regs, uint8_t flags, int enable) 1252 { 1253 uint8_t cr; 1254 1255 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1256 enable ? "enable" : "disable", flags)); 1257 1258 cr = RTW_READ8(regs, RTW_CR); 1259 1260 /* XXX reference source does not enable MULRW */ 1261 #if 0 1262 /* enable PCI Read/Write Multiple */ 1263 cr |= RTW_CR_MULRW; 1264 #endif 1265 1266 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1267 if (enable) 1268 cr |= flags; 1269 else 1270 cr &= ~flags; 1271 RTW_WRITE8(regs, RTW_CR, cr); 1272 RTW_SYNC(regs, RTW_CR, RTW_CR); 1273 } 1274 1275 static void 1276 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1277 { 1278 #define IS_BEACON(__fc0) \ 1279 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1280 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1281 1282 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1283 * hardware -> net80211 1284 */ 1285 u_int next, nproc = 0; 1286 int hwrate, len, rate, rssi, sq; 1287 uint32_t hrssi, hstat, htsfth, htsftl; 1288 struct rtw_rxdesc *rd; 1289 struct rtw_rxsoft *rs; 1290 struct rtw_rxdesc_blk *rdb; 1291 struct mbuf *m; 1292 1293 struct ieee80211_node *ni; 1294 struct ieee80211_frame *wh; 1295 1296 rdb = &sc->sc_rxdesc_blk; 1297 1298 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1299 1300 for (next = rdb->rdb_next; ; next = (next + 1) % rdb->rdb_ndesc) { 1301 rtw_rxdescs_sync(rdb, next, 1, 1302 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1303 rd = &rdb->rdb_desc[next]; 1304 rs = &sc->sc_rxsoft[next]; 1305 1306 hstat = le32toh(rd->rd_stat); 1307 hrssi = le32toh(rd->rd_rssi); 1308 htsfth = le32toh(rd->rd_tsfth); 1309 htsftl = le32toh(rd->rd_tsftl); 1310 1311 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1312 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1313 __func__, next, hstat, hrssi, htsfth, htsftl)); 1314 1315 ++nproc; 1316 1317 /* still belongs to NIC */ 1318 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1319 if (nproc > 1) 1320 break; 1321 1322 /* sometimes the NIC skips to the 0th descriptor */ 1323 rtw_rxdescs_sync(rdb, 0, 1, 1324 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1325 rd = &rdb->rdb_desc[0]; 1326 if ((rd->rd_stat & htole32(RTW_RXSTAT_OWN)) != 0) 1327 break; 1328 RTW_DPRINTF(RTW_DEBUG_BUGS, 1329 ("%s: NIC skipped from rxdesc[%u] to rxdesc[0]\n", 1330 sc->sc_dev.dv_xname, next)); 1331 next = rdb->rdb_ndesc - 1; 1332 continue; 1333 } 1334 1335 #ifdef RTW_DEBUG 1336 #define PRINTSTAT(flag) do { \ 1337 if ((hstat & flag) != 0) { \ 1338 printf("%s" #flag, delim); \ 1339 delim = ","; \ 1340 } \ 1341 } while (0) 1342 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1343 const char *delim = "<"; 1344 printf("%s: ", sc->sc_dev.dv_xname); 1345 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1346 printf("status %08x", hstat); 1347 PRINTSTAT(RTW_RXSTAT_SPLCP); 1348 PRINTSTAT(RTW_RXSTAT_MAR); 1349 PRINTSTAT(RTW_RXSTAT_PAR); 1350 PRINTSTAT(RTW_RXSTAT_BAR); 1351 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1352 PRINTSTAT(RTW_RXSTAT_CRC32); 1353 PRINTSTAT(RTW_RXSTAT_ICV); 1354 printf(">, "); 1355 } 1356 } 1357 #endif /* RTW_DEBUG */ 1358 1359 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1360 printf("%s: DMA error/FIFO overflow %08x, " 1361 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1362 hstat & RTW_RXSTAT_IOERROR, next); 1363 sc->sc_if.if_ierrors++; 1364 goto next; 1365 } 1366 1367 len = MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1368 if (len < IEEE80211_MIN_LEN) { 1369 sc->sc_ic.ic_stats.is_rx_tooshort++; 1370 goto next; 1371 } 1372 1373 /* CRC is included with the packet; trim it off. */ 1374 len -= IEEE80211_CRC_LEN; 1375 1376 hwrate = MASK_AND_RSHIFT(hstat, RTW_RXSTAT_RATE_MASK); 1377 if (hwrate >= sizeof(ratetbl) / sizeof(ratetbl[0])) { 1378 printf("%s: unknown rate #%d\n", sc->sc_dev.dv_xname, 1379 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_RATE_MASK)); 1380 sc->sc_if.if_ierrors++; 1381 goto next; 1382 } 1383 rate = ratetbl[hwrate]; 1384 1385 #ifdef RTW_DEBUG 1386 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1387 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1388 (rate * 5) % 10, htsfth, htsftl)); 1389 #endif /* RTW_DEBUG */ 1390 1391 if ((hstat & RTW_RXSTAT_RES) != 0 && 1392 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1393 goto next; 1394 1395 /* if bad flags, skip descriptor */ 1396 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1397 printf("%s: too many rx segments\n", 1398 sc->sc_dev.dv_xname); 1399 goto next; 1400 } 1401 1402 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1403 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1404 1405 m = rs->rs_mbuf; 1406 1407 /* if temporarily out of memory, re-use mbuf */ 1408 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1409 case 0: 1410 break; 1411 case ENOBUFS: 1412 printf("%s: rtw_rxsoft_alloc(, %d) failed, " 1413 "dropping packet\n", sc->sc_dev.dv_xname, next); 1414 goto next; 1415 default: 1416 /* XXX shorten rx ring, instead? */ 1417 panic("%s: could not load DMA map\n", 1418 sc->sc_dev.dv_xname); 1419 } 1420 1421 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1422 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1423 else { 1424 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1425 /* TBD find out each front-end's LNA gain in the 1426 * front-end's units 1427 */ 1428 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1429 rssi |= 0x80; 1430 } 1431 sq = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_SQ); 1432 1433 /* Note well: now we cannot recycle the rs_mbuf unless 1434 * we restore its original length. 1435 */ 1436 m->m_pkthdr.rcvif = &sc->sc_if; 1437 m->m_pkthdr.len = m->m_len = len; 1438 1439 wh = mtod(m, struct ieee80211_frame *); 1440 1441 if (!IS_BEACON(wh->i_fc[0])) 1442 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1443 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1444 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1445 1446 sc->sc_tsfth = htsfth; 1447 1448 #ifdef RTW_DEBUG 1449 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 1450 (IFF_DEBUG|IFF_LINK2)) { 1451 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1452 rate, rssi); 1453 } 1454 #endif /* RTW_DEBUG */ 1455 1456 #if NBPFILTER > 0 1457 if (sc->sc_radiobpf != NULL) { 1458 struct ieee80211com *ic = &sc->sc_ic; 1459 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1460 1461 rr->rr_tsft = 1462 htole64(((uint64_t)htsfth << 32) | htsftl); 1463 1464 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1465 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE; 1466 1467 rr->rr_flags = 0; 1468 rr->rr_rate = rate; 1469 rr->rr_chan_freq = 1470 htole16(ic->ic_bss->ni_chan->ic_freq); 1471 rr->rr_chan_flags = 1472 htole16(ic->ic_bss->ni_chan->ic_flags); 1473 rr->rr_antsignal = rssi; 1474 rr->rr_barker_lock = htole16(sq); 1475 1476 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rr, 1477 sizeof(sc->sc_rxtapu), m); 1478 } 1479 #endif /* NPBFILTER > 0 */ 1480 1481 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1482 ieee80211_release_node(&sc->sc_ic, ni); 1483 next: 1484 rtw_rxdesc_init(rdb, rs, next, 0); 1485 } 1486 rdb->rdb_next = next; 1487 1488 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1489 1490 return; 1491 #undef IS_BEACON 1492 } 1493 1494 static void 1495 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1496 struct rtw_txsoft *ts) 1497 { 1498 struct mbuf *m; 1499 struct ieee80211_node *ni; 1500 1501 m = ts->ts_mbuf; 1502 ni = ts->ts_ni; 1503 KASSERT(m != NULL); 1504 KASSERT(ni != NULL); 1505 ts->ts_mbuf = NULL; 1506 ts->ts_ni = NULL; 1507 1508 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1509 BUS_DMASYNC_POSTWRITE); 1510 bus_dmamap_unload(dmat, ts->ts_dmamap); 1511 m_freem(m); 1512 ieee80211_release_node(ic, ni); 1513 } 1514 1515 static void 1516 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1517 struct rtw_txsoft_blk *tsb) 1518 { 1519 struct rtw_txsoft *ts; 1520 1521 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1522 rtw_txsoft_release(dmat, ic, ts); 1523 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1524 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1525 } 1526 } 1527 1528 static __inline void 1529 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1530 struct rtw_txsoft *ts, int ndesc) 1531 { 1532 uint32_t hstat; 1533 int data_retry, rts_retry; 1534 struct rtw_txdesc *tdn; 1535 const char *condstring; 1536 1537 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1538 1539 tdb->tdb_nfree += ndesc; 1540 1541 tdn = &tdb->tdb_desc[ts->ts_last]; 1542 1543 hstat = le32toh(tdn->td_stat); 1544 rts_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1545 data_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_DRC_MASK); 1546 1547 sc->sc_if.if_collisions += rts_retry + data_retry; 1548 1549 if ((hstat & RTW_TXSTAT_TOK) != 0) 1550 condstring = "ok"; 1551 else { 1552 sc->sc_if.if_oerrors++; 1553 condstring = "error"; 1554 } 1555 1556 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1557 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1558 sc->sc_dev.dv_xname, ts, ts->ts_first, ts->ts_last, 1559 condstring, rts_retry, data_retry)); 1560 } 1561 1562 /* Collect transmitted packets. */ 1563 static __inline void 1564 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1565 struct rtw_txdesc_blk *tdb) 1566 { 1567 int ndesc; 1568 struct rtw_txsoft *ts; 1569 1570 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1571 ndesc = 1 + ts->ts_last - ts->ts_first; 1572 if (ts->ts_last < ts->ts_first) 1573 ndesc += tdb->tdb_ndesc; 1574 1575 KASSERT(ndesc > 0); 1576 1577 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1578 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1579 1580 if ((tdb->tdb_desc[ts->ts_last].td_stat & 1581 htole32(RTW_TXSTAT_OWN)) != 0) 1582 break; 1583 1584 if (&sc->sc_txdesc_blk[RTW_TXPRIBCN] == tdb) { 1585 RTW_DPRINTF(RTW_DEBUG_BEACON, 1586 ("%s: collected beacon\n", __func__)); 1587 } 1588 1589 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1590 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1591 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1592 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1593 } 1594 if (ts == NULL) 1595 tsb->tsb_tx_timer = 0; 1596 } 1597 1598 static void 1599 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1600 { 1601 int pri; 1602 struct rtw_txsoft_blk *tsb; 1603 struct rtw_txdesc_blk *tdb; 1604 1605 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1606 tsb = &sc->sc_txsoft_blk[pri]; 1607 tdb = &sc->sc_txdesc_blk[pri]; 1608 1609 rtw_collect_txring(sc, tsb, tdb); 1610 1611 if ((isr & RTW_INTR_TX) != 0) 1612 rtw_start(&sc->sc_if); 1613 } 1614 1615 /* TBD */ 1616 return; 1617 } 1618 1619 static void 1620 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1621 { 1622 /* TBD */ 1623 return; 1624 } 1625 1626 static void 1627 rtw_intr_atim(struct rtw_softc *sc) 1628 { 1629 /* TBD */ 1630 return; 1631 } 1632 1633 #ifdef RTW_DEBUG 1634 static void 1635 rtw_dump_rings(struct rtw_softc *sc) 1636 { 1637 struct rtw_txdesc_blk *tdb; 1638 struct rtw_rxdesc *rd; 1639 struct rtw_rxdesc_blk *rdb; 1640 int desc, pri; 1641 1642 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1643 return; 1644 1645 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1646 tdb = &sc->sc_txdesc_blk[pri]; 1647 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1648 tdb->tdb_ndesc, tdb->tdb_nfree); 1649 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1650 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1651 } 1652 1653 rdb = &sc->sc_rxdesc_blk; 1654 1655 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1656 rd = &rdb->rdb_desc[desc]; 1657 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1658 "rsvd1/tsfth %08x\n", __func__, 1659 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1660 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1661 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1662 } 1663 } 1664 #endif /* RTW_DEBUG */ 1665 1666 static void 1667 rtw_hwring_setup(struct rtw_softc *sc) 1668 { 1669 struct rtw_regs *regs = &sc->sc_regs; 1670 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1671 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1672 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1673 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1674 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1675 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1676 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1677 ("%s: reg[TLPDA] <- %" PRIxPTR "\n", __func__, 1678 (uintptr_t)RTW_RING_BASE(sc, hd_txlo))); 1679 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1680 ("%s: reg[TNPDA] <- %" PRIxPTR "\n", __func__, 1681 (uintptr_t)RTW_RING_BASE(sc, hd_txmd))); 1682 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1683 ("%s: reg[THPDA] <- %" PRIxPTR "\n", __func__, 1684 (uintptr_t)RTW_RING_BASE(sc, hd_txhi))); 1685 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1686 ("%s: reg[TBDA] <- %" PRIxPTR "\n", __func__, 1687 (uintptr_t)RTW_RING_BASE(sc, hd_bcn))); 1688 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1689 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1690 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1691 } 1692 1693 static int 1694 rtw_swring_setup(struct rtw_softc *sc) 1695 { 1696 int rc; 1697 struct rtw_rxdesc_blk *rdb; 1698 1699 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1700 1701 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1702 1703 rdb = &sc->sc_rxdesc_blk; 1704 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1705 sc->sc_dev.dv_xname)) != 0 && rdb->rdb_ndesc == 0) { 1706 printf("%s: could not allocate rx buffers\n", 1707 sc->sc_dev.dv_xname); 1708 return rc; 1709 } 1710 1711 rdb = &sc->sc_rxdesc_blk; 1712 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1713 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1714 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1715 1716 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1717 return 0; 1718 } 1719 1720 static void 1721 rtw_txdesc_blk_reset(struct rtw_txdesc_blk *tdb) 1722 { 1723 int i; 1724 1725 (void)memset(tdb->tdb_desc, 0, 1726 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 1727 for (i = 0; i < tdb->tdb_ndesc; i++) 1728 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 1729 tdb->tdb_nfree = tdb->tdb_ndesc; 1730 tdb->tdb_next = 0; 1731 } 1732 1733 static void 1734 rtw_txdescs_reset(struct rtw_softc *sc) 1735 { 1736 int pri; 1737 struct rtw_txdesc_blk *tdb; 1738 1739 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1740 tdb = &sc->sc_txdesc_blk[pri]; 1741 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 1742 &sc->sc_txsoft_blk[pri]); 1743 rtw_txdesc_blk_reset(tdb); 1744 rtw_txdescs_sync(tdb, 0, tdb->tdb_ndesc, 1745 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1746 } 1747 } 1748 1749 static void 1750 rtw_rxdescs_reset(struct rtw_softc *sc) 1751 { 1752 rtw_rxdesc_init_all(&sc->sc_rxdesc_blk, &sc->sc_rxsoft[0], 1); 1753 } 1754 1755 static void 1756 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 1757 { 1758 struct rtw_regs *regs = &sc->sc_regs; 1759 1760 if ((isr & RTW_INTR_TXFOVW) != 0) 1761 printf("%s: tx fifo overflow\n", sc->sc_dev.dv_xname); 1762 1763 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) == 0) 1764 return; 1765 1766 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: restarting xmit/recv, isr %" PRIx16 1767 "\n", sc->sc_dev.dv_xname, isr)); 1768 1769 #ifdef RTW_DEBUG 1770 rtw_dump_rings(sc); 1771 #endif /* RTW_DEBUG */ 1772 1773 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1774 1775 /* Collect rx'd packets. Refresh rx buffers. */ 1776 rtw_intr_rx(sc, 0); 1777 /* Collect tx'd packets. */ 1778 rtw_intr_tx(sc, 0); 1779 1780 RTW_WRITE16(regs, RTW_IMR, 0); 1781 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1782 1783 rtw_chip_reset1(regs, sc->sc_dev.dv_xname); 1784 1785 rtw_rxdescs_reset(sc); 1786 rtw_txdescs_reset(sc); 1787 1788 rtw_hwring_setup(sc); 1789 1790 #ifdef RTW_DEBUG 1791 rtw_dump_rings(sc); 1792 #endif /* RTW_DEBUG */ 1793 1794 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1795 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1796 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1797 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1798 } 1799 1800 static __inline void 1801 rtw_suspend_ticks(struct rtw_softc *sc) 1802 { 1803 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1804 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 1805 sc->sc_do_tick = 0; 1806 } 1807 1808 static __inline void 1809 rtw_resume_ticks(struct rtw_softc *sc) 1810 { 1811 uint32_t tsftrl0, tsftrl1, next_tick; 1812 1813 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1814 1815 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1816 next_tick = tsftrl1 + 1000000; 1817 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1818 1819 sc->sc_do_tick = 1; 1820 1821 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1822 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1823 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 1824 } 1825 1826 static void 1827 rtw_intr_timeout(struct rtw_softc *sc) 1828 { 1829 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 1830 if (sc->sc_do_tick) 1831 rtw_resume_ticks(sc); 1832 return; 1833 } 1834 1835 int 1836 rtw_intr(void *arg) 1837 { 1838 int i; 1839 struct rtw_softc *sc = arg; 1840 struct rtw_regs *regs = &sc->sc_regs; 1841 uint16_t isr; 1842 1843 /* 1844 * If the interface isn't running, the interrupt couldn't 1845 * possibly have come from us. 1846 */ 1847 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1848 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1849 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1850 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1851 return (0); 1852 } 1853 1854 for (i = 0; i < 10; i++) { 1855 isr = RTW_READ16(regs, RTW_ISR); 1856 1857 RTW_WRITE16(regs, RTW_ISR, isr); 1858 RTW_WBR(regs, RTW_ISR, RTW_ISR); 1859 1860 if (sc->sc_intr_ack != NULL) 1861 (*sc->sc_intr_ack)(regs); 1862 1863 if (isr == 0) 1864 break; 1865 1866 #ifdef RTW_DEBUG 1867 #define PRINTINTR(flag) do { \ 1868 if ((isr & flag) != 0) { \ 1869 printf("%s" #flag, delim); \ 1870 delim = ","; \ 1871 } \ 1872 } while (0) 1873 1874 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 1875 const char *delim = "<"; 1876 1877 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1878 1879 PRINTINTR(RTW_INTR_TXFOVW); 1880 PRINTINTR(RTW_INTR_TIMEOUT); 1881 PRINTINTR(RTW_INTR_BCNINT); 1882 PRINTINTR(RTW_INTR_ATIMINT); 1883 PRINTINTR(RTW_INTR_TBDER); 1884 PRINTINTR(RTW_INTR_TBDOK); 1885 PRINTINTR(RTW_INTR_THPDER); 1886 PRINTINTR(RTW_INTR_THPDOK); 1887 PRINTINTR(RTW_INTR_TNPDER); 1888 PRINTINTR(RTW_INTR_TNPDOK); 1889 PRINTINTR(RTW_INTR_RXFOVW); 1890 PRINTINTR(RTW_INTR_RDU); 1891 PRINTINTR(RTW_INTR_TLPDER); 1892 PRINTINTR(RTW_INTR_TLPDOK); 1893 PRINTINTR(RTW_INTR_RER); 1894 PRINTINTR(RTW_INTR_ROK); 1895 1896 printf(">\n"); 1897 } 1898 #undef PRINTINTR 1899 #endif /* RTW_DEBUG */ 1900 1901 if ((isr & RTW_INTR_RX) != 0) 1902 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1903 if ((isr & RTW_INTR_TX) != 0) 1904 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1905 if ((isr & RTW_INTR_BEACON) != 0) 1906 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1907 if ((isr & RTW_INTR_ATIMINT) != 0) 1908 rtw_intr_atim(sc); 1909 if ((isr & RTW_INTR_IOERROR) != 0) 1910 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1911 if ((isr & RTW_INTR_TIMEOUT) != 0) 1912 rtw_intr_timeout(sc); 1913 } 1914 1915 return 1; 1916 } 1917 1918 /* Must be called at splnet. */ 1919 static void 1920 rtw_stop(struct ifnet *ifp, int disable) 1921 { 1922 int pri; 1923 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1924 struct ieee80211com *ic = &sc->sc_ic; 1925 struct rtw_regs *regs = &sc->sc_regs; 1926 1927 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1928 return; 1929 1930 rtw_suspend_ticks(sc); 1931 1932 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1933 1934 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1935 /* Disable interrupts. */ 1936 RTW_WRITE16(regs, RTW_IMR, 0); 1937 1938 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 1939 1940 /* Stop the transmit and receive processes. First stop DMA, 1941 * then disable receiver and transmitter. 1942 */ 1943 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 1944 1945 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 1946 1947 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1948 } 1949 1950 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1951 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 1952 &sc->sc_txsoft_blk[pri]); 1953 } 1954 1955 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 1956 1957 if (disable) 1958 rtw_disable(sc); 1959 1960 /* Mark the interface as not running. Cancel the watchdog timer. */ 1961 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1962 ifp->if_timer = 0; 1963 1964 return; 1965 } 1966 1967 const char * 1968 rtw_pwrstate_string(enum rtw_pwrstate power) 1969 { 1970 switch (power) { 1971 case RTW_ON: 1972 return "on"; 1973 case RTW_SLEEP: 1974 return "sleep"; 1975 case RTW_OFF: 1976 return "off"; 1977 default: 1978 return "unknown"; 1979 } 1980 } 1981 1982 /* XXX For Maxim, I am using the RFMD settings gleaned from the 1983 * reference driver, plus a magic Maxim "ON" value that comes from 1984 * the Realtek document "Windows PG for Rtl8180." 1985 */ 1986 static void 1987 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1988 int before_rf, int digphy) 1989 { 1990 uint32_t anaparm; 1991 1992 anaparm = RTW_READ(regs, RTW_ANAPARM); 1993 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 1994 1995 switch (power) { 1996 case RTW_OFF: 1997 if (before_rf) 1998 return; 1999 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2000 anaparm |= RTW_ANAPARM_TXDACOFF; 2001 break; 2002 case RTW_SLEEP: 2003 if (!before_rf) 2004 return; 2005 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2006 anaparm |= RTW_ANAPARM_TXDACOFF; 2007 break; 2008 case RTW_ON: 2009 if (!before_rf) 2010 return; 2011 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2012 break; 2013 } 2014 RTW_DPRINTF(RTW_DEBUG_PWR, 2015 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2016 __func__, rtw_pwrstate_string(power), 2017 (before_rf) ? "before" : "after", anaparm)); 2018 2019 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2020 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2021 } 2022 2023 /* XXX I am using the RFMD settings gleaned from the reference 2024 * driver. They agree 2025 */ 2026 static void 2027 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2028 int before_rf, int digphy) 2029 { 2030 uint32_t anaparm; 2031 2032 anaparm = RTW_READ(regs, RTW_ANAPARM); 2033 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2034 2035 switch (power) { 2036 case RTW_OFF: 2037 if (before_rf) 2038 return; 2039 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2040 anaparm |= RTW_ANAPARM_TXDACOFF; 2041 break; 2042 case RTW_SLEEP: 2043 if (!before_rf) 2044 return; 2045 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2046 anaparm |= RTW_ANAPARM_TXDACOFF; 2047 break; 2048 case RTW_ON: 2049 if (!before_rf) 2050 return; 2051 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2052 break; 2053 } 2054 RTW_DPRINTF(RTW_DEBUG_PWR, 2055 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2056 __func__, rtw_pwrstate_string(power), 2057 (before_rf) ? "before" : "after", anaparm)); 2058 2059 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2060 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2061 } 2062 2063 static void 2064 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2065 int before_rf, int digphy) 2066 { 2067 uint32_t anaparm; 2068 2069 anaparm = RTW_READ(regs, RTW_ANAPARM); 2070 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2071 2072 switch (power) { 2073 case RTW_OFF: 2074 if (before_rf) 2075 return; 2076 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2077 anaparm |= RTW_ANAPARM_TXDACOFF; 2078 break; 2079 case RTW_SLEEP: 2080 if (!before_rf) 2081 return; 2082 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2083 anaparm |= RTW_ANAPARM_TXDACOFF; 2084 break; 2085 case RTW_ON: 2086 if (!before_rf) 2087 return; 2088 if (digphy) { 2089 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2090 /* XXX guess */ 2091 anaparm |= RTW_ANAPARM_TXDACOFF; 2092 } else 2093 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2094 break; 2095 } 2096 RTW_DPRINTF(RTW_DEBUG_PWR, 2097 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2098 __func__, rtw_pwrstate_string(power), 2099 (before_rf) ? "before" : "after", anaparm)); 2100 2101 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2102 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2103 } 2104 2105 static void 2106 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2107 int digphy) 2108 { 2109 struct rtw_regs *regs = &sc->sc_regs; 2110 2111 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2112 2113 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2114 2115 rtw_set_access(regs, RTW_ACCESS_NONE); 2116 2117 return; 2118 } 2119 2120 static int 2121 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2122 { 2123 int rc; 2124 2125 RTW_DPRINTF(RTW_DEBUG_PWR, 2126 ("%s: %s->%s\n", __func__, 2127 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2128 2129 if (sc->sc_pwrstate == power) 2130 return 0; 2131 2132 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2133 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2134 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2135 2136 switch (power) { 2137 case RTW_ON: 2138 /* TBD set LEDs */ 2139 break; 2140 case RTW_SLEEP: 2141 /* TBD */ 2142 break; 2143 case RTW_OFF: 2144 /* TBD */ 2145 break; 2146 } 2147 if (rc == 0) 2148 sc->sc_pwrstate = power; 2149 else 2150 sc->sc_pwrstate = RTW_OFF; 2151 return rc; 2152 } 2153 2154 static int 2155 rtw_tune(struct rtw_softc *sc) 2156 { 2157 struct ieee80211com *ic = &sc->sc_ic; 2158 u_int chan; 2159 int rc; 2160 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2161 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2162 2163 KASSERT(ic->ic_bss->ni_chan != NULL); 2164 2165 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2166 if (chan == IEEE80211_CHAN_ANY) 2167 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 2168 2169 if (chan == sc->sc_cur_chan) { 2170 RTW_DPRINTF(RTW_DEBUG_TUNE, 2171 ("%s: already tuned chan #%d\n", __func__, chan)); 2172 return 0; 2173 } 2174 2175 rtw_suspend_ticks(sc); 2176 2177 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 2178 2179 /* TBD wait for Tx to complete */ 2180 2181 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2182 2183 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2184 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 2185 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 2186 dflantb, RTW_ON)) != 0) { 2187 /* XXX condition on powersaving */ 2188 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2189 } 2190 2191 sc->sc_cur_chan = chan; 2192 2193 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 2194 2195 rtw_resume_ticks(sc); 2196 2197 return rc; 2198 } 2199 2200 void 2201 rtw_disable(struct rtw_softc *sc) 2202 { 2203 int rc; 2204 2205 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2206 return; 2207 2208 /* turn off PHY */ 2209 if ((sc->sc_flags & RTW_F_INVALID) == 0 && 2210 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2211 printf("%s: failed to turn off PHY (%d)\n", 2212 sc->sc_dev.dv_xname, rc); 2213 } 2214 2215 if (sc->sc_disable != NULL) 2216 (*sc->sc_disable)(sc); 2217 2218 sc->sc_flags &= ~RTW_F_ENABLED; 2219 } 2220 2221 int 2222 rtw_enable(struct rtw_softc *sc) 2223 { 2224 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2225 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2226 printf("%s: device enable failed\n", 2227 sc->sc_dev.dv_xname); 2228 return (EIO); 2229 } 2230 sc->sc_flags |= RTW_F_ENABLED; 2231 } 2232 return (0); 2233 } 2234 2235 static void 2236 rtw_transmit_config(struct rtw_regs *regs) 2237 { 2238 uint32_t tcr; 2239 2240 tcr = RTW_READ(regs, RTW_TCR); 2241 2242 tcr |= RTW_TCR_CWMIN; 2243 tcr &= ~RTW_TCR_MXDMA_MASK; 2244 tcr |= RTW_TCR_MXDMA_256; 2245 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2246 tcr &= ~RTW_TCR_LBK_MASK; 2247 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2248 2249 /* set short/long retry limits */ 2250 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2251 tcr |= LSHIFT(4, RTW_TCR_SRL_MASK) | LSHIFT(4, RTW_TCR_LRL_MASK); 2252 2253 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2254 2255 RTW_WRITE(regs, RTW_TCR, tcr); 2256 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2257 } 2258 2259 static __inline void 2260 rtw_enable_interrupts(struct rtw_softc *sc) 2261 { 2262 struct rtw_regs *regs = &sc->sc_regs; 2263 2264 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2265 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2266 2267 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2268 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2269 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2270 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2271 2272 /* XXX necessary? */ 2273 if (sc->sc_intr_ack != NULL) 2274 (*sc->sc_intr_ack)(regs); 2275 } 2276 2277 static void 2278 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2279 { 2280 uint8_t msr; 2281 2282 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2283 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2284 2285 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2286 2287 switch (opmode) { 2288 case IEEE80211_M_AHDEMO: 2289 case IEEE80211_M_IBSS: 2290 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2291 break; 2292 case IEEE80211_M_HOSTAP: 2293 msr |= RTW_MSR_NETYPE_AP_OK; 2294 break; 2295 case IEEE80211_M_MONITOR: 2296 /* XXX */ 2297 msr |= RTW_MSR_NETYPE_NOLINK; 2298 break; 2299 case IEEE80211_M_STA: 2300 msr |= RTW_MSR_NETYPE_INFRA_OK; 2301 break; 2302 } 2303 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2304 2305 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2306 } 2307 2308 #define rtw_calchash(addr) \ 2309 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2310 2311 static void 2312 rtw_pktfilt_load(struct rtw_softc *sc) 2313 { 2314 struct rtw_regs *regs = &sc->sc_regs; 2315 struct ieee80211com *ic = &sc->sc_ic; 2316 struct ethercom *ec = &ic->ic_ec; 2317 struct ifnet *ifp = &sc->sc_ic.ic_if; 2318 int hash; 2319 uint32_t hashes[2] = { 0, 0 }; 2320 struct ether_multi *enm; 2321 struct ether_multistep step; 2322 2323 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2324 2325 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2326 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2327 2328 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2329 /* MAC auto-reset PHY (huh?) */ 2330 sc->sc_rcr |= RTW_RCR_ENMARP; 2331 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2332 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2333 2334 switch (ic->ic_opmode) { 2335 case IEEE80211_M_MONITOR: 2336 sc->sc_rcr |= RTW_RCR_MONITOR; 2337 break; 2338 case IEEE80211_M_AHDEMO: 2339 case IEEE80211_M_IBSS: 2340 /* receive broadcasts in our BSS */ 2341 sc->sc_rcr |= RTW_RCR_ADD3; 2342 break; 2343 default: 2344 break; 2345 } 2346 2347 ifp->if_flags &= ~IFF_ALLMULTI; 2348 2349 /* XXX accept all broadcast if scanning */ 2350 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2351 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2352 2353 if (ifp->if_flags & IFF_PROMISC) { 2354 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2355 allmulti: 2356 ifp->if_flags |= IFF_ALLMULTI; 2357 goto setit; 2358 } 2359 2360 /* 2361 * Program the 64-bit multicast hash filter. 2362 */ 2363 ETHER_FIRST_MULTI(step, ec, enm); 2364 while (enm != NULL) { 2365 /* XXX */ 2366 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2367 ETHER_ADDR_LEN) != 0) 2368 goto allmulti; 2369 2370 hash = rtw_calchash(enm->enm_addrlo); 2371 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2372 sc->sc_rcr |= RTW_RCR_AM; 2373 ETHER_NEXT_MULTI(step, enm); 2374 } 2375 2376 /* all bits set => hash is useless */ 2377 if (~(hashes[0] & hashes[1]) == 0) 2378 goto allmulti; 2379 2380 setit: 2381 if (ifp->if_flags & IFF_ALLMULTI) { 2382 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2383 hashes[0] = hashes[1] = 0xffffffff; 2384 } 2385 2386 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2387 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2388 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2389 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2390 2391 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2392 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2393 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2394 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2395 2396 return; 2397 } 2398 2399 #define IEEE80211_BEACON_TIMESTAMP_LEN 8 2400 #define IEEE80211_BEACON_BINTVL_LEN 2 2401 #define IEEE80211_BEACON_CAPINFO_LEN 2 2402 #define IEEE80211_TLV_SSID_LEN(__esslen) (2 + (__esslen)) 2403 #define IEEE80211_TLV_SUPRATES_LEN(__nrates) (2 + (__nrates)) 2404 #define IEEE80211_TLV_XSUPRATES_LEN(__nrates) (2 + (__nrates)) 2405 #define IEEE80211_TLV_DSPARMS_LEN 3 2406 #define IEEE80211_TLV_IBSSPARMS 4 2407 #define IEEE80211_TLV_MIN_TIM 6 2408 2409 #define IEEE80211_TLV_ALLRATES_LEN(__nrates) \ 2410 (((__nrates) > IEEE80211_RATE_SIZE) ? 4 + (__nrates) : 2 + (__nrates)) 2411 2412 /* TBD factor with ieee80211_getmbuf */ 2413 static struct mbuf * 2414 rtw_getmbuf(int flags, int type, u_int pktlen) 2415 { 2416 struct mbuf *m; 2417 2418 KASSERT2(pktlen <= MCLBYTES, ("802.11 packet too large: %u", pktlen)); 2419 MGETHDR(m, flags, type); 2420 if (m == NULL || pktlen <= MHLEN) 2421 return m; 2422 MCLGET(m, flags); 2423 if ((m->m_flags & M_EXT) != 0) 2424 return m; 2425 m_free(m); 2426 return NULL; 2427 } 2428 2429 /* TBD factor with ath_beacon_alloc */ 2430 static struct mbuf * 2431 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2432 { 2433 struct ieee80211com *ic = &sc->sc_ic; 2434 struct ifnet *ifp = &ic->ic_if; 2435 struct ieee80211_frame *wh; 2436 struct mbuf *m; 2437 int pktlen; 2438 uint8_t *frm; 2439 uint16_t capinfo; 2440 struct ieee80211_rateset *rs; 2441 2442 /* 2443 * NB: the beacon data buffer must be 32-bit aligned; 2444 * we assume the mbuf routines will return us something 2445 * with this alignment (perhaps should assert). 2446 */ 2447 rs = &ni->ni_rates; 2448 pktlen = sizeof(struct ieee80211_frame) 2449 + IEEE80211_BEACON_TIMESTAMP_LEN 2450 + IEEE80211_BEACON_BINTVL_LEN 2451 + IEEE80211_BEACON_CAPINFO_LEN 2452 + IEEE80211_TLV_SSID_LEN(ni->ni_esslen) 2453 + IEEE80211_TLV_ALLRATES_LEN(rs->rs_nrates) 2454 + IEEE80211_TLV_DSPARMS_LEN 2455 + MAX(IEEE80211_TLV_IBSSPARMS, IEEE80211_TLV_MIN_TIM); 2456 2457 m = rtw_getmbuf(M_DONTWAIT, MT_DATA, pktlen); 2458 if (m == NULL) { 2459 RTW_DPRINTF(RTW_DEBUG_BEACON, 2460 ("%s: cannot get mbuf/cluster; size %u\n", 2461 __func__, pktlen)); 2462 #if 0 2463 sc->sc_stats.ast_be_nombuf++; 2464 #endif 2465 return NULL; 2466 } 2467 2468 wh = mtod(m, struct ieee80211_frame *); 2469 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 2470 IEEE80211_FC0_SUBTYPE_BEACON; 2471 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 2472 *(u_int16_t *)wh->i_dur = 0; 2473 memcpy(wh->i_addr1, ifp->if_broadcastaddr, IEEE80211_ADDR_LEN); 2474 memcpy(wh->i_addr2, ic->ic_myaddr, IEEE80211_ADDR_LEN); 2475 memcpy(wh->i_addr3, ni->ni_bssid, IEEE80211_ADDR_LEN); 2476 *(u_int16_t *)wh->i_seq = 0; 2477 2478 /* 2479 * beacon frame format 2480 * [8] time stamp 2481 * [2] beacon interval 2482 * [2] cabability information 2483 * [tlv] ssid 2484 * [tlv] supported rates 2485 * [tlv] parameter set (IBSS) 2486 * [tlv] extended supported rates 2487 */ 2488 frm = (u_int8_t *)&wh[1]; 2489 /* timestamp is set by hardware */ 2490 memset(frm, 0, IEEE80211_BEACON_TIMESTAMP_LEN); 2491 frm += IEEE80211_BEACON_TIMESTAMP_LEN; 2492 *(u_int16_t *)frm = htole16(ni->ni_intval); 2493 frm += IEEE80211_BEACON_BINTVL_LEN; 2494 if (ic->ic_opmode == IEEE80211_M_IBSS) 2495 capinfo = IEEE80211_CAPINFO_IBSS; 2496 else 2497 capinfo = IEEE80211_CAPINFO_ESS; 2498 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2499 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2500 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2501 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2502 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2503 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2504 capinfo |= IEEE80211_CAPINFO_SHORT_SLOTTIME; 2505 *(u_int16_t *)frm = htole16(capinfo); 2506 frm += IEEE80211_BEACON_CAPINFO_LEN; 2507 *frm++ = IEEE80211_ELEMID_SSID; 2508 *frm++ = ni->ni_esslen; 2509 memcpy(frm, ni->ni_essid, ni->ni_esslen); 2510 frm += ni->ni_esslen; 2511 frm = ieee80211_add_rates(frm, rs); 2512 *frm++ = IEEE80211_ELEMID_DSPARMS; 2513 *frm++ = 1; 2514 *frm++ = ieee80211_chan2ieee(ic, ni->ni_chan); 2515 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2516 *frm++ = IEEE80211_ELEMID_IBSSPARMS; 2517 *frm++ = 2; 2518 *frm++ = 0; *frm++ = 0; /* TODO: ATIM window */ 2519 } else { 2520 /* TODO: TIM */ 2521 *frm++ = IEEE80211_ELEMID_TIM; 2522 *frm++ = 4; /* length */ 2523 *frm++ = 0; /* DTIM count */ 2524 *frm++ = 1; /* DTIM period */ 2525 *frm++ = 0; /* bitmap control */ 2526 *frm++ = 0; /* Partial Virtual Bitmap (variable length) */ 2527 } 2528 frm = ieee80211_add_xrates(frm, rs); 2529 m->m_pkthdr.len = m->m_len = frm - mtod(m, u_int8_t *); 2530 m->m_pkthdr.rcvif = (void *)ni; 2531 KASSERT2(m->m_pkthdr.len <= pktlen, 2532 ("beacon bigger than expected, len %u calculated %u", 2533 m->m_pkthdr.len, pktlen)); 2534 2535 RTW_DPRINTF(RTW_DEBUG_BEACON, 2536 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2537 2538 return m; 2539 } 2540 2541 /* Must be called at splnet. */ 2542 static int 2543 rtw_init(struct ifnet *ifp) 2544 { 2545 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2546 struct ieee80211com *ic = &sc->sc_ic; 2547 struct rtw_regs *regs = &sc->sc_regs; 2548 int rc = 0; 2549 2550 if ((rc = rtw_enable(sc)) != 0) 2551 goto out; 2552 2553 /* Cancel pending I/O and reset. */ 2554 rtw_stop(ifp, 0); 2555 2556 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2557 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2558 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2559 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2560 2561 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2562 goto out; 2563 2564 if ((rc = rtw_swring_setup(sc)) != 0) 2565 goto out; 2566 2567 rtw_transmit_config(regs); 2568 2569 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2570 2571 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2572 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2573 2574 /* long PLCP header, 1Mb/2Mb basic rate */ 2575 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2576 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2577 2578 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2579 rtw_set_access(regs, RTW_ACCESS_NONE); 2580 2581 /* XXX from reference sources */ 2582 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2583 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2584 2585 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2586 2587 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2588 /* from Linux driver */ 2589 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2590 2591 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2592 2593 rtw_enable_interrupts(sc); 2594 2595 rtw_pktfilt_load(sc); 2596 2597 rtw_hwring_setup(sc); 2598 2599 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_wep_txkey); 2600 2601 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2602 2603 ifp->if_flags |= IFF_RUNNING; 2604 ic->ic_state = IEEE80211_S_INIT; 2605 2606 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2607 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2608 2609 rtw_resume_ticks(sc); 2610 2611 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2612 2613 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2614 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2615 else 2616 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2617 2618 out: 2619 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2620 return rc; 2621 } 2622 2623 static __inline void 2624 rtw_led_init(struct rtw_regs *regs) 2625 { 2626 uint8_t cfg0, cfg1; 2627 2628 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2629 2630 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2631 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2632 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2633 2634 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2635 RTW_DPRINTF(RTW_DEBUG_LED, 2636 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2637 2638 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2639 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2640 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2641 2642 rtw_set_access(regs, RTW_ACCESS_NONE); 2643 } 2644 2645 /* 2646 * IEEE80211_S_INIT: LED1 off 2647 * 2648 * IEEE80211_S_AUTH, 2649 * IEEE80211_S_ASSOC, 2650 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2651 * 2652 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2653 */ 2654 static void 2655 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2656 { 2657 struct rtw_led_state *ls; 2658 2659 ls = &sc->sc_led_state; 2660 2661 switch (nstate) { 2662 case IEEE80211_S_INIT: 2663 rtw_led_init(&sc->sc_regs); 2664 callout_stop(&ls->ls_slow_ch); 2665 callout_stop(&ls->ls_fast_ch); 2666 ls->ls_slowblink = 0; 2667 ls->ls_actblink = 0; 2668 ls->ls_default = 0; 2669 break; 2670 case IEEE80211_S_SCAN: 2671 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2672 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2673 /*FALLTHROUGH*/ 2674 case IEEE80211_S_AUTH: 2675 case IEEE80211_S_ASSOC: 2676 ls->ls_default = RTW_LED1; 2677 ls->ls_actblink = RTW_LED1; 2678 ls->ls_slowblink = RTW_LED1; 2679 break; 2680 case IEEE80211_S_RUN: 2681 ls->ls_slowblink = 0; 2682 break; 2683 } 2684 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2685 } 2686 2687 static void 2688 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2689 { 2690 uint8_t led_condition; 2691 bus_size_t ofs; 2692 uint8_t mask, newval, val; 2693 2694 led_condition = ls->ls_default; 2695 2696 if (ls->ls_state & RTW_LED_S_SLOW) 2697 led_condition ^= ls->ls_slowblink; 2698 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2699 led_condition ^= ls->ls_actblink; 2700 2701 RTW_DPRINTF(RTW_DEBUG_LED, 2702 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2703 2704 switch (hwverid) { 2705 default: 2706 case 'F': 2707 ofs = RTW_PSR; 2708 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2709 if (led_condition & RTW_LED0) 2710 newval &= ~RTW_PSR_LEDGPO0; 2711 if (led_condition & RTW_LED1) 2712 newval &= ~RTW_PSR_LEDGPO1; 2713 break; 2714 case 'D': 2715 ofs = RTW_9346CR; 2716 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2717 newval = RTW_9346CR_EEM_PROGRAM; 2718 if (led_condition & RTW_LED0) 2719 newval |= RTW_9346CR_EEDI; 2720 if (led_condition & RTW_LED1) 2721 newval |= RTW_9346CR_EECS; 2722 break; 2723 } 2724 val = RTW_READ8(regs, ofs); 2725 RTW_DPRINTF(RTW_DEBUG_LED, 2726 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2727 (uintptr_t)ofs)); 2728 val &= ~mask; 2729 val |= newval; 2730 RTW_WRITE8(regs, ofs, val); 2731 RTW_DPRINTF(RTW_DEBUG_LED, 2732 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2733 (uintptr_t)ofs)); 2734 RTW_SYNC(regs, ofs, ofs); 2735 } 2736 2737 static void 2738 rtw_led_fastblink(void *arg) 2739 { 2740 int ostate, s; 2741 struct rtw_softc *sc = (struct rtw_softc *)arg; 2742 struct rtw_led_state *ls = &sc->sc_led_state; 2743 2744 s = splnet(); 2745 ostate = ls->ls_state; 2746 ls->ls_state ^= ls->ls_event; 2747 2748 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2749 ls->ls_state &= ~RTW_LED_S_TX; 2750 2751 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2752 ls->ls_state &= ~RTW_LED_S_RX; 2753 2754 ls->ls_event = 0; 2755 2756 if (ostate != ls->ls_state) 2757 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2758 splx(s); 2759 2760 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2761 } 2762 2763 static void 2764 rtw_led_slowblink(void *arg) 2765 { 2766 int s; 2767 struct rtw_softc *sc = (struct rtw_softc *)arg; 2768 struct rtw_led_state *ls = &sc->sc_led_state; 2769 2770 s = splnet(); 2771 ls->ls_state ^= RTW_LED_S_SLOW; 2772 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2773 splx(s); 2774 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2775 } 2776 2777 static __inline void 2778 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2779 { 2780 callout_init(&ls->ls_fast_ch); 2781 callout_init(&ls->ls_slow_ch); 2782 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2783 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2784 } 2785 2786 static int 2787 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2788 { 2789 int rc = 0, s; 2790 struct rtw_softc *sc = ifp->if_softc; 2791 struct ifreq *ifr = (struct ifreq *)data; 2792 2793 s = splnet(); 2794 switch (cmd) { 2795 case SIOCSIFFLAGS: 2796 if ((ifp->if_flags & IFF_UP) != 0) { 2797 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2798 rtw_pktfilt_load(sc); 2799 } else 2800 rc = rtw_init(ifp); 2801 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2802 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2803 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2804 rtw_stop(ifp, 1); 2805 } 2806 break; 2807 case SIOCADDMULTI: 2808 case SIOCDELMULTI: 2809 if (cmd == SIOCADDMULTI) 2810 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2811 else 2812 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2813 if (rc != ENETRESET) 2814 break; 2815 if (ifp->if_flags & IFF_RUNNING) 2816 rtw_pktfilt_load(sc); 2817 rc = 0; 2818 break; 2819 case SIOCS80211NWKEY: 2820 if ((rc = ieee80211_ioctl(ifp, cmd, data)) != ENETRESET) 2821 break; 2822 rc = 0; 2823 if ((ifp->if_flags & IFF_RUNNING) == 0) 2824 break; 2825 rtw_wep_setkeys(sc, sc->sc_ic.ic_nw_keys, 2826 sc->sc_ic.ic_wep_txkey); 2827 break; 2828 default: 2829 if ((rc = ieee80211_ioctl(ifp, cmd, data)) != ENETRESET) 2830 break; 2831 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2832 rc = rtw_init(ifp); 2833 else 2834 rc = 0; 2835 break; 2836 } 2837 splx(s); 2838 return rc; 2839 } 2840 2841 /* Select a transmit ring with at least one h/w and s/w descriptor free. 2842 * Return 0 on success, -1 on failure. 2843 */ 2844 static __inline int 2845 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 2846 struct rtw_txdesc_blk **tdbp, int pri) 2847 { 2848 struct rtw_txsoft_blk *tsb; 2849 struct rtw_txdesc_blk *tdb; 2850 2851 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 2852 2853 tsb = &sc->sc_txsoft_blk[pri]; 2854 tdb = &sc->sc_txdesc_blk[pri]; 2855 2856 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 2857 *tsbp = NULL; 2858 *tdbp = NULL; 2859 return -1; 2860 } 2861 *tsbp = tsb; 2862 *tdbp = tdb; 2863 return 0; 2864 } 2865 2866 static __inline struct mbuf * 2867 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 2868 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 2869 struct ieee80211_node **nip, short *if_flagsp) 2870 { 2871 struct mbuf *m; 2872 2873 if (IF_IS_EMPTY(ifq)) 2874 return NULL; 2875 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 2876 *if_flagsp |= IFF_OACTIVE; 2877 return NULL; 2878 } 2879 IF_DEQUEUE(ifq, m); 2880 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2881 m->m_pkthdr.rcvif = NULL; 2882 return m; 2883 } 2884 2885 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 2886 * at the driver's selection of transmit control block for the packet. 2887 */ 2888 static __inline int 2889 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 2890 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 2891 struct ieee80211_node **nip) 2892 { 2893 struct mbuf *m0; 2894 struct rtw_softc *sc; 2895 short *if_flagsp; 2896 2897 sc = (struct rtw_softc *)ifp->if_softc; 2898 2899 DPRINTF(sc, RTW_DEBUG_XMIT, 2900 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2901 2902 if_flagsp = &ifp->if_flags; 2903 2904 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 2905 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 2906 tdbp, nip, if_flagsp)) != NULL) { 2907 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 2908 __func__)); 2909 return 0; 2910 } 2911 2912 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 2913 tdbp, nip, if_flagsp)) != NULL) { 2914 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 2915 __func__)); 2916 return 0; 2917 } 2918 2919 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 2920 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 2921 return 0; 2922 } 2923 2924 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_pwrsaveq, RTW_TXPRIHI, 2925 tsbp, tdbp, nip, if_flagsp)) != NULL) { 2926 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue pwrsave frame\n", 2927 __func__)); 2928 return 0; 2929 } 2930 2931 if (rtw_txring_choose(sc, tsbp, tdbp, RTW_TXPRIMD) == -1) { 2932 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no descriptor\n", __func__)); 2933 *if_flagsp |= IFF_OACTIVE; 2934 return 0; 2935 } 2936 2937 *mp = NULL; 2938 2939 IFQ_DEQUEUE(&ifp->if_snd, m0); 2940 if (m0 == NULL) { 2941 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame/ring ready\n", 2942 __func__)); 2943 return 0; 2944 } 2945 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 2946 ifp->if_opackets++; 2947 #if NBPFILTER > 0 2948 if (ifp->if_bpf) 2949 bpf_mtap(ifp->if_bpf, m0); 2950 #endif 2951 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2952 DPRINTF(sc, RTW_DEBUG_XMIT, 2953 ("%s: encap error\n", __func__)); 2954 ifp->if_oerrors++; 2955 return -1; 2956 } 2957 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 2958 *mp = m0; 2959 return 0; 2960 } 2961 2962 static int 2963 rtw_seg_too_short(bus_dmamap_t dmamap) 2964 { 2965 int i; 2966 for (i = 0; i < dmamap->dm_nsegs; i++) { 2967 if (dmamap->dm_segs[i].ds_len < 4) { 2968 printf("%s: segment too short\n", __func__); 2969 return 1; 2970 } 2971 } 2972 return 0; 2973 } 2974 2975 /* TBD factor with atw_start */ 2976 static struct mbuf * 2977 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2978 u_int ndescfree, short *ifflagsp, const char *dvname) 2979 { 2980 int first, rc; 2981 struct mbuf *m, *m0; 2982 2983 m0 = chain; 2984 2985 /* 2986 * Load the DMA map. Copy and try (once) again if the packet 2987 * didn't fit in the alloted number of segments. 2988 */ 2989 for (first = 1; 2990 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2991 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2992 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 2993 first = 0) { 2994 if (rc == 0) 2995 bus_dmamap_unload(dmat, dmam); 2996 MGETHDR(m, M_DONTWAIT, MT_DATA); 2997 if (m == NULL) { 2998 printf("%s: unable to allocate Tx mbuf\n", 2999 dvname); 3000 break; 3001 } 3002 if (m0->m_pkthdr.len > MHLEN) { 3003 MCLGET(m, M_DONTWAIT); 3004 if ((m->m_flags & M_EXT) == 0) { 3005 printf("%s: cannot allocate Tx cluster\n", 3006 dvname); 3007 m_freem(m); 3008 break; 3009 } 3010 } 3011 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3012 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3013 m_freem(m0); 3014 m0 = m; 3015 m = NULL; 3016 } 3017 if (rc != 0) { 3018 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 3019 m_freem(m0); 3020 return NULL; 3021 } else if (rtw_seg_too_short(dmam)) { 3022 printf("%s: cannot load Tx buffer, segment too short\n", 3023 dvname); 3024 bus_dmamap_unload(dmat, dmam); 3025 m_freem(m0); 3026 return NULL; 3027 } else if (dmam->dm_nsegs > ndescfree) { 3028 *ifflagsp |= IFF_OACTIVE; 3029 bus_dmamap_unload(dmat, dmam); 3030 m_freem(m0); 3031 return NULL; 3032 } 3033 return m0; 3034 } 3035 3036 #ifdef RTW_DEBUG 3037 static void 3038 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3039 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3040 { 3041 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3042 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] ctl0 %#08x " 3043 "ctl1 %#08x buf %#08x len %#08x\n", 3044 sc->sc_dev.dv_xname, ts, action, desc, 3045 le32toh(td->td_ctl0), 3046 le32toh(td->td_ctl1), le32toh(td->td_buf), 3047 le32toh(td->td_len))); 3048 } 3049 #endif /* RTW_DEBUG */ 3050 3051 static void 3052 rtw_start(struct ifnet *ifp) 3053 { 3054 uint8_t tppoll; 3055 int desc, i, lastdesc, npkt, rate; 3056 uint32_t proto_ctl0, ctl0, ctl1; 3057 bus_dmamap_t dmamap; 3058 struct ieee80211com *ic; 3059 struct ieee80211_duration *d0; 3060 struct ieee80211_frame *wh; 3061 struct ieee80211_node *ni; 3062 struct mbuf *m0; 3063 struct rtw_softc *sc; 3064 struct rtw_txsoft_blk *tsb; 3065 struct rtw_txdesc_blk *tdb; 3066 struct rtw_txsoft *ts; 3067 struct rtw_txdesc *td; 3068 3069 sc = (struct rtw_softc *)ifp->if_softc; 3070 ic = &sc->sc_ic; 3071 3072 DPRINTF(sc, RTW_DEBUG_XMIT, 3073 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3074 3075 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3076 goto out; 3077 3078 /* XXX do real rate control */ 3079 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3080 3081 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3082 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3083 3084 for (;;) { 3085 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3086 continue; 3087 if (m0 == NULL) 3088 break; 3089 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3090 3091 dmamap = ts->ts_dmamap; 3092 3093 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3094 tdb->tdb_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 3095 3096 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3097 DPRINTF(sc, RTW_DEBUG_XMIT, 3098 ("%s: fail dmamap load\n", __func__)); 3099 goto post_dequeue_err; 3100 } 3101 3102 wh = mtod(m0, struct ieee80211_frame *); 3103 3104 /* XXX do real rate control */ 3105 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3106 IEEE80211_FC0_TYPE_MGT) 3107 rate = 2; 3108 else 3109 rate = MAX(2, ieee80211_get_rate(ic)); 3110 3111 #ifdef RTW_DEBUG 3112 if ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 3113 (IFF_DEBUG|IFF_LINK2)) { 3114 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3115 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3116 : sizeof(wh), 3117 rate, 0); 3118 } 3119 #endif /* RTW_DEBUG */ 3120 ctl0 = proto_ctl0 | 3121 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3122 3123 switch (rate) { 3124 default: 3125 case 2: 3126 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3127 break; 3128 case 4: 3129 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3130 break; 3131 case 11: 3132 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3133 break; 3134 case 22: 3135 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3136 break; 3137 } 3138 3139 /* XXX >= ? Compare after fragmentation? */ 3140 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3141 ctl0 |= RTW_TXCTL0_RTSEN; 3142 3143 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) 3144 ctl0 |= LSHIFT(sc->sc_txkey, RTW_TXCTL0_KEYID_MASK); 3145 3146 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3147 IEEE80211_FC0_TYPE_MGT) { 3148 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3149 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3150 IEEE80211_FC0_SUBTYPE_BEACON) 3151 ctl0 |= RTW_TXCTL0_BEACON; 3152 } 3153 3154 if (ieee80211_compute_duration(wh, m0->m_pkthdr.len, 3155 ic->ic_flags, ic->ic_fragthreshold, 3156 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3157 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 3158 (IFF_DEBUG|IFF_LINK2)) == -1) { 3159 DPRINTF(sc, RTW_DEBUG_XMIT, 3160 ("%s: fail compute duration\n", __func__)); 3161 goto post_load_err; 3162 } 3163 3164 d0 = &ts->ts_d0; 3165 3166 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3167 3168 ctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3169 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3170 3171 if (d0->d_residue) 3172 ctl1 |= RTW_TXCTL1_LENGEXT; 3173 3174 /* TBD fragmentation */ 3175 3176 ts->ts_first = tdb->tdb_next; 3177 3178 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3179 BUS_DMASYNC_PREWRITE); 3180 3181 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3182 3183 #if NBPFILTER > 0 3184 if (ic->ic_rawbpf != NULL) 3185 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3186 3187 if (sc->sc_radiobpf != NULL) { 3188 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3189 3190 rt->rt_flags = 0; 3191 rt->rt_rate = rate; 3192 rt->rt_chan_freq = 3193 htole16(ic->ic_bss->ni_chan->ic_freq); 3194 rt->rt_chan_flags = 3195 htole16(ic->ic_bss->ni_chan->ic_flags); 3196 3197 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rt, 3198 sizeof(sc->sc_txtapu), m0); 3199 } 3200 #endif /* NPBFILTER > 0 */ 3201 3202 for (i = 0, lastdesc = desc = ts->ts_first; 3203 i < dmamap->dm_nsegs; 3204 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3205 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3206 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3207 ("%s: seg too long\n", __func__)); 3208 goto post_load_err; 3209 } 3210 td = &tdb->tdb_desc[desc]; 3211 td->td_ctl0 = htole32(ctl0); 3212 if (i != 0) 3213 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3214 td->td_ctl1 = htole32(ctl1); 3215 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3216 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3217 lastdesc = desc; 3218 #ifdef RTW_DEBUG 3219 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3220 #endif /* RTW_DEBUG */ 3221 } 3222 3223 KASSERT(desc < tdb->tdb_ndesc); 3224 3225 ts->ts_ni = ni; 3226 ts->ts_mbuf = m0; 3227 ts->ts_last = lastdesc; 3228 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3229 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3230 htole32(RTW_TXCTL0_FS); 3231 3232 #ifdef RTW_DEBUG 3233 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3234 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3235 #endif /* RTW_DEBUG */ 3236 3237 tdb->tdb_nfree -= dmamap->dm_nsegs; 3238 tdb->tdb_next = desc; 3239 3240 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3241 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3242 3243 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3244 htole32(RTW_TXCTL0_OWN); 3245 3246 #ifdef RTW_DEBUG 3247 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3248 #endif /* RTW_DEBUG */ 3249 3250 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3251 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3252 3253 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3254 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3255 3256 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) { 3257 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3258 tsb->tsb_tx_timer = 5; 3259 ifp->if_timer = 1; 3260 } 3261 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3262 tppoll &= ~RTW_TPPOLL_SALL; 3263 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL; 3264 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3265 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3266 } 3267 out: 3268 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3269 return; 3270 post_load_err: 3271 bus_dmamap_unload(sc->sc_dmat, dmamap); 3272 m_freem(m0); 3273 post_dequeue_err: 3274 ieee80211_release_node(&sc->sc_ic, ni); 3275 return; 3276 } 3277 3278 static void 3279 rtw_watchdog(struct ifnet *ifp) 3280 { 3281 int pri; 3282 struct rtw_softc *sc; 3283 struct rtw_txsoft_blk *tsb; 3284 3285 sc = ifp->if_softc; 3286 3287 ifp->if_timer = 0; 3288 3289 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 3290 return; 3291 3292 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3293 tsb = &sc->sc_txsoft_blk[pri]; 3294 3295 if (tsb->tsb_tx_timer == 0) 3296 continue; 3297 3298 if (--tsb->tsb_tx_timer == 0) { 3299 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3300 continue; 3301 printf("%s: transmit timeout, priority %d\n", 3302 ifp->if_xname, pri); 3303 ifp->if_oerrors++; 3304 /* Stop Tx DMA, disable transmitter, clear 3305 * Tx rings, and restart. 3306 * 3307 * TBD Stop/restart just the broken ring? 3308 */ 3309 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3310 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3311 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 0); 3312 rtw_txdescs_reset(sc); 3313 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 1); 3314 sc->sc_if.if_flags &= ~IFF_OACTIVE; 3315 rtw_start(ifp); 3316 } else 3317 ifp->if_timer = 1; 3318 } 3319 ieee80211_watchdog(ifp); 3320 return; 3321 } 3322 3323 static void 3324 rtw_next_scan(void *arg) 3325 { 3326 struct ieee80211com *ic = arg; 3327 int s; 3328 3329 /* don't call rtw_start w/o network interrupts blocked */ 3330 s = splnet(); 3331 if (ic->ic_state == IEEE80211_S_SCAN) 3332 ieee80211_next_scan(ic); 3333 splx(s); 3334 } 3335 3336 static void 3337 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3338 { 3339 uint16_t bcnitv, intval; 3340 int i; 3341 struct rtw_regs *regs = &sc->sc_regs; 3342 3343 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3344 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3345 3346 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3347 3348 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3349 3350 intval = MIN(intval0, PRESHIFT(RTW_BCNITV_BCNITV_MASK)); 3351 3352 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3353 bcnitv |= LSHIFT(intval, RTW_BCNITV_BCNITV_MASK); 3354 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3355 /* magic from Linux */ 3356 RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND)); 3357 RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV)); 3358 3359 rtw_set_access(regs, RTW_ACCESS_NONE); 3360 3361 /* TBD WEP */ 3362 RTW_WRITE8(regs, RTW_SCR, 0); 3363 3364 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 3365 } 3366 3367 /* Synchronize the hardware state with the software state. */ 3368 static int 3369 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3370 { 3371 struct ifnet *ifp = &ic->ic_if; 3372 struct rtw_softc *sc = ifp->if_softc; 3373 struct mbuf *m; 3374 enum ieee80211_state ostate; 3375 int error; 3376 3377 ostate = ic->ic_state; 3378 3379 rtw_led_newstate(sc, nstate); 3380 3381 if (nstate == IEEE80211_S_INIT) { 3382 callout_stop(&sc->sc_scan_ch); 3383 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3384 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3385 } 3386 3387 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3388 rtw_pwrstate(sc, RTW_ON); 3389 3390 if ((error = rtw_tune(sc)) != 0) 3391 return error; 3392 3393 switch (nstate) { 3394 case IEEE80211_S_INIT: 3395 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3396 break; 3397 case IEEE80211_S_SCAN: 3398 if (ostate != IEEE80211_S_SCAN) { 3399 (void)memset(ic->ic_bss->ni_bssid, 0, 3400 IEEE80211_ADDR_LEN); 3401 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3402 } 3403 3404 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3405 rtw_next_scan, ic); 3406 3407 break; 3408 case IEEE80211_S_RUN: 3409 switch (ic->ic_opmode) { 3410 case IEEE80211_M_HOSTAP: 3411 case IEEE80211_M_IBSS: 3412 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3413 m = rtw_beacon_alloc(sc, ic->ic_bss); 3414 if (m == NULL) { 3415 printf("%s: could not allocate beacon\n", 3416 sc->sc_dev.dv_xname); 3417 } else 3418 IF_ENQUEUE(&sc->sc_beaconq, m); 3419 /*FALLTHROUGH*/ 3420 case IEEE80211_M_AHDEMO: 3421 case IEEE80211_M_STA: 3422 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3423 ic->ic_bss->ni_intval); 3424 break; 3425 case IEEE80211_M_MONITOR: 3426 break; 3427 } 3428 rtw_set_nettype(sc, ic->ic_opmode); 3429 break; 3430 case IEEE80211_S_ASSOC: 3431 case IEEE80211_S_AUTH: 3432 break; 3433 } 3434 3435 if (nstate != IEEE80211_S_SCAN) 3436 callout_stop(&sc->sc_scan_ch); 3437 3438 /* Start beacon transmission. */ 3439 if (nstate == IEEE80211_S_RUN && 3440 (ic->ic_opmode == IEEE80211_M_HOSTAP || 3441 ic->ic_opmode == IEEE80211_M_IBSS)) 3442 rtw_start(&sc->sc_if); 3443 3444 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3445 } 3446 3447 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3448 static uint64_t 3449 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3450 { 3451 uint32_t tsftl, tsfth; 3452 3453 tsfth = RTW_READ(regs, RTW_TSFTRH); 3454 tsftl = RTW_READ(regs, RTW_TSFTRL); 3455 if (tsftl < rstamp) /* Compensate for rollover. */ 3456 tsfth--; 3457 return ((uint64_t)tsfth << 32) | rstamp; 3458 } 3459 3460 static void 3461 rtw_ibss_merge(struct rtw_softc *sc, struct ieee80211_node *ni, uint32_t rstamp) 3462 { 3463 uint8_t tppoll; 3464 struct ieee80211com *ic = &sc->sc_ic; 3465 3466 if (le64toh(ni->ni_tsf) >= rtw_tsf_extend(&sc->sc_regs, rstamp) && 3467 ieee80211_ibss_merge(ic, ni) == ENETRESET) { 3468 /* Stop beacon queue. Kick state machine to synchronize 3469 * with the new IBSS. 3470 */ 3471 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3472 tppoll |= RTW_TPPOLL_SBQ; 3473 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3474 (void)ieee80211_new_state(&sc->sc_ic, IEEE80211_S_RUN, -1); 3475 } 3476 return; 3477 } 3478 3479 static void 3480 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3481 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3482 { 3483 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 3484 3485 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3486 3487 switch (subtype) { 3488 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3489 case IEEE80211_FC0_SUBTYPE_BEACON: 3490 if (ic->ic_opmode != IEEE80211_M_IBSS || 3491 ic->ic_state != IEEE80211_S_RUN) 3492 return; 3493 rtw_ibss_merge(sc, ni, rstamp); 3494 break; 3495 default: 3496 break; 3497 } 3498 return; 3499 } 3500 3501 static struct ieee80211_node * 3502 rtw_node_alloc(struct ieee80211com *ic) 3503 { 3504 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 3505 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 3506 3507 DPRINTF(sc, RTW_DEBUG_NODE, 3508 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3509 return ni; 3510 } 3511 3512 static void 3513 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 3514 { 3515 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 3516 3517 DPRINTF(sc, RTW_DEBUG_NODE, 3518 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3519 ether_sprintf(ni->ni_bssid))); 3520 (*sc->sc_mtbl.mt_node_free)(ic, ni); 3521 } 3522 3523 static int 3524 rtw_media_change(struct ifnet *ifp) 3525 { 3526 int error; 3527 3528 error = ieee80211_media_change(ifp); 3529 if (error == ENETRESET) { 3530 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3531 (IFF_RUNNING|IFF_UP)) 3532 rtw_init(ifp); /* XXX lose error */ 3533 error = 0; 3534 } 3535 return error; 3536 } 3537 3538 static void 3539 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3540 { 3541 struct rtw_softc *sc = ifp->if_softc; 3542 3543 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3544 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3545 imr->ifm_status = 0; 3546 return; 3547 } 3548 ieee80211_media_status(ifp, imr); 3549 } 3550 3551 void 3552 rtw_power(int why, void *arg) 3553 { 3554 struct rtw_softc *sc = arg; 3555 struct ifnet *ifp = &sc->sc_ic.ic_if; 3556 int s; 3557 3558 DPRINTF(sc, RTW_DEBUG_PWR, 3559 ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3560 3561 s = splnet(); 3562 switch (why) { 3563 case PWR_STANDBY: 3564 /* XXX do nothing. */ 3565 break; 3566 case PWR_SUSPEND: 3567 rtw_stop(ifp, 0); 3568 if (sc->sc_power != NULL) 3569 (*sc->sc_power)(sc, why); 3570 break; 3571 case PWR_RESUME: 3572 if (ifp->if_flags & IFF_UP) { 3573 if (sc->sc_power != NULL) 3574 (*sc->sc_power)(sc, why); 3575 rtw_init(ifp); 3576 } 3577 break; 3578 case PWR_SOFTSUSPEND: 3579 case PWR_SOFTSTANDBY: 3580 case PWR_SOFTRESUME: 3581 break; 3582 } 3583 splx(s); 3584 } 3585 3586 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 3587 void 3588 rtw_shutdown(void *arg) 3589 { 3590 struct rtw_softc *sc = arg; 3591 3592 rtw_stop(&sc->sc_ic.ic_if, 1); 3593 } 3594 3595 static __inline void 3596 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3597 { 3598 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3599 ifp->if_softc = softc; 3600 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3601 IFF_NOTRAILERS; 3602 ifp->if_ioctl = rtw_ioctl; 3603 ifp->if_start = rtw_start; 3604 ifp->if_watchdog = rtw_watchdog; 3605 ifp->if_init = rtw_init; 3606 ifp->if_stop = rtw_stop; 3607 } 3608 3609 static __inline void 3610 rtw_set80211props(struct ieee80211com *ic) 3611 { 3612 int nrate; 3613 ic->ic_phytype = IEEE80211_T_DS; 3614 ic->ic_opmode = IEEE80211_M_STA; 3615 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3616 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 3617 3618 nrate = 0; 3619 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3620 IEEE80211_RATE_BASIC | 2; 3621 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3622 IEEE80211_RATE_BASIC | 4; 3623 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3624 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3625 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3626 } 3627 3628 static __inline void 3629 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3630 { 3631 mtbl->mt_newstate = ic->ic_newstate; 3632 ic->ic_newstate = rtw_newstate; 3633 3634 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3635 ic->ic_recv_mgmt = rtw_recv_mgmt; 3636 3637 mtbl->mt_node_free = ic->ic_node_free; 3638 ic->ic_node_free = rtw_node_free; 3639 3640 mtbl->mt_node_alloc = ic->ic_node_alloc; 3641 ic->ic_node_alloc = rtw_node_alloc; 3642 } 3643 3644 static __inline void 3645 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 3646 void *arg) 3647 { 3648 /* 3649 * Make sure the interface is shutdown during reboot. 3650 */ 3651 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 3652 if (hooks->rh_shutdown == NULL) 3653 printf("%s: WARNING: unable to establish shutdown hook\n", 3654 dvname); 3655 3656 /* 3657 * Add a suspend hook to make sure we come back up after a 3658 * resume. 3659 */ 3660 hooks->rh_power = powerhook_establish(rtw_power, arg); 3661 if (hooks->rh_power == NULL) 3662 printf("%s: WARNING: unable to establish power hook\n", 3663 dvname); 3664 } 3665 3666 static __inline void 3667 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 3668 void *arg) 3669 { 3670 if (hooks->rh_shutdown != NULL) 3671 shutdownhook_disestablish(hooks->rh_shutdown); 3672 3673 if (hooks->rh_power != NULL) 3674 powerhook_disestablish(hooks->rh_power); 3675 } 3676 3677 static __inline void 3678 rtw_init_radiotap(struct rtw_softc *sc) 3679 { 3680 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3681 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3682 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT); 3683 3684 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3685 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3686 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3687 } 3688 3689 static int 3690 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3691 { 3692 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3693 SIMPLEQ_INIT(&tsb->tsb_freeq); 3694 tsb->tsb_ndesc = qlen; 3695 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3696 M_NOWAIT); 3697 if (tsb->tsb_desc == NULL) 3698 return ENOMEM; 3699 return 0; 3700 } 3701 3702 static void 3703 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3704 { 3705 int pri; 3706 struct rtw_txsoft_blk *tsb; 3707 3708 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3709 tsb = &sc->sc_txsoft_blk[pri]; 3710 free(tsb->tsb_desc, M_DEVBUF); 3711 tsb->tsb_desc = NULL; 3712 } 3713 } 3714 3715 static int 3716 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3717 { 3718 int pri, rc = 0; 3719 int qlen[RTW_NTXPRI] = 3720 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3721 struct rtw_txsoft_blk *tsbs; 3722 3723 tsbs = sc->sc_txsoft_blk; 3724 3725 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3726 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3727 if (rc != 0) 3728 break; 3729 } 3730 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3731 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3732 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3733 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3734 return rc; 3735 } 3736 3737 static void 3738 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3739 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3740 { 3741 tdb->tdb_ndesc = ndesc; 3742 tdb->tdb_desc = desc; 3743 tdb->tdb_physbase = physbase; 3744 tdb->tdb_ofs = ofs; 3745 3746 (void)memset(tdb->tdb_desc, 0, 3747 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3748 3749 rtw_txdesc_blk_reset(tdb); 3750 } 3751 3752 static void 3753 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3754 { 3755 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3756 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3757 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3758 3759 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3760 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3761 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3762 3763 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3764 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3765 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3766 3767 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3768 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3769 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3770 } 3771 3772 static struct rtw_rf * 3773 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3774 { 3775 rtw_rf_write_t rf_write; 3776 struct rtw_rf *rf; 3777 3778 switch (rfchipid) { 3779 default: 3780 rf_write = rtw_rf_hostwrite; 3781 break; 3782 case RTW_RFCHIPID_INTERSIL: 3783 case RTW_RFCHIPID_PHILIPS: 3784 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3785 case RTW_RFCHIPID_RFMD: 3786 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3787 break; 3788 } 3789 3790 switch (rfchipid) { 3791 case RTW_RFCHIPID_MAXIM: 3792 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3793 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3794 break; 3795 case RTW_RFCHIPID_PHILIPS: 3796 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3797 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3798 break; 3799 case RTW_RFCHIPID_RFMD: 3800 /* XXX RFMD has no RF constructor */ 3801 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3802 /*FALLTHROUGH*/ 3803 default: 3804 return NULL; 3805 } 3806 rf->rf_continuous_tx_cb = 3807 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3808 rf->rf_continuous_tx_arg = (void *)sc; 3809 return rf; 3810 } 3811 3812 /* Revision C and later use a different PHY delay setting than 3813 * revisions A and B. 3814 */ 3815 static uint8_t 3816 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 3817 { 3818 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3819 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3820 3821 uint8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 3822 3823 RTW_WRITE(regs, RTW_RCR, REVAB); 3824 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3825 RTW_WRITE(regs, RTW_RCR, REVC); 3826 3827 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3828 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3829 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3830 3831 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 3832 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3833 3834 return phydelay; 3835 #undef REVC 3836 } 3837 3838 void 3839 rtw_attach(struct rtw_softc *sc) 3840 { 3841 struct rtw_txsoft_blk *tsb; 3842 int pri, rc; 3843 3844 NEXT_ATTACH_STATE(sc, DETACHED); 3845 3846 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3847 case RTW_TCR_HWVERID_F: 3848 sc->sc_hwverid = 'F'; 3849 break; 3850 case RTW_TCR_HWVERID_D: 3851 sc->sc_hwverid = 'D'; 3852 break; 3853 default: 3854 sc->sc_hwverid = '?'; 3855 break; 3856 } 3857 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, 3858 sc->sc_hwverid); 3859 3860 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3861 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3862 0); 3863 3864 if (rc != 0) { 3865 printf("%s: could not allocate hw descriptors, error %d\n", 3866 sc->sc_dev.dv_xname, rc); 3867 goto err; 3868 } 3869 3870 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3871 3872 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3873 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3874 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3875 3876 if (rc != 0) { 3877 printf("%s: could not map hw descriptors, error %d\n", 3878 sc->sc_dev.dv_xname, rc); 3879 goto err; 3880 } 3881 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3882 3883 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3884 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3885 3886 if (rc != 0) { 3887 printf("%s: could not create DMA map for hw descriptors, " 3888 "error %d\n", sc->sc_dev.dv_xname, rc); 3889 goto err; 3890 } 3891 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3892 3893 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 3894 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 3895 3896 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3897 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 3898 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 3899 } 3900 3901 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3902 sizeof(struct rtw_descs), NULL, 0); 3903 3904 if (rc != 0) { 3905 printf("%s: could not load DMA map for hw descriptors, " 3906 "error %d\n", sc->sc_dev.dv_xname, rc); 3907 goto err; 3908 } 3909 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3910 3911 if (rtw_txsoft_blk_setup_all(sc) != 0) 3912 goto err; 3913 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3914 3915 rtw_txdesc_blk_setup_all(sc); 3916 3917 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3918 3919 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 3920 3921 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3922 tsb = &sc->sc_txsoft_blk[pri]; 3923 3924 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3925 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 3926 printf("%s: could not load DMA map for " 3927 "hw tx descriptors, error %d\n", 3928 sc->sc_dev.dv_xname, rc); 3929 goto err; 3930 } 3931 } 3932 3933 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3934 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 3935 RTW_RXQLEN)) != 0) { 3936 printf("%s: could not load DMA map for hw rx descriptors, " 3937 "error %d\n", sc->sc_dev.dv_xname, rc); 3938 goto err; 3939 } 3940 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3941 3942 /* Reset the chip to a known state. */ 3943 if (rtw_reset(sc) != 0) 3944 goto err; 3945 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3946 3947 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3948 3949 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3950 sc->sc_flags |= RTW_F_9356SROM; 3951 3952 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3953 sc->sc_dev.dv_xname) != 0) 3954 goto err; 3955 3956 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3957 3958 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3959 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3960 sc->sc_dev.dv_xname) != 0) { 3961 printf("%s: attach failed, malformed serial ROM\n", 3962 sc->sc_dev.dv_xname); 3963 goto err; 3964 } 3965 3966 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 3967 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 3968 3969 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 3970 3971 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3972 3973 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 3974 sc->sc_flags & RTW_F_DIGPHY); 3975 3976 if (sc->sc_rf == NULL) { 3977 printf("%s: attach failed, could not attach RF\n", 3978 sc->sc_dev.dv_xname); 3979 goto err; 3980 } 3981 3982 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3983 3984 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 3985 3986 RTW_DPRINTF(RTW_DEBUG_ATTACH, 3987 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 3988 3989 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 3990 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 3991 sc->sc_dev.dv_xname); 3992 3993 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 3994 sc->sc_dev.dv_xname); 3995 3996 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 3997 sc->sc_dev.dv_xname) != 0) 3998 goto err; 3999 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4000 4001 rtw_setifprops(&sc->sc_if, sc->sc_dev.dv_xname, (void*)sc); 4002 4003 IFQ_SET_READY(&sc->sc_if.if_snd); 4004 4005 rtw_set80211props(&sc->sc_ic); 4006 4007 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4008 4009 /* 4010 * Call MI attach routines. 4011 */ 4012 if_attach(&sc->sc_if); 4013 ieee80211_ifattach(&sc->sc_if); 4014 4015 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4016 4017 /* possibly we should fill in our own sc_send_prresp, since 4018 * the RTL8180 is probably sending probe responses in ad hoc 4019 * mode. 4020 */ 4021 4022 /* complete initialization */ 4023 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 4024 callout_init(&sc->sc_scan_ch); 4025 4026 rtw_init_radiotap(sc); 4027 4028 #if NBPFILTER > 0 4029 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 4030 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4031 #endif 4032 4033 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 4034 4035 NEXT_ATTACH_STATE(sc, FINISHED); 4036 4037 return; 4038 err: 4039 rtw_detach(sc); 4040 return; 4041 } 4042 4043 int 4044 rtw_detach(struct rtw_softc *sc) 4045 { 4046 int pri; 4047 4048 sc->sc_flags |= RTW_F_INVALID; 4049 4050 switch (sc->sc_attach_state) { 4051 case FINISHED: 4052 rtw_stop(&sc->sc_if, 1); 4053 4054 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 4055 (void*)sc); 4056 callout_stop(&sc->sc_scan_ch); 4057 ieee80211_ifdetach(&sc->sc_if); 4058 if_detach(&sc->sc_if); 4059 break; 4060 case FINISH_ID_STA: 4061 case FINISH_RF_ATTACH: 4062 rtw_rf_destroy(sc->sc_rf); 4063 sc->sc_rf = NULL; 4064 /*FALLTHROUGH*/ 4065 case FINISH_PARSE_SROM: 4066 case FINISH_READ_SROM: 4067 rtw_srom_free(&sc->sc_srom); 4068 /*FALLTHROUGH*/ 4069 case FINISH_RESET: 4070 case FINISH_RXMAPS_CREATE: 4071 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4072 RTW_RXQLEN); 4073 /*FALLTHROUGH*/ 4074 case FINISH_TXMAPS_CREATE: 4075 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4076 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4077 sc->sc_txsoft_blk[pri].tsb_desc, 4078 sc->sc_txsoft_blk[pri].tsb_ndesc); 4079 } 4080 /*FALLTHROUGH*/ 4081 case FINISH_TXDESCBLK_SETUP: 4082 case FINISH_TXCTLBLK_SETUP: 4083 rtw_txsoft_blk_cleanup_all(sc); 4084 /*FALLTHROUGH*/ 4085 case FINISH_DESCMAP_LOAD: 4086 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4087 /*FALLTHROUGH*/ 4088 case FINISH_DESCMAP_CREATE: 4089 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4090 /*FALLTHROUGH*/ 4091 case FINISH_DESC_MAP: 4092 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 4093 sizeof(struct rtw_descs)); 4094 /*FALLTHROUGH*/ 4095 case FINISH_DESC_ALLOC: 4096 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4097 sc->sc_desc_nsegs); 4098 /*FALLTHROUGH*/ 4099 case DETACHED: 4100 NEXT_ATTACH_STATE(sc, DETACHED); 4101 break; 4102 } 4103 return 0; 4104 } 4105 4106 int 4107 rtw_activate(struct device *self, enum devact act) 4108 { 4109 struct rtw_softc *sc = (struct rtw_softc *)self; 4110 int rc = 0, s; 4111 4112 s = splnet(); 4113 switch (act) { 4114 case DVACT_ACTIVATE: 4115 rc = EOPNOTSUPP; 4116 break; 4117 4118 case DVACT_DEACTIVATE: 4119 if_deactivate(&sc->sc_ic.ic_if); 4120 break; 4121 } 4122 splx(s); 4123 return rc; 4124 } 4125
Indexes created Mon Sep 29 21:09:56 GMT 2025