rtw.c revision 1.5
1 /* $NetBSD: rtw.c,v 1.5 2004/12/19 08:19:25 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.5 2004/12/19 08:19:25 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #if 0 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #endif 54 #include <sys/time.h> 55 #include <sys/types.h> 56 57 #include <machine/endian.h> 58 #include <machine/bus.h> 59 #include <machine/intr.h> /* splnet */ 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_compat.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <dev/ic/rtwreg.h> 76 #include <dev/ic/rtwvar.h> 77 #include <dev/ic/rtwphyio.h> 78 #include <dev/ic/rtwphy.h> 79 80 #include <dev/ic/smc93cx6var.h> 81 82 #define KASSERT2(__cond, __msg) \ 83 do { \ 84 if (!(__cond)) \ 85 panic __msg ; \ 86 } while (0) 87 88 int rtw_rfprog_fallback = 0; 89 int rtw_host_rfio = 0; 90 int rtw_flush_rfio = 1; 91 int rtw_rfio_delay = 0; 92 93 #ifdef RTW_DEBUG 94 int rtw_debug = 2; 95 #endif /* RTW_DEBUG */ 96 97 #define NEXT_ATTACH_STATE(sc, state) do { \ 98 DPRINTF(sc, ("%s: attach state %s\n", __func__, #state)); \ 99 sc->sc_attach_state = state; \ 100 } while (0) 101 102 int rtw_dwelltime = 1000; /* milliseconds */ 103 104 static void rtw_start(struct ifnet *); 105 106 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 107 static int rtw_sysctl_verify_rfio_delay(SYSCTLFN_PROTO); 108 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 109 #ifdef RTW_DEBUG 110 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 111 #endif /* RTW_DEBUG */ 112 113 /* 114 * Setup sysctl(3) MIB, hw.rtw.* 115 * 116 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 117 */ 118 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 119 { 120 int rc; 121 struct sysctlnode *cnode, *rnode; 122 123 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 124 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 125 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 126 goto err; 127 128 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 129 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 130 "Realtek RTL818x 802.11 controls", 131 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 132 goto err; 133 134 #ifdef RTW_DEBUG 135 /* control debugging printfs */ 136 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 137 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 138 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 139 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 140 CTL_CREATE, CTL_EOL)) != 0) 141 goto err; 142 #endif /* RTW_DEBUG */ 143 /* set fallback RF programming method */ 144 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 145 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 146 "rfprog_fallback", 147 SYSCTL_DESCR("Set fallback RF programming method"), 148 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 149 CTL_CREATE, CTL_EOL)) != 0) 150 goto err; 151 152 /* force host to flush I/O by reading RTW_PHYADDR */ 153 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 154 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 155 "flush_rfio", SYSCTL_DESCR("Enable RF I/O flushing"), 156 rtw_sysctl_verify_rfio, 0, &rtw_flush_rfio, 0, 157 CTL_CREATE, CTL_EOL)) != 0) 158 goto err; 159 160 /* force host to control RF I/O bus */ 161 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 162 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 163 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 164 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 165 CTL_CREATE, CTL_EOL)) != 0) 166 goto err; 167 168 /* control RF I/O delay */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfio_delay", SYSCTL_DESCR("Set RF I/O delay"), 172 rtw_sysctl_verify_rfio_delay, 0, &rtw_rfio_delay, 0, 173 CTL_CREATE, CTL_EOL)) != 0) 174 goto err; 175 176 return; 177 err: 178 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 179 } 180 181 static int 182 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 183 { 184 int error, t; 185 struct sysctlnode node; 186 187 node = *rnode; 188 t = *(int*)rnode->sysctl_data; 189 node.sysctl_data = &t; 190 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 191 if (error || newp == NULL) 192 return (error); 193 194 if (t < lower || t > upper) 195 return (EINVAL); 196 197 *(int*)rnode->sysctl_data = t; 198 199 return (0); 200 } 201 202 static int 203 rtw_sysctl_verify_rfio_delay(SYSCTLFN_ARGS) 204 { 205 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1000000); 206 } 207 208 static int 209 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 210 { 211 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 212 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 213 } 214 215 static int 216 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 217 { 218 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1); 219 } 220 221 #ifdef RTW_DEBUG 222 static int 223 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 224 { 225 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 2); 226 } 227 228 static void 229 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 230 { 231 #define PRINTREG32(sc, reg) \ 232 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 233 dvname, reg, RTW_READ(regs, reg))) 234 235 #define PRINTREG16(sc, reg) \ 236 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %04x\n", \ 237 dvname, reg, RTW_READ16(regs, reg))) 238 239 #define PRINTREG8(sc, reg) \ 240 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %02x\n", \ 241 dvname, reg, RTW_READ8(regs, reg))) 242 243 RTW_DPRINTF2(("%s: %s\n", dvname, where)); 244 245 PRINTREG32(regs, RTW_IDR0); 246 PRINTREG32(regs, RTW_IDR1); 247 PRINTREG32(regs, RTW_MAR0); 248 PRINTREG32(regs, RTW_MAR1); 249 PRINTREG32(regs, RTW_TSFTRL); 250 PRINTREG32(regs, RTW_TSFTRH); 251 PRINTREG32(regs, RTW_TLPDA); 252 PRINTREG32(regs, RTW_TNPDA); 253 PRINTREG32(regs, RTW_THPDA); 254 PRINTREG32(regs, RTW_TCR); 255 PRINTREG32(regs, RTW_RCR); 256 PRINTREG32(regs, RTW_TINT); 257 PRINTREG32(regs, RTW_TBDA); 258 PRINTREG32(regs, RTW_ANAPARM); 259 PRINTREG32(regs, RTW_BB); 260 PRINTREG32(regs, RTW_PHYCFG); 261 PRINTREG32(regs, RTW_WAKEUP0L); 262 PRINTREG32(regs, RTW_WAKEUP0H); 263 PRINTREG32(regs, RTW_WAKEUP1L); 264 PRINTREG32(regs, RTW_WAKEUP1H); 265 PRINTREG32(regs, RTW_WAKEUP2LL); 266 PRINTREG32(regs, RTW_WAKEUP2LH); 267 PRINTREG32(regs, RTW_WAKEUP2HL); 268 PRINTREG32(regs, RTW_WAKEUP2HH); 269 PRINTREG32(regs, RTW_WAKEUP3LL); 270 PRINTREG32(regs, RTW_WAKEUP3LH); 271 PRINTREG32(regs, RTW_WAKEUP3HL); 272 PRINTREG32(regs, RTW_WAKEUP3HH); 273 PRINTREG32(regs, RTW_WAKEUP4LL); 274 PRINTREG32(regs, RTW_WAKEUP4LH); 275 PRINTREG32(regs, RTW_WAKEUP4HL); 276 PRINTREG32(regs, RTW_WAKEUP4HH); 277 PRINTREG32(regs, RTW_DK0); 278 PRINTREG32(regs, RTW_DK1); 279 PRINTREG32(regs, RTW_DK2); 280 PRINTREG32(regs, RTW_DK3); 281 PRINTREG32(regs, RTW_RETRYCTR); 282 PRINTREG32(regs, RTW_RDSAR); 283 PRINTREG32(regs, RTW_FER); 284 PRINTREG32(regs, RTW_FEMR); 285 PRINTREG32(regs, RTW_FPSR); 286 PRINTREG32(regs, RTW_FFER); 287 288 /* 16-bit registers */ 289 PRINTREG16(regs, RTW_BRSR); 290 PRINTREG16(regs, RTW_IMR); 291 PRINTREG16(regs, RTW_ISR); 292 PRINTREG16(regs, RTW_BCNITV); 293 PRINTREG16(regs, RTW_ATIMWND); 294 PRINTREG16(regs, RTW_BINTRITV); 295 PRINTREG16(regs, RTW_ATIMTRITV); 296 PRINTREG16(regs, RTW_CRC16ERR); 297 PRINTREG16(regs, RTW_CRC0); 298 PRINTREG16(regs, RTW_CRC1); 299 PRINTREG16(regs, RTW_CRC2); 300 PRINTREG16(regs, RTW_CRC3); 301 PRINTREG16(regs, RTW_CRC4); 302 PRINTREG16(regs, RTW_CWR); 303 304 /* 8-bit registers */ 305 PRINTREG8(regs, RTW_CR); 306 PRINTREG8(regs, RTW_9346CR); 307 PRINTREG8(regs, RTW_CONFIG0); 308 PRINTREG8(regs, RTW_CONFIG1); 309 PRINTREG8(regs, RTW_CONFIG2); 310 PRINTREG8(regs, RTW_MSR); 311 PRINTREG8(regs, RTW_CONFIG3); 312 PRINTREG8(regs, RTW_CONFIG4); 313 PRINTREG8(regs, RTW_TESTR); 314 PRINTREG8(regs, RTW_PSR); 315 PRINTREG8(regs, RTW_SCR); 316 PRINTREG8(regs, RTW_PHYDELAY); 317 PRINTREG8(regs, RTW_CRCOUNT); 318 PRINTREG8(regs, RTW_PHYADDR); 319 PRINTREG8(regs, RTW_PHYDATAW); 320 PRINTREG8(regs, RTW_PHYDATAR); 321 PRINTREG8(regs, RTW_CONFIG5); 322 PRINTREG8(regs, RTW_TPPOLL); 323 324 PRINTREG16(regs, RTW_BSSID16); 325 PRINTREG32(regs, RTW_BSSID32); 326 #undef PRINTREG32 327 #undef PRINTREG16 328 #undef PRINTREG8 329 } 330 #endif /* RTW_DEBUG */ 331 332 void 333 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 334 { 335 struct rtw_regs *regs = &sc->sc_regs; 336 337 u_int32_t tcr; 338 tcr = RTW_READ(regs, RTW_TCR); 339 tcr &= ~RTW_TCR_LBK_MASK; 340 if (enable) 341 tcr |= RTW_TCR_LBK_CONT; 342 else 343 tcr |= RTW_TCR_LBK_NORMAL; 344 RTW_WRITE(regs, RTW_TCR, tcr); 345 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 346 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 347 rtw_txdac_enable(sc, !enable); 348 rtw_set_access(sc, RTW_ACCESS_ANAPARM); /* XXX Voodoo from Linux. */ 349 rtw_set_access(sc, RTW_ACCESS_NONE); 350 } 351 352 static const char * 353 rtw_access_string(enum rtw_access access) 354 { 355 switch (access) { 356 case RTW_ACCESS_NONE: 357 return "none"; 358 case RTW_ACCESS_CONFIG: 359 return "config"; 360 case RTW_ACCESS_ANAPARM: 361 return "anaparm"; 362 default: 363 return "unknown"; 364 } 365 } 366 367 static void 368 rtw_set_access1(struct rtw_regs *regs, 369 enum rtw_access oaccess, enum rtw_access naccess) 370 { 371 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 372 KASSERT(oaccess >= RTW_ACCESS_NONE && oaccess <= RTW_ACCESS_ANAPARM); 373 374 if (naccess == oaccess) 375 return; 376 377 switch (naccess) { 378 case RTW_ACCESS_NONE: 379 switch (oaccess) { 380 case RTW_ACCESS_ANAPARM: 381 rtw_anaparm_enable(regs, 0); 382 /*FALLTHROUGH*/ 383 case RTW_ACCESS_CONFIG: 384 rtw_config0123_enable(regs, 0); 385 /*FALLTHROUGH*/ 386 case RTW_ACCESS_NONE: 387 break; 388 } 389 break; 390 case RTW_ACCESS_CONFIG: 391 switch (oaccess) { 392 case RTW_ACCESS_NONE: 393 rtw_config0123_enable(regs, 1); 394 /*FALLTHROUGH*/ 395 case RTW_ACCESS_CONFIG: 396 break; 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 break; 400 } 401 break; 402 case RTW_ACCESS_ANAPARM: 403 switch (oaccess) { 404 case RTW_ACCESS_NONE: 405 rtw_config0123_enable(regs, 1); 406 /*FALLTHROUGH*/ 407 case RTW_ACCESS_CONFIG: 408 rtw_anaparm_enable(regs, 1); 409 /*FALLTHROUGH*/ 410 case RTW_ACCESS_ANAPARM: 411 break; 412 } 413 break; 414 } 415 } 416 417 void 418 rtw_set_access(struct rtw_softc *sc, enum rtw_access access) 419 { 420 rtw_set_access1(&sc->sc_regs, sc->sc_access, access); 421 RTW_DPRINTF(("%s: access %s -> %s\n", sc->sc_dev.dv_xname, 422 rtw_access_string(sc->sc_access), 423 rtw_access_string(access))); 424 sc->sc_access = access; 425 } 426 427 /* 428 * Enable registers, switch register banks. 429 */ 430 void 431 rtw_config0123_enable(struct rtw_regs *regs, int enable) 432 { 433 u_int8_t ecr; 434 ecr = RTW_READ8(regs, RTW_9346CR); 435 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 436 if (enable) 437 ecr |= RTW_9346CR_EEM_CONFIG; 438 else 439 ecr |= RTW_9346CR_EEM_NORMAL; 440 RTW_WRITE8(regs, RTW_9346CR, ecr); 441 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 442 } 443 444 /* requires rtw_config0123_enable(, 1) */ 445 void 446 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 447 { 448 u_int8_t cfg3; 449 450 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 451 cfg3 |= RTW_CONFIG3_CLKRUNEN; 452 if (enable) 453 cfg3 |= RTW_CONFIG3_PARMEN; 454 else 455 cfg3 &= ~RTW_CONFIG3_PARMEN; 456 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 457 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 458 } 459 460 /* requires rtw_anaparm_enable(, 1) */ 461 void 462 rtw_txdac_enable(struct rtw_softc *sc, int enable) 463 { 464 u_int32_t anaparm; 465 struct rtw_regs *regs = &sc->sc_regs; 466 467 anaparm = RTW_READ(regs, RTW_ANAPARM); 468 if (enable) 469 anaparm &= ~RTW_ANAPARM_TXDACOFF; 470 else 471 anaparm |= RTW_ANAPARM_TXDACOFF; 472 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 473 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 474 } 475 476 static __inline int 477 rtw_chip_reset1(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 478 { 479 u_int8_t cr; 480 int i; 481 482 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 483 484 RTW_WBR(regs, RTW_CR, RTW_CR); 485 486 for (i = 0; i < 10000; i++) { 487 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 488 RTW_DPRINTF(("%s: reset in %dus\n", *dvname, i)); 489 return 0; 490 } 491 RTW_RBR(regs, RTW_CR, RTW_CR); 492 DELAY(1); /* 1us */ 493 } 494 495 printf("%s: reset failed\n", *dvname); 496 return ETIMEDOUT; 497 } 498 499 static __inline int 500 rtw_chip_reset(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 501 { 502 uint32_t tcr; 503 504 /* from Linux driver */ 505 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 506 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 507 508 RTW_WRITE(regs, RTW_TCR, tcr); 509 510 RTW_WBW(regs, RTW_CR, RTW_TCR); 511 512 return rtw_chip_reset1(regs, dvname); 513 } 514 515 static __inline int 516 rtw_recall_eeprom(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 517 { 518 int i; 519 u_int8_t ecr; 520 521 ecr = RTW_READ8(regs, RTW_9346CR); 522 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 523 RTW_WRITE8(regs, RTW_9346CR, ecr); 524 525 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 526 527 /* wait 2.5ms for completion */ 528 for (i = 0; i < 25; i++) { 529 ecr = RTW_READ8(regs, RTW_9346CR); 530 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 531 RTW_DPRINTF(("%s: recall EEPROM in %dus\n", *dvname, 532 i * 100)); 533 return 0; 534 } 535 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 536 DELAY(100); 537 } 538 printf("%s: recall EEPROM failed\n", *dvname); 539 return ETIMEDOUT; 540 } 541 542 static __inline int 543 rtw_reset(struct rtw_softc *sc) 544 { 545 int rc; 546 uint8_t config1; 547 548 if ((rc = rtw_chip_reset(&sc->sc_regs, &sc->sc_dev.dv_xname)) != 0) 549 return rc; 550 551 if ((rc = rtw_recall_eeprom(&sc->sc_regs, &sc->sc_dev.dv_xname)) != 0) 552 ; 553 554 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 555 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 556 /* TBD turn off maximum power saving? */ 557 558 return 0; 559 } 560 561 static __inline int 562 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txctl *descs, 563 u_int ndescs) 564 { 565 int i, rc = 0; 566 for (i = 0; i < ndescs; i++) { 567 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 568 0, 0, &descs[i].stx_dmamap); 569 if (rc != 0) 570 break; 571 } 572 return rc; 573 } 574 575 static __inline int 576 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 577 u_int ndescs) 578 { 579 int i, rc = 0; 580 for (i = 0; i < ndescs; i++) { 581 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 582 &descs[i].srx_dmamap); 583 if (rc != 0) 584 break; 585 } 586 return rc; 587 } 588 589 static __inline void 590 rtw_rxctls_setup(struct rtw_rxctl *descs) 591 { 592 int i; 593 for (i = 0; i < RTW_RXQLEN; i++) 594 descs[i].srx_mbuf = NULL; 595 } 596 597 static __inline void 598 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 599 u_int ndescs) 600 { 601 int i; 602 for (i = 0; i < ndescs; i++) { 603 if (descs[i].srx_dmamap != NULL) 604 bus_dmamap_destroy(dmat, descs[i].srx_dmamap); 605 } 606 } 607 608 static __inline void 609 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txctl *descs, 610 u_int ndescs) 611 { 612 int i; 613 for (i = 0; i < ndescs; i++) { 614 if (descs[i].stx_dmamap != NULL) 615 bus_dmamap_destroy(dmat, descs[i].stx_dmamap); 616 } 617 } 618 619 static __inline void 620 rtw_srom_free(struct rtw_srom *sr) 621 { 622 sr->sr_size = 0; 623 if (sr->sr_content == NULL) 624 return; 625 free(sr->sr_content, M_DEVBUF); 626 sr->sr_content = NULL; 627 } 628 629 static void 630 rtw_srom_defaults(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 631 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, char (*dvname)[IFNAMSIZ]) 632 { 633 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 634 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 635 *rcr |= RTW_RCR_ENCS1; 636 *rfchipid = RTW_RFCHIPID_PHILIPS; 637 } 638 639 static int 640 rtw_srom_parse(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 641 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, enum rtw_locale *locale, 642 char (*dvname)[IFNAMSIZ]) 643 { 644 int i; 645 const char *rfname, *paname; 646 char scratch[sizeof("unknown 0xXX")]; 647 u_int16_t version; 648 u_int8_t mac[IEEE80211_ADDR_LEN]; 649 650 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 651 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 652 653 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 654 printf("%s: SROM version %d.%d", *dvname, version >> 8, version & 0xff); 655 656 if (version <= 0x0101) { 657 printf(" is not understood, limping along with defaults\n"); 658 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr, 659 dvname); 660 return 0; 661 } 662 printf("\n"); 663 664 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 665 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 666 667 RTW_DPRINTF(("%s: EEPROM MAC %s\n", *dvname, ether_sprintf(mac))); 668 669 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 670 671 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 672 *flags |= RTW_F_ANTDIV; 673 674 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) != 0) 675 *flags |= RTW_F_DIGPHY; 676 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 677 *flags |= RTW_F_DFLANTB; 678 679 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 680 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 681 682 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 683 switch (*rfchipid) { 684 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 685 rfname = "GCT GRF5101"; 686 paname = "Winspring WS9901"; 687 break; 688 case RTW_RFCHIPID_MAXIM: 689 rfname = "Maxim MAX2820"; /* guess */ 690 paname = "Maxim MAX2422"; /* guess */ 691 break; 692 case RTW_RFCHIPID_INTERSIL: 693 rfname = "Intersil HFA3873"; /* guess */ 694 paname = "Intersil <unknown>"; 695 break; 696 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 697 rfname = "Philips SA2400A"; 698 paname = "Philips SA2411"; 699 break; 700 case RTW_RFCHIPID_RFMD: 701 /* this is the same front-end as an atw(4)! */ 702 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 703 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 704 "SYN: Silicon Labs Si4126"; /* inferred from 705 * reference driver 706 */ 707 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 708 break; 709 case RTW_RFCHIPID_RESERVED: 710 rfname = paname = "reserved"; 711 break; 712 default: 713 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 714 rfname = paname = scratch; 715 } 716 printf("%s: RF: %s, PA: %s\n", *dvname, rfname, paname); 717 718 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 719 case RTW_CONFIG0_GL_USA: 720 *locale = RTW_LOCALE_USA; 721 break; 722 case RTW_CONFIG0_GL_EUROPE: 723 *locale = RTW_LOCALE_EUROPE; 724 break; 725 case RTW_CONFIG0_GL_JAPAN: 726 *locale = RTW_LOCALE_JAPAN; 727 break; 728 default: 729 *locale = RTW_LOCALE_UNKNOWN; 730 break; 731 } 732 return 0; 733 } 734 735 /* Returns -1 on failure. */ 736 static int 737 rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr, 738 char (*dvname)[IFNAMSIZ]) 739 { 740 int rc; 741 struct seeprom_descriptor sd; 742 u_int8_t ecr; 743 744 (void)memset(&sd, 0, sizeof(sd)); 745 746 ecr = RTW_READ8(regs, RTW_9346CR); 747 748 if ((flags & RTW_F_9356SROM) != 0) { 749 RTW_DPRINTF(("%s: 93c56 SROM\n", *dvname)); 750 sr->sr_size = 256; 751 sd.sd_chip = C56_66; 752 } else { 753 RTW_DPRINTF(("%s: 93c46 SROM\n", *dvname)); 754 sr->sr_size = 128; 755 sd.sd_chip = C46; 756 } 757 758 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 759 RTW_9346CR_EEM_MASK); 760 ecr |= RTW_9346CR_EEM_PROGRAM; 761 762 RTW_WRITE8(regs, RTW_9346CR, ecr); 763 764 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 765 766 if (sr->sr_content == NULL) { 767 printf("%s: unable to allocate SROM buffer\n", *dvname); 768 return ENOMEM; 769 } 770 771 (void)memset(sr->sr_content, 0, sr->sr_size); 772 773 /* RTL8180 has a single 8-bit register for controlling the 774 * 93cx6 SROM. There is no "ready" bit. The RTL8180 775 * input/output sense is the reverse of read_seeprom's. 776 */ 777 sd.sd_tag = regs->r_bt; 778 sd.sd_bsh = regs->r_bh; 779 sd.sd_regsize = 1; 780 sd.sd_control_offset = RTW_9346CR; 781 sd.sd_status_offset = RTW_9346CR; 782 sd.sd_dataout_offset = RTW_9346CR; 783 sd.sd_CK = RTW_9346CR_EESK; 784 sd.sd_CS = RTW_9346CR_EECS; 785 sd.sd_DI = RTW_9346CR_EEDO; 786 sd.sd_DO = RTW_9346CR_EEDI; 787 /* make read_seeprom enter EEPROM read/write mode */ 788 sd.sd_MS = ecr; 789 sd.sd_RDY = 0; 790 #if 0 791 sd.sd_clkdelay = 50; 792 #endif 793 794 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 795 printf("%s: could not read SROM\n", *dvname); 796 free(sr->sr_content, M_DEVBUF); 797 sr->sr_content = NULL; 798 return -1; /* XXX */ 799 } 800 801 /* end EEPROM read/write mode */ 802 RTW_WRITE8(regs, RTW_9346CR, 803 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 804 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 805 806 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 807 return rc; 808 809 #ifdef RTW_DEBUG 810 { 811 int i; 812 RTW_DPRINTF(("\n%s: serial ROM:\n\t", *dvname)); 813 for (i = 0; i < sr->sr_size/2; i++) { 814 if (((i % 8) == 0) && (i != 0)) 815 RTW_DPRINTF(("\n\t")); 816 RTW_DPRINTF((" %04x", sr->sr_content[i])); 817 } 818 RTW_DPRINTF(("\n")); 819 } 820 #endif /* RTW_DEBUG */ 821 return 0; 822 } 823 824 static void 825 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 826 const char *dvname) 827 { 828 u_int8_t cfg4; 829 const char *method; 830 831 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 832 833 switch (rfchipid) { 834 default: 835 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 836 method = "fallback"; 837 break; 838 case RTW_RFCHIPID_INTERSIL: 839 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 840 method = "Intersil"; 841 break; 842 case RTW_RFCHIPID_PHILIPS: 843 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 844 method = "Philips"; 845 break; 846 case RTW_RFCHIPID_RFMD: 847 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 848 method = "RFMD"; 849 break; 850 } 851 852 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 853 854 printf("%s: %s RF programming method, %#02x\n", dvname, method, 855 RTW_READ8(regs, RTW_CONFIG4)); 856 } 857 858 #if 0 859 static __inline int 860 rtw_identify_rf(struct rtw_regs *regs, enum rtw_rftype *rftype, 861 char (*dvname)[IFNAMSIZ]) 862 { 863 u_int8_t cfg4; 864 const char *name; 865 866 cfg4 = RTW_READ8(regs, RTW_CONFIG4); 867 868 switch (cfg4 & RTW_CONFIG4_RFTYPE_MASK) { 869 case RTW_CONFIG4_RFTYPE_PHILIPS: 870 *rftype = RTW_RFTYPE_PHILIPS; 871 name = "Philips"; 872 break; 873 case RTW_CONFIG4_RFTYPE_INTERSIL: 874 *rftype = RTW_RFTYPE_INTERSIL; 875 name = "Intersil"; 876 break; 877 case RTW_CONFIG4_RFTYPE_RFMD: 878 *rftype = RTW_RFTYPE_RFMD; 879 name = "RFMD"; 880 break; 881 default: 882 name = "<unknown>"; 883 return ENXIO; 884 } 885 886 printf("%s: RF prog type %s\n", *dvname, name); 887 return 0; 888 } 889 #endif 890 891 static __inline void 892 rtw_init_channels(enum rtw_locale locale, 893 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 894 char (*dvname)[IFNAMSIZ]) 895 { 896 int i; 897 const char *name = NULL; 898 #define ADD_CHANNEL(_chans, _chan) do { \ 899 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 900 (*_chans)[_chan].ic_freq = \ 901 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 902 } while (0) 903 904 switch (locale) { 905 case RTW_LOCALE_USA: /* 1-11 */ 906 name = "USA"; 907 for (i = 1; i <= 11; i++) 908 ADD_CHANNEL(chans, i); 909 break; 910 case RTW_LOCALE_JAPAN: /* 1-14 */ 911 name = "Japan"; 912 ADD_CHANNEL(chans, 14); 913 for (i = 1; i <= 14; i++) 914 ADD_CHANNEL(chans, i); 915 break; 916 case RTW_LOCALE_EUROPE: /* 1-13 */ 917 name = "Europe"; 918 for (i = 1; i <= 13; i++) 919 ADD_CHANNEL(chans, i); 920 break; 921 default: /* 10-11 allowed by most countries */ 922 name = "<unknown>"; 923 for (i = 10; i <= 11; i++) 924 ADD_CHANNEL(chans, i); 925 break; 926 } 927 printf("%s: Geographic Location %s\n", *dvname, name); 928 #undef ADD_CHANNEL 929 } 930 931 static __inline void 932 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 933 char (*dvname)[IFNAMSIZ]) 934 { 935 u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 936 937 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 938 case RTW_CONFIG0_GL_USA: 939 *locale = RTW_LOCALE_USA; 940 break; 941 case RTW_CONFIG0_GL_JAPAN: 942 *locale = RTW_LOCALE_JAPAN; 943 break; 944 case RTW_CONFIG0_GL_EUROPE: 945 *locale = RTW_LOCALE_EUROPE; 946 break; 947 default: 948 *locale = RTW_LOCALE_UNKNOWN; 949 break; 950 } 951 } 952 953 static __inline int 954 rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN], 955 char (*dvname)[IFNAMSIZ]) 956 { 957 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 958 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 959 }; 960 u_int32_t idr0 = RTW_READ(regs, RTW_IDR0), 961 idr1 = RTW_READ(regs, RTW_IDR1); 962 963 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 964 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 965 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 966 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 967 968 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 969 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 970 971 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 972 printf("%s: could not get mac address, attach failed\n", 973 *dvname); 974 return ENXIO; 975 } 976 977 printf("%s: 802.11 address %s\n", *dvname, ether_sprintf(*addr)); 978 979 return 0; 980 } 981 982 static u_int8_t 983 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 984 struct ieee80211_channel *chan) 985 { 986 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 987 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 988 ("%s: channel %d out of range", __func__, 989 idx - RTW_SR_TXPOWER1 + 1)); 990 return RTW_SR_GET(sr, idx); 991 } 992 993 static void 994 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *htcs) 995 { 996 int pri; 997 u_int ndesc[RTW_NTXPRI] = 998 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 999 1000 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1001 htcs[pri].htc_nfree = ndesc[pri]; 1002 htcs[pri].htc_next = 0; 1003 } 1004 } 1005 1006 static int 1007 rtw_txctl_blk_init(struct rtw_txctl_blk *stc) 1008 { 1009 int i; 1010 struct rtw_txctl *stx; 1011 1012 SIMPLEQ_INIT(&stc->stc_dirtyq); 1013 SIMPLEQ_INIT(&stc->stc_freeq); 1014 for (i = 0; i < stc->stc_ndesc; i++) { 1015 stx = &stc->stc_desc[i]; 1016 stx->stx_mbuf = NULL; 1017 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1018 } 1019 return 0; 1020 } 1021 1022 static void 1023 rtw_txctl_blk_init_all(struct rtw_txctl_blk *stcs) 1024 { 1025 int pri; 1026 for (pri = 0; pri < RTW_NTXPRI; pri++) 1027 rtw_txctl_blk_init(&stcs[pri]); 1028 } 1029 1030 static __inline void 1031 rtw_rxdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, u_int desc0, u_int 1032 nsync, int ops) 1033 { 1034 /* sync to end of ring */ 1035 if (desc0 + nsync > RTW_NRXDESC) { 1036 bus_dmamap_sync(dmat, dmap, 1037 offsetof(struct rtw_descs, hd_rx[desc0]), 1038 sizeof(struct rtw_rxdesc) * (RTW_NRXDESC - desc0), ops); 1039 nsync -= (RTW_NRXDESC - desc0); 1040 desc0 = 0; 1041 } 1042 1043 /* sync what remains */ 1044 bus_dmamap_sync(dmat, dmap, 1045 offsetof(struct rtw_descs, hd_rx[desc0]), 1046 sizeof(struct rtw_rxdesc) * nsync, ops); 1047 } 1048 1049 static void 1050 rtw_txdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1051 struct rtw_txdesc_blk *htc, u_int desc0, u_int nsync, int ops) 1052 { 1053 /* sync to end of ring */ 1054 if (desc0 + nsync > htc->htc_ndesc) { 1055 bus_dmamap_sync(dmat, dmap, 1056 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1057 sizeof(struct rtw_txdesc) * (htc->htc_ndesc - desc0), 1058 ops); 1059 nsync -= (htc->htc_ndesc - desc0); 1060 desc0 = 0; 1061 } 1062 1063 /* sync what remains */ 1064 bus_dmamap_sync(dmat, dmap, 1065 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1066 sizeof(struct rtw_txdesc) * nsync, ops); 1067 } 1068 1069 static void 1070 rtw_txdescs_sync_all(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1071 struct rtw_txdesc_blk *htcs) 1072 { 1073 int pri; 1074 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1075 rtw_txdescs_sync(dmat, dmap, 1076 &htcs[pri], 0, htcs[pri].htc_ndesc, 1077 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1078 } 1079 } 1080 1081 static void 1082 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxctl *desc) 1083 { 1084 int i; 1085 struct rtw_rxctl *srx; 1086 1087 for (i = 0; i < RTW_NRXDESC; i++) { 1088 srx = &desc[i]; 1089 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, 1090 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1091 bus_dmamap_unload(dmat, srx->srx_dmamap); 1092 m_freem(srx->srx_mbuf); 1093 srx->srx_mbuf = NULL; 1094 } 1095 } 1096 1097 static __inline int 1098 rtw_rxbuf_alloc(bus_dma_tag_t dmat, struct rtw_rxctl *srx) 1099 { 1100 int rc; 1101 struct mbuf *m; 1102 1103 MGETHDR(m, M_DONTWAIT, MT_DATA); 1104 if (m == NULL) 1105 return ENOMEM; 1106 1107 MCLGET(m, M_DONTWAIT); 1108 if (m == NULL) 1109 return ENOMEM; 1110 1111 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1112 1113 rc = bus_dmamap_load_mbuf(dmat, srx->srx_dmamap, m, BUS_DMA_NOWAIT); 1114 if (rc != 0) 1115 return rc; 1116 1117 srx->srx_mbuf = m; 1118 1119 return 0; 1120 } 1121 1122 static int 1123 rtw_rxctl_init_all(bus_dma_tag_t dmat, struct rtw_rxctl *desc, 1124 u_int *next, char (*dvname)[IFNAMSIZ]) 1125 { 1126 int i, rc; 1127 struct rtw_rxctl *srx; 1128 1129 for (i = 0; i < RTW_NRXDESC; i++) { 1130 srx = &desc[i]; 1131 if ((rc = rtw_rxbuf_alloc(dmat, srx)) == 0) 1132 continue; 1133 printf("%s: failed rtw_rxbuf_alloc after %d buffers, rc = %d\n", 1134 *dvname, i, rc); 1135 if (i == 0) { 1136 rtw_rxbufs_release(dmat, desc); 1137 return rc; 1138 } 1139 } 1140 *next = 0; 1141 return 0; 1142 } 1143 1144 static __inline void 1145 rtw_rxdesc_init(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1146 struct rtw_rxdesc *hrx, struct rtw_rxctl *srx, int idx) 1147 { 1148 int is_last = (idx == RTW_NRXDESC - 1); 1149 uint32_t ctl; 1150 1151 hrx->hrx_buf = htole32(srx->srx_dmamap->dm_segs[0].ds_addr); 1152 1153 ctl = LSHIFT(srx->srx_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1154 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1155 1156 if (is_last) 1157 ctl |= RTW_RXCTL_EOR; 1158 1159 hrx->hrx_ctl = htole32(ctl); 1160 1161 /* sync the mbuf */ 1162 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, srx->srx_dmamap->dm_mapsize, 1163 BUS_DMASYNC_PREREAD); 1164 1165 /* sync the descriptor */ 1166 bus_dmamap_sync(dmat, dmam, RTW_DESC_OFFSET(hd_rx, idx), 1167 sizeof(struct rtw_rxdesc), 1168 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1169 } 1170 1171 static void 1172 rtw_rxdesc_init_all(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1173 struct rtw_rxdesc *desc, struct rtw_rxctl *ctl) 1174 { 1175 int i; 1176 struct rtw_rxdesc *hrx; 1177 struct rtw_rxctl *srx; 1178 1179 for (i = 0; i < RTW_NRXDESC; i++) { 1180 hrx = &desc[i]; 1181 srx = &ctl[i]; 1182 rtw_rxdesc_init(dmat, dmam, hrx, srx, i); 1183 } 1184 } 1185 1186 static void 1187 rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable) 1188 { 1189 u_int8_t cr; 1190 1191 RTW_DPRINTF(("%s: %s 0x%02x\n", __func__, 1192 enable ? "enable" : "disable", flags)); 1193 1194 cr = RTW_READ8(regs, RTW_CR); 1195 1196 /* XXX reference source does not enable MULRW */ 1197 #if 0 1198 /* enable PCI Read/Write Multiple */ 1199 cr |= RTW_CR_MULRW; 1200 #endif 1201 1202 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1203 if (enable) 1204 cr |= flags; 1205 else 1206 cr &= ~flags; 1207 RTW_WRITE8(regs, RTW_CR, cr); 1208 RTW_SYNC(regs, RTW_CR, RTW_CR); 1209 } 1210 1211 static void 1212 rtw_intr_rx(struct rtw_softc *sc, u_int16_t isr) 1213 { 1214 u_int next; 1215 int rate, rssi; 1216 u_int32_t hrssi, hstat, htsfth, htsftl; 1217 struct rtw_rxdesc *hrx; 1218 struct rtw_rxctl *srx; 1219 struct mbuf *m; 1220 1221 struct ieee80211_node *ni; 1222 struct ieee80211_frame *wh; 1223 1224 for (next = sc->sc_rxnext; ; next = (next + 1) % RTW_RXQLEN) { 1225 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1226 next, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1227 hrx = &sc->sc_rxdesc[next]; 1228 srx = &sc->sc_rxctl[next]; 1229 1230 hstat = le32toh(hrx->hrx_stat); 1231 hrssi = le32toh(hrx->hrx_rssi); 1232 htsfth = le32toh(hrx->hrx_tsfth); 1233 htsftl = le32toh(hrx->hrx_tsftl); 1234 1235 RTW_DPRINTF2(("%s: rxdesc[%d] hstat %#08x hrssi %#08x " 1236 "htsft %#08x%08x\n", __func__, next, 1237 hstat, hrssi, htsfth, htsftl)); 1238 1239 if ((hstat & RTW_RXSTAT_OWN) != 0) /* belongs to NIC */ 1240 break; 1241 1242 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1243 printf("%s: DMA error/FIFO overflow %08x, " 1244 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1245 hstat & RTW_RXSTAT_IOERROR, next); 1246 goto next; 1247 } 1248 1249 switch (hstat & RTW_RXSTAT_RATE_MASK) { 1250 case RTW_RXSTAT_RATE_1MBPS: 1251 rate = 10; 1252 break; 1253 case RTW_RXSTAT_RATE_2MBPS: 1254 rate = 20; 1255 break; 1256 case RTW_RXSTAT_RATE_5MBPS: 1257 rate = 55; 1258 break; 1259 default: 1260 #ifdef RTW_DEBUG 1261 if (rtw_debug > 1) 1262 printf("%s: interpreting rate #%d as 11 MB/s\n", 1263 sc->sc_dev.dv_xname, 1264 MASK_AND_RSHIFT(hstat, 1265 RTW_RXSTAT_RATE_MASK)); 1266 #endif /* RTW_DEBUG */ 1267 /*FALLTHROUGH*/ 1268 case RTW_RXSTAT_RATE_11MBPS: 1269 rate = 110; 1270 break; 1271 } 1272 1273 RTW_DPRINTF2(("%s: rate %d\n", __func__, rate)); 1274 1275 #ifdef RTW_DEBUG 1276 #define PRINTSTAT(flag) do { \ 1277 if ((hstat & flag) != 0) { \ 1278 printf("%s" #flag, delim); \ 1279 delim = ","; \ 1280 } \ 1281 } while (0) 1282 if (rtw_debug > 1) { 1283 const char *delim = "<"; 1284 printf("%s: ", sc->sc_dev.dv_xname); 1285 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1286 printf("status %08x<", hstat); 1287 PRINTSTAT(RTW_RXSTAT_SPLCP); 1288 PRINTSTAT(RTW_RXSTAT_MAR); 1289 PRINTSTAT(RTW_RXSTAT_PAR); 1290 PRINTSTAT(RTW_RXSTAT_BAR); 1291 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1292 PRINTSTAT(RTW_RXSTAT_CRC32); 1293 PRINTSTAT(RTW_RXSTAT_ICV); 1294 printf(">, "); 1295 } 1296 printf("rate %d.%d Mb/s, time %08x%08x\n", 1297 rate / 10, rate % 10, htsfth, htsftl); 1298 } 1299 #endif /* RTW_DEBUG */ 1300 1301 if ((hstat & RTW_RXSTAT_RES) != 0 && 1302 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1303 goto next; 1304 1305 /* if bad flags, skip descriptor */ 1306 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1307 printf("%s: too many rx segments\n", 1308 sc->sc_dev.dv_xname); 1309 goto next; 1310 } 1311 1312 m = srx->srx_mbuf; 1313 1314 /* if temporarily out of memory, re-use mbuf */ 1315 if (rtw_rxbuf_alloc(sc->sc_dmat, srx) != 0) { 1316 printf("%s: rtw_rxbuf_alloc(, %d) failed, " 1317 "dropping this packet\n", sc->sc_dev.dv_xname, 1318 next); 1319 goto next; 1320 } 1321 1322 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1323 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1324 else { 1325 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1326 /* TBD find out each front-end's LNA gain in the 1327 * front-end's units 1328 */ 1329 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1330 rssi |= 0x80; 1331 } 1332 1333 m->m_pkthdr.len = m->m_len = 1334 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1335 m->m_flags |= M_HASFCS; 1336 1337 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 1338 sc->sc_ic.ic_stats.is_rx_tooshort++; 1339 goto next; 1340 } 1341 wh = mtod(m, struct ieee80211_frame *); 1342 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1343 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1344 1345 sc->sc_tsfth = htsfth; 1346 1347 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1348 ieee80211_release_node(&sc->sc_ic, ni); 1349 next: 1350 rtw_rxdesc_init(sc->sc_dmat, sc->sc_desc_dmamap, 1351 hrx, srx, next); 1352 } 1353 sc->sc_rxnext = next; 1354 1355 return; 1356 } 1357 1358 static void 1359 rtw_txbuf_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1360 struct rtw_txctl *stx) 1361 { 1362 struct mbuf *m; 1363 struct ieee80211_node *ni; 1364 bus_dmamap_t dmamap; 1365 1366 dmamap = stx->stx_dmamap; 1367 m = stx->stx_mbuf; 1368 ni = stx->stx_ni; 1369 stx->stx_dmamap = NULL; 1370 stx->stx_mbuf = NULL; 1371 stx->stx_ni = NULL; 1372 1373 bus_dmamap_sync(dmat, dmamap, 0, dmamap->dm_mapsize, 1374 BUS_DMASYNC_POSTWRITE); 1375 bus_dmamap_unload(dmat, dmamap); 1376 m_freem(m); 1377 ieee80211_release_node(ic, ni); 1378 } 1379 1380 static void 1381 rtw_txbufs_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1382 struct rtw_txctl_blk *stc) 1383 { 1384 struct rtw_txctl *stx; 1385 1386 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1387 rtw_txbuf_release(dmat, ic, stx); 1388 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1389 SIMPLEQ_INSERT_HEAD(&stc->stc_dirtyq, stx, stx_q); 1390 } 1391 } 1392 1393 static __inline void 1394 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *htc, 1395 struct rtw_txctl *stx, int ndesc) 1396 { 1397 int data_retry, rts_retry; 1398 struct rtw_txdesc *htx0, *htxn; 1399 const char *condstring; 1400 1401 rtw_txbuf_release(sc->sc_dmat, &sc->sc_ic, stx); 1402 1403 htc->htc_nfree += ndesc; 1404 1405 htx0 = &htc->htc_desc[stx->stx_first]; 1406 htxn = &htc->htc_desc[stx->stx_last]; 1407 1408 rts_retry = MASK_AND_RSHIFT(le32toh(htx0->htx_stat), 1409 RTW_TXSTAT_RTSRETRY_MASK); 1410 data_retry = MASK_AND_RSHIFT(le32toh(htx0->htx_stat), 1411 RTW_TXSTAT_DRC_MASK); 1412 1413 sc->sc_if.if_collisions += rts_retry + data_retry; 1414 1415 if ((htx0->htx_stat & htole32(RTW_TXSTAT_TOK)) != 0) 1416 condstring = "ok"; 1417 else { 1418 sc->sc_if.if_oerrors++; 1419 condstring = "error"; 1420 } 1421 1422 DPRINTF2(sc, ("%s: stx %p txdesc[%d, %d] %s tries rts %u data %u\n", 1423 sc->sc_dev.dv_xname, stx, stx->stx_first, stx->stx_last, 1424 condstring, rts_retry, data_retry)); 1425 } 1426 1427 /* Collect transmitted packets. */ 1428 static __inline void 1429 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txctl_blk *stc, 1430 struct rtw_txdesc_blk *htc) 1431 { 1432 int ndesc; 1433 struct rtw_txctl *stx; 1434 1435 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1436 ndesc = 1 + stx->stx_last - stx->stx_first; 1437 if (stx->stx_last < stx->stx_first) 1438 ndesc += htc->htc_ndesc; 1439 1440 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, htc, 1441 stx->stx_first, ndesc, 1442 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1443 1444 if ((htc->htc_desc[stx->stx_first].htx_stat & 1445 htole32(RTW_TXSTAT_OWN)) != 0) 1446 break; 1447 1448 rtw_collect_txpkt(sc, htc, stx, ndesc); 1449 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1450 SIMPLEQ_INSERT_HEAD(&stc->stc_freeq, stx, stx_q); 1451 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1452 } 1453 if (stx == NULL) 1454 stc->stc_tx_timer = 0; 1455 } 1456 1457 static void 1458 rtw_intr_tx(struct rtw_softc *sc, u_int16_t isr) 1459 { 1460 int pri; 1461 struct rtw_txctl_blk *stc; 1462 struct rtw_txdesc_blk *htc; 1463 1464 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1465 stc = &sc->sc_txctl_blk[pri]; 1466 htc = &sc->sc_txdesc_blk[pri]; 1467 1468 rtw_collect_txring(sc, stc, htc); 1469 1470 rtw_start(&sc->sc_if); 1471 } 1472 1473 /* TBD */ 1474 return; 1475 } 1476 1477 static void 1478 rtw_intr_beacon(struct rtw_softc *sc, u_int16_t isr) 1479 { 1480 /* TBD */ 1481 return; 1482 } 1483 1484 static void 1485 rtw_intr_atim(struct rtw_softc *sc) 1486 { 1487 /* TBD */ 1488 return; 1489 } 1490 1491 static void 1492 rtw_hwring_setup(struct rtw_softc *sc) 1493 { 1494 struct rtw_regs *regs = &sc->sc_regs; 1495 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1496 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1497 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1498 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1499 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1500 } 1501 1502 static void 1503 rtw_swring_setup(struct rtw_softc *sc) 1504 { 1505 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1506 1507 rtw_txctl_blk_init_all(&sc->sc_txctl_blk[0]); 1508 1509 rtw_rxctl_init_all(sc->sc_dmat, sc->sc_rxctl, &sc->sc_rxnext, 1510 &sc->sc_dev.dv_xname); 1511 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, 1512 sc->sc_rxdesc, sc->sc_rxctl); 1513 1514 rtw_txdescs_sync_all(sc->sc_dmat, sc->sc_desc_dmamap, 1515 &sc->sc_txdesc_blk[0]); 1516 #if 0 /* redundant with rtw_rxdesc_init_all */ 1517 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1518 0, RTW_NRXDESC, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1519 #endif 1520 } 1521 1522 static void 1523 rtw_kick(struct rtw_softc *sc) 1524 { 1525 int pri; 1526 struct rtw_regs *regs = &sc->sc_regs; 1527 1528 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1529 RTW_WRITE16(regs, RTW_IMR, 0); 1530 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1531 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1532 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1533 &sc->sc_txctl_blk[pri]); 1534 } 1535 rtw_swring_setup(sc); 1536 rtw_hwring_setup(sc); 1537 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1538 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1539 } 1540 1541 static void 1542 rtw_intr_ioerror(struct rtw_softc *sc, u_int16_t isr) 1543 { 1544 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) { 1545 rtw_kick(sc); 1546 } 1547 if ((isr & RTW_INTR_TXFOVW) != 0) 1548 ; /* TBD restart transmit engine */ 1549 return; 1550 } 1551 1552 static __inline void 1553 rtw_suspend_ticks(struct rtw_softc *sc) 1554 { 1555 printf("%s: suspending ticks\n", sc->sc_dev.dv_xname); 1556 sc->sc_do_tick = 0; 1557 } 1558 1559 static __inline void 1560 rtw_resume_ticks(struct rtw_softc *sc) 1561 { 1562 u_int32_t tsftrl0, tsftrl1, next_tick; 1563 1564 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1565 1566 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1567 next_tick = tsftrl1 + 1000000; 1568 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1569 1570 sc->sc_do_tick = 1; 1571 1572 printf("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1573 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick); 1574 } 1575 1576 static void 1577 rtw_intr_timeout(struct rtw_softc *sc) 1578 { 1579 printf("%s: timeout\n", sc->sc_dev.dv_xname); 1580 if (sc->sc_do_tick) 1581 rtw_resume_ticks(sc); 1582 return; 1583 } 1584 1585 int 1586 rtw_intr(void *arg) 1587 { 1588 int i; 1589 struct rtw_softc *sc = arg; 1590 struct rtw_regs *regs = &sc->sc_regs; 1591 u_int16_t isr; 1592 1593 /* 1594 * If the interface isn't running, the interrupt couldn't 1595 * possibly have come from us. 1596 */ 1597 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1598 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1599 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1600 RTW_DPRINTF2(("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1601 return (0); 1602 } 1603 1604 for (i = 0; i < 10; i++) { 1605 isr = RTW_READ16(regs, RTW_ISR); 1606 1607 RTW_WRITE16(regs, RTW_ISR, isr); 1608 1609 if (sc->sc_intr_ack != NULL) 1610 (*sc->sc_intr_ack)(regs); 1611 1612 if (isr == 0) 1613 break; 1614 1615 #ifdef RTW_DEBUG 1616 #define PRINTINTR(flag) do { \ 1617 if ((isr & flag) != 0) { \ 1618 printf("%s" #flag, delim); \ 1619 delim = ","; \ 1620 } \ 1621 } while (0) 1622 1623 if (rtw_debug > 1 && isr != 0) { 1624 const char *delim = "<"; 1625 1626 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1627 1628 PRINTINTR(RTW_INTR_TXFOVW); 1629 PRINTINTR(RTW_INTR_TIMEOUT); 1630 PRINTINTR(RTW_INTR_BCNINT); 1631 PRINTINTR(RTW_INTR_ATIMINT); 1632 PRINTINTR(RTW_INTR_TBDER); 1633 PRINTINTR(RTW_INTR_TBDOK); 1634 PRINTINTR(RTW_INTR_THPDER); 1635 PRINTINTR(RTW_INTR_THPDOK); 1636 PRINTINTR(RTW_INTR_TNPDER); 1637 PRINTINTR(RTW_INTR_TNPDOK); 1638 PRINTINTR(RTW_INTR_RXFOVW); 1639 PRINTINTR(RTW_INTR_RDU); 1640 PRINTINTR(RTW_INTR_TLPDER); 1641 PRINTINTR(RTW_INTR_TLPDOK); 1642 PRINTINTR(RTW_INTR_RER); 1643 PRINTINTR(RTW_INTR_ROK); 1644 1645 printf(">\n"); 1646 } 1647 #undef PRINTINTR 1648 #endif /* RTW_DEBUG */ 1649 1650 if ((isr & RTW_INTR_RX) != 0) 1651 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1652 if ((isr & RTW_INTR_TX) != 0) 1653 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1654 if ((isr & RTW_INTR_BEACON) != 0) 1655 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1656 if ((isr & RTW_INTR_ATIMINT) != 0) 1657 rtw_intr_atim(sc); 1658 if ((isr & RTW_INTR_IOERROR) != 0) 1659 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1660 if ((isr & RTW_INTR_TIMEOUT) != 0) 1661 rtw_intr_timeout(sc); 1662 } 1663 1664 return 1; 1665 } 1666 1667 static void 1668 rtw_stop(struct ifnet *ifp, int disable) 1669 { 1670 int pri, s; 1671 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1672 struct ieee80211com *ic = &sc->sc_ic; 1673 struct rtw_regs *regs = &sc->sc_regs; 1674 1675 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1676 return; 1677 1678 rtw_suspend_ticks(sc); 1679 1680 s = splnet(); 1681 1682 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1683 1684 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1685 /* Disable interrupts. */ 1686 RTW_WRITE16(regs, RTW_IMR, 0); 1687 1688 /* Stop the transmit and receive processes. First stop DMA, 1689 * then disable receiver and transmitter. 1690 */ 1691 RTW_WRITE8(regs, RTW_TPPOLL, 1692 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ| 1693 RTW_TPPOLL_SLPQ); 1694 1695 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1696 } 1697 1698 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1699 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1700 &sc->sc_txctl_blk[pri]); 1701 } 1702 1703 if (disable) { 1704 rtw_disable(sc); 1705 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1706 } 1707 1708 /* Mark the interface as not running. Cancel the watchdog timer. */ 1709 ifp->if_flags &= ~IFF_RUNNING; 1710 ifp->if_timer = 0; 1711 1712 splx(s); 1713 1714 return; 1715 } 1716 1717 const char * 1718 rtw_pwrstate_string(enum rtw_pwrstate power) 1719 { 1720 switch (power) { 1721 case RTW_ON: 1722 return "on"; 1723 case RTW_SLEEP: 1724 return "sleep"; 1725 case RTW_OFF: 1726 return "off"; 1727 default: 1728 return "unknown"; 1729 } 1730 } 1731 1732 /* XXX I am using the RFMD settings gleaned from the reference 1733 * driver. 1734 */ 1735 static void 1736 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1737 int before_rf) 1738 { 1739 u_int32_t anaparm; 1740 1741 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1742 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1743 1744 anaparm = RTW_READ(regs, RTW_ANAPARM); 1745 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1746 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1747 1748 switch (power) { 1749 case RTW_OFF: 1750 if (before_rf) 1751 return; 1752 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_OFF; 1753 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_OFF; 1754 anaparm |= RTW_ANAPARM_TXDACOFF; 1755 break; 1756 case RTW_SLEEP: 1757 if (!before_rf) 1758 return; 1759 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_SLEEP; 1760 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_SLEEP; 1761 anaparm |= RTW_ANAPARM_TXDACOFF; 1762 break; 1763 case RTW_ON: 1764 if (!before_rf) 1765 return; 1766 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_ON; 1767 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_ON; 1768 break; 1769 } 1770 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1771 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1772 } 1773 1774 static void 1775 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1776 int before_rf) 1777 { 1778 u_int32_t anaparm; 1779 1780 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1781 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1782 1783 anaparm = RTW_READ(regs, RTW_ANAPARM); 1784 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1785 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1786 1787 switch (power) { 1788 case RTW_OFF: 1789 if (before_rf) 1790 return; 1791 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_OFF; 1792 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_OFF; 1793 anaparm |= RTW_ANAPARM_TXDACOFF; 1794 break; 1795 case RTW_SLEEP: 1796 if (!before_rf) 1797 return; 1798 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_SLEEP; 1799 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_SLEEP; 1800 anaparm |= RTW_ANAPARM_TXDACOFF; 1801 break; 1802 case RTW_ON: 1803 if (!before_rf) 1804 return; 1805 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_ON; 1806 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_ON; 1807 break; 1808 } 1809 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1810 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1811 } 1812 1813 static void 1814 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf) 1815 { 1816 struct rtw_regs *regs = &sc->sc_regs; 1817 1818 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 1819 1820 (*sc->sc_pwrstate_cb)(regs, power, before_rf); 1821 1822 rtw_set_access(sc, RTW_ACCESS_NONE); 1823 1824 return; 1825 } 1826 1827 static int 1828 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 1829 { 1830 int rc; 1831 1832 RTW_DPRINTF2(("%s: %s->%s\n", __func__, 1833 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 1834 1835 if (sc->sc_pwrstate == power) 1836 return 0; 1837 1838 rtw_pwrstate0(sc, power, 1); 1839 rc = rtw_rf_pwrstate(sc->sc_rf, power); 1840 rtw_pwrstate0(sc, power, 0); 1841 1842 switch (power) { 1843 case RTW_ON: 1844 /* TBD set LEDs */ 1845 break; 1846 case RTW_SLEEP: 1847 /* TBD */ 1848 break; 1849 case RTW_OFF: 1850 /* TBD */ 1851 break; 1852 } 1853 if (rc == 0) 1854 sc->sc_pwrstate = power; 1855 else 1856 sc->sc_pwrstate = RTW_OFF; 1857 return rc; 1858 } 1859 1860 static int 1861 rtw_tune(struct rtw_softc *sc) 1862 { 1863 struct ieee80211com *ic = &sc->sc_ic; 1864 u_int chan; 1865 int rc; 1866 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 1867 dflantb = sc->sc_flags & RTW_F_DFLANTB; 1868 1869 KASSERT(ic->ic_bss->ni_chan != NULL); 1870 1871 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1872 if (chan == IEEE80211_CHAN_ANY) 1873 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1874 1875 if (chan == sc->sc_cur_chan) { 1876 RTW_DPRINTF(("%s: already tuned chan #%d\n", __func__, chan)); 1877 return 0; 1878 } 1879 1880 rtw_suspend_ticks(sc); 1881 1882 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 1883 1884 /* TBD wait for Tx to complete */ 1885 1886 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 1887 1888 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 1889 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 1890 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 1891 dflantb, RTW_ON)) != 0) { 1892 /* XXX condition on powersaving */ 1893 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 1894 } 1895 1896 sc->sc_cur_chan = chan; 1897 1898 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 1899 1900 rtw_resume_ticks(sc); 1901 1902 return rc; 1903 } 1904 1905 void 1906 rtw_disable(struct rtw_softc *sc) 1907 { 1908 int rc; 1909 1910 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1911 return; 1912 1913 /* turn off PHY */ 1914 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 1915 printf("%s: failed to turn off PHY (%d)\n", 1916 sc->sc_dev.dv_xname, rc); 1917 1918 if (sc->sc_disable != NULL) 1919 (*sc->sc_disable)(sc); 1920 1921 sc->sc_flags &= ~RTW_F_ENABLED; 1922 } 1923 1924 int 1925 rtw_enable(struct rtw_softc *sc) 1926 { 1927 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 1928 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 1929 printf("%s: device enable failed\n", 1930 sc->sc_dev.dv_xname); 1931 return (EIO); 1932 } 1933 sc->sc_flags |= RTW_F_ENABLED; 1934 } 1935 return (0); 1936 } 1937 1938 static void 1939 rtw_transmit_config(struct rtw_regs *regs) 1940 { 1941 u_int32_t tcr; 1942 1943 tcr = RTW_READ(regs, RTW_TCR); 1944 1945 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 1946 tcr &= ~RTW_TCR_LBK_MASK; 1947 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 1948 1949 /* set short/long retry limits */ 1950 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 1951 tcr |= LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 1952 1953 tcr |= RTW_TCR_CRC; /* NIC appends CRC32 */ 1954 1955 RTW_WRITE(regs, RTW_TCR, tcr); 1956 } 1957 1958 static __inline void 1959 rtw_enable_interrupts(struct rtw_softc *sc) 1960 { 1961 struct rtw_regs *regs = &sc->sc_regs; 1962 1963 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 1964 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 1965 1966 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1967 RTW_WRITE16(regs, RTW_ISR, 0xffff); 1968 1969 /* XXX necessary? */ 1970 if (sc->sc_intr_ack != NULL) 1971 (*sc->sc_intr_ack)(regs); 1972 } 1973 1974 /* XXX is the endianness correct? test. */ 1975 #define rtw_calchash(addr) \ 1976 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1977 1978 static void 1979 rtw_pktfilt_load(struct rtw_softc *sc) 1980 { 1981 struct rtw_regs *regs = &sc->sc_regs; 1982 struct ieee80211com *ic = &sc->sc_ic; 1983 struct ethercom *ec = &ic->ic_ec; 1984 struct ifnet *ifp = &sc->sc_ic.ic_if; 1985 int hash; 1986 u_int32_t hashes[2] = { 0, 0 }; 1987 struct ether_multi *enm; 1988 struct ether_multistep step; 1989 1990 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 1991 1992 #define RTW_RCR_MONITOR (RTW_RCR_ACRC32|RTW_RCR_APM|RTW_RCR_AAP|RTW_RCR_AB) 1993 1994 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1995 sc->sc_rcr |= RTW_RCR_MONITOR; 1996 else 1997 sc->sc_rcr &= ~RTW_RCR_MONITOR; 1998 1999 /* XXX reference sources BEGIN */ 2000 sc->sc_rcr |= RTW_RCR_ENMARP | RTW_RCR_AICV | RTW_RCR_ACRC32; 2001 sc->sc_rcr |= RTW_RCR_AB | RTW_RCR_AM | RTW_RCR_APM; 2002 #if 0 2003 /* receive broadcasts in our BSS */ 2004 sc->sc_rcr |= RTW_RCR_ADD3; 2005 #endif 2006 /* XXX reference sources END */ 2007 2008 /* receive pwrmgmt frames. */ 2009 sc->sc_rcr |= RTW_RCR_APWRMGT; 2010 /* receive mgmt/ctrl/data frames. */ 2011 sc->sc_rcr |= RTW_RCR_AMF | RTW_RCR_ACF | RTW_RCR_ADF; 2012 /* initialize Rx DMA threshold, Tx DMA burst size */ 2013 sc->sc_rcr |= RTW_RCR_RXFTH_WHOLE | RTW_RCR_MXDMA_1024; 2014 2015 ifp->if_flags &= ~IFF_ALLMULTI; 2016 2017 if (ifp->if_flags & IFF_PROMISC) { 2018 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2019 allmulti: 2020 ifp->if_flags |= IFF_ALLMULTI; 2021 goto setit; 2022 } 2023 2024 /* 2025 * Program the 64-bit multicast hash filter. 2026 */ 2027 ETHER_FIRST_MULTI(step, ec, enm); 2028 while (enm != NULL) { 2029 /* XXX */ 2030 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2031 ETHER_ADDR_LEN) != 0) 2032 goto allmulti; 2033 2034 hash = rtw_calchash(enm->enm_addrlo); 2035 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2036 ETHER_NEXT_MULTI(step, enm); 2037 } 2038 2039 if (ifp->if_flags & IFF_BROADCAST) { 2040 hash = rtw_calchash(etherbroadcastaddr); 2041 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2042 } 2043 2044 /* all bits set => hash is useless */ 2045 if (~(hashes[0] & hashes[1]) == 0) 2046 goto allmulti; 2047 2048 setit: 2049 if (ifp->if_flags & IFF_ALLMULTI) 2050 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2051 2052 if (ic->ic_state == IEEE80211_S_SCAN) 2053 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2054 2055 hashes[0] = hashes[1] = 0xffffffff; 2056 2057 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2058 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2059 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2060 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2061 2062 DPRINTF(sc, ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2063 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2064 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2065 2066 return; 2067 } 2068 2069 static int 2070 rtw_init(struct ifnet *ifp) 2071 { 2072 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2073 struct ieee80211com *ic = &sc->sc_ic; 2074 struct rtw_regs *regs = &sc->sc_regs; 2075 int rc = 0; 2076 2077 if ((rc = rtw_enable(sc)) != 0) 2078 goto out; 2079 2080 /* Cancel pending I/O and reset. */ 2081 rtw_stop(ifp, 0); 2082 2083 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2084 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 2085 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2086 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2087 2088 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2089 goto out; 2090 2091 rtw_swring_setup(sc); 2092 2093 rtw_transmit_config(regs); 2094 2095 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2096 2097 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2098 2099 /* long PLCP header, 1Mbps basic rate */ 2100 RTW_WRITE16(regs, RTW_BRSR, 0x0); 2101 2102 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 2103 rtw_set_access(sc, RTW_ACCESS_NONE); 2104 2105 #if 0 2106 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_GWAKE|RTW_FEMR_WKUP|RTW_FEMR_INTR); 2107 #endif 2108 /* XXX from reference sources */ 2109 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2110 2111 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2112 2113 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2114 /* from Linux driver */ 2115 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2116 2117 rtw_enable_interrupts(sc); 2118 2119 rtw_pktfilt_load(sc); 2120 2121 rtw_hwring_setup(sc); 2122 2123 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2124 2125 ifp->if_flags |= IFF_RUNNING; 2126 ic->ic_state = IEEE80211_S_INIT; 2127 2128 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2129 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2130 2131 rtw_resume_ticks(sc); 2132 2133 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2134 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2135 2136 switch (ic->ic_opmode) { 2137 case IEEE80211_M_AHDEMO: 2138 case IEEE80211_M_IBSS: 2139 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_ADHOC_OK); 2140 break; 2141 case IEEE80211_M_HOSTAP: 2142 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_AP_OK); 2143 break; 2144 case IEEE80211_M_MONITOR: 2145 /* XXX */ 2146 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_NOLINK); 2147 break; 2148 case IEEE80211_M_STA: 2149 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_INFRA_OK); 2150 break; 2151 } 2152 2153 rtw_set_access(sc, RTW_ACCESS_NONE); 2154 2155 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2156 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2157 else 2158 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2159 2160 out: 2161 return rc; 2162 } 2163 2164 static int 2165 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2166 { 2167 int rc = 0; 2168 struct rtw_softc *sc = ifp->if_softc; 2169 struct ifreq *ifr = (struct ifreq *)data; 2170 2171 switch (cmd) { 2172 case SIOCSIFFLAGS: 2173 if ((ifp->if_flags & IFF_UP) != 0) { 2174 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2175 rtw_pktfilt_load(sc); 2176 } else 2177 rc = rtw_init(ifp); 2178 #ifdef RTW_DEBUG 2179 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2180 #endif /* RTW_DEBUG */ 2181 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2182 #ifdef RTW_DEBUG 2183 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2184 #endif /* RTW_DEBUG */ 2185 rtw_stop(ifp, 1); 2186 } 2187 break; 2188 case SIOCADDMULTI: 2189 case SIOCDELMULTI: 2190 if (cmd == SIOCADDMULTI) 2191 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2192 else 2193 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2194 if (rc == ENETRESET) { 2195 if (ifp->if_flags & IFF_RUNNING) 2196 rtw_pktfilt_load(sc); 2197 rc = 0; 2198 } 2199 break; 2200 default: 2201 if ((rc = ieee80211_ioctl(ifp, cmd, data)) == ENETRESET) { 2202 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2203 rc = rtw_init(ifp); 2204 else 2205 rc = 0; 2206 } 2207 break; 2208 } 2209 return rc; 2210 } 2211 2212 /* Point *mp at the next 802.11 frame to transmit. Point *stcp 2213 * at the driver's selection of transmit control block for the packet. 2214 */ 2215 static __inline int 2216 rtw_dequeue(struct ifnet *ifp, struct rtw_txctl_blk **stcp, 2217 struct rtw_txdesc_blk **htcp, struct mbuf **mp, 2218 struct ieee80211_node **nip) 2219 { 2220 struct rtw_txctl_blk *stc; 2221 struct rtw_txdesc_blk *htc; 2222 struct mbuf *m0; 2223 struct rtw_softc *sc; 2224 struct ieee80211com *ic; 2225 2226 sc = (struct rtw_softc *)ifp->if_softc; 2227 2228 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2229 *mp = NULL; 2230 2231 stc = &sc->sc_txctl_blk[RTW_TXPRIMD]; 2232 htc = &sc->sc_txdesc_blk[RTW_TXPRIMD]; 2233 2234 if (SIMPLEQ_EMPTY(&stc->stc_freeq) || htc->htc_nfree == 0) { 2235 DPRINTF2(sc, ("%s: out of descriptors\n", __func__)); 2236 ifp->if_flags |= IFF_OACTIVE; 2237 return 0; 2238 } 2239 2240 ic = &sc->sc_ic; 2241 2242 if (!IF_IS_EMPTY(&ic->ic_mgtq)) { 2243 IF_DEQUEUE(&ic->ic_mgtq, m0); 2244 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2245 m0->m_pkthdr.rcvif = NULL; 2246 DPRINTF2(sc, ("%s: dequeue mgt frame\n", __func__)); 2247 } else if (ic->ic_state != IEEE80211_S_RUN) { 2248 DPRINTF2(sc, ("%s: not running\n", __func__)); 2249 return 0; 2250 } else if (!IF_IS_EMPTY(&ic->ic_pwrsaveq)) { 2251 IF_DEQUEUE(&ic->ic_pwrsaveq, m0); 2252 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2253 m0->m_pkthdr.rcvif = NULL; 2254 DPRINTF2(sc, ("%s: dequeue pwrsave frame\n", __func__)); 2255 } else { 2256 IFQ_POLL(&ifp->if_snd, m0); 2257 if (m0 == NULL) { 2258 DPRINTF2(sc, ("%s: no frame\n", __func__)); 2259 return 0; 2260 } 2261 DPRINTF2(sc, ("%s: dequeue data frame\n", __func__)); 2262 IFQ_DEQUEUE(&ifp->if_snd, m0); 2263 ifp->if_opackets++; 2264 #if NBPFILTER > 0 2265 if (ifp->if_bpf) 2266 bpf_mtap(ifp->if_bpf, m0); 2267 #endif 2268 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2269 DPRINTF2(sc, ("%s: encap error\n", __func__)); 2270 ifp->if_oerrors++; 2271 return -1; 2272 } 2273 } 2274 DPRINTF2(sc, ("%s: leave\n", __func__)); 2275 *stcp = stc; 2276 *htcp = htc; 2277 *mp = m0; 2278 return 0; 2279 } 2280 2281 /* TBD factor with atw_start */ 2282 static struct mbuf * 2283 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2284 u_int ndescfree, short *ifflagsp, const char *dvname) 2285 { 2286 int first, rc; 2287 struct mbuf *m, *m0; 2288 2289 m0 = chain; 2290 2291 /* 2292 * Load the DMA map. Copy and try (once) again if the packet 2293 * didn't fit in the alloted number of segments. 2294 */ 2295 for (first = 1; 2296 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2297 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2298 dmam->dm_nsegs > ndescfree) && first; 2299 first = 0) { 2300 if (rc == 0) 2301 bus_dmamap_unload(dmat, dmam); 2302 MGETHDR(m, M_DONTWAIT, MT_DATA); 2303 if (m == NULL) { 2304 printf("%s: unable to allocate Tx mbuf\n", 2305 dvname); 2306 break; 2307 } 2308 if (m0->m_pkthdr.len > MHLEN) { 2309 MCLGET(m, M_DONTWAIT); 2310 if ((m->m_flags & M_EXT) == 0) { 2311 printf("%s: cannot allocate Tx cluster\n", 2312 dvname); 2313 m_freem(m); 2314 break; 2315 } 2316 } 2317 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2318 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 2319 m_freem(m0); 2320 m0 = m; 2321 m = NULL; 2322 } 2323 if (rc != 0) { 2324 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 2325 m_freem(m0); 2326 return NULL; 2327 } else if (dmam->dm_nsegs > ndescfree) { 2328 *ifflagsp |= IFF_OACTIVE; 2329 bus_dmamap_unload(dmat, dmam); 2330 m_freem(m0); 2331 return NULL; 2332 } 2333 return m0; 2334 } 2335 2336 static void 2337 rtw_start(struct ifnet *ifp) 2338 { 2339 int desc, i, lastdesc, npkt, rate; 2340 uint32_t proto_txctl0, txctl0, txctl1; 2341 bus_dmamap_t dmamap; 2342 struct ieee80211com *ic; 2343 struct ieee80211_duration *d0; 2344 struct ieee80211_frame *wh; 2345 struct ieee80211_node *ni; 2346 struct mbuf *m0; 2347 struct rtw_softc *sc; 2348 struct rtw_txctl_blk *stc; 2349 struct rtw_txdesc_blk *htc; 2350 struct rtw_txctl *stx; 2351 struct rtw_txdesc *htx; 2352 2353 sc = (struct rtw_softc *)ifp->if_softc; 2354 ic = &sc->sc_ic; 2355 2356 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2357 2358 /* XXX do real rate control */ 2359 proto_txctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 2360 2361 switch (rate = MAX(2, ieee80211_get_rate(ic))) { 2362 case 2: 2363 proto_txctl0 |= RTW_TXCTL0_RATE_1MBPS; 2364 break; 2365 case 4: 2366 proto_txctl0 |= RTW_TXCTL0_RATE_2MBPS; 2367 break; 2368 case 11: 2369 proto_txctl0 |= RTW_TXCTL0_RATE_5MBPS; 2370 break; 2371 case 22: 2372 proto_txctl0 |= RTW_TXCTL0_RATE_11MBPS; 2373 break; 2374 } 2375 2376 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 2377 proto_txctl0 |= RTW_TXCTL0_SPLCP; 2378 2379 for (;;) { 2380 if (rtw_dequeue(ifp, &stc, &htc, &m0, &ni) == -1) 2381 continue; 2382 if (m0 == NULL) 2383 break; 2384 stx = SIMPLEQ_FIRST(&stc->stc_freeq); 2385 2386 dmamap = stx->stx_dmamap; 2387 2388 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 2389 htc->htc_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 2390 2391 if (m0 == NULL || dmamap->dm_nsegs == 0) { 2392 DPRINTF2(sc, ("%s: fail dmamap load\n", __func__)); 2393 goto post_dequeue_err; 2394 } 2395 2396 txctl0 = proto_txctl0 | 2397 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 2398 2399 wh = mtod(m0, struct ieee80211_frame *); 2400 2401 if (ieee80211_compute_duration(wh, 2402 m0->m_pkthdr.len - sizeof(wh), 2403 ic->ic_flags, ic->ic_fragthreshold, 2404 rate, &stx->stx_d0, &stx->stx_dn, &npkt) == -1) { 2405 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 2406 goto post_load_err; 2407 } 2408 2409 /* XXX >= ? */ 2410 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 2411 txctl0 |= RTW_TXCTL0_RTSEN; 2412 2413 d0 = &stx->stx_d0; 2414 2415 txctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 2416 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 2417 2418 if ((d0->d_plcp_svc & IEEE80211_PLCP_SERVICE_LENEXT) != 0) 2419 txctl1 |= RTW_TXCTL1_LENGEXT; 2420 2421 /* TBD fragmentation */ 2422 2423 stx->stx_first = htc->htc_next; 2424 2425 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2426 htc, stx->stx_first, dmamap->dm_nsegs, 2427 BUS_DMASYNC_PREWRITE); 2428 2429 for (i = 0, lastdesc = desc = stx->stx_first; 2430 i < dmamap->dm_nsegs; 2431 i++, desc = RTW_NEXT_IDX(htc, desc)) { 2432 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 2433 DPRINTF2(sc, ("%s: seg too long\n", __func__)); 2434 goto post_load_err; 2435 } 2436 htx = &htc->htc_desc[desc]; 2437 htx->htx_ctl0 = htole32(txctl0); 2438 if (i != 0) 2439 htx->htx_ctl0 |= htole32(RTW_TXCTL0_OWN); 2440 htx->htx_ctl1 = htole32(txctl1); 2441 htx->htx_buf = htole32(dmamap->dm_segs[i].ds_addr); 2442 htx->htx_len = htole32(dmamap->dm_segs[i].ds_len); 2443 lastdesc = desc; 2444 DPRINTF2(sc, ("%s: stx %p txdesc[%d] ctl0 %#08x " 2445 "ctl1 %#08x buf %#08x len %#08x\n", 2446 sc->sc_dev.dv_xname, stx, desc, htx->htx_ctl0, 2447 htx->htx_ctl1, htx->htx_buf, htx->htx_len)); 2448 } 2449 2450 htc->htc_desc[lastdesc].htx_ctl0 |= htole32(RTW_TXCTL0_LS); 2451 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2452 htole32(RTW_TXCTL0_FS); 2453 2454 DPRINTF2(sc, ("%s: stx %p FS on txdesc[%d], LS on txdesc[%d]\n", 2455 sc->sc_dev.dv_xname, stx, lastdesc, stx->stx_first)); 2456 2457 stx->stx_ni = ni; 2458 stx->stx_mbuf = m0; 2459 stx->stx_last = lastdesc; 2460 2461 htc->htc_nfree -= dmamap->dm_nsegs; 2462 htc->htc_next = desc; 2463 2464 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2465 htc, stx->stx_first, dmamap->dm_nsegs, 2466 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2467 2468 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2469 htole32(RTW_TXCTL0_OWN); 2470 2471 DPRINTF2(sc, ("%s: stx %p OWN on txdesc[%d]\n", 2472 sc->sc_dev.dv_xname, stx, stx->stx_first)); 2473 2474 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2475 htc, stx->stx_first, 1, 2476 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2477 2478 SIMPLEQ_REMOVE_HEAD(&stc->stc_freeq, stx_q); 2479 SIMPLEQ_INSERT_TAIL(&stc->stc_dirtyq, stx, stx_q); 2480 2481 /* TBD poke just one txmtr? */ 2482 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, 2483 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ | RTW_TPPOLL_HPQ | 2484 RTW_TPPOLL_BQ); 2485 } 2486 DPRINTF2(sc, ("%s: leave\n", __func__)); 2487 return; 2488 post_load_err: 2489 bus_dmamap_unload(sc->sc_dmat, dmamap); 2490 m_freem(m0); 2491 post_dequeue_err: 2492 ieee80211_release_node(&sc->sc_ic, ni); 2493 return; 2494 } 2495 2496 static void 2497 rtw_watchdog(struct ifnet *ifp) 2498 { 2499 int pri; 2500 struct rtw_softc *sc; 2501 struct rtw_txctl_blk *stc; 2502 2503 sc = ifp->if_softc; 2504 2505 ifp->if_timer = 0; 2506 2507 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2508 return; 2509 2510 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2511 stc = &sc->sc_txctl_blk[pri]; 2512 2513 if (stc->stc_tx_timer == 0) 2514 continue; 2515 2516 if (--stc->stc_tx_timer == 0) { 2517 if (SIMPLEQ_EMPTY(&stc->stc_dirtyq)) 2518 continue; 2519 printf("%s: transmit timeout, priority %d\n", 2520 ifp->if_xname, pri); 2521 ifp->if_oerrors++; 2522 /* XXX be gentle */ 2523 (void)rtw_init(ifp); 2524 rtw_start(ifp); 2525 } else 2526 ifp->if_timer = 1; 2527 } 2528 /* TBD */ 2529 return; 2530 } 2531 2532 static void 2533 rtw_start_beacon(struct rtw_softc *sc, int enable) 2534 { 2535 /* TBD */ 2536 return; 2537 } 2538 2539 static void 2540 rtw_next_scan(void *arg) 2541 { 2542 struct ieee80211com *ic = arg; 2543 int s; 2544 2545 /* don't call rtw_start w/o network interrupts blocked */ 2546 s = splnet(); 2547 if (ic->ic_state == IEEE80211_S_SCAN) 2548 ieee80211_next_scan(ic); 2549 splx(s); 2550 } 2551 2552 /* Synchronize the hardware state with the software state. */ 2553 static int 2554 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2555 { 2556 struct ifnet *ifp = &ic->ic_if; 2557 struct rtw_softc *sc = ifp->if_softc; 2558 enum ieee80211_state ostate; 2559 int error; 2560 2561 ostate = ic->ic_state; 2562 2563 if (nstate == IEEE80211_S_INIT) { 2564 callout_stop(&sc->sc_scan_ch); 2565 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2566 rtw_start_beacon(sc, 0); 2567 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2568 } 2569 2570 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 2571 rtw_pwrstate(sc, RTW_ON); 2572 2573 if ((error = rtw_tune(sc)) != 0) 2574 return error; 2575 2576 switch (nstate) { 2577 case IEEE80211_S_ASSOC: 2578 break; 2579 case IEEE80211_S_INIT: 2580 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2581 break; 2582 case IEEE80211_S_SCAN: 2583 #if 0 2584 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2585 rtw_write_bssid(sc); 2586 #endif 2587 2588 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 2589 rtw_next_scan, ic); 2590 2591 break; 2592 case IEEE80211_S_RUN: 2593 if (ic->ic_opmode == IEEE80211_M_STA) 2594 break; 2595 /*FALLTHROUGH*/ 2596 case IEEE80211_S_AUTH: 2597 #if 0 2598 rtw_write_bssid(sc); 2599 rtw_write_bcn_thresh(sc); 2600 rtw_write_ssid(sc); 2601 rtw_write_sup_rates(sc); 2602 #endif 2603 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2604 ic->ic_opmode == IEEE80211_M_MONITOR) 2605 break; 2606 2607 /* TBD set listen interval, beacon interval */ 2608 2609 #if 0 2610 rtw_tsf(sc); 2611 #endif 2612 break; 2613 } 2614 2615 if (nstate != IEEE80211_S_SCAN) 2616 callout_stop(&sc->sc_scan_ch); 2617 2618 if (nstate == IEEE80211_S_RUN && 2619 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2620 ic->ic_opmode == IEEE80211_M_IBSS)) 2621 rtw_start_beacon(sc, 1); 2622 else 2623 rtw_start_beacon(sc, 0); 2624 2625 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2626 } 2627 2628 static void 2629 rtw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2630 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2631 { 2632 /* TBD */ 2633 return; 2634 } 2635 2636 static void 2637 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2638 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2639 { 2640 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 2641 2642 switch (subtype) { 2643 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2644 /* do nothing: hardware answers probe request XXX */ 2645 break; 2646 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2647 case IEEE80211_FC0_SUBTYPE_BEACON: 2648 rtw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2649 break; 2650 default: 2651 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2652 break; 2653 } 2654 return; 2655 } 2656 2657 static struct ieee80211_node * 2658 rtw_node_alloc(struct ieee80211com *ic) 2659 { 2660 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2661 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 2662 2663 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 2664 return ni; 2665 } 2666 2667 static void 2668 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 2669 { 2670 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2671 2672 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 2673 ether_sprintf(ni->ni_bssid))); 2674 (*sc->sc_mtbl.mt_node_free)(ic, ni); 2675 } 2676 2677 static int 2678 rtw_media_change(struct ifnet *ifp) 2679 { 2680 int error; 2681 2682 error = ieee80211_media_change(ifp); 2683 if (error == ENETRESET) { 2684 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 2685 (IFF_RUNNING|IFF_UP)) 2686 rtw_init(ifp); /* XXX lose error */ 2687 error = 0; 2688 } 2689 return error; 2690 } 2691 2692 static void 2693 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 2694 { 2695 struct rtw_softc *sc = ifp->if_softc; 2696 2697 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2698 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 2699 imr->ifm_status = 0; 2700 return; 2701 } 2702 ieee80211_media_status(ifp, imr); 2703 } 2704 2705 void 2706 rtw_power(int why, void *arg) 2707 { 2708 struct rtw_softc *sc = arg; 2709 struct ifnet *ifp = &sc->sc_ic.ic_if; 2710 int s; 2711 2712 DPRINTF(sc, ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 2713 2714 s = splnet(); 2715 switch (why) { 2716 case PWR_STANDBY: 2717 /* XXX do nothing. */ 2718 break; 2719 case PWR_SUSPEND: 2720 rtw_stop(ifp, 0); 2721 if (sc->sc_power != NULL) 2722 (*sc->sc_power)(sc, why); 2723 break; 2724 case PWR_RESUME: 2725 if (ifp->if_flags & IFF_UP) { 2726 if (sc->sc_power != NULL) 2727 (*sc->sc_power)(sc, why); 2728 rtw_init(ifp); 2729 } 2730 break; 2731 case PWR_SOFTSUSPEND: 2732 case PWR_SOFTSTANDBY: 2733 case PWR_SOFTRESUME: 2734 break; 2735 } 2736 splx(s); 2737 } 2738 2739 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 2740 void 2741 rtw_shutdown(void *arg) 2742 { 2743 struct rtw_softc *sc = arg; 2744 2745 rtw_stop(&sc->sc_ic.ic_if, 1); 2746 } 2747 2748 static __inline void 2749 rtw_setifprops(struct ifnet *ifp, char (*dvname)[IFNAMSIZ], void *softc) 2750 { 2751 (void)memcpy(ifp->if_xname, *dvname, IFNAMSIZ); 2752 ifp->if_softc = softc; 2753 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 2754 IFF_NOTRAILERS; 2755 ifp->if_ioctl = rtw_ioctl; 2756 ifp->if_start = rtw_start; 2757 ifp->if_watchdog = rtw_watchdog; 2758 ifp->if_init = rtw_init; 2759 ifp->if_stop = rtw_stop; 2760 } 2761 2762 static __inline void 2763 rtw_set80211props(struct ieee80211com *ic) 2764 { 2765 int nrate; 2766 ic->ic_phytype = IEEE80211_T_DS; 2767 ic->ic_opmode = IEEE80211_M_STA; 2768 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 2769 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 2770 2771 nrate = 0; 2772 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 2773 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 2774 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 2775 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 2776 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 2777 } 2778 2779 static __inline void 2780 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 2781 { 2782 mtbl->mt_newstate = ic->ic_newstate; 2783 ic->ic_newstate = rtw_newstate; 2784 2785 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 2786 ic->ic_recv_mgmt = rtw_recv_mgmt; 2787 2788 mtbl->mt_node_free = ic->ic_node_free; 2789 ic->ic_node_free = rtw_node_free; 2790 2791 mtbl->mt_node_alloc = ic->ic_node_alloc; 2792 ic->ic_node_alloc = rtw_node_alloc; 2793 } 2794 2795 static __inline void 2796 rtw_establish_hooks(struct rtw_hooks *hooks, char (*dvname)[IFNAMSIZ], 2797 void *arg) 2798 { 2799 /* 2800 * Make sure the interface is shutdown during reboot. 2801 */ 2802 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 2803 if (hooks->rh_shutdown == NULL) 2804 printf("%s: WARNING: unable to establish shutdown hook\n", 2805 *dvname); 2806 2807 /* 2808 * Add a suspend hook to make sure we come back up after a 2809 * resume. 2810 */ 2811 hooks->rh_power = powerhook_establish(rtw_power, arg); 2812 if (hooks->rh_power == NULL) 2813 printf("%s: WARNING: unable to establish power hook\n", 2814 *dvname); 2815 } 2816 2817 static __inline void 2818 rtw_disestablish_hooks(struct rtw_hooks *hooks, char (*dvname)[IFNAMSIZ], 2819 void *arg) 2820 { 2821 if (hooks->rh_shutdown != NULL) 2822 shutdownhook_disestablish(hooks->rh_shutdown); 2823 2824 if (hooks->rh_power != NULL) 2825 powerhook_disestablish(hooks->rh_power); 2826 } 2827 2828 static __inline void 2829 rtw_init_radiotap(struct rtw_softc *sc) 2830 { 2831 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 2832 sc->sc_rxtap.rr_ihdr.it_len = sizeof(sc->sc_rxtapu); 2833 sc->sc_rxtap.rr_ihdr.it_present = RTW_RX_RADIOTAP_PRESENT; 2834 2835 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 2836 sc->sc_txtap.rt_ihdr.it_len = sizeof(sc->sc_txtapu); 2837 sc->sc_txtap.rt_ihdr.it_present = RTW_TX_RADIOTAP_PRESENT; 2838 } 2839 2840 static int 2841 rtw_txctl_blk_setup(struct rtw_txctl_blk *stc, u_int qlen) 2842 { 2843 SIMPLEQ_INIT(&stc->stc_dirtyq); 2844 SIMPLEQ_INIT(&stc->stc_freeq); 2845 stc->stc_ndesc = qlen; 2846 stc->stc_desc = malloc(qlen * sizeof(*stc->stc_desc), M_DEVBUF, 2847 M_NOWAIT); 2848 if (stc->stc_desc == NULL) 2849 return ENOMEM; 2850 return 0; 2851 } 2852 2853 static void 2854 rtw_txctl_blk_cleanup_all(struct rtw_softc *sc) 2855 { 2856 struct rtw_txctl_blk *stc; 2857 int qlen[RTW_NTXPRI] = 2858 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2859 int pri; 2860 2861 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2862 stc = &sc->sc_txctl_blk[pri]; 2863 free(stc->stc_desc, M_DEVBUF); 2864 stc->stc_desc = NULL; 2865 } 2866 } 2867 2868 static int 2869 rtw_txctl_blk_setup_all(struct rtw_softc *sc) 2870 { 2871 int pri, rc = 0; 2872 int qlen[RTW_NTXPRI] = 2873 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2874 2875 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2876 rc = rtw_txctl_blk_setup(&sc->sc_txctl_blk[pri], qlen[pri]); 2877 if (rc != 0) 2878 break; 2879 } 2880 return rc; 2881 } 2882 2883 static void 2884 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *htc, struct rtw_txdesc *desc, 2885 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 2886 { 2887 int i; 2888 2889 htc->htc_ndesc = ndesc; 2890 htc->htc_desc = desc; 2891 htc->htc_physbase = physbase; 2892 htc->htc_ofs = ofs; 2893 2894 (void)memset(htc->htc_desc, 0, 2895 sizeof(htc->htc_desc[0]) * htc->htc_ndesc); 2896 2897 for (i = 0; i < htc->htc_ndesc; i++) { 2898 htc->htc_desc[i].htx_next = htole32(RTW_NEXT_DESC(htc, i)); 2899 } 2900 } 2901 2902 static void 2903 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 2904 { 2905 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 2906 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 2907 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 2908 2909 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 2910 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 2911 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 2912 2913 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 2914 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 2915 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 2916 2917 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 2918 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 2919 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 2920 } 2921 2922 static struct rtw_rf * 2923 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, 2924 rtw_rf_write_t rf_write, int digphy) 2925 { 2926 struct rtw_rf *rf; 2927 2928 switch (rfchipid) { 2929 case RTW_RFCHIPID_MAXIM: 2930 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 2931 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 2932 break; 2933 case RTW_RFCHIPID_PHILIPS: 2934 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 2935 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 2936 break; 2937 default: 2938 return NULL; 2939 } 2940 rf->rf_continuous_tx_cb = 2941 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 2942 rf->rf_continuous_tx_arg = (void *)sc; 2943 return rf; 2944 } 2945 2946 /* Revision C and later use a different PHY delay setting than 2947 * revisions A and B. 2948 */ 2949 static u_int8_t 2950 rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0) 2951 { 2952 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 2953 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 2954 2955 u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 2956 2957 RTW_WRITE(regs, RTW_RCR, REVAB); 2958 RTW_WRITE(regs, RTW_RCR, REVC); 2959 2960 RTW_WBR(regs, RTW_RCR, RTW_RCR); 2961 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 2962 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 2963 2964 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 2965 2966 return phydelay; 2967 #undef REVC 2968 } 2969 2970 void 2971 rtw_attach(struct rtw_softc *sc) 2972 { 2973 rtw_rf_write_t rf_write; 2974 struct rtw_txctl_blk *stc; 2975 int pri, rc, vers; 2976 2977 #if 0 2978 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_txdesc) == 0, 2979 "RTW_DESC_ALIGNMENT is not a multiple of " 2980 "sizeof(struct rtw_txdesc)"); 2981 2982 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_rxdesc) == 0, 2983 "RTW_DESC_ALIGNMENT is not a multiple of " 2984 "sizeof(struct rtw_rxdesc)"); 2985 2986 CASSERT(RTW_DESC_ALIGNMENT % RTW_MAXPKTSEGS == 0, 2987 "RTW_DESC_ALIGNMENT is not a multiple of RTW_MAXPKTSEGS"); 2988 #endif 2989 2990 NEXT_ATTACH_STATE(sc, DETACHED); 2991 2992 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 2993 case RTW_TCR_HWVERID_F: 2994 vers = 'F'; 2995 rf_write = rtw_rf_hostwrite; 2996 break; 2997 case RTW_TCR_HWVERID_D: 2998 vers = 'D'; 2999 if (rtw_host_rfio) 3000 rf_write = rtw_rf_hostwrite; 3001 else 3002 rf_write = rtw_rf_macwrite; 3003 break; 3004 default: 3005 vers = '?'; 3006 rf_write = rtw_rf_macwrite; 3007 break; 3008 } 3009 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, vers); 3010 3011 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3012 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3013 0); 3014 3015 if (rc != 0) { 3016 printf("%s: could not allocate hw descriptors, error %d\n", 3017 sc->sc_dev.dv_xname, rc); 3018 goto err; 3019 } 3020 3021 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3022 3023 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3024 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3025 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3026 3027 if (rc != 0) { 3028 printf("%s: could not map hw descriptors, error %d\n", 3029 sc->sc_dev.dv_xname, rc); 3030 goto err; 3031 } 3032 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3033 3034 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3035 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3036 3037 if (rc != 0) { 3038 printf("%s: could not create DMA map for hw descriptors, " 3039 "error %d\n", sc->sc_dev.dv_xname, rc); 3040 goto err; 3041 } 3042 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3043 3044 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3045 sizeof(struct rtw_descs), NULL, 0); 3046 3047 if (rc != 0) { 3048 printf("%s: could not load DMA map for hw descriptors, " 3049 "error %d\n", sc->sc_dev.dv_xname, rc); 3050 goto err; 3051 } 3052 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3053 3054 if (rtw_txctl_blk_setup_all(sc) != 0) 3055 goto err; 3056 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3057 3058 rtw_txdesc_blk_setup_all(sc); 3059 3060 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3061 3062 sc->sc_rxdesc = &sc->sc_descs->hd_rx[0]; 3063 3064 rtw_rxctls_setup(&sc->sc_rxctl[0]); 3065 3066 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3067 stc = &sc->sc_txctl_blk[pri]; 3068 3069 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3070 &stc->stc_desc[0], stc->stc_ndesc)) != 0) { 3071 printf("%s: could not load DMA map for " 3072 "hw tx descriptors, error %d\n", 3073 sc->sc_dev.dv_xname, rc); 3074 goto err; 3075 } 3076 } 3077 3078 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3079 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxctl[0], 3080 RTW_RXQLEN)) != 0) { 3081 printf("%s: could not load DMA map for hw rx descriptors, " 3082 "error %d\n", sc->sc_dev.dv_xname, rc); 3083 goto err; 3084 } 3085 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3086 3087 /* Reset the chip to a known state. */ 3088 if (rtw_reset(sc) != 0) 3089 goto err; 3090 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3091 3092 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3093 3094 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3095 sc->sc_flags |= RTW_F_9356SROM; 3096 3097 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3098 &sc->sc_dev.dv_xname) != 0) 3099 goto err; 3100 3101 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3102 3103 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3104 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3105 &sc->sc_dev.dv_xname) != 0) { 3106 printf("%s: attach failed, malformed serial ROM\n", 3107 sc->sc_dev.dv_xname); 3108 goto err; 3109 } 3110 3111 RTW_DPRINTF(("%s: CS threshold %u\n", sc->sc_dev.dv_xname, 3112 sc->sc_csthr)); 3113 3114 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3115 3116 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, rf_write, 3117 sc->sc_flags & RTW_F_DIGPHY); 3118 3119 if (sc->sc_rf == NULL) { 3120 printf("%s: attach failed, could not attach RF\n", 3121 sc->sc_dev.dv_xname); 3122 goto err; 3123 } 3124 3125 #if 0 3126 if (rtw_identify_rf(&sc->sc_regs, &sc->sc_rftype, 3127 &sc->sc_dev.dv_xname) != 0) { 3128 printf("%s: attach failed, unknown RF unidentified\n", 3129 sc->sc_dev.dv_xname); 3130 goto err; 3131 } 3132 #endif 3133 3134 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3135 3136 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 3137 3138 RTW_DPRINTF(("%s: PHY delay %d\n", sc->sc_dev.dv_xname, 3139 sc->sc_phydelay)); 3140 3141 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 3142 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 3143 &sc->sc_dev.dv_xname); 3144 3145 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 3146 &sc->sc_dev.dv_xname); 3147 3148 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 3149 &sc->sc_dev.dv_xname) != 0) 3150 goto err; 3151 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 3152 3153 rtw_setifprops(&sc->sc_if, &sc->sc_dev.dv_xname, (void*)sc); 3154 3155 IFQ_SET_READY(&sc->sc_if.if_snd); 3156 3157 rtw_set80211props(&sc->sc_ic); 3158 3159 /* 3160 * Call MI attach routines. 3161 */ 3162 if_attach(&sc->sc_if); 3163 ieee80211_ifattach(&sc->sc_if); 3164 3165 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 3166 3167 /* possibly we should fill in our own sc_send_prresp, since 3168 * the RTL8180 is probably sending probe responses in ad hoc 3169 * mode. 3170 */ 3171 3172 /* complete initialization */ 3173 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 3174 callout_init(&sc->sc_scan_ch); 3175 3176 #if NBPFILTER > 0 3177 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 3178 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 3179 #endif 3180 3181 rtw_establish_hooks(&sc->sc_hooks, &sc->sc_dev.dv_xname, (void*)sc); 3182 3183 rtw_init_radiotap(sc); 3184 3185 NEXT_ATTACH_STATE(sc, FINISHED); 3186 3187 return; 3188 err: 3189 rtw_detach(sc); 3190 return; 3191 } 3192 3193 int 3194 rtw_detach(struct rtw_softc *sc) 3195 { 3196 int pri; 3197 3198 switch (sc->sc_attach_state) { 3199 case FINISHED: 3200 rtw_stop(&sc->sc_if, 1); 3201 3202 rtw_disestablish_hooks(&sc->sc_hooks, &sc->sc_dev.dv_xname, 3203 (void*)sc); 3204 callout_stop(&sc->sc_scan_ch); 3205 ieee80211_ifdetach(&sc->sc_if); 3206 if_detach(&sc->sc_if); 3207 break; 3208 case FINISH_ID_STA: 3209 case FINISH_RF_ATTACH: 3210 rtw_rf_destroy(sc->sc_rf); 3211 sc->sc_rf = NULL; 3212 /*FALLTHROUGH*/ 3213 case FINISH_PARSE_SROM: 3214 case FINISH_READ_SROM: 3215 rtw_srom_free(&sc->sc_srom); 3216 /*FALLTHROUGH*/ 3217 case FINISH_RESET: 3218 case FINISH_RXMAPS_CREATE: 3219 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxctl[0], 3220 RTW_RXQLEN); 3221 /*FALLTHROUGH*/ 3222 case FINISH_TXMAPS_CREATE: 3223 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3224 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 3225 sc->sc_txctl_blk[pri].stc_desc, 3226 sc->sc_txctl_blk[pri].stc_ndesc); 3227 } 3228 /*FALLTHROUGH*/ 3229 case FINISH_TXDESCBLK_SETUP: 3230 case FINISH_TXCTLBLK_SETUP: 3231 rtw_txctl_blk_cleanup_all(sc); 3232 /*FALLTHROUGH*/ 3233 case FINISH_DESCMAP_LOAD: 3234 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 3235 /*FALLTHROUGH*/ 3236 case FINISH_DESCMAP_CREATE: 3237 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 3238 /*FALLTHROUGH*/ 3239 case FINISH_DESC_MAP: 3240 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 3241 sizeof(struct rtw_descs)); 3242 /*FALLTHROUGH*/ 3243 case FINISH_DESC_ALLOC: 3244 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 3245 sc->sc_desc_nsegs); 3246 /*FALLTHROUGH*/ 3247 case DETACHED: 3248 NEXT_ATTACH_STATE(sc, DETACHED); 3249 break; 3250 } 3251 return 0; 3252 } 3253 3254 int 3255 rtw_activate(struct device *self, enum devact act) 3256 { 3257 struct rtw_softc *sc = (struct rtw_softc *)self; 3258 int rc = 0, s; 3259 3260 s = splnet(); 3261 switch (act) { 3262 case DVACT_ACTIVATE: 3263 rc = EOPNOTSUPP; 3264 break; 3265 3266 case DVACT_DEACTIVATE: 3267 if_deactivate(&sc->sc_ic.ic_if); 3268 break; 3269 } 3270 splx(s); 3271 return rc; 3272 } 3273
Indexes created Thu Sep 25 16:09:42 GMT 2025