rtw.c revision 1.55
1 /* $NetBSD: rtw.c,v 1.55 2005/09/07 05:25:41 dogcow Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.55 2005/09/07 05:25:41 dogcow Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/time.h> 49 #include <sys/types.h> 50 51 #include <machine/endian.h> 52 #include <machine/bus.h> 53 #include <machine/intr.h> /* splnet */ 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <dev/ic/rtwreg.h> 70 #include <dev/ic/rtwvar.h> 71 #include <dev/ic/rtwphyio.h> 72 #include <dev/ic/rtwphy.h> 73 74 #include <dev/ic/smc93cx6var.h> 75 76 #define KASSERT2(__cond, __msg) \ 77 do { \ 78 if (!(__cond)) \ 79 panic __msg ; \ 80 } while (0) 81 82 int rtw_rfprog_fallback = 0; 83 int rtw_host_rfio = 0; 84 85 #ifdef RTW_DEBUG 86 int rtw_debug = 0; 87 int rtw_rxbufs_limit = RTW_RXQLEN; 88 #endif /* RTW_DEBUG */ 89 90 #define NEXT_ATTACH_STATE(sc, state) do { \ 91 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 92 ("%s: attach state %s\n", __func__, #state)); \ 93 sc->sc_attach_state = state; \ 94 } while (0) 95 96 int rtw_dwelltime = 200; /* milliseconds */ 97 static struct ieee80211_cipher rtw_cipher_wep; 98 99 static void rtw_start(struct ifnet *); 100 101 static void rtw_io_enable(struct rtw_regs *, uint8_t, int); 102 static int rtw_key_alloc(struct ieee80211com *, const struct ieee80211_key *); 103 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 104 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 105 const u_int8_t[IEEE80211_ADDR_LEN]); 106 static void rtw_key_update_end(struct ieee80211com *); 107 static void rtw_key_update_begin(struct ieee80211com *); 108 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 109 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 110 111 static void rtw_led_attach(struct rtw_led_state *, void *); 112 static void rtw_led_init(struct rtw_regs *); 113 static void rtw_led_slowblink(void *); 114 static void rtw_led_fastblink(void *); 115 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 116 117 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 118 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 119 #ifdef RTW_DEBUG 120 static void rtw_print_txdesc(struct rtw_softc *, const char *, 121 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 122 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 123 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 124 #endif /* RTW_DEBUG */ 125 126 /* 127 * Setup sysctl(3) MIB, hw.rtw.* 128 * 129 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 130 */ 131 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 132 { 133 int rc; 134 const struct sysctlnode *cnode, *rnode; 135 136 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 137 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 138 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 139 goto err; 140 141 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 142 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 143 "Realtek RTL818x 802.11 controls", 144 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 145 goto err; 146 147 #ifdef RTW_DEBUG 148 /* control debugging printfs */ 149 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 150 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 151 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 152 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 153 CTL_CREATE, CTL_EOL)) != 0) 154 goto err; 155 156 /* Limit rx buffers, for simulating resource exhaustion. */ 157 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 158 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 159 "rxbufs_limit", 160 SYSCTL_DESCR("Set rx buffers limit"), 161 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 162 CTL_CREATE, CTL_EOL)) != 0) 163 goto err; 164 165 #endif /* RTW_DEBUG */ 166 /* set fallback RF programming method */ 167 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 168 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 169 "rfprog_fallback", 170 SYSCTL_DESCR("Set fallback RF programming method"), 171 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 172 CTL_CREATE, CTL_EOL)) != 0) 173 goto err; 174 175 /* force host to control RF I/O bus */ 176 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 177 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 178 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 179 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 180 CTL_CREATE, CTL_EOL)) != 0) 181 goto err; 182 183 return; 184 err: 185 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 186 } 187 188 static int 189 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 190 { 191 int error, t; 192 struct sysctlnode node; 193 194 node = *rnode; 195 t = *(int*)rnode->sysctl_data; 196 node.sysctl_data = &t; 197 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 198 if (error || newp == NULL) 199 return (error); 200 201 if (t < lower || t > upper) 202 return (EINVAL); 203 204 *(int*)rnode->sysctl_data = t; 205 206 return (0); 207 } 208 209 static int 210 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 211 { 212 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 213 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 214 } 215 216 static int 217 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 218 { 219 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 220 } 221 222 #ifdef RTW_DEBUG 223 static int 224 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 225 { 226 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 227 0, RTW_DEBUG_MAX); 228 } 229 230 static int 231 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 232 { 233 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 234 0, RTW_RXQLEN); 235 } 236 237 static void 238 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 239 { 240 #define PRINTREG32(sc, reg) \ 241 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 242 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 243 dvname, reg, RTW_READ(regs, reg))) 244 245 #define PRINTREG16(sc, reg) \ 246 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 247 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 248 dvname, reg, RTW_READ16(regs, reg))) 249 250 #define PRINTREG8(sc, reg) \ 251 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 252 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 253 dvname, reg, RTW_READ8(regs, reg))) 254 255 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 256 257 PRINTREG32(regs, RTW_IDR0); 258 PRINTREG32(regs, RTW_IDR1); 259 PRINTREG32(regs, RTW_MAR0); 260 PRINTREG32(regs, RTW_MAR1); 261 PRINTREG32(regs, RTW_TSFTRL); 262 PRINTREG32(regs, RTW_TSFTRH); 263 PRINTREG32(regs, RTW_TLPDA); 264 PRINTREG32(regs, RTW_TNPDA); 265 PRINTREG32(regs, RTW_THPDA); 266 PRINTREG32(regs, RTW_TCR); 267 PRINTREG32(regs, RTW_RCR); 268 PRINTREG32(regs, RTW_TINT); 269 PRINTREG32(regs, RTW_TBDA); 270 PRINTREG32(regs, RTW_ANAPARM); 271 PRINTREG32(regs, RTW_BB); 272 PRINTREG32(regs, RTW_PHYCFG); 273 PRINTREG32(regs, RTW_WAKEUP0L); 274 PRINTREG32(regs, RTW_WAKEUP0H); 275 PRINTREG32(regs, RTW_WAKEUP1L); 276 PRINTREG32(regs, RTW_WAKEUP1H); 277 PRINTREG32(regs, RTW_WAKEUP2LL); 278 PRINTREG32(regs, RTW_WAKEUP2LH); 279 PRINTREG32(regs, RTW_WAKEUP2HL); 280 PRINTREG32(regs, RTW_WAKEUP2HH); 281 PRINTREG32(regs, RTW_WAKEUP3LL); 282 PRINTREG32(regs, RTW_WAKEUP3LH); 283 PRINTREG32(regs, RTW_WAKEUP3HL); 284 PRINTREG32(regs, RTW_WAKEUP3HH); 285 PRINTREG32(regs, RTW_WAKEUP4LL); 286 PRINTREG32(regs, RTW_WAKEUP4LH); 287 PRINTREG32(regs, RTW_WAKEUP4HL); 288 PRINTREG32(regs, RTW_WAKEUP4HH); 289 PRINTREG32(regs, RTW_DK0); 290 PRINTREG32(regs, RTW_DK1); 291 PRINTREG32(regs, RTW_DK2); 292 PRINTREG32(regs, RTW_DK3); 293 PRINTREG32(regs, RTW_RETRYCTR); 294 PRINTREG32(regs, RTW_RDSAR); 295 PRINTREG32(regs, RTW_FER); 296 PRINTREG32(regs, RTW_FEMR); 297 PRINTREG32(regs, RTW_FPSR); 298 PRINTREG32(regs, RTW_FFER); 299 300 /* 16-bit registers */ 301 PRINTREG16(regs, RTW_BRSR); 302 PRINTREG16(regs, RTW_IMR); 303 PRINTREG16(regs, RTW_ISR); 304 PRINTREG16(regs, RTW_BCNITV); 305 PRINTREG16(regs, RTW_ATIMWND); 306 PRINTREG16(regs, RTW_BINTRITV); 307 PRINTREG16(regs, RTW_ATIMTRITV); 308 PRINTREG16(regs, RTW_CRC16ERR); 309 PRINTREG16(regs, RTW_CRC0); 310 PRINTREG16(regs, RTW_CRC1); 311 PRINTREG16(regs, RTW_CRC2); 312 PRINTREG16(regs, RTW_CRC3); 313 PRINTREG16(regs, RTW_CRC4); 314 PRINTREG16(regs, RTW_CWR); 315 316 /* 8-bit registers */ 317 PRINTREG8(regs, RTW_CR); 318 PRINTREG8(regs, RTW_9346CR); 319 PRINTREG8(regs, RTW_CONFIG0); 320 PRINTREG8(regs, RTW_CONFIG1); 321 PRINTREG8(regs, RTW_CONFIG2); 322 PRINTREG8(regs, RTW_MSR); 323 PRINTREG8(regs, RTW_CONFIG3); 324 PRINTREG8(regs, RTW_CONFIG4); 325 PRINTREG8(regs, RTW_TESTR); 326 PRINTREG8(regs, RTW_PSR); 327 PRINTREG8(regs, RTW_SCR); 328 PRINTREG8(regs, RTW_PHYDELAY); 329 PRINTREG8(regs, RTW_CRCOUNT); 330 PRINTREG8(regs, RTW_PHYADDR); 331 PRINTREG8(regs, RTW_PHYDATAW); 332 PRINTREG8(regs, RTW_PHYDATAR); 333 PRINTREG8(regs, RTW_CONFIG5); 334 PRINTREG8(regs, RTW_TPPOLL); 335 336 PRINTREG16(regs, RTW_BSSID16); 337 PRINTREG32(regs, RTW_BSSID32); 338 #undef PRINTREG32 339 #undef PRINTREG16 340 #undef PRINTREG8 341 } 342 #endif /* RTW_DEBUG */ 343 344 void 345 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 346 { 347 struct rtw_regs *regs = &sc->sc_regs; 348 349 uint32_t tcr; 350 tcr = RTW_READ(regs, RTW_TCR); 351 tcr &= ~RTW_TCR_LBK_MASK; 352 if (enable) 353 tcr |= RTW_TCR_LBK_CONT; 354 else 355 tcr |= RTW_TCR_LBK_NORMAL; 356 RTW_WRITE(regs, RTW_TCR, tcr); 357 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 358 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 359 rtw_txdac_enable(sc, !enable); 360 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 361 rtw_set_access(regs, RTW_ACCESS_NONE); 362 } 363 364 #ifdef RTW_DEBUG 365 static const char * 366 rtw_access_string(enum rtw_access access) 367 { 368 switch (access) { 369 case RTW_ACCESS_NONE: 370 return "none"; 371 case RTW_ACCESS_CONFIG: 372 return "config"; 373 case RTW_ACCESS_ANAPARM: 374 return "anaparm"; 375 default: 376 return "unknown"; 377 } 378 } 379 #endif /* RTW_DEBUG */ 380 381 static void 382 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 383 { 384 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 385 KASSERT(regs->r_access >= RTW_ACCESS_NONE && 386 regs->r_access <= RTW_ACCESS_ANAPARM); 387 388 if (naccess == regs->r_access) 389 return; 390 391 switch (naccess) { 392 case RTW_ACCESS_NONE: 393 switch (regs->r_access) { 394 case RTW_ACCESS_ANAPARM: 395 rtw_anaparm_enable(regs, 0); 396 /*FALLTHROUGH*/ 397 case RTW_ACCESS_CONFIG: 398 rtw_config0123_enable(regs, 0); 399 /*FALLTHROUGH*/ 400 case RTW_ACCESS_NONE: 401 break; 402 } 403 break; 404 case RTW_ACCESS_CONFIG: 405 switch (regs->r_access) { 406 case RTW_ACCESS_NONE: 407 rtw_config0123_enable(regs, 1); 408 /*FALLTHROUGH*/ 409 case RTW_ACCESS_CONFIG: 410 break; 411 case RTW_ACCESS_ANAPARM: 412 rtw_anaparm_enable(regs, 0); 413 break; 414 } 415 break; 416 case RTW_ACCESS_ANAPARM: 417 switch (regs->r_access) { 418 case RTW_ACCESS_NONE: 419 rtw_config0123_enable(regs, 1); 420 /*FALLTHROUGH*/ 421 case RTW_ACCESS_CONFIG: 422 rtw_anaparm_enable(regs, 1); 423 /*FALLTHROUGH*/ 424 case RTW_ACCESS_ANAPARM: 425 break; 426 } 427 break; 428 } 429 } 430 431 void 432 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 433 { 434 rtw_set_access1(regs, access); 435 RTW_DPRINTF(RTW_DEBUG_ACCESS, 436 ("%s: access %s -> %s\n", __func__, 437 rtw_access_string(regs->r_access), 438 rtw_access_string(access))); 439 regs->r_access = access; 440 } 441 442 /* 443 * Enable registers, switch register banks. 444 */ 445 void 446 rtw_config0123_enable(struct rtw_regs *regs, int enable) 447 { 448 uint8_t ecr; 449 ecr = RTW_READ8(regs, RTW_9346CR); 450 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 451 if (enable) 452 ecr |= RTW_9346CR_EEM_CONFIG; 453 else { 454 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 455 ecr |= RTW_9346CR_EEM_NORMAL; 456 } 457 RTW_WRITE8(regs, RTW_9346CR, ecr); 458 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 459 } 460 461 /* requires rtw_config0123_enable(, 1) */ 462 void 463 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 464 { 465 uint8_t cfg3; 466 467 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 468 cfg3 |= RTW_CONFIG3_CLKRUNEN; 469 if (enable) 470 cfg3 |= RTW_CONFIG3_PARMEN; 471 else 472 cfg3 &= ~RTW_CONFIG3_PARMEN; 473 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 474 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 475 } 476 477 /* requires rtw_anaparm_enable(, 1) */ 478 void 479 rtw_txdac_enable(struct rtw_softc *sc, int enable) 480 { 481 uint32_t anaparm; 482 struct rtw_regs *regs = &sc->sc_regs; 483 484 anaparm = RTW_READ(regs, RTW_ANAPARM); 485 if (enable) 486 anaparm &= ~RTW_ANAPARM_TXDACOFF; 487 else 488 anaparm |= RTW_ANAPARM_TXDACOFF; 489 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 490 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 491 } 492 493 static __inline int 494 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 495 { 496 uint8_t cr; 497 int i; 498 499 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 500 501 RTW_WBR(regs, RTW_CR, RTW_CR); 502 503 for (i = 0; i < 1000; i++) { 504 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 505 RTW_DPRINTF(RTW_DEBUG_RESET, 506 ("%s: reset in %dus\n", dvname, i)); 507 return 0; 508 } 509 RTW_RBR(regs, RTW_CR, RTW_CR); 510 DELAY(10); /* 10us */ 511 } 512 513 printf("%s: reset failed\n", dvname); 514 return ETIMEDOUT; 515 } 516 517 static __inline int 518 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 519 { 520 uint32_t tcr; 521 522 /* from Linux driver */ 523 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 524 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 525 526 RTW_WRITE(regs, RTW_TCR, tcr); 527 528 RTW_WBW(regs, RTW_CR, RTW_TCR); 529 530 return rtw_chip_reset1(regs, dvname); 531 } 532 533 static int 534 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int force) 535 { 536 struct ieee80211_key keycopy; 537 538 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 539 540 keycopy = *k; 541 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 542 543 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, force); 544 } 545 546 static int 547 rtw_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k) 548 { 549 int keyix; 550 #ifdef RTW_DEBUG 551 struct rtw_softc *sc = ic->ic_ifp->if_softc; 552 #endif 553 554 if (&ic->ic_nw_keys[0] <= k && k < &ic->ic_nw_keys[IEEE80211_WEP_NKID]) 555 keyix = k - ic->ic_nw_keys; 556 else 557 keyix = IEEE80211_KEYIX_NONE; 558 559 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: alloc key %u\n", __func__, keyix)); 560 561 return keyix; 562 } 563 564 static int 565 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 566 { 567 struct rtw_softc *sc = ic->ic_ifp->if_softc; 568 u_int keyix = k->wk_keyix; 569 570 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix)); 571 572 if (keyix >= IEEE80211_WEP_NKID) 573 return 0; 574 if (k->wk_keylen != 0) 575 sc->sc_flags &= ~RTW_F_DK_VALID; 576 577 return 1; 578 } 579 580 static int 581 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 582 const u_int8_t mac[IEEE80211_ADDR_LEN]) 583 { 584 struct rtw_softc *sc = ic->ic_ifp->if_softc; 585 586 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 587 588 if (k->wk_keyix >= IEEE80211_WEP_NKID) 589 return 0; 590 591 if (k->wk_cipher == &ieee80211_cipher_wep) { 592 rtw_cipher_wep = ieee80211_cipher_wep; 593 rtw_cipher_wep.ic_decap = rtw_wep_decap; 594 ic->ic_nw_keys[k->wk_keyix].wk_cipher = &rtw_cipher_wep; 595 } 596 sc->sc_flags &= ~RTW_F_DK_VALID; 597 598 return 1; 599 } 600 601 static void 602 rtw_key_update_begin(struct ieee80211com *ic) 603 { 604 #ifdef RTW_DEBUG 605 struct ifnet *ifp = ic->ic_ifp; 606 struct rtw_softc *sc = ifp->if_softc; 607 #endif 608 609 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 610 } 611 612 static void 613 rtw_key_update_end(struct ieee80211com *ic) 614 { 615 struct ifnet *ifp = ic->ic_ifp; 616 struct rtw_softc *sc = ifp->if_softc; 617 618 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 619 620 if ((sc->sc_flags & RTW_F_DK_VALID) != 0) 621 return; 622 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 623 return; 624 625 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 626 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 627 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 628 (ifp->if_flags & IFF_RUNNING) != 0); 629 } 630 631 static void 632 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 633 { 634 uint8_t cfg0, psr, scr; 635 int i, tx_key_len; 636 struct rtw_regs *regs; 637 union rtw_keys *rk; 638 639 regs = &sc->sc_regs; 640 rk = &sc->sc_keys; 641 642 (void)memset(rk->rk_keys, 0, sizeof(rk->rk_keys)); 643 644 rtw_set_access(regs, RTW_ACCESS_CONFIG); 645 646 psr = RTW_READ8(regs, RTW_PSR); 647 scr = RTW_READ8(regs, RTW_SCR); 648 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 649 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 650 cfg0 &= ~(RTW_CONFIG0_WEP104 | RTW_CONFIG0_WEP40); 651 652 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 653 goto out; 654 655 tx_key_len = wk[txkey].wk_keylen; 656 657 switch (tx_key_len) { 658 case 5: 659 scr |= RTW_SCR_RXSECON | RTW_SCR_KM_WEP40; 660 break; 661 case 13: 662 scr |= RTW_SCR_RXSECON | RTW_SCR_KM_WEP104; 663 break; 664 default: 665 goto out; 666 } 667 668 cfg0 |= RTW_CONFIG0_WEP104 | RTW_CONFIG0_WEP40; 669 670 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 671 if (wk[i].wk_keylen != tx_key_len) 672 continue; 673 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 674 } 675 676 out: 677 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 678 679 bus_space_write_region_4(regs->r_bt, regs->r_bh, 680 RTW_DK0, rk->rk_words, 681 sizeof(rk->rk_words) / sizeof(rk->rk_words[0])); 682 683 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 684 BUS_SPACE_BARRIER_SYNC); 685 686 printf("%s: psr = %#" PRIx8, sc->sc_dev.dv_xname, psr); 687 688 RTW_WRITE8(regs, RTW_PSR, psr); 689 690 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 691 RTW_WBW(regs, RTW_CONFIG0, RTW_SCR); 692 RTW_WRITE8(regs, RTW_SCR, scr); 693 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 694 rtw_set_access(regs, RTW_ACCESS_NONE); 695 sc->sc_flags |= RTW_F_DK_VALID; 696 } 697 698 static __inline int 699 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 700 { 701 int i; 702 uint8_t ecr; 703 704 ecr = RTW_READ8(regs, RTW_9346CR); 705 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 706 RTW_WRITE8(regs, RTW_9346CR, ecr); 707 708 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 709 710 /* wait 25ms for completion */ 711 for (i = 0; i < 250; i++) { 712 ecr = RTW_READ8(regs, RTW_9346CR); 713 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 714 RTW_DPRINTF(RTW_DEBUG_RESET, 715 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 716 return 0; 717 } 718 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 719 DELAY(100); 720 } 721 printf("%s: recall EEPROM failed\n", dvname); 722 return ETIMEDOUT; 723 } 724 725 static __inline int 726 rtw_reset(struct rtw_softc *sc) 727 { 728 int rc; 729 uint8_t config1; 730 731 sc->sc_flags &= ~RTW_F_DK_VALID; 732 733 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 734 return rc; 735 736 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 737 ; 738 739 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 740 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 741 /* TBD turn off maximum power saving? */ 742 743 return 0; 744 } 745 746 static __inline int 747 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 748 u_int ndescs) 749 { 750 int i, rc = 0; 751 for (i = 0; i < ndescs; i++) { 752 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 753 0, 0, &descs[i].ts_dmamap); 754 if (rc != 0) 755 break; 756 } 757 return rc; 758 } 759 760 static __inline int 761 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 762 u_int ndescs) 763 { 764 int i, rc = 0; 765 for (i = 0; i < ndescs; i++) { 766 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 767 &descs[i].rs_dmamap); 768 if (rc != 0) 769 break; 770 } 771 return rc; 772 } 773 774 static __inline void 775 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 776 u_int ndescs) 777 { 778 int i; 779 for (i = 0; i < ndescs; i++) { 780 if (descs[i].rs_dmamap != NULL) 781 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 782 } 783 } 784 785 static __inline void 786 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 787 u_int ndescs) 788 { 789 int i; 790 for (i = 0; i < ndescs; i++) { 791 if (descs[i].ts_dmamap != NULL) 792 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 793 } 794 } 795 796 static __inline void 797 rtw_srom_free(struct rtw_srom *sr) 798 { 799 sr->sr_size = 0; 800 if (sr->sr_content == NULL) 801 return; 802 free(sr->sr_content, M_DEVBUF); 803 sr->sr_content = NULL; 804 } 805 806 static void 807 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 808 enum rtw_rfchipid *rfchipid, uint32_t *rcr) 809 { 810 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 811 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 812 *rcr |= RTW_RCR_ENCS1; 813 *rfchipid = RTW_RFCHIPID_PHILIPS; 814 } 815 816 static int 817 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 818 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 819 const char *dvname) 820 { 821 int i; 822 const char *rfname, *paname; 823 char scratch[sizeof("unknown 0xXX")]; 824 uint16_t srom_version; 825 uint8_t mac[IEEE80211_ADDR_LEN]; 826 827 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 828 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 829 830 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 831 printf("%s: SROM version %d.%d", dvname, 832 srom_version >> 8, srom_version & 0xff); 833 834 if (srom_version <= 0x0101) { 835 printf(" is not understood, limping along with defaults\n"); 836 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 837 return 0; 838 } 839 printf("\n"); 840 841 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 842 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 843 844 RTW_DPRINTF(RTW_DEBUG_ATTACH, 845 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 846 847 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 848 849 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 850 *flags |= RTW_F_ANTDIV; 851 852 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 853 * to be reversed. 854 */ 855 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 856 *flags |= RTW_F_DIGPHY; 857 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 858 *flags |= RTW_F_DFLANTB; 859 860 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 861 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 862 863 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 864 switch (*rfchipid) { 865 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 866 rfname = "GCT GRF5101"; 867 paname = "Winspring WS9901"; 868 break; 869 case RTW_RFCHIPID_MAXIM: 870 rfname = "Maxim MAX2820"; /* guess */ 871 paname = "Maxim MAX2422"; /* guess */ 872 break; 873 case RTW_RFCHIPID_INTERSIL: 874 rfname = "Intersil HFA3873"; /* guess */ 875 paname = "Intersil <unknown>"; 876 break; 877 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 878 rfname = "Philips SA2400A"; 879 paname = "Philips SA2411"; 880 break; 881 case RTW_RFCHIPID_RFMD: 882 /* this is the same front-end as an atw(4)! */ 883 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 884 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 885 "SYN: Silicon Labs Si4126"; /* inferred from 886 * reference driver 887 */ 888 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 889 break; 890 case RTW_RFCHIPID_RESERVED: 891 rfname = paname = "reserved"; 892 break; 893 default: 894 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 895 rfname = paname = scratch; 896 } 897 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 898 899 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 900 case RTW_CONFIG0_GL_USA: 901 case _RTW_CONFIG0_GL_USA: 902 *locale = RTW_LOCALE_USA; 903 break; 904 case RTW_CONFIG0_GL_EUROPE: 905 *locale = RTW_LOCALE_EUROPE; 906 break; 907 case RTW_CONFIG0_GL_JAPAN: 908 *locale = RTW_LOCALE_JAPAN; 909 break; 910 default: 911 *locale = RTW_LOCALE_UNKNOWN; 912 break; 913 } 914 return 0; 915 } 916 917 /* Returns -1 on failure. */ 918 static int 919 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 920 const char *dvname) 921 { 922 int rc; 923 struct seeprom_descriptor sd; 924 uint8_t ecr; 925 926 (void)memset(&sd, 0, sizeof(sd)); 927 928 ecr = RTW_READ8(regs, RTW_9346CR); 929 930 if ((flags & RTW_F_9356SROM) != 0) { 931 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 932 sr->sr_size = 256; 933 sd.sd_chip = C56_66; 934 } else { 935 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 936 sr->sr_size = 128; 937 sd.sd_chip = C46; 938 } 939 940 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 941 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 942 ecr |= RTW_9346CR_EEM_PROGRAM; 943 944 RTW_WRITE8(regs, RTW_9346CR, ecr); 945 946 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 947 948 if (sr->sr_content == NULL) { 949 printf("%s: unable to allocate SROM buffer\n", dvname); 950 return ENOMEM; 951 } 952 953 (void)memset(sr->sr_content, 0, sr->sr_size); 954 955 /* RTL8180 has a single 8-bit register for controlling the 956 * 93cx6 SROM. There is no "ready" bit. The RTL8180 957 * input/output sense is the reverse of read_seeprom's. 958 */ 959 sd.sd_tag = regs->r_bt; 960 sd.sd_bsh = regs->r_bh; 961 sd.sd_regsize = 1; 962 sd.sd_control_offset = RTW_9346CR; 963 sd.sd_status_offset = RTW_9346CR; 964 sd.sd_dataout_offset = RTW_9346CR; 965 sd.sd_CK = RTW_9346CR_EESK; 966 sd.sd_CS = RTW_9346CR_EECS; 967 sd.sd_DI = RTW_9346CR_EEDO; 968 sd.sd_DO = RTW_9346CR_EEDI; 969 /* make read_seeprom enter EEPROM read/write mode */ 970 sd.sd_MS = ecr; 971 sd.sd_RDY = 0; 972 973 /* TBD bus barriers */ 974 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 975 printf("%s: could not read SROM\n", dvname); 976 free(sr->sr_content, M_DEVBUF); 977 sr->sr_content = NULL; 978 return -1; /* XXX */ 979 } 980 981 /* end EEPROM read/write mode */ 982 RTW_WRITE8(regs, RTW_9346CR, 983 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 984 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 985 986 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 987 return rc; 988 989 #ifdef RTW_DEBUG 990 { 991 int i; 992 RTW_DPRINTF(RTW_DEBUG_ATTACH, 993 ("\n%s: serial ROM:\n\t", dvname)); 994 for (i = 0; i < sr->sr_size/2; i++) { 995 if (((i % 8) == 0) && (i != 0)) 996 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 997 RTW_DPRINTF(RTW_DEBUG_ATTACH, 998 (" %04x", sr->sr_content[i])); 999 } 1000 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 1001 } 1002 #endif /* RTW_DEBUG */ 1003 return 0; 1004 } 1005 1006 static void 1007 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 1008 const char *dvname) 1009 { 1010 uint8_t cfg4; 1011 const char *method; 1012 1013 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 1014 1015 switch (rfchipid) { 1016 default: 1017 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 1018 method = "fallback"; 1019 break; 1020 case RTW_RFCHIPID_INTERSIL: 1021 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1022 method = "Intersil"; 1023 break; 1024 case RTW_RFCHIPID_PHILIPS: 1025 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1026 method = "Philips"; 1027 break; 1028 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1029 case RTW_RFCHIPID_RFMD: 1030 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1031 method = "RFMD"; 1032 break; 1033 } 1034 1035 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1036 1037 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1038 1039 RTW_DPRINTF(RTW_DEBUG_INIT, 1040 ("%s: %s RF programming method, %#02x\n", dvname, method, 1041 RTW_READ8(regs, RTW_CONFIG4))); 1042 } 1043 1044 static __inline void 1045 rtw_init_channels(enum rtw_locale locale, 1046 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 1047 const char *dvname) 1048 { 1049 int i; 1050 const char *name = NULL; 1051 #define ADD_CHANNEL(_chans, _chan) do { \ 1052 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1053 (*_chans)[_chan].ic_freq = \ 1054 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1055 } while (0) 1056 1057 switch (locale) { 1058 case RTW_LOCALE_USA: /* 1-11 */ 1059 name = "USA"; 1060 for (i = 1; i <= 11; i++) 1061 ADD_CHANNEL(chans, i); 1062 break; 1063 case RTW_LOCALE_JAPAN: /* 1-14 */ 1064 name = "Japan"; 1065 ADD_CHANNEL(chans, 14); 1066 for (i = 1; i <= 14; i++) 1067 ADD_CHANNEL(chans, i); 1068 break; 1069 case RTW_LOCALE_EUROPE: /* 1-13 */ 1070 name = "Europe"; 1071 for (i = 1; i <= 13; i++) 1072 ADD_CHANNEL(chans, i); 1073 break; 1074 default: /* 10-11 allowed by most countries */ 1075 name = "<unknown>"; 1076 for (i = 10; i <= 11; i++) 1077 ADD_CHANNEL(chans, i); 1078 break; 1079 } 1080 printf("%s: Geographic Location %s\n", dvname, name); 1081 #undef ADD_CHANNEL 1082 } 1083 1084 static __inline void 1085 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 1086 const char *dvname) 1087 { 1088 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1089 1090 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1091 case RTW_CONFIG0_GL_USA: 1092 case _RTW_CONFIG0_GL_USA: 1093 *locale = RTW_LOCALE_USA; 1094 break; 1095 case RTW_CONFIG0_GL_JAPAN: 1096 *locale = RTW_LOCALE_JAPAN; 1097 break; 1098 case RTW_CONFIG0_GL_EUROPE: 1099 *locale = RTW_LOCALE_EUROPE; 1100 break; 1101 default: 1102 *locale = RTW_LOCALE_UNKNOWN; 1103 break; 1104 } 1105 } 1106 1107 static __inline int 1108 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1109 const char *dvname) 1110 { 1111 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1113 }; 1114 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1115 idr1 = RTW_READ(regs, RTW_IDR1); 1116 1117 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 1118 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 1119 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 1120 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 1121 1122 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 1123 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 1124 1125 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1126 printf("%s: could not get mac address, attach failed\n", 1127 dvname); 1128 return ENXIO; 1129 } 1130 1131 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 1132 1133 return 0; 1134 } 1135 1136 static uint8_t 1137 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1138 struct ieee80211_channel *chan) 1139 { 1140 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1141 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 1142 ("%s: channel %d out of range", __func__, 1143 idx - RTW_SR_TXPOWER1 + 1)); 1144 return RTW_SR_GET(sr, idx); 1145 } 1146 1147 static void 1148 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1149 { 1150 int pri; 1151 u_int ndesc[RTW_NTXPRI] = 1152 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 1153 1154 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1155 tdb[pri].tdb_nfree = ndesc[pri]; 1156 tdb[pri].tdb_next = 0; 1157 } 1158 } 1159 1160 static int 1161 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1162 { 1163 int i; 1164 struct rtw_txsoft *ts; 1165 1166 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1167 SIMPLEQ_INIT(&tsb->tsb_freeq); 1168 for (i = 0; i < tsb->tsb_ndesc; i++) { 1169 ts = &tsb->tsb_desc[i]; 1170 ts->ts_mbuf = NULL; 1171 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1172 } 1173 return 0; 1174 } 1175 1176 static void 1177 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1178 { 1179 int pri; 1180 for (pri = 0; pri < RTW_NTXPRI; pri++) 1181 rtw_txsoft_blk_init(&tsb[pri]); 1182 } 1183 1184 static __inline void 1185 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1186 { 1187 KASSERT(nsync <= rdb->rdb_ndesc); 1188 /* sync to end of ring */ 1189 if (desc0 + nsync > rdb->rdb_ndesc) { 1190 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1191 offsetof(struct rtw_descs, hd_rx[desc0]), 1192 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1193 nsync -= (rdb->rdb_ndesc - desc0); 1194 desc0 = 0; 1195 } 1196 1197 KASSERT(desc0 < rdb->rdb_ndesc); 1198 KASSERT(nsync <= rdb->rdb_ndesc); 1199 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1200 1201 /* sync what remains */ 1202 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1203 offsetof(struct rtw_descs, hd_rx[desc0]), 1204 sizeof(struct rtw_rxdesc) * nsync, ops); 1205 } 1206 1207 static void 1208 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1209 { 1210 /* sync to end of ring */ 1211 if (desc0 + nsync > tdb->tdb_ndesc) { 1212 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1213 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1214 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1215 ops); 1216 nsync -= (tdb->tdb_ndesc - desc0); 1217 desc0 = 0; 1218 } 1219 1220 /* sync what remains */ 1221 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1222 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1223 sizeof(struct rtw_txdesc) * nsync, ops); 1224 } 1225 1226 static void 1227 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1228 { 1229 int pri; 1230 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1231 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1232 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1233 } 1234 } 1235 1236 static void 1237 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1238 { 1239 int i; 1240 struct rtw_rxsoft *rs; 1241 1242 for (i = 0; i < RTW_RXQLEN; i++) { 1243 rs = &desc[i]; 1244 if (rs->rs_mbuf == NULL) 1245 continue; 1246 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1247 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1248 bus_dmamap_unload(dmat, rs->rs_dmamap); 1249 m_freem(rs->rs_mbuf); 1250 rs->rs_mbuf = NULL; 1251 } 1252 } 1253 1254 static __inline int 1255 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1256 { 1257 int rc; 1258 struct mbuf *m; 1259 1260 MGETHDR(m, M_DONTWAIT, MT_DATA); 1261 if (m == NULL) 1262 return ENOBUFS; 1263 1264 MCLGET(m, M_DONTWAIT); 1265 if ((m->m_flags & M_EXT) == 0) { 1266 m_freem(m); 1267 return ENOBUFS; 1268 } 1269 1270 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1271 1272 if (rs->rs_mbuf != NULL) 1273 bus_dmamap_unload(dmat, rs->rs_dmamap); 1274 1275 rs->rs_mbuf = NULL; 1276 1277 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1278 if (rc != 0) { 1279 m_freem(m); 1280 return -1; 1281 } 1282 1283 rs->rs_mbuf = m; 1284 1285 return 0; 1286 } 1287 1288 static int 1289 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1290 int *ndesc, const char *dvname) 1291 { 1292 int i, rc = 0; 1293 struct rtw_rxsoft *rs; 1294 1295 for (i = 0; i < RTW_RXQLEN; i++) { 1296 rs = &desc[i]; 1297 /* we're in rtw_init, so there should be no mbufs allocated */ 1298 KASSERT(rs->rs_mbuf == NULL); 1299 #ifdef RTW_DEBUG 1300 if (i == rtw_rxbufs_limit) { 1301 printf("%s: TEST hit %d-buffer limit\n", dvname, i); 1302 rc = ENOBUFS; 1303 break; 1304 } 1305 #endif /* RTW_DEBUG */ 1306 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1307 printf("%s: rtw_rxsoft_alloc failed, %d buffers, " 1308 "rc %d\n", dvname, i, rc); 1309 break; 1310 } 1311 } 1312 *ndesc = i; 1313 return rc; 1314 } 1315 1316 static __inline void 1317 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1318 int idx, int kick) 1319 { 1320 int is_last = (idx == rdb->rdb_ndesc - 1); 1321 uint32_t ctl, octl, obuf; 1322 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1323 1324 obuf = rd->rd_buf; 1325 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1326 1327 ctl = LSHIFT(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1328 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1329 1330 if (is_last) 1331 ctl |= RTW_RXCTL_EOR; 1332 1333 octl = rd->rd_ctl; 1334 rd->rd_ctl = htole32(ctl); 1335 1336 RTW_DPRINTF( 1337 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1338 : RTW_DEBUG_RECV_DESC, 1339 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1340 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1341 le32toh(rd->rd_ctl))); 1342 1343 /* sync the mbuf */ 1344 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1345 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1346 1347 /* sync the descriptor */ 1348 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1349 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1350 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1351 } 1352 1353 static void 1354 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1355 { 1356 int i; 1357 struct rtw_rxdesc *rd; 1358 struct rtw_rxsoft *rs; 1359 1360 for (i = 0; i < rdb->rdb_ndesc; i++) { 1361 rd = &rdb->rdb_desc[i]; 1362 rs = &ctl[i]; 1363 rtw_rxdesc_init(rdb, rs, i, kick); 1364 } 1365 rdb->rdb_next = 0; 1366 } 1367 1368 static void 1369 rtw_io_enable(struct rtw_regs *regs, uint8_t flags, int enable) 1370 { 1371 uint8_t cr; 1372 1373 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1374 enable ? "enable" : "disable", flags)); 1375 1376 cr = RTW_READ8(regs, RTW_CR); 1377 1378 /* XXX reference source does not enable MULRW */ 1379 #if 0 1380 /* enable PCI Read/Write Multiple */ 1381 cr |= RTW_CR_MULRW; 1382 #endif 1383 1384 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1385 if (enable) 1386 cr |= flags; 1387 else 1388 cr &= ~flags; 1389 RTW_WRITE8(regs, RTW_CR, cr); 1390 RTW_SYNC(regs, RTW_CR, RTW_CR); 1391 } 1392 1393 static void 1394 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1395 { 1396 #define IS_BEACON(__fc0) \ 1397 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1398 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1399 1400 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1401 * hardware -> net80211 1402 */ 1403 u_int next, nproc = 0; 1404 int hwrate, len, rate, rssi, sq; 1405 uint32_t hrssi, hstat, htsfth, htsftl; 1406 struct rtw_rxdesc *rd; 1407 struct rtw_rxsoft *rs; 1408 struct rtw_rxdesc_blk *rdb; 1409 struct mbuf *m; 1410 struct ifnet *ifp = &sc->sc_if; 1411 1412 struct ieee80211_node *ni; 1413 struct ieee80211_frame_min *wh; 1414 1415 rdb = &sc->sc_rxdesc_blk; 1416 1417 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1418 1419 for (next = rdb->rdb_next; ; next = (next + 1) % rdb->rdb_ndesc) { 1420 rtw_rxdescs_sync(rdb, next, 1, 1421 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1422 rd = &rdb->rdb_desc[next]; 1423 rs = &sc->sc_rxsoft[next]; 1424 1425 hstat = le32toh(rd->rd_stat); 1426 hrssi = le32toh(rd->rd_rssi); 1427 htsfth = le32toh(rd->rd_tsfth); 1428 htsftl = le32toh(rd->rd_tsftl); 1429 1430 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1431 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1432 __func__, next, hstat, hrssi, htsfth, htsftl)); 1433 1434 ++nproc; 1435 1436 /* still belongs to NIC */ 1437 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1438 if (nproc > 1) 1439 break; 1440 1441 /* sometimes the NIC skips to the 0th descriptor */ 1442 rtw_rxdescs_sync(rdb, 0, 1, 1443 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1444 rd = &rdb->rdb_desc[0]; 1445 if ((rd->rd_stat & htole32(RTW_RXSTAT_OWN)) != 0) 1446 break; 1447 RTW_DPRINTF(RTW_DEBUG_BUGS, 1448 ("%s: NIC skipped from rxdesc[%u] to rxdesc[0]\n", 1449 sc->sc_dev.dv_xname, next)); 1450 next = rdb->rdb_ndesc - 1; 1451 continue; 1452 } 1453 1454 #ifdef RTW_DEBUG 1455 #define PRINTSTAT(flag) do { \ 1456 if ((hstat & flag) != 0) { \ 1457 printf("%s" #flag, delim); \ 1458 delim = ","; \ 1459 } \ 1460 } while (0) 1461 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1462 const char *delim = "<"; 1463 printf("%s: ", sc->sc_dev.dv_xname); 1464 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1465 printf("status %08x", hstat); 1466 PRINTSTAT(RTW_RXSTAT_SPLCP); 1467 PRINTSTAT(RTW_RXSTAT_MAR); 1468 PRINTSTAT(RTW_RXSTAT_PAR); 1469 PRINTSTAT(RTW_RXSTAT_BAR); 1470 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1471 PRINTSTAT(RTW_RXSTAT_CRC32); 1472 PRINTSTAT(RTW_RXSTAT_ICV); 1473 printf(">, "); 1474 } 1475 } 1476 #endif /* RTW_DEBUG */ 1477 1478 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1479 printf("%s: DMA error/FIFO overflow %08x, " 1480 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1481 hstat & RTW_RXSTAT_IOERROR, next); 1482 ifp->if_ierrors++; 1483 goto next; 1484 } 1485 1486 len = MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1487 if (len < IEEE80211_MIN_LEN) { 1488 sc->sc_ic.ic_stats.is_rx_tooshort++; 1489 goto next; 1490 } 1491 1492 /* CRC is included with the packet; trim it off. */ 1493 len -= IEEE80211_CRC_LEN; 1494 1495 hwrate = MASK_AND_RSHIFT(hstat, RTW_RXSTAT_RATE_MASK); 1496 if (hwrate >= sizeof(ratetbl) / sizeof(ratetbl[0])) { 1497 printf("%s: unknown rate #%d\n", sc->sc_dev.dv_xname, 1498 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_RATE_MASK)); 1499 ifp->if_ierrors++; 1500 goto next; 1501 } 1502 rate = ratetbl[hwrate]; 1503 1504 #ifdef RTW_DEBUG 1505 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1506 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1507 (rate * 5) % 10, htsfth, htsftl)); 1508 #endif /* RTW_DEBUG */ 1509 1510 if ((hstat & RTW_RXSTAT_RES) != 0 && 1511 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1512 goto next; 1513 1514 /* if bad flags, skip descriptor */ 1515 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1516 printf("%s: too many rx segments\n", 1517 sc->sc_dev.dv_xname); 1518 goto next; 1519 } 1520 1521 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1522 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1523 1524 m = rs->rs_mbuf; 1525 1526 /* if temporarily out of memory, re-use mbuf */ 1527 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1528 case 0: 1529 break; 1530 case ENOBUFS: 1531 printf("%s: rtw_rxsoft_alloc(, %d) failed, " 1532 "dropping packet\n", sc->sc_dev.dv_xname, next); 1533 goto next; 1534 default: 1535 /* XXX shorten rx ring, instead? */ 1536 panic("%s: could not load DMA map\n", 1537 sc->sc_dev.dv_xname); 1538 } 1539 1540 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1541 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1542 else { 1543 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1544 /* TBD find out each front-end's LNA gain in the 1545 * front-end's units 1546 */ 1547 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1548 rssi |= 0x80; 1549 } 1550 sq = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_SQ); 1551 1552 /* Note well: now we cannot recycle the rs_mbuf unless 1553 * we restore its original length. 1554 */ 1555 m->m_pkthdr.rcvif = ifp; 1556 m->m_pkthdr.len = m->m_len = len; 1557 1558 wh = mtod(m, struct ieee80211_frame_min *); 1559 1560 if (!IS_BEACON(wh->i_fc[0])) 1561 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1562 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1563 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1564 1565 sc->sc_tsfth = htsfth; 1566 1567 #ifdef RTW_DEBUG 1568 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 1569 (IFF_DEBUG|IFF_LINK2)) { 1570 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1571 rate, rssi); 1572 } 1573 #endif /* RTW_DEBUG */ 1574 1575 #if NBPFILTER > 0 1576 if (sc->sc_radiobpf != NULL) { 1577 struct ieee80211com *ic = &sc->sc_ic; 1578 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1579 1580 rr->rr_tsft = 1581 htole64(((uint64_t)htsfth << 32) | htsftl); 1582 1583 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1584 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE; 1585 1586 rr->rr_flags = 0; 1587 rr->rr_rate = rate; 1588 rr->rr_chan_freq = 1589 htole16(ic->ic_bss->ni_chan->ic_freq); 1590 rr->rr_chan_flags = 1591 htole16(ic->ic_bss->ni_chan->ic_flags); 1592 rr->rr_antsignal = rssi; 1593 rr->rr_barker_lock = htole16(sq); 1594 1595 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rr, 1596 sizeof(sc->sc_rxtapu), m); 1597 } 1598 #endif /* NPBFILTER > 0 */ 1599 1600 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1601 ieee80211_free_node(ni); 1602 next: 1603 rtw_rxdesc_init(rdb, rs, next, 0); 1604 } 1605 rdb->rdb_next = next; 1606 1607 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1608 1609 return; 1610 #undef IS_BEACON 1611 } 1612 1613 static void 1614 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1615 struct rtw_txsoft *ts) 1616 { 1617 struct mbuf *m; 1618 struct ieee80211_node *ni; 1619 1620 m = ts->ts_mbuf; 1621 ni = ts->ts_ni; 1622 KASSERT(m != NULL); 1623 KASSERT(ni != NULL); 1624 ts->ts_mbuf = NULL; 1625 ts->ts_ni = NULL; 1626 1627 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1628 BUS_DMASYNC_POSTWRITE); 1629 bus_dmamap_unload(dmat, ts->ts_dmamap); 1630 m_freem(m); 1631 ieee80211_free_node(ni); 1632 } 1633 1634 static void 1635 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1636 struct rtw_txsoft_blk *tsb) 1637 { 1638 struct rtw_txsoft *ts; 1639 1640 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1641 rtw_txsoft_release(dmat, ic, ts); 1642 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1643 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1644 } 1645 } 1646 1647 static __inline void 1648 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1649 struct rtw_txsoft *ts, int ndesc) 1650 { 1651 uint32_t hstat; 1652 int data_retry, rts_retry; 1653 struct rtw_txdesc *tdn; 1654 const char *condstring; 1655 struct ifnet *ifp = &sc->sc_if; 1656 1657 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1658 1659 tdb->tdb_nfree += ndesc; 1660 1661 tdn = &tdb->tdb_desc[ts->ts_last]; 1662 1663 hstat = le32toh(tdn->td_stat); 1664 rts_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1665 data_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_DRC_MASK); 1666 1667 ifp->if_collisions += rts_retry + data_retry; 1668 1669 if ((hstat & RTW_TXSTAT_TOK) != 0) 1670 condstring = "ok"; 1671 else { 1672 ifp->if_oerrors++; 1673 condstring = "error"; 1674 } 1675 1676 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1677 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1678 sc->sc_dev.dv_xname, ts, ts->ts_first, ts->ts_last, 1679 condstring, rts_retry, data_retry)); 1680 } 1681 1682 /* Collect transmitted packets. */ 1683 static __inline void 1684 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1685 struct rtw_txdesc_blk *tdb) 1686 { 1687 int ndesc; 1688 struct rtw_txsoft *ts; 1689 struct ifnet *ifp = &sc->sc_if; 1690 1691 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1692 ndesc = 1 + ts->ts_last - ts->ts_first; 1693 if (ts->ts_last < ts->ts_first) 1694 ndesc += tdb->tdb_ndesc; 1695 1696 KASSERT(ndesc > 0); 1697 1698 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1699 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1700 1701 if ((tdb->tdb_desc[ts->ts_last].td_stat & 1702 htole32(RTW_TXSTAT_OWN)) != 0) 1703 break; 1704 1705 if (&sc->sc_txdesc_blk[RTW_TXPRIBCN] == tdb) { 1706 RTW_DPRINTF(RTW_DEBUG_BEACON, 1707 ("%s: collected beacon\n", __func__)); 1708 } 1709 1710 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1711 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1712 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1713 ifp->if_flags &= ~IFF_OACTIVE; 1714 } 1715 if (ts == NULL) 1716 tsb->tsb_tx_timer = 0; 1717 } 1718 1719 static void 1720 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1721 { 1722 int pri; 1723 struct rtw_txsoft_blk *tsb; 1724 struct rtw_txdesc_blk *tdb; 1725 struct ifnet *ifp = &sc->sc_if; 1726 1727 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1728 tsb = &sc->sc_txsoft_blk[pri]; 1729 tdb = &sc->sc_txdesc_blk[pri]; 1730 1731 rtw_collect_txring(sc, tsb, tdb); 1732 1733 if ((isr & RTW_INTR_TX) != 0) 1734 rtw_start(ifp); 1735 } 1736 1737 /* TBD */ 1738 return; 1739 } 1740 1741 static void 1742 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1743 { 1744 /* TBD */ 1745 return; 1746 } 1747 1748 static void 1749 rtw_intr_atim(struct rtw_softc *sc) 1750 { 1751 /* TBD */ 1752 return; 1753 } 1754 1755 #ifdef RTW_DEBUG 1756 static void 1757 rtw_dump_rings(struct rtw_softc *sc) 1758 { 1759 struct rtw_txdesc_blk *tdb; 1760 struct rtw_rxdesc *rd; 1761 struct rtw_rxdesc_blk *rdb; 1762 int desc, pri; 1763 1764 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1765 return; 1766 1767 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1768 tdb = &sc->sc_txdesc_blk[pri]; 1769 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1770 tdb->tdb_ndesc, tdb->tdb_nfree); 1771 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1772 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1773 } 1774 1775 rdb = &sc->sc_rxdesc_blk; 1776 1777 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1778 rd = &rdb->rdb_desc[desc]; 1779 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1780 "rsvd1/tsfth %08x\n", __func__, 1781 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1782 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1783 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1784 } 1785 } 1786 #endif /* RTW_DEBUG */ 1787 1788 static void 1789 rtw_hwring_setup(struct rtw_softc *sc) 1790 { 1791 struct rtw_regs *regs = &sc->sc_regs; 1792 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1793 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1794 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1795 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1796 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1797 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1798 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1799 ("%s: reg[TLPDA] <- %" PRIxPTR "\n", __func__, 1800 (uintptr_t)RTW_RING_BASE(sc, hd_txlo))); 1801 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1802 ("%s: reg[TNPDA] <- %" PRIxPTR "\n", __func__, 1803 (uintptr_t)RTW_RING_BASE(sc, hd_txmd))); 1804 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1805 ("%s: reg[THPDA] <- %" PRIxPTR "\n", __func__, 1806 (uintptr_t)RTW_RING_BASE(sc, hd_txhi))); 1807 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1808 ("%s: reg[TBDA] <- %" PRIxPTR "\n", __func__, 1809 (uintptr_t)RTW_RING_BASE(sc, hd_bcn))); 1810 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1811 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1812 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1813 } 1814 1815 static int 1816 rtw_swring_setup(struct rtw_softc *sc) 1817 { 1818 int rc; 1819 struct rtw_rxdesc_blk *rdb; 1820 1821 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1822 1823 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1824 1825 rdb = &sc->sc_rxdesc_blk; 1826 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1827 sc->sc_dev.dv_xname)) != 0 && rdb->rdb_ndesc == 0) { 1828 printf("%s: could not allocate rx buffers\n", 1829 sc->sc_dev.dv_xname); 1830 return rc; 1831 } 1832 1833 rdb = &sc->sc_rxdesc_blk; 1834 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1835 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1836 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1837 1838 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1839 return 0; 1840 } 1841 1842 static void 1843 rtw_txdesc_blk_reset(struct rtw_txdesc_blk *tdb) 1844 { 1845 int i; 1846 1847 (void)memset(tdb->tdb_desc, 0, 1848 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 1849 for (i = 0; i < tdb->tdb_ndesc; i++) 1850 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 1851 tdb->tdb_nfree = tdb->tdb_ndesc; 1852 tdb->tdb_next = 0; 1853 } 1854 1855 static void 1856 rtw_txdescs_reset(struct rtw_softc *sc) 1857 { 1858 int pri; 1859 struct rtw_txdesc_blk *tdb; 1860 1861 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1862 tdb = &sc->sc_txdesc_blk[pri]; 1863 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 1864 &sc->sc_txsoft_blk[pri]); 1865 rtw_txdesc_blk_reset(tdb); 1866 rtw_txdescs_sync(tdb, 0, tdb->tdb_ndesc, 1867 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1868 } 1869 } 1870 1871 static void 1872 rtw_rxdescs_reset(struct rtw_softc *sc) 1873 { 1874 rtw_rxdesc_init_all(&sc->sc_rxdesc_blk, &sc->sc_rxsoft[0], 1); 1875 } 1876 1877 static void 1878 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 1879 { 1880 struct ifnet *ifp = &sc->sc_if; 1881 struct rtw_regs *regs = &sc->sc_regs; 1882 1883 if ((isr & RTW_INTR_TXFOVW) != 0) 1884 printf("%s: tx fifo overflow\n", sc->sc_dev.dv_xname); 1885 1886 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) == 0) 1887 return; 1888 1889 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: restarting xmit/recv, isr %" PRIx16 1890 "\n", sc->sc_dev.dv_xname, isr)); 1891 1892 #ifdef RTW_DEBUG 1893 rtw_dump_rings(sc); 1894 #endif /* RTW_DEBUG */ 1895 1896 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1897 1898 /* Collect rx'd packets. Refresh rx buffers. */ 1899 rtw_intr_rx(sc, 0); 1900 /* Collect tx'd packets. */ 1901 rtw_intr_tx(sc, 0); 1902 1903 RTW_WRITE16(regs, RTW_IMR, 0); 1904 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1905 1906 rtw_chip_reset1(regs, sc->sc_dev.dv_xname); 1907 rtw_wep_setkeys(sc, sc->sc_ic.ic_nw_keys, sc->sc_ic.ic_def_txkey); 1908 1909 rtw_rxdescs_reset(sc); 1910 rtw_txdescs_reset(sc); 1911 1912 rtw_hwring_setup(sc); 1913 1914 #ifdef RTW_DEBUG 1915 rtw_dump_rings(sc); 1916 #endif /* RTW_DEBUG */ 1917 1918 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1919 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1920 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1921 ifp->if_flags &= ~IFF_OACTIVE; 1922 } 1923 1924 static __inline void 1925 rtw_suspend_ticks(struct rtw_softc *sc) 1926 { 1927 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1928 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 1929 sc->sc_do_tick = 0; 1930 } 1931 1932 static __inline void 1933 rtw_resume_ticks(struct rtw_softc *sc) 1934 { 1935 uint32_t tsftrl0, tsftrl1, next_tick; 1936 1937 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1938 1939 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1940 next_tick = tsftrl1 + 1000000; 1941 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1942 1943 sc->sc_do_tick = 1; 1944 1945 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1946 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1947 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 1948 } 1949 1950 static void 1951 rtw_intr_timeout(struct rtw_softc *sc) 1952 { 1953 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 1954 if (sc->sc_do_tick) 1955 rtw_resume_ticks(sc); 1956 return; 1957 } 1958 1959 int 1960 rtw_intr(void *arg) 1961 { 1962 int i; 1963 struct rtw_softc *sc = arg; 1964 struct rtw_regs *regs = &sc->sc_regs; 1965 uint16_t isr; 1966 struct ifnet *ifp = &sc->sc_if; 1967 1968 /* 1969 * If the interface isn't running, the interrupt couldn't 1970 * possibly have come from us. 1971 */ 1972 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1973 (ifp->if_flags & IFF_RUNNING) == 0 || 1974 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1975 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1976 return (0); 1977 } 1978 1979 for (i = 0; i < 10; i++) { 1980 isr = RTW_READ16(regs, RTW_ISR); 1981 1982 RTW_WRITE16(regs, RTW_ISR, isr); 1983 RTW_WBR(regs, RTW_ISR, RTW_ISR); 1984 1985 if (sc->sc_intr_ack != NULL) 1986 (*sc->sc_intr_ack)(regs); 1987 1988 if (isr == 0) 1989 break; 1990 1991 #ifdef RTW_DEBUG 1992 #define PRINTINTR(flag) do { \ 1993 if ((isr & flag) != 0) { \ 1994 printf("%s" #flag, delim); \ 1995 delim = ","; \ 1996 } \ 1997 } while (0) 1998 1999 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 2000 const char *delim = "<"; 2001 2002 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 2003 2004 PRINTINTR(RTW_INTR_TXFOVW); 2005 PRINTINTR(RTW_INTR_TIMEOUT); 2006 PRINTINTR(RTW_INTR_BCNINT); 2007 PRINTINTR(RTW_INTR_ATIMINT); 2008 PRINTINTR(RTW_INTR_TBDER); 2009 PRINTINTR(RTW_INTR_TBDOK); 2010 PRINTINTR(RTW_INTR_THPDER); 2011 PRINTINTR(RTW_INTR_THPDOK); 2012 PRINTINTR(RTW_INTR_TNPDER); 2013 PRINTINTR(RTW_INTR_TNPDOK); 2014 PRINTINTR(RTW_INTR_RXFOVW); 2015 PRINTINTR(RTW_INTR_RDU); 2016 PRINTINTR(RTW_INTR_TLPDER); 2017 PRINTINTR(RTW_INTR_TLPDOK); 2018 PRINTINTR(RTW_INTR_RER); 2019 PRINTINTR(RTW_INTR_ROK); 2020 2021 printf(">\n"); 2022 } 2023 #undef PRINTINTR 2024 #endif /* RTW_DEBUG */ 2025 2026 if ((isr & RTW_INTR_RX) != 0) 2027 rtw_intr_rx(sc, isr & RTW_INTR_RX); 2028 if ((isr & RTW_INTR_TX) != 0) 2029 rtw_intr_tx(sc, isr & RTW_INTR_TX); 2030 if ((isr & RTW_INTR_BEACON) != 0) 2031 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 2032 if ((isr & RTW_INTR_ATIMINT) != 0) 2033 rtw_intr_atim(sc); 2034 if ((isr & RTW_INTR_IOERROR) != 0) 2035 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 2036 if ((isr & RTW_INTR_TIMEOUT) != 0) 2037 rtw_intr_timeout(sc); 2038 } 2039 2040 return 1; 2041 } 2042 2043 /* Must be called at splnet. */ 2044 static void 2045 rtw_stop(struct ifnet *ifp, int disable) 2046 { 2047 int pri; 2048 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2049 struct ieee80211com *ic = &sc->sc_ic; 2050 struct rtw_regs *regs = &sc->sc_regs; 2051 2052 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2053 return; 2054 2055 rtw_suspend_ticks(sc); 2056 2057 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2058 2059 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 2060 /* Disable interrupts. */ 2061 RTW_WRITE16(regs, RTW_IMR, 0); 2062 2063 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2064 2065 /* Stop the transmit and receive processes. First stop DMA, 2066 * then disable receiver and transmitter. 2067 */ 2068 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2069 2070 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2071 2072 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 2073 } 2074 2075 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2076 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2077 &sc->sc_txsoft_blk[pri]); 2078 } 2079 2080 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2081 2082 if (disable) 2083 rtw_disable(sc); 2084 2085 /* Mark the interface as not running. Cancel the watchdog timer. */ 2086 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2087 ifp->if_timer = 0; 2088 2089 return; 2090 } 2091 2092 const char * 2093 rtw_pwrstate_string(enum rtw_pwrstate power) 2094 { 2095 switch (power) { 2096 case RTW_ON: 2097 return "on"; 2098 case RTW_SLEEP: 2099 return "sleep"; 2100 case RTW_OFF: 2101 return "off"; 2102 default: 2103 return "unknown"; 2104 } 2105 } 2106 2107 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2108 * reference driver, plus a magic Maxim "ON" value that comes from 2109 * the Realtek document "Windows PG for Rtl8180." 2110 */ 2111 static void 2112 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2113 int before_rf, int digphy) 2114 { 2115 uint32_t anaparm; 2116 2117 anaparm = RTW_READ(regs, RTW_ANAPARM); 2118 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2119 2120 switch (power) { 2121 case RTW_OFF: 2122 if (before_rf) 2123 return; 2124 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2125 anaparm |= RTW_ANAPARM_TXDACOFF; 2126 break; 2127 case RTW_SLEEP: 2128 if (!before_rf) 2129 return; 2130 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2131 anaparm |= RTW_ANAPARM_TXDACOFF; 2132 break; 2133 case RTW_ON: 2134 if (!before_rf) 2135 return; 2136 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2137 break; 2138 } 2139 RTW_DPRINTF(RTW_DEBUG_PWR, 2140 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2141 __func__, rtw_pwrstate_string(power), 2142 (before_rf) ? "before" : "after", anaparm)); 2143 2144 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2145 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2146 } 2147 2148 /* XXX I am using the RFMD settings gleaned from the reference 2149 * driver. They agree 2150 */ 2151 static void 2152 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2153 int before_rf, int digphy) 2154 { 2155 uint32_t anaparm; 2156 2157 anaparm = RTW_READ(regs, RTW_ANAPARM); 2158 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2159 2160 switch (power) { 2161 case RTW_OFF: 2162 if (before_rf) 2163 return; 2164 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2165 anaparm |= RTW_ANAPARM_TXDACOFF; 2166 break; 2167 case RTW_SLEEP: 2168 if (!before_rf) 2169 return; 2170 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2171 anaparm |= RTW_ANAPARM_TXDACOFF; 2172 break; 2173 case RTW_ON: 2174 if (!before_rf) 2175 return; 2176 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2177 break; 2178 } 2179 RTW_DPRINTF(RTW_DEBUG_PWR, 2180 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2181 __func__, rtw_pwrstate_string(power), 2182 (before_rf) ? "before" : "after", anaparm)); 2183 2184 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2185 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2186 } 2187 2188 static void 2189 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2190 int before_rf, int digphy) 2191 { 2192 uint32_t anaparm; 2193 2194 anaparm = RTW_READ(regs, RTW_ANAPARM); 2195 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2196 2197 switch (power) { 2198 case RTW_OFF: 2199 if (before_rf) 2200 return; 2201 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2202 anaparm |= RTW_ANAPARM_TXDACOFF; 2203 break; 2204 case RTW_SLEEP: 2205 if (!before_rf) 2206 return; 2207 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2208 anaparm |= RTW_ANAPARM_TXDACOFF; 2209 break; 2210 case RTW_ON: 2211 if (!before_rf) 2212 return; 2213 if (digphy) { 2214 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2215 /* XXX guess */ 2216 anaparm |= RTW_ANAPARM_TXDACOFF; 2217 } else 2218 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2219 break; 2220 } 2221 RTW_DPRINTF(RTW_DEBUG_PWR, 2222 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2223 __func__, rtw_pwrstate_string(power), 2224 (before_rf) ? "before" : "after", anaparm)); 2225 2226 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2227 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2228 } 2229 2230 static void 2231 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2232 int digphy) 2233 { 2234 struct rtw_regs *regs = &sc->sc_regs; 2235 2236 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2237 2238 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2239 2240 rtw_set_access(regs, RTW_ACCESS_NONE); 2241 2242 return; 2243 } 2244 2245 static int 2246 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2247 { 2248 int rc; 2249 2250 RTW_DPRINTF(RTW_DEBUG_PWR, 2251 ("%s: %s->%s\n", __func__, 2252 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2253 2254 if (sc->sc_pwrstate == power) 2255 return 0; 2256 2257 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2258 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2259 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2260 2261 switch (power) { 2262 case RTW_ON: 2263 /* TBD set LEDs */ 2264 break; 2265 case RTW_SLEEP: 2266 /* TBD */ 2267 break; 2268 case RTW_OFF: 2269 /* TBD */ 2270 break; 2271 } 2272 if (rc == 0) 2273 sc->sc_pwrstate = power; 2274 else 2275 sc->sc_pwrstate = RTW_OFF; 2276 return rc; 2277 } 2278 2279 static int 2280 rtw_tune(struct rtw_softc *sc) 2281 { 2282 struct ieee80211com *ic = &sc->sc_ic; 2283 u_int chan; 2284 int rc; 2285 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2286 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2287 2288 KASSERT(ic->ic_bss->ni_chan != NULL); 2289 2290 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2291 if (chan == IEEE80211_CHAN_ANY) 2292 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 2293 2294 if (chan == sc->sc_cur_chan) { 2295 RTW_DPRINTF(RTW_DEBUG_TUNE, 2296 ("%s: already tuned chan #%d\n", __func__, chan)); 2297 return 0; 2298 } 2299 2300 rtw_suspend_ticks(sc); 2301 2302 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 2303 2304 /* TBD wait for Tx to complete */ 2305 2306 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2307 2308 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2309 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 2310 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 2311 dflantb, RTW_ON)) != 0) { 2312 /* XXX condition on powersaving */ 2313 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2314 } 2315 2316 sc->sc_cur_chan = chan; 2317 2318 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 2319 2320 rtw_resume_ticks(sc); 2321 2322 return rc; 2323 } 2324 2325 void 2326 rtw_disable(struct rtw_softc *sc) 2327 { 2328 int rc; 2329 2330 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2331 return; 2332 2333 /* turn off PHY */ 2334 if ((sc->sc_flags & RTW_F_INVALID) == 0 && 2335 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2336 printf("%s: failed to turn off PHY (%d)\n", 2337 sc->sc_dev.dv_xname, rc); 2338 } 2339 2340 if (sc->sc_disable != NULL) 2341 (*sc->sc_disable)(sc); 2342 2343 sc->sc_flags &= ~RTW_F_ENABLED; 2344 } 2345 2346 int 2347 rtw_enable(struct rtw_softc *sc) 2348 { 2349 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2350 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2351 printf("%s: device enable failed\n", 2352 sc->sc_dev.dv_xname); 2353 return (EIO); 2354 } 2355 sc->sc_flags |= RTW_F_ENABLED; 2356 } 2357 return (0); 2358 } 2359 2360 static void 2361 rtw_transmit_config(struct rtw_regs *regs) 2362 { 2363 uint32_t tcr; 2364 2365 tcr = RTW_READ(regs, RTW_TCR); 2366 2367 tcr |= RTW_TCR_CWMIN; 2368 tcr &= ~RTW_TCR_MXDMA_MASK; 2369 tcr |= RTW_TCR_MXDMA_256; 2370 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2371 tcr &= ~RTW_TCR_LBK_MASK; 2372 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2373 2374 /* set short/long retry limits */ 2375 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2376 tcr |= LSHIFT(4, RTW_TCR_SRL_MASK) | LSHIFT(4, RTW_TCR_LRL_MASK); 2377 2378 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2379 2380 RTW_WRITE(regs, RTW_TCR, tcr); 2381 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2382 } 2383 2384 static __inline void 2385 rtw_enable_interrupts(struct rtw_softc *sc) 2386 { 2387 struct rtw_regs *regs = &sc->sc_regs; 2388 2389 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2390 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2391 2392 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2393 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2394 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2395 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2396 2397 /* XXX necessary? */ 2398 if (sc->sc_intr_ack != NULL) 2399 (*sc->sc_intr_ack)(regs); 2400 } 2401 2402 static void 2403 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2404 { 2405 uint8_t msr; 2406 2407 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2408 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2409 2410 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2411 2412 switch (opmode) { 2413 case IEEE80211_M_AHDEMO: 2414 case IEEE80211_M_IBSS: 2415 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2416 break; 2417 case IEEE80211_M_HOSTAP: 2418 msr |= RTW_MSR_NETYPE_AP_OK; 2419 break; 2420 case IEEE80211_M_MONITOR: 2421 /* XXX */ 2422 msr |= RTW_MSR_NETYPE_NOLINK; 2423 break; 2424 case IEEE80211_M_STA: 2425 msr |= RTW_MSR_NETYPE_INFRA_OK; 2426 break; 2427 } 2428 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2429 2430 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2431 } 2432 2433 #define rtw_calchash(addr) \ 2434 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2435 2436 static void 2437 rtw_pktfilt_load(struct rtw_softc *sc) 2438 { 2439 struct rtw_regs *regs = &sc->sc_regs; 2440 struct ieee80211com *ic = &sc->sc_ic; 2441 struct ethercom *ec = &sc->sc_ec; 2442 struct ifnet *ifp = &sc->sc_if; 2443 int hash; 2444 uint32_t hashes[2] = { 0, 0 }; 2445 struct ether_multi *enm; 2446 struct ether_multistep step; 2447 2448 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2449 2450 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2451 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2452 2453 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2454 /* MAC auto-reset PHY (huh?) */ 2455 sc->sc_rcr |= RTW_RCR_ENMARP; 2456 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2457 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2458 2459 switch (ic->ic_opmode) { 2460 case IEEE80211_M_MONITOR: 2461 sc->sc_rcr |= RTW_RCR_MONITOR; 2462 break; 2463 case IEEE80211_M_AHDEMO: 2464 case IEEE80211_M_IBSS: 2465 /* receive broadcasts in our BSS */ 2466 sc->sc_rcr |= RTW_RCR_ADD3; 2467 break; 2468 default: 2469 break; 2470 } 2471 2472 ifp->if_flags &= ~IFF_ALLMULTI; 2473 2474 /* XXX accept all broadcast if scanning */ 2475 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2476 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2477 2478 if (ifp->if_flags & IFF_PROMISC) { 2479 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2480 allmulti: 2481 ifp->if_flags |= IFF_ALLMULTI; 2482 goto setit; 2483 } 2484 2485 /* 2486 * Program the 64-bit multicast hash filter. 2487 */ 2488 ETHER_FIRST_MULTI(step, ec, enm); 2489 while (enm != NULL) { 2490 /* XXX */ 2491 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2492 ETHER_ADDR_LEN) != 0) 2493 goto allmulti; 2494 2495 hash = rtw_calchash(enm->enm_addrlo); 2496 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2497 sc->sc_rcr |= RTW_RCR_AM; 2498 ETHER_NEXT_MULTI(step, enm); 2499 } 2500 2501 /* all bits set => hash is useless */ 2502 if (~(hashes[0] & hashes[1]) == 0) 2503 goto allmulti; 2504 2505 setit: 2506 if (ifp->if_flags & IFF_ALLMULTI) { 2507 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2508 hashes[0] = hashes[1] = 0xffffffff; 2509 } 2510 2511 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2512 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2513 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2514 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2515 2516 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2517 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2518 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2519 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2520 2521 return; 2522 } 2523 2524 #define IEEE80211_BEACON_TIMESTAMP_LEN 8 2525 #define IEEE80211_BEACON_BINTVL_LEN 2 2526 #define IEEE80211_BEACON_CAPINFO_LEN 2 2527 #define IEEE80211_TLV_SSID_LEN(__esslen) (2 + (__esslen)) 2528 #define IEEE80211_TLV_SUPRATES_LEN(__nrates) (2 + (__nrates)) 2529 #define IEEE80211_TLV_XSUPRATES_LEN(__nrates) (2 + (__nrates)) 2530 #define IEEE80211_TLV_DSPARMS_LEN 3 2531 #define IEEE80211_TLV_IBSSPARMS 4 2532 #define IEEE80211_TLV_MIN_TIM 6 2533 2534 #define IEEE80211_TLV_ALLRATES_LEN(__nrates) \ 2535 (((__nrates) > IEEE80211_RATE_SIZE) ? 4 + (__nrates) : 2 + (__nrates)) 2536 2537 static struct mbuf * 2538 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2539 { 2540 struct ieee80211com *ic = &sc->sc_ic; 2541 struct mbuf *m; 2542 struct ieee80211_beacon_offsets boff; 2543 2544 m = ieee80211_beacon_alloc(ic, ni, &boff); 2545 2546 RTW_DPRINTF(RTW_DEBUG_BEACON, 2547 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2548 2549 return m; 2550 } 2551 2552 /* Must be called at splnet. */ 2553 static int 2554 rtw_init(struct ifnet *ifp) 2555 { 2556 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2557 struct ieee80211com *ic = &sc->sc_ic; 2558 struct rtw_regs *regs = &sc->sc_regs; 2559 int rc = 0; 2560 2561 if ((rc = rtw_enable(sc)) != 0) 2562 goto out; 2563 2564 /* Cancel pending I/O and reset. */ 2565 rtw_stop(ifp, 0); 2566 2567 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2568 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2569 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2570 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2571 2572 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2573 goto out; 2574 2575 if ((rc = rtw_swring_setup(sc)) != 0) 2576 goto out; 2577 2578 rtw_transmit_config(regs); 2579 2580 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2581 2582 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2583 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2584 2585 /* long PLCP header, 1Mb/2Mb basic rate */ 2586 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2587 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2588 2589 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2590 rtw_set_access(regs, RTW_ACCESS_NONE); 2591 2592 /* XXX from reference sources */ 2593 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2594 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2595 2596 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2597 2598 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2599 /* from Linux driver */ 2600 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2601 2602 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2603 2604 rtw_enable_interrupts(sc); 2605 2606 rtw_pktfilt_load(sc); 2607 2608 rtw_hwring_setup(sc); 2609 2610 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2611 2612 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2613 2614 ifp->if_flags |= IFF_RUNNING; 2615 ic->ic_state = IEEE80211_S_INIT; 2616 2617 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2618 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2619 2620 rtw_resume_ticks(sc); 2621 2622 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2623 2624 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2625 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2626 else 2627 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2628 2629 out: 2630 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2631 return rc; 2632 } 2633 2634 static __inline void 2635 rtw_led_init(struct rtw_regs *regs) 2636 { 2637 uint8_t cfg0, cfg1; 2638 2639 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2640 2641 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2642 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2643 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2644 2645 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2646 RTW_DPRINTF(RTW_DEBUG_LED, 2647 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2648 2649 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2650 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2651 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2652 2653 rtw_set_access(regs, RTW_ACCESS_NONE); 2654 } 2655 2656 /* 2657 * IEEE80211_S_INIT: LED1 off 2658 * 2659 * IEEE80211_S_AUTH, 2660 * IEEE80211_S_ASSOC, 2661 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2662 * 2663 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2664 */ 2665 static void 2666 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2667 { 2668 struct rtw_led_state *ls; 2669 2670 ls = &sc->sc_led_state; 2671 2672 switch (nstate) { 2673 case IEEE80211_S_INIT: 2674 rtw_led_init(&sc->sc_regs); 2675 callout_stop(&ls->ls_slow_ch); 2676 callout_stop(&ls->ls_fast_ch); 2677 ls->ls_slowblink = 0; 2678 ls->ls_actblink = 0; 2679 ls->ls_default = 0; 2680 break; 2681 case IEEE80211_S_SCAN: 2682 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2683 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2684 /*FALLTHROUGH*/ 2685 case IEEE80211_S_AUTH: 2686 case IEEE80211_S_ASSOC: 2687 ls->ls_default = RTW_LED1; 2688 ls->ls_actblink = RTW_LED1; 2689 ls->ls_slowblink = RTW_LED1; 2690 break; 2691 case IEEE80211_S_RUN: 2692 ls->ls_slowblink = 0; 2693 break; 2694 } 2695 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2696 } 2697 2698 static void 2699 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2700 { 2701 uint8_t led_condition; 2702 bus_size_t ofs; 2703 uint8_t mask, newval, val; 2704 2705 led_condition = ls->ls_default; 2706 2707 if (ls->ls_state & RTW_LED_S_SLOW) 2708 led_condition ^= ls->ls_slowblink; 2709 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2710 led_condition ^= ls->ls_actblink; 2711 2712 RTW_DPRINTF(RTW_DEBUG_LED, 2713 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2714 2715 switch (hwverid) { 2716 default: 2717 case 'F': 2718 ofs = RTW_PSR; 2719 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2720 if (led_condition & RTW_LED0) 2721 newval &= ~RTW_PSR_LEDGPO0; 2722 if (led_condition & RTW_LED1) 2723 newval &= ~RTW_PSR_LEDGPO1; 2724 break; 2725 case 'D': 2726 ofs = RTW_9346CR; 2727 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2728 newval = RTW_9346CR_EEM_PROGRAM; 2729 if (led_condition & RTW_LED0) 2730 newval |= RTW_9346CR_EEDI; 2731 if (led_condition & RTW_LED1) 2732 newval |= RTW_9346CR_EECS; 2733 break; 2734 } 2735 val = RTW_READ8(regs, ofs); 2736 RTW_DPRINTF(RTW_DEBUG_LED, 2737 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2738 (uintptr_t)ofs)); 2739 val &= ~mask; 2740 val |= newval; 2741 RTW_WRITE8(regs, ofs, val); 2742 RTW_DPRINTF(RTW_DEBUG_LED, 2743 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2744 (uintptr_t)ofs)); 2745 RTW_SYNC(regs, ofs, ofs); 2746 } 2747 2748 static void 2749 rtw_led_fastblink(void *arg) 2750 { 2751 int ostate, s; 2752 struct rtw_softc *sc = (struct rtw_softc *)arg; 2753 struct rtw_led_state *ls = &sc->sc_led_state; 2754 2755 s = splnet(); 2756 ostate = ls->ls_state; 2757 ls->ls_state ^= ls->ls_event; 2758 2759 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2760 ls->ls_state &= ~RTW_LED_S_TX; 2761 2762 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2763 ls->ls_state &= ~RTW_LED_S_RX; 2764 2765 ls->ls_event = 0; 2766 2767 if (ostate != ls->ls_state) 2768 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2769 splx(s); 2770 2771 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2772 } 2773 2774 static void 2775 rtw_led_slowblink(void *arg) 2776 { 2777 int s; 2778 struct rtw_softc *sc = (struct rtw_softc *)arg; 2779 struct rtw_led_state *ls = &sc->sc_led_state; 2780 2781 s = splnet(); 2782 ls->ls_state ^= RTW_LED_S_SLOW; 2783 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2784 splx(s); 2785 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2786 } 2787 2788 static __inline void 2789 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2790 { 2791 callout_init(&ls->ls_fast_ch); 2792 callout_init(&ls->ls_slow_ch); 2793 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2794 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2795 } 2796 2797 static int 2798 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2799 { 2800 int rc = 0, s; 2801 struct rtw_softc *sc = ifp->if_softc; 2802 struct ifreq *ifr = (struct ifreq *)data; 2803 2804 s = splnet(); 2805 switch (cmd) { 2806 case SIOCSIFFLAGS: 2807 if ((ifp->if_flags & IFF_UP) != 0) { 2808 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2809 rtw_pktfilt_load(sc); 2810 } else 2811 rc = rtw_init(ifp); 2812 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2813 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2814 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2815 rtw_stop(ifp, 1); 2816 } 2817 break; 2818 case SIOCADDMULTI: 2819 case SIOCDELMULTI: 2820 if (cmd == SIOCADDMULTI) 2821 rc = ether_addmulti(ifr, &sc->sc_ec); 2822 else 2823 rc = ether_delmulti(ifr, &sc->sc_ec); 2824 if (rc != ENETRESET) 2825 break; 2826 if (ifp->if_flags & IFF_RUNNING) 2827 rtw_pktfilt_load(sc); 2828 rc = 0; 2829 break; 2830 default: 2831 if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 2832 break; 2833 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2834 rc = rtw_init(ifp); 2835 else 2836 rc = 0; 2837 break; 2838 } 2839 splx(s); 2840 return rc; 2841 } 2842 2843 /* Select a transmit ring with at least one h/w and s/w descriptor free. 2844 * Return 0 on success, -1 on failure. 2845 */ 2846 static __inline int 2847 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 2848 struct rtw_txdesc_blk **tdbp, int pri) 2849 { 2850 struct rtw_txsoft_blk *tsb; 2851 struct rtw_txdesc_blk *tdb; 2852 2853 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 2854 2855 tsb = &sc->sc_txsoft_blk[pri]; 2856 tdb = &sc->sc_txdesc_blk[pri]; 2857 2858 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 2859 *tsbp = NULL; 2860 *tdbp = NULL; 2861 return -1; 2862 } 2863 *tsbp = tsb; 2864 *tdbp = tdb; 2865 return 0; 2866 } 2867 2868 static __inline struct mbuf * 2869 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 2870 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 2871 struct ieee80211_node **nip, short *if_flagsp) 2872 { 2873 struct mbuf *m; 2874 2875 if (IF_IS_EMPTY(ifq)) 2876 return NULL; 2877 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 2878 *if_flagsp |= IFF_OACTIVE; 2879 return NULL; 2880 } 2881 IF_DEQUEUE(ifq, m); 2882 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2883 m->m_pkthdr.rcvif = NULL; 2884 KASSERT(*nip != NULL); 2885 return m; 2886 } 2887 2888 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 2889 * at the driver's selection of transmit control block for the packet. 2890 */ 2891 static __inline int 2892 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 2893 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 2894 struct ieee80211_node **nip) 2895 { 2896 int pri; 2897 struct ether_header *eh; 2898 struct mbuf *m0; 2899 struct rtw_softc *sc; 2900 short *if_flagsp; 2901 2902 sc = (struct rtw_softc *)ifp->if_softc; 2903 2904 DPRINTF(sc, RTW_DEBUG_XMIT, 2905 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2906 2907 if_flagsp = &ifp->if_flags; 2908 2909 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 2910 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 2911 tdbp, nip, if_flagsp)) != NULL) { 2912 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 2913 __func__)); 2914 return 0; 2915 } 2916 2917 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 2918 tdbp, nip, if_flagsp)) != NULL) { 2919 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 2920 __func__)); 2921 return 0; 2922 } 2923 2924 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 2925 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 2926 return 0; 2927 } 2928 2929 *mp = NULL; 2930 2931 IFQ_POLL(&ifp->if_snd, m0); 2932 if (m0 == NULL) { 2933 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 2934 __func__)); 2935 return 0; 2936 } 2937 2938 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 2939 2940 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 2941 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no descriptor\n", __func__)); 2942 *if_flagsp |= IFF_OACTIVE; 2943 return 0; 2944 } 2945 2946 IFQ_DEQUEUE(&ifp->if_snd, m0); 2947 if (m0 == NULL) { 2948 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 2949 __func__)); 2950 return 0; 2951 } 2952 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 2953 ifp->if_opackets++; 2954 #if NBPFILTER > 0 2955 if (ifp->if_bpf) 2956 bpf_mtap(ifp->if_bpf, m0); 2957 #endif 2958 eh = mtod(m0, struct ether_header *); 2959 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 2960 if (*nip == NULL) { 2961 /* NB: ieee80211_find_txnode does stat+msg */ 2962 m_freem(m0); 2963 return -1; 2964 } 2965 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 2966 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 2967 ifp->if_oerrors++; 2968 return -1; 2969 } 2970 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 2971 *mp = m0; 2972 return 0; 2973 } 2974 2975 static int 2976 rtw_seg_too_short(bus_dmamap_t dmamap) 2977 { 2978 int i; 2979 for (i = 0; i < dmamap->dm_nsegs; i++) { 2980 if (dmamap->dm_segs[i].ds_len < 4) { 2981 printf("%s: segment too short\n", __func__); 2982 return 1; 2983 } 2984 } 2985 return 0; 2986 } 2987 2988 /* TBD factor with atw_start */ 2989 static struct mbuf * 2990 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2991 u_int ndescfree, short *ifflagsp, const char *dvname) 2992 { 2993 int first, rc; 2994 struct mbuf *m, *m0; 2995 2996 m0 = chain; 2997 2998 /* 2999 * Load the DMA map. Copy and try (once) again if the packet 3000 * didn't fit in the alloted number of segments. 3001 */ 3002 for (first = 1; 3003 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 3004 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 3005 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 3006 first = 0) { 3007 if (rc == 0) 3008 bus_dmamap_unload(dmat, dmam); 3009 MGETHDR(m, M_DONTWAIT, MT_DATA); 3010 if (m == NULL) { 3011 printf("%s: unable to allocate Tx mbuf\n", 3012 dvname); 3013 break; 3014 } 3015 if (m0->m_pkthdr.len > MHLEN) { 3016 MCLGET(m, M_DONTWAIT); 3017 if ((m->m_flags & M_EXT) == 0) { 3018 printf("%s: cannot allocate Tx cluster\n", 3019 dvname); 3020 m_freem(m); 3021 break; 3022 } 3023 } 3024 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3025 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3026 m_freem(m0); 3027 m0 = m; 3028 m = NULL; 3029 } 3030 if (rc != 0) { 3031 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 3032 m_freem(m0); 3033 return NULL; 3034 } else if (rtw_seg_too_short(dmam)) { 3035 printf("%s: cannot load Tx buffer, segment too short\n", 3036 dvname); 3037 bus_dmamap_unload(dmat, dmam); 3038 m_freem(m0); 3039 return NULL; 3040 } else if (dmam->dm_nsegs > ndescfree) { 3041 printf("%s: too many tx segments\n", dvname); 3042 *ifflagsp |= IFF_OACTIVE; 3043 bus_dmamap_unload(dmat, dmam); 3044 m_freem(m0); 3045 return NULL; 3046 } 3047 return m0; 3048 } 3049 3050 #ifdef RTW_DEBUG 3051 static void 3052 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3053 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3054 { 3055 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3056 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] ctl0 %#08x " 3057 "ctl1 %#08x buf %#08x len %#08x\n", 3058 sc->sc_dev.dv_xname, ts, action, desc, 3059 le32toh(td->td_ctl0), 3060 le32toh(td->td_ctl1), le32toh(td->td_buf), 3061 le32toh(td->td_len))); 3062 } 3063 #endif /* RTW_DEBUG */ 3064 3065 static void 3066 rtw_start(struct ifnet *ifp) 3067 { 3068 uint8_t tppoll; 3069 int desc, i, lastdesc, npkt, rate; 3070 uint32_t proto_ctl0, ctl0, ctl1; 3071 bus_dmamap_t dmamap; 3072 struct ieee80211com *ic; 3073 struct ieee80211_duration *d0; 3074 struct ieee80211_frame_min *wh; 3075 struct ieee80211_node *ni; 3076 struct mbuf *m0; 3077 struct rtw_softc *sc; 3078 struct rtw_txsoft_blk *tsb; 3079 struct rtw_txdesc_blk *tdb; 3080 struct rtw_txsoft *ts; 3081 struct rtw_txdesc *td; 3082 struct ieee80211_key *k; 3083 3084 sc = (struct rtw_softc *)ifp->if_softc; 3085 ic = &sc->sc_ic; 3086 3087 DPRINTF(sc, RTW_DEBUG_XMIT, 3088 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3089 3090 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3091 goto out; 3092 3093 /* XXX do real rate control */ 3094 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3095 3096 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3097 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3098 3099 for (;;) { 3100 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3101 continue; 3102 if (m0 == NULL) 3103 break; 3104 3105 wh = mtod(m0, struct ieee80211_frame_min *); 3106 3107 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3108 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3109 m_freem(m0); 3110 break; 3111 } else 3112 k = NULL; 3113 3114 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3115 3116 dmamap = ts->ts_dmamap; 3117 3118 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3119 tdb->tdb_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 3120 3121 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3122 DPRINTF(sc, RTW_DEBUG_XMIT, 3123 ("%s: fail dmamap load\n", __func__)); 3124 goto post_dequeue_err; 3125 } 3126 3127 /* Note well: rtw_dmamap_load_txbuf may have created 3128 * a new chain, so we must find the header once 3129 * more. 3130 */ 3131 wh = mtod(m0, struct ieee80211_frame_min *); 3132 3133 /* XXX do real rate control */ 3134 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3135 IEEE80211_FC0_TYPE_MGT) 3136 rate = 2; 3137 else 3138 rate = MAX(2, ieee80211_get_rate(ic)); 3139 3140 #ifdef RTW_DEBUG 3141 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3142 (IFF_DEBUG|IFF_LINK2)) { 3143 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3144 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3145 : sizeof(wh), 3146 rate, 0); 3147 } 3148 #endif /* RTW_DEBUG */ 3149 ctl0 = proto_ctl0 | 3150 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3151 3152 switch (rate) { 3153 default: 3154 case 2: 3155 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3156 break; 3157 case 4: 3158 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3159 break; 3160 case 11: 3161 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3162 break; 3163 case 22: 3164 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3165 break; 3166 } 3167 /* XXX >= ? Compare after fragmentation? */ 3168 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3169 ctl0 |= RTW_TXCTL0_RTSEN; 3170 3171 if (k != NULL) { 3172 ctl0 |= LSHIFT(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3173 RTW_TXCTL0_KEYID_MASK; 3174 } 3175 3176 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3177 IEEE80211_FC0_TYPE_MGT) { 3178 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3179 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3180 IEEE80211_FC0_SUBTYPE_BEACON) 3181 ctl0 |= RTW_TXCTL0_BEACON; 3182 } 3183 3184 if (ieee80211_compute_duration(wh, m0->m_pkthdr.len, 3185 ic->ic_flags, ic->ic_fragthreshold, 3186 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3187 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3188 (IFF_DEBUG|IFF_LINK2)) == -1) { 3189 DPRINTF(sc, RTW_DEBUG_XMIT, 3190 ("%s: fail compute duration\n", __func__)); 3191 goto post_load_err; 3192 } 3193 3194 d0 = &ts->ts_d0; 3195 3196 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3197 3198 ctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3199 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3200 3201 if (d0->d_residue) 3202 ctl1 |= RTW_TXCTL1_LENGEXT; 3203 3204 /* TBD fragmentation */ 3205 3206 ts->ts_first = tdb->tdb_next; 3207 3208 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3209 BUS_DMASYNC_PREWRITE); 3210 3211 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3212 3213 #if NBPFILTER > 0 3214 if (ic->ic_rawbpf != NULL) 3215 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3216 3217 if (sc->sc_radiobpf != NULL) { 3218 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3219 3220 rt->rt_flags = 0; 3221 rt->rt_rate = rate; 3222 rt->rt_chan_freq = 3223 htole16(ic->ic_bss->ni_chan->ic_freq); 3224 rt->rt_chan_flags = 3225 htole16(ic->ic_bss->ni_chan->ic_flags); 3226 3227 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rt, 3228 sizeof(sc->sc_txtapu), m0); 3229 } 3230 #endif /* NPBFILTER > 0 */ 3231 3232 for (i = 0, lastdesc = desc = ts->ts_first; 3233 i < dmamap->dm_nsegs; 3234 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3235 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3236 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3237 ("%s: seg too long\n", __func__)); 3238 goto post_load_err; 3239 } 3240 td = &tdb->tdb_desc[desc]; 3241 td->td_ctl0 = htole32(ctl0); 3242 if (i != 0) 3243 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3244 td->td_ctl1 = htole32(ctl1); 3245 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3246 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3247 lastdesc = desc; 3248 #ifdef RTW_DEBUG 3249 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3250 #endif /* RTW_DEBUG */ 3251 } 3252 3253 KASSERT(desc < tdb->tdb_ndesc); 3254 3255 ts->ts_ni = ni; 3256 KASSERT(ni != NULL); 3257 ts->ts_mbuf = m0; 3258 ts->ts_last = lastdesc; 3259 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3260 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3261 htole32(RTW_TXCTL0_FS); 3262 3263 #ifdef RTW_DEBUG 3264 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3265 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3266 #endif /* RTW_DEBUG */ 3267 3268 tdb->tdb_nfree -= dmamap->dm_nsegs; 3269 tdb->tdb_next = desc; 3270 3271 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3272 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3273 3274 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3275 htole32(RTW_TXCTL0_OWN); 3276 3277 #ifdef RTW_DEBUG 3278 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3279 #endif /* RTW_DEBUG */ 3280 3281 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3282 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3283 3284 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3285 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3286 3287 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) { 3288 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3289 tsb->tsb_tx_timer = 5; 3290 ifp->if_timer = 1; 3291 } 3292 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3293 tppoll &= ~RTW_TPPOLL_SALL; 3294 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL; 3295 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3296 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3297 } 3298 out: 3299 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3300 return; 3301 post_load_err: 3302 bus_dmamap_unload(sc->sc_dmat, dmamap); 3303 m_freem(m0); 3304 post_dequeue_err: 3305 ieee80211_free_node(ni); 3306 return; 3307 } 3308 3309 static void 3310 rtw_watchdog(struct ifnet *ifp) 3311 { 3312 int pri; 3313 struct rtw_softc *sc; 3314 struct rtw_txsoft_blk *tsb; 3315 3316 sc = ifp->if_softc; 3317 3318 ifp->if_timer = 0; 3319 3320 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 3321 return; 3322 3323 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3324 tsb = &sc->sc_txsoft_blk[pri]; 3325 3326 if (tsb->tsb_tx_timer == 0) 3327 continue; 3328 3329 if (--tsb->tsb_tx_timer == 0) { 3330 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3331 continue; 3332 printf("%s: transmit timeout, priority %d\n", 3333 ifp->if_xname, pri); 3334 ifp->if_oerrors++; 3335 /* Stop Tx DMA, disable transmitter, clear 3336 * Tx rings, and restart. 3337 * 3338 * TBD Stop/restart just the broken ring? 3339 */ 3340 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3341 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3342 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 0); 3343 rtw_txdescs_reset(sc); 3344 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 1); 3345 ifp->if_flags &= ~IFF_OACTIVE; 3346 rtw_start(ifp); 3347 } else 3348 ifp->if_timer = 1; 3349 } 3350 ieee80211_watchdog(&sc->sc_ic); 3351 return; 3352 } 3353 3354 static void 3355 rtw_next_scan(void *arg) 3356 { 3357 struct ieee80211com *ic = arg; 3358 int s; 3359 3360 /* don't call rtw_start w/o network interrupts blocked */ 3361 s = splnet(); 3362 if (ic->ic_state == IEEE80211_S_SCAN) 3363 ieee80211_next_scan(ic); 3364 splx(s); 3365 } 3366 3367 static void 3368 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3369 { 3370 uint16_t bcnitv, intval; 3371 int i; 3372 struct rtw_regs *regs = &sc->sc_regs; 3373 3374 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3375 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3376 3377 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3378 3379 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3380 3381 intval = MIN(intval0, PRESHIFT(RTW_BCNITV_BCNITV_MASK)); 3382 3383 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3384 bcnitv |= LSHIFT(intval, RTW_BCNITV_BCNITV_MASK); 3385 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3386 /* magic from Linux */ 3387 RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND)); 3388 RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV)); 3389 3390 rtw_set_access(regs, RTW_ACCESS_NONE); 3391 3392 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 3393 } 3394 3395 /* Synchronize the hardware state with the software state. */ 3396 static int 3397 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3398 { 3399 struct ifnet *ifp = ic->ic_ifp; 3400 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3401 struct mbuf *m; 3402 enum ieee80211_state ostate; 3403 int error; 3404 3405 ostate = ic->ic_state; 3406 3407 rtw_led_newstate(sc, nstate); 3408 3409 if (nstate == IEEE80211_S_INIT) { 3410 callout_stop(&sc->sc_scan_ch); 3411 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3412 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3413 } 3414 3415 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3416 rtw_pwrstate(sc, RTW_ON); 3417 3418 if ((error = rtw_tune(sc)) != 0) 3419 return error; 3420 3421 switch (nstate) { 3422 case IEEE80211_S_INIT: 3423 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3424 break; 3425 case IEEE80211_S_SCAN: 3426 if (ostate != IEEE80211_S_SCAN) { 3427 (void)memset(ic->ic_bss->ni_bssid, 0, 3428 IEEE80211_ADDR_LEN); 3429 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3430 } 3431 3432 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3433 rtw_next_scan, ic); 3434 3435 break; 3436 case IEEE80211_S_RUN: 3437 switch (ic->ic_opmode) { 3438 case IEEE80211_M_HOSTAP: 3439 case IEEE80211_M_IBSS: 3440 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3441 m = rtw_beacon_alloc(sc, ic->ic_bss); 3442 if (m == NULL) { 3443 printf("%s: could not allocate beacon\n", 3444 sc->sc_dev.dv_xname); 3445 } else { 3446 IF_ENQUEUE(&sc->sc_beaconq, m); 3447 m->m_pkthdr.rcvif = 3448 (void *)ieee80211_ref_node(ic->ic_bss); 3449 } 3450 /*FALLTHROUGH*/ 3451 case IEEE80211_M_AHDEMO: 3452 case IEEE80211_M_STA: 3453 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3454 ic->ic_bss->ni_intval); 3455 break; 3456 case IEEE80211_M_MONITOR: 3457 break; 3458 } 3459 rtw_set_nettype(sc, ic->ic_opmode); 3460 break; 3461 case IEEE80211_S_ASSOC: 3462 case IEEE80211_S_AUTH: 3463 break; 3464 } 3465 3466 if (nstate != IEEE80211_S_SCAN) 3467 callout_stop(&sc->sc_scan_ch); 3468 3469 /* Start beacon transmission. */ 3470 if (nstate == IEEE80211_S_RUN && 3471 (ic->ic_opmode == IEEE80211_M_HOSTAP || 3472 ic->ic_opmode == IEEE80211_M_IBSS)) 3473 rtw_start(ifp); 3474 3475 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3476 } 3477 3478 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3479 static uint64_t 3480 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3481 { 3482 uint32_t tsftl, tsfth; 3483 3484 tsfth = RTW_READ(regs, RTW_TSFTRH); 3485 tsftl = RTW_READ(regs, RTW_TSFTRL); 3486 if (tsftl < rstamp) /* Compensate for rollover. */ 3487 tsfth--; 3488 return ((uint64_t)tsfth << 32) | rstamp; 3489 } 3490 3491 static void 3492 rtw_ibss_merge(struct rtw_softc *sc, struct ieee80211_node *ni, uint32_t rstamp) 3493 { 3494 uint8_t tppoll; 3495 struct ieee80211com *ic = &sc->sc_ic; 3496 3497 if (le64toh(ni->ni_tstamp.tsf) < rtw_tsf_extend(&sc->sc_regs, rstamp)) 3498 return; 3499 if (ieee80211_ibss_merge(ic, ni) == ENETRESET) { 3500 /* Stop beacon queue. Kick state machine to synchronize 3501 * with the new IBSS. 3502 */ 3503 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3504 tppoll |= RTW_TPPOLL_SBQ; 3505 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3506 (void)ieee80211_new_state(&sc->sc_ic, IEEE80211_S_RUN, -1); 3507 } 3508 return; 3509 } 3510 3511 static void 3512 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3513 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3514 { 3515 struct ifnet *ifp = ic->ic_ifp; 3516 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3517 3518 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3519 3520 switch (subtype) { 3521 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3522 case IEEE80211_FC0_SUBTYPE_BEACON: 3523 if (ic->ic_opmode != IEEE80211_M_IBSS || 3524 ic->ic_state != IEEE80211_S_RUN) 3525 return; 3526 rtw_ibss_merge(sc, ni, rstamp); 3527 break; 3528 default: 3529 break; 3530 } 3531 return; 3532 } 3533 3534 static struct ieee80211_node * 3535 rtw_node_alloc(struct ieee80211_node_table *nt) 3536 { 3537 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3538 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3539 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3540 3541 DPRINTF(sc, RTW_DEBUG_NODE, 3542 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3543 return ni; 3544 } 3545 3546 static void 3547 rtw_node_free(struct ieee80211_node *ni) 3548 { 3549 struct ieee80211com *ic = ni->ni_ic; 3550 struct ifnet *ifp = ic->ic_ifp; 3551 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3552 3553 DPRINTF(sc, RTW_DEBUG_NODE, 3554 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3555 ether_sprintf(ni->ni_bssid))); 3556 (*sc->sc_mtbl.mt_node_free)(ni); 3557 } 3558 3559 static int 3560 rtw_media_change(struct ifnet *ifp) 3561 { 3562 int error; 3563 3564 error = ieee80211_media_change(ifp); 3565 if (error == ENETRESET) { 3566 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3567 (IFF_RUNNING|IFF_UP)) 3568 rtw_init(ifp); /* XXX lose error */ 3569 error = 0; 3570 } 3571 return error; 3572 } 3573 3574 static void 3575 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3576 { 3577 struct rtw_softc *sc = ifp->if_softc; 3578 3579 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3580 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3581 imr->ifm_status = 0; 3582 return; 3583 } 3584 ieee80211_media_status(ifp, imr); 3585 } 3586 3587 void 3588 rtw_power(int why, void *arg) 3589 { 3590 struct rtw_softc *sc = arg; 3591 struct ifnet *ifp = &sc->sc_if; 3592 int s; 3593 3594 DPRINTF(sc, RTW_DEBUG_PWR, 3595 ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3596 3597 s = splnet(); 3598 switch (why) { 3599 case PWR_STANDBY: 3600 /* XXX do nothing. */ 3601 break; 3602 case PWR_SUSPEND: 3603 rtw_stop(ifp, 0); 3604 if (sc->sc_power != NULL) 3605 (*sc->sc_power)(sc, why); 3606 break; 3607 case PWR_RESUME: 3608 if (ifp->if_flags & IFF_UP) { 3609 if (sc->sc_power != NULL) 3610 (*sc->sc_power)(sc, why); 3611 rtw_init(ifp); 3612 } 3613 break; 3614 case PWR_SOFTSUSPEND: 3615 case PWR_SOFTSTANDBY: 3616 case PWR_SOFTRESUME: 3617 break; 3618 } 3619 splx(s); 3620 } 3621 3622 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 3623 void 3624 rtw_shutdown(void *arg) 3625 { 3626 struct rtw_softc *sc = arg; 3627 3628 rtw_stop(&sc->sc_if, 1); 3629 } 3630 3631 static __inline void 3632 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3633 { 3634 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3635 ifp->if_softc = softc; 3636 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3637 IFF_NOTRAILERS; 3638 ifp->if_ioctl = rtw_ioctl; 3639 ifp->if_start = rtw_start; 3640 ifp->if_watchdog = rtw_watchdog; 3641 ifp->if_init = rtw_init; 3642 ifp->if_stop = rtw_stop; 3643 } 3644 3645 static __inline void 3646 rtw_set80211props(struct ieee80211com *ic) 3647 { 3648 int nrate; 3649 ic->ic_phytype = IEEE80211_T_DS; 3650 ic->ic_opmode = IEEE80211_M_STA; 3651 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3652 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 3653 3654 nrate = 0; 3655 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3656 IEEE80211_RATE_BASIC | 2; 3657 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3658 IEEE80211_RATE_BASIC | 4; 3659 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3660 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3661 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3662 } 3663 3664 static __inline void 3665 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3666 { 3667 mtbl->mt_newstate = ic->ic_newstate; 3668 ic->ic_newstate = rtw_newstate; 3669 3670 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3671 ic->ic_recv_mgmt = rtw_recv_mgmt; 3672 3673 mtbl->mt_node_free = ic->ic_node_free; 3674 ic->ic_node_free = rtw_node_free; 3675 3676 mtbl->mt_node_alloc = ic->ic_node_alloc; 3677 ic->ic_node_alloc = rtw_node_alloc; 3678 3679 ic->ic_crypto.cs_key_alloc = rtw_key_alloc; 3680 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3681 ic->ic_crypto.cs_key_set = rtw_key_set; 3682 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3683 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3684 } 3685 3686 static __inline void 3687 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 3688 void *arg) 3689 { 3690 /* 3691 * Make sure the interface is shutdown during reboot. 3692 */ 3693 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 3694 if (hooks->rh_shutdown == NULL) 3695 printf("%s: WARNING: unable to establish shutdown hook\n", 3696 dvname); 3697 3698 /* 3699 * Add a suspend hook to make sure we come back up after a 3700 * resume. 3701 */ 3702 hooks->rh_power = powerhook_establish(rtw_power, arg); 3703 if (hooks->rh_power == NULL) 3704 printf("%s: WARNING: unable to establish power hook\n", 3705 dvname); 3706 } 3707 3708 static __inline void 3709 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 3710 void *arg) 3711 { 3712 if (hooks->rh_shutdown != NULL) 3713 shutdownhook_disestablish(hooks->rh_shutdown); 3714 3715 if (hooks->rh_power != NULL) 3716 powerhook_disestablish(hooks->rh_power); 3717 } 3718 3719 static __inline void 3720 rtw_init_radiotap(struct rtw_softc *sc) 3721 { 3722 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3723 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3724 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT); 3725 3726 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3727 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3728 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3729 } 3730 3731 static int 3732 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3733 { 3734 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3735 SIMPLEQ_INIT(&tsb->tsb_freeq); 3736 tsb->tsb_ndesc = qlen; 3737 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3738 M_NOWAIT); 3739 if (tsb->tsb_desc == NULL) 3740 return ENOMEM; 3741 return 0; 3742 } 3743 3744 static void 3745 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3746 { 3747 int pri; 3748 struct rtw_txsoft_blk *tsb; 3749 3750 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3751 tsb = &sc->sc_txsoft_blk[pri]; 3752 free(tsb->tsb_desc, M_DEVBUF); 3753 tsb->tsb_desc = NULL; 3754 } 3755 } 3756 3757 static int 3758 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3759 { 3760 int pri, rc = 0; 3761 int qlen[RTW_NTXPRI] = 3762 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3763 struct rtw_txsoft_blk *tsbs; 3764 3765 tsbs = sc->sc_txsoft_blk; 3766 3767 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3768 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3769 if (rc != 0) 3770 break; 3771 } 3772 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3773 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3774 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3775 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3776 return rc; 3777 } 3778 3779 static void 3780 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3781 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3782 { 3783 tdb->tdb_ndesc = ndesc; 3784 tdb->tdb_desc = desc; 3785 tdb->tdb_physbase = physbase; 3786 tdb->tdb_ofs = ofs; 3787 3788 (void)memset(tdb->tdb_desc, 0, 3789 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3790 3791 rtw_txdesc_blk_reset(tdb); 3792 } 3793 3794 static void 3795 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3796 { 3797 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3798 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3799 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3800 3801 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3802 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3803 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3804 3805 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3806 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3807 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3808 3809 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3810 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3811 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3812 } 3813 3814 static struct rtw_rf * 3815 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3816 { 3817 rtw_rf_write_t rf_write; 3818 struct rtw_rf *rf; 3819 3820 switch (rfchipid) { 3821 default: 3822 rf_write = rtw_rf_hostwrite; 3823 break; 3824 case RTW_RFCHIPID_INTERSIL: 3825 case RTW_RFCHIPID_PHILIPS: 3826 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3827 case RTW_RFCHIPID_RFMD: 3828 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3829 break; 3830 } 3831 3832 switch (rfchipid) { 3833 case RTW_RFCHIPID_MAXIM: 3834 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3835 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3836 break; 3837 case RTW_RFCHIPID_PHILIPS: 3838 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3839 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3840 break; 3841 case RTW_RFCHIPID_RFMD: 3842 /* XXX RFMD has no RF constructor */ 3843 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3844 /*FALLTHROUGH*/ 3845 default: 3846 return NULL; 3847 } 3848 rf->rf_continuous_tx_cb = 3849 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3850 rf->rf_continuous_tx_arg = (void *)sc; 3851 return rf; 3852 } 3853 3854 /* Revision C and later use a different PHY delay setting than 3855 * revisions A and B. 3856 */ 3857 static uint8_t 3858 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 3859 { 3860 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3861 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3862 3863 uint8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 3864 3865 RTW_WRITE(regs, RTW_RCR, REVAB); 3866 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3867 RTW_WRITE(regs, RTW_RCR, REVC); 3868 3869 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3870 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3871 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3872 3873 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 3874 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3875 3876 return phydelay; 3877 #undef REVC 3878 } 3879 3880 void 3881 rtw_attach(struct rtw_softc *sc) 3882 { 3883 struct ifnet *ifp = &sc->sc_if; 3884 struct ieee80211com *ic = &sc->sc_ic; 3885 struct rtw_txsoft_blk *tsb; 3886 int pri, rc; 3887 3888 NEXT_ATTACH_STATE(sc, DETACHED); 3889 3890 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3891 case RTW_TCR_HWVERID_F: 3892 sc->sc_hwverid = 'F'; 3893 break; 3894 case RTW_TCR_HWVERID_D: 3895 sc->sc_hwverid = 'D'; 3896 break; 3897 default: 3898 sc->sc_hwverid = '?'; 3899 break; 3900 } 3901 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, 3902 sc->sc_hwverid); 3903 3904 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3905 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3906 0); 3907 3908 if (rc != 0) { 3909 printf("%s: could not allocate hw descriptors, error %d\n", 3910 sc->sc_dev.dv_xname, rc); 3911 goto err; 3912 } 3913 3914 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3915 3916 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3917 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3918 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3919 3920 if (rc != 0) { 3921 printf("%s: could not map hw descriptors, error %d\n", 3922 sc->sc_dev.dv_xname, rc); 3923 goto err; 3924 } 3925 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3926 3927 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3928 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3929 3930 if (rc != 0) { 3931 printf("%s: could not create DMA map for hw descriptors, " 3932 "error %d\n", sc->sc_dev.dv_xname, rc); 3933 goto err; 3934 } 3935 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3936 3937 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 3938 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 3939 3940 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3941 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 3942 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 3943 } 3944 3945 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3946 sizeof(struct rtw_descs), NULL, 0); 3947 3948 if (rc != 0) { 3949 printf("%s: could not load DMA map for hw descriptors, " 3950 "error %d\n", sc->sc_dev.dv_xname, rc); 3951 goto err; 3952 } 3953 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3954 3955 if (rtw_txsoft_blk_setup_all(sc) != 0) 3956 goto err; 3957 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3958 3959 rtw_txdesc_blk_setup_all(sc); 3960 3961 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3962 3963 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 3964 3965 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3966 tsb = &sc->sc_txsoft_blk[pri]; 3967 3968 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3969 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 3970 printf("%s: could not load DMA map for " 3971 "hw tx descriptors, error %d\n", 3972 sc->sc_dev.dv_xname, rc); 3973 goto err; 3974 } 3975 } 3976 3977 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3978 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 3979 RTW_RXQLEN)) != 0) { 3980 printf("%s: could not load DMA map for hw rx descriptors, " 3981 "error %d\n", sc->sc_dev.dv_xname, rc); 3982 goto err; 3983 } 3984 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3985 3986 /* Reset the chip to a known state. */ 3987 if (rtw_reset(sc) != 0) 3988 goto err; 3989 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3990 3991 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3992 3993 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3994 sc->sc_flags |= RTW_F_9356SROM; 3995 3996 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3997 sc->sc_dev.dv_xname) != 0) 3998 goto err; 3999 4000 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 4001 4002 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 4003 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 4004 sc->sc_dev.dv_xname) != 0) { 4005 printf("%s: attach failed, malformed serial ROM\n", 4006 sc->sc_dev.dv_xname); 4007 goto err; 4008 } 4009 4010 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 4011 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 4012 4013 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 4014 4015 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 4016 4017 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 4018 sc->sc_flags & RTW_F_DIGPHY); 4019 4020 if (sc->sc_rf == NULL) { 4021 printf("%s: attach failed, could not attach RF\n", 4022 sc->sc_dev.dv_xname); 4023 goto err; 4024 } 4025 4026 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 4027 4028 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4029 4030 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4031 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 4032 4033 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4034 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 4035 sc->sc_dev.dv_xname); 4036 4037 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 4038 sc->sc_dev.dv_xname); 4039 4040 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4041 sc->sc_dev.dv_xname) != 0) 4042 goto err; 4043 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4044 4045 rtw_setifprops(ifp, sc->sc_dev.dv_xname, (void*)sc); 4046 4047 IFQ_SET_READY(ifp->if_snd); 4048 4049 sc->sc_ic.ic_ifp = ifp; 4050 rtw_set80211props(&sc->sc_ic); 4051 4052 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4053 4054 /* 4055 * Call MI attach routines. 4056 */ 4057 if_attach(ifp); 4058 ieee80211_ifattach(&sc->sc_ic); 4059 4060 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4061 4062 /* possibly we should fill in our own sc_send_prresp, since 4063 * the RTL8180 is probably sending probe responses in ad hoc 4064 * mode. 4065 */ 4066 4067 /* complete initialization */ 4068 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4069 callout_init(&sc->sc_scan_ch); 4070 4071 rtw_init_radiotap(sc); 4072 4073 #if NBPFILTER > 0 4074 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4075 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4076 #endif 4077 4078 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 4079 4080 NEXT_ATTACH_STATE(sc, FINISHED); 4081 4082 ieee80211_announce(ic); 4083 return; 4084 err: 4085 rtw_detach(sc); 4086 return; 4087 } 4088 4089 int 4090 rtw_detach(struct rtw_softc *sc) 4091 { 4092 struct ifnet *ifp = &sc->sc_if; 4093 int pri; 4094 4095 sc->sc_flags |= RTW_F_INVALID; 4096 4097 switch (sc->sc_attach_state) { 4098 case FINISHED: 4099 rtw_stop(ifp, 1); 4100 4101 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 4102 (void*)sc); 4103 callout_stop(&sc->sc_scan_ch); 4104 ieee80211_ifdetach(&sc->sc_ic); 4105 if_detach(ifp); 4106 break; 4107 case FINISH_ID_STA: 4108 case FINISH_RF_ATTACH: 4109 rtw_rf_destroy(sc->sc_rf); 4110 sc->sc_rf = NULL; 4111 /*FALLTHROUGH*/ 4112 case FINISH_PARSE_SROM: 4113 case FINISH_READ_SROM: 4114 rtw_srom_free(&sc->sc_srom); 4115 /*FALLTHROUGH*/ 4116 case FINISH_RESET: 4117 case FINISH_RXMAPS_CREATE: 4118 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4119 RTW_RXQLEN); 4120 /*FALLTHROUGH*/ 4121 case FINISH_TXMAPS_CREATE: 4122 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4123 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4124 sc->sc_txsoft_blk[pri].tsb_desc, 4125 sc->sc_txsoft_blk[pri].tsb_ndesc); 4126 } 4127 /*FALLTHROUGH*/ 4128 case FINISH_TXDESCBLK_SETUP: 4129 case FINISH_TXCTLBLK_SETUP: 4130 rtw_txsoft_blk_cleanup_all(sc); 4131 /*FALLTHROUGH*/ 4132 case FINISH_DESCMAP_LOAD: 4133 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4134 /*FALLTHROUGH*/ 4135 case FINISH_DESCMAP_CREATE: 4136 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4137 /*FALLTHROUGH*/ 4138 case FINISH_DESC_MAP: 4139 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 4140 sizeof(struct rtw_descs)); 4141 /*FALLTHROUGH*/ 4142 case FINISH_DESC_ALLOC: 4143 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4144 sc->sc_desc_nsegs); 4145 /*FALLTHROUGH*/ 4146 case DETACHED: 4147 NEXT_ATTACH_STATE(sc, DETACHED); 4148 break; 4149 } 4150 return 0; 4151 } 4152 4153 int 4154 rtw_activate(struct device *self, enum devact act) 4155 { 4156 struct rtw_softc *sc = (struct rtw_softc *)self; 4157 int rc = 0, s; 4158 4159 s = splnet(); 4160 switch (act) { 4161 case DVACT_ACTIVATE: 4162 rc = EOPNOTSUPP; 4163 break; 4164 4165 case DVACT_DEACTIVATE: 4166 if_deactivate(&sc->sc_if); 4167 break; 4168 } 4169 splx(s); 4170 return rc; 4171 } 4172
Indexes created Thu Sep 25 16:09:42 GMT 2025