rtw.c revision 1.57
1 /* $NetBSD: rtw.c,v 1.57 2005/11/18 16:53:56 skrll Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.57 2005/11/18 16:53:56 skrll Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/time.h> 49 #include <sys/types.h> 50 51 #include <machine/endian.h> 52 #include <machine/bus.h> 53 #include <machine/intr.h> /* splnet */ 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <dev/ic/rtwreg.h> 70 #include <dev/ic/rtwvar.h> 71 #include <dev/ic/rtwphyio.h> 72 #include <dev/ic/rtwphy.h> 73 74 #include <dev/ic/smc93cx6var.h> 75 76 #define KASSERT2(__cond, __msg) \ 77 do { \ 78 if (!(__cond)) \ 79 panic __msg ; \ 80 } while (0) 81 82 int rtw_rfprog_fallback = 0; 83 int rtw_host_rfio = 0; 84 85 #ifdef RTW_DEBUG 86 int rtw_debug = 0; 87 int rtw_rxbufs_limit = RTW_RXQLEN; 88 #endif /* RTW_DEBUG */ 89 90 #define NEXT_ATTACH_STATE(sc, state) do { \ 91 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 92 ("%s: attach state %s\n", __func__, #state)); \ 93 sc->sc_attach_state = state; \ 94 } while (0) 95 96 int rtw_dwelltime = 200; /* milliseconds */ 97 static struct ieee80211_cipher rtw_cipher_wep; 98 99 static void rtw_start(struct ifnet *); 100 101 static void rtw_io_enable(struct rtw_regs *, uint8_t, int); 102 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 103 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 104 const u_int8_t[IEEE80211_ADDR_LEN]); 105 static void rtw_key_update_end(struct ieee80211com *); 106 static void rtw_key_update_begin(struct ieee80211com *); 107 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 108 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 109 110 static void rtw_led_attach(struct rtw_led_state *, void *); 111 static void rtw_led_init(struct rtw_regs *); 112 static void rtw_led_slowblink(void *); 113 static void rtw_led_fastblink(void *); 114 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 115 116 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 117 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 118 #ifdef RTW_DEBUG 119 static void rtw_print_txdesc(struct rtw_softc *, const char *, 120 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 121 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 122 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 123 #endif /* RTW_DEBUG */ 124 125 /* 126 * Setup sysctl(3) MIB, hw.rtw.* 127 * 128 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 129 */ 130 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 131 { 132 int rc; 133 const struct sysctlnode *cnode, *rnode; 134 135 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 136 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 137 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 138 goto err; 139 140 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 141 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 142 "Realtek RTL818x 802.11 controls", 143 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 144 goto err; 145 146 #ifdef RTW_DEBUG 147 /* control debugging printfs */ 148 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 149 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 150 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 151 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 152 CTL_CREATE, CTL_EOL)) != 0) 153 goto err; 154 155 /* Limit rx buffers, for simulating resource exhaustion. */ 156 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 157 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 158 "rxbufs_limit", 159 SYSCTL_DESCR("Set rx buffers limit"), 160 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 161 CTL_CREATE, CTL_EOL)) != 0) 162 goto err; 163 164 #endif /* RTW_DEBUG */ 165 /* set fallback RF programming method */ 166 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 167 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 168 "rfprog_fallback", 169 SYSCTL_DESCR("Set fallback RF programming method"), 170 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 171 CTL_CREATE, CTL_EOL)) != 0) 172 goto err; 173 174 /* force host to control RF I/O bus */ 175 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 176 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 177 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 178 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 179 CTL_CREATE, CTL_EOL)) != 0) 180 goto err; 181 182 return; 183 err: 184 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 185 } 186 187 static int 188 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 189 { 190 int error, t; 191 struct sysctlnode node; 192 193 node = *rnode; 194 t = *(int*)rnode->sysctl_data; 195 node.sysctl_data = &t; 196 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 197 if (error || newp == NULL) 198 return (error); 199 200 if (t < lower || t > upper) 201 return (EINVAL); 202 203 *(int*)rnode->sysctl_data = t; 204 205 return (0); 206 } 207 208 static int 209 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 210 { 211 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 212 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 213 } 214 215 static int 216 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 217 { 218 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 219 } 220 221 #ifdef RTW_DEBUG 222 static int 223 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 224 { 225 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 226 0, RTW_DEBUG_MAX); 227 } 228 229 static int 230 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 231 { 232 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 233 0, RTW_RXQLEN); 234 } 235 236 static void 237 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 238 { 239 #define PRINTREG32(sc, reg) \ 240 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 241 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 242 dvname, reg, RTW_READ(regs, reg))) 243 244 #define PRINTREG16(sc, reg) \ 245 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 246 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 247 dvname, reg, RTW_READ16(regs, reg))) 248 249 #define PRINTREG8(sc, reg) \ 250 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 251 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 252 dvname, reg, RTW_READ8(regs, reg))) 253 254 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 255 256 PRINTREG32(regs, RTW_IDR0); 257 PRINTREG32(regs, RTW_IDR1); 258 PRINTREG32(regs, RTW_MAR0); 259 PRINTREG32(regs, RTW_MAR1); 260 PRINTREG32(regs, RTW_TSFTRL); 261 PRINTREG32(regs, RTW_TSFTRH); 262 PRINTREG32(regs, RTW_TLPDA); 263 PRINTREG32(regs, RTW_TNPDA); 264 PRINTREG32(regs, RTW_THPDA); 265 PRINTREG32(regs, RTW_TCR); 266 PRINTREG32(regs, RTW_RCR); 267 PRINTREG32(regs, RTW_TINT); 268 PRINTREG32(regs, RTW_TBDA); 269 PRINTREG32(regs, RTW_ANAPARM); 270 PRINTREG32(regs, RTW_BB); 271 PRINTREG32(regs, RTW_PHYCFG); 272 PRINTREG32(regs, RTW_WAKEUP0L); 273 PRINTREG32(regs, RTW_WAKEUP0H); 274 PRINTREG32(regs, RTW_WAKEUP1L); 275 PRINTREG32(regs, RTW_WAKEUP1H); 276 PRINTREG32(regs, RTW_WAKEUP2LL); 277 PRINTREG32(regs, RTW_WAKEUP2LH); 278 PRINTREG32(regs, RTW_WAKEUP2HL); 279 PRINTREG32(regs, RTW_WAKEUP2HH); 280 PRINTREG32(regs, RTW_WAKEUP3LL); 281 PRINTREG32(regs, RTW_WAKEUP3LH); 282 PRINTREG32(regs, RTW_WAKEUP3HL); 283 PRINTREG32(regs, RTW_WAKEUP3HH); 284 PRINTREG32(regs, RTW_WAKEUP4LL); 285 PRINTREG32(regs, RTW_WAKEUP4LH); 286 PRINTREG32(regs, RTW_WAKEUP4HL); 287 PRINTREG32(regs, RTW_WAKEUP4HH); 288 PRINTREG32(regs, RTW_DK0); 289 PRINTREG32(regs, RTW_DK1); 290 PRINTREG32(regs, RTW_DK2); 291 PRINTREG32(regs, RTW_DK3); 292 PRINTREG32(regs, RTW_RETRYCTR); 293 PRINTREG32(regs, RTW_RDSAR); 294 PRINTREG32(regs, RTW_FER); 295 PRINTREG32(regs, RTW_FEMR); 296 PRINTREG32(regs, RTW_FPSR); 297 PRINTREG32(regs, RTW_FFER); 298 299 /* 16-bit registers */ 300 PRINTREG16(regs, RTW_BRSR); 301 PRINTREG16(regs, RTW_IMR); 302 PRINTREG16(regs, RTW_ISR); 303 PRINTREG16(regs, RTW_BCNITV); 304 PRINTREG16(regs, RTW_ATIMWND); 305 PRINTREG16(regs, RTW_BINTRITV); 306 PRINTREG16(regs, RTW_ATIMTRITV); 307 PRINTREG16(regs, RTW_CRC16ERR); 308 PRINTREG16(regs, RTW_CRC0); 309 PRINTREG16(regs, RTW_CRC1); 310 PRINTREG16(regs, RTW_CRC2); 311 PRINTREG16(regs, RTW_CRC3); 312 PRINTREG16(regs, RTW_CRC4); 313 PRINTREG16(regs, RTW_CWR); 314 315 /* 8-bit registers */ 316 PRINTREG8(regs, RTW_CR); 317 PRINTREG8(regs, RTW_9346CR); 318 PRINTREG8(regs, RTW_CONFIG0); 319 PRINTREG8(regs, RTW_CONFIG1); 320 PRINTREG8(regs, RTW_CONFIG2); 321 PRINTREG8(regs, RTW_MSR); 322 PRINTREG8(regs, RTW_CONFIG3); 323 PRINTREG8(regs, RTW_CONFIG4); 324 PRINTREG8(regs, RTW_TESTR); 325 PRINTREG8(regs, RTW_PSR); 326 PRINTREG8(regs, RTW_SCR); 327 PRINTREG8(regs, RTW_PHYDELAY); 328 PRINTREG8(regs, RTW_CRCOUNT); 329 PRINTREG8(regs, RTW_PHYADDR); 330 PRINTREG8(regs, RTW_PHYDATAW); 331 PRINTREG8(regs, RTW_PHYDATAR); 332 PRINTREG8(regs, RTW_CONFIG5); 333 PRINTREG8(regs, RTW_TPPOLL); 334 335 PRINTREG16(regs, RTW_BSSID16); 336 PRINTREG32(regs, RTW_BSSID32); 337 #undef PRINTREG32 338 #undef PRINTREG16 339 #undef PRINTREG8 340 } 341 #endif /* RTW_DEBUG */ 342 343 void 344 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 345 { 346 struct rtw_regs *regs = &sc->sc_regs; 347 348 uint32_t tcr; 349 tcr = RTW_READ(regs, RTW_TCR); 350 tcr &= ~RTW_TCR_LBK_MASK; 351 if (enable) 352 tcr |= RTW_TCR_LBK_CONT; 353 else 354 tcr |= RTW_TCR_LBK_NORMAL; 355 RTW_WRITE(regs, RTW_TCR, tcr); 356 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 357 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 358 rtw_txdac_enable(sc, !enable); 359 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 360 rtw_set_access(regs, RTW_ACCESS_NONE); 361 } 362 363 #ifdef RTW_DEBUG 364 static const char * 365 rtw_access_string(enum rtw_access access) 366 { 367 switch (access) { 368 case RTW_ACCESS_NONE: 369 return "none"; 370 case RTW_ACCESS_CONFIG: 371 return "config"; 372 case RTW_ACCESS_ANAPARM: 373 return "anaparm"; 374 default: 375 return "unknown"; 376 } 377 } 378 #endif /* RTW_DEBUG */ 379 380 static void 381 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 382 { 383 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 384 KASSERT(regs->r_access >= RTW_ACCESS_NONE && 385 regs->r_access <= RTW_ACCESS_ANAPARM); 386 387 if (naccess == regs->r_access) 388 return; 389 390 switch (naccess) { 391 case RTW_ACCESS_NONE: 392 switch (regs->r_access) { 393 case RTW_ACCESS_ANAPARM: 394 rtw_anaparm_enable(regs, 0); 395 /*FALLTHROUGH*/ 396 case RTW_ACCESS_CONFIG: 397 rtw_config0123_enable(regs, 0); 398 /*FALLTHROUGH*/ 399 case RTW_ACCESS_NONE: 400 break; 401 } 402 break; 403 case RTW_ACCESS_CONFIG: 404 switch (regs->r_access) { 405 case RTW_ACCESS_NONE: 406 rtw_config0123_enable(regs, 1); 407 /*FALLTHROUGH*/ 408 case RTW_ACCESS_CONFIG: 409 break; 410 case RTW_ACCESS_ANAPARM: 411 rtw_anaparm_enable(regs, 0); 412 break; 413 } 414 break; 415 case RTW_ACCESS_ANAPARM: 416 switch (regs->r_access) { 417 case RTW_ACCESS_NONE: 418 rtw_config0123_enable(regs, 1); 419 /*FALLTHROUGH*/ 420 case RTW_ACCESS_CONFIG: 421 rtw_anaparm_enable(regs, 1); 422 /*FALLTHROUGH*/ 423 case RTW_ACCESS_ANAPARM: 424 break; 425 } 426 break; 427 } 428 } 429 430 void 431 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 432 { 433 rtw_set_access1(regs, access); 434 RTW_DPRINTF(RTW_DEBUG_ACCESS, 435 ("%s: access %s -> %s\n", __func__, 436 rtw_access_string(regs->r_access), 437 rtw_access_string(access))); 438 regs->r_access = access; 439 } 440 441 /* 442 * Enable registers, switch register banks. 443 */ 444 void 445 rtw_config0123_enable(struct rtw_regs *regs, int enable) 446 { 447 uint8_t ecr; 448 ecr = RTW_READ8(regs, RTW_9346CR); 449 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 450 if (enable) 451 ecr |= RTW_9346CR_EEM_CONFIG; 452 else { 453 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 454 ecr |= RTW_9346CR_EEM_NORMAL; 455 } 456 RTW_WRITE8(regs, RTW_9346CR, ecr); 457 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 458 } 459 460 /* requires rtw_config0123_enable(, 1) */ 461 void 462 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 463 { 464 uint8_t cfg3; 465 466 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 467 cfg3 |= RTW_CONFIG3_CLKRUNEN; 468 if (enable) 469 cfg3 |= RTW_CONFIG3_PARMEN; 470 else 471 cfg3 &= ~RTW_CONFIG3_PARMEN; 472 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 473 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 474 } 475 476 /* requires rtw_anaparm_enable(, 1) */ 477 void 478 rtw_txdac_enable(struct rtw_softc *sc, int enable) 479 { 480 uint32_t anaparm; 481 struct rtw_regs *regs = &sc->sc_regs; 482 483 anaparm = RTW_READ(regs, RTW_ANAPARM); 484 if (enable) 485 anaparm &= ~RTW_ANAPARM_TXDACOFF; 486 else 487 anaparm |= RTW_ANAPARM_TXDACOFF; 488 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 489 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 490 } 491 492 static __inline int 493 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 494 { 495 uint8_t cr; 496 int i; 497 498 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 499 500 RTW_WBR(regs, RTW_CR, RTW_CR); 501 502 for (i = 0; i < 1000; i++) { 503 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 504 RTW_DPRINTF(RTW_DEBUG_RESET, 505 ("%s: reset in %dus\n", dvname, i)); 506 return 0; 507 } 508 RTW_RBR(regs, RTW_CR, RTW_CR); 509 DELAY(10); /* 10us */ 510 } 511 512 printf("%s: reset failed\n", dvname); 513 return ETIMEDOUT; 514 } 515 516 static __inline int 517 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 518 { 519 uint32_t tcr; 520 521 /* from Linux driver */ 522 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 523 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 524 525 RTW_WRITE(regs, RTW_TCR, tcr); 526 527 RTW_WBW(regs, RTW_CR, RTW_TCR); 528 529 return rtw_chip_reset1(regs, dvname); 530 } 531 532 static int 533 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int force) 534 { 535 struct ieee80211_key keycopy; 536 537 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 538 539 keycopy = *k; 540 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 541 542 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, force); 543 } 544 545 static int 546 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 547 { 548 struct rtw_softc *sc = ic->ic_ifp->if_softc; 549 u_int keyix = k->wk_keyix; 550 551 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix)); 552 553 if (keyix >= IEEE80211_WEP_NKID) 554 return 0; 555 if (k->wk_keylen != 0) 556 sc->sc_flags &= ~RTW_F_DK_VALID; 557 558 return 1; 559 } 560 561 static int 562 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 563 const u_int8_t mac[IEEE80211_ADDR_LEN]) 564 { 565 struct rtw_softc *sc = ic->ic_ifp->if_softc; 566 567 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 568 569 if (k->wk_keyix >= IEEE80211_WEP_NKID) 570 return 0; 571 572 if (k->wk_cipher == &ieee80211_cipher_wep) { 573 rtw_cipher_wep = ieee80211_cipher_wep; 574 rtw_cipher_wep.ic_decap = rtw_wep_decap; 575 ic->ic_nw_keys[k->wk_keyix].wk_cipher = &rtw_cipher_wep; 576 } 577 sc->sc_flags &= ~RTW_F_DK_VALID; 578 579 return 1; 580 } 581 582 static void 583 rtw_key_update_begin(struct ieee80211com *ic) 584 { 585 #ifdef RTW_DEBUG 586 struct ifnet *ifp = ic->ic_ifp; 587 struct rtw_softc *sc = ifp->if_softc; 588 #endif 589 590 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 591 } 592 593 static void 594 rtw_key_update_end(struct ieee80211com *ic) 595 { 596 struct ifnet *ifp = ic->ic_ifp; 597 struct rtw_softc *sc = ifp->if_softc; 598 599 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 600 601 if ((sc->sc_flags & RTW_F_DK_VALID) != 0) 602 return; 603 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 604 return; 605 606 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 607 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 608 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 609 (ifp->if_flags & IFF_RUNNING) != 0); 610 } 611 612 static void 613 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 614 { 615 uint8_t cfg0, psr, scr; 616 int i, tx_key_len; 617 struct rtw_regs *regs; 618 union rtw_keys *rk; 619 620 regs = &sc->sc_regs; 621 rk = &sc->sc_keys; 622 623 (void)memset(rk->rk_keys, 0, sizeof(rk->rk_keys)); 624 625 rtw_set_access(regs, RTW_ACCESS_CONFIG); 626 627 psr = RTW_READ8(regs, RTW_PSR); 628 scr = RTW_READ8(regs, RTW_SCR); 629 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 630 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 631 cfg0 &= ~(RTW_CONFIG0_WEP104 | RTW_CONFIG0_WEP40); 632 633 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 634 goto out; 635 636 tx_key_len = wk[txkey].wk_keylen; 637 638 switch (tx_key_len) { 639 case 5: 640 scr |= RTW_SCR_RXSECON | RTW_SCR_KM_WEP40; 641 break; 642 case 13: 643 scr |= RTW_SCR_RXSECON | RTW_SCR_KM_WEP104; 644 break; 645 default: 646 goto out; 647 } 648 649 cfg0 |= RTW_CONFIG0_WEP104 | RTW_CONFIG0_WEP40; 650 651 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 652 if (wk[i].wk_keylen != tx_key_len) 653 continue; 654 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 655 } 656 657 out: 658 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 659 660 bus_space_write_region_4(regs->r_bt, regs->r_bh, 661 RTW_DK0, rk->rk_words, 662 sizeof(rk->rk_words) / sizeof(rk->rk_words[0])); 663 664 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 665 BUS_SPACE_BARRIER_SYNC); 666 667 printf("%s: psr = %#" PRIx8, sc->sc_dev.dv_xname, psr); 668 669 RTW_WRITE8(regs, RTW_PSR, psr); 670 671 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 672 RTW_WBW(regs, RTW_CONFIG0, RTW_SCR); 673 RTW_WRITE8(regs, RTW_SCR, scr); 674 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 675 rtw_set_access(regs, RTW_ACCESS_NONE); 676 sc->sc_flags |= RTW_F_DK_VALID; 677 } 678 679 static __inline int 680 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 681 { 682 int i; 683 uint8_t ecr; 684 685 ecr = RTW_READ8(regs, RTW_9346CR); 686 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 687 RTW_WRITE8(regs, RTW_9346CR, ecr); 688 689 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 690 691 /* wait 25ms for completion */ 692 for (i = 0; i < 250; i++) { 693 ecr = RTW_READ8(regs, RTW_9346CR); 694 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 695 RTW_DPRINTF(RTW_DEBUG_RESET, 696 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 697 return 0; 698 } 699 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 700 DELAY(100); 701 } 702 printf("%s: recall EEPROM failed\n", dvname); 703 return ETIMEDOUT; 704 } 705 706 static __inline int 707 rtw_reset(struct rtw_softc *sc) 708 { 709 int rc; 710 uint8_t config1; 711 712 sc->sc_flags &= ~RTW_F_DK_VALID; 713 714 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 715 return rc; 716 717 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 718 ; 719 720 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 721 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 722 /* TBD turn off maximum power saving? */ 723 724 return 0; 725 } 726 727 static __inline int 728 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 729 u_int ndescs) 730 { 731 int i, rc = 0; 732 for (i = 0; i < ndescs; i++) { 733 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 734 0, 0, &descs[i].ts_dmamap); 735 if (rc != 0) 736 break; 737 } 738 return rc; 739 } 740 741 static __inline int 742 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 743 u_int ndescs) 744 { 745 int i, rc = 0; 746 for (i = 0; i < ndescs; i++) { 747 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 748 &descs[i].rs_dmamap); 749 if (rc != 0) 750 break; 751 } 752 return rc; 753 } 754 755 static __inline void 756 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 757 u_int ndescs) 758 { 759 int i; 760 for (i = 0; i < ndescs; i++) { 761 if (descs[i].rs_dmamap != NULL) 762 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 763 } 764 } 765 766 static __inline void 767 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 768 u_int ndescs) 769 { 770 int i; 771 for (i = 0; i < ndescs; i++) { 772 if (descs[i].ts_dmamap != NULL) 773 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 774 } 775 } 776 777 static __inline void 778 rtw_srom_free(struct rtw_srom *sr) 779 { 780 sr->sr_size = 0; 781 if (sr->sr_content == NULL) 782 return; 783 free(sr->sr_content, M_DEVBUF); 784 sr->sr_content = NULL; 785 } 786 787 static void 788 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 789 enum rtw_rfchipid *rfchipid, uint32_t *rcr) 790 { 791 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 792 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 793 *rcr |= RTW_RCR_ENCS1; 794 *rfchipid = RTW_RFCHIPID_PHILIPS; 795 } 796 797 static int 798 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 799 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 800 const char *dvname) 801 { 802 int i; 803 const char *rfname, *paname; 804 char scratch[sizeof("unknown 0xXX")]; 805 uint16_t srom_version; 806 uint8_t mac[IEEE80211_ADDR_LEN]; 807 808 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 809 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 810 811 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 812 printf("%s: SROM version %d.%d", dvname, 813 srom_version >> 8, srom_version & 0xff); 814 815 if (srom_version <= 0x0101) { 816 printf(" is not understood, limping along with defaults\n"); 817 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 818 return 0; 819 } 820 printf("\n"); 821 822 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 823 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 824 825 RTW_DPRINTF(RTW_DEBUG_ATTACH, 826 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 827 828 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 829 830 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 831 *flags |= RTW_F_ANTDIV; 832 833 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 834 * to be reversed. 835 */ 836 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 837 *flags |= RTW_F_DIGPHY; 838 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 839 *flags |= RTW_F_DFLANTB; 840 841 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 842 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 843 844 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 845 switch (*rfchipid) { 846 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 847 rfname = "GCT GRF5101"; 848 paname = "Winspring WS9901"; 849 break; 850 case RTW_RFCHIPID_MAXIM: 851 rfname = "Maxim MAX2820"; /* guess */ 852 paname = "Maxim MAX2422"; /* guess */ 853 break; 854 case RTW_RFCHIPID_INTERSIL: 855 rfname = "Intersil HFA3873"; /* guess */ 856 paname = "Intersil <unknown>"; 857 break; 858 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 859 rfname = "Philips SA2400A"; 860 paname = "Philips SA2411"; 861 break; 862 case RTW_RFCHIPID_RFMD: 863 /* this is the same front-end as an atw(4)! */ 864 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 865 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 866 "SYN: Silicon Labs Si4126"; /* inferred from 867 * reference driver 868 */ 869 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 870 break; 871 case RTW_RFCHIPID_RESERVED: 872 rfname = paname = "reserved"; 873 break; 874 default: 875 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 876 rfname = paname = scratch; 877 } 878 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 879 880 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 881 case RTW_CONFIG0_GL_USA: 882 case _RTW_CONFIG0_GL_USA: 883 *locale = RTW_LOCALE_USA; 884 break; 885 case RTW_CONFIG0_GL_EUROPE: 886 *locale = RTW_LOCALE_EUROPE; 887 break; 888 case RTW_CONFIG0_GL_JAPAN: 889 *locale = RTW_LOCALE_JAPAN; 890 break; 891 default: 892 *locale = RTW_LOCALE_UNKNOWN; 893 break; 894 } 895 return 0; 896 } 897 898 /* Returns -1 on failure. */ 899 static int 900 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 901 const char *dvname) 902 { 903 int rc; 904 struct seeprom_descriptor sd; 905 uint8_t ecr; 906 907 (void)memset(&sd, 0, sizeof(sd)); 908 909 ecr = RTW_READ8(regs, RTW_9346CR); 910 911 if ((flags & RTW_F_9356SROM) != 0) { 912 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 913 sr->sr_size = 256; 914 sd.sd_chip = C56_66; 915 } else { 916 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 917 sr->sr_size = 128; 918 sd.sd_chip = C46; 919 } 920 921 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 922 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 923 ecr |= RTW_9346CR_EEM_PROGRAM; 924 925 RTW_WRITE8(regs, RTW_9346CR, ecr); 926 927 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 928 929 if (sr->sr_content == NULL) { 930 printf("%s: unable to allocate SROM buffer\n", dvname); 931 return ENOMEM; 932 } 933 934 (void)memset(sr->sr_content, 0, sr->sr_size); 935 936 /* RTL8180 has a single 8-bit register for controlling the 937 * 93cx6 SROM. There is no "ready" bit. The RTL8180 938 * input/output sense is the reverse of read_seeprom's. 939 */ 940 sd.sd_tag = regs->r_bt; 941 sd.sd_bsh = regs->r_bh; 942 sd.sd_regsize = 1; 943 sd.sd_control_offset = RTW_9346CR; 944 sd.sd_status_offset = RTW_9346CR; 945 sd.sd_dataout_offset = RTW_9346CR; 946 sd.sd_CK = RTW_9346CR_EESK; 947 sd.sd_CS = RTW_9346CR_EECS; 948 sd.sd_DI = RTW_9346CR_EEDO; 949 sd.sd_DO = RTW_9346CR_EEDI; 950 /* make read_seeprom enter EEPROM read/write mode */ 951 sd.sd_MS = ecr; 952 sd.sd_RDY = 0; 953 954 /* TBD bus barriers */ 955 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 956 printf("%s: could not read SROM\n", dvname); 957 free(sr->sr_content, M_DEVBUF); 958 sr->sr_content = NULL; 959 return -1; /* XXX */ 960 } 961 962 /* end EEPROM read/write mode */ 963 RTW_WRITE8(regs, RTW_9346CR, 964 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 965 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 966 967 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 968 return rc; 969 970 #ifdef RTW_DEBUG 971 { 972 int i; 973 RTW_DPRINTF(RTW_DEBUG_ATTACH, 974 ("\n%s: serial ROM:\n\t", dvname)); 975 for (i = 0; i < sr->sr_size/2; i++) { 976 if (((i % 8) == 0) && (i != 0)) 977 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 978 RTW_DPRINTF(RTW_DEBUG_ATTACH, 979 (" %04x", sr->sr_content[i])); 980 } 981 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 982 } 983 #endif /* RTW_DEBUG */ 984 return 0; 985 } 986 987 static void 988 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 989 const char *dvname) 990 { 991 uint8_t cfg4; 992 const char *method; 993 994 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 995 996 switch (rfchipid) { 997 default: 998 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 999 method = "fallback"; 1000 break; 1001 case RTW_RFCHIPID_INTERSIL: 1002 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1003 method = "Intersil"; 1004 break; 1005 case RTW_RFCHIPID_PHILIPS: 1006 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1007 method = "Philips"; 1008 break; 1009 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1010 case RTW_RFCHIPID_RFMD: 1011 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1012 method = "RFMD"; 1013 break; 1014 } 1015 1016 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1017 1018 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1019 1020 RTW_DPRINTF(RTW_DEBUG_INIT, 1021 ("%s: %s RF programming method, %#02x\n", dvname, method, 1022 RTW_READ8(regs, RTW_CONFIG4))); 1023 } 1024 1025 static __inline void 1026 rtw_init_channels(enum rtw_locale locale, 1027 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 1028 const char *dvname) 1029 { 1030 int i; 1031 const char *name = NULL; 1032 #define ADD_CHANNEL(_chans, _chan) do { \ 1033 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1034 (*_chans)[_chan].ic_freq = \ 1035 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1036 } while (0) 1037 1038 switch (locale) { 1039 case RTW_LOCALE_USA: /* 1-11 */ 1040 name = "USA"; 1041 for (i = 1; i <= 11; i++) 1042 ADD_CHANNEL(chans, i); 1043 break; 1044 case RTW_LOCALE_JAPAN: /* 1-14 */ 1045 name = "Japan"; 1046 ADD_CHANNEL(chans, 14); 1047 for (i = 1; i <= 14; i++) 1048 ADD_CHANNEL(chans, i); 1049 break; 1050 case RTW_LOCALE_EUROPE: /* 1-13 */ 1051 name = "Europe"; 1052 for (i = 1; i <= 13; i++) 1053 ADD_CHANNEL(chans, i); 1054 break; 1055 default: /* 10-11 allowed by most countries */ 1056 name = "<unknown>"; 1057 for (i = 10; i <= 11; i++) 1058 ADD_CHANNEL(chans, i); 1059 break; 1060 } 1061 printf("%s: Geographic Location %s\n", dvname, name); 1062 #undef ADD_CHANNEL 1063 } 1064 1065 static __inline void 1066 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 1067 const char *dvname) 1068 { 1069 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1070 1071 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1072 case RTW_CONFIG0_GL_USA: 1073 case _RTW_CONFIG0_GL_USA: 1074 *locale = RTW_LOCALE_USA; 1075 break; 1076 case RTW_CONFIG0_GL_JAPAN: 1077 *locale = RTW_LOCALE_JAPAN; 1078 break; 1079 case RTW_CONFIG0_GL_EUROPE: 1080 *locale = RTW_LOCALE_EUROPE; 1081 break; 1082 default: 1083 *locale = RTW_LOCALE_UNKNOWN; 1084 break; 1085 } 1086 } 1087 1088 static __inline int 1089 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1090 const char *dvname) 1091 { 1092 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1093 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1094 }; 1095 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1096 idr1 = RTW_READ(regs, RTW_IDR1); 1097 1098 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 1099 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 1100 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 1101 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 1102 1103 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 1104 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 1105 1106 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1107 printf("%s: could not get mac address, attach failed\n", 1108 dvname); 1109 return ENXIO; 1110 } 1111 1112 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 1113 1114 return 0; 1115 } 1116 1117 static uint8_t 1118 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1119 struct ieee80211_channel *chan) 1120 { 1121 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1122 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 1123 ("%s: channel %d out of range", __func__, 1124 idx - RTW_SR_TXPOWER1 + 1)); 1125 return RTW_SR_GET(sr, idx); 1126 } 1127 1128 static void 1129 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1130 { 1131 int pri; 1132 u_int ndesc[RTW_NTXPRI] = 1133 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 1134 1135 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1136 tdb[pri].tdb_nfree = ndesc[pri]; 1137 tdb[pri].tdb_next = 0; 1138 } 1139 } 1140 1141 static int 1142 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1143 { 1144 int i; 1145 struct rtw_txsoft *ts; 1146 1147 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1148 SIMPLEQ_INIT(&tsb->tsb_freeq); 1149 for (i = 0; i < tsb->tsb_ndesc; i++) { 1150 ts = &tsb->tsb_desc[i]; 1151 ts->ts_mbuf = NULL; 1152 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1153 } 1154 return 0; 1155 } 1156 1157 static void 1158 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1159 { 1160 int pri; 1161 for (pri = 0; pri < RTW_NTXPRI; pri++) 1162 rtw_txsoft_blk_init(&tsb[pri]); 1163 } 1164 1165 static __inline void 1166 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1167 { 1168 KASSERT(nsync <= rdb->rdb_ndesc); 1169 /* sync to end of ring */ 1170 if (desc0 + nsync > rdb->rdb_ndesc) { 1171 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1172 offsetof(struct rtw_descs, hd_rx[desc0]), 1173 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1174 nsync -= (rdb->rdb_ndesc - desc0); 1175 desc0 = 0; 1176 } 1177 1178 KASSERT(desc0 < rdb->rdb_ndesc); 1179 KASSERT(nsync <= rdb->rdb_ndesc); 1180 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1181 1182 /* sync what remains */ 1183 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1184 offsetof(struct rtw_descs, hd_rx[desc0]), 1185 sizeof(struct rtw_rxdesc) * nsync, ops); 1186 } 1187 1188 static void 1189 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1190 { 1191 /* sync to end of ring */ 1192 if (desc0 + nsync > tdb->tdb_ndesc) { 1193 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1194 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1195 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1196 ops); 1197 nsync -= (tdb->tdb_ndesc - desc0); 1198 desc0 = 0; 1199 } 1200 1201 /* sync what remains */ 1202 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1203 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1204 sizeof(struct rtw_txdesc) * nsync, ops); 1205 } 1206 1207 static void 1208 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1209 { 1210 int pri; 1211 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1212 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1213 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1214 } 1215 } 1216 1217 static void 1218 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1219 { 1220 int i; 1221 struct rtw_rxsoft *rs; 1222 1223 for (i = 0; i < RTW_RXQLEN; i++) { 1224 rs = &desc[i]; 1225 if (rs->rs_mbuf == NULL) 1226 continue; 1227 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1228 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1229 bus_dmamap_unload(dmat, rs->rs_dmamap); 1230 m_freem(rs->rs_mbuf); 1231 rs->rs_mbuf = NULL; 1232 } 1233 } 1234 1235 static __inline int 1236 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1237 { 1238 int rc; 1239 struct mbuf *m; 1240 1241 MGETHDR(m, M_DONTWAIT, MT_DATA); 1242 if (m == NULL) 1243 return ENOBUFS; 1244 1245 MCLGET(m, M_DONTWAIT); 1246 if ((m->m_flags & M_EXT) == 0) { 1247 m_freem(m); 1248 return ENOBUFS; 1249 } 1250 1251 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1252 1253 if (rs->rs_mbuf != NULL) 1254 bus_dmamap_unload(dmat, rs->rs_dmamap); 1255 1256 rs->rs_mbuf = NULL; 1257 1258 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1259 if (rc != 0) { 1260 m_freem(m); 1261 return -1; 1262 } 1263 1264 rs->rs_mbuf = m; 1265 1266 return 0; 1267 } 1268 1269 static int 1270 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1271 int *ndesc, const char *dvname) 1272 { 1273 int i, rc = 0; 1274 struct rtw_rxsoft *rs; 1275 1276 for (i = 0; i < RTW_RXQLEN; i++) { 1277 rs = &desc[i]; 1278 /* we're in rtw_init, so there should be no mbufs allocated */ 1279 KASSERT(rs->rs_mbuf == NULL); 1280 #ifdef RTW_DEBUG 1281 if (i == rtw_rxbufs_limit) { 1282 printf("%s: TEST hit %d-buffer limit\n", dvname, i); 1283 rc = ENOBUFS; 1284 break; 1285 } 1286 #endif /* RTW_DEBUG */ 1287 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1288 printf("%s: rtw_rxsoft_alloc failed, %d buffers, " 1289 "rc %d\n", dvname, i, rc); 1290 break; 1291 } 1292 } 1293 *ndesc = i; 1294 return rc; 1295 } 1296 1297 static __inline void 1298 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1299 int idx, int kick) 1300 { 1301 int is_last = (idx == rdb->rdb_ndesc - 1); 1302 uint32_t ctl, octl, obuf; 1303 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1304 1305 obuf = rd->rd_buf; 1306 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1307 1308 ctl = LSHIFT(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1309 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1310 1311 if (is_last) 1312 ctl |= RTW_RXCTL_EOR; 1313 1314 octl = rd->rd_ctl; 1315 rd->rd_ctl = htole32(ctl); 1316 1317 RTW_DPRINTF( 1318 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1319 : RTW_DEBUG_RECV_DESC, 1320 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1321 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1322 le32toh(rd->rd_ctl))); 1323 1324 /* sync the mbuf */ 1325 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1326 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1327 1328 /* sync the descriptor */ 1329 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1330 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1331 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1332 } 1333 1334 static void 1335 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1336 { 1337 int i; 1338 struct rtw_rxdesc *rd; 1339 struct rtw_rxsoft *rs; 1340 1341 for (i = 0; i < rdb->rdb_ndesc; i++) { 1342 rd = &rdb->rdb_desc[i]; 1343 rs = &ctl[i]; 1344 rtw_rxdesc_init(rdb, rs, i, kick); 1345 } 1346 rdb->rdb_next = 0; 1347 } 1348 1349 static void 1350 rtw_io_enable(struct rtw_regs *regs, uint8_t flags, int enable) 1351 { 1352 uint8_t cr; 1353 1354 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1355 enable ? "enable" : "disable", flags)); 1356 1357 cr = RTW_READ8(regs, RTW_CR); 1358 1359 /* XXX reference source does not enable MULRW */ 1360 #if 0 1361 /* enable PCI Read/Write Multiple */ 1362 cr |= RTW_CR_MULRW; 1363 #endif 1364 1365 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1366 if (enable) 1367 cr |= flags; 1368 else 1369 cr &= ~flags; 1370 RTW_WRITE8(regs, RTW_CR, cr); 1371 RTW_SYNC(regs, RTW_CR, RTW_CR); 1372 } 1373 1374 static void 1375 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1376 { 1377 #define IS_BEACON(__fc0) \ 1378 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1379 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1380 1381 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1382 * hardware -> net80211 1383 */ 1384 u_int next, nproc = 0; 1385 int hwrate, len, rate, rssi, sq; 1386 uint32_t hrssi, hstat, htsfth, htsftl; 1387 struct rtw_rxdesc *rd; 1388 struct rtw_rxsoft *rs; 1389 struct rtw_rxdesc_blk *rdb; 1390 struct mbuf *m; 1391 struct ifnet *ifp = &sc->sc_if; 1392 1393 struct ieee80211_node *ni; 1394 struct ieee80211_frame_min *wh; 1395 1396 rdb = &sc->sc_rxdesc_blk; 1397 1398 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1399 1400 for (next = rdb->rdb_next; ; next = (next + 1) % rdb->rdb_ndesc) { 1401 rtw_rxdescs_sync(rdb, next, 1, 1402 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1403 rd = &rdb->rdb_desc[next]; 1404 rs = &sc->sc_rxsoft[next]; 1405 1406 hstat = le32toh(rd->rd_stat); 1407 hrssi = le32toh(rd->rd_rssi); 1408 htsfth = le32toh(rd->rd_tsfth); 1409 htsftl = le32toh(rd->rd_tsftl); 1410 1411 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1412 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1413 __func__, next, hstat, hrssi, htsfth, htsftl)); 1414 1415 ++nproc; 1416 1417 /* still belongs to NIC */ 1418 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1419 if (nproc > 1) 1420 break; 1421 1422 /* sometimes the NIC skips to the 0th descriptor */ 1423 rtw_rxdescs_sync(rdb, 0, 1, 1424 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1425 rd = &rdb->rdb_desc[0]; 1426 if ((rd->rd_stat & htole32(RTW_RXSTAT_OWN)) != 0) 1427 break; 1428 RTW_DPRINTF(RTW_DEBUG_BUGS, 1429 ("%s: NIC skipped from rxdesc[%u] to rxdesc[0]\n", 1430 sc->sc_dev.dv_xname, next)); 1431 next = rdb->rdb_ndesc - 1; 1432 continue; 1433 } 1434 1435 #ifdef RTW_DEBUG 1436 #define PRINTSTAT(flag) do { \ 1437 if ((hstat & flag) != 0) { \ 1438 printf("%s" #flag, delim); \ 1439 delim = ","; \ 1440 } \ 1441 } while (0) 1442 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1443 const char *delim = "<"; 1444 printf("%s: ", sc->sc_dev.dv_xname); 1445 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1446 printf("status %08x", hstat); 1447 PRINTSTAT(RTW_RXSTAT_SPLCP); 1448 PRINTSTAT(RTW_RXSTAT_MAR); 1449 PRINTSTAT(RTW_RXSTAT_PAR); 1450 PRINTSTAT(RTW_RXSTAT_BAR); 1451 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1452 PRINTSTAT(RTW_RXSTAT_CRC32); 1453 PRINTSTAT(RTW_RXSTAT_ICV); 1454 printf(">, "); 1455 } 1456 } 1457 #endif /* RTW_DEBUG */ 1458 1459 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1460 printf("%s: DMA error/FIFO overflow %08x, " 1461 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1462 hstat & RTW_RXSTAT_IOERROR, next); 1463 ifp->if_ierrors++; 1464 goto next; 1465 } 1466 1467 len = MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1468 if (len < IEEE80211_MIN_LEN) { 1469 sc->sc_ic.ic_stats.is_rx_tooshort++; 1470 goto next; 1471 } 1472 1473 /* CRC is included with the packet; trim it off. */ 1474 len -= IEEE80211_CRC_LEN; 1475 1476 hwrate = MASK_AND_RSHIFT(hstat, RTW_RXSTAT_RATE_MASK); 1477 if (hwrate >= sizeof(ratetbl) / sizeof(ratetbl[0])) { 1478 printf("%s: unknown rate #%d\n", sc->sc_dev.dv_xname, 1479 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_RATE_MASK)); 1480 ifp->if_ierrors++; 1481 goto next; 1482 } 1483 rate = ratetbl[hwrate]; 1484 1485 #ifdef RTW_DEBUG 1486 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1487 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1488 (rate * 5) % 10, htsfth, htsftl)); 1489 #endif /* RTW_DEBUG */ 1490 1491 if ((hstat & RTW_RXSTAT_RES) != 0 && 1492 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1493 goto next; 1494 1495 /* if bad flags, skip descriptor */ 1496 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1497 printf("%s: too many rx segments\n", 1498 sc->sc_dev.dv_xname); 1499 goto next; 1500 } 1501 1502 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1503 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1504 1505 m = rs->rs_mbuf; 1506 1507 /* if temporarily out of memory, re-use mbuf */ 1508 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1509 case 0: 1510 break; 1511 case ENOBUFS: 1512 printf("%s: rtw_rxsoft_alloc(, %d) failed, " 1513 "dropping packet\n", sc->sc_dev.dv_xname, next); 1514 goto next; 1515 default: 1516 /* XXX shorten rx ring, instead? */ 1517 panic("%s: could not load DMA map\n", 1518 sc->sc_dev.dv_xname); 1519 } 1520 1521 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1522 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1523 else { 1524 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1525 /* TBD find out each front-end's LNA gain in the 1526 * front-end's units 1527 */ 1528 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1529 rssi |= 0x80; 1530 } 1531 sq = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_SQ); 1532 1533 /* Note well: now we cannot recycle the rs_mbuf unless 1534 * we restore its original length. 1535 */ 1536 m->m_pkthdr.rcvif = ifp; 1537 m->m_pkthdr.len = m->m_len = len; 1538 1539 wh = mtod(m, struct ieee80211_frame_min *); 1540 1541 if (!IS_BEACON(wh->i_fc[0])) 1542 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1543 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1544 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1545 1546 sc->sc_tsfth = htsfth; 1547 1548 #ifdef RTW_DEBUG 1549 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 1550 (IFF_DEBUG|IFF_LINK2)) { 1551 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1552 rate, rssi); 1553 } 1554 #endif /* RTW_DEBUG */ 1555 1556 #if NBPFILTER > 0 1557 if (sc->sc_radiobpf != NULL) { 1558 struct ieee80211com *ic = &sc->sc_ic; 1559 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1560 1561 rr->rr_tsft = 1562 htole64(((uint64_t)htsfth << 32) | htsftl); 1563 1564 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1565 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE; 1566 1567 rr->rr_flags = 0; 1568 rr->rr_rate = rate; 1569 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1570 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1571 rr->rr_antsignal = rssi; 1572 rr->rr_barker_lock = htole16(sq); 1573 1574 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rr, 1575 sizeof(sc->sc_rxtapu), m); 1576 } 1577 #endif /* NPBFILTER > 0 */ 1578 1579 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1580 ieee80211_free_node(ni); 1581 next: 1582 rtw_rxdesc_init(rdb, rs, next, 0); 1583 } 1584 rdb->rdb_next = next; 1585 1586 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1587 1588 return; 1589 #undef IS_BEACON 1590 } 1591 1592 static void 1593 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1594 struct rtw_txsoft *ts) 1595 { 1596 struct mbuf *m; 1597 struct ieee80211_node *ni; 1598 1599 m = ts->ts_mbuf; 1600 ni = ts->ts_ni; 1601 KASSERT(m != NULL); 1602 KASSERT(ni != NULL); 1603 ts->ts_mbuf = NULL; 1604 ts->ts_ni = NULL; 1605 1606 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1607 BUS_DMASYNC_POSTWRITE); 1608 bus_dmamap_unload(dmat, ts->ts_dmamap); 1609 m_freem(m); 1610 ieee80211_free_node(ni); 1611 } 1612 1613 static void 1614 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1615 struct rtw_txsoft_blk *tsb) 1616 { 1617 struct rtw_txsoft *ts; 1618 1619 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1620 rtw_txsoft_release(dmat, ic, ts); 1621 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1622 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1623 } 1624 } 1625 1626 static __inline void 1627 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1628 struct rtw_txsoft *ts, int ndesc) 1629 { 1630 uint32_t hstat; 1631 int data_retry, rts_retry; 1632 struct rtw_txdesc *tdn; 1633 const char *condstring; 1634 struct ifnet *ifp = &sc->sc_if; 1635 1636 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1637 1638 tdb->tdb_nfree += ndesc; 1639 1640 tdn = &tdb->tdb_desc[ts->ts_last]; 1641 1642 hstat = le32toh(tdn->td_stat); 1643 rts_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1644 data_retry = MASK_AND_RSHIFT(hstat, RTW_TXSTAT_DRC_MASK); 1645 1646 ifp->if_collisions += rts_retry + data_retry; 1647 1648 if ((hstat & RTW_TXSTAT_TOK) != 0) 1649 condstring = "ok"; 1650 else { 1651 ifp->if_oerrors++; 1652 condstring = "error"; 1653 } 1654 1655 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1656 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1657 sc->sc_dev.dv_xname, ts, ts->ts_first, ts->ts_last, 1658 condstring, rts_retry, data_retry)); 1659 } 1660 1661 /* Collect transmitted packets. */ 1662 static __inline void 1663 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1664 struct rtw_txdesc_blk *tdb) 1665 { 1666 int ndesc; 1667 struct rtw_txsoft *ts; 1668 struct ifnet *ifp = &sc->sc_if; 1669 1670 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1671 ndesc = 1 + ts->ts_last - ts->ts_first; 1672 if (ts->ts_last < ts->ts_first) 1673 ndesc += tdb->tdb_ndesc; 1674 1675 KASSERT(ndesc > 0); 1676 1677 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1678 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1679 1680 if ((tdb->tdb_desc[ts->ts_last].td_stat & 1681 htole32(RTW_TXSTAT_OWN)) != 0) 1682 break; 1683 1684 if (&sc->sc_txdesc_blk[RTW_TXPRIBCN] == tdb) { 1685 RTW_DPRINTF(RTW_DEBUG_BEACON, 1686 ("%s: collected beacon\n", __func__)); 1687 } 1688 1689 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1690 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1691 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1692 ifp->if_flags &= ~IFF_OACTIVE; 1693 } 1694 if (ts == NULL) 1695 tsb->tsb_tx_timer = 0; 1696 } 1697 1698 static void 1699 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1700 { 1701 int pri; 1702 struct rtw_txsoft_blk *tsb; 1703 struct rtw_txdesc_blk *tdb; 1704 struct ifnet *ifp = &sc->sc_if; 1705 1706 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1707 tsb = &sc->sc_txsoft_blk[pri]; 1708 tdb = &sc->sc_txdesc_blk[pri]; 1709 1710 rtw_collect_txring(sc, tsb, tdb); 1711 1712 if ((isr & RTW_INTR_TX) != 0) 1713 rtw_start(ifp); 1714 } 1715 1716 /* TBD */ 1717 return; 1718 } 1719 1720 static void 1721 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1722 { 1723 /* TBD */ 1724 return; 1725 } 1726 1727 static void 1728 rtw_intr_atim(struct rtw_softc *sc) 1729 { 1730 /* TBD */ 1731 return; 1732 } 1733 1734 #ifdef RTW_DEBUG 1735 static void 1736 rtw_dump_rings(struct rtw_softc *sc) 1737 { 1738 struct rtw_txdesc_blk *tdb; 1739 struct rtw_rxdesc *rd; 1740 struct rtw_rxdesc_blk *rdb; 1741 int desc, pri; 1742 1743 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1744 return; 1745 1746 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1747 tdb = &sc->sc_txdesc_blk[pri]; 1748 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1749 tdb->tdb_ndesc, tdb->tdb_nfree); 1750 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1751 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1752 } 1753 1754 rdb = &sc->sc_rxdesc_blk; 1755 1756 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1757 rd = &rdb->rdb_desc[desc]; 1758 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1759 "rsvd1/tsfth %08x\n", __func__, 1760 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1761 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1762 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1763 } 1764 } 1765 #endif /* RTW_DEBUG */ 1766 1767 static void 1768 rtw_hwring_setup(struct rtw_softc *sc) 1769 { 1770 struct rtw_regs *regs = &sc->sc_regs; 1771 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1772 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1773 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1774 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1775 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1776 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1777 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1778 ("%s: reg[TLPDA] <- %" PRIxPTR "\n", __func__, 1779 (uintptr_t)RTW_RING_BASE(sc, hd_txlo))); 1780 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1781 ("%s: reg[TNPDA] <- %" PRIxPTR "\n", __func__, 1782 (uintptr_t)RTW_RING_BASE(sc, hd_txmd))); 1783 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1784 ("%s: reg[THPDA] <- %" PRIxPTR "\n", __func__, 1785 (uintptr_t)RTW_RING_BASE(sc, hd_txhi))); 1786 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1787 ("%s: reg[TBDA] <- %" PRIxPTR "\n", __func__, 1788 (uintptr_t)RTW_RING_BASE(sc, hd_bcn))); 1789 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1790 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1791 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1792 } 1793 1794 static int 1795 rtw_swring_setup(struct rtw_softc *sc) 1796 { 1797 int rc; 1798 struct rtw_rxdesc_blk *rdb; 1799 1800 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1801 1802 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1803 1804 rdb = &sc->sc_rxdesc_blk; 1805 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1806 sc->sc_dev.dv_xname)) != 0 && rdb->rdb_ndesc == 0) { 1807 printf("%s: could not allocate rx buffers\n", 1808 sc->sc_dev.dv_xname); 1809 return rc; 1810 } 1811 1812 rdb = &sc->sc_rxdesc_blk; 1813 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1814 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1815 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1816 1817 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1818 return 0; 1819 } 1820 1821 static void 1822 rtw_txdesc_blk_reset(struct rtw_txdesc_blk *tdb) 1823 { 1824 int i; 1825 1826 (void)memset(tdb->tdb_desc, 0, 1827 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 1828 for (i = 0; i < tdb->tdb_ndesc; i++) 1829 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 1830 tdb->tdb_nfree = tdb->tdb_ndesc; 1831 tdb->tdb_next = 0; 1832 } 1833 1834 static void 1835 rtw_txdescs_reset(struct rtw_softc *sc) 1836 { 1837 int pri; 1838 struct rtw_txdesc_blk *tdb; 1839 1840 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1841 tdb = &sc->sc_txdesc_blk[pri]; 1842 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 1843 &sc->sc_txsoft_blk[pri]); 1844 rtw_txdesc_blk_reset(tdb); 1845 rtw_txdescs_sync(tdb, 0, tdb->tdb_ndesc, 1846 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1847 } 1848 } 1849 1850 static void 1851 rtw_rxdescs_reset(struct rtw_softc *sc) 1852 { 1853 rtw_rxdesc_init_all(&sc->sc_rxdesc_blk, &sc->sc_rxsoft[0], 1); 1854 } 1855 1856 static void 1857 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 1858 { 1859 struct ifnet *ifp = &sc->sc_if; 1860 struct rtw_regs *regs = &sc->sc_regs; 1861 1862 if ((isr & RTW_INTR_TXFOVW) != 0) 1863 printf("%s: tx fifo overflow\n", sc->sc_dev.dv_xname); 1864 1865 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) == 0) 1866 return; 1867 1868 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: restarting xmit/recv, isr %" PRIx16 1869 "\n", sc->sc_dev.dv_xname, isr)); 1870 1871 #ifdef RTW_DEBUG 1872 rtw_dump_rings(sc); 1873 #endif /* RTW_DEBUG */ 1874 1875 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1876 1877 /* Collect rx'd packets. Refresh rx buffers. */ 1878 rtw_intr_rx(sc, 0); 1879 /* Collect tx'd packets. */ 1880 rtw_intr_tx(sc, 0); 1881 1882 RTW_WRITE16(regs, RTW_IMR, 0); 1883 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1884 1885 rtw_chip_reset1(regs, sc->sc_dev.dv_xname); 1886 rtw_wep_setkeys(sc, sc->sc_ic.ic_nw_keys, sc->sc_ic.ic_def_txkey); 1887 1888 rtw_rxdescs_reset(sc); 1889 rtw_txdescs_reset(sc); 1890 1891 rtw_hwring_setup(sc); 1892 1893 #ifdef RTW_DEBUG 1894 rtw_dump_rings(sc); 1895 #endif /* RTW_DEBUG */ 1896 1897 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1898 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1899 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1900 ifp->if_flags &= ~IFF_OACTIVE; 1901 } 1902 1903 static __inline void 1904 rtw_suspend_ticks(struct rtw_softc *sc) 1905 { 1906 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1907 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 1908 sc->sc_do_tick = 0; 1909 } 1910 1911 static __inline void 1912 rtw_resume_ticks(struct rtw_softc *sc) 1913 { 1914 uint32_t tsftrl0, tsftrl1, next_tick; 1915 1916 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1917 1918 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1919 next_tick = tsftrl1 + 1000000; 1920 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1921 1922 sc->sc_do_tick = 1; 1923 1924 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 1925 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1926 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 1927 } 1928 1929 static void 1930 rtw_intr_timeout(struct rtw_softc *sc) 1931 { 1932 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 1933 if (sc->sc_do_tick) 1934 rtw_resume_ticks(sc); 1935 return; 1936 } 1937 1938 int 1939 rtw_intr(void *arg) 1940 { 1941 int i; 1942 struct rtw_softc *sc = arg; 1943 struct rtw_regs *regs = &sc->sc_regs; 1944 uint16_t isr; 1945 struct ifnet *ifp = &sc->sc_if; 1946 1947 /* 1948 * If the interface isn't running, the interrupt couldn't 1949 * possibly have come from us. 1950 */ 1951 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1952 (ifp->if_flags & IFF_RUNNING) == 0 || 1953 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1954 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1955 return (0); 1956 } 1957 1958 for (i = 0; i < 10; i++) { 1959 isr = RTW_READ16(regs, RTW_ISR); 1960 1961 RTW_WRITE16(regs, RTW_ISR, isr); 1962 RTW_WBR(regs, RTW_ISR, RTW_ISR); 1963 1964 if (sc->sc_intr_ack != NULL) 1965 (*sc->sc_intr_ack)(regs); 1966 1967 if (isr == 0) 1968 break; 1969 1970 #ifdef RTW_DEBUG 1971 #define PRINTINTR(flag) do { \ 1972 if ((isr & flag) != 0) { \ 1973 printf("%s" #flag, delim); \ 1974 delim = ","; \ 1975 } \ 1976 } while (0) 1977 1978 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 1979 const char *delim = "<"; 1980 1981 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1982 1983 PRINTINTR(RTW_INTR_TXFOVW); 1984 PRINTINTR(RTW_INTR_TIMEOUT); 1985 PRINTINTR(RTW_INTR_BCNINT); 1986 PRINTINTR(RTW_INTR_ATIMINT); 1987 PRINTINTR(RTW_INTR_TBDER); 1988 PRINTINTR(RTW_INTR_TBDOK); 1989 PRINTINTR(RTW_INTR_THPDER); 1990 PRINTINTR(RTW_INTR_THPDOK); 1991 PRINTINTR(RTW_INTR_TNPDER); 1992 PRINTINTR(RTW_INTR_TNPDOK); 1993 PRINTINTR(RTW_INTR_RXFOVW); 1994 PRINTINTR(RTW_INTR_RDU); 1995 PRINTINTR(RTW_INTR_TLPDER); 1996 PRINTINTR(RTW_INTR_TLPDOK); 1997 PRINTINTR(RTW_INTR_RER); 1998 PRINTINTR(RTW_INTR_ROK); 1999 2000 printf(">\n"); 2001 } 2002 #undef PRINTINTR 2003 #endif /* RTW_DEBUG */ 2004 2005 if ((isr & RTW_INTR_RX) != 0) 2006 rtw_intr_rx(sc, isr & RTW_INTR_RX); 2007 if ((isr & RTW_INTR_TX) != 0) 2008 rtw_intr_tx(sc, isr & RTW_INTR_TX); 2009 if ((isr & RTW_INTR_BEACON) != 0) 2010 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 2011 if ((isr & RTW_INTR_ATIMINT) != 0) 2012 rtw_intr_atim(sc); 2013 if ((isr & RTW_INTR_IOERROR) != 0) 2014 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 2015 if ((isr & RTW_INTR_TIMEOUT) != 0) 2016 rtw_intr_timeout(sc); 2017 } 2018 2019 return 1; 2020 } 2021 2022 /* Must be called at splnet. */ 2023 static void 2024 rtw_stop(struct ifnet *ifp, int disable) 2025 { 2026 int pri; 2027 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2028 struct ieee80211com *ic = &sc->sc_ic; 2029 struct rtw_regs *regs = &sc->sc_regs; 2030 2031 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2032 return; 2033 2034 rtw_suspend_ticks(sc); 2035 2036 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2037 2038 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 2039 /* Disable interrupts. */ 2040 RTW_WRITE16(regs, RTW_IMR, 0); 2041 2042 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2043 2044 /* Stop the transmit and receive processes. First stop DMA, 2045 * then disable receiver and transmitter. 2046 */ 2047 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2048 2049 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2050 2051 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 2052 } 2053 2054 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2055 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2056 &sc->sc_txsoft_blk[pri]); 2057 } 2058 2059 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2060 2061 if (disable) 2062 rtw_disable(sc); 2063 2064 /* Mark the interface as not running. Cancel the watchdog timer. */ 2065 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2066 ifp->if_timer = 0; 2067 2068 return; 2069 } 2070 2071 const char * 2072 rtw_pwrstate_string(enum rtw_pwrstate power) 2073 { 2074 switch (power) { 2075 case RTW_ON: 2076 return "on"; 2077 case RTW_SLEEP: 2078 return "sleep"; 2079 case RTW_OFF: 2080 return "off"; 2081 default: 2082 return "unknown"; 2083 } 2084 } 2085 2086 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2087 * reference driver, plus a magic Maxim "ON" value that comes from 2088 * the Realtek document "Windows PG for Rtl8180." 2089 */ 2090 static void 2091 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2092 int before_rf, int digphy) 2093 { 2094 uint32_t anaparm; 2095 2096 anaparm = RTW_READ(regs, RTW_ANAPARM); 2097 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2098 2099 switch (power) { 2100 case RTW_OFF: 2101 if (before_rf) 2102 return; 2103 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2104 anaparm |= RTW_ANAPARM_TXDACOFF; 2105 break; 2106 case RTW_SLEEP: 2107 if (!before_rf) 2108 return; 2109 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2110 anaparm |= RTW_ANAPARM_TXDACOFF; 2111 break; 2112 case RTW_ON: 2113 if (!before_rf) 2114 return; 2115 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2116 break; 2117 } 2118 RTW_DPRINTF(RTW_DEBUG_PWR, 2119 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2120 __func__, rtw_pwrstate_string(power), 2121 (before_rf) ? "before" : "after", anaparm)); 2122 2123 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2124 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2125 } 2126 2127 /* XXX I am using the RFMD settings gleaned from the reference 2128 * driver. They agree 2129 */ 2130 static void 2131 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2132 int before_rf, int digphy) 2133 { 2134 uint32_t anaparm; 2135 2136 anaparm = RTW_READ(regs, RTW_ANAPARM); 2137 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2138 2139 switch (power) { 2140 case RTW_OFF: 2141 if (before_rf) 2142 return; 2143 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2144 anaparm |= RTW_ANAPARM_TXDACOFF; 2145 break; 2146 case RTW_SLEEP: 2147 if (!before_rf) 2148 return; 2149 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2150 anaparm |= RTW_ANAPARM_TXDACOFF; 2151 break; 2152 case RTW_ON: 2153 if (!before_rf) 2154 return; 2155 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2156 break; 2157 } 2158 RTW_DPRINTF(RTW_DEBUG_PWR, 2159 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2160 __func__, rtw_pwrstate_string(power), 2161 (before_rf) ? "before" : "after", anaparm)); 2162 2163 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2164 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2165 } 2166 2167 static void 2168 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2169 int before_rf, int digphy) 2170 { 2171 uint32_t anaparm; 2172 2173 anaparm = RTW_READ(regs, RTW_ANAPARM); 2174 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2175 2176 switch (power) { 2177 case RTW_OFF: 2178 if (before_rf) 2179 return; 2180 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2181 anaparm |= RTW_ANAPARM_TXDACOFF; 2182 break; 2183 case RTW_SLEEP: 2184 if (!before_rf) 2185 return; 2186 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2187 anaparm |= RTW_ANAPARM_TXDACOFF; 2188 break; 2189 case RTW_ON: 2190 if (!before_rf) 2191 return; 2192 if (digphy) { 2193 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2194 /* XXX guess */ 2195 anaparm |= RTW_ANAPARM_TXDACOFF; 2196 } else 2197 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2198 break; 2199 } 2200 RTW_DPRINTF(RTW_DEBUG_PWR, 2201 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2202 __func__, rtw_pwrstate_string(power), 2203 (before_rf) ? "before" : "after", anaparm)); 2204 2205 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2206 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2207 } 2208 2209 static void 2210 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2211 int digphy) 2212 { 2213 struct rtw_regs *regs = &sc->sc_regs; 2214 2215 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2216 2217 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2218 2219 rtw_set_access(regs, RTW_ACCESS_NONE); 2220 2221 return; 2222 } 2223 2224 static int 2225 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2226 { 2227 int rc; 2228 2229 RTW_DPRINTF(RTW_DEBUG_PWR, 2230 ("%s: %s->%s\n", __func__, 2231 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2232 2233 if (sc->sc_pwrstate == power) 2234 return 0; 2235 2236 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2237 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2238 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2239 2240 switch (power) { 2241 case RTW_ON: 2242 /* TBD set LEDs */ 2243 break; 2244 case RTW_SLEEP: 2245 /* TBD */ 2246 break; 2247 case RTW_OFF: 2248 /* TBD */ 2249 break; 2250 } 2251 if (rc == 0) 2252 sc->sc_pwrstate = power; 2253 else 2254 sc->sc_pwrstate = RTW_OFF; 2255 return rc; 2256 } 2257 2258 static int 2259 rtw_tune(struct rtw_softc *sc) 2260 { 2261 struct ieee80211com *ic = &sc->sc_ic; 2262 u_int chan; 2263 int rc; 2264 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2265 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2266 2267 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2268 if (chan == IEEE80211_CHAN_ANY) 2269 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 2270 2271 if (chan == sc->sc_cur_chan) { 2272 RTW_DPRINTF(RTW_DEBUG_TUNE, 2273 ("%s: already tuned chan #%d\n", __func__, chan)); 2274 return 0; 2275 } 2276 2277 rtw_suspend_ticks(sc); 2278 2279 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 2280 2281 /* TBD wait for Tx to complete */ 2282 2283 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2284 2285 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2286 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr, 2287 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) { 2288 /* XXX condition on powersaving */ 2289 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2290 } 2291 2292 sc->sc_cur_chan = chan; 2293 2294 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 2295 2296 rtw_resume_ticks(sc); 2297 2298 return rc; 2299 } 2300 2301 void 2302 rtw_disable(struct rtw_softc *sc) 2303 { 2304 int rc; 2305 2306 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2307 return; 2308 2309 /* turn off PHY */ 2310 if ((sc->sc_flags & RTW_F_INVALID) == 0 && 2311 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2312 printf("%s: failed to turn off PHY (%d)\n", 2313 sc->sc_dev.dv_xname, rc); 2314 } 2315 2316 if (sc->sc_disable != NULL) 2317 (*sc->sc_disable)(sc); 2318 2319 sc->sc_flags &= ~RTW_F_ENABLED; 2320 } 2321 2322 int 2323 rtw_enable(struct rtw_softc *sc) 2324 { 2325 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2326 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2327 printf("%s: device enable failed\n", 2328 sc->sc_dev.dv_xname); 2329 return (EIO); 2330 } 2331 sc->sc_flags |= RTW_F_ENABLED; 2332 } 2333 return (0); 2334 } 2335 2336 static void 2337 rtw_transmit_config(struct rtw_regs *regs) 2338 { 2339 uint32_t tcr; 2340 2341 tcr = RTW_READ(regs, RTW_TCR); 2342 2343 tcr |= RTW_TCR_CWMIN; 2344 tcr &= ~RTW_TCR_MXDMA_MASK; 2345 tcr |= RTW_TCR_MXDMA_256; 2346 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2347 tcr &= ~RTW_TCR_LBK_MASK; 2348 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2349 2350 /* set short/long retry limits */ 2351 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2352 tcr |= LSHIFT(4, RTW_TCR_SRL_MASK) | LSHIFT(4, RTW_TCR_LRL_MASK); 2353 2354 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2355 2356 RTW_WRITE(regs, RTW_TCR, tcr); 2357 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2358 } 2359 2360 static __inline void 2361 rtw_enable_interrupts(struct rtw_softc *sc) 2362 { 2363 struct rtw_regs *regs = &sc->sc_regs; 2364 2365 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2366 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2367 2368 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2369 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2370 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2371 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2372 2373 /* XXX necessary? */ 2374 if (sc->sc_intr_ack != NULL) 2375 (*sc->sc_intr_ack)(regs); 2376 } 2377 2378 static void 2379 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2380 { 2381 uint8_t msr; 2382 2383 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2384 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2385 2386 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2387 2388 switch (opmode) { 2389 case IEEE80211_M_AHDEMO: 2390 case IEEE80211_M_IBSS: 2391 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2392 break; 2393 case IEEE80211_M_HOSTAP: 2394 msr |= RTW_MSR_NETYPE_AP_OK; 2395 break; 2396 case IEEE80211_M_MONITOR: 2397 /* XXX */ 2398 msr |= RTW_MSR_NETYPE_NOLINK; 2399 break; 2400 case IEEE80211_M_STA: 2401 msr |= RTW_MSR_NETYPE_INFRA_OK; 2402 break; 2403 } 2404 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2405 2406 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2407 } 2408 2409 #define rtw_calchash(addr) \ 2410 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2411 2412 static void 2413 rtw_pktfilt_load(struct rtw_softc *sc) 2414 { 2415 struct rtw_regs *regs = &sc->sc_regs; 2416 struct ieee80211com *ic = &sc->sc_ic; 2417 struct ethercom *ec = &sc->sc_ec; 2418 struct ifnet *ifp = &sc->sc_if; 2419 int hash; 2420 uint32_t hashes[2] = { 0, 0 }; 2421 struct ether_multi *enm; 2422 struct ether_multistep step; 2423 2424 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2425 2426 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2427 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2428 2429 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2430 /* MAC auto-reset PHY (huh?) */ 2431 sc->sc_rcr |= RTW_RCR_ENMARP; 2432 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2433 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2434 2435 switch (ic->ic_opmode) { 2436 case IEEE80211_M_MONITOR: 2437 sc->sc_rcr |= RTW_RCR_MONITOR; 2438 break; 2439 case IEEE80211_M_AHDEMO: 2440 case IEEE80211_M_IBSS: 2441 /* receive broadcasts in our BSS */ 2442 sc->sc_rcr |= RTW_RCR_ADD3; 2443 break; 2444 default: 2445 break; 2446 } 2447 2448 ifp->if_flags &= ~IFF_ALLMULTI; 2449 2450 /* XXX accept all broadcast if scanning */ 2451 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2452 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2453 2454 if (ifp->if_flags & IFF_PROMISC) { 2455 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2456 allmulti: 2457 ifp->if_flags |= IFF_ALLMULTI; 2458 goto setit; 2459 } 2460 2461 /* 2462 * Program the 64-bit multicast hash filter. 2463 */ 2464 ETHER_FIRST_MULTI(step, ec, enm); 2465 while (enm != NULL) { 2466 /* XXX */ 2467 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2468 ETHER_ADDR_LEN) != 0) 2469 goto allmulti; 2470 2471 hash = rtw_calchash(enm->enm_addrlo); 2472 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2473 sc->sc_rcr |= RTW_RCR_AM; 2474 ETHER_NEXT_MULTI(step, enm); 2475 } 2476 2477 /* all bits set => hash is useless */ 2478 if (~(hashes[0] & hashes[1]) == 0) 2479 goto allmulti; 2480 2481 setit: 2482 if (ifp->if_flags & IFF_ALLMULTI) { 2483 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2484 hashes[0] = hashes[1] = 0xffffffff; 2485 } 2486 2487 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2488 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2489 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2490 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2491 2492 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2493 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2494 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2495 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2496 2497 return; 2498 } 2499 2500 #define IEEE80211_BEACON_TIMESTAMP_LEN 8 2501 #define IEEE80211_BEACON_BINTVL_LEN 2 2502 #define IEEE80211_BEACON_CAPINFO_LEN 2 2503 #define IEEE80211_TLV_SSID_LEN(__esslen) (2 + (__esslen)) 2504 #define IEEE80211_TLV_SUPRATES_LEN(__nrates) (2 + (__nrates)) 2505 #define IEEE80211_TLV_XSUPRATES_LEN(__nrates) (2 + (__nrates)) 2506 #define IEEE80211_TLV_DSPARMS_LEN 3 2507 #define IEEE80211_TLV_IBSSPARMS 4 2508 #define IEEE80211_TLV_MIN_TIM 6 2509 2510 #define IEEE80211_TLV_ALLRATES_LEN(__nrates) \ 2511 (((__nrates) > IEEE80211_RATE_SIZE) ? 4 + (__nrates) : 2 + (__nrates)) 2512 2513 static struct mbuf * 2514 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2515 { 2516 struct ieee80211com *ic = &sc->sc_ic; 2517 struct mbuf *m; 2518 struct ieee80211_beacon_offsets boff; 2519 2520 m = ieee80211_beacon_alloc(ic, ni, &boff); 2521 2522 RTW_DPRINTF(RTW_DEBUG_BEACON, 2523 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2524 2525 return m; 2526 } 2527 2528 /* Must be called at splnet. */ 2529 static int 2530 rtw_init(struct ifnet *ifp) 2531 { 2532 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2533 struct ieee80211com *ic = &sc->sc_ic; 2534 struct rtw_regs *regs = &sc->sc_regs; 2535 int rc = 0; 2536 2537 if ((rc = rtw_enable(sc)) != 0) 2538 goto out; 2539 2540 /* Cancel pending I/O and reset. */ 2541 rtw_stop(ifp, 0); 2542 2543 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2544 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 2545 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 2546 2547 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2548 goto out; 2549 2550 if ((rc = rtw_swring_setup(sc)) != 0) 2551 goto out; 2552 2553 rtw_transmit_config(regs); 2554 2555 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2556 2557 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2558 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2559 2560 /* long PLCP header, 1Mb/2Mb basic rate */ 2561 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2562 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2563 2564 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2565 rtw_set_access(regs, RTW_ACCESS_NONE); 2566 2567 /* XXX from reference sources */ 2568 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2569 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2570 2571 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2572 2573 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2574 /* from Linux driver */ 2575 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2576 2577 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2578 2579 rtw_enable_interrupts(sc); 2580 2581 rtw_pktfilt_load(sc); 2582 2583 rtw_hwring_setup(sc); 2584 2585 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2586 2587 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2588 2589 ifp->if_flags |= IFF_RUNNING; 2590 ic->ic_state = IEEE80211_S_INIT; 2591 2592 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2593 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2594 2595 rtw_resume_ticks(sc); 2596 2597 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2598 2599 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2600 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2601 else 2602 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2603 2604 out: 2605 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2606 return rc; 2607 } 2608 2609 static __inline void 2610 rtw_led_init(struct rtw_regs *regs) 2611 { 2612 uint8_t cfg0, cfg1; 2613 2614 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2615 2616 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2617 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2618 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2619 2620 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2621 RTW_DPRINTF(RTW_DEBUG_LED, 2622 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2623 2624 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2625 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2626 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2627 2628 rtw_set_access(regs, RTW_ACCESS_NONE); 2629 } 2630 2631 /* 2632 * IEEE80211_S_INIT: LED1 off 2633 * 2634 * IEEE80211_S_AUTH, 2635 * IEEE80211_S_ASSOC, 2636 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2637 * 2638 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2639 */ 2640 static void 2641 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2642 { 2643 struct rtw_led_state *ls; 2644 2645 ls = &sc->sc_led_state; 2646 2647 switch (nstate) { 2648 case IEEE80211_S_INIT: 2649 rtw_led_init(&sc->sc_regs); 2650 callout_stop(&ls->ls_slow_ch); 2651 callout_stop(&ls->ls_fast_ch); 2652 ls->ls_slowblink = 0; 2653 ls->ls_actblink = 0; 2654 ls->ls_default = 0; 2655 break; 2656 case IEEE80211_S_SCAN: 2657 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2658 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2659 /*FALLTHROUGH*/ 2660 case IEEE80211_S_AUTH: 2661 case IEEE80211_S_ASSOC: 2662 ls->ls_default = RTW_LED1; 2663 ls->ls_actblink = RTW_LED1; 2664 ls->ls_slowblink = RTW_LED1; 2665 break; 2666 case IEEE80211_S_RUN: 2667 ls->ls_slowblink = 0; 2668 break; 2669 } 2670 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2671 } 2672 2673 static void 2674 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2675 { 2676 uint8_t led_condition; 2677 bus_size_t ofs; 2678 uint8_t mask, newval, val; 2679 2680 led_condition = ls->ls_default; 2681 2682 if (ls->ls_state & RTW_LED_S_SLOW) 2683 led_condition ^= ls->ls_slowblink; 2684 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2685 led_condition ^= ls->ls_actblink; 2686 2687 RTW_DPRINTF(RTW_DEBUG_LED, 2688 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2689 2690 switch (hwverid) { 2691 default: 2692 case 'F': 2693 ofs = RTW_PSR; 2694 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2695 if (led_condition & RTW_LED0) 2696 newval &= ~RTW_PSR_LEDGPO0; 2697 if (led_condition & RTW_LED1) 2698 newval &= ~RTW_PSR_LEDGPO1; 2699 break; 2700 case 'D': 2701 ofs = RTW_9346CR; 2702 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2703 newval = RTW_9346CR_EEM_PROGRAM; 2704 if (led_condition & RTW_LED0) 2705 newval |= RTW_9346CR_EEDI; 2706 if (led_condition & RTW_LED1) 2707 newval |= RTW_9346CR_EECS; 2708 break; 2709 } 2710 val = RTW_READ8(regs, ofs); 2711 RTW_DPRINTF(RTW_DEBUG_LED, 2712 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2713 (uintptr_t)ofs)); 2714 val &= ~mask; 2715 val |= newval; 2716 RTW_WRITE8(regs, ofs, val); 2717 RTW_DPRINTF(RTW_DEBUG_LED, 2718 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2719 (uintptr_t)ofs)); 2720 RTW_SYNC(regs, ofs, ofs); 2721 } 2722 2723 static void 2724 rtw_led_fastblink(void *arg) 2725 { 2726 int ostate, s; 2727 struct rtw_softc *sc = (struct rtw_softc *)arg; 2728 struct rtw_led_state *ls = &sc->sc_led_state; 2729 2730 s = splnet(); 2731 ostate = ls->ls_state; 2732 ls->ls_state ^= ls->ls_event; 2733 2734 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2735 ls->ls_state &= ~RTW_LED_S_TX; 2736 2737 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2738 ls->ls_state &= ~RTW_LED_S_RX; 2739 2740 ls->ls_event = 0; 2741 2742 if (ostate != ls->ls_state) 2743 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2744 splx(s); 2745 2746 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2747 } 2748 2749 static void 2750 rtw_led_slowblink(void *arg) 2751 { 2752 int s; 2753 struct rtw_softc *sc = (struct rtw_softc *)arg; 2754 struct rtw_led_state *ls = &sc->sc_led_state; 2755 2756 s = splnet(); 2757 ls->ls_state ^= RTW_LED_S_SLOW; 2758 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2759 splx(s); 2760 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2761 } 2762 2763 static __inline void 2764 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2765 { 2766 callout_init(&ls->ls_fast_ch); 2767 callout_init(&ls->ls_slow_ch); 2768 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2769 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2770 } 2771 2772 static int 2773 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2774 { 2775 int rc = 0, s; 2776 struct rtw_softc *sc = ifp->if_softc; 2777 struct ifreq *ifr = (struct ifreq *)data; 2778 2779 s = splnet(); 2780 switch (cmd) { 2781 case SIOCSIFFLAGS: 2782 if ((ifp->if_flags & IFF_UP) != 0) { 2783 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2784 rtw_pktfilt_load(sc); 2785 } else 2786 rc = rtw_init(ifp); 2787 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2788 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2789 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2790 rtw_stop(ifp, 1); 2791 } 2792 break; 2793 case SIOCADDMULTI: 2794 case SIOCDELMULTI: 2795 if (cmd == SIOCADDMULTI) 2796 rc = ether_addmulti(ifr, &sc->sc_ec); 2797 else 2798 rc = ether_delmulti(ifr, &sc->sc_ec); 2799 if (rc != ENETRESET) 2800 break; 2801 if (ifp->if_flags & IFF_RUNNING) 2802 rtw_pktfilt_load(sc); 2803 rc = 0; 2804 break; 2805 default: 2806 if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 2807 break; 2808 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2809 rc = rtw_init(ifp); 2810 else 2811 rc = 0; 2812 break; 2813 } 2814 splx(s); 2815 return rc; 2816 } 2817 2818 /* Select a transmit ring with at least one h/w and s/w descriptor free. 2819 * Return 0 on success, -1 on failure. 2820 */ 2821 static __inline int 2822 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 2823 struct rtw_txdesc_blk **tdbp, int pri) 2824 { 2825 struct rtw_txsoft_blk *tsb; 2826 struct rtw_txdesc_blk *tdb; 2827 2828 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 2829 2830 tsb = &sc->sc_txsoft_blk[pri]; 2831 tdb = &sc->sc_txdesc_blk[pri]; 2832 2833 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 2834 *tsbp = NULL; 2835 *tdbp = NULL; 2836 return -1; 2837 } 2838 *tsbp = tsb; 2839 *tdbp = tdb; 2840 return 0; 2841 } 2842 2843 static __inline struct mbuf * 2844 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 2845 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 2846 struct ieee80211_node **nip, short *if_flagsp) 2847 { 2848 struct mbuf *m; 2849 2850 if (IF_IS_EMPTY(ifq)) 2851 return NULL; 2852 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 2853 *if_flagsp |= IFF_OACTIVE; 2854 return NULL; 2855 } 2856 IF_DEQUEUE(ifq, m); 2857 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2858 m->m_pkthdr.rcvif = NULL; 2859 KASSERT(*nip != NULL); 2860 return m; 2861 } 2862 2863 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 2864 * at the driver's selection of transmit control block for the packet. 2865 */ 2866 static __inline int 2867 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 2868 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 2869 struct ieee80211_node **nip) 2870 { 2871 int pri; 2872 struct ether_header *eh; 2873 struct mbuf *m0; 2874 struct rtw_softc *sc; 2875 short *if_flagsp; 2876 2877 sc = (struct rtw_softc *)ifp->if_softc; 2878 2879 DPRINTF(sc, RTW_DEBUG_XMIT, 2880 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2881 2882 if_flagsp = &ifp->if_flags; 2883 2884 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 2885 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 2886 tdbp, nip, if_flagsp)) != NULL) { 2887 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 2888 __func__)); 2889 return 0; 2890 } 2891 2892 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 2893 tdbp, nip, if_flagsp)) != NULL) { 2894 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 2895 __func__)); 2896 return 0; 2897 } 2898 2899 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 2900 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 2901 return 0; 2902 } 2903 2904 *mp = NULL; 2905 2906 IFQ_POLL(&ifp->if_snd, m0); 2907 if (m0 == NULL) { 2908 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 2909 __func__)); 2910 return 0; 2911 } 2912 2913 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 2914 2915 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 2916 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no descriptor\n", __func__)); 2917 *if_flagsp |= IFF_OACTIVE; 2918 return 0; 2919 } 2920 2921 IFQ_DEQUEUE(&ifp->if_snd, m0); 2922 if (m0 == NULL) { 2923 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 2924 __func__)); 2925 return 0; 2926 } 2927 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 2928 ifp->if_opackets++; 2929 #if NBPFILTER > 0 2930 if (ifp->if_bpf) 2931 bpf_mtap(ifp->if_bpf, m0); 2932 #endif 2933 eh = mtod(m0, struct ether_header *); 2934 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 2935 if (*nip == NULL) { 2936 /* NB: ieee80211_find_txnode does stat+msg */ 2937 m_freem(m0); 2938 return -1; 2939 } 2940 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 2941 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 2942 ifp->if_oerrors++; 2943 return -1; 2944 } 2945 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 2946 *mp = m0; 2947 return 0; 2948 } 2949 2950 static int 2951 rtw_seg_too_short(bus_dmamap_t dmamap) 2952 { 2953 int i; 2954 for (i = 0; i < dmamap->dm_nsegs; i++) { 2955 if (dmamap->dm_segs[i].ds_len < 4) { 2956 printf("%s: segment too short\n", __func__); 2957 return 1; 2958 } 2959 } 2960 return 0; 2961 } 2962 2963 /* TBD factor with atw_start */ 2964 static struct mbuf * 2965 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2966 u_int ndescfree, short *ifflagsp, const char *dvname) 2967 { 2968 int first, rc; 2969 struct mbuf *m, *m0; 2970 2971 m0 = chain; 2972 2973 /* 2974 * Load the DMA map. Copy and try (once) again if the packet 2975 * didn't fit in the alloted number of segments. 2976 */ 2977 for (first = 1; 2978 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2979 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2980 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 2981 first = 0) { 2982 if (rc == 0) 2983 bus_dmamap_unload(dmat, dmam); 2984 MGETHDR(m, M_DONTWAIT, MT_DATA); 2985 if (m == NULL) { 2986 printf("%s: unable to allocate Tx mbuf\n", 2987 dvname); 2988 break; 2989 } 2990 if (m0->m_pkthdr.len > MHLEN) { 2991 MCLGET(m, M_DONTWAIT); 2992 if ((m->m_flags & M_EXT) == 0) { 2993 printf("%s: cannot allocate Tx cluster\n", 2994 dvname); 2995 m_freem(m); 2996 break; 2997 } 2998 } 2999 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3000 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3001 m_freem(m0); 3002 m0 = m; 3003 m = NULL; 3004 } 3005 if (rc != 0) { 3006 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 3007 m_freem(m0); 3008 return NULL; 3009 } else if (rtw_seg_too_short(dmam)) { 3010 printf("%s: cannot load Tx buffer, segment too short\n", 3011 dvname); 3012 bus_dmamap_unload(dmat, dmam); 3013 m_freem(m0); 3014 return NULL; 3015 } else if (dmam->dm_nsegs > ndescfree) { 3016 printf("%s: too many tx segments\n", dvname); 3017 *ifflagsp |= IFF_OACTIVE; 3018 bus_dmamap_unload(dmat, dmam); 3019 m_freem(m0); 3020 return NULL; 3021 } 3022 return m0; 3023 } 3024 3025 #ifdef RTW_DEBUG 3026 static void 3027 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3028 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3029 { 3030 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3031 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] ctl0 %#08x " 3032 "ctl1 %#08x buf %#08x len %#08x\n", 3033 sc->sc_dev.dv_xname, ts, action, desc, 3034 le32toh(td->td_ctl0), 3035 le32toh(td->td_ctl1), le32toh(td->td_buf), 3036 le32toh(td->td_len))); 3037 } 3038 #endif /* RTW_DEBUG */ 3039 3040 static void 3041 rtw_start(struct ifnet *ifp) 3042 { 3043 uint8_t tppoll; 3044 int desc, i, lastdesc, npkt, rate; 3045 uint32_t proto_ctl0, ctl0, ctl1; 3046 bus_dmamap_t dmamap; 3047 struct ieee80211com *ic; 3048 struct ieee80211_duration *d0; 3049 struct ieee80211_frame_min *wh; 3050 struct ieee80211_node *ni; 3051 struct mbuf *m0; 3052 struct rtw_softc *sc; 3053 struct rtw_txsoft_blk *tsb; 3054 struct rtw_txdesc_blk *tdb; 3055 struct rtw_txsoft *ts; 3056 struct rtw_txdesc *td; 3057 struct ieee80211_key *k; 3058 3059 sc = (struct rtw_softc *)ifp->if_softc; 3060 ic = &sc->sc_ic; 3061 3062 DPRINTF(sc, RTW_DEBUG_XMIT, 3063 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3064 3065 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3066 goto out; 3067 3068 /* XXX do real rate control */ 3069 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3070 3071 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3072 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3073 3074 for (;;) { 3075 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3076 continue; 3077 if (m0 == NULL) 3078 break; 3079 3080 wh = mtod(m0, struct ieee80211_frame_min *); 3081 3082 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3083 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3084 m_freem(m0); 3085 break; 3086 } else 3087 k = NULL; 3088 3089 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3090 3091 dmamap = ts->ts_dmamap; 3092 3093 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3094 tdb->tdb_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 3095 3096 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3097 DPRINTF(sc, RTW_DEBUG_XMIT, 3098 ("%s: fail dmamap load\n", __func__)); 3099 goto post_dequeue_err; 3100 } 3101 3102 /* Note well: rtw_dmamap_load_txbuf may have created 3103 * a new chain, so we must find the header once 3104 * more. 3105 */ 3106 wh = mtod(m0, struct ieee80211_frame_min *); 3107 3108 /* XXX do real rate control */ 3109 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3110 IEEE80211_FC0_TYPE_MGT) 3111 rate = 2; 3112 else 3113 rate = MAX(2, ieee80211_get_rate(ic)); 3114 3115 #ifdef RTW_DEBUG 3116 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3117 (IFF_DEBUG|IFF_LINK2)) { 3118 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3119 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3120 : sizeof(wh), 3121 rate, 0); 3122 } 3123 #endif /* RTW_DEBUG */ 3124 ctl0 = proto_ctl0 | 3125 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3126 3127 switch (rate) { 3128 default: 3129 case 2: 3130 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3131 break; 3132 case 4: 3133 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3134 break; 3135 case 11: 3136 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3137 break; 3138 case 22: 3139 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3140 break; 3141 } 3142 /* XXX >= ? Compare after fragmentation? */ 3143 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3144 ctl0 |= RTW_TXCTL0_RTSEN; 3145 3146 if (k != NULL) { 3147 ctl0 |= LSHIFT(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3148 RTW_TXCTL0_KEYID_MASK; 3149 } 3150 3151 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3152 IEEE80211_FC0_TYPE_MGT) { 3153 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3154 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3155 IEEE80211_FC0_SUBTYPE_BEACON) 3156 ctl0 |= RTW_TXCTL0_BEACON; 3157 } 3158 3159 if (ieee80211_compute_duration(wh, m0->m_pkthdr.len, 3160 ic->ic_flags, ic->ic_fragthreshold, 3161 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3162 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3163 (IFF_DEBUG|IFF_LINK2)) == -1) { 3164 DPRINTF(sc, RTW_DEBUG_XMIT, 3165 ("%s: fail compute duration\n", __func__)); 3166 goto post_load_err; 3167 } 3168 3169 d0 = &ts->ts_d0; 3170 3171 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3172 3173 ctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3174 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3175 3176 if (d0->d_residue) 3177 ctl1 |= RTW_TXCTL1_LENGEXT; 3178 3179 /* TBD fragmentation */ 3180 3181 ts->ts_first = tdb->tdb_next; 3182 3183 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3184 BUS_DMASYNC_PREWRITE); 3185 3186 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3187 3188 #if NBPFILTER > 0 3189 if (ic->ic_rawbpf != NULL) 3190 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3191 3192 if (sc->sc_radiobpf != NULL) { 3193 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3194 3195 rt->rt_flags = 0; 3196 rt->rt_rate = rate; 3197 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq); 3198 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags); 3199 3200 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rt, 3201 sizeof(sc->sc_txtapu), m0); 3202 } 3203 #endif /* NPBFILTER > 0 */ 3204 3205 for (i = 0, lastdesc = desc = ts->ts_first; 3206 i < dmamap->dm_nsegs; 3207 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3208 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3209 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3210 ("%s: seg too long\n", __func__)); 3211 goto post_load_err; 3212 } 3213 td = &tdb->tdb_desc[desc]; 3214 td->td_ctl0 = htole32(ctl0); 3215 if (i != 0) 3216 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3217 td->td_ctl1 = htole32(ctl1); 3218 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3219 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3220 lastdesc = desc; 3221 #ifdef RTW_DEBUG 3222 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3223 #endif /* RTW_DEBUG */ 3224 } 3225 3226 KASSERT(desc < tdb->tdb_ndesc); 3227 3228 ts->ts_ni = ni; 3229 KASSERT(ni != NULL); 3230 ts->ts_mbuf = m0; 3231 ts->ts_last = lastdesc; 3232 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3233 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3234 htole32(RTW_TXCTL0_FS); 3235 3236 #ifdef RTW_DEBUG 3237 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3238 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3239 #endif /* RTW_DEBUG */ 3240 3241 tdb->tdb_nfree -= dmamap->dm_nsegs; 3242 tdb->tdb_next = desc; 3243 3244 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3245 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3246 3247 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3248 htole32(RTW_TXCTL0_OWN); 3249 3250 #ifdef RTW_DEBUG 3251 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3252 #endif /* RTW_DEBUG */ 3253 3254 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3255 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3256 3257 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3258 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3259 3260 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) { 3261 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3262 tsb->tsb_tx_timer = 5; 3263 ifp->if_timer = 1; 3264 } 3265 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3266 tppoll &= ~RTW_TPPOLL_SALL; 3267 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL; 3268 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3269 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3270 } 3271 out: 3272 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3273 return; 3274 post_load_err: 3275 bus_dmamap_unload(sc->sc_dmat, dmamap); 3276 m_freem(m0); 3277 post_dequeue_err: 3278 ieee80211_free_node(ni); 3279 return; 3280 } 3281 3282 static void 3283 rtw_watchdog(struct ifnet *ifp) 3284 { 3285 int pri; 3286 struct rtw_softc *sc; 3287 struct rtw_txsoft_blk *tsb; 3288 3289 sc = ifp->if_softc; 3290 3291 ifp->if_timer = 0; 3292 3293 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 3294 return; 3295 3296 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3297 tsb = &sc->sc_txsoft_blk[pri]; 3298 3299 if (tsb->tsb_tx_timer == 0) 3300 continue; 3301 3302 if (--tsb->tsb_tx_timer == 0) { 3303 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3304 continue; 3305 printf("%s: transmit timeout, priority %d\n", 3306 ifp->if_xname, pri); 3307 ifp->if_oerrors++; 3308 /* Stop Tx DMA, disable transmitter, clear 3309 * Tx rings, and restart. 3310 * 3311 * TBD Stop/restart just the broken ring? 3312 */ 3313 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3314 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3315 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 0); 3316 rtw_txdescs_reset(sc); 3317 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 1); 3318 ifp->if_flags &= ~IFF_OACTIVE; 3319 rtw_start(ifp); 3320 } else 3321 ifp->if_timer = 1; 3322 } 3323 ieee80211_watchdog(&sc->sc_ic); 3324 return; 3325 } 3326 3327 static void 3328 rtw_next_scan(void *arg) 3329 { 3330 struct ieee80211com *ic = arg; 3331 int s; 3332 3333 /* don't call rtw_start w/o network interrupts blocked */ 3334 s = splnet(); 3335 if (ic->ic_state == IEEE80211_S_SCAN) 3336 ieee80211_next_scan(ic); 3337 splx(s); 3338 } 3339 3340 static void 3341 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3342 { 3343 uint16_t bcnitv, intval; 3344 int i; 3345 struct rtw_regs *regs = &sc->sc_regs; 3346 3347 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3348 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3349 3350 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3351 3352 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3353 3354 intval = MIN(intval0, PRESHIFT(RTW_BCNITV_BCNITV_MASK)); 3355 3356 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3357 bcnitv |= LSHIFT(intval, RTW_BCNITV_BCNITV_MASK); 3358 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3359 /* magic from Linux */ 3360 RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND)); 3361 RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV)); 3362 3363 rtw_set_access(regs, RTW_ACCESS_NONE); 3364 3365 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 3366 } 3367 3368 /* Synchronize the hardware state with the software state. */ 3369 static int 3370 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3371 { 3372 struct ifnet *ifp = ic->ic_ifp; 3373 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3374 struct mbuf *m; 3375 enum ieee80211_state ostate; 3376 int error; 3377 3378 ostate = ic->ic_state; 3379 3380 rtw_led_newstate(sc, nstate); 3381 3382 if (nstate == IEEE80211_S_INIT) { 3383 callout_stop(&sc->sc_scan_ch); 3384 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3385 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3386 } 3387 3388 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3389 rtw_pwrstate(sc, RTW_ON); 3390 3391 if ((error = rtw_tune(sc)) != 0) 3392 return error; 3393 3394 switch (nstate) { 3395 case IEEE80211_S_INIT: 3396 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3397 break; 3398 case IEEE80211_S_SCAN: 3399 if (ostate != IEEE80211_S_SCAN) { 3400 (void)memset(ic->ic_bss->ni_bssid, 0, 3401 IEEE80211_ADDR_LEN); 3402 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3403 } 3404 3405 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3406 rtw_next_scan, ic); 3407 3408 break; 3409 case IEEE80211_S_RUN: 3410 switch (ic->ic_opmode) { 3411 case IEEE80211_M_HOSTAP: 3412 case IEEE80211_M_IBSS: 3413 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3414 m = rtw_beacon_alloc(sc, ic->ic_bss); 3415 if (m == NULL) { 3416 printf("%s: could not allocate beacon\n", 3417 sc->sc_dev.dv_xname); 3418 } else { 3419 IF_ENQUEUE(&sc->sc_beaconq, m); 3420 m->m_pkthdr.rcvif = 3421 (void *)ieee80211_ref_node(ic->ic_bss); 3422 } 3423 /*FALLTHROUGH*/ 3424 case IEEE80211_M_AHDEMO: 3425 case IEEE80211_M_STA: 3426 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3427 ic->ic_bss->ni_intval); 3428 break; 3429 case IEEE80211_M_MONITOR: 3430 break; 3431 } 3432 rtw_set_nettype(sc, ic->ic_opmode); 3433 break; 3434 case IEEE80211_S_ASSOC: 3435 case IEEE80211_S_AUTH: 3436 break; 3437 } 3438 3439 if (nstate != IEEE80211_S_SCAN) 3440 callout_stop(&sc->sc_scan_ch); 3441 3442 /* Start beacon transmission. */ 3443 if (nstate == IEEE80211_S_RUN && 3444 (ic->ic_opmode == IEEE80211_M_HOSTAP || 3445 ic->ic_opmode == IEEE80211_M_IBSS)) 3446 rtw_start(ifp); 3447 3448 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3449 } 3450 3451 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3452 static uint64_t 3453 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3454 { 3455 uint32_t tsftl, tsfth; 3456 3457 tsfth = RTW_READ(regs, RTW_TSFTRH); 3458 tsftl = RTW_READ(regs, RTW_TSFTRL); 3459 if (tsftl < rstamp) /* Compensate for rollover. */ 3460 tsfth--; 3461 return ((uint64_t)tsfth << 32) | rstamp; 3462 } 3463 3464 static void 3465 rtw_ibss_merge(struct rtw_softc *sc, struct ieee80211_node *ni, uint32_t rstamp) 3466 { 3467 uint8_t tppoll; 3468 3469 if (le64toh(ni->ni_tstamp.tsf) < rtw_tsf_extend(&sc->sc_regs, rstamp)) 3470 return; 3471 if (ieee80211_ibss_merge(ni) == ENETRESET) { 3472 /* Stop beacon queue. Kick state machine to synchronize 3473 * with the new IBSS. 3474 */ 3475 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3476 tppoll |= RTW_TPPOLL_SBQ; 3477 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3478 (void)ieee80211_new_state(&sc->sc_ic, IEEE80211_S_RUN, -1); 3479 } 3480 return; 3481 } 3482 3483 static void 3484 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3485 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3486 { 3487 struct ifnet *ifp = ic->ic_ifp; 3488 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3489 3490 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3491 3492 switch (subtype) { 3493 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3494 case IEEE80211_FC0_SUBTYPE_BEACON: 3495 if (ic->ic_opmode != IEEE80211_M_IBSS || 3496 ic->ic_state != IEEE80211_S_RUN) 3497 return; 3498 rtw_ibss_merge(sc, ni, rstamp); 3499 break; 3500 default: 3501 break; 3502 } 3503 return; 3504 } 3505 3506 static struct ieee80211_node * 3507 rtw_node_alloc(struct ieee80211_node_table *nt) 3508 { 3509 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3510 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3511 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3512 3513 DPRINTF(sc, RTW_DEBUG_NODE, 3514 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3515 return ni; 3516 } 3517 3518 static void 3519 rtw_node_free(struct ieee80211_node *ni) 3520 { 3521 struct ieee80211com *ic = ni->ni_ic; 3522 struct ifnet *ifp = ic->ic_ifp; 3523 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3524 3525 DPRINTF(sc, RTW_DEBUG_NODE, 3526 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3527 ether_sprintf(ni->ni_bssid))); 3528 (*sc->sc_mtbl.mt_node_free)(ni); 3529 } 3530 3531 static int 3532 rtw_media_change(struct ifnet *ifp) 3533 { 3534 int error; 3535 3536 error = ieee80211_media_change(ifp); 3537 if (error == ENETRESET) { 3538 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3539 (IFF_RUNNING|IFF_UP)) 3540 rtw_init(ifp); /* XXX lose error */ 3541 error = 0; 3542 } 3543 return error; 3544 } 3545 3546 static void 3547 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3548 { 3549 struct rtw_softc *sc = ifp->if_softc; 3550 3551 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3552 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3553 imr->ifm_status = 0; 3554 return; 3555 } 3556 ieee80211_media_status(ifp, imr); 3557 } 3558 3559 void 3560 rtw_power(int why, void *arg) 3561 { 3562 struct rtw_softc *sc = arg; 3563 struct ifnet *ifp = &sc->sc_if; 3564 int s; 3565 3566 DPRINTF(sc, RTW_DEBUG_PWR, 3567 ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3568 3569 s = splnet(); 3570 switch (why) { 3571 case PWR_STANDBY: 3572 /* XXX do nothing. */ 3573 break; 3574 case PWR_SUSPEND: 3575 rtw_stop(ifp, 0); 3576 if (sc->sc_power != NULL) 3577 (*sc->sc_power)(sc, why); 3578 break; 3579 case PWR_RESUME: 3580 if (ifp->if_flags & IFF_UP) { 3581 if (sc->sc_power != NULL) 3582 (*sc->sc_power)(sc, why); 3583 rtw_init(ifp); 3584 } 3585 break; 3586 case PWR_SOFTSUSPEND: 3587 case PWR_SOFTSTANDBY: 3588 case PWR_SOFTRESUME: 3589 break; 3590 } 3591 splx(s); 3592 } 3593 3594 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 3595 void 3596 rtw_shutdown(void *arg) 3597 { 3598 struct rtw_softc *sc = arg; 3599 3600 rtw_stop(&sc->sc_if, 1); 3601 } 3602 3603 static __inline void 3604 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3605 { 3606 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3607 ifp->if_softc = softc; 3608 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3609 IFF_NOTRAILERS; 3610 ifp->if_ioctl = rtw_ioctl; 3611 ifp->if_start = rtw_start; 3612 ifp->if_watchdog = rtw_watchdog; 3613 ifp->if_init = rtw_init; 3614 ifp->if_stop = rtw_stop; 3615 } 3616 3617 static __inline void 3618 rtw_set80211props(struct ieee80211com *ic) 3619 { 3620 int nrate; 3621 ic->ic_phytype = IEEE80211_T_DS; 3622 ic->ic_opmode = IEEE80211_M_STA; 3623 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3624 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 3625 3626 nrate = 0; 3627 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3628 IEEE80211_RATE_BASIC | 2; 3629 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3630 IEEE80211_RATE_BASIC | 4; 3631 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3632 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3633 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3634 } 3635 3636 static __inline void 3637 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3638 { 3639 mtbl->mt_newstate = ic->ic_newstate; 3640 ic->ic_newstate = rtw_newstate; 3641 3642 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3643 ic->ic_recv_mgmt = rtw_recv_mgmt; 3644 3645 mtbl->mt_node_free = ic->ic_node_free; 3646 ic->ic_node_free = rtw_node_free; 3647 3648 mtbl->mt_node_alloc = ic->ic_node_alloc; 3649 ic->ic_node_alloc = rtw_node_alloc; 3650 3651 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3652 ic->ic_crypto.cs_key_set = rtw_key_set; 3653 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3654 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3655 } 3656 3657 static __inline void 3658 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 3659 void *arg) 3660 { 3661 /* 3662 * Make sure the interface is shutdown during reboot. 3663 */ 3664 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 3665 if (hooks->rh_shutdown == NULL) 3666 printf("%s: WARNING: unable to establish shutdown hook\n", 3667 dvname); 3668 3669 /* 3670 * Add a suspend hook to make sure we come back up after a 3671 * resume. 3672 */ 3673 hooks->rh_power = powerhook_establish(rtw_power, arg); 3674 if (hooks->rh_power == NULL) 3675 printf("%s: WARNING: unable to establish power hook\n", 3676 dvname); 3677 } 3678 3679 static __inline void 3680 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 3681 void *arg) 3682 { 3683 if (hooks->rh_shutdown != NULL) 3684 shutdownhook_disestablish(hooks->rh_shutdown); 3685 3686 if (hooks->rh_power != NULL) 3687 powerhook_disestablish(hooks->rh_power); 3688 } 3689 3690 static __inline void 3691 rtw_init_radiotap(struct rtw_softc *sc) 3692 { 3693 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3694 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3695 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT); 3696 3697 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3698 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3699 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3700 } 3701 3702 static int 3703 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3704 { 3705 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3706 SIMPLEQ_INIT(&tsb->tsb_freeq); 3707 tsb->tsb_ndesc = qlen; 3708 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3709 M_NOWAIT); 3710 if (tsb->tsb_desc == NULL) 3711 return ENOMEM; 3712 return 0; 3713 } 3714 3715 static void 3716 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3717 { 3718 int pri; 3719 struct rtw_txsoft_blk *tsb; 3720 3721 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3722 tsb = &sc->sc_txsoft_blk[pri]; 3723 free(tsb->tsb_desc, M_DEVBUF); 3724 tsb->tsb_desc = NULL; 3725 } 3726 } 3727 3728 static int 3729 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3730 { 3731 int pri, rc = 0; 3732 int qlen[RTW_NTXPRI] = 3733 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3734 struct rtw_txsoft_blk *tsbs; 3735 3736 tsbs = sc->sc_txsoft_blk; 3737 3738 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3739 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3740 if (rc != 0) 3741 break; 3742 } 3743 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3744 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3745 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3746 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3747 return rc; 3748 } 3749 3750 static void 3751 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3752 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3753 { 3754 tdb->tdb_ndesc = ndesc; 3755 tdb->tdb_desc = desc; 3756 tdb->tdb_physbase = physbase; 3757 tdb->tdb_ofs = ofs; 3758 3759 (void)memset(tdb->tdb_desc, 0, 3760 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3761 3762 rtw_txdesc_blk_reset(tdb); 3763 } 3764 3765 static void 3766 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3767 { 3768 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3769 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3770 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3771 3772 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3773 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3774 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3775 3776 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3777 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3778 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3779 3780 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3781 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3782 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3783 } 3784 3785 static struct rtw_rf * 3786 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3787 { 3788 rtw_rf_write_t rf_write; 3789 struct rtw_rf *rf; 3790 3791 switch (rfchipid) { 3792 default: 3793 rf_write = rtw_rf_hostwrite; 3794 break; 3795 case RTW_RFCHIPID_INTERSIL: 3796 case RTW_RFCHIPID_PHILIPS: 3797 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3798 case RTW_RFCHIPID_RFMD: 3799 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3800 break; 3801 } 3802 3803 switch (rfchipid) { 3804 case RTW_RFCHIPID_MAXIM: 3805 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3806 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3807 break; 3808 case RTW_RFCHIPID_PHILIPS: 3809 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3810 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3811 break; 3812 case RTW_RFCHIPID_RFMD: 3813 /* XXX RFMD has no RF constructor */ 3814 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3815 /*FALLTHROUGH*/ 3816 default: 3817 return NULL; 3818 } 3819 rf->rf_continuous_tx_cb = 3820 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3821 rf->rf_continuous_tx_arg = (void *)sc; 3822 return rf; 3823 } 3824 3825 /* Revision C and later use a different PHY delay setting than 3826 * revisions A and B. 3827 */ 3828 static uint8_t 3829 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 3830 { 3831 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3832 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3833 3834 uint8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 3835 3836 RTW_WRITE(regs, RTW_RCR, REVAB); 3837 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3838 RTW_WRITE(regs, RTW_RCR, REVC); 3839 3840 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3841 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3842 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3843 3844 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 3845 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3846 3847 return phydelay; 3848 #undef REVC 3849 } 3850 3851 void 3852 rtw_attach(struct rtw_softc *sc) 3853 { 3854 struct ifnet *ifp = &sc->sc_if; 3855 struct ieee80211com *ic = &sc->sc_ic; 3856 struct rtw_txsoft_blk *tsb; 3857 int pri, rc; 3858 3859 NEXT_ATTACH_STATE(sc, DETACHED); 3860 3861 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3862 case RTW_TCR_HWVERID_F: 3863 sc->sc_hwverid = 'F'; 3864 break; 3865 case RTW_TCR_HWVERID_D: 3866 sc->sc_hwverid = 'D'; 3867 break; 3868 default: 3869 sc->sc_hwverid = '?'; 3870 break; 3871 } 3872 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, 3873 sc->sc_hwverid); 3874 3875 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3876 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3877 0); 3878 3879 if (rc != 0) { 3880 printf("%s: could not allocate hw descriptors, error %d\n", 3881 sc->sc_dev.dv_xname, rc); 3882 goto err; 3883 } 3884 3885 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3886 3887 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3888 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3889 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3890 3891 if (rc != 0) { 3892 printf("%s: could not map hw descriptors, error %d\n", 3893 sc->sc_dev.dv_xname, rc); 3894 goto err; 3895 } 3896 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3897 3898 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3899 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3900 3901 if (rc != 0) { 3902 printf("%s: could not create DMA map for hw descriptors, " 3903 "error %d\n", sc->sc_dev.dv_xname, rc); 3904 goto err; 3905 } 3906 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3907 3908 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 3909 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 3910 3911 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3912 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 3913 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 3914 } 3915 3916 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3917 sizeof(struct rtw_descs), NULL, 0); 3918 3919 if (rc != 0) { 3920 printf("%s: could not load DMA map for hw descriptors, " 3921 "error %d\n", sc->sc_dev.dv_xname, rc); 3922 goto err; 3923 } 3924 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3925 3926 if (rtw_txsoft_blk_setup_all(sc) != 0) 3927 goto err; 3928 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3929 3930 rtw_txdesc_blk_setup_all(sc); 3931 3932 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3933 3934 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 3935 3936 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3937 tsb = &sc->sc_txsoft_blk[pri]; 3938 3939 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3940 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 3941 printf("%s: could not load DMA map for " 3942 "hw tx descriptors, error %d\n", 3943 sc->sc_dev.dv_xname, rc); 3944 goto err; 3945 } 3946 } 3947 3948 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3949 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 3950 RTW_RXQLEN)) != 0) { 3951 printf("%s: could not load DMA map for hw rx descriptors, " 3952 "error %d\n", sc->sc_dev.dv_xname, rc); 3953 goto err; 3954 } 3955 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3956 3957 /* Reset the chip to a known state. */ 3958 if (rtw_reset(sc) != 0) 3959 goto err; 3960 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3961 3962 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3963 3964 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3965 sc->sc_flags |= RTW_F_9356SROM; 3966 3967 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3968 sc->sc_dev.dv_xname) != 0) 3969 goto err; 3970 3971 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3972 3973 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3974 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3975 sc->sc_dev.dv_xname) != 0) { 3976 printf("%s: attach failed, malformed serial ROM\n", 3977 sc->sc_dev.dv_xname); 3978 goto err; 3979 } 3980 3981 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 3982 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 3983 3984 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 3985 3986 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3987 3988 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 3989 sc->sc_flags & RTW_F_DIGPHY); 3990 3991 if (sc->sc_rf == NULL) { 3992 printf("%s: attach failed, could not attach RF\n", 3993 sc->sc_dev.dv_xname); 3994 goto err; 3995 } 3996 3997 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3998 3999 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4000 4001 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4002 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 4003 4004 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4005 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 4006 sc->sc_dev.dv_xname); 4007 4008 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 4009 sc->sc_dev.dv_xname); 4010 4011 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4012 sc->sc_dev.dv_xname) != 0) 4013 goto err; 4014 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4015 4016 rtw_setifprops(ifp, sc->sc_dev.dv_xname, (void*)sc); 4017 4018 IFQ_SET_READY(&ifp->if_snd); 4019 4020 sc->sc_ic.ic_ifp = ifp; 4021 rtw_set80211props(&sc->sc_ic); 4022 4023 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4024 4025 /* 4026 * Call MI attach routines. 4027 */ 4028 if_attach(ifp); 4029 ieee80211_ifattach(&sc->sc_ic); 4030 4031 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4032 4033 /* possibly we should fill in our own sc_send_prresp, since 4034 * the RTL8180 is probably sending probe responses in ad hoc 4035 * mode. 4036 */ 4037 4038 /* complete initialization */ 4039 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4040 callout_init(&sc->sc_scan_ch); 4041 4042 rtw_init_radiotap(sc); 4043 4044 #if NBPFILTER > 0 4045 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4046 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4047 #endif 4048 4049 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 4050 4051 NEXT_ATTACH_STATE(sc, FINISHED); 4052 4053 ieee80211_announce(ic); 4054 return; 4055 err: 4056 rtw_detach(sc); 4057 return; 4058 } 4059 4060 int 4061 rtw_detach(struct rtw_softc *sc) 4062 { 4063 struct ifnet *ifp = &sc->sc_if; 4064 int pri; 4065 4066 sc->sc_flags |= RTW_F_INVALID; 4067 4068 switch (sc->sc_attach_state) { 4069 case FINISHED: 4070 rtw_stop(ifp, 1); 4071 4072 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 4073 (void*)sc); 4074 callout_stop(&sc->sc_scan_ch); 4075 ieee80211_ifdetach(&sc->sc_ic); 4076 if_detach(ifp); 4077 break; 4078 case FINISH_ID_STA: 4079 case FINISH_RF_ATTACH: 4080 rtw_rf_destroy(sc->sc_rf); 4081 sc->sc_rf = NULL; 4082 /*FALLTHROUGH*/ 4083 case FINISH_PARSE_SROM: 4084 case FINISH_READ_SROM: 4085 rtw_srom_free(&sc->sc_srom); 4086 /*FALLTHROUGH*/ 4087 case FINISH_RESET: 4088 case FINISH_RXMAPS_CREATE: 4089 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4090 RTW_RXQLEN); 4091 /*FALLTHROUGH*/ 4092 case FINISH_TXMAPS_CREATE: 4093 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4094 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4095 sc->sc_txsoft_blk[pri].tsb_desc, 4096 sc->sc_txsoft_blk[pri].tsb_ndesc); 4097 } 4098 /*FALLTHROUGH*/ 4099 case FINISH_TXDESCBLK_SETUP: 4100 case FINISH_TXCTLBLK_SETUP: 4101 rtw_txsoft_blk_cleanup_all(sc); 4102 /*FALLTHROUGH*/ 4103 case FINISH_DESCMAP_LOAD: 4104 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4105 /*FALLTHROUGH*/ 4106 case FINISH_DESCMAP_CREATE: 4107 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4108 /*FALLTHROUGH*/ 4109 case FINISH_DESC_MAP: 4110 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 4111 sizeof(struct rtw_descs)); 4112 /*FALLTHROUGH*/ 4113 case FINISH_DESC_ALLOC: 4114 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4115 sc->sc_desc_nsegs); 4116 /*FALLTHROUGH*/ 4117 case DETACHED: 4118 NEXT_ATTACH_STATE(sc, DETACHED); 4119 break; 4120 } 4121 return 0; 4122 } 4123 4124 int 4125 rtw_activate(struct device *self, enum devact act) 4126 { 4127 struct rtw_softc *sc = (struct rtw_softc *)self; 4128 int rc = 0, s; 4129 4130 s = splnet(); 4131 switch (act) { 4132 case DVACT_ACTIVATE: 4133 rc = EOPNOTSUPP; 4134 break; 4135 4136 case DVACT_DEACTIVATE: 4137 if_deactivate(&sc->sc_if); 4138 break; 4139 } 4140 splx(s); 4141 return rc; 4142 } 4143
Indexes created Sun Sep 28 16:09:52 GMT 2025