rtw.c revision 1.6
1 /* $NetBSD: rtw.c,v 1.6 2004/12/20 00:16:21 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.6 2004/12/20 00:16:21 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #if 0 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #endif 54 #include <sys/time.h> 55 #include <sys/types.h> 56 57 #include <machine/endian.h> 58 #include <machine/bus.h> 59 #include <machine/intr.h> /* splnet */ 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_compat.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <dev/ic/rtwreg.h> 76 #include <dev/ic/rtwvar.h> 77 #include <dev/ic/rtwphyio.h> 78 #include <dev/ic/rtwphy.h> 79 80 #include <dev/ic/smc93cx6var.h> 81 82 #define KASSERT2(__cond, __msg) \ 83 do { \ 84 if (!(__cond)) \ 85 panic __msg ; \ 86 } while (0) 87 88 int rtw_rfprog_fallback = 0; 89 int rtw_host_rfio = 0; 90 int rtw_flush_rfio = 1; 91 int rtw_rfio_delay = 0; 92 93 #ifdef RTW_DEBUG 94 int rtw_debug = 2; 95 #endif /* RTW_DEBUG */ 96 97 #define NEXT_ATTACH_STATE(sc, state) do { \ 98 DPRINTF(sc, ("%s: attach state %s\n", __func__, #state)); \ 99 sc->sc_attach_state = state; \ 100 } while (0) 101 102 int rtw_dwelltime = 1000; /* milliseconds */ 103 104 static void rtw_start(struct ifnet *); 105 106 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 107 static int rtw_sysctl_verify_rfio_delay(SYSCTLFN_PROTO); 108 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 109 #ifdef RTW_DEBUG 110 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 111 #endif /* RTW_DEBUG */ 112 113 /* 114 * Setup sysctl(3) MIB, hw.rtw.* 115 * 116 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 117 */ 118 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 119 { 120 int rc; 121 struct sysctlnode *cnode, *rnode; 122 123 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 124 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 125 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 126 goto err; 127 128 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 129 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 130 "Realtek RTL818x 802.11 controls", 131 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 132 goto err; 133 134 #ifdef RTW_DEBUG 135 /* control debugging printfs */ 136 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 137 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 138 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 139 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 140 CTL_CREATE, CTL_EOL)) != 0) 141 goto err; 142 #endif /* RTW_DEBUG */ 143 /* set fallback RF programming method */ 144 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 145 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 146 "rfprog_fallback", 147 SYSCTL_DESCR("Set fallback RF programming method"), 148 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 149 CTL_CREATE, CTL_EOL)) != 0) 150 goto err; 151 152 /* force host to flush I/O by reading RTW_PHYADDR */ 153 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 154 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 155 "flush_rfio", SYSCTL_DESCR("Enable RF I/O flushing"), 156 rtw_sysctl_verify_rfio, 0, &rtw_flush_rfio, 0, 157 CTL_CREATE, CTL_EOL)) != 0) 158 goto err; 159 160 /* force host to control RF I/O bus */ 161 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 162 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 163 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 164 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 165 CTL_CREATE, CTL_EOL)) != 0) 166 goto err; 167 168 /* control RF I/O delay */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfio_delay", SYSCTL_DESCR("Set RF I/O delay"), 172 rtw_sysctl_verify_rfio_delay, 0, &rtw_rfio_delay, 0, 173 CTL_CREATE, CTL_EOL)) != 0) 174 goto err; 175 176 return; 177 err: 178 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 179 } 180 181 static int 182 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 183 { 184 int error, t; 185 struct sysctlnode node; 186 187 node = *rnode; 188 t = *(int*)rnode->sysctl_data; 189 node.sysctl_data = &t; 190 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 191 if (error || newp == NULL) 192 return (error); 193 194 if (t < lower || t > upper) 195 return (EINVAL); 196 197 *(int*)rnode->sysctl_data = t; 198 199 return (0); 200 } 201 202 static int 203 rtw_sysctl_verify_rfio_delay(SYSCTLFN_ARGS) 204 { 205 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1000000); 206 } 207 208 static int 209 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 210 { 211 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 212 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 213 } 214 215 static int 216 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 217 { 218 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1); 219 } 220 221 #ifdef RTW_DEBUG 222 static int 223 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 224 { 225 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 2); 226 } 227 228 static void 229 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 230 { 231 #define PRINTREG32(sc, reg) \ 232 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 233 dvname, reg, RTW_READ(regs, reg))) 234 235 #define PRINTREG16(sc, reg) \ 236 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %04x\n", \ 237 dvname, reg, RTW_READ16(regs, reg))) 238 239 #define PRINTREG8(sc, reg) \ 240 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %02x\n", \ 241 dvname, reg, RTW_READ8(regs, reg))) 242 243 RTW_DPRINTF2(("%s: %s\n", dvname, where)); 244 245 PRINTREG32(regs, RTW_IDR0); 246 PRINTREG32(regs, RTW_IDR1); 247 PRINTREG32(regs, RTW_MAR0); 248 PRINTREG32(regs, RTW_MAR1); 249 PRINTREG32(regs, RTW_TSFTRL); 250 PRINTREG32(regs, RTW_TSFTRH); 251 PRINTREG32(regs, RTW_TLPDA); 252 PRINTREG32(regs, RTW_TNPDA); 253 PRINTREG32(regs, RTW_THPDA); 254 PRINTREG32(regs, RTW_TCR); 255 PRINTREG32(regs, RTW_RCR); 256 PRINTREG32(regs, RTW_TINT); 257 PRINTREG32(regs, RTW_TBDA); 258 PRINTREG32(regs, RTW_ANAPARM); 259 PRINTREG32(regs, RTW_BB); 260 PRINTREG32(regs, RTW_PHYCFG); 261 PRINTREG32(regs, RTW_WAKEUP0L); 262 PRINTREG32(regs, RTW_WAKEUP0H); 263 PRINTREG32(regs, RTW_WAKEUP1L); 264 PRINTREG32(regs, RTW_WAKEUP1H); 265 PRINTREG32(regs, RTW_WAKEUP2LL); 266 PRINTREG32(regs, RTW_WAKEUP2LH); 267 PRINTREG32(regs, RTW_WAKEUP2HL); 268 PRINTREG32(regs, RTW_WAKEUP2HH); 269 PRINTREG32(regs, RTW_WAKEUP3LL); 270 PRINTREG32(regs, RTW_WAKEUP3LH); 271 PRINTREG32(regs, RTW_WAKEUP3HL); 272 PRINTREG32(regs, RTW_WAKEUP3HH); 273 PRINTREG32(regs, RTW_WAKEUP4LL); 274 PRINTREG32(regs, RTW_WAKEUP4LH); 275 PRINTREG32(regs, RTW_WAKEUP4HL); 276 PRINTREG32(regs, RTW_WAKEUP4HH); 277 PRINTREG32(regs, RTW_DK0); 278 PRINTREG32(regs, RTW_DK1); 279 PRINTREG32(regs, RTW_DK2); 280 PRINTREG32(regs, RTW_DK3); 281 PRINTREG32(regs, RTW_RETRYCTR); 282 PRINTREG32(regs, RTW_RDSAR); 283 PRINTREG32(regs, RTW_FER); 284 PRINTREG32(regs, RTW_FEMR); 285 PRINTREG32(regs, RTW_FPSR); 286 PRINTREG32(regs, RTW_FFER); 287 288 /* 16-bit registers */ 289 PRINTREG16(regs, RTW_BRSR); 290 PRINTREG16(regs, RTW_IMR); 291 PRINTREG16(regs, RTW_ISR); 292 PRINTREG16(regs, RTW_BCNITV); 293 PRINTREG16(regs, RTW_ATIMWND); 294 PRINTREG16(regs, RTW_BINTRITV); 295 PRINTREG16(regs, RTW_ATIMTRITV); 296 PRINTREG16(regs, RTW_CRC16ERR); 297 PRINTREG16(regs, RTW_CRC0); 298 PRINTREG16(regs, RTW_CRC1); 299 PRINTREG16(regs, RTW_CRC2); 300 PRINTREG16(regs, RTW_CRC3); 301 PRINTREG16(regs, RTW_CRC4); 302 PRINTREG16(regs, RTW_CWR); 303 304 /* 8-bit registers */ 305 PRINTREG8(regs, RTW_CR); 306 PRINTREG8(regs, RTW_9346CR); 307 PRINTREG8(regs, RTW_CONFIG0); 308 PRINTREG8(regs, RTW_CONFIG1); 309 PRINTREG8(regs, RTW_CONFIG2); 310 PRINTREG8(regs, RTW_MSR); 311 PRINTREG8(regs, RTW_CONFIG3); 312 PRINTREG8(regs, RTW_CONFIG4); 313 PRINTREG8(regs, RTW_TESTR); 314 PRINTREG8(regs, RTW_PSR); 315 PRINTREG8(regs, RTW_SCR); 316 PRINTREG8(regs, RTW_PHYDELAY); 317 PRINTREG8(regs, RTW_CRCOUNT); 318 PRINTREG8(regs, RTW_PHYADDR); 319 PRINTREG8(regs, RTW_PHYDATAW); 320 PRINTREG8(regs, RTW_PHYDATAR); 321 PRINTREG8(regs, RTW_CONFIG5); 322 PRINTREG8(regs, RTW_TPPOLL); 323 324 PRINTREG16(regs, RTW_BSSID16); 325 PRINTREG32(regs, RTW_BSSID32); 326 #undef PRINTREG32 327 #undef PRINTREG16 328 #undef PRINTREG8 329 } 330 #endif /* RTW_DEBUG */ 331 332 void 333 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 334 { 335 struct rtw_regs *regs = &sc->sc_regs; 336 337 u_int32_t tcr; 338 tcr = RTW_READ(regs, RTW_TCR); 339 tcr &= ~RTW_TCR_LBK_MASK; 340 if (enable) 341 tcr |= RTW_TCR_LBK_CONT; 342 else 343 tcr |= RTW_TCR_LBK_NORMAL; 344 RTW_WRITE(regs, RTW_TCR, tcr); 345 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 346 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 347 rtw_txdac_enable(sc, !enable); 348 rtw_set_access(sc, RTW_ACCESS_ANAPARM); /* XXX Voodoo from Linux. */ 349 rtw_set_access(sc, RTW_ACCESS_NONE); 350 } 351 352 static const char * 353 rtw_access_string(enum rtw_access access) 354 { 355 switch (access) { 356 case RTW_ACCESS_NONE: 357 return "none"; 358 case RTW_ACCESS_CONFIG: 359 return "config"; 360 case RTW_ACCESS_ANAPARM: 361 return "anaparm"; 362 default: 363 return "unknown"; 364 } 365 } 366 367 static void 368 rtw_set_access1(struct rtw_regs *regs, 369 enum rtw_access oaccess, enum rtw_access naccess) 370 { 371 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 372 KASSERT(oaccess >= RTW_ACCESS_NONE && oaccess <= RTW_ACCESS_ANAPARM); 373 374 if (naccess == oaccess) 375 return; 376 377 switch (naccess) { 378 case RTW_ACCESS_NONE: 379 switch (oaccess) { 380 case RTW_ACCESS_ANAPARM: 381 rtw_anaparm_enable(regs, 0); 382 /*FALLTHROUGH*/ 383 case RTW_ACCESS_CONFIG: 384 rtw_config0123_enable(regs, 0); 385 /*FALLTHROUGH*/ 386 case RTW_ACCESS_NONE: 387 break; 388 } 389 break; 390 case RTW_ACCESS_CONFIG: 391 switch (oaccess) { 392 case RTW_ACCESS_NONE: 393 rtw_config0123_enable(regs, 1); 394 /*FALLTHROUGH*/ 395 case RTW_ACCESS_CONFIG: 396 break; 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 break; 400 } 401 break; 402 case RTW_ACCESS_ANAPARM: 403 switch (oaccess) { 404 case RTW_ACCESS_NONE: 405 rtw_config0123_enable(regs, 1); 406 /*FALLTHROUGH*/ 407 case RTW_ACCESS_CONFIG: 408 rtw_anaparm_enable(regs, 1); 409 /*FALLTHROUGH*/ 410 case RTW_ACCESS_ANAPARM: 411 break; 412 } 413 break; 414 } 415 } 416 417 void 418 rtw_set_access(struct rtw_softc *sc, enum rtw_access access) 419 { 420 rtw_set_access1(&sc->sc_regs, sc->sc_access, access); 421 RTW_DPRINTF(("%s: access %s -> %s\n", sc->sc_dev.dv_xname, 422 rtw_access_string(sc->sc_access), 423 rtw_access_string(access))); 424 sc->sc_access = access; 425 } 426 427 /* 428 * Enable registers, switch register banks. 429 */ 430 void 431 rtw_config0123_enable(struct rtw_regs *regs, int enable) 432 { 433 u_int8_t ecr; 434 ecr = RTW_READ8(regs, RTW_9346CR); 435 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 436 if (enable) 437 ecr |= RTW_9346CR_EEM_CONFIG; 438 else 439 ecr |= RTW_9346CR_EEM_NORMAL; 440 RTW_WRITE8(regs, RTW_9346CR, ecr); 441 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 442 } 443 444 /* requires rtw_config0123_enable(, 1) */ 445 void 446 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 447 { 448 u_int8_t cfg3; 449 450 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 451 cfg3 |= RTW_CONFIG3_CLKRUNEN; 452 if (enable) 453 cfg3 |= RTW_CONFIG3_PARMEN; 454 else 455 cfg3 &= ~RTW_CONFIG3_PARMEN; 456 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 457 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 458 } 459 460 /* requires rtw_anaparm_enable(, 1) */ 461 void 462 rtw_txdac_enable(struct rtw_softc *sc, int enable) 463 { 464 u_int32_t anaparm; 465 struct rtw_regs *regs = &sc->sc_regs; 466 467 anaparm = RTW_READ(regs, RTW_ANAPARM); 468 if (enable) 469 anaparm &= ~RTW_ANAPARM_TXDACOFF; 470 else 471 anaparm |= RTW_ANAPARM_TXDACOFF; 472 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 473 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 474 } 475 476 static __inline int 477 rtw_chip_reset1(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 478 { 479 u_int8_t cr; 480 int i; 481 482 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 483 484 RTW_WBR(regs, RTW_CR, RTW_CR); 485 486 for (i = 0; i < 10000; i++) { 487 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 488 RTW_DPRINTF(("%s: reset in %dus\n", *dvname, i)); 489 return 0; 490 } 491 RTW_RBR(regs, RTW_CR, RTW_CR); 492 DELAY(1); /* 1us */ 493 } 494 495 printf("%s: reset failed\n", *dvname); 496 return ETIMEDOUT; 497 } 498 499 static __inline int 500 rtw_chip_reset(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 501 { 502 uint32_t tcr; 503 504 /* from Linux driver */ 505 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 506 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 507 508 RTW_WRITE(regs, RTW_TCR, tcr); 509 510 RTW_WBW(regs, RTW_CR, RTW_TCR); 511 512 return rtw_chip_reset1(regs, dvname); 513 } 514 515 static __inline int 516 rtw_recall_eeprom(struct rtw_regs *regs, char (*dvname)[IFNAMSIZ]) 517 { 518 int i; 519 u_int8_t ecr; 520 521 ecr = RTW_READ8(regs, RTW_9346CR); 522 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 523 RTW_WRITE8(regs, RTW_9346CR, ecr); 524 525 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 526 527 /* wait 2.5ms for completion */ 528 for (i = 0; i < 25; i++) { 529 ecr = RTW_READ8(regs, RTW_9346CR); 530 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 531 RTW_DPRINTF(("%s: recall EEPROM in %dus\n", *dvname, 532 i * 100)); 533 return 0; 534 } 535 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 536 DELAY(100); 537 } 538 printf("%s: recall EEPROM failed\n", *dvname); 539 return ETIMEDOUT; 540 } 541 542 static __inline int 543 rtw_reset(struct rtw_softc *sc) 544 { 545 int rc; 546 uint8_t config1; 547 548 if ((rc = rtw_chip_reset(&sc->sc_regs, &sc->sc_dev.dv_xname)) != 0) 549 return rc; 550 551 if ((rc = rtw_recall_eeprom(&sc->sc_regs, &sc->sc_dev.dv_xname)) != 0) 552 ; 553 554 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 555 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 556 /* TBD turn off maximum power saving? */ 557 558 return 0; 559 } 560 561 static __inline int 562 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txctl *descs, 563 u_int ndescs) 564 { 565 int i, rc = 0; 566 for (i = 0; i < ndescs; i++) { 567 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 568 0, 0, &descs[i].stx_dmamap); 569 if (rc != 0) 570 break; 571 } 572 return rc; 573 } 574 575 static __inline int 576 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 577 u_int ndescs) 578 { 579 int i, rc = 0; 580 for (i = 0; i < ndescs; i++) { 581 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 582 &descs[i].srx_dmamap); 583 if (rc != 0) 584 break; 585 } 586 return rc; 587 } 588 589 static __inline void 590 rtw_rxctls_setup(struct rtw_rxctl *descs) 591 { 592 int i; 593 for (i = 0; i < RTW_RXQLEN; i++) 594 descs[i].srx_mbuf = NULL; 595 } 596 597 static __inline void 598 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 599 u_int ndescs) 600 { 601 int i; 602 for (i = 0; i < ndescs; i++) { 603 if (descs[i].srx_dmamap != NULL) 604 bus_dmamap_destroy(dmat, descs[i].srx_dmamap); 605 } 606 } 607 608 static __inline void 609 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txctl *descs, 610 u_int ndescs) 611 { 612 int i; 613 for (i = 0; i < ndescs; i++) { 614 if (descs[i].stx_dmamap != NULL) 615 bus_dmamap_destroy(dmat, descs[i].stx_dmamap); 616 } 617 } 618 619 static __inline void 620 rtw_srom_free(struct rtw_srom *sr) 621 { 622 sr->sr_size = 0; 623 if (sr->sr_content == NULL) 624 return; 625 free(sr->sr_content, M_DEVBUF); 626 sr->sr_content = NULL; 627 } 628 629 static void 630 rtw_srom_defaults(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 631 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, char (*dvname)[IFNAMSIZ]) 632 { 633 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 634 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 635 *rcr |= RTW_RCR_ENCS1; 636 *rfchipid = RTW_RFCHIPID_PHILIPS; 637 } 638 639 static int 640 rtw_srom_parse(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 641 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, enum rtw_locale *locale, 642 char (*dvname)[IFNAMSIZ]) 643 { 644 int i; 645 const char *rfname, *paname; 646 char scratch[sizeof("unknown 0xXX")]; 647 u_int16_t version; 648 u_int8_t mac[IEEE80211_ADDR_LEN]; 649 650 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 651 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 652 653 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 654 printf("%s: SROM version %d.%d", *dvname, version >> 8, version & 0xff); 655 656 if (version <= 0x0101) { 657 printf(" is not understood, limping along with defaults\n"); 658 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr, 659 dvname); 660 return 0; 661 } 662 printf("\n"); 663 664 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 665 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 666 667 RTW_DPRINTF(("%s: EEPROM MAC %s\n", *dvname, ether_sprintf(mac))); 668 669 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 670 671 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 672 *flags |= RTW_F_ANTDIV; 673 674 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) != 0) 675 *flags |= RTW_F_DIGPHY; 676 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 677 *flags |= RTW_F_DFLANTB; 678 679 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 680 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 681 682 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 683 switch (*rfchipid) { 684 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 685 rfname = "GCT GRF5101"; 686 paname = "Winspring WS9901"; 687 break; 688 case RTW_RFCHIPID_MAXIM: 689 rfname = "Maxim MAX2820"; /* guess */ 690 paname = "Maxim MAX2422"; /* guess */ 691 break; 692 case RTW_RFCHIPID_INTERSIL: 693 rfname = "Intersil HFA3873"; /* guess */ 694 paname = "Intersil <unknown>"; 695 break; 696 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 697 rfname = "Philips SA2400A"; 698 paname = "Philips SA2411"; 699 break; 700 case RTW_RFCHIPID_RFMD: 701 /* this is the same front-end as an atw(4)! */ 702 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 703 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 704 "SYN: Silicon Labs Si4126"; /* inferred from 705 * reference driver 706 */ 707 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 708 break; 709 case RTW_RFCHIPID_RESERVED: 710 rfname = paname = "reserved"; 711 break; 712 default: 713 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 714 rfname = paname = scratch; 715 } 716 printf("%s: RF: %s, PA: %s\n", *dvname, rfname, paname); 717 718 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 719 case RTW_CONFIG0_GL_USA: 720 *locale = RTW_LOCALE_USA; 721 break; 722 case RTW_CONFIG0_GL_EUROPE: 723 *locale = RTW_LOCALE_EUROPE; 724 break; 725 case RTW_CONFIG0_GL_JAPAN: 726 *locale = RTW_LOCALE_JAPAN; 727 break; 728 default: 729 *locale = RTW_LOCALE_UNKNOWN; 730 break; 731 } 732 return 0; 733 } 734 735 /* Returns -1 on failure. */ 736 static int 737 rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr, 738 char (*dvname)[IFNAMSIZ]) 739 { 740 int rc; 741 struct seeprom_descriptor sd; 742 u_int8_t ecr; 743 744 (void)memset(&sd, 0, sizeof(sd)); 745 746 ecr = RTW_READ8(regs, RTW_9346CR); 747 748 if ((flags & RTW_F_9356SROM) != 0) { 749 RTW_DPRINTF(("%s: 93c56 SROM\n", *dvname)); 750 sr->sr_size = 256; 751 sd.sd_chip = C56_66; 752 } else { 753 RTW_DPRINTF(("%s: 93c46 SROM\n", *dvname)); 754 sr->sr_size = 128; 755 sd.sd_chip = C46; 756 } 757 758 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 759 RTW_9346CR_EEM_MASK); 760 ecr |= RTW_9346CR_EEM_PROGRAM; 761 762 RTW_WRITE8(regs, RTW_9346CR, ecr); 763 764 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 765 766 if (sr->sr_content == NULL) { 767 printf("%s: unable to allocate SROM buffer\n", *dvname); 768 return ENOMEM; 769 } 770 771 (void)memset(sr->sr_content, 0, sr->sr_size); 772 773 /* RTL8180 has a single 8-bit register for controlling the 774 * 93cx6 SROM. There is no "ready" bit. The RTL8180 775 * input/output sense is the reverse of read_seeprom's. 776 */ 777 sd.sd_tag = regs->r_bt; 778 sd.sd_bsh = regs->r_bh; 779 sd.sd_regsize = 1; 780 sd.sd_control_offset = RTW_9346CR; 781 sd.sd_status_offset = RTW_9346CR; 782 sd.sd_dataout_offset = RTW_9346CR; 783 sd.sd_CK = RTW_9346CR_EESK; 784 sd.sd_CS = RTW_9346CR_EECS; 785 sd.sd_DI = RTW_9346CR_EEDO; 786 sd.sd_DO = RTW_9346CR_EEDI; 787 /* make read_seeprom enter EEPROM read/write mode */ 788 sd.sd_MS = ecr; 789 sd.sd_RDY = 0; 790 #if 0 791 sd.sd_clkdelay = 50; 792 #endif 793 794 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 795 printf("%s: could not read SROM\n", *dvname); 796 free(sr->sr_content, M_DEVBUF); 797 sr->sr_content = NULL; 798 return -1; /* XXX */ 799 } 800 801 /* end EEPROM read/write mode */ 802 RTW_WRITE8(regs, RTW_9346CR, 803 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 804 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 805 806 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 807 return rc; 808 809 #ifdef RTW_DEBUG 810 { 811 int i; 812 RTW_DPRINTF(("\n%s: serial ROM:\n\t", *dvname)); 813 for (i = 0; i < sr->sr_size/2; i++) { 814 if (((i % 8) == 0) && (i != 0)) 815 RTW_DPRINTF(("\n\t")); 816 RTW_DPRINTF((" %04x", sr->sr_content[i])); 817 } 818 RTW_DPRINTF(("\n")); 819 } 820 #endif /* RTW_DEBUG */ 821 return 0; 822 } 823 824 static void 825 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 826 const char *dvname) 827 { 828 u_int8_t cfg4; 829 const char *method; 830 831 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 832 833 switch (rfchipid) { 834 default: 835 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 836 method = "fallback"; 837 break; 838 case RTW_RFCHIPID_INTERSIL: 839 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 840 method = "Intersil"; 841 break; 842 case RTW_RFCHIPID_PHILIPS: 843 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 844 method = "Philips"; 845 break; 846 case RTW_RFCHIPID_RFMD: 847 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 848 method = "RFMD"; 849 break; 850 } 851 852 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 853 854 printf("%s: %s RF programming method, %#02x\n", dvname, method, 855 RTW_READ8(regs, RTW_CONFIG4)); 856 } 857 858 #if 0 859 static __inline int 860 rtw_identify_rf(struct rtw_regs *regs, enum rtw_rftype *rftype, 861 char (*dvname)[IFNAMSIZ]) 862 { 863 u_int8_t cfg4; 864 const char *name; 865 866 cfg4 = RTW_READ8(regs, RTW_CONFIG4); 867 868 switch (cfg4 & RTW_CONFIG4_RFTYPE_MASK) { 869 case RTW_CONFIG4_RFTYPE_PHILIPS: 870 *rftype = RTW_RFTYPE_PHILIPS; 871 name = "Philips"; 872 break; 873 case RTW_CONFIG4_RFTYPE_INTERSIL: 874 *rftype = RTW_RFTYPE_INTERSIL; 875 name = "Intersil"; 876 break; 877 case RTW_CONFIG4_RFTYPE_RFMD: 878 *rftype = RTW_RFTYPE_RFMD; 879 name = "RFMD"; 880 break; 881 default: 882 name = "<unknown>"; 883 return ENXIO; 884 } 885 886 printf("%s: RF prog type %s\n", *dvname, name); 887 return 0; 888 } 889 #endif 890 891 static __inline void 892 rtw_init_channels(enum rtw_locale locale, 893 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 894 char (*dvname)[IFNAMSIZ]) 895 { 896 int i; 897 const char *name = NULL; 898 #define ADD_CHANNEL(_chans, _chan) do { \ 899 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 900 (*_chans)[_chan].ic_freq = \ 901 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 902 } while (0) 903 904 switch (locale) { 905 case RTW_LOCALE_USA: /* 1-11 */ 906 name = "USA"; 907 for (i = 1; i <= 11; i++) 908 ADD_CHANNEL(chans, i); 909 break; 910 case RTW_LOCALE_JAPAN: /* 1-14 */ 911 name = "Japan"; 912 ADD_CHANNEL(chans, 14); 913 for (i = 1; i <= 14; i++) 914 ADD_CHANNEL(chans, i); 915 break; 916 case RTW_LOCALE_EUROPE: /* 1-13 */ 917 name = "Europe"; 918 for (i = 1; i <= 13; i++) 919 ADD_CHANNEL(chans, i); 920 break; 921 default: /* 10-11 allowed by most countries */ 922 name = "<unknown>"; 923 for (i = 10; i <= 11; i++) 924 ADD_CHANNEL(chans, i); 925 break; 926 } 927 printf("%s: Geographic Location %s\n", *dvname, name); 928 #undef ADD_CHANNEL 929 } 930 931 static __inline void 932 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 933 char (*dvname)[IFNAMSIZ]) 934 { 935 u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 936 937 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 938 case RTW_CONFIG0_GL_USA: 939 *locale = RTW_LOCALE_USA; 940 break; 941 case RTW_CONFIG0_GL_JAPAN: 942 *locale = RTW_LOCALE_JAPAN; 943 break; 944 case RTW_CONFIG0_GL_EUROPE: 945 *locale = RTW_LOCALE_EUROPE; 946 break; 947 default: 948 *locale = RTW_LOCALE_UNKNOWN; 949 break; 950 } 951 } 952 953 static __inline int 954 rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN], 955 char (*dvname)[IFNAMSIZ]) 956 { 957 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 958 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 959 }; 960 u_int32_t idr0 = RTW_READ(regs, RTW_IDR0), 961 idr1 = RTW_READ(regs, RTW_IDR1); 962 963 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 964 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 965 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 966 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 967 968 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 969 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 970 971 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 972 printf("%s: could not get mac address, attach failed\n", 973 *dvname); 974 return ENXIO; 975 } 976 977 printf("%s: 802.11 address %s\n", *dvname, ether_sprintf(*addr)); 978 979 return 0; 980 } 981 982 static u_int8_t 983 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 984 struct ieee80211_channel *chan) 985 { 986 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 987 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 988 ("%s: channel %d out of range", __func__, 989 idx - RTW_SR_TXPOWER1 + 1)); 990 return RTW_SR_GET(sr, idx); 991 } 992 993 static void 994 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *htcs) 995 { 996 int pri; 997 u_int ndesc[RTW_NTXPRI] = 998 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 999 1000 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1001 htcs[pri].htc_nfree = ndesc[pri]; 1002 htcs[pri].htc_next = 0; 1003 } 1004 } 1005 1006 static int 1007 rtw_txctl_blk_init(struct rtw_txctl_blk *stc) 1008 { 1009 int i; 1010 struct rtw_txctl *stx; 1011 1012 SIMPLEQ_INIT(&stc->stc_dirtyq); 1013 SIMPLEQ_INIT(&stc->stc_freeq); 1014 for (i = 0; i < stc->stc_ndesc; i++) { 1015 stx = &stc->stc_desc[i]; 1016 stx->stx_mbuf = NULL; 1017 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1018 } 1019 return 0; 1020 } 1021 1022 static void 1023 rtw_txctl_blk_init_all(struct rtw_txctl_blk *stcs) 1024 { 1025 int pri; 1026 for (pri = 0; pri < RTW_NTXPRI; pri++) 1027 rtw_txctl_blk_init(&stcs[pri]); 1028 } 1029 1030 static __inline void 1031 rtw_rxdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, u_int desc0, u_int 1032 nsync, int ops) 1033 { 1034 /* sync to end of ring */ 1035 if (desc0 + nsync > RTW_NRXDESC) { 1036 bus_dmamap_sync(dmat, dmap, 1037 offsetof(struct rtw_descs, hd_rx[desc0]), 1038 sizeof(struct rtw_rxdesc) * (RTW_NRXDESC - desc0), ops); 1039 nsync -= (RTW_NRXDESC - desc0); 1040 desc0 = 0; 1041 } 1042 1043 /* sync what remains */ 1044 bus_dmamap_sync(dmat, dmap, 1045 offsetof(struct rtw_descs, hd_rx[desc0]), 1046 sizeof(struct rtw_rxdesc) * nsync, ops); 1047 } 1048 1049 static void 1050 rtw_txdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1051 struct rtw_txdesc_blk *htc, u_int desc0, u_int nsync, int ops) 1052 { 1053 /* sync to end of ring */ 1054 if (desc0 + nsync > htc->htc_ndesc) { 1055 bus_dmamap_sync(dmat, dmap, 1056 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1057 sizeof(struct rtw_txdesc) * (htc->htc_ndesc - desc0), 1058 ops); 1059 nsync -= (htc->htc_ndesc - desc0); 1060 desc0 = 0; 1061 } 1062 1063 /* sync what remains */ 1064 bus_dmamap_sync(dmat, dmap, 1065 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1066 sizeof(struct rtw_txdesc) * nsync, ops); 1067 } 1068 1069 static void 1070 rtw_txdescs_sync_all(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1071 struct rtw_txdesc_blk *htcs) 1072 { 1073 int pri; 1074 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1075 rtw_txdescs_sync(dmat, dmap, 1076 &htcs[pri], 0, htcs[pri].htc_ndesc, 1077 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1078 } 1079 } 1080 1081 static void 1082 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxctl *desc) 1083 { 1084 int i; 1085 struct rtw_rxctl *srx; 1086 1087 for (i = 0; i < RTW_NRXDESC; i++) { 1088 srx = &desc[i]; 1089 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, 1090 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1091 bus_dmamap_unload(dmat, srx->srx_dmamap); 1092 m_freem(srx->srx_mbuf); 1093 srx->srx_mbuf = NULL; 1094 } 1095 } 1096 1097 static __inline int 1098 rtw_rxbuf_alloc(bus_dma_tag_t dmat, struct rtw_rxctl *srx) 1099 { 1100 int rc; 1101 struct mbuf *m; 1102 1103 MGETHDR(m, M_DONTWAIT, MT_DATA); 1104 if (m == NULL) 1105 return ENOMEM; 1106 1107 MCLGET(m, M_DONTWAIT); 1108 if (m == NULL) 1109 return ENOMEM; 1110 1111 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1112 1113 rc = bus_dmamap_load_mbuf(dmat, srx->srx_dmamap, m, BUS_DMA_NOWAIT); 1114 if (rc != 0) 1115 return rc; 1116 1117 srx->srx_mbuf = m; 1118 1119 return 0; 1120 } 1121 1122 static int 1123 rtw_rxctl_init_all(bus_dma_tag_t dmat, struct rtw_rxctl *desc, 1124 u_int *next, char (*dvname)[IFNAMSIZ]) 1125 { 1126 int i, rc; 1127 struct rtw_rxctl *srx; 1128 1129 for (i = 0; i < RTW_NRXDESC; i++) { 1130 srx = &desc[i]; 1131 if ((rc = rtw_rxbuf_alloc(dmat, srx)) == 0) 1132 continue; 1133 printf("%s: failed rtw_rxbuf_alloc after %d buffers, rc = %d\n", 1134 *dvname, i, rc); 1135 if (i == 0) { 1136 rtw_rxbufs_release(dmat, desc); 1137 return rc; 1138 } 1139 } 1140 *next = 0; 1141 return 0; 1142 } 1143 1144 static __inline void 1145 rtw_rxdesc_init(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1146 struct rtw_rxdesc *hrx, struct rtw_rxctl *srx, int idx) 1147 { 1148 int is_last = (idx == RTW_NRXDESC - 1); 1149 uint32_t ctl; 1150 1151 hrx->hrx_buf = htole32(srx->srx_dmamap->dm_segs[0].ds_addr); 1152 1153 ctl = LSHIFT(srx->srx_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1154 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1155 1156 if (is_last) 1157 ctl |= RTW_RXCTL_EOR; 1158 1159 hrx->hrx_ctl = htole32(ctl); 1160 1161 /* sync the mbuf */ 1162 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, srx->srx_dmamap->dm_mapsize, 1163 BUS_DMASYNC_PREREAD); 1164 1165 /* sync the descriptor */ 1166 bus_dmamap_sync(dmat, dmam, RTW_DESC_OFFSET(hd_rx, idx), 1167 sizeof(struct rtw_rxdesc), 1168 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1169 } 1170 1171 static void 1172 rtw_rxdesc_init_all(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1173 struct rtw_rxdesc *desc, struct rtw_rxctl *ctl) 1174 { 1175 int i; 1176 struct rtw_rxdesc *hrx; 1177 struct rtw_rxctl *srx; 1178 1179 for (i = 0; i < RTW_NRXDESC; i++) { 1180 hrx = &desc[i]; 1181 srx = &ctl[i]; 1182 rtw_rxdesc_init(dmat, dmam, hrx, srx, i); 1183 } 1184 } 1185 1186 static void 1187 rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable) 1188 { 1189 u_int8_t cr; 1190 1191 RTW_DPRINTF(("%s: %s 0x%02x\n", __func__, 1192 enable ? "enable" : "disable", flags)); 1193 1194 cr = RTW_READ8(regs, RTW_CR); 1195 1196 /* XXX reference source does not enable MULRW */ 1197 #if 0 1198 /* enable PCI Read/Write Multiple */ 1199 cr |= RTW_CR_MULRW; 1200 #endif 1201 1202 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1203 if (enable) 1204 cr |= flags; 1205 else 1206 cr &= ~flags; 1207 RTW_WRITE8(regs, RTW_CR, cr); 1208 RTW_SYNC(regs, RTW_CR, RTW_CR); 1209 } 1210 1211 static void 1212 rtw_intr_rx(struct rtw_softc *sc, u_int16_t isr) 1213 { 1214 u_int next; 1215 int rate, rssi; 1216 u_int32_t hrssi, hstat, htsfth, htsftl; 1217 struct rtw_rxdesc *hrx; 1218 struct rtw_rxctl *srx; 1219 struct mbuf *m; 1220 1221 struct ieee80211_node *ni; 1222 struct ieee80211_frame *wh; 1223 1224 for (next = sc->sc_rxnext; ; next = (next + 1) % RTW_RXQLEN) { 1225 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1226 next, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1227 hrx = &sc->sc_rxdesc[next]; 1228 srx = &sc->sc_rxctl[next]; 1229 1230 hstat = le32toh(hrx->hrx_stat); 1231 hrssi = le32toh(hrx->hrx_rssi); 1232 htsfth = le32toh(hrx->hrx_tsfth); 1233 htsftl = le32toh(hrx->hrx_tsftl); 1234 1235 RTW_DPRINTF2(("%s: rxdesc[%d] hstat %#08x hrssi %#08x " 1236 "htsft %#08x%08x\n", __func__, next, 1237 hstat, hrssi, htsfth, htsftl)); 1238 1239 if ((hstat & RTW_RXSTAT_OWN) != 0) /* belongs to NIC */ 1240 break; 1241 1242 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1243 printf("%s: DMA error/FIFO overflow %08x, " 1244 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1245 hstat & RTW_RXSTAT_IOERROR, next); 1246 goto next; 1247 } 1248 1249 switch (hstat & RTW_RXSTAT_RATE_MASK) { 1250 case RTW_RXSTAT_RATE_1MBPS: 1251 rate = 10; 1252 break; 1253 case RTW_RXSTAT_RATE_2MBPS: 1254 rate = 20; 1255 break; 1256 case RTW_RXSTAT_RATE_5MBPS: 1257 rate = 55; 1258 break; 1259 default: 1260 #ifdef RTW_DEBUG 1261 if (rtw_debug > 1) 1262 printf("%s: interpreting rate #%d as 11 MB/s\n", 1263 sc->sc_dev.dv_xname, 1264 MASK_AND_RSHIFT(hstat, 1265 RTW_RXSTAT_RATE_MASK)); 1266 #endif /* RTW_DEBUG */ 1267 /*FALLTHROUGH*/ 1268 case RTW_RXSTAT_RATE_11MBPS: 1269 rate = 110; 1270 break; 1271 } 1272 1273 RTW_DPRINTF2(("%s: rate %d\n", __func__, rate)); 1274 1275 #ifdef RTW_DEBUG 1276 #define PRINTSTAT(flag) do { \ 1277 if ((hstat & flag) != 0) { \ 1278 printf("%s" #flag, delim); \ 1279 delim = ","; \ 1280 } \ 1281 } while (0) 1282 if (rtw_debug > 1) { 1283 const char *delim = "<"; 1284 printf("%s: ", sc->sc_dev.dv_xname); 1285 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1286 printf("status %08x<", hstat); 1287 PRINTSTAT(RTW_RXSTAT_SPLCP); 1288 PRINTSTAT(RTW_RXSTAT_MAR); 1289 PRINTSTAT(RTW_RXSTAT_PAR); 1290 PRINTSTAT(RTW_RXSTAT_BAR); 1291 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1292 PRINTSTAT(RTW_RXSTAT_CRC32); 1293 PRINTSTAT(RTW_RXSTAT_ICV); 1294 printf(">, "); 1295 } 1296 printf("rate %d.%d Mb/s, time %08x%08x\n", 1297 rate / 10, rate % 10, htsfth, htsftl); 1298 } 1299 #endif /* RTW_DEBUG */ 1300 1301 if ((hstat & RTW_RXSTAT_RES) != 0 && 1302 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1303 goto next; 1304 1305 /* if bad flags, skip descriptor */ 1306 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1307 printf("%s: too many rx segments\n", 1308 sc->sc_dev.dv_xname); 1309 goto next; 1310 } 1311 1312 m = srx->srx_mbuf; 1313 1314 /* if temporarily out of memory, re-use mbuf */ 1315 if (rtw_rxbuf_alloc(sc->sc_dmat, srx) != 0) { 1316 printf("%s: rtw_rxbuf_alloc(, %d) failed, " 1317 "dropping this packet\n", sc->sc_dev.dv_xname, 1318 next); 1319 goto next; 1320 } 1321 1322 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1323 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1324 else { 1325 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1326 /* TBD find out each front-end's LNA gain in the 1327 * front-end's units 1328 */ 1329 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1330 rssi |= 0x80; 1331 } 1332 1333 m->m_pkthdr.len = m->m_len = 1334 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1335 m->m_flags |= M_HASFCS; 1336 1337 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 1338 sc->sc_ic.ic_stats.is_rx_tooshort++; 1339 goto next; 1340 } 1341 wh = mtod(m, struct ieee80211_frame *); 1342 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1343 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1344 1345 sc->sc_tsfth = htsfth; 1346 1347 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1348 ieee80211_release_node(&sc->sc_ic, ni); 1349 next: 1350 rtw_rxdesc_init(sc->sc_dmat, sc->sc_desc_dmamap, 1351 hrx, srx, next); 1352 } 1353 sc->sc_rxnext = next; 1354 1355 return; 1356 } 1357 1358 static void 1359 rtw_txbuf_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1360 struct rtw_txctl *stx) 1361 { 1362 struct mbuf *m; 1363 struct ieee80211_node *ni; 1364 bus_dmamap_t dmamap; 1365 1366 dmamap = stx->stx_dmamap; 1367 m = stx->stx_mbuf; 1368 ni = stx->stx_ni; 1369 stx->stx_dmamap = NULL; 1370 stx->stx_mbuf = NULL; 1371 stx->stx_ni = NULL; 1372 1373 bus_dmamap_sync(dmat, dmamap, 0, dmamap->dm_mapsize, 1374 BUS_DMASYNC_POSTWRITE); 1375 bus_dmamap_unload(dmat, dmamap); 1376 m_freem(m); 1377 ieee80211_release_node(ic, ni); 1378 } 1379 1380 static void 1381 rtw_txbufs_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1382 struct rtw_txctl_blk *stc) 1383 { 1384 struct rtw_txctl *stx; 1385 1386 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1387 rtw_txbuf_release(dmat, ic, stx); 1388 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1389 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1390 } 1391 } 1392 1393 static __inline void 1394 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *htc, 1395 struct rtw_txctl *stx, int ndesc) 1396 { 1397 int data_retry, rts_retry; 1398 struct rtw_txdesc *htx0, *htxn; 1399 const char *condstring; 1400 1401 rtw_txbuf_release(sc->sc_dmat, &sc->sc_ic, stx); 1402 1403 htc->htc_nfree += ndesc; 1404 1405 htx0 = &htc->htc_desc[stx->stx_first]; 1406 htxn = &htc->htc_desc[stx->stx_last]; 1407 1408 rts_retry = MASK_AND_RSHIFT(le32toh(htx0->htx_stat), 1409 RTW_TXSTAT_RTSRETRY_MASK); 1410 data_retry = MASK_AND_RSHIFT(le32toh(htx0->htx_stat), 1411 RTW_TXSTAT_DRC_MASK); 1412 1413 sc->sc_if.if_collisions += rts_retry + data_retry; 1414 1415 if ((htx0->htx_stat & htole32(RTW_TXSTAT_TOK)) != 0) 1416 condstring = "ok"; 1417 else { 1418 sc->sc_if.if_oerrors++; 1419 condstring = "error"; 1420 } 1421 1422 DPRINTF2(sc, ("%s: stx %p txdesc[%d, %d] %s tries rts %u data %u\n", 1423 sc->sc_dev.dv_xname, stx, stx->stx_first, stx->stx_last, 1424 condstring, rts_retry, data_retry)); 1425 } 1426 1427 /* Collect transmitted packets. */ 1428 static __inline void 1429 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txctl_blk *stc, 1430 struct rtw_txdesc_blk *htc) 1431 { 1432 int ndesc; 1433 struct rtw_txctl *stx; 1434 1435 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1436 ndesc = 1 + stx->stx_last - stx->stx_first; 1437 if (stx->stx_last < stx->stx_first) 1438 ndesc += htc->htc_ndesc; 1439 1440 KASSERT(ndesc > 0); 1441 1442 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, htc, 1443 stx->stx_first, ndesc, 1444 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1445 1446 if ((htc->htc_desc[stx->stx_first].htx_stat & 1447 htole32(RTW_TXSTAT_OWN)) != 0) 1448 break; 1449 1450 rtw_collect_txpkt(sc, htc, stx, ndesc); 1451 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1452 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1453 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1454 } 1455 if (stx == NULL) 1456 stc->stc_tx_timer = 0; 1457 } 1458 1459 static void 1460 rtw_intr_tx(struct rtw_softc *sc, u_int16_t isr) 1461 { 1462 int pri; 1463 struct rtw_txctl_blk *stc; 1464 struct rtw_txdesc_blk *htc; 1465 1466 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1467 stc = &sc->sc_txctl_blk[pri]; 1468 htc = &sc->sc_txdesc_blk[pri]; 1469 1470 rtw_collect_txring(sc, stc, htc); 1471 1472 rtw_start(&sc->sc_if); 1473 } 1474 1475 /* TBD */ 1476 return; 1477 } 1478 1479 static void 1480 rtw_intr_beacon(struct rtw_softc *sc, u_int16_t isr) 1481 { 1482 /* TBD */ 1483 return; 1484 } 1485 1486 static void 1487 rtw_intr_atim(struct rtw_softc *sc) 1488 { 1489 /* TBD */ 1490 return; 1491 } 1492 1493 static void 1494 rtw_hwring_setup(struct rtw_softc *sc) 1495 { 1496 struct rtw_regs *regs = &sc->sc_regs; 1497 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1498 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1499 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1500 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1501 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1502 } 1503 1504 static void 1505 rtw_swring_setup(struct rtw_softc *sc) 1506 { 1507 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1508 1509 rtw_txctl_blk_init_all(&sc->sc_txctl_blk[0]); 1510 1511 rtw_rxctl_init_all(sc->sc_dmat, sc->sc_rxctl, &sc->sc_rxnext, 1512 &sc->sc_dev.dv_xname); 1513 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, 1514 sc->sc_rxdesc, sc->sc_rxctl); 1515 1516 rtw_txdescs_sync_all(sc->sc_dmat, sc->sc_desc_dmamap, 1517 &sc->sc_txdesc_blk[0]); 1518 #if 0 /* redundant with rtw_rxdesc_init_all */ 1519 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1520 0, RTW_NRXDESC, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1521 #endif 1522 } 1523 1524 static void 1525 rtw_kick(struct rtw_softc *sc) 1526 { 1527 int pri; 1528 struct rtw_regs *regs = &sc->sc_regs; 1529 1530 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1531 RTW_WRITE16(regs, RTW_IMR, 0); 1532 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1533 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1534 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1535 &sc->sc_txctl_blk[pri]); 1536 } 1537 rtw_swring_setup(sc); 1538 rtw_hwring_setup(sc); 1539 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1540 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1541 } 1542 1543 static void 1544 rtw_intr_ioerror(struct rtw_softc *sc, u_int16_t isr) 1545 { 1546 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) { 1547 rtw_kick(sc); 1548 } 1549 if ((isr & RTW_INTR_TXFOVW) != 0) 1550 ; /* TBD restart transmit engine */ 1551 return; 1552 } 1553 1554 static __inline void 1555 rtw_suspend_ticks(struct rtw_softc *sc) 1556 { 1557 printf("%s: suspending ticks\n", sc->sc_dev.dv_xname); 1558 sc->sc_do_tick = 0; 1559 } 1560 1561 static __inline void 1562 rtw_resume_ticks(struct rtw_softc *sc) 1563 { 1564 u_int32_t tsftrl0, tsftrl1, next_tick; 1565 1566 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1567 1568 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1569 next_tick = tsftrl1 + 1000000; 1570 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1571 1572 sc->sc_do_tick = 1; 1573 1574 printf("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1575 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick); 1576 } 1577 1578 static void 1579 rtw_intr_timeout(struct rtw_softc *sc) 1580 { 1581 printf("%s: timeout\n", sc->sc_dev.dv_xname); 1582 if (sc->sc_do_tick) 1583 rtw_resume_ticks(sc); 1584 return; 1585 } 1586 1587 int 1588 rtw_intr(void *arg) 1589 { 1590 int i; 1591 struct rtw_softc *sc = arg; 1592 struct rtw_regs *regs = &sc->sc_regs; 1593 u_int16_t isr; 1594 1595 /* 1596 * If the interface isn't running, the interrupt couldn't 1597 * possibly have come from us. 1598 */ 1599 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1600 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1601 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1602 RTW_DPRINTF2(("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1603 return (0); 1604 } 1605 1606 for (i = 0; i < 10; i++) { 1607 isr = RTW_READ16(regs, RTW_ISR); 1608 1609 RTW_WRITE16(regs, RTW_ISR, isr); 1610 1611 if (sc->sc_intr_ack != NULL) 1612 (*sc->sc_intr_ack)(regs); 1613 1614 if (isr == 0) 1615 break; 1616 1617 #ifdef RTW_DEBUG 1618 #define PRINTINTR(flag) do { \ 1619 if ((isr & flag) != 0) { \ 1620 printf("%s" #flag, delim); \ 1621 delim = ","; \ 1622 } \ 1623 } while (0) 1624 1625 if (rtw_debug > 1 && isr != 0) { 1626 const char *delim = "<"; 1627 1628 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1629 1630 PRINTINTR(RTW_INTR_TXFOVW); 1631 PRINTINTR(RTW_INTR_TIMEOUT); 1632 PRINTINTR(RTW_INTR_BCNINT); 1633 PRINTINTR(RTW_INTR_ATIMINT); 1634 PRINTINTR(RTW_INTR_TBDER); 1635 PRINTINTR(RTW_INTR_TBDOK); 1636 PRINTINTR(RTW_INTR_THPDER); 1637 PRINTINTR(RTW_INTR_THPDOK); 1638 PRINTINTR(RTW_INTR_TNPDER); 1639 PRINTINTR(RTW_INTR_TNPDOK); 1640 PRINTINTR(RTW_INTR_RXFOVW); 1641 PRINTINTR(RTW_INTR_RDU); 1642 PRINTINTR(RTW_INTR_TLPDER); 1643 PRINTINTR(RTW_INTR_TLPDOK); 1644 PRINTINTR(RTW_INTR_RER); 1645 PRINTINTR(RTW_INTR_ROK); 1646 1647 printf(">\n"); 1648 } 1649 #undef PRINTINTR 1650 #endif /* RTW_DEBUG */ 1651 1652 if ((isr & RTW_INTR_RX) != 0) 1653 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1654 if ((isr & RTW_INTR_TX) != 0) 1655 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1656 if ((isr & RTW_INTR_BEACON) != 0) 1657 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1658 if ((isr & RTW_INTR_ATIMINT) != 0) 1659 rtw_intr_atim(sc); 1660 if ((isr & RTW_INTR_IOERROR) != 0) 1661 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1662 if ((isr & RTW_INTR_TIMEOUT) != 0) 1663 rtw_intr_timeout(sc); 1664 } 1665 1666 return 1; 1667 } 1668 1669 static void 1670 rtw_stop(struct ifnet *ifp, int disable) 1671 { 1672 int pri, s; 1673 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1674 struct ieee80211com *ic = &sc->sc_ic; 1675 struct rtw_regs *regs = &sc->sc_regs; 1676 1677 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1678 return; 1679 1680 rtw_suspend_ticks(sc); 1681 1682 s = splnet(); 1683 1684 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1685 1686 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1687 /* Disable interrupts. */ 1688 RTW_WRITE16(regs, RTW_IMR, 0); 1689 1690 /* Stop the transmit and receive processes. First stop DMA, 1691 * then disable receiver and transmitter. 1692 */ 1693 RTW_WRITE8(regs, RTW_TPPOLL, 1694 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ| 1695 RTW_TPPOLL_SLPQ); 1696 1697 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1698 } 1699 1700 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1701 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1702 &sc->sc_txctl_blk[pri]); 1703 } 1704 1705 if (disable) { 1706 rtw_disable(sc); 1707 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1708 } 1709 1710 /* Mark the interface as not running. Cancel the watchdog timer. */ 1711 ifp->if_flags &= ~IFF_RUNNING; 1712 ifp->if_timer = 0; 1713 1714 splx(s); 1715 1716 return; 1717 } 1718 1719 const char * 1720 rtw_pwrstate_string(enum rtw_pwrstate power) 1721 { 1722 switch (power) { 1723 case RTW_ON: 1724 return "on"; 1725 case RTW_SLEEP: 1726 return "sleep"; 1727 case RTW_OFF: 1728 return "off"; 1729 default: 1730 return "unknown"; 1731 } 1732 } 1733 1734 /* XXX I am using the RFMD settings gleaned from the reference 1735 * driver. 1736 */ 1737 static void 1738 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1739 int before_rf) 1740 { 1741 u_int32_t anaparm; 1742 1743 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1744 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1745 1746 anaparm = RTW_READ(regs, RTW_ANAPARM); 1747 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1748 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1749 1750 switch (power) { 1751 case RTW_OFF: 1752 if (before_rf) 1753 return; 1754 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_OFF; 1755 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_OFF; 1756 anaparm |= RTW_ANAPARM_TXDACOFF; 1757 break; 1758 case RTW_SLEEP: 1759 if (!before_rf) 1760 return; 1761 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_SLEEP; 1762 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_SLEEP; 1763 anaparm |= RTW_ANAPARM_TXDACOFF; 1764 break; 1765 case RTW_ON: 1766 if (!before_rf) 1767 return; 1768 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_ON; 1769 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_ON; 1770 break; 1771 } 1772 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1773 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1774 } 1775 1776 static void 1777 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1778 int before_rf) 1779 { 1780 u_int32_t anaparm; 1781 1782 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1783 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1784 1785 anaparm = RTW_READ(regs, RTW_ANAPARM); 1786 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1787 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1788 1789 switch (power) { 1790 case RTW_OFF: 1791 if (before_rf) 1792 return; 1793 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_OFF; 1794 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_OFF; 1795 anaparm |= RTW_ANAPARM_TXDACOFF; 1796 break; 1797 case RTW_SLEEP: 1798 if (!before_rf) 1799 return; 1800 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_SLEEP; 1801 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_SLEEP; 1802 anaparm |= RTW_ANAPARM_TXDACOFF; 1803 break; 1804 case RTW_ON: 1805 if (!before_rf) 1806 return; 1807 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_ON; 1808 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_ON; 1809 break; 1810 } 1811 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1812 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1813 } 1814 1815 static void 1816 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf) 1817 { 1818 struct rtw_regs *regs = &sc->sc_regs; 1819 1820 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 1821 1822 (*sc->sc_pwrstate_cb)(regs, power, before_rf); 1823 1824 rtw_set_access(sc, RTW_ACCESS_NONE); 1825 1826 return; 1827 } 1828 1829 static int 1830 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 1831 { 1832 int rc; 1833 1834 RTW_DPRINTF2(("%s: %s->%s\n", __func__, 1835 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 1836 1837 if (sc->sc_pwrstate == power) 1838 return 0; 1839 1840 rtw_pwrstate0(sc, power, 1); 1841 rc = rtw_rf_pwrstate(sc->sc_rf, power); 1842 rtw_pwrstate0(sc, power, 0); 1843 1844 switch (power) { 1845 case RTW_ON: 1846 /* TBD set LEDs */ 1847 break; 1848 case RTW_SLEEP: 1849 /* TBD */ 1850 break; 1851 case RTW_OFF: 1852 /* TBD */ 1853 break; 1854 } 1855 if (rc == 0) 1856 sc->sc_pwrstate = power; 1857 else 1858 sc->sc_pwrstate = RTW_OFF; 1859 return rc; 1860 } 1861 1862 static int 1863 rtw_tune(struct rtw_softc *sc) 1864 { 1865 struct ieee80211com *ic = &sc->sc_ic; 1866 u_int chan; 1867 int rc; 1868 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 1869 dflantb = sc->sc_flags & RTW_F_DFLANTB; 1870 1871 KASSERT(ic->ic_bss->ni_chan != NULL); 1872 1873 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1874 if (chan == IEEE80211_CHAN_ANY) 1875 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1876 1877 if (chan == sc->sc_cur_chan) { 1878 RTW_DPRINTF(("%s: already tuned chan #%d\n", __func__, chan)); 1879 return 0; 1880 } 1881 1882 rtw_suspend_ticks(sc); 1883 1884 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 1885 1886 /* TBD wait for Tx to complete */ 1887 1888 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 1889 1890 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 1891 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 1892 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 1893 dflantb, RTW_ON)) != 0) { 1894 /* XXX condition on powersaving */ 1895 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 1896 } 1897 1898 sc->sc_cur_chan = chan; 1899 1900 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 1901 1902 rtw_resume_ticks(sc); 1903 1904 return rc; 1905 } 1906 1907 void 1908 rtw_disable(struct rtw_softc *sc) 1909 { 1910 int rc; 1911 1912 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1913 return; 1914 1915 /* turn off PHY */ 1916 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 1917 printf("%s: failed to turn off PHY (%d)\n", 1918 sc->sc_dev.dv_xname, rc); 1919 1920 if (sc->sc_disable != NULL) 1921 (*sc->sc_disable)(sc); 1922 1923 sc->sc_flags &= ~RTW_F_ENABLED; 1924 } 1925 1926 int 1927 rtw_enable(struct rtw_softc *sc) 1928 { 1929 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 1930 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 1931 printf("%s: device enable failed\n", 1932 sc->sc_dev.dv_xname); 1933 return (EIO); 1934 } 1935 sc->sc_flags |= RTW_F_ENABLED; 1936 } 1937 return (0); 1938 } 1939 1940 static void 1941 rtw_transmit_config(struct rtw_regs *regs) 1942 { 1943 u_int32_t tcr; 1944 1945 tcr = RTW_READ(regs, RTW_TCR); 1946 1947 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 1948 tcr &= ~RTW_TCR_LBK_MASK; 1949 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 1950 1951 /* set short/long retry limits */ 1952 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 1953 tcr |= LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 1954 1955 tcr |= RTW_TCR_CRC; /* NIC appends CRC32 */ 1956 1957 RTW_WRITE(regs, RTW_TCR, tcr); 1958 } 1959 1960 static __inline void 1961 rtw_enable_interrupts(struct rtw_softc *sc) 1962 { 1963 struct rtw_regs *regs = &sc->sc_regs; 1964 1965 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 1966 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 1967 1968 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1969 RTW_WRITE16(regs, RTW_ISR, 0xffff); 1970 1971 /* XXX necessary? */ 1972 if (sc->sc_intr_ack != NULL) 1973 (*sc->sc_intr_ack)(regs); 1974 } 1975 1976 /* XXX is the endianness correct? test. */ 1977 #define rtw_calchash(addr) \ 1978 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1979 1980 static void 1981 rtw_pktfilt_load(struct rtw_softc *sc) 1982 { 1983 struct rtw_regs *regs = &sc->sc_regs; 1984 struct ieee80211com *ic = &sc->sc_ic; 1985 struct ethercom *ec = &ic->ic_ec; 1986 struct ifnet *ifp = &sc->sc_ic.ic_if; 1987 int hash; 1988 u_int32_t hashes[2] = { 0, 0 }; 1989 struct ether_multi *enm; 1990 struct ether_multistep step; 1991 1992 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 1993 1994 #define RTW_RCR_MONITOR (RTW_RCR_ACRC32|RTW_RCR_APM|RTW_RCR_AAP|RTW_RCR_AB) 1995 1996 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1997 sc->sc_rcr |= RTW_RCR_MONITOR; 1998 else 1999 sc->sc_rcr &= ~RTW_RCR_MONITOR; 2000 2001 /* XXX reference sources BEGIN */ 2002 sc->sc_rcr |= RTW_RCR_ENMARP | RTW_RCR_AICV | RTW_RCR_ACRC32; 2003 sc->sc_rcr |= RTW_RCR_AB | RTW_RCR_AM | RTW_RCR_APM; 2004 #if 0 2005 /* receive broadcasts in our BSS */ 2006 sc->sc_rcr |= RTW_RCR_ADD3; 2007 #endif 2008 /* XXX reference sources END */ 2009 2010 /* receive pwrmgmt frames. */ 2011 sc->sc_rcr |= RTW_RCR_APWRMGT; 2012 /* receive mgmt/ctrl/data frames. */ 2013 sc->sc_rcr |= RTW_RCR_AMF | RTW_RCR_ACF | RTW_RCR_ADF; 2014 /* initialize Rx DMA threshold, Tx DMA burst size */ 2015 sc->sc_rcr |= RTW_RCR_RXFTH_WHOLE | RTW_RCR_MXDMA_1024; 2016 2017 ifp->if_flags &= ~IFF_ALLMULTI; 2018 2019 if (ifp->if_flags & IFF_PROMISC) { 2020 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2021 allmulti: 2022 ifp->if_flags |= IFF_ALLMULTI; 2023 goto setit; 2024 } 2025 2026 /* 2027 * Program the 64-bit multicast hash filter. 2028 */ 2029 ETHER_FIRST_MULTI(step, ec, enm); 2030 while (enm != NULL) { 2031 /* XXX */ 2032 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2033 ETHER_ADDR_LEN) != 0) 2034 goto allmulti; 2035 2036 hash = rtw_calchash(enm->enm_addrlo); 2037 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2038 ETHER_NEXT_MULTI(step, enm); 2039 } 2040 2041 if (ifp->if_flags & IFF_BROADCAST) { 2042 hash = rtw_calchash(etherbroadcastaddr); 2043 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2044 } 2045 2046 /* all bits set => hash is useless */ 2047 if (~(hashes[0] & hashes[1]) == 0) 2048 goto allmulti; 2049 2050 setit: 2051 if (ifp->if_flags & IFF_ALLMULTI) 2052 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2053 2054 if (ic->ic_state == IEEE80211_S_SCAN) 2055 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2056 2057 hashes[0] = hashes[1] = 0xffffffff; 2058 2059 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2060 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2061 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2062 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2063 2064 DPRINTF(sc, ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2065 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2066 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2067 2068 return; 2069 } 2070 2071 static int 2072 rtw_init(struct ifnet *ifp) 2073 { 2074 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2075 struct ieee80211com *ic = &sc->sc_ic; 2076 struct rtw_regs *regs = &sc->sc_regs; 2077 int rc = 0; 2078 2079 if ((rc = rtw_enable(sc)) != 0) 2080 goto out; 2081 2082 /* Cancel pending I/O and reset. */ 2083 rtw_stop(ifp, 0); 2084 2085 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2086 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 2087 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2088 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2089 2090 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2091 goto out; 2092 2093 rtw_swring_setup(sc); 2094 2095 rtw_transmit_config(regs); 2096 2097 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2098 2099 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2100 2101 /* long PLCP header, 1Mbps basic rate */ 2102 RTW_WRITE16(regs, RTW_BRSR, 0x0); 2103 2104 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 2105 rtw_set_access(sc, RTW_ACCESS_NONE); 2106 2107 #if 0 2108 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_GWAKE|RTW_FEMR_WKUP|RTW_FEMR_INTR); 2109 #endif 2110 /* XXX from reference sources */ 2111 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2112 2113 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2114 2115 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2116 /* from Linux driver */ 2117 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2118 2119 rtw_enable_interrupts(sc); 2120 2121 rtw_pktfilt_load(sc); 2122 2123 rtw_hwring_setup(sc); 2124 2125 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2126 2127 ifp->if_flags |= IFF_RUNNING; 2128 ic->ic_state = IEEE80211_S_INIT; 2129 2130 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2131 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2132 2133 rtw_resume_ticks(sc); 2134 2135 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2136 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2137 2138 switch (ic->ic_opmode) { 2139 case IEEE80211_M_AHDEMO: 2140 case IEEE80211_M_IBSS: 2141 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_ADHOC_OK); 2142 break; 2143 case IEEE80211_M_HOSTAP: 2144 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_AP_OK); 2145 break; 2146 case IEEE80211_M_MONITOR: 2147 /* XXX */ 2148 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_NOLINK); 2149 break; 2150 case IEEE80211_M_STA: 2151 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_INFRA_OK); 2152 break; 2153 } 2154 2155 rtw_set_access(sc, RTW_ACCESS_NONE); 2156 2157 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2158 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2159 else 2160 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2161 2162 out: 2163 return rc; 2164 } 2165 2166 static int 2167 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2168 { 2169 int rc = 0; 2170 struct rtw_softc *sc = ifp->if_softc; 2171 struct ifreq *ifr = (struct ifreq *)data; 2172 2173 switch (cmd) { 2174 case SIOCSIFFLAGS: 2175 if ((ifp->if_flags & IFF_UP) != 0) { 2176 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2177 rtw_pktfilt_load(sc); 2178 } else 2179 rc = rtw_init(ifp); 2180 #ifdef RTW_DEBUG 2181 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2182 #endif /* RTW_DEBUG */ 2183 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2184 #ifdef RTW_DEBUG 2185 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2186 #endif /* RTW_DEBUG */ 2187 rtw_stop(ifp, 1); 2188 } 2189 break; 2190 case SIOCADDMULTI: 2191 case SIOCDELMULTI: 2192 if (cmd == SIOCADDMULTI) 2193 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2194 else 2195 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2196 if (rc == ENETRESET) { 2197 if (ifp->if_flags & IFF_RUNNING) 2198 rtw_pktfilt_load(sc); 2199 rc = 0; 2200 } 2201 break; 2202 default: 2203 if ((rc = ieee80211_ioctl(ifp, cmd, data)) == ENETRESET) { 2204 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2205 rc = rtw_init(ifp); 2206 else 2207 rc = 0; 2208 } 2209 break; 2210 } 2211 return rc; 2212 } 2213 2214 /* Point *mp at the next 802.11 frame to transmit. Point *stcp 2215 * at the driver's selection of transmit control block for the packet. 2216 */ 2217 static __inline int 2218 rtw_dequeue(struct ifnet *ifp, struct rtw_txctl_blk **stcp, 2219 struct rtw_txdesc_blk **htcp, struct mbuf **mp, 2220 struct ieee80211_node **nip) 2221 { 2222 struct rtw_txctl_blk *stc; 2223 struct rtw_txdesc_blk *htc; 2224 struct mbuf *m0; 2225 struct rtw_softc *sc; 2226 struct ieee80211com *ic; 2227 2228 sc = (struct rtw_softc *)ifp->if_softc; 2229 2230 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2231 *mp = NULL; 2232 2233 stc = &sc->sc_txctl_blk[RTW_TXPRIMD]; 2234 htc = &sc->sc_txdesc_blk[RTW_TXPRIMD]; 2235 2236 if (SIMPLEQ_EMPTY(&stc->stc_freeq) || htc->htc_nfree == 0) { 2237 DPRINTF2(sc, ("%s: out of descriptors\n", __func__)); 2238 ifp->if_flags |= IFF_OACTIVE; 2239 return 0; 2240 } 2241 2242 ic = &sc->sc_ic; 2243 2244 if (!IF_IS_EMPTY(&ic->ic_mgtq)) { 2245 IF_DEQUEUE(&ic->ic_mgtq, m0); 2246 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2247 m0->m_pkthdr.rcvif = NULL; 2248 DPRINTF2(sc, ("%s: dequeue mgt frame\n", __func__)); 2249 } else if (ic->ic_state != IEEE80211_S_RUN) { 2250 DPRINTF2(sc, ("%s: not running\n", __func__)); 2251 return 0; 2252 } else if (!IF_IS_EMPTY(&ic->ic_pwrsaveq)) { 2253 IF_DEQUEUE(&ic->ic_pwrsaveq, m0); 2254 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2255 m0->m_pkthdr.rcvif = NULL; 2256 DPRINTF2(sc, ("%s: dequeue pwrsave frame\n", __func__)); 2257 } else { 2258 IFQ_POLL(&ifp->if_snd, m0); 2259 if (m0 == NULL) { 2260 DPRINTF2(sc, ("%s: no frame\n", __func__)); 2261 return 0; 2262 } 2263 DPRINTF2(sc, ("%s: dequeue data frame\n", __func__)); 2264 IFQ_DEQUEUE(&ifp->if_snd, m0); 2265 ifp->if_opackets++; 2266 #if NBPFILTER > 0 2267 if (ifp->if_bpf) 2268 bpf_mtap(ifp->if_bpf, m0); 2269 #endif 2270 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2271 DPRINTF2(sc, ("%s: encap error\n", __func__)); 2272 ifp->if_oerrors++; 2273 return -1; 2274 } 2275 } 2276 DPRINTF2(sc, ("%s: leave\n", __func__)); 2277 *stcp = stc; 2278 *htcp = htc; 2279 *mp = m0; 2280 return 0; 2281 } 2282 2283 /* TBD factor with atw_start */ 2284 static struct mbuf * 2285 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2286 u_int ndescfree, short *ifflagsp, const char *dvname) 2287 { 2288 int first, rc; 2289 struct mbuf *m, *m0; 2290 2291 m0 = chain; 2292 2293 /* 2294 * Load the DMA map. Copy and try (once) again if the packet 2295 * didn't fit in the alloted number of segments. 2296 */ 2297 for (first = 1; 2298 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2299 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2300 dmam->dm_nsegs > ndescfree) && first; 2301 first = 0) { 2302 if (rc == 0) 2303 bus_dmamap_unload(dmat, dmam); 2304 MGETHDR(m, M_DONTWAIT, MT_DATA); 2305 if (m == NULL) { 2306 printf("%s: unable to allocate Tx mbuf\n", 2307 dvname); 2308 break; 2309 } 2310 if (m0->m_pkthdr.len > MHLEN) { 2311 MCLGET(m, M_DONTWAIT); 2312 if ((m->m_flags & M_EXT) == 0) { 2313 printf("%s: cannot allocate Tx cluster\n", 2314 dvname); 2315 m_freem(m); 2316 break; 2317 } 2318 } 2319 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2320 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 2321 m_freem(m0); 2322 m0 = m; 2323 m = NULL; 2324 } 2325 if (rc != 0) { 2326 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 2327 m_freem(m0); 2328 return NULL; 2329 } else if (dmam->dm_nsegs > ndescfree) { 2330 *ifflagsp |= IFF_OACTIVE; 2331 bus_dmamap_unload(dmat, dmam); 2332 m_freem(m0); 2333 return NULL; 2334 } 2335 return m0; 2336 } 2337 2338 static void 2339 rtw_start(struct ifnet *ifp) 2340 { 2341 int desc, i, lastdesc, npkt, rate; 2342 uint32_t proto_txctl0, txctl0, txctl1; 2343 bus_dmamap_t dmamap; 2344 struct ieee80211com *ic; 2345 struct ieee80211_duration *d0; 2346 struct ieee80211_frame *wh; 2347 struct ieee80211_node *ni; 2348 struct mbuf *m0; 2349 struct rtw_softc *sc; 2350 struct rtw_txctl_blk *stc; 2351 struct rtw_txdesc_blk *htc; 2352 struct rtw_txctl *stx; 2353 struct rtw_txdesc *htx; 2354 2355 sc = (struct rtw_softc *)ifp->if_softc; 2356 ic = &sc->sc_ic; 2357 2358 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2359 2360 /* XXX do real rate control */ 2361 proto_txctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 2362 2363 switch (rate = MAX(2, ieee80211_get_rate(ic))) { 2364 case 2: 2365 proto_txctl0 |= RTW_TXCTL0_RATE_1MBPS; 2366 break; 2367 case 4: 2368 proto_txctl0 |= RTW_TXCTL0_RATE_2MBPS; 2369 break; 2370 case 11: 2371 proto_txctl0 |= RTW_TXCTL0_RATE_5MBPS; 2372 break; 2373 case 22: 2374 proto_txctl0 |= RTW_TXCTL0_RATE_11MBPS; 2375 break; 2376 } 2377 2378 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 2379 proto_txctl0 |= RTW_TXCTL0_SPLCP; 2380 2381 for (;;) { 2382 if (rtw_dequeue(ifp, &stc, &htc, &m0, &ni) == -1) 2383 continue; 2384 if (m0 == NULL) 2385 break; 2386 stx = SIMPLEQ_FIRST(&stc->stc_freeq); 2387 2388 dmamap = stx->stx_dmamap; 2389 2390 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 2391 htc->htc_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 2392 2393 if (m0 == NULL || dmamap->dm_nsegs == 0) { 2394 DPRINTF2(sc, ("%s: fail dmamap load\n", __func__)); 2395 goto post_dequeue_err; 2396 } 2397 2398 txctl0 = proto_txctl0 | 2399 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 2400 2401 wh = mtod(m0, struct ieee80211_frame *); 2402 2403 if (ieee80211_compute_duration(wh, 2404 m0->m_pkthdr.len - sizeof(wh), 2405 ic->ic_flags, ic->ic_fragthreshold, 2406 rate, &stx->stx_d0, &stx->stx_dn, &npkt) == -1) { 2407 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 2408 goto post_load_err; 2409 } 2410 2411 /* XXX >= ? */ 2412 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 2413 txctl0 |= RTW_TXCTL0_RTSEN; 2414 2415 d0 = &stx->stx_d0; 2416 2417 txctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 2418 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 2419 2420 if ((d0->d_plcp_svc & IEEE80211_PLCP_SERVICE_LENEXT) != 0) 2421 txctl1 |= RTW_TXCTL1_LENGEXT; 2422 2423 /* TBD fragmentation */ 2424 2425 stx->stx_first = htc->htc_next; 2426 2427 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2428 htc, stx->stx_first, dmamap->dm_nsegs, 2429 BUS_DMASYNC_PREWRITE); 2430 2431 for (i = 0, lastdesc = desc = stx->stx_first; 2432 i < dmamap->dm_nsegs; 2433 i++, desc = RTW_NEXT_IDX(htc, desc)) { 2434 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 2435 DPRINTF2(sc, ("%s: seg too long\n", __func__)); 2436 goto post_load_err; 2437 } 2438 htx = &htc->htc_desc[desc]; 2439 htx->htx_ctl0 = htole32(txctl0); 2440 if (i != 0) 2441 htx->htx_ctl0 |= htole32(RTW_TXCTL0_OWN); 2442 htx->htx_ctl1 = htole32(txctl1); 2443 htx->htx_buf = htole32(dmamap->dm_segs[i].ds_addr); 2444 htx->htx_len = htole32(dmamap->dm_segs[i].ds_len); 2445 lastdesc = desc; 2446 DPRINTF2(sc, ("%s: stx %p txdesc[%d] ctl0 %#08x " 2447 "ctl1 %#08x buf %#08x len %#08x\n", 2448 sc->sc_dev.dv_xname, stx, desc, htx->htx_ctl0, 2449 htx->htx_ctl1, htx->htx_buf, htx->htx_len)); 2450 } 2451 2452 htc->htc_desc[lastdesc].htx_ctl0 |= htole32(RTW_TXCTL0_LS); 2453 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2454 htole32(RTW_TXCTL0_FS); 2455 2456 DPRINTF2(sc, ("%s: stx %p FS on txdesc[%d], LS on txdesc[%d]\n", 2457 sc->sc_dev.dv_xname, stx, lastdesc, stx->stx_first)); 2458 2459 stx->stx_ni = ni; 2460 stx->stx_mbuf = m0; 2461 stx->stx_last = lastdesc; 2462 2463 htc->htc_nfree -= dmamap->dm_nsegs; 2464 htc->htc_next = desc; 2465 2466 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2467 htc, stx->stx_first, dmamap->dm_nsegs, 2468 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2469 2470 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2471 htole32(RTW_TXCTL0_OWN); 2472 2473 DPRINTF2(sc, ("%s: stx %p OWN on txdesc[%d]\n", 2474 sc->sc_dev.dv_xname, stx, stx->stx_first)); 2475 2476 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2477 htc, stx->stx_first, 1, 2478 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2479 2480 SIMPLEQ_REMOVE_HEAD(&stc->stc_freeq, stx_q); 2481 SIMPLEQ_INSERT_TAIL(&stc->stc_dirtyq, stx, stx_q); 2482 2483 stc->stc_tx_timer = 5; 2484 ifp->if_timer = 1; 2485 2486 /* TBD poke just one txmtr? */ 2487 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, 2488 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ | RTW_TPPOLL_HPQ | 2489 RTW_TPPOLL_BQ); 2490 } 2491 DPRINTF2(sc, ("%s: leave\n", __func__)); 2492 return; 2493 post_load_err: 2494 bus_dmamap_unload(sc->sc_dmat, dmamap); 2495 m_freem(m0); 2496 post_dequeue_err: 2497 ieee80211_release_node(&sc->sc_ic, ni); 2498 return; 2499 } 2500 2501 static void 2502 rtw_watchdog(struct ifnet *ifp) 2503 { 2504 int pri; 2505 struct rtw_softc *sc; 2506 struct rtw_txctl_blk *stc; 2507 2508 sc = ifp->if_softc; 2509 2510 ifp->if_timer = 0; 2511 2512 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2513 return; 2514 2515 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2516 stc = &sc->sc_txctl_blk[pri]; 2517 2518 if (stc->stc_tx_timer == 0) 2519 continue; 2520 2521 if (--stc->stc_tx_timer == 0) { 2522 if (SIMPLEQ_EMPTY(&stc->stc_dirtyq)) 2523 continue; 2524 printf("%s: transmit timeout, priority %d\n", 2525 ifp->if_xname, pri); 2526 ifp->if_oerrors++; 2527 /* XXX be gentle */ 2528 (void)rtw_init(ifp); 2529 rtw_start(ifp); 2530 } else 2531 ifp->if_timer = 1; 2532 } 2533 /* TBD */ 2534 return; 2535 } 2536 2537 static void 2538 rtw_start_beacon(struct rtw_softc *sc, int enable) 2539 { 2540 /* TBD */ 2541 return; 2542 } 2543 2544 static void 2545 rtw_next_scan(void *arg) 2546 { 2547 struct ieee80211com *ic = arg; 2548 int s; 2549 2550 /* don't call rtw_start w/o network interrupts blocked */ 2551 s = splnet(); 2552 if (ic->ic_state == IEEE80211_S_SCAN) 2553 ieee80211_next_scan(ic); 2554 splx(s); 2555 } 2556 2557 /* Synchronize the hardware state with the software state. */ 2558 static int 2559 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2560 { 2561 struct ifnet *ifp = &ic->ic_if; 2562 struct rtw_softc *sc = ifp->if_softc; 2563 enum ieee80211_state ostate; 2564 int error; 2565 2566 ostate = ic->ic_state; 2567 2568 if (nstate == IEEE80211_S_INIT) { 2569 callout_stop(&sc->sc_scan_ch); 2570 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2571 rtw_start_beacon(sc, 0); 2572 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2573 } 2574 2575 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 2576 rtw_pwrstate(sc, RTW_ON); 2577 2578 if ((error = rtw_tune(sc)) != 0) 2579 return error; 2580 2581 switch (nstate) { 2582 case IEEE80211_S_ASSOC: 2583 break; 2584 case IEEE80211_S_INIT: 2585 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2586 break; 2587 case IEEE80211_S_SCAN: 2588 #if 0 2589 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2590 rtw_write_bssid(sc); 2591 #endif 2592 2593 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 2594 rtw_next_scan, ic); 2595 2596 break; 2597 case IEEE80211_S_RUN: 2598 if (ic->ic_opmode == IEEE80211_M_STA) 2599 break; 2600 /*FALLTHROUGH*/ 2601 case IEEE80211_S_AUTH: 2602 #if 0 2603 rtw_write_bssid(sc); 2604 rtw_write_bcn_thresh(sc); 2605 rtw_write_ssid(sc); 2606 rtw_write_sup_rates(sc); 2607 #endif 2608 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2609 ic->ic_opmode == IEEE80211_M_MONITOR) 2610 break; 2611 2612 /* TBD set listen interval, beacon interval */ 2613 2614 #if 0 2615 rtw_tsf(sc); 2616 #endif 2617 break; 2618 } 2619 2620 if (nstate != IEEE80211_S_SCAN) 2621 callout_stop(&sc->sc_scan_ch); 2622 2623 if (nstate == IEEE80211_S_RUN && 2624 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2625 ic->ic_opmode == IEEE80211_M_IBSS)) 2626 rtw_start_beacon(sc, 1); 2627 else 2628 rtw_start_beacon(sc, 0); 2629 2630 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2631 } 2632 2633 static void 2634 rtw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2635 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2636 { 2637 /* TBD */ 2638 return; 2639 } 2640 2641 static void 2642 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2643 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2644 { 2645 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 2646 2647 switch (subtype) { 2648 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2649 /* do nothing: hardware answers probe request XXX */ 2650 break; 2651 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2652 case IEEE80211_FC0_SUBTYPE_BEACON: 2653 rtw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2654 break; 2655 default: 2656 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2657 break; 2658 } 2659 return; 2660 } 2661 2662 static struct ieee80211_node * 2663 rtw_node_alloc(struct ieee80211com *ic) 2664 { 2665 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2666 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 2667 2668 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 2669 return ni; 2670 } 2671 2672 static void 2673 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 2674 { 2675 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2676 2677 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 2678 ether_sprintf(ni->ni_bssid))); 2679 (*sc->sc_mtbl.mt_node_free)(ic, ni); 2680 } 2681 2682 static int 2683 rtw_media_change(struct ifnet *ifp) 2684 { 2685 int error; 2686 2687 error = ieee80211_media_change(ifp); 2688 if (error == ENETRESET) { 2689 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 2690 (IFF_RUNNING|IFF_UP)) 2691 rtw_init(ifp); /* XXX lose error */ 2692 error = 0; 2693 } 2694 return error; 2695 } 2696 2697 static void 2698 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 2699 { 2700 struct rtw_softc *sc = ifp->if_softc; 2701 2702 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2703 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 2704 imr->ifm_status = 0; 2705 return; 2706 } 2707 ieee80211_media_status(ifp, imr); 2708 } 2709 2710 void 2711 rtw_power(int why, void *arg) 2712 { 2713 struct rtw_softc *sc = arg; 2714 struct ifnet *ifp = &sc->sc_ic.ic_if; 2715 int s; 2716 2717 DPRINTF(sc, ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 2718 2719 s = splnet(); 2720 switch (why) { 2721 case PWR_STANDBY: 2722 /* XXX do nothing. */ 2723 break; 2724 case PWR_SUSPEND: 2725 rtw_stop(ifp, 0); 2726 if (sc->sc_power != NULL) 2727 (*sc->sc_power)(sc, why); 2728 break; 2729 case PWR_RESUME: 2730 if (ifp->if_flags & IFF_UP) { 2731 if (sc->sc_power != NULL) 2732 (*sc->sc_power)(sc, why); 2733 rtw_init(ifp); 2734 } 2735 break; 2736 case PWR_SOFTSUSPEND: 2737 case PWR_SOFTSTANDBY: 2738 case PWR_SOFTRESUME: 2739 break; 2740 } 2741 splx(s); 2742 } 2743 2744 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 2745 void 2746 rtw_shutdown(void *arg) 2747 { 2748 struct rtw_softc *sc = arg; 2749 2750 rtw_stop(&sc->sc_ic.ic_if, 1); 2751 } 2752 2753 static __inline void 2754 rtw_setifprops(struct ifnet *ifp, char (*dvname)[IFNAMSIZ], void *softc) 2755 { 2756 (void)memcpy(ifp->if_xname, *dvname, IFNAMSIZ); 2757 ifp->if_softc = softc; 2758 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 2759 IFF_NOTRAILERS; 2760 ifp->if_ioctl = rtw_ioctl; 2761 ifp->if_start = rtw_start; 2762 ifp->if_watchdog = rtw_watchdog; 2763 ifp->if_init = rtw_init; 2764 ifp->if_stop = rtw_stop; 2765 } 2766 2767 static __inline void 2768 rtw_set80211props(struct ieee80211com *ic) 2769 { 2770 int nrate; 2771 ic->ic_phytype = IEEE80211_T_DS; 2772 ic->ic_opmode = IEEE80211_M_STA; 2773 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 2774 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 2775 2776 nrate = 0; 2777 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 2778 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 2779 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 2780 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 2781 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 2782 } 2783 2784 static __inline void 2785 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 2786 { 2787 mtbl->mt_newstate = ic->ic_newstate; 2788 ic->ic_newstate = rtw_newstate; 2789 2790 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 2791 ic->ic_recv_mgmt = rtw_recv_mgmt; 2792 2793 mtbl->mt_node_free = ic->ic_node_free; 2794 ic->ic_node_free = rtw_node_free; 2795 2796 mtbl->mt_node_alloc = ic->ic_node_alloc; 2797 ic->ic_node_alloc = rtw_node_alloc; 2798 } 2799 2800 static __inline void 2801 rtw_establish_hooks(struct rtw_hooks *hooks, char (*dvname)[IFNAMSIZ], 2802 void *arg) 2803 { 2804 /* 2805 * Make sure the interface is shutdown during reboot. 2806 */ 2807 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 2808 if (hooks->rh_shutdown == NULL) 2809 printf("%s: WARNING: unable to establish shutdown hook\n", 2810 *dvname); 2811 2812 /* 2813 * Add a suspend hook to make sure we come back up after a 2814 * resume. 2815 */ 2816 hooks->rh_power = powerhook_establish(rtw_power, arg); 2817 if (hooks->rh_power == NULL) 2818 printf("%s: WARNING: unable to establish power hook\n", 2819 *dvname); 2820 } 2821 2822 static __inline void 2823 rtw_disestablish_hooks(struct rtw_hooks *hooks, char (*dvname)[IFNAMSIZ], 2824 void *arg) 2825 { 2826 if (hooks->rh_shutdown != NULL) 2827 shutdownhook_disestablish(hooks->rh_shutdown); 2828 2829 if (hooks->rh_power != NULL) 2830 powerhook_disestablish(hooks->rh_power); 2831 } 2832 2833 static __inline void 2834 rtw_init_radiotap(struct rtw_softc *sc) 2835 { 2836 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 2837 sc->sc_rxtap.rr_ihdr.it_len = sizeof(sc->sc_rxtapu); 2838 sc->sc_rxtap.rr_ihdr.it_present = RTW_RX_RADIOTAP_PRESENT; 2839 2840 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 2841 sc->sc_txtap.rt_ihdr.it_len = sizeof(sc->sc_txtapu); 2842 sc->sc_txtap.rt_ihdr.it_present = RTW_TX_RADIOTAP_PRESENT; 2843 } 2844 2845 static int 2846 rtw_txctl_blk_setup(struct rtw_txctl_blk *stc, u_int qlen) 2847 { 2848 SIMPLEQ_INIT(&stc->stc_dirtyq); 2849 SIMPLEQ_INIT(&stc->stc_freeq); 2850 stc->stc_ndesc = qlen; 2851 stc->stc_desc = malloc(qlen * sizeof(*stc->stc_desc), M_DEVBUF, 2852 M_NOWAIT); 2853 if (stc->stc_desc == NULL) 2854 return ENOMEM; 2855 return 0; 2856 } 2857 2858 static void 2859 rtw_txctl_blk_cleanup_all(struct rtw_softc *sc) 2860 { 2861 struct rtw_txctl_blk *stc; 2862 int qlen[RTW_NTXPRI] = 2863 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2864 int pri; 2865 2866 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2867 stc = &sc->sc_txctl_blk[pri]; 2868 free(stc->stc_desc, M_DEVBUF); 2869 stc->stc_desc = NULL; 2870 } 2871 } 2872 2873 static int 2874 rtw_txctl_blk_setup_all(struct rtw_softc *sc) 2875 { 2876 int pri, rc = 0; 2877 int qlen[RTW_NTXPRI] = 2878 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2879 2880 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2881 rc = rtw_txctl_blk_setup(&sc->sc_txctl_blk[pri], qlen[pri]); 2882 if (rc != 0) 2883 break; 2884 } 2885 return rc; 2886 } 2887 2888 static void 2889 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *htc, struct rtw_txdesc *desc, 2890 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 2891 { 2892 int i; 2893 2894 htc->htc_ndesc = ndesc; 2895 htc->htc_desc = desc; 2896 htc->htc_physbase = physbase; 2897 htc->htc_ofs = ofs; 2898 2899 (void)memset(htc->htc_desc, 0, 2900 sizeof(htc->htc_desc[0]) * htc->htc_ndesc); 2901 2902 for (i = 0; i < htc->htc_ndesc; i++) { 2903 htc->htc_desc[i].htx_next = htole32(RTW_NEXT_DESC(htc, i)); 2904 } 2905 } 2906 2907 static void 2908 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 2909 { 2910 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 2911 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 2912 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 2913 2914 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 2915 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 2916 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 2917 2918 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 2919 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 2920 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 2921 2922 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 2923 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 2924 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 2925 } 2926 2927 static struct rtw_rf * 2928 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, 2929 rtw_rf_write_t rf_write, int digphy) 2930 { 2931 struct rtw_rf *rf; 2932 2933 switch (rfchipid) { 2934 case RTW_RFCHIPID_MAXIM: 2935 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 2936 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 2937 break; 2938 case RTW_RFCHIPID_PHILIPS: 2939 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 2940 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 2941 break; 2942 default: 2943 return NULL; 2944 } 2945 rf->rf_continuous_tx_cb = 2946 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 2947 rf->rf_continuous_tx_arg = (void *)sc; 2948 return rf; 2949 } 2950 2951 /* Revision C and later use a different PHY delay setting than 2952 * revisions A and B. 2953 */ 2954 static u_int8_t 2955 rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0) 2956 { 2957 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 2958 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 2959 2960 u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 2961 2962 RTW_WRITE(regs, RTW_RCR, REVAB); 2963 RTW_WRITE(regs, RTW_RCR, REVC); 2964 2965 RTW_WBR(regs, RTW_RCR, RTW_RCR); 2966 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 2967 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 2968 2969 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 2970 2971 return phydelay; 2972 #undef REVC 2973 } 2974 2975 void 2976 rtw_attach(struct rtw_softc *sc) 2977 { 2978 rtw_rf_write_t rf_write; 2979 struct rtw_txctl_blk *stc; 2980 int pri, rc, vers; 2981 2982 #if 0 2983 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_txdesc) == 0, 2984 "RTW_DESC_ALIGNMENT is not a multiple of " 2985 "sizeof(struct rtw_txdesc)"); 2986 2987 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_rxdesc) == 0, 2988 "RTW_DESC_ALIGNMENT is not a multiple of " 2989 "sizeof(struct rtw_rxdesc)"); 2990 2991 CASSERT(RTW_DESC_ALIGNMENT % RTW_MAXPKTSEGS == 0, 2992 "RTW_DESC_ALIGNMENT is not a multiple of RTW_MAXPKTSEGS"); 2993 #endif 2994 2995 NEXT_ATTACH_STATE(sc, DETACHED); 2996 2997 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 2998 case RTW_TCR_HWVERID_F: 2999 vers = 'F'; 3000 rf_write = rtw_rf_hostwrite; 3001 break; 3002 case RTW_TCR_HWVERID_D: 3003 vers = 'D'; 3004 if (rtw_host_rfio) 3005 rf_write = rtw_rf_hostwrite; 3006 else 3007 rf_write = rtw_rf_macwrite; 3008 break; 3009 default: 3010 vers = '?'; 3011 rf_write = rtw_rf_macwrite; 3012 break; 3013 } 3014 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, vers); 3015 3016 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3017 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3018 0); 3019 3020 if (rc != 0) { 3021 printf("%s: could not allocate hw descriptors, error %d\n", 3022 sc->sc_dev.dv_xname, rc); 3023 goto err; 3024 } 3025 3026 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3027 3028 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3029 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3030 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3031 3032 if (rc != 0) { 3033 printf("%s: could not map hw descriptors, error %d\n", 3034 sc->sc_dev.dv_xname, rc); 3035 goto err; 3036 } 3037 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3038 3039 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3040 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3041 3042 if (rc != 0) { 3043 printf("%s: could not create DMA map for hw descriptors, " 3044 "error %d\n", sc->sc_dev.dv_xname, rc); 3045 goto err; 3046 } 3047 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3048 3049 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3050 sizeof(struct rtw_descs), NULL, 0); 3051 3052 if (rc != 0) { 3053 printf("%s: could not load DMA map for hw descriptors, " 3054 "error %d\n", sc->sc_dev.dv_xname, rc); 3055 goto err; 3056 } 3057 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3058 3059 if (rtw_txctl_blk_setup_all(sc) != 0) 3060 goto err; 3061 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3062 3063 rtw_txdesc_blk_setup_all(sc); 3064 3065 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3066 3067 sc->sc_rxdesc = &sc->sc_descs->hd_rx[0]; 3068 3069 rtw_rxctls_setup(&sc->sc_rxctl[0]); 3070 3071 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3072 stc = &sc->sc_txctl_blk[pri]; 3073 3074 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3075 &stc->stc_desc[0], stc->stc_ndesc)) != 0) { 3076 printf("%s: could not load DMA map for " 3077 "hw tx descriptors, error %d\n", 3078 sc->sc_dev.dv_xname, rc); 3079 goto err; 3080 } 3081 } 3082 3083 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3084 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxctl[0], 3085 RTW_RXQLEN)) != 0) { 3086 printf("%s: could not load DMA map for hw rx descriptors, " 3087 "error %d\n", sc->sc_dev.dv_xname, rc); 3088 goto err; 3089 } 3090 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3091 3092 /* Reset the chip to a known state. */ 3093 if (rtw_reset(sc) != 0) 3094 goto err; 3095 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3096 3097 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3098 3099 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3100 sc->sc_flags |= RTW_F_9356SROM; 3101 3102 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3103 &sc->sc_dev.dv_xname) != 0) 3104 goto err; 3105 3106 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3107 3108 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3109 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3110 &sc->sc_dev.dv_xname) != 0) { 3111 printf("%s: attach failed, malformed serial ROM\n", 3112 sc->sc_dev.dv_xname); 3113 goto err; 3114 } 3115 3116 RTW_DPRINTF(("%s: CS threshold %u\n", sc->sc_dev.dv_xname, 3117 sc->sc_csthr)); 3118 3119 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3120 3121 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, rf_write, 3122 sc->sc_flags & RTW_F_DIGPHY); 3123 3124 if (sc->sc_rf == NULL) { 3125 printf("%s: attach failed, could not attach RF\n", 3126 sc->sc_dev.dv_xname); 3127 goto err; 3128 } 3129 3130 #if 0 3131 if (rtw_identify_rf(&sc->sc_regs, &sc->sc_rftype, 3132 &sc->sc_dev.dv_xname) != 0) { 3133 printf("%s: attach failed, unknown RF unidentified\n", 3134 sc->sc_dev.dv_xname); 3135 goto err; 3136 } 3137 #endif 3138 3139 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3140 3141 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 3142 3143 RTW_DPRINTF(("%s: PHY delay %d\n", sc->sc_dev.dv_xname, 3144 sc->sc_phydelay)); 3145 3146 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 3147 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 3148 &sc->sc_dev.dv_xname); 3149 3150 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 3151 &sc->sc_dev.dv_xname); 3152 3153 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 3154 &sc->sc_dev.dv_xname) != 0) 3155 goto err; 3156 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 3157 3158 rtw_setifprops(&sc->sc_if, &sc->sc_dev.dv_xname, (void*)sc); 3159 3160 IFQ_SET_READY(&sc->sc_if.if_snd); 3161 3162 rtw_set80211props(&sc->sc_ic); 3163 3164 /* 3165 * Call MI attach routines. 3166 */ 3167 if_attach(&sc->sc_if); 3168 ieee80211_ifattach(&sc->sc_if); 3169 3170 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 3171 3172 /* possibly we should fill in our own sc_send_prresp, since 3173 * the RTL8180 is probably sending probe responses in ad hoc 3174 * mode. 3175 */ 3176 3177 /* complete initialization */ 3178 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 3179 callout_init(&sc->sc_scan_ch); 3180 3181 #if NBPFILTER > 0 3182 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 3183 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 3184 #endif 3185 3186 rtw_establish_hooks(&sc->sc_hooks, &sc->sc_dev.dv_xname, (void*)sc); 3187 3188 rtw_init_radiotap(sc); 3189 3190 NEXT_ATTACH_STATE(sc, FINISHED); 3191 3192 return; 3193 err: 3194 rtw_detach(sc); 3195 return; 3196 } 3197 3198 int 3199 rtw_detach(struct rtw_softc *sc) 3200 { 3201 int pri; 3202 3203 switch (sc->sc_attach_state) { 3204 case FINISHED: 3205 rtw_stop(&sc->sc_if, 1); 3206 3207 rtw_disestablish_hooks(&sc->sc_hooks, &sc->sc_dev.dv_xname, 3208 (void*)sc); 3209 callout_stop(&sc->sc_scan_ch); 3210 ieee80211_ifdetach(&sc->sc_if); 3211 if_detach(&sc->sc_if); 3212 break; 3213 case FINISH_ID_STA: 3214 case FINISH_RF_ATTACH: 3215 rtw_rf_destroy(sc->sc_rf); 3216 sc->sc_rf = NULL; 3217 /*FALLTHROUGH*/ 3218 case FINISH_PARSE_SROM: 3219 case FINISH_READ_SROM: 3220 rtw_srom_free(&sc->sc_srom); 3221 /*FALLTHROUGH*/ 3222 case FINISH_RESET: 3223 case FINISH_RXMAPS_CREATE: 3224 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxctl[0], 3225 RTW_RXQLEN); 3226 /*FALLTHROUGH*/ 3227 case FINISH_TXMAPS_CREATE: 3228 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3229 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 3230 sc->sc_txctl_blk[pri].stc_desc, 3231 sc->sc_txctl_blk[pri].stc_ndesc); 3232 } 3233 /*FALLTHROUGH*/ 3234 case FINISH_TXDESCBLK_SETUP: 3235 case FINISH_TXCTLBLK_SETUP: 3236 rtw_txctl_blk_cleanup_all(sc); 3237 /*FALLTHROUGH*/ 3238 case FINISH_DESCMAP_LOAD: 3239 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 3240 /*FALLTHROUGH*/ 3241 case FINISH_DESCMAP_CREATE: 3242 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 3243 /*FALLTHROUGH*/ 3244 case FINISH_DESC_MAP: 3245 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 3246 sizeof(struct rtw_descs)); 3247 /*FALLTHROUGH*/ 3248 case FINISH_DESC_ALLOC: 3249 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 3250 sc->sc_desc_nsegs); 3251 /*FALLTHROUGH*/ 3252 case DETACHED: 3253 NEXT_ATTACH_STATE(sc, DETACHED); 3254 break; 3255 } 3256 return 0; 3257 } 3258 3259 int 3260 rtw_activate(struct device *self, enum devact act) 3261 { 3262 struct rtw_softc *sc = (struct rtw_softc *)self; 3263 int rc = 0, s; 3264 3265 s = splnet(); 3266 switch (act) { 3267 case DVACT_ACTIVATE: 3268 rc = EOPNOTSUPP; 3269 break; 3270 3271 case DVACT_DEACTIVATE: 3272 if_deactivate(&sc->sc_ic.ic_if); 3273 break; 3274 } 3275 splx(s); 3276 return rc; 3277 } 3278
Indexes created Wed Sep 24 05:09:52 GMT 2025