rtw.c revision 1.68
1 /* $NetBSD: rtw.c,v 1.68 2006/03/08 00:24:06 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.68 2006/03/08 00:24:06 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/time.h> 49 #include <sys/types.h> 50 51 #include <machine/endian.h> 52 #include <machine/bus.h> 53 #include <machine/intr.h> /* splnet */ 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <dev/ic/rtwreg.h> 70 #include <dev/ic/rtwvar.h> 71 #include <dev/ic/rtwphyio.h> 72 #include <dev/ic/rtwphy.h> 73 74 #include <dev/ic/smc93cx6var.h> 75 76 #define KASSERT2(__cond, __msg) \ 77 do { \ 78 if (!(__cond)) \ 79 panic __msg ; \ 80 } while (0) 81 82 static int rtw_rfprog_fallback = 0; 83 static int rtw_host_rfio = 0; 84 85 #ifdef RTW_DEBUG 86 int rtw_debug = 0; 87 static int rtw_rxbufs_limit = RTW_RXQLEN; 88 #endif /* RTW_DEBUG */ 89 90 #define NEXT_ATTACH_STATE(sc, state) do { \ 91 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 92 ("%s: attach state %s\n", __func__, #state)); \ 93 sc->sc_attach_state = state; \ 94 } while (0) 95 96 static int rtw_xmtr_restart = 0; 97 static int rtw_do_chip_reset = 0; 98 static int rtw_ring_reset = 0; 99 100 int rtw_dwelltime = 200; /* milliseconds */ 101 static struct ieee80211_cipher rtw_cipher_wep; 102 103 static void rtw_start(struct ifnet *); 104 static void rtw_reset_oactive(struct rtw_softc *); 105 static struct mbuf *rtw_beacon_alloc(struct rtw_softc *, 106 struct ieee80211_node *); 107 static u_int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *); 108 109 static void rtw_io_enable(struct rtw_regs *, uint8_t, int); 110 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 111 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 112 const u_int8_t[IEEE80211_ADDR_LEN]); 113 static void rtw_key_update_end(struct ieee80211com *); 114 static void rtw_key_update_begin(struct ieee80211com *); 115 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 116 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 117 118 static void rtw_led_attach(struct rtw_led_state *, void *); 119 static void rtw_led_init(struct rtw_regs *); 120 static void rtw_led_slowblink(void *); 121 static void rtw_led_fastblink(void *); 122 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 123 124 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 125 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 126 #ifdef RTW_DEBUG 127 static void rtw_print_txdesc(struct rtw_softc *, const char *, 128 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 129 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 130 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 131 #endif /* RTW_DEBUG */ 132 133 /* 134 * Setup sysctl(3) MIB, hw.rtw.* 135 * 136 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 137 */ 138 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 139 { 140 int rc; 141 const struct sysctlnode *cnode, *rnode; 142 143 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 144 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 145 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 146 goto err; 147 148 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 149 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 150 "Realtek RTL818x 802.11 controls", 151 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 152 goto err; 153 154 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 155 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 156 "chip_reset", SYSCTL_DESCR("Gratuitously reset chip on rcvr error"), 157 NULL, 0, &rtw_do_chip_reset, 0, 158 CTL_CREATE, CTL_EOL)) != 0) 159 goto err; 160 161 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 162 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 163 "ring_reset", SYSCTL_DESCR("Reset ring pointers on rcvr error"), 164 NULL, 0, &rtw_ring_reset, 0, 165 CTL_CREATE, CTL_EOL)) != 0) 166 goto err; 167 168 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 169 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 170 "xmtr_restart", 171 SYSCTL_DESCR("Gratuitously reset xmtr on rcvr error"), 172 NULL, 0, &rtw_xmtr_restart, 0, 173 CTL_CREATE, CTL_EOL)) != 0) 174 goto err; 175 176 #ifdef RTW_DEBUG 177 /* control debugging printfs */ 178 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 179 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 180 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 181 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 182 CTL_CREATE, CTL_EOL)) != 0) 183 goto err; 184 185 /* Limit rx buffers, for simulating resource exhaustion. */ 186 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 187 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 188 "rxbufs_limit", 189 SYSCTL_DESCR("Set rx buffers limit"), 190 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 191 CTL_CREATE, CTL_EOL)) != 0) 192 goto err; 193 194 #endif /* RTW_DEBUG */ 195 /* set fallback RF programming method */ 196 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 197 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 198 "rfprog_fallback", 199 SYSCTL_DESCR("Set fallback RF programming method"), 200 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 201 CTL_CREATE, CTL_EOL)) != 0) 202 goto err; 203 204 /* force host to control RF I/O bus */ 205 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 206 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 207 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 208 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 209 CTL_CREATE, CTL_EOL)) != 0) 210 goto err; 211 212 return; 213 err: 214 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 215 } 216 217 static int 218 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 219 { 220 int error, t; 221 struct sysctlnode node; 222 223 node = *rnode; 224 t = *(int*)rnode->sysctl_data; 225 node.sysctl_data = &t; 226 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 227 if (error || newp == NULL) 228 return (error); 229 230 if (t < lower || t > upper) 231 return (EINVAL); 232 233 *(int*)rnode->sysctl_data = t; 234 235 return (0); 236 } 237 238 static int 239 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 240 { 241 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 242 SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 243 } 244 245 static int 246 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 247 { 248 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 249 } 250 251 #ifdef RTW_DEBUG 252 static int 253 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 254 { 255 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 256 0, RTW_DEBUG_MAX); 257 } 258 259 static int 260 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 261 { 262 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 263 0, RTW_RXQLEN); 264 } 265 266 static void 267 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 268 { 269 #define PRINTREG32(sc, reg) \ 270 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 271 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 272 dvname, reg, RTW_READ(regs, reg))) 273 274 #define PRINTREG16(sc, reg) \ 275 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 276 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 277 dvname, reg, RTW_READ16(regs, reg))) 278 279 #define PRINTREG8(sc, reg) \ 280 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 281 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 282 dvname, reg, RTW_READ8(regs, reg))) 283 284 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 285 286 PRINTREG32(regs, RTW_IDR0); 287 PRINTREG32(regs, RTW_IDR1); 288 PRINTREG32(regs, RTW_MAR0); 289 PRINTREG32(regs, RTW_MAR1); 290 PRINTREG32(regs, RTW_TSFTRL); 291 PRINTREG32(regs, RTW_TSFTRH); 292 PRINTREG32(regs, RTW_TLPDA); 293 PRINTREG32(regs, RTW_TNPDA); 294 PRINTREG32(regs, RTW_THPDA); 295 PRINTREG32(regs, RTW_TCR); 296 PRINTREG32(regs, RTW_RCR); 297 PRINTREG32(regs, RTW_TINT); 298 PRINTREG32(regs, RTW_TBDA); 299 PRINTREG32(regs, RTW_ANAPARM); 300 PRINTREG32(regs, RTW_BB); 301 PRINTREG32(regs, RTW_PHYCFG); 302 PRINTREG32(regs, RTW_WAKEUP0L); 303 PRINTREG32(regs, RTW_WAKEUP0H); 304 PRINTREG32(regs, RTW_WAKEUP1L); 305 PRINTREG32(regs, RTW_WAKEUP1H); 306 PRINTREG32(regs, RTW_WAKEUP2LL); 307 PRINTREG32(regs, RTW_WAKEUP2LH); 308 PRINTREG32(regs, RTW_WAKEUP2HL); 309 PRINTREG32(regs, RTW_WAKEUP2HH); 310 PRINTREG32(regs, RTW_WAKEUP3LL); 311 PRINTREG32(regs, RTW_WAKEUP3LH); 312 PRINTREG32(regs, RTW_WAKEUP3HL); 313 PRINTREG32(regs, RTW_WAKEUP3HH); 314 PRINTREG32(regs, RTW_WAKEUP4LL); 315 PRINTREG32(regs, RTW_WAKEUP4LH); 316 PRINTREG32(regs, RTW_WAKEUP4HL); 317 PRINTREG32(regs, RTW_WAKEUP4HH); 318 PRINTREG32(regs, RTW_DK0); 319 PRINTREG32(regs, RTW_DK1); 320 PRINTREG32(regs, RTW_DK2); 321 PRINTREG32(regs, RTW_DK3); 322 PRINTREG32(regs, RTW_RETRYCTR); 323 PRINTREG32(regs, RTW_RDSAR); 324 PRINTREG32(regs, RTW_FER); 325 PRINTREG32(regs, RTW_FEMR); 326 PRINTREG32(regs, RTW_FPSR); 327 PRINTREG32(regs, RTW_FFER); 328 329 /* 16-bit registers */ 330 PRINTREG16(regs, RTW_BRSR); 331 PRINTREG16(regs, RTW_IMR); 332 PRINTREG16(regs, RTW_ISR); 333 PRINTREG16(regs, RTW_BCNITV); 334 PRINTREG16(regs, RTW_ATIMWND); 335 PRINTREG16(regs, RTW_BINTRITV); 336 PRINTREG16(regs, RTW_ATIMTRITV); 337 PRINTREG16(regs, RTW_CRC16ERR); 338 PRINTREG16(regs, RTW_CRC0); 339 PRINTREG16(regs, RTW_CRC1); 340 PRINTREG16(regs, RTW_CRC2); 341 PRINTREG16(regs, RTW_CRC3); 342 PRINTREG16(regs, RTW_CRC4); 343 PRINTREG16(regs, RTW_CWR); 344 345 /* 8-bit registers */ 346 PRINTREG8(regs, RTW_CR); 347 PRINTREG8(regs, RTW_9346CR); 348 PRINTREG8(regs, RTW_CONFIG0); 349 PRINTREG8(regs, RTW_CONFIG1); 350 PRINTREG8(regs, RTW_CONFIG2); 351 PRINTREG8(regs, RTW_MSR); 352 PRINTREG8(regs, RTW_CONFIG3); 353 PRINTREG8(regs, RTW_CONFIG4); 354 PRINTREG8(regs, RTW_TESTR); 355 PRINTREG8(regs, RTW_PSR); 356 PRINTREG8(regs, RTW_SCR); 357 PRINTREG8(regs, RTW_PHYDELAY); 358 PRINTREG8(regs, RTW_CRCOUNT); 359 PRINTREG8(regs, RTW_PHYADDR); 360 PRINTREG8(regs, RTW_PHYDATAW); 361 PRINTREG8(regs, RTW_PHYDATAR); 362 PRINTREG8(regs, RTW_CONFIG5); 363 PRINTREG8(regs, RTW_TPPOLL); 364 365 PRINTREG16(regs, RTW_BSSID16); 366 PRINTREG32(regs, RTW_BSSID32); 367 #undef PRINTREG32 368 #undef PRINTREG16 369 #undef PRINTREG8 370 } 371 #endif /* RTW_DEBUG */ 372 373 void 374 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 375 { 376 struct rtw_regs *regs = &sc->sc_regs; 377 378 uint32_t tcr; 379 tcr = RTW_READ(regs, RTW_TCR); 380 tcr &= ~RTW_TCR_LBK_MASK; 381 if (enable) 382 tcr |= RTW_TCR_LBK_CONT; 383 else 384 tcr |= RTW_TCR_LBK_NORMAL; 385 RTW_WRITE(regs, RTW_TCR, tcr); 386 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 387 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 388 rtw_txdac_enable(sc, !enable); 389 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 390 rtw_set_access(regs, RTW_ACCESS_NONE); 391 } 392 393 #ifdef RTW_DEBUG 394 static const char * 395 rtw_access_string(enum rtw_access access) 396 { 397 switch (access) { 398 case RTW_ACCESS_NONE: 399 return "none"; 400 case RTW_ACCESS_CONFIG: 401 return "config"; 402 case RTW_ACCESS_ANAPARM: 403 return "anaparm"; 404 default: 405 return "unknown"; 406 } 407 } 408 #endif /* RTW_DEBUG */ 409 410 static void 411 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 412 { 413 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 414 KASSERT(regs->r_access >= RTW_ACCESS_NONE && 415 regs->r_access <= RTW_ACCESS_ANAPARM); 416 417 if (naccess == regs->r_access) 418 return; 419 420 switch (naccess) { 421 case RTW_ACCESS_NONE: 422 switch (regs->r_access) { 423 case RTW_ACCESS_ANAPARM: 424 rtw_anaparm_enable(regs, 0); 425 /*FALLTHROUGH*/ 426 case RTW_ACCESS_CONFIG: 427 rtw_config0123_enable(regs, 0); 428 /*FALLTHROUGH*/ 429 case RTW_ACCESS_NONE: 430 break; 431 } 432 break; 433 case RTW_ACCESS_CONFIG: 434 switch (regs->r_access) { 435 case RTW_ACCESS_NONE: 436 rtw_config0123_enable(regs, 1); 437 /*FALLTHROUGH*/ 438 case RTW_ACCESS_CONFIG: 439 break; 440 case RTW_ACCESS_ANAPARM: 441 rtw_anaparm_enable(regs, 0); 442 break; 443 } 444 break; 445 case RTW_ACCESS_ANAPARM: 446 switch (regs->r_access) { 447 case RTW_ACCESS_NONE: 448 rtw_config0123_enable(regs, 1); 449 /*FALLTHROUGH*/ 450 case RTW_ACCESS_CONFIG: 451 rtw_anaparm_enable(regs, 1); 452 /*FALLTHROUGH*/ 453 case RTW_ACCESS_ANAPARM: 454 break; 455 } 456 break; 457 } 458 } 459 460 void 461 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 462 { 463 rtw_set_access1(regs, access); 464 RTW_DPRINTF(RTW_DEBUG_ACCESS, 465 ("%s: access %s -> %s\n", __func__, 466 rtw_access_string(regs->r_access), 467 rtw_access_string(access))); 468 regs->r_access = access; 469 } 470 471 /* 472 * Enable registers, switch register banks. 473 */ 474 void 475 rtw_config0123_enable(struct rtw_regs *regs, int enable) 476 { 477 uint8_t ecr; 478 ecr = RTW_READ8(regs, RTW_9346CR); 479 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 480 if (enable) 481 ecr |= RTW_9346CR_EEM_CONFIG; 482 else { 483 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 484 ecr |= RTW_9346CR_EEM_NORMAL; 485 } 486 RTW_WRITE8(regs, RTW_9346CR, ecr); 487 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 488 } 489 490 /* requires rtw_config0123_enable(, 1) */ 491 void 492 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 493 { 494 uint8_t cfg3; 495 496 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 497 cfg3 |= RTW_CONFIG3_CLKRUNEN; 498 if (enable) 499 cfg3 |= RTW_CONFIG3_PARMEN; 500 else 501 cfg3 &= ~RTW_CONFIG3_PARMEN; 502 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 503 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 504 } 505 506 /* requires rtw_anaparm_enable(, 1) */ 507 void 508 rtw_txdac_enable(struct rtw_softc *sc, int enable) 509 { 510 uint32_t anaparm; 511 struct rtw_regs *regs = &sc->sc_regs; 512 513 anaparm = RTW_READ(regs, RTW_ANAPARM); 514 if (enable) 515 anaparm &= ~RTW_ANAPARM_TXDACOFF; 516 else 517 anaparm |= RTW_ANAPARM_TXDACOFF; 518 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 519 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 520 } 521 522 static inline int 523 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 524 { 525 uint8_t cr; 526 int i; 527 528 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 529 530 RTW_WBR(regs, RTW_CR, RTW_CR); 531 532 for (i = 0; i < 1000; i++) { 533 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 534 RTW_DPRINTF(RTW_DEBUG_RESET, 535 ("%s: reset in %dus\n", dvname, i)); 536 return 0; 537 } 538 RTW_RBR(regs, RTW_CR, RTW_CR); 539 DELAY(10); /* 10us */ 540 } 541 542 printf("%s: reset failed\n", dvname); 543 return ETIMEDOUT; 544 } 545 546 static inline int 547 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 548 { 549 uint32_t tcr; 550 551 /* from Linux driver */ 552 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 553 SHIFTIN(7, RTW_TCR_SRL_MASK) | SHIFTIN(7, RTW_TCR_LRL_MASK); 554 555 RTW_WRITE(regs, RTW_TCR, tcr); 556 557 RTW_WBW(regs, RTW_CR, RTW_TCR); 558 559 return rtw_chip_reset1(regs, dvname); 560 } 561 562 static int 563 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen) 564 { 565 struct ieee80211_key keycopy; 566 567 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 568 569 keycopy = *k; 570 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 571 572 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, hdrlen); 573 } 574 575 static int 576 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 577 { 578 struct rtw_softc *sc = ic->ic_ifp->if_softc; 579 u_int keyix = k->wk_keyix; 580 581 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix)); 582 583 if (keyix >= IEEE80211_WEP_NKID) 584 return 0; 585 if (k->wk_keylen != 0) 586 sc->sc_flags &= ~RTW_F_DK_VALID; 587 588 return 1; 589 } 590 591 static int 592 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 593 const u_int8_t mac[IEEE80211_ADDR_LEN]) 594 { 595 struct rtw_softc *sc = ic->ic_ifp->if_softc; 596 597 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 598 599 if (k->wk_keyix >= IEEE80211_WEP_NKID) 600 return 0; 601 602 sc->sc_flags &= ~RTW_F_DK_VALID; 603 604 return 1; 605 } 606 607 static void 608 rtw_key_update_begin(struct ieee80211com *ic) 609 { 610 #ifdef RTW_DEBUG 611 struct ifnet *ifp = ic->ic_ifp; 612 struct rtw_softc *sc = ifp->if_softc; 613 #endif 614 615 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 616 } 617 618 static void 619 rtw_key_update_end(struct ieee80211com *ic) 620 { 621 struct ifnet *ifp = ic->ic_ifp; 622 struct rtw_softc *sc = ifp->if_softc; 623 624 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 625 626 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 || 627 (sc->sc_flags & RTW_F_ENABLED) == 0 || 628 (sc->sc_flags & RTW_F_INVALID) != 0) 629 return; 630 631 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 632 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 633 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 634 (ifp->if_flags & IFF_RUNNING) != 0); 635 } 636 637 static inline int 638 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k) 639 { 640 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 641 return 0; 642 643 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) || 644 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13); 645 } 646 647 static void 648 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 649 { 650 uint8_t psr, scr; 651 int i, keylen; 652 struct rtw_regs *regs; 653 union rtw_keys *rk; 654 655 regs = &sc->sc_regs; 656 rk = &sc->sc_keys; 657 658 (void)memset(rk->rk_keys, 0, sizeof(rk->rk_keys)); 659 660 /* Temporarily use software crypto for all keys. */ 661 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 662 if (wk[i].wk_cipher == &rtw_cipher_wep) 663 wk[i].wk_cipher = &ieee80211_cipher_wep; 664 } 665 666 rtw_set_access(regs, RTW_ACCESS_CONFIG); 667 668 psr = RTW_READ8(regs, RTW_PSR); 669 scr = RTW_READ8(regs, RTW_SCR); 670 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 671 672 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 673 goto out; 674 675 for (keylen = i = 0; i < IEEE80211_WEP_NKID; i++) { 676 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i])) 677 continue; 678 if (i == txkey) { 679 keylen = wk[i].wk_keylen; 680 break; 681 } 682 keylen = MAX(keylen, wk[i].wk_keylen); 683 } 684 685 if (keylen == 5) 686 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON; 687 else if (keylen == 13) 688 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON; 689 690 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 691 if (wk[i].wk_keylen != keylen || 692 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 693 continue; 694 /* h/w will decrypt, s/w still strips headers */ 695 wk[i].wk_cipher = &rtw_cipher_wep; 696 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 697 } 698 699 out: 700 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 701 702 bus_space_write_region_4(regs->r_bt, regs->r_bh, 703 RTW_DK0, rk->rk_words, 704 sizeof(rk->rk_words) / sizeof(rk->rk_words[0])); 705 706 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 707 BUS_SPACE_BARRIER_SYNC); 708 709 RTW_WBW(regs, RTW_DK0, RTW_PSR); 710 RTW_WRITE8(regs, RTW_PSR, psr); 711 RTW_WBW(regs, RTW_PSR, RTW_SCR); 712 RTW_WRITE8(regs, RTW_SCR, scr); 713 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 714 rtw_set_access(regs, RTW_ACCESS_NONE); 715 sc->sc_flags |= RTW_F_DK_VALID; 716 } 717 718 static inline int 719 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 720 { 721 int i; 722 uint8_t ecr; 723 724 ecr = RTW_READ8(regs, RTW_9346CR); 725 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 726 RTW_WRITE8(regs, RTW_9346CR, ecr); 727 728 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 729 730 /* wait 25ms for completion */ 731 for (i = 0; i < 250; i++) { 732 ecr = RTW_READ8(regs, RTW_9346CR); 733 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 734 RTW_DPRINTF(RTW_DEBUG_RESET, 735 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 736 return 0; 737 } 738 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 739 DELAY(100); 740 } 741 printf("%s: recall EEPROM failed\n", dvname); 742 return ETIMEDOUT; 743 } 744 745 static inline int 746 rtw_reset(struct rtw_softc *sc) 747 { 748 int rc; 749 uint8_t config1; 750 751 sc->sc_flags &= ~RTW_F_DK_VALID; 752 753 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 754 return rc; 755 756 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 757 ; 758 759 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 760 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 761 /* TBD turn off maximum power saving? */ 762 763 return 0; 764 } 765 766 static inline int 767 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 768 u_int ndescs) 769 { 770 int i, rc = 0; 771 for (i = 0; i < ndescs; i++) { 772 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 773 0, 0, &descs[i].ts_dmamap); 774 if (rc != 0) 775 break; 776 } 777 return rc; 778 } 779 780 static inline int 781 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 782 u_int ndescs) 783 { 784 int i, rc = 0; 785 for (i = 0; i < ndescs; i++) { 786 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 787 &descs[i].rs_dmamap); 788 if (rc != 0) 789 break; 790 } 791 return rc; 792 } 793 794 static inline void 795 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 796 u_int ndescs) 797 { 798 int i; 799 for (i = 0; i < ndescs; i++) { 800 if (descs[i].rs_dmamap != NULL) 801 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 802 } 803 } 804 805 static inline void 806 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 807 u_int ndescs) 808 { 809 int i; 810 for (i = 0; i < ndescs; i++) { 811 if (descs[i].ts_dmamap != NULL) 812 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 813 } 814 } 815 816 static inline void 817 rtw_srom_free(struct rtw_srom *sr) 818 { 819 sr->sr_size = 0; 820 if (sr->sr_content == NULL) 821 return; 822 free(sr->sr_content, M_DEVBUF); 823 sr->sr_content = NULL; 824 } 825 826 static void 827 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 828 enum rtw_rfchipid *rfchipid, uint32_t *rcr) 829 { 830 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 831 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 832 *rcr |= RTW_RCR_ENCS1; 833 *rfchipid = RTW_RFCHIPID_PHILIPS; 834 } 835 836 static int 837 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 838 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 839 const char *dvname) 840 { 841 int i; 842 const char *rfname, *paname; 843 char scratch[sizeof("unknown 0xXX")]; 844 uint16_t srom_version; 845 uint8_t mac[IEEE80211_ADDR_LEN]; 846 847 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 848 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 849 850 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 851 printf("%s: SROM version %d.%d", dvname, 852 srom_version >> 8, srom_version & 0xff); 853 854 if (srom_version <= 0x0101) { 855 printf(" is not understood, limping along with defaults\n"); 856 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 857 return 0; 858 } 859 printf("\n"); 860 861 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 862 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 863 864 RTW_DPRINTF(RTW_DEBUG_ATTACH, 865 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 866 867 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 868 869 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 870 *flags |= RTW_F_ANTDIV; 871 872 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 873 * to be reversed. 874 */ 875 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 876 *flags |= RTW_F_DIGPHY; 877 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 878 *flags |= RTW_F_DFLANTB; 879 880 *rcr |= SHIFTIN(SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), 881 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 882 883 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0) 884 *flags |= RTW_C_RXWEP_104; 885 886 *flags |= RTW_C_RXWEP_40; /* XXX */ 887 888 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 889 switch (*rfchipid) { 890 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 891 rfname = "GCT GRF5101"; 892 paname = "Winspring WS9901"; 893 break; 894 case RTW_RFCHIPID_MAXIM: 895 rfname = "Maxim MAX2820"; /* guess */ 896 paname = "Maxim MAX2422"; /* guess */ 897 break; 898 case RTW_RFCHIPID_INTERSIL: 899 rfname = "Intersil HFA3873"; /* guess */ 900 paname = "Intersil <unknown>"; 901 break; 902 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 903 rfname = "Philips SA2400A"; 904 paname = "Philips SA2411"; 905 break; 906 case RTW_RFCHIPID_RFMD: 907 /* this is the same front-end as an atw(4)! */ 908 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 909 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 910 "SYN: Silicon Labs Si4126"; /* inferred from 911 * reference driver 912 */ 913 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 914 break; 915 case RTW_RFCHIPID_RESERVED: 916 rfname = paname = "reserved"; 917 break; 918 default: 919 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 920 rfname = paname = scratch; 921 } 922 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 923 924 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 925 case RTW_CONFIG0_GL_USA: 926 case _RTW_CONFIG0_GL_USA: 927 *locale = RTW_LOCALE_USA; 928 break; 929 case RTW_CONFIG0_GL_EUROPE: 930 *locale = RTW_LOCALE_EUROPE; 931 break; 932 case RTW_CONFIG0_GL_JAPAN: 933 *locale = RTW_LOCALE_JAPAN; 934 break; 935 default: 936 *locale = RTW_LOCALE_UNKNOWN; 937 break; 938 } 939 return 0; 940 } 941 942 /* Returns -1 on failure. */ 943 static int 944 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 945 const char *dvname) 946 { 947 int rc; 948 struct seeprom_descriptor sd; 949 uint8_t ecr; 950 951 (void)memset(&sd, 0, sizeof(sd)); 952 953 ecr = RTW_READ8(regs, RTW_9346CR); 954 955 if ((flags & RTW_F_9356SROM) != 0) { 956 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 957 sr->sr_size = 256; 958 sd.sd_chip = C56_66; 959 } else { 960 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 961 sr->sr_size = 128; 962 sd.sd_chip = C46; 963 } 964 965 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 966 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 967 ecr |= RTW_9346CR_EEM_PROGRAM; 968 969 RTW_WRITE8(regs, RTW_9346CR, ecr); 970 971 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 972 973 if (sr->sr_content == NULL) { 974 printf("%s: unable to allocate SROM buffer\n", dvname); 975 return ENOMEM; 976 } 977 978 (void)memset(sr->sr_content, 0, sr->sr_size); 979 980 /* RTL8180 has a single 8-bit register for controlling the 981 * 93cx6 SROM. There is no "ready" bit. The RTL8180 982 * input/output sense is the reverse of read_seeprom's. 983 */ 984 sd.sd_tag = regs->r_bt; 985 sd.sd_bsh = regs->r_bh; 986 sd.sd_regsize = 1; 987 sd.sd_control_offset = RTW_9346CR; 988 sd.sd_status_offset = RTW_9346CR; 989 sd.sd_dataout_offset = RTW_9346CR; 990 sd.sd_CK = RTW_9346CR_EESK; 991 sd.sd_CS = RTW_9346CR_EECS; 992 sd.sd_DI = RTW_9346CR_EEDO; 993 sd.sd_DO = RTW_9346CR_EEDI; 994 /* make read_seeprom enter EEPROM read/write mode */ 995 sd.sd_MS = ecr; 996 sd.sd_RDY = 0; 997 998 /* TBD bus barriers */ 999 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 1000 printf("%s: could not read SROM\n", dvname); 1001 free(sr->sr_content, M_DEVBUF); 1002 sr->sr_content = NULL; 1003 return -1; /* XXX */ 1004 } 1005 1006 /* end EEPROM read/write mode */ 1007 RTW_WRITE8(regs, RTW_9346CR, 1008 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 1009 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 1010 1011 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 1012 return rc; 1013 1014 #ifdef RTW_DEBUG 1015 { 1016 int i; 1017 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1018 ("\n%s: serial ROM:\n\t", dvname)); 1019 for (i = 0; i < sr->sr_size/2; i++) { 1020 if (((i % 8) == 0) && (i != 0)) 1021 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 1022 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1023 (" %04x", sr->sr_content[i])); 1024 } 1025 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 1026 } 1027 #endif /* RTW_DEBUG */ 1028 return 0; 1029 } 1030 1031 static void 1032 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 1033 const char *dvname) 1034 { 1035 uint8_t cfg4; 1036 const char *method; 1037 1038 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 1039 1040 switch (rfchipid) { 1041 default: 1042 cfg4 |= SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 1043 method = "fallback"; 1044 break; 1045 case RTW_RFCHIPID_INTERSIL: 1046 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1047 method = "Intersil"; 1048 break; 1049 case RTW_RFCHIPID_PHILIPS: 1050 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1051 method = "Philips"; 1052 break; 1053 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1054 case RTW_RFCHIPID_RFMD: 1055 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1056 method = "RFMD"; 1057 break; 1058 } 1059 1060 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1061 1062 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1063 1064 RTW_DPRINTF(RTW_DEBUG_INIT, 1065 ("%s: %s RF programming method, %#02x\n", dvname, method, 1066 RTW_READ8(regs, RTW_CONFIG4))); 1067 } 1068 1069 static inline void 1070 rtw_init_channels(enum rtw_locale locale, 1071 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 1072 const char *dvname) 1073 { 1074 int i; 1075 const char *name = NULL; 1076 #define ADD_CHANNEL(_chans, _chan) do { \ 1077 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1078 (*_chans)[_chan].ic_freq = \ 1079 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1080 } while (0) 1081 1082 switch (locale) { 1083 case RTW_LOCALE_USA: /* 1-11 */ 1084 name = "USA"; 1085 for (i = 1; i <= 11; i++) 1086 ADD_CHANNEL(chans, i); 1087 break; 1088 case RTW_LOCALE_JAPAN: /* 1-14 */ 1089 name = "Japan"; 1090 ADD_CHANNEL(chans, 14); 1091 for (i = 1; i <= 14; i++) 1092 ADD_CHANNEL(chans, i); 1093 break; 1094 case RTW_LOCALE_EUROPE: /* 1-13 */ 1095 name = "Europe"; 1096 for (i = 1; i <= 13; i++) 1097 ADD_CHANNEL(chans, i); 1098 break; 1099 default: /* 10-11 allowed by most countries */ 1100 name = "<unknown>"; 1101 for (i = 10; i <= 11; i++) 1102 ADD_CHANNEL(chans, i); 1103 break; 1104 } 1105 printf("%s: Geographic Location %s\n", dvname, name); 1106 #undef ADD_CHANNEL 1107 } 1108 1109 1110 static inline void 1111 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale) 1112 { 1113 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1114 1115 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1116 case RTW_CONFIG0_GL_USA: 1117 case _RTW_CONFIG0_GL_USA: 1118 *locale = RTW_LOCALE_USA; 1119 break; 1120 case RTW_CONFIG0_GL_JAPAN: 1121 *locale = RTW_LOCALE_JAPAN; 1122 break; 1123 case RTW_CONFIG0_GL_EUROPE: 1124 *locale = RTW_LOCALE_EUROPE; 1125 break; 1126 default: 1127 *locale = RTW_LOCALE_UNKNOWN; 1128 break; 1129 } 1130 } 1131 1132 static inline int 1133 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1134 const char *dvname) 1135 { 1136 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1138 }; 1139 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1140 idr1 = RTW_READ(regs, RTW_IDR1); 1141 1142 (*addr)[0] = SHIFTOUT(idr0, BITS(0, 7)); 1143 (*addr)[1] = SHIFTOUT(idr0, BITS(8, 15)); 1144 (*addr)[2] = SHIFTOUT(idr0, BITS(16, 23)); 1145 (*addr)[3] = SHIFTOUT(idr0, BITS(24 ,31)); 1146 1147 (*addr)[4] = SHIFTOUT(idr1, BITS(0, 7)); 1148 (*addr)[5] = SHIFTOUT(idr1, BITS(8, 15)); 1149 1150 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1151 printf("%s: could not get mac address, attach failed\n", 1152 dvname); 1153 return ENXIO; 1154 } 1155 1156 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 1157 1158 return 0; 1159 } 1160 1161 static uint8_t 1162 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1163 struct ieee80211_channel *chan) 1164 { 1165 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1166 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 1167 ("%s: channel %d out of range", __func__, 1168 idx - RTW_SR_TXPOWER1 + 1)); 1169 return RTW_SR_GET(sr, idx); 1170 } 1171 1172 static void 1173 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1174 { 1175 int pri; 1176 /* nfree: the number of free descriptors in each ring. 1177 * The beacon ring is a special case: I do not let the 1178 * driver use all of the descriptors on the beacon ring. 1179 * The reasons are two-fold: 1180 * 1181 * (1) A BEACON descriptor's OWN bit is (apparently) not 1182 * updated, so the driver cannot easily know if the descriptor 1183 * belongs to it, or if it is racing the NIC. If the NIC 1184 * does not OWN every descriptor, then the driver can safely 1185 * update the descriptors when RTW_TBDA points at tdb_next. 1186 * 1187 * (2) I hope that the NIC will process more than one BEACON 1188 * descriptor in a single beacon interval, since that will 1189 * enable multiple-BSS support. Since the NIC does not 1190 * clear the OWN bit, there is no natural place for it to 1191 * stop processing BEACON desciptors. Maybe it will *not* 1192 * stop processing them! I do not want to chance the NIC 1193 * looping around and around a saturated beacon ring, so 1194 * I will leave one descriptor unOWNed at all times. 1195 */ 1196 u_int nfree[RTW_NTXPRI] = 1197 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, 1198 RTW_NTXDESCBCN - 1}; 1199 1200 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1201 tdb[pri].tdb_nfree = nfree[pri]; 1202 tdb[pri].tdb_next = 0; 1203 } 1204 } 1205 1206 static int 1207 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1208 { 1209 int i; 1210 struct rtw_txsoft *ts; 1211 1212 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1213 SIMPLEQ_INIT(&tsb->tsb_freeq); 1214 for (i = 0; i < tsb->tsb_ndesc; i++) { 1215 ts = &tsb->tsb_desc[i]; 1216 ts->ts_mbuf = NULL; 1217 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1218 } 1219 tsb->tsb_tx_timer = 0; 1220 return 0; 1221 } 1222 1223 static void 1224 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1225 { 1226 int pri; 1227 for (pri = 0; pri < RTW_NTXPRI; pri++) 1228 rtw_txsoft_blk_init(&tsb[pri]); 1229 } 1230 1231 static inline void 1232 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1233 { 1234 KASSERT(nsync <= rdb->rdb_ndesc); 1235 /* sync to end of ring */ 1236 if (desc0 + nsync > rdb->rdb_ndesc) { 1237 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1238 offsetof(struct rtw_descs, hd_rx[desc0]), 1239 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1240 nsync -= (rdb->rdb_ndesc - desc0); 1241 desc0 = 0; 1242 } 1243 1244 KASSERT(desc0 < rdb->rdb_ndesc); 1245 KASSERT(nsync <= rdb->rdb_ndesc); 1246 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1247 1248 /* sync what remains */ 1249 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1250 offsetof(struct rtw_descs, hd_rx[desc0]), 1251 sizeof(struct rtw_rxdesc) * nsync, ops); 1252 } 1253 1254 static void 1255 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1256 { 1257 /* sync to end of ring */ 1258 if (desc0 + nsync > tdb->tdb_ndesc) { 1259 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1260 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1261 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1262 ops); 1263 nsync -= (tdb->tdb_ndesc - desc0); 1264 desc0 = 0; 1265 } 1266 1267 /* sync what remains */ 1268 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1269 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1270 sizeof(struct rtw_txdesc) * nsync, ops); 1271 } 1272 1273 static void 1274 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1275 { 1276 int pri; 1277 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1278 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1279 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1280 } 1281 } 1282 1283 static void 1284 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1285 { 1286 int i; 1287 struct rtw_rxsoft *rs; 1288 1289 for (i = 0; i < RTW_RXQLEN; i++) { 1290 rs = &desc[i]; 1291 if (rs->rs_mbuf == NULL) 1292 continue; 1293 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1294 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1295 bus_dmamap_unload(dmat, rs->rs_dmamap); 1296 m_freem(rs->rs_mbuf); 1297 rs->rs_mbuf = NULL; 1298 } 1299 } 1300 1301 static inline int 1302 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1303 { 1304 int rc; 1305 struct mbuf *m; 1306 1307 MGETHDR(m, M_DONTWAIT, MT_DATA); 1308 if (m == NULL) 1309 return ENOBUFS; 1310 1311 MCLGET(m, M_DONTWAIT); 1312 if ((m->m_flags & M_EXT) == 0) { 1313 m_freem(m); 1314 return ENOBUFS; 1315 } 1316 1317 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1318 1319 if (rs->rs_mbuf != NULL) 1320 bus_dmamap_unload(dmat, rs->rs_dmamap); 1321 1322 rs->rs_mbuf = NULL; 1323 1324 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1325 if (rc != 0) { 1326 m_freem(m); 1327 return -1; 1328 } 1329 1330 rs->rs_mbuf = m; 1331 1332 return 0; 1333 } 1334 1335 static int 1336 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1337 int *ndesc, const char *dvname) 1338 { 1339 int i, rc = 0; 1340 struct rtw_rxsoft *rs; 1341 1342 for (i = 0; i < RTW_RXQLEN; i++) { 1343 rs = &desc[i]; 1344 /* we're in rtw_init, so there should be no mbufs allocated */ 1345 KASSERT(rs->rs_mbuf == NULL); 1346 #ifdef RTW_DEBUG 1347 if (i == rtw_rxbufs_limit) { 1348 printf("%s: TEST hit %d-buffer limit\n", dvname, i); 1349 rc = ENOBUFS; 1350 break; 1351 } 1352 #endif /* RTW_DEBUG */ 1353 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1354 printf("%s: rtw_rxsoft_alloc failed, %d buffers, " 1355 "rc %d\n", dvname, i, rc); 1356 break; 1357 } 1358 } 1359 *ndesc = i; 1360 return rc; 1361 } 1362 1363 static inline void 1364 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1365 int idx, int kick) 1366 { 1367 int is_last = (idx == rdb->rdb_ndesc - 1); 1368 uint32_t ctl, octl, obuf; 1369 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1370 1371 obuf = rd->rd_buf; 1372 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1373 1374 ctl = SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1375 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1376 1377 if (is_last) 1378 ctl |= RTW_RXCTL_EOR; 1379 1380 octl = rd->rd_ctl; 1381 rd->rd_ctl = htole32(ctl); 1382 1383 RTW_DPRINTF( 1384 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1385 : RTW_DEBUG_RECV_DESC, 1386 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1387 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1388 le32toh(rd->rd_ctl))); 1389 1390 /* sync the mbuf */ 1391 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1392 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1393 1394 /* sync the descriptor */ 1395 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1396 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1397 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1398 } 1399 1400 static void 1401 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1402 { 1403 int i; 1404 struct rtw_rxdesc *rd; 1405 struct rtw_rxsoft *rs; 1406 1407 for (i = 0; i < rdb->rdb_ndesc; i++) { 1408 rd = &rdb->rdb_desc[i]; 1409 rs = &ctl[i]; 1410 rtw_rxdesc_init(rdb, rs, i, kick); 1411 } 1412 } 1413 1414 static void 1415 rtw_io_enable(struct rtw_regs *regs, uint8_t flags, int enable) 1416 { 1417 uint8_t cr; 1418 1419 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1420 enable ? "enable" : "disable", flags)); 1421 1422 cr = RTW_READ8(regs, RTW_CR); 1423 1424 /* XXX reference source does not enable MULRW */ 1425 #if 0 1426 /* enable PCI Read/Write Multiple */ 1427 cr |= RTW_CR_MULRW; 1428 #endif 1429 1430 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1431 if (enable) 1432 cr |= flags; 1433 else 1434 cr &= ~flags; 1435 RTW_WRITE8(regs, RTW_CR, cr); 1436 RTW_SYNC(regs, RTW_CR, RTW_CR); 1437 } 1438 1439 static void 1440 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1441 { 1442 #define IS_BEACON(__fc0) \ 1443 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1444 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1445 1446 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1447 * hardware -> net80211 1448 */ 1449 u_int next, nproc = 0; 1450 int hwrate, len, rate, rssi, sq; 1451 uint32_t hrssi, hstat, htsfth, htsftl; 1452 struct rtw_rxdesc *rd; 1453 struct rtw_rxsoft *rs; 1454 struct rtw_rxdesc_blk *rdb; 1455 struct mbuf *m; 1456 struct ifnet *ifp = &sc->sc_if; 1457 1458 struct ieee80211_node *ni; 1459 struct ieee80211_frame_min *wh; 1460 1461 rdb = &sc->sc_rxdesc_blk; 1462 1463 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1464 1465 for (next = rdb->rdb_next; ; next = (next + 1) % rdb->rdb_ndesc) { 1466 rtw_rxdescs_sync(rdb, next, 1, 1467 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1468 rd = &rdb->rdb_desc[next]; 1469 rs = &sc->sc_rxsoft[next]; 1470 1471 hstat = le32toh(rd->rd_stat); 1472 hrssi = le32toh(rd->rd_rssi); 1473 htsfth = le32toh(rd->rd_tsfth); 1474 htsftl = le32toh(rd->rd_tsftl); 1475 1476 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1477 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1478 __func__, next, hstat, hrssi, htsfth, htsftl)); 1479 1480 ++nproc; 1481 1482 /* still belongs to NIC */ 1483 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1484 if (nproc > 1) 1485 break; 1486 1487 /* sometimes the NIC skips to the 0th descriptor */ 1488 rtw_rxdescs_sync(rdb, 0, 1, 1489 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1490 rd = &rdb->rdb_desc[0]; 1491 if ((rd->rd_stat & htole32(RTW_RXSTAT_OWN)) != 0) 1492 break; 1493 RTW_DPRINTF(RTW_DEBUG_BUGS, 1494 ("%s: NIC skipped from rxdesc[%u] to rxdesc[0]\n", 1495 sc->sc_dev.dv_xname, next)); 1496 next = rdb->rdb_ndesc - 1; 1497 continue; 1498 } 1499 1500 #ifdef RTW_DEBUG 1501 #define PRINTSTAT(flag) do { \ 1502 if ((hstat & flag) != 0) { \ 1503 printf("%s" #flag, delim); \ 1504 delim = ","; \ 1505 } \ 1506 } while (0) 1507 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1508 const char *delim = "<"; 1509 printf("%s: ", sc->sc_dev.dv_xname); 1510 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1511 printf("status %08x", hstat); 1512 PRINTSTAT(RTW_RXSTAT_SPLCP); 1513 PRINTSTAT(RTW_RXSTAT_MAR); 1514 PRINTSTAT(RTW_RXSTAT_PAR); 1515 PRINTSTAT(RTW_RXSTAT_BAR); 1516 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1517 PRINTSTAT(RTW_RXSTAT_CRC32); 1518 PRINTSTAT(RTW_RXSTAT_ICV); 1519 printf(">, "); 1520 } 1521 } 1522 #endif /* RTW_DEBUG */ 1523 1524 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1525 printf("%s: DMA error/FIFO overflow %08x, " 1526 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1527 hstat & RTW_RXSTAT_IOERROR, next); 1528 ifp->if_ierrors++; 1529 goto next; 1530 } 1531 1532 len = SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); 1533 if (len < IEEE80211_MIN_LEN) { 1534 sc->sc_ic.ic_stats.is_rx_tooshort++; 1535 goto next; 1536 } 1537 1538 /* CRC is included with the packet; trim it off. */ 1539 len -= IEEE80211_CRC_LEN; 1540 1541 hwrate = SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); 1542 if (hwrate >= sizeof(ratetbl) / sizeof(ratetbl[0])) { 1543 printf("%s: unknown rate #%d\n", sc->sc_dev.dv_xname, 1544 SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); 1545 ifp->if_ierrors++; 1546 goto next; 1547 } 1548 rate = ratetbl[hwrate]; 1549 1550 #ifdef RTW_DEBUG 1551 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1552 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1553 (rate * 5) % 10, htsfth, htsftl)); 1554 #endif /* RTW_DEBUG */ 1555 1556 if ((hstat & RTW_RXSTAT_RES) != 0 && 1557 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1558 goto next; 1559 1560 /* if bad flags, skip descriptor */ 1561 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1562 printf("%s: too many rx segments\n", 1563 sc->sc_dev.dv_xname); 1564 goto next; 1565 } 1566 1567 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1568 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1569 1570 m = rs->rs_mbuf; 1571 1572 /* if temporarily out of memory, re-use mbuf */ 1573 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1574 case 0: 1575 break; 1576 case ENOBUFS: 1577 printf("%s: rtw_rxsoft_alloc(, %d) failed, " 1578 "dropping packet\n", sc->sc_dev.dv_xname, next); 1579 goto next; 1580 default: 1581 /* XXX shorten rx ring, instead? */ 1582 panic("%s: could not load DMA map\n", 1583 sc->sc_dev.dv_xname); 1584 } 1585 1586 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1587 rssi = SHIFTOUT(hrssi, RTW_RXRSSI_RSSI); 1588 else { 1589 rssi = SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); 1590 /* TBD find out each front-end's LNA gain in the 1591 * front-end's units 1592 */ 1593 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1594 rssi |= 0x80; 1595 } 1596 sq = SHIFTOUT(hrssi, RTW_RXRSSI_SQ); 1597 1598 /* Note well: now we cannot recycle the rs_mbuf unless 1599 * we restore its original length. 1600 */ 1601 m->m_pkthdr.rcvif = ifp; 1602 m->m_pkthdr.len = m->m_len = len; 1603 1604 wh = mtod(m, struct ieee80211_frame_min *); 1605 1606 if (!IS_BEACON(wh->i_fc[0])) 1607 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1608 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1609 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1610 1611 sc->sc_tsfth = htsfth; 1612 1613 #ifdef RTW_DEBUG 1614 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 1615 (IFF_DEBUG|IFF_LINK2)) { 1616 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1617 rate, rssi); 1618 } 1619 #endif /* RTW_DEBUG */ 1620 1621 #if NBPFILTER > 0 1622 if (sc->sc_radiobpf != NULL) { 1623 struct ieee80211com *ic = &sc->sc_ic; 1624 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1625 1626 rr->rr_tsft = 1627 htole64(((uint64_t)htsfth << 32) | htsftl); 1628 1629 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1630 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE; 1631 1632 rr->rr_flags = 0; 1633 rr->rr_rate = rate; 1634 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1635 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1636 rr->rr_antsignal = rssi; 1637 rr->rr_barker_lock = htole16(sq); 1638 1639 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rr, 1640 sizeof(sc->sc_rxtapu), m); 1641 } 1642 #endif /* NPBFILTER > 0 */ 1643 1644 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1645 ieee80211_free_node(ni); 1646 next: 1647 rtw_rxdesc_init(rdb, rs, next, 0); 1648 } 1649 rdb->rdb_next = next; 1650 1651 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1652 1653 return; 1654 #undef IS_BEACON 1655 } 1656 1657 static void 1658 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1659 struct rtw_txsoft *ts) 1660 { 1661 struct mbuf *m; 1662 struct ieee80211_node *ni; 1663 1664 m = ts->ts_mbuf; 1665 ni = ts->ts_ni; 1666 KASSERT(m != NULL); 1667 KASSERT(ni != NULL); 1668 ts->ts_mbuf = NULL; 1669 ts->ts_ni = NULL; 1670 1671 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1672 BUS_DMASYNC_POSTWRITE); 1673 bus_dmamap_unload(dmat, ts->ts_dmamap); 1674 m_freem(m); 1675 ieee80211_free_node(ni); 1676 } 1677 1678 static void 1679 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1680 struct rtw_txsoft_blk *tsb) 1681 { 1682 struct rtw_txsoft *ts; 1683 1684 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1685 rtw_txsoft_release(dmat, ic, ts); 1686 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1687 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1688 } 1689 tsb->tsb_tx_timer = 0; 1690 } 1691 1692 static inline void 1693 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1694 struct rtw_txsoft *ts, int ndesc) 1695 { 1696 uint32_t hstat; 1697 int data_retry, rts_retry; 1698 struct rtw_txdesc *tdn; 1699 const char *condstring; 1700 struct ifnet *ifp = &sc->sc_if; 1701 1702 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1703 1704 tdb->tdb_nfree += ndesc; 1705 1706 tdn = &tdb->tdb_desc[ts->ts_last]; 1707 1708 hstat = le32toh(tdn->td_stat); 1709 rts_retry = SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1710 data_retry = SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); 1711 1712 ifp->if_collisions += rts_retry + data_retry; 1713 1714 if ((hstat & RTW_TXSTAT_TOK) != 0) 1715 condstring = "ok"; 1716 else { 1717 ifp->if_oerrors++; 1718 condstring = "error"; 1719 } 1720 1721 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1722 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1723 sc->sc_dev.dv_xname, ts, ts->ts_first, ts->ts_last, 1724 condstring, rts_retry, data_retry)); 1725 } 1726 1727 static void 1728 rtw_reset_oactive(struct rtw_softc *sc) 1729 { 1730 short oflags; 1731 int pri; 1732 struct rtw_txsoft_blk *tsb; 1733 struct rtw_txdesc_blk *tdb; 1734 oflags = sc->sc_if.if_flags; 1735 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1736 tsb = &sc->sc_txsoft_blk[pri]; 1737 tdb = &sc->sc_txdesc_blk[pri]; 1738 if (!SIMPLEQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0) 1739 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1740 } 1741 if (oflags != sc->sc_if.if_flags) { 1742 DPRINTF(sc, RTW_DEBUG_OACTIVE, 1743 ("%s: reset OACTIVE\n", __func__)); 1744 } 1745 } 1746 1747 /* Collect transmitted packets. */ 1748 static inline void 1749 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1750 struct rtw_txdesc_blk *tdb, int force) 1751 { 1752 int ndesc; 1753 struct rtw_txsoft *ts; 1754 1755 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1756 ndesc = 1 + ts->ts_last - ts->ts_first; 1757 if (ts->ts_last < ts->ts_first) 1758 ndesc += tdb->tdb_ndesc; 1759 1760 KASSERT(ndesc > 0); 1761 1762 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1763 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1764 1765 if (force) { 1766 int i; 1767 for (i = ts->ts_first; ; i = RTW_NEXT_IDX(tdb, i)) { 1768 tdb->tdb_desc[i].td_stat &= 1769 ~htole32(RTW_TXSTAT_OWN); 1770 if (i == ts->ts_last) 1771 break; 1772 } 1773 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1774 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1775 } else if ((tdb->tdb_desc[ts->ts_last].td_stat & 1776 htole32(RTW_TXSTAT_OWN)) != 0) 1777 break; 1778 1779 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1780 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1781 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1782 } 1783 /* no more pending transmissions, cancel watchdog */ 1784 if (ts == NULL) 1785 tsb->tsb_tx_timer = 0; 1786 rtw_reset_oactive(sc); 1787 } 1788 1789 static void 1790 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1791 { 1792 int pri; 1793 struct rtw_txsoft_blk *tsb; 1794 struct rtw_txdesc_blk *tdb; 1795 struct ifnet *ifp = &sc->sc_if; 1796 1797 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1798 tsb = &sc->sc_txsoft_blk[pri]; 1799 tdb = &sc->sc_txdesc_blk[pri]; 1800 1801 rtw_collect_txring(sc, tsb, tdb, 0); 1802 } 1803 1804 if ((isr & RTW_INTR_TX) != 0) 1805 rtw_start(ifp); 1806 1807 return; 1808 } 1809 1810 static void 1811 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1812 { 1813 u_int next; 1814 uint32_t tsfth, tsftl; 1815 struct ieee80211com *ic; 1816 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN]; 1817 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN]; 1818 struct mbuf *m; 1819 1820 tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH); 1821 tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1822 1823 if ((isr & (RTW_INTR_TBDOK|RTW_INTR_TBDER)) != 0) { 1824 next = rtw_txring_next(&sc->sc_regs, tdb); 1825 RTW_DPRINTF(RTW_DEBUG_BEACON, 1826 ("%s: beacon ring %sprocessed, isr = %#04" PRIx16 1827 ", next %u expected %u, %" PRIu64 "\n", __func__, 1828 (next == tdb->tdb_next) ? "" : "un", isr, next, 1829 tdb->tdb_next, (uint64_t)tsfth << 32 | tsftl)); 1830 if ((RTW_READ8(&sc->sc_regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0){ 1831 rtw_collect_txring(sc, tsb, tdb, 1); 1832 tdb->tdb_next = 0; 1833 } 1834 } 1835 /* Start beacon transmission. */ 1836 1837 if ((isr & RTW_INTR_BCNINT) != 0 && 1838 sc->sc_ic.ic_state == IEEE80211_S_RUN && 1839 SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) { 1840 RTW_DPRINTF(RTW_DEBUG_BEACON, 1841 ("%s: beacon prep. time, isr = %#04" PRIx16 1842 ", %16" PRIu64 "\n", __func__, isr, 1843 (uint64_t)tsfth << 32 | tsftl)); 1844 ic = &sc->sc_ic; 1845 m = rtw_beacon_alloc(sc, ic->ic_bss); 1846 1847 if (m == NULL) { 1848 printf("%s: could not allocate beacon\n", 1849 sc->sc_dev.dv_xname); 1850 return; 1851 } 1852 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss); 1853 IF_ENQUEUE(&sc->sc_beaconq, m); 1854 rtw_start(&sc->sc_if); 1855 } 1856 } 1857 1858 static void 1859 rtw_intr_atim(struct rtw_softc *sc) 1860 { 1861 /* TBD */ 1862 return; 1863 } 1864 1865 #ifdef RTW_DEBUG 1866 static void 1867 rtw_dump_rings(struct rtw_softc *sc) 1868 { 1869 struct rtw_txdesc_blk *tdb; 1870 struct rtw_rxdesc *rd; 1871 struct rtw_rxdesc_blk *rdb; 1872 int desc, pri; 1873 1874 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1875 return; 1876 1877 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1878 tdb = &sc->sc_txdesc_blk[pri]; 1879 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1880 tdb->tdb_ndesc, tdb->tdb_nfree); 1881 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1882 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1883 } 1884 1885 rdb = &sc->sc_rxdesc_blk; 1886 1887 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1888 rd = &rdb->rdb_desc[desc]; 1889 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1890 "rsvd1/tsfth %08x\n", __func__, 1891 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1892 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1893 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1894 } 1895 } 1896 #endif /* RTW_DEBUG */ 1897 1898 static void 1899 rtw_hwring_setup(struct rtw_softc *sc) 1900 { 1901 int pri; 1902 struct rtw_regs *regs = &sc->sc_regs; 1903 struct rtw_txdesc_blk *tdb; 1904 1905 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_basereg = RTW_TLPDA; 1906 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_base = RTW_RING_BASE(sc, hd_txlo); 1907 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_basereg = RTW_TNPDA; 1908 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_base = RTW_RING_BASE(sc, hd_txmd); 1909 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_basereg = RTW_THPDA; 1910 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_base = RTW_RING_BASE(sc, hd_txhi); 1911 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_basereg = RTW_TBDA; 1912 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_base = RTW_RING_BASE(sc, hd_bcn); 1913 1914 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1915 tdb = &sc->sc_txdesc_blk[pri]; 1916 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base); 1917 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1918 ("%s: reg[tdb->tdb_basereg] <- %" PRIxPTR "\n", __func__, 1919 (uintptr_t)tdb->tdb_base)); 1920 } 1921 1922 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1923 1924 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1925 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1926 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1927 1928 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1929 1930 } 1931 1932 static int 1933 rtw_swring_setup(struct rtw_softc *sc) 1934 { 1935 int rc; 1936 struct rtw_rxdesc_blk *rdb; 1937 1938 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1939 1940 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1941 1942 rdb = &sc->sc_rxdesc_blk; 1943 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1944 sc->sc_dev.dv_xname)) != 0 && rdb->rdb_ndesc == 0) { 1945 printf("%s: could not allocate rx buffers\n", 1946 sc->sc_dev.dv_xname); 1947 return rc; 1948 } 1949 1950 rdb = &sc->sc_rxdesc_blk; 1951 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1952 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1953 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1954 rdb->rdb_next = 0; 1955 1956 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1957 return 0; 1958 } 1959 1960 static void 1961 rtw_txdesc_blk_init(struct rtw_txdesc_blk *tdb) 1962 { 1963 int i; 1964 1965 (void)memset(tdb->tdb_desc, 0, 1966 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 1967 for (i = 0; i < tdb->tdb_ndesc; i++) 1968 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 1969 } 1970 1971 static u_int 1972 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb) 1973 { 1974 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) / 1975 sizeof(struct rtw_txdesc); 1976 } 1977 1978 static void 1979 rtw_txring_fixup(struct rtw_softc *sc) 1980 { 1981 int pri; 1982 u_int next; 1983 struct rtw_txdesc_blk *tdb; 1984 struct rtw_regs *regs = &sc->sc_regs; 1985 1986 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1987 tdb = &sc->sc_txdesc_blk[pri]; 1988 next = rtw_txring_next(regs, tdb); 1989 if (tdb->tdb_next == next) 1990 continue; 1991 printf("%s: tx-ring %d expected next %u, read %u\n", __func__, 1992 pri, tdb->tdb_next, next); 1993 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1); 1994 } 1995 } 1996 1997 static void 1998 rtw_rxring_fixup(struct rtw_softc *sc) 1999 { 2000 u_int next; 2001 uint32_t rdsar; 2002 struct rtw_rxdesc_blk *rdb; 2003 2004 rdsar = le32toh(RTW_READ(&sc->sc_regs, RTW_RDSAR)); 2005 next = (rdsar - RTW_RING_BASE(sc, hd_rx)) / sizeof(struct rtw_rxdesc); 2006 2007 rdb = &sc->sc_rxdesc_blk; 2008 if (rdb->rdb_next != next) { 2009 printf("%s: rx-ring expected next %u, read %u\n", __func__, 2010 rdb->rdb_next, next); 2011 rdb->rdb_next = MIN(next, rdb->rdb_ndesc - 1); 2012 } 2013 } 2014 2015 static void 2016 rtw_txdescs_reset(struct rtw_softc *sc) 2017 { 2018 int pri; 2019 2020 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2021 rtw_collect_txring(sc, &sc->sc_txsoft_blk[pri], 2022 &sc->sc_txdesc_blk[pri], 1); 2023 } 2024 } 2025 2026 static void 2027 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 2028 { 2029 uint8_t cr = 0; 2030 int xmtr = 0, rcvr = 0; 2031 struct rtw_regs *regs = &sc->sc_regs; 2032 2033 if ((isr & RTW_INTR_TXFOVW) != 0) { 2034 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 2035 rcvr = xmtr = 1; 2036 cr |= RTW_CR_TE | RTW_CR_RE; 2037 } 2038 2039 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) { 2040 cr |= RTW_CR_RE; 2041 rcvr = 1; 2042 } 2043 2044 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: restarting xmit/recv, isr %" PRIx16 2045 "\n", sc->sc_dev.dv_xname, isr)); 2046 2047 #ifdef RTW_DEBUG 2048 rtw_dump_rings(sc); 2049 #endif /* RTW_DEBUG */ 2050 2051 rtw_io_enable(regs, cr, 0); 2052 2053 /* Collect rx'd packets. Refresh rx buffers. */ 2054 if (rcvr) 2055 rtw_intr_rx(sc, 0); 2056 /* Collect tx'd packets. XXX let's hope this stops the transmit 2057 * timeouts. 2058 */ 2059 if (xmtr) 2060 rtw_txdescs_reset(sc); 2061 2062 RTW_WRITE16(regs, RTW_IMR, 0); 2063 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 2064 2065 if (rtw_do_chip_reset) { 2066 rtw_chip_reset1(regs, sc->sc_dev.dv_xname); 2067 rtw_wep_setkeys(sc, sc->sc_ic.ic_nw_keys, 2068 sc->sc_ic.ic_def_txkey); 2069 } 2070 2071 rtw_rxdesc_init_all(&sc->sc_rxdesc_blk, &sc->sc_rxsoft[0], 1); 2072 2073 #ifdef RTW_DEBUG 2074 rtw_dump_rings(sc); 2075 #endif /* RTW_DEBUG */ 2076 2077 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2078 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 2079 if (rcvr) 2080 rtw_rxring_fixup(sc); 2081 rtw_io_enable(regs, cr, 1); 2082 if (xmtr) 2083 rtw_txring_fixup(sc); 2084 } 2085 2086 static inline void 2087 rtw_suspend_ticks(struct rtw_softc *sc) 2088 { 2089 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2090 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 2091 sc->sc_do_tick = 0; 2092 } 2093 2094 static inline void 2095 rtw_resume_ticks(struct rtw_softc *sc) 2096 { 2097 uint32_t tsftrl0, tsftrl1, next_tick; 2098 2099 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2100 2101 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2102 next_tick = tsftrl1 + 1000000; 2103 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 2104 2105 sc->sc_do_tick = 1; 2106 2107 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2108 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 2109 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 2110 } 2111 2112 static void 2113 rtw_intr_timeout(struct rtw_softc *sc) 2114 { 2115 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 2116 if (sc->sc_do_tick) 2117 rtw_resume_ticks(sc); 2118 return; 2119 } 2120 2121 int 2122 rtw_intr(void *arg) 2123 { 2124 int i; 2125 struct rtw_softc *sc = arg; 2126 struct rtw_regs *regs = &sc->sc_regs; 2127 uint16_t isr; 2128 struct ifnet *ifp = &sc->sc_if; 2129 2130 /* 2131 * If the interface isn't running, the interrupt couldn't 2132 * possibly have come from us. 2133 */ 2134 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 2135 (ifp->if_flags & IFF_RUNNING) == 0 || 2136 !device_is_active(&sc->sc_dev)) { 2137 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 2138 return (0); 2139 } 2140 2141 for (i = 0; i < 10; i++) { 2142 isr = RTW_READ16(regs, RTW_ISR); 2143 2144 RTW_WRITE16(regs, RTW_ISR, isr); 2145 RTW_WBR(regs, RTW_ISR, RTW_ISR); 2146 2147 if (sc->sc_intr_ack != NULL) 2148 (*sc->sc_intr_ack)(regs); 2149 2150 if (isr == 0) 2151 break; 2152 2153 #ifdef RTW_DEBUG 2154 #define PRINTINTR(flag) do { \ 2155 if ((isr & flag) != 0) { \ 2156 printf("%s" #flag, delim); \ 2157 delim = ","; \ 2158 } \ 2159 } while (0) 2160 2161 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 2162 const char *delim = "<"; 2163 2164 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 2165 2166 PRINTINTR(RTW_INTR_TXFOVW); 2167 PRINTINTR(RTW_INTR_TIMEOUT); 2168 PRINTINTR(RTW_INTR_BCNINT); 2169 PRINTINTR(RTW_INTR_ATIMINT); 2170 PRINTINTR(RTW_INTR_TBDER); 2171 PRINTINTR(RTW_INTR_TBDOK); 2172 PRINTINTR(RTW_INTR_THPDER); 2173 PRINTINTR(RTW_INTR_THPDOK); 2174 PRINTINTR(RTW_INTR_TNPDER); 2175 PRINTINTR(RTW_INTR_TNPDOK); 2176 PRINTINTR(RTW_INTR_RXFOVW); 2177 PRINTINTR(RTW_INTR_RDU); 2178 PRINTINTR(RTW_INTR_TLPDER); 2179 PRINTINTR(RTW_INTR_TLPDOK); 2180 PRINTINTR(RTW_INTR_RER); 2181 PRINTINTR(RTW_INTR_ROK); 2182 2183 printf(">\n"); 2184 } 2185 #undef PRINTINTR 2186 #endif /* RTW_DEBUG */ 2187 2188 if ((isr & RTW_INTR_RX) != 0) 2189 rtw_intr_rx(sc, isr & RTW_INTR_RX); 2190 if ((isr & RTW_INTR_TX) != 0) 2191 rtw_intr_tx(sc, isr & RTW_INTR_TX); 2192 if ((isr & RTW_INTR_BEACON) != 0) 2193 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 2194 if ((isr & RTW_INTR_ATIMINT) != 0) 2195 rtw_intr_atim(sc); 2196 if ((isr & RTW_INTR_IOERROR) != 0) 2197 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 2198 if ((isr & RTW_INTR_TIMEOUT) != 0) 2199 rtw_intr_timeout(sc); 2200 } 2201 2202 return 1; 2203 } 2204 2205 /* Must be called at splnet. */ 2206 static void 2207 rtw_stop(struct ifnet *ifp, int disable) 2208 { 2209 int pri; 2210 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2211 struct ieee80211com *ic = &sc->sc_ic; 2212 struct rtw_regs *regs = &sc->sc_regs; 2213 2214 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2215 return; 2216 2217 rtw_suspend_ticks(sc); 2218 2219 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2220 2221 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 2222 /* Disable interrupts. */ 2223 RTW_WRITE16(regs, RTW_IMR, 0); 2224 2225 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2226 2227 /* Stop the transmit and receive processes. First stop DMA, 2228 * then disable receiver and transmitter. 2229 */ 2230 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2231 2232 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2233 2234 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 2235 } 2236 2237 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2238 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2239 &sc->sc_txsoft_blk[pri]); 2240 } 2241 2242 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2243 2244 if (disable) 2245 rtw_disable(sc); 2246 2247 /* Mark the interface as not running. Cancel the watchdog timer. */ 2248 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2249 ifp->if_timer = 0; 2250 2251 return; 2252 } 2253 2254 const char * 2255 rtw_pwrstate_string(enum rtw_pwrstate power) 2256 { 2257 switch (power) { 2258 case RTW_ON: 2259 return "on"; 2260 case RTW_SLEEP: 2261 return "sleep"; 2262 case RTW_OFF: 2263 return "off"; 2264 default: 2265 return "unknown"; 2266 } 2267 } 2268 2269 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2270 * reference driver, plus a magic Maxim "ON" value that comes from 2271 * the Realtek document "Windows PG for Rtl8180." 2272 */ 2273 static void 2274 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2275 int before_rf, int digphy) 2276 { 2277 uint32_t anaparm; 2278 2279 anaparm = RTW_READ(regs, RTW_ANAPARM); 2280 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2281 2282 switch (power) { 2283 case RTW_OFF: 2284 if (before_rf) 2285 return; 2286 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2287 anaparm |= RTW_ANAPARM_TXDACOFF; 2288 break; 2289 case RTW_SLEEP: 2290 if (!before_rf) 2291 return; 2292 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2293 anaparm |= RTW_ANAPARM_TXDACOFF; 2294 break; 2295 case RTW_ON: 2296 if (!before_rf) 2297 return; 2298 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2299 break; 2300 } 2301 RTW_DPRINTF(RTW_DEBUG_PWR, 2302 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2303 __func__, rtw_pwrstate_string(power), 2304 (before_rf) ? "before" : "after", anaparm)); 2305 2306 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2307 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2308 } 2309 2310 /* XXX I am using the RFMD settings gleaned from the reference 2311 * driver. They agree 2312 */ 2313 static void 2314 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2315 int before_rf, int digphy) 2316 { 2317 uint32_t anaparm; 2318 2319 anaparm = RTW_READ(regs, RTW_ANAPARM); 2320 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2321 2322 switch (power) { 2323 case RTW_OFF: 2324 if (before_rf) 2325 return; 2326 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2327 anaparm |= RTW_ANAPARM_TXDACOFF; 2328 break; 2329 case RTW_SLEEP: 2330 if (!before_rf) 2331 return; 2332 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2333 anaparm |= RTW_ANAPARM_TXDACOFF; 2334 break; 2335 case RTW_ON: 2336 if (!before_rf) 2337 return; 2338 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2339 break; 2340 } 2341 RTW_DPRINTF(RTW_DEBUG_PWR, 2342 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2343 __func__, rtw_pwrstate_string(power), 2344 (before_rf) ? "before" : "after", anaparm)); 2345 2346 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2347 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2348 } 2349 2350 static void 2351 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2352 int before_rf, int digphy) 2353 { 2354 uint32_t anaparm; 2355 2356 anaparm = RTW_READ(regs, RTW_ANAPARM); 2357 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2358 2359 switch (power) { 2360 case RTW_OFF: 2361 if (before_rf) 2362 return; 2363 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2364 anaparm |= RTW_ANAPARM_TXDACOFF; 2365 break; 2366 case RTW_SLEEP: 2367 if (!before_rf) 2368 return; 2369 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2370 anaparm |= RTW_ANAPARM_TXDACOFF; 2371 break; 2372 case RTW_ON: 2373 if (!before_rf) 2374 return; 2375 if (digphy) { 2376 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2377 /* XXX guess */ 2378 anaparm |= RTW_ANAPARM_TXDACOFF; 2379 } else 2380 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2381 break; 2382 } 2383 RTW_DPRINTF(RTW_DEBUG_PWR, 2384 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2385 __func__, rtw_pwrstate_string(power), 2386 (before_rf) ? "before" : "after", anaparm)); 2387 2388 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2389 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2390 } 2391 2392 static void 2393 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2394 int digphy) 2395 { 2396 struct rtw_regs *regs = &sc->sc_regs; 2397 2398 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2399 2400 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2401 2402 rtw_set_access(regs, RTW_ACCESS_NONE); 2403 2404 return; 2405 } 2406 2407 static int 2408 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2409 { 2410 int rc; 2411 2412 RTW_DPRINTF(RTW_DEBUG_PWR, 2413 ("%s: %s->%s\n", __func__, 2414 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2415 2416 if (sc->sc_pwrstate == power) 2417 return 0; 2418 2419 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2420 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2421 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2422 2423 switch (power) { 2424 case RTW_ON: 2425 /* TBD set LEDs */ 2426 break; 2427 case RTW_SLEEP: 2428 /* TBD */ 2429 break; 2430 case RTW_OFF: 2431 /* TBD */ 2432 break; 2433 } 2434 if (rc == 0) 2435 sc->sc_pwrstate = power; 2436 else 2437 sc->sc_pwrstate = RTW_OFF; 2438 return rc; 2439 } 2440 2441 static int 2442 rtw_tune(struct rtw_softc *sc) 2443 { 2444 struct ieee80211com *ic = &sc->sc_ic; 2445 u_int chan; 2446 int rc; 2447 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2448 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2449 2450 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2451 if (chan == IEEE80211_CHAN_ANY) 2452 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 2453 2454 if (chan == sc->sc_cur_chan) { 2455 RTW_DPRINTF(RTW_DEBUG_TUNE, 2456 ("%s: already tuned chan #%d\n", __func__, chan)); 2457 return 0; 2458 } 2459 2460 rtw_suspend_ticks(sc); 2461 2462 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 2463 2464 /* TBD wait for Tx to complete */ 2465 2466 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2467 2468 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2469 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr, 2470 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) { 2471 /* XXX condition on powersaving */ 2472 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2473 } 2474 2475 sc->sc_cur_chan = chan; 2476 2477 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 2478 2479 rtw_resume_ticks(sc); 2480 2481 return rc; 2482 } 2483 2484 void 2485 rtw_disable(struct rtw_softc *sc) 2486 { 2487 int rc; 2488 2489 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2490 return; 2491 2492 /* turn off PHY */ 2493 if ((sc->sc_flags & RTW_F_INVALID) == 0 && 2494 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2495 printf("%s: failed to turn off PHY (%d)\n", 2496 sc->sc_dev.dv_xname, rc); 2497 } 2498 2499 if (sc->sc_disable != NULL) 2500 (*sc->sc_disable)(sc); 2501 2502 sc->sc_flags &= ~RTW_F_ENABLED; 2503 } 2504 2505 int 2506 rtw_enable(struct rtw_softc *sc) 2507 { 2508 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2509 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2510 printf("%s: device enable failed\n", 2511 sc->sc_dev.dv_xname); 2512 return (EIO); 2513 } 2514 sc->sc_flags |= RTW_F_ENABLED; 2515 /* Power may have been removed, and WEP keys thus 2516 * reset. 2517 */ 2518 sc->sc_flags &= ~RTW_F_DK_VALID; 2519 } 2520 return (0); 2521 } 2522 2523 static void 2524 rtw_transmit_config(struct rtw_regs *regs) 2525 { 2526 uint32_t tcr; 2527 2528 tcr = RTW_READ(regs, RTW_TCR); 2529 2530 tcr |= RTW_TCR_CWMIN; 2531 tcr &= ~RTW_TCR_MXDMA_MASK; 2532 tcr |= RTW_TCR_MXDMA_256; 2533 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2534 tcr &= ~RTW_TCR_LBK_MASK; 2535 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2536 2537 /* set short/long retry limits */ 2538 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2539 tcr |= SHIFTIN(4, RTW_TCR_SRL_MASK) | SHIFTIN(4, RTW_TCR_LRL_MASK); 2540 2541 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2542 2543 RTW_WRITE(regs, RTW_TCR, tcr); 2544 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2545 } 2546 2547 static inline void 2548 rtw_enable_interrupts(struct rtw_softc *sc) 2549 { 2550 struct rtw_regs *regs = &sc->sc_regs; 2551 2552 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2553 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2554 2555 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2556 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2557 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2558 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2559 2560 /* XXX necessary? */ 2561 if (sc->sc_intr_ack != NULL) 2562 (*sc->sc_intr_ack)(regs); 2563 } 2564 2565 static void 2566 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2567 { 2568 uint8_t msr; 2569 2570 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2571 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2572 2573 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2574 2575 switch (opmode) { 2576 case IEEE80211_M_AHDEMO: 2577 case IEEE80211_M_IBSS: 2578 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2579 break; 2580 case IEEE80211_M_HOSTAP: 2581 msr |= RTW_MSR_NETYPE_AP_OK; 2582 break; 2583 case IEEE80211_M_MONITOR: 2584 /* XXX */ 2585 msr |= RTW_MSR_NETYPE_NOLINK; 2586 break; 2587 case IEEE80211_M_STA: 2588 msr |= RTW_MSR_NETYPE_INFRA_OK; 2589 break; 2590 } 2591 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2592 2593 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2594 } 2595 2596 #define rtw_calchash(addr) \ 2597 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2598 2599 static void 2600 rtw_pktfilt_load(struct rtw_softc *sc) 2601 { 2602 struct rtw_regs *regs = &sc->sc_regs; 2603 struct ieee80211com *ic = &sc->sc_ic; 2604 struct ethercom *ec = &sc->sc_ec; 2605 struct ifnet *ifp = &sc->sc_if; 2606 int hash; 2607 uint32_t hashes[2] = { 0, 0 }; 2608 struct ether_multi *enm; 2609 struct ether_multistep step; 2610 2611 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2612 2613 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2614 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2615 2616 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2617 /* MAC auto-reset PHY (huh?) */ 2618 sc->sc_rcr |= RTW_RCR_ENMARP; 2619 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2620 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2621 2622 switch (ic->ic_opmode) { 2623 case IEEE80211_M_MONITOR: 2624 sc->sc_rcr |= RTW_RCR_MONITOR; 2625 break; 2626 case IEEE80211_M_AHDEMO: 2627 case IEEE80211_M_IBSS: 2628 /* receive broadcasts in our BSS */ 2629 sc->sc_rcr |= RTW_RCR_ADD3; 2630 break; 2631 default: 2632 break; 2633 } 2634 2635 ifp->if_flags &= ~IFF_ALLMULTI; 2636 2637 /* XXX accept all broadcast if scanning */ 2638 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2639 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2640 2641 if (ifp->if_flags & IFF_PROMISC) { 2642 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2643 allmulti: 2644 ifp->if_flags |= IFF_ALLMULTI; 2645 goto setit; 2646 } 2647 2648 /* 2649 * Program the 64-bit multicast hash filter. 2650 */ 2651 ETHER_FIRST_MULTI(step, ec, enm); 2652 while (enm != NULL) { 2653 /* XXX */ 2654 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2655 ETHER_ADDR_LEN) != 0) 2656 goto allmulti; 2657 2658 hash = rtw_calchash(enm->enm_addrlo); 2659 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2660 sc->sc_rcr |= RTW_RCR_AM; 2661 ETHER_NEXT_MULTI(step, enm); 2662 } 2663 2664 /* all bits set => hash is useless */ 2665 if (~(hashes[0] & hashes[1]) == 0) 2666 goto allmulti; 2667 2668 setit: 2669 if (ifp->if_flags & IFF_ALLMULTI) { 2670 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2671 hashes[0] = hashes[1] = 0xffffffff; 2672 } 2673 2674 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2675 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2676 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2677 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2678 2679 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2680 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2681 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2682 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2683 2684 return; 2685 } 2686 2687 static struct mbuf * 2688 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2689 { 2690 struct ieee80211com *ic = &sc->sc_ic; 2691 struct mbuf *m; 2692 struct ieee80211_beacon_offsets boff; 2693 2694 if ((m = ieee80211_beacon_alloc(ic, ni, &boff)) != NULL) { 2695 RTW_DPRINTF(RTW_DEBUG_BEACON, 2696 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2697 } 2698 return m; 2699 } 2700 2701 /* Must be called at splnet. */ 2702 static int 2703 rtw_init(struct ifnet *ifp) 2704 { 2705 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2706 struct ieee80211com *ic = &sc->sc_ic; 2707 struct rtw_regs *regs = &sc->sc_regs; 2708 int rc = 0; 2709 2710 if ((rc = rtw_enable(sc)) != 0) 2711 goto out; 2712 2713 /* Cancel pending I/O and reset. */ 2714 rtw_stop(ifp, 0); 2715 2716 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2717 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 2718 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 2719 2720 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2721 goto out; 2722 2723 if ((rc = rtw_swring_setup(sc)) != 0) 2724 goto out; 2725 2726 rtw_transmit_config(regs); 2727 2728 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2729 2730 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2731 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2732 2733 /* long PLCP header, 1Mb/2Mb basic rate */ 2734 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2735 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2736 2737 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2738 rtw_set_access(regs, RTW_ACCESS_NONE); 2739 2740 /* XXX from reference sources */ 2741 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2742 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2743 2744 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2745 2746 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2747 /* from Linux driver */ 2748 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2749 2750 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2751 2752 rtw_enable_interrupts(sc); 2753 2754 rtw_pktfilt_load(sc); 2755 2756 rtw_hwring_setup(sc); 2757 2758 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2759 2760 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2761 2762 ifp->if_flags |= IFF_RUNNING; 2763 ic->ic_state = IEEE80211_S_INIT; 2764 2765 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2766 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2767 2768 rtw_resume_ticks(sc); 2769 2770 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2771 2772 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2773 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2774 else 2775 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2776 2777 out: 2778 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2779 return rc; 2780 } 2781 2782 static inline void 2783 rtw_led_init(struct rtw_regs *regs) 2784 { 2785 uint8_t cfg0, cfg1; 2786 2787 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2788 2789 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2790 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2791 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2792 2793 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2794 RTW_DPRINTF(RTW_DEBUG_LED, 2795 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2796 2797 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2798 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2799 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2800 2801 rtw_set_access(regs, RTW_ACCESS_NONE); 2802 } 2803 2804 /* 2805 * IEEE80211_S_INIT: LED1 off 2806 * 2807 * IEEE80211_S_AUTH, 2808 * IEEE80211_S_ASSOC, 2809 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2810 * 2811 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2812 */ 2813 static void 2814 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2815 { 2816 struct rtw_led_state *ls; 2817 2818 ls = &sc->sc_led_state; 2819 2820 switch (nstate) { 2821 case IEEE80211_S_INIT: 2822 rtw_led_init(&sc->sc_regs); 2823 callout_stop(&ls->ls_slow_ch); 2824 callout_stop(&ls->ls_fast_ch); 2825 ls->ls_slowblink = 0; 2826 ls->ls_actblink = 0; 2827 ls->ls_default = 0; 2828 break; 2829 case IEEE80211_S_SCAN: 2830 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2831 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2832 /*FALLTHROUGH*/ 2833 case IEEE80211_S_AUTH: 2834 case IEEE80211_S_ASSOC: 2835 ls->ls_default = RTW_LED1; 2836 ls->ls_actblink = RTW_LED1; 2837 ls->ls_slowblink = RTW_LED1; 2838 break; 2839 case IEEE80211_S_RUN: 2840 ls->ls_slowblink = 0; 2841 break; 2842 } 2843 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2844 } 2845 2846 static void 2847 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2848 { 2849 uint8_t led_condition; 2850 bus_size_t ofs; 2851 uint8_t mask, newval, val; 2852 2853 led_condition = ls->ls_default; 2854 2855 if (ls->ls_state & RTW_LED_S_SLOW) 2856 led_condition ^= ls->ls_slowblink; 2857 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2858 led_condition ^= ls->ls_actblink; 2859 2860 RTW_DPRINTF(RTW_DEBUG_LED, 2861 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2862 2863 switch (hwverid) { 2864 default: 2865 case 'F': 2866 ofs = RTW_PSR; 2867 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2868 if (led_condition & RTW_LED0) 2869 newval &= ~RTW_PSR_LEDGPO0; 2870 if (led_condition & RTW_LED1) 2871 newval &= ~RTW_PSR_LEDGPO1; 2872 break; 2873 case 'D': 2874 ofs = RTW_9346CR; 2875 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2876 newval = RTW_9346CR_EEM_PROGRAM; 2877 if (led_condition & RTW_LED0) 2878 newval |= RTW_9346CR_EEDI; 2879 if (led_condition & RTW_LED1) 2880 newval |= RTW_9346CR_EECS; 2881 break; 2882 } 2883 val = RTW_READ8(regs, ofs); 2884 RTW_DPRINTF(RTW_DEBUG_LED, 2885 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2886 (uintptr_t)ofs)); 2887 val &= ~mask; 2888 val |= newval; 2889 RTW_WRITE8(regs, ofs, val); 2890 RTW_DPRINTF(RTW_DEBUG_LED, 2891 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2892 (uintptr_t)ofs)); 2893 RTW_SYNC(regs, ofs, ofs); 2894 } 2895 2896 static void 2897 rtw_led_fastblink(void *arg) 2898 { 2899 int ostate, s; 2900 struct rtw_softc *sc = (struct rtw_softc *)arg; 2901 struct rtw_led_state *ls = &sc->sc_led_state; 2902 2903 s = splnet(); 2904 ostate = ls->ls_state; 2905 ls->ls_state ^= ls->ls_event; 2906 2907 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2908 ls->ls_state &= ~RTW_LED_S_TX; 2909 2910 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2911 ls->ls_state &= ~RTW_LED_S_RX; 2912 2913 ls->ls_event = 0; 2914 2915 if (ostate != ls->ls_state) 2916 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2917 splx(s); 2918 2919 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2920 } 2921 2922 static void 2923 rtw_led_slowblink(void *arg) 2924 { 2925 int s; 2926 struct rtw_softc *sc = (struct rtw_softc *)arg; 2927 struct rtw_led_state *ls = &sc->sc_led_state; 2928 2929 s = splnet(); 2930 ls->ls_state ^= RTW_LED_S_SLOW; 2931 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2932 splx(s); 2933 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2934 } 2935 2936 static inline void 2937 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2938 { 2939 callout_init(&ls->ls_fast_ch); 2940 callout_init(&ls->ls_slow_ch); 2941 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2942 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2943 } 2944 2945 static int 2946 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2947 { 2948 int rc = 0, s; 2949 struct rtw_softc *sc = ifp->if_softc; 2950 struct ifreq *ifr = (struct ifreq *)data; 2951 2952 s = splnet(); 2953 switch (cmd) { 2954 case SIOCSIFFLAGS: 2955 if ((ifp->if_flags & IFF_UP) != 0) { 2956 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2957 rtw_pktfilt_load(sc); 2958 } else 2959 rc = rtw_init(ifp); 2960 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2961 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2962 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2963 rtw_stop(ifp, 1); 2964 } 2965 break; 2966 case SIOCADDMULTI: 2967 case SIOCDELMULTI: 2968 if (cmd == SIOCADDMULTI) 2969 rc = ether_addmulti(ifr, &sc->sc_ec); 2970 else 2971 rc = ether_delmulti(ifr, &sc->sc_ec); 2972 if (rc != ENETRESET) 2973 break; 2974 if (ifp->if_flags & IFF_RUNNING) 2975 rtw_pktfilt_load(sc); 2976 rc = 0; 2977 break; 2978 default: 2979 if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 2980 break; 2981 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2982 rc = rtw_init(ifp); 2983 else 2984 rc = 0; 2985 break; 2986 } 2987 splx(s); 2988 return rc; 2989 } 2990 2991 /* Select a transmit ring with at least one h/w and s/w descriptor free. 2992 * Return 0 on success, -1 on failure. 2993 */ 2994 static inline int 2995 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 2996 struct rtw_txdesc_blk **tdbp, int pri) 2997 { 2998 struct rtw_txsoft_blk *tsb; 2999 struct rtw_txdesc_blk *tdb; 3000 3001 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 3002 3003 tsb = &sc->sc_txsoft_blk[pri]; 3004 tdb = &sc->sc_txdesc_blk[pri]; 3005 3006 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 3007 if (tsb->tsb_tx_timer == 0) 3008 tsb->tsb_tx_timer = 5; 3009 *tsbp = NULL; 3010 *tdbp = NULL; 3011 return -1; 3012 } 3013 *tsbp = tsb; 3014 *tdbp = tdb; 3015 return 0; 3016 } 3017 3018 static inline struct mbuf * 3019 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 3020 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 3021 struct ieee80211_node **nip, short *if_flagsp) 3022 { 3023 struct mbuf *m; 3024 3025 if (IF_IS_EMPTY(ifq)) 3026 return NULL; 3027 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3028 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3029 __func__, pri)); 3030 *if_flagsp |= IFF_OACTIVE; 3031 sc->sc_if.if_timer = 1; 3032 return NULL; 3033 } 3034 IF_DEQUEUE(ifq, m); 3035 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3036 m->m_pkthdr.rcvif = NULL; 3037 KASSERT(*nip != NULL); 3038 return m; 3039 } 3040 3041 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 3042 * at the driver's selection of transmit control block for the packet. 3043 */ 3044 static inline int 3045 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 3046 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 3047 struct ieee80211_node **nip) 3048 { 3049 int pri; 3050 struct ether_header *eh; 3051 struct mbuf *m0; 3052 struct rtw_softc *sc; 3053 short *if_flagsp; 3054 3055 sc = (struct rtw_softc *)ifp->if_softc; 3056 3057 DPRINTF(sc, RTW_DEBUG_XMIT, 3058 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3059 3060 if_flagsp = &ifp->if_flags; 3061 3062 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 3063 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 3064 tdbp, nip, if_flagsp)) != NULL) { 3065 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 3066 __func__)); 3067 return 0; 3068 } 3069 3070 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 3071 tdbp, nip, if_flagsp)) != NULL) { 3072 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 3073 __func__)); 3074 return 0; 3075 } 3076 3077 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 3078 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 3079 return 0; 3080 } 3081 3082 *mp = NULL; 3083 3084 IFQ_POLL(&ifp->if_snd, m0); 3085 if (m0 == NULL) { 3086 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3087 __func__)); 3088 return 0; 3089 } 3090 3091 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 3092 3093 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3094 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3095 __func__, pri)); 3096 *if_flagsp |= IFF_OACTIVE; 3097 sc->sc_if.if_timer = 1; 3098 return 0; 3099 } 3100 3101 IFQ_DEQUEUE(&ifp->if_snd, m0); 3102 if (m0 == NULL) { 3103 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3104 __func__)); 3105 return 0; 3106 } 3107 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 3108 ifp->if_opackets++; 3109 #if NBPFILTER > 0 3110 if (ifp->if_bpf) 3111 bpf_mtap(ifp->if_bpf, m0); 3112 #endif 3113 eh = mtod(m0, struct ether_header *); 3114 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 3115 if (*nip == NULL) { 3116 /* NB: ieee80211_find_txnode does stat+msg */ 3117 m_freem(m0); 3118 return -1; 3119 } 3120 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 3121 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 3122 ifp->if_oerrors++; 3123 return -1; 3124 } 3125 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3126 *mp = m0; 3127 return 0; 3128 } 3129 3130 static int 3131 rtw_seg_too_short(bus_dmamap_t dmamap) 3132 { 3133 int i; 3134 for (i = 0; i < dmamap->dm_nsegs; i++) { 3135 if (dmamap->dm_segs[i].ds_len < 4) { 3136 printf("%s: segment too short\n", __func__); 3137 return 1; 3138 } 3139 } 3140 return 0; 3141 } 3142 3143 /* TBD factor with atw_start */ 3144 static struct mbuf * 3145 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 3146 u_int ndescfree, short *ifflagsp, const char *dvname) 3147 { 3148 int first, rc; 3149 struct mbuf *m, *m0; 3150 3151 m0 = chain; 3152 3153 /* 3154 * Load the DMA map. Copy and try (once) again if the packet 3155 * didn't fit in the alloted number of segments. 3156 */ 3157 for (first = 1; 3158 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 3159 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 3160 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 3161 first = 0) { 3162 if (rc == 0) 3163 bus_dmamap_unload(dmat, dmam); 3164 MGETHDR(m, M_DONTWAIT, MT_DATA); 3165 if (m == NULL) { 3166 printf("%s: unable to allocate Tx mbuf\n", 3167 dvname); 3168 break; 3169 } 3170 if (m0->m_pkthdr.len > MHLEN) { 3171 MCLGET(m, M_DONTWAIT); 3172 if ((m->m_flags & M_EXT) == 0) { 3173 printf("%s: cannot allocate Tx cluster\n", 3174 dvname); 3175 m_freem(m); 3176 break; 3177 } 3178 } 3179 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3180 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3181 m_freem(m0); 3182 m0 = m; 3183 m = NULL; 3184 } 3185 if (rc != 0) { 3186 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 3187 m_freem(m0); 3188 return NULL; 3189 } else if (rtw_seg_too_short(dmam)) { 3190 printf("%s: cannot load Tx buffer, segment too short\n", 3191 dvname); 3192 bus_dmamap_unload(dmat, dmam); 3193 m_freem(m0); 3194 return NULL; 3195 } else if (dmam->dm_nsegs > ndescfree) { 3196 printf("%s: too many tx segments\n", dvname); 3197 bus_dmamap_unload(dmat, dmam); 3198 m_freem(m0); 3199 return NULL; 3200 } 3201 return m0; 3202 } 3203 3204 #ifdef RTW_DEBUG 3205 static void 3206 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3207 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3208 { 3209 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3210 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] next %#08x " 3211 "buf %#08x ctl0 %#08x ctl1 %#08x len %#08x\n", 3212 sc->sc_dev.dv_xname, ts, action, desc, 3213 le32toh(td->td_buf), le32toh(td->td_next), 3214 le32toh(td->td_ctl0), le32toh(td->td_ctl1), 3215 le32toh(td->td_len))); 3216 } 3217 #endif /* RTW_DEBUG */ 3218 3219 static void 3220 rtw_start(struct ifnet *ifp) 3221 { 3222 uint8_t tppoll; 3223 int desc, i, lastdesc, npkt, rate; 3224 uint32_t proto_ctl0, ctl0, ctl1; 3225 bus_dmamap_t dmamap; 3226 struct ieee80211com *ic; 3227 struct ieee80211_duration *d0; 3228 struct ieee80211_frame_min *wh; 3229 struct ieee80211_node *ni; 3230 struct mbuf *m0; 3231 struct rtw_softc *sc; 3232 struct rtw_txsoft_blk *tsb; 3233 struct rtw_txdesc_blk *tdb; 3234 struct rtw_txsoft *ts; 3235 struct rtw_txdesc *td; 3236 struct ieee80211_key *k; 3237 3238 sc = (struct rtw_softc *)ifp->if_softc; 3239 ic = &sc->sc_ic; 3240 3241 DPRINTF(sc, RTW_DEBUG_XMIT, 3242 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3243 3244 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3245 goto out; 3246 3247 /* XXX do real rate control */ 3248 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3249 3250 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3251 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3252 3253 for (;;) { 3254 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3255 continue; 3256 if (m0 == NULL) 3257 break; 3258 3259 wh = mtod(m0, struct ieee80211_frame_min *); 3260 3261 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3262 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3263 m_freem(m0); 3264 break; 3265 } else 3266 k = NULL; 3267 3268 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3269 3270 dmamap = ts->ts_dmamap; 3271 3272 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3273 tdb->tdb_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 3274 3275 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3276 DPRINTF(sc, RTW_DEBUG_XMIT, 3277 ("%s: fail dmamap load\n", __func__)); 3278 goto post_dequeue_err; 3279 } 3280 3281 /* Note well: rtw_dmamap_load_txbuf may have created 3282 * a new chain, so we must find the header once 3283 * more. 3284 */ 3285 wh = mtod(m0, struct ieee80211_frame_min *); 3286 3287 /* XXX do real rate control */ 3288 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3289 IEEE80211_FC0_TYPE_MGT) 3290 rate = 2; 3291 else 3292 rate = MAX(2, ieee80211_get_rate(ic)); 3293 3294 #ifdef RTW_DEBUG 3295 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3296 (IFF_DEBUG|IFF_LINK2)) { 3297 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3298 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3299 : sizeof(wh), 3300 rate, 0); 3301 } 3302 #endif /* RTW_DEBUG */ 3303 ctl0 = proto_ctl0 | 3304 SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3305 3306 switch (rate) { 3307 default: 3308 case 2: 3309 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3310 break; 3311 case 4: 3312 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3313 break; 3314 case 11: 3315 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3316 break; 3317 case 22: 3318 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3319 break; 3320 } 3321 /* XXX >= ? Compare after fragmentation? */ 3322 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3323 ctl0 |= RTW_TXCTL0_RTSEN; 3324 3325 /* XXX Sometimes writes a bogus keyid; h/w doesn't 3326 * seem to care, since we don't activate h/w Tx 3327 * encryption. 3328 */ 3329 if (k != NULL) { 3330 ctl0 |= SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3331 RTW_TXCTL0_KEYID_MASK; 3332 } 3333 3334 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3335 IEEE80211_FC0_TYPE_MGT) { 3336 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3337 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3338 IEEE80211_FC0_SUBTYPE_BEACON) 3339 ctl0 |= RTW_TXCTL0_BEACON; 3340 } 3341 3342 if (ieee80211_compute_duration(wh, k, m0->m_pkthdr.len, 3343 ic->ic_flags, ic->ic_fragthreshold, 3344 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3345 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3346 (IFF_DEBUG|IFF_LINK2)) == -1) { 3347 DPRINTF(sc, RTW_DEBUG_XMIT, 3348 ("%s: fail compute duration\n", __func__)); 3349 goto post_load_err; 3350 } 3351 3352 d0 = &ts->ts_d0; 3353 3354 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3355 3356 ctl1 = SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3357 SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3358 3359 if (d0->d_residue) 3360 ctl1 |= RTW_TXCTL1_LENGEXT; 3361 3362 /* TBD fragmentation */ 3363 3364 ts->ts_first = tdb->tdb_next; 3365 3366 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3367 BUS_DMASYNC_PREWRITE); 3368 3369 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3370 3371 #if NBPFILTER > 0 3372 if (ic->ic_rawbpf != NULL) 3373 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3374 3375 if (sc->sc_radiobpf != NULL) { 3376 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3377 3378 rt->rt_flags = 0; 3379 rt->rt_rate = rate; 3380 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq); 3381 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags); 3382 3383 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rt, 3384 sizeof(sc->sc_txtapu), m0); 3385 } 3386 #endif /* NPBFILTER > 0 */ 3387 3388 for (i = 0, lastdesc = desc = ts->ts_first; 3389 i < dmamap->dm_nsegs; 3390 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3391 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3392 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3393 ("%s: seg too long\n", __func__)); 3394 goto post_load_err; 3395 } 3396 td = &tdb->tdb_desc[desc]; 3397 td->td_ctl0 = htole32(ctl0); 3398 if (i != 0) 3399 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3400 td->td_ctl1 = htole32(ctl1); 3401 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3402 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3403 lastdesc = desc; 3404 #ifdef RTW_DEBUG 3405 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3406 #endif /* RTW_DEBUG */ 3407 } 3408 3409 KASSERT(desc < tdb->tdb_ndesc); 3410 3411 ts->ts_ni = ni; 3412 KASSERT(ni != NULL); 3413 ts->ts_mbuf = m0; 3414 ts->ts_last = lastdesc; 3415 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3416 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3417 htole32(RTW_TXCTL0_FS); 3418 3419 #ifdef RTW_DEBUG 3420 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3421 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3422 #endif /* RTW_DEBUG */ 3423 3424 tdb->tdb_nfree -= dmamap->dm_nsegs; 3425 tdb->tdb_next = desc; 3426 3427 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3428 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3429 3430 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3431 htole32(RTW_TXCTL0_OWN); 3432 3433 #ifdef RTW_DEBUG 3434 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3435 #endif /* RTW_DEBUG */ 3436 3437 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3438 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3439 3440 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3441 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3442 3443 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) 3444 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3445 tsb->tsb_tx_timer = 5; 3446 ifp->if_timer = 1; 3447 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3448 tppoll &= ~RTW_TPPOLL_SALL; 3449 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL; 3450 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3451 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3452 } 3453 out: 3454 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3455 return; 3456 post_load_err: 3457 bus_dmamap_unload(sc->sc_dmat, dmamap); 3458 m_freem(m0); 3459 post_dequeue_err: 3460 ieee80211_free_node(ni); 3461 return; 3462 } 3463 3464 static void 3465 rtw_idle(struct rtw_regs *regs) 3466 { 3467 int active; 3468 3469 /* request stop DMA; wait for packets to stop transmitting. */ 3470 3471 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3472 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL); 3473 3474 for (active = 0; active < 300 && 3475 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0; active++) 3476 DELAY(10); 3477 printf("%s: transmit DMA idle in %dus\n", __func__, active * 10); 3478 } 3479 3480 static void 3481 rtw_watchdog(struct ifnet *ifp) 3482 { 3483 int pri, tx_timeouts = 0; 3484 struct rtw_softc *sc; 3485 struct rtw_txsoft_blk *tsb; 3486 3487 sc = ifp->if_softc; 3488 3489 ifp->if_timer = 0; 3490 3491 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 3492 return; 3493 3494 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3495 tsb = &sc->sc_txsoft_blk[pri]; 3496 3497 if (tsb->tsb_tx_timer == 0) 3498 continue; 3499 else if (--tsb->tsb_tx_timer == 0) { 3500 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3501 continue; 3502 printf("%s: transmit timeout, priority %d\n", 3503 ifp->if_xname, pri); 3504 ifp->if_oerrors++; 3505 tx_timeouts++; 3506 } else 3507 ifp->if_timer = 1; 3508 } 3509 3510 if (tx_timeouts > 0) { 3511 /* Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr, 3512 * reset s/w tx-ring pointers, and start transmission. 3513 * 3514 * TBD Stop/restart just the broken rings? 3515 */ 3516 rtw_idle(&sc->sc_regs); 3517 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 0); 3518 rtw_txdescs_reset(sc); 3519 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 1); 3520 rtw_txring_fixup(sc); 3521 rtw_start(ifp); 3522 } 3523 ieee80211_watchdog(&sc->sc_ic); 3524 return; 3525 } 3526 3527 static void 3528 rtw_next_scan(void *arg) 3529 { 3530 struct ieee80211com *ic = arg; 3531 int s; 3532 3533 /* don't call rtw_start w/o network interrupts blocked */ 3534 s = splnet(); 3535 if (ic->ic_state == IEEE80211_S_SCAN) 3536 ieee80211_next_scan(ic); 3537 splx(s); 3538 } 3539 3540 static void 3541 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3542 { 3543 uint16_t bcnitv, bintritv, intval; 3544 int i; 3545 struct rtw_regs *regs = &sc->sc_regs; 3546 3547 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3548 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3549 3550 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3551 3552 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3553 3554 intval = MIN(intval0, SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); 3555 3556 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3557 bcnitv |= SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); 3558 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3559 /* interrupt host 1ms before the TBTT */ 3560 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV; 3561 bintritv |= SHIFTIN(1000, RTW_BINTRITV_BINTRITV); 3562 RTW_WRITE16(regs, RTW_BINTRITV, bintritv); 3563 /* magic from Linux */ 3564 RTW_WRITE16(regs, RTW_ATIMWND, SHIFTIN(1, RTW_ATIMWND_ATIMWND)); 3565 RTW_WRITE16(regs, RTW_ATIMTRITV, SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); 3566 rtw_set_access(regs, RTW_ACCESS_NONE); 3567 3568 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 3569 } 3570 3571 /* Synchronize the hardware state with the software state. */ 3572 static int 3573 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3574 { 3575 struct ifnet *ifp = ic->ic_ifp; 3576 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3577 enum ieee80211_state ostate; 3578 int error; 3579 3580 ostate = ic->ic_state; 3581 3582 rtw_led_newstate(sc, nstate); 3583 3584 if (nstate == IEEE80211_S_INIT) { 3585 callout_stop(&sc->sc_scan_ch); 3586 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3587 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3588 } 3589 3590 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3591 rtw_pwrstate(sc, RTW_ON); 3592 3593 if ((error = rtw_tune(sc)) != 0) 3594 return error; 3595 3596 switch (nstate) { 3597 case IEEE80211_S_INIT: 3598 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3599 break; 3600 case IEEE80211_S_SCAN: 3601 if (ostate != IEEE80211_S_SCAN) { 3602 (void)memset(ic->ic_bss->ni_bssid, 0, 3603 IEEE80211_ADDR_LEN); 3604 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3605 } 3606 3607 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3608 rtw_next_scan, ic); 3609 3610 break; 3611 case IEEE80211_S_RUN: 3612 switch (ic->ic_opmode) { 3613 case IEEE80211_M_HOSTAP: 3614 case IEEE80211_M_IBSS: 3615 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3616 /*FALLTHROUGH*/ 3617 case IEEE80211_M_AHDEMO: 3618 case IEEE80211_M_STA: 3619 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3620 ic->ic_bss->ni_intval); 3621 break; 3622 case IEEE80211_M_MONITOR: 3623 break; 3624 } 3625 rtw_set_nettype(sc, ic->ic_opmode); 3626 break; 3627 case IEEE80211_S_ASSOC: 3628 case IEEE80211_S_AUTH: 3629 break; 3630 } 3631 3632 if (nstate != IEEE80211_S_SCAN) 3633 callout_stop(&sc->sc_scan_ch); 3634 3635 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3636 } 3637 3638 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3639 static uint64_t 3640 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3641 { 3642 uint32_t tsftl, tsfth; 3643 3644 tsfth = RTW_READ(regs, RTW_TSFTRH); 3645 tsftl = RTW_READ(regs, RTW_TSFTRL); 3646 if (tsftl < rstamp) /* Compensate for rollover. */ 3647 tsfth--; 3648 return ((uint64_t)tsfth << 32) | rstamp; 3649 } 3650 3651 static void 3652 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3653 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3654 { 3655 struct ifnet *ifp = ic->ic_ifp; 3656 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3657 3658 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3659 3660 switch (subtype) { 3661 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3662 case IEEE80211_FC0_SUBTYPE_BEACON: 3663 if (ic->ic_opmode == IEEE80211_M_IBSS && 3664 ic->ic_state == IEEE80211_S_RUN) { 3665 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp); 3666 if (le64toh(ni->ni_tstamp.tsf) >= tsf) 3667 (void)ieee80211_ibss_merge(ni); 3668 } 3669 break; 3670 default: 3671 break; 3672 } 3673 return; 3674 } 3675 3676 static struct ieee80211_node * 3677 rtw_node_alloc(struct ieee80211_node_table *nt) 3678 { 3679 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3680 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3681 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3682 3683 DPRINTF(sc, RTW_DEBUG_NODE, 3684 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3685 return ni; 3686 } 3687 3688 static void 3689 rtw_node_free(struct ieee80211_node *ni) 3690 { 3691 struct ieee80211com *ic = ni->ni_ic; 3692 struct ifnet *ifp = ic->ic_ifp; 3693 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3694 3695 DPRINTF(sc, RTW_DEBUG_NODE, 3696 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3697 ether_sprintf(ni->ni_bssid))); 3698 (*sc->sc_mtbl.mt_node_free)(ni); 3699 } 3700 3701 static int 3702 rtw_media_change(struct ifnet *ifp) 3703 { 3704 int error; 3705 3706 error = ieee80211_media_change(ifp); 3707 if (error == ENETRESET) { 3708 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3709 (IFF_RUNNING|IFF_UP)) 3710 rtw_init(ifp); /* XXX lose error */ 3711 error = 0; 3712 } 3713 return error; 3714 } 3715 3716 static void 3717 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3718 { 3719 struct rtw_softc *sc = ifp->if_softc; 3720 3721 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3722 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3723 imr->ifm_status = 0; 3724 return; 3725 } 3726 ieee80211_media_status(ifp, imr); 3727 } 3728 3729 void 3730 rtw_power(int why, void *arg) 3731 { 3732 struct rtw_softc *sc = arg; 3733 struct ifnet *ifp = &sc->sc_if; 3734 int s; 3735 3736 DPRINTF(sc, RTW_DEBUG_PWR, 3737 ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3738 3739 s = splnet(); 3740 switch (why) { 3741 case PWR_STANDBY: 3742 /* XXX do nothing. */ 3743 break; 3744 case PWR_SUSPEND: 3745 rtw_stop(ifp, 0); 3746 if (sc->sc_power != NULL) 3747 (*sc->sc_power)(sc, why); 3748 break; 3749 case PWR_RESUME: 3750 if (ifp->if_flags & IFF_UP) { 3751 if (sc->sc_power != NULL) 3752 (*sc->sc_power)(sc, why); 3753 rtw_init(ifp); 3754 } 3755 break; 3756 case PWR_SOFTSUSPEND: 3757 case PWR_SOFTSTANDBY: 3758 case PWR_SOFTRESUME: 3759 break; 3760 } 3761 splx(s); 3762 } 3763 3764 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 3765 void 3766 rtw_shutdown(void *arg) 3767 { 3768 struct rtw_softc *sc = arg; 3769 3770 rtw_stop(&sc->sc_if, 1); 3771 } 3772 3773 static inline void 3774 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3775 { 3776 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3777 ifp->if_softc = softc; 3778 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3779 IFF_NOTRAILERS; 3780 ifp->if_ioctl = rtw_ioctl; 3781 ifp->if_start = rtw_start; 3782 ifp->if_watchdog = rtw_watchdog; 3783 ifp->if_init = rtw_init; 3784 ifp->if_stop = rtw_stop; 3785 } 3786 3787 static inline void 3788 rtw_set80211props(struct ieee80211com *ic) 3789 { 3790 int nrate; 3791 ic->ic_phytype = IEEE80211_T_DS; 3792 ic->ic_opmode = IEEE80211_M_STA; 3793 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3794 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 3795 3796 nrate = 0; 3797 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3798 IEEE80211_RATE_BASIC | 2; 3799 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3800 IEEE80211_RATE_BASIC | 4; 3801 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3802 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3803 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3804 } 3805 3806 static inline void 3807 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3808 { 3809 mtbl->mt_newstate = ic->ic_newstate; 3810 ic->ic_newstate = rtw_newstate; 3811 3812 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3813 ic->ic_recv_mgmt = rtw_recv_mgmt; 3814 3815 mtbl->mt_node_free = ic->ic_node_free; 3816 ic->ic_node_free = rtw_node_free; 3817 3818 mtbl->mt_node_alloc = ic->ic_node_alloc; 3819 ic->ic_node_alloc = rtw_node_alloc; 3820 3821 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3822 ic->ic_crypto.cs_key_set = rtw_key_set; 3823 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3824 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3825 } 3826 3827 static inline void 3828 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 3829 void *arg) 3830 { 3831 /* 3832 * Make sure the interface is shutdown during reboot. 3833 */ 3834 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 3835 if (hooks->rh_shutdown == NULL) 3836 printf("%s: WARNING: unable to establish shutdown hook\n", 3837 dvname); 3838 3839 /* 3840 * Add a suspend hook to make sure we come back up after a 3841 * resume. 3842 */ 3843 hooks->rh_power = powerhook_establish(rtw_power, arg); 3844 if (hooks->rh_power == NULL) 3845 printf("%s: WARNING: unable to establish power hook\n", 3846 dvname); 3847 } 3848 3849 static inline void 3850 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 3851 void *arg) 3852 { 3853 if (hooks->rh_shutdown != NULL) 3854 shutdownhook_disestablish(hooks->rh_shutdown); 3855 3856 if (hooks->rh_power != NULL) 3857 powerhook_disestablish(hooks->rh_power); 3858 } 3859 3860 static inline void 3861 rtw_init_radiotap(struct rtw_softc *sc) 3862 { 3863 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3864 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3865 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT); 3866 3867 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3868 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3869 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3870 } 3871 3872 static int 3873 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3874 { 3875 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3876 SIMPLEQ_INIT(&tsb->tsb_freeq); 3877 tsb->tsb_ndesc = qlen; 3878 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3879 M_NOWAIT); 3880 if (tsb->tsb_desc == NULL) 3881 return ENOMEM; 3882 return 0; 3883 } 3884 3885 static void 3886 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3887 { 3888 int pri; 3889 struct rtw_txsoft_blk *tsb; 3890 3891 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3892 tsb = &sc->sc_txsoft_blk[pri]; 3893 free(tsb->tsb_desc, M_DEVBUF); 3894 tsb->tsb_desc = NULL; 3895 } 3896 } 3897 3898 static int 3899 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3900 { 3901 int pri, rc = 0; 3902 int qlen[RTW_NTXPRI] = 3903 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3904 struct rtw_txsoft_blk *tsbs; 3905 3906 tsbs = sc->sc_txsoft_blk; 3907 3908 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3909 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3910 if (rc != 0) 3911 break; 3912 } 3913 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3914 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3915 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3916 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3917 return rc; 3918 } 3919 3920 static void 3921 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3922 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3923 { 3924 tdb->tdb_ndesc = ndesc; 3925 tdb->tdb_desc = desc; 3926 tdb->tdb_physbase = physbase; 3927 tdb->tdb_ofs = ofs; 3928 3929 (void)memset(tdb->tdb_desc, 0, 3930 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3931 3932 rtw_txdesc_blk_init(tdb); 3933 tdb->tdb_next = 0; 3934 } 3935 3936 static void 3937 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3938 { 3939 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3940 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3941 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3942 3943 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3944 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3945 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3946 3947 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3948 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3949 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3950 3951 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3952 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3953 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3954 } 3955 3956 static struct rtw_rf * 3957 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3958 { 3959 rtw_rf_write_t rf_write; 3960 struct rtw_rf *rf; 3961 3962 switch (rfchipid) { 3963 default: 3964 rf_write = rtw_rf_hostwrite; 3965 break; 3966 case RTW_RFCHIPID_INTERSIL: 3967 case RTW_RFCHIPID_PHILIPS: 3968 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3969 case RTW_RFCHIPID_RFMD: 3970 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3971 break; 3972 } 3973 3974 switch (rfchipid) { 3975 case RTW_RFCHIPID_GCT: 3976 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0); 3977 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3978 break; 3979 case RTW_RFCHIPID_MAXIM: 3980 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3981 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3982 break; 3983 case RTW_RFCHIPID_PHILIPS: 3984 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3985 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3986 break; 3987 case RTW_RFCHIPID_RFMD: 3988 /* XXX RFMD has no RF constructor */ 3989 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3990 /*FALLTHROUGH*/ 3991 default: 3992 return NULL; 3993 } 3994 rf->rf_continuous_tx_cb = 3995 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3996 rf->rf_continuous_tx_arg = (void *)sc; 3997 return rf; 3998 } 3999 4000 /* Revision C and later use a different PHY delay setting than 4001 * revisions A and B. 4002 */ 4003 static uint8_t 4004 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 4005 { 4006 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 4007 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 4008 4009 uint8_t phydelay = SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); 4010 4011 RTW_WRITE(regs, RTW_RCR, REVAB); 4012 RTW_WBW(regs, RTW_RCR, RTW_RCR); 4013 RTW_WRITE(regs, RTW_RCR, REVC); 4014 4015 RTW_WBR(regs, RTW_RCR, RTW_RCR); 4016 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 4017 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 4018 4019 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 4020 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 4021 4022 return phydelay; 4023 #undef REVC 4024 } 4025 4026 void 4027 rtw_attach(struct rtw_softc *sc) 4028 { 4029 struct ifnet *ifp = &sc->sc_if; 4030 struct ieee80211com *ic = &sc->sc_ic; 4031 struct rtw_txsoft_blk *tsb; 4032 int pri, rc; 4033 4034 rtw_cipher_wep = ieee80211_cipher_wep; 4035 rtw_cipher_wep.ic_decap = rtw_wep_decap; 4036 4037 NEXT_ATTACH_STATE(sc, DETACHED); 4038 4039 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 4040 case RTW_TCR_HWVERID_F: 4041 sc->sc_hwverid = 'F'; 4042 break; 4043 case RTW_TCR_HWVERID_D: 4044 sc->sc_hwverid = 'D'; 4045 break; 4046 default: 4047 sc->sc_hwverid = '?'; 4048 break; 4049 } 4050 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, 4051 sc->sc_hwverid); 4052 4053 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 4054 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 4055 0); 4056 4057 if (rc != 0) { 4058 printf("%s: could not allocate hw descriptors, error %d\n", 4059 sc->sc_dev.dv_xname, rc); 4060 goto err; 4061 } 4062 4063 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 4064 4065 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 4066 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 4067 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 4068 4069 if (rc != 0) { 4070 printf("%s: could not map hw descriptors, error %d\n", 4071 sc->sc_dev.dv_xname, rc); 4072 goto err; 4073 } 4074 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 4075 4076 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 4077 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 4078 4079 if (rc != 0) { 4080 printf("%s: could not create DMA map for hw descriptors, " 4081 "error %d\n", sc->sc_dev.dv_xname, rc); 4082 goto err; 4083 } 4084 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 4085 4086 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 4087 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 4088 4089 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4090 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 4091 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 4092 } 4093 4094 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 4095 sizeof(struct rtw_descs), NULL, 0); 4096 4097 if (rc != 0) { 4098 printf("%s: could not load DMA map for hw descriptors, " 4099 "error %d\n", sc->sc_dev.dv_xname, rc); 4100 goto err; 4101 } 4102 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 4103 4104 if (rtw_txsoft_blk_setup_all(sc) != 0) 4105 goto err; 4106 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 4107 4108 rtw_txdesc_blk_setup_all(sc); 4109 4110 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 4111 4112 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 4113 4114 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4115 tsb = &sc->sc_txsoft_blk[pri]; 4116 4117 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 4118 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 4119 printf("%s: could not load DMA map for " 4120 "hw tx descriptors, error %d\n", 4121 sc->sc_dev.dv_xname, rc); 4122 goto err; 4123 } 4124 } 4125 4126 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 4127 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 4128 RTW_RXQLEN)) != 0) { 4129 printf("%s: could not load DMA map for hw rx descriptors, " 4130 "error %d\n", sc->sc_dev.dv_xname, rc); 4131 goto err; 4132 } 4133 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 4134 4135 /* Reset the chip to a known state. */ 4136 if (rtw_reset(sc) != 0) 4137 goto err; 4138 NEXT_ATTACH_STATE(sc, FINISH_RESET); 4139 4140 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 4141 4142 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 4143 sc->sc_flags |= RTW_F_9356SROM; 4144 4145 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 4146 sc->sc_dev.dv_xname) != 0) 4147 goto err; 4148 4149 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 4150 4151 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 4152 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 4153 sc->sc_dev.dv_xname) != 0) { 4154 printf("%s: attach failed, malformed serial ROM\n", 4155 sc->sc_dev.dv_xname); 4156 goto err; 4157 } 4158 4159 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 4160 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 4161 4162 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 4163 4164 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 4165 4166 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 4167 sc->sc_flags & RTW_F_DIGPHY); 4168 4169 if (sc->sc_rf == NULL) { 4170 printf("%s: attach failed, could not attach RF\n", 4171 sc->sc_dev.dv_xname); 4172 goto err; 4173 } 4174 4175 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 4176 4177 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4178 4179 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4180 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 4181 4182 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4183 rtw_identify_country(&sc->sc_regs, &sc->sc_locale); 4184 4185 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 4186 sc->sc_dev.dv_xname); 4187 4188 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4189 sc->sc_dev.dv_xname) != 0) 4190 goto err; 4191 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4192 4193 rtw_setifprops(ifp, sc->sc_dev.dv_xname, (void*)sc); 4194 4195 IFQ_SET_READY(&ifp->if_snd); 4196 4197 sc->sc_ic.ic_ifp = ifp; 4198 rtw_set80211props(&sc->sc_ic); 4199 4200 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4201 4202 /* 4203 * Call MI attach routines. 4204 */ 4205 if_attach(ifp); 4206 ieee80211_ifattach(&sc->sc_ic); 4207 4208 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4209 4210 /* possibly we should fill in our own sc_send_prresp, since 4211 * the RTL8180 is probably sending probe responses in ad hoc 4212 * mode. 4213 */ 4214 4215 /* complete initialization */ 4216 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4217 callout_init(&sc->sc_scan_ch); 4218 4219 rtw_init_radiotap(sc); 4220 4221 #if NBPFILTER > 0 4222 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4223 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4224 #endif 4225 4226 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 4227 4228 NEXT_ATTACH_STATE(sc, FINISHED); 4229 4230 ieee80211_announce(ic); 4231 return; 4232 err: 4233 rtw_detach(sc); 4234 return; 4235 } 4236 4237 int 4238 rtw_detach(struct rtw_softc *sc) 4239 { 4240 struct ifnet *ifp = &sc->sc_if; 4241 int pri; 4242 4243 sc->sc_flags |= RTW_F_INVALID; 4244 4245 switch (sc->sc_attach_state) { 4246 case FINISHED: 4247 rtw_stop(ifp, 1); 4248 4249 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 4250 (void*)sc); 4251 callout_stop(&sc->sc_scan_ch); 4252 ieee80211_ifdetach(&sc->sc_ic); 4253 if_detach(ifp); 4254 break; 4255 case FINISH_ID_STA: 4256 case FINISH_RF_ATTACH: 4257 rtw_rf_destroy(sc->sc_rf); 4258 sc->sc_rf = NULL; 4259 /*FALLTHROUGH*/ 4260 case FINISH_PARSE_SROM: 4261 case FINISH_READ_SROM: 4262 rtw_srom_free(&sc->sc_srom); 4263 /*FALLTHROUGH*/ 4264 case FINISH_RESET: 4265 case FINISH_RXMAPS_CREATE: 4266 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4267 RTW_RXQLEN); 4268 /*FALLTHROUGH*/ 4269 case FINISH_TXMAPS_CREATE: 4270 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4271 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4272 sc->sc_txsoft_blk[pri].tsb_desc, 4273 sc->sc_txsoft_blk[pri].tsb_ndesc); 4274 } 4275 /*FALLTHROUGH*/ 4276 case FINISH_TXDESCBLK_SETUP: 4277 case FINISH_TXCTLBLK_SETUP: 4278 rtw_txsoft_blk_cleanup_all(sc); 4279 /*FALLTHROUGH*/ 4280 case FINISH_DESCMAP_LOAD: 4281 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4282 /*FALLTHROUGH*/ 4283 case FINISH_DESCMAP_CREATE: 4284 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4285 /*FALLTHROUGH*/ 4286 case FINISH_DESC_MAP: 4287 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 4288 sizeof(struct rtw_descs)); 4289 /*FALLTHROUGH*/ 4290 case FINISH_DESC_ALLOC: 4291 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4292 sc->sc_desc_nsegs); 4293 /*FALLTHROUGH*/ 4294 case DETACHED: 4295 NEXT_ATTACH_STATE(sc, DETACHED); 4296 break; 4297 } 4298 return 0; 4299 } 4300 4301 int 4302 rtw_activate(struct device *self, enum devact act) 4303 { 4304 struct rtw_softc *sc = (struct rtw_softc *)self; 4305 int rc = 0, s; 4306 4307 s = splnet(); 4308 switch (act) { 4309 case DVACT_ACTIVATE: 4310 rc = EOPNOTSUPP; 4311 break; 4312 4313 case DVACT_DEACTIVATE: 4314 if_deactivate(&sc->sc_if); 4315 break; 4316 } 4317 splx(s); 4318 return rc; 4319 } 4320
Indexes created Fri Sep 26 08:10:20 GMT 2025