rtw.c revision 1.7
1 /* $NetBSD: rtw.c,v 1.7 2004/12/20 00:28:02 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.7 2004/12/20 00:28:02 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #if 0 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #endif 54 #include <sys/time.h> 55 #include <sys/types.h> 56 57 #include <machine/endian.h> 58 #include <machine/bus.h> 59 #include <machine/intr.h> /* splnet */ 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_compat.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <dev/ic/rtwreg.h> 76 #include <dev/ic/rtwvar.h> 77 #include <dev/ic/rtwphyio.h> 78 #include <dev/ic/rtwphy.h> 79 80 #include <dev/ic/smc93cx6var.h> 81 82 #define KASSERT2(__cond, __msg) \ 83 do { \ 84 if (!(__cond)) \ 85 panic __msg ; \ 86 } while (0) 87 88 int rtw_rfprog_fallback = 0; 89 int rtw_host_rfio = 0; 90 int rtw_flush_rfio = 1; 91 int rtw_rfio_delay = 0; 92 93 #ifdef RTW_DEBUG 94 int rtw_debug = 2; 95 #endif /* RTW_DEBUG */ 96 97 #define NEXT_ATTACH_STATE(sc, state) do { \ 98 DPRINTF(sc, ("%s: attach state %s\n", __func__, #state)); \ 99 sc->sc_attach_state = state; \ 100 } while (0) 101 102 int rtw_dwelltime = 1000; /* milliseconds */ 103 104 static void rtw_start(struct ifnet *); 105 106 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 107 static int rtw_sysctl_verify_rfio_delay(SYSCTLFN_PROTO); 108 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 109 #ifdef RTW_DEBUG 110 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 111 #endif /* RTW_DEBUG */ 112 113 /* 114 * Setup sysctl(3) MIB, hw.rtw.* 115 * 116 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 117 */ 118 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 119 { 120 int rc; 121 struct sysctlnode *cnode, *rnode; 122 123 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 124 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 125 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 126 goto err; 127 128 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 129 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 130 "Realtek RTL818x 802.11 controls", 131 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 132 goto err; 133 134 #ifdef RTW_DEBUG 135 /* control debugging printfs */ 136 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 137 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 138 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 139 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 140 CTL_CREATE, CTL_EOL)) != 0) 141 goto err; 142 #endif /* RTW_DEBUG */ 143 /* set fallback RF programming method */ 144 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 145 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 146 "rfprog_fallback", 147 SYSCTL_DESCR("Set fallback RF programming method"), 148 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 149 CTL_CREATE, CTL_EOL)) != 0) 150 goto err; 151 152 /* force host to flush I/O by reading RTW_PHYADDR */ 153 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 154 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 155 "flush_rfio", SYSCTL_DESCR("Enable RF I/O flushing"), 156 rtw_sysctl_verify_rfio, 0, &rtw_flush_rfio, 0, 157 CTL_CREATE, CTL_EOL)) != 0) 158 goto err; 159 160 /* force host to control RF I/O bus */ 161 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 162 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 163 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 164 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 165 CTL_CREATE, CTL_EOL)) != 0) 166 goto err; 167 168 /* control RF I/O delay */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfio_delay", SYSCTL_DESCR("Set RF I/O delay"), 172 rtw_sysctl_verify_rfio_delay, 0, &rtw_rfio_delay, 0, 173 CTL_CREATE, CTL_EOL)) != 0) 174 goto err; 175 176 return; 177 err: 178 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 179 } 180 181 static int 182 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 183 { 184 int error, t; 185 struct sysctlnode node; 186 187 node = *rnode; 188 t = *(int*)rnode->sysctl_data; 189 node.sysctl_data = &t; 190 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 191 if (error || newp == NULL) 192 return (error); 193 194 if (t < lower || t > upper) 195 return (EINVAL); 196 197 *(int*)rnode->sysctl_data = t; 198 199 return (0); 200 } 201 202 static int 203 rtw_sysctl_verify_rfio_delay(SYSCTLFN_ARGS) 204 { 205 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1000000); 206 } 207 208 static int 209 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 210 { 211 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 212 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 213 } 214 215 static int 216 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 217 { 218 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1); 219 } 220 221 #ifdef RTW_DEBUG 222 static int 223 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 224 { 225 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 2); 226 } 227 228 static void 229 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 230 { 231 #define PRINTREG32(sc, reg) \ 232 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 233 dvname, reg, RTW_READ(regs, reg))) 234 235 #define PRINTREG16(sc, reg) \ 236 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %04x\n", \ 237 dvname, reg, RTW_READ16(regs, reg))) 238 239 #define PRINTREG8(sc, reg) \ 240 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %02x\n", \ 241 dvname, reg, RTW_READ8(regs, reg))) 242 243 RTW_DPRINTF2(("%s: %s\n", dvname, where)); 244 245 PRINTREG32(regs, RTW_IDR0); 246 PRINTREG32(regs, RTW_IDR1); 247 PRINTREG32(regs, RTW_MAR0); 248 PRINTREG32(regs, RTW_MAR1); 249 PRINTREG32(regs, RTW_TSFTRL); 250 PRINTREG32(regs, RTW_TSFTRH); 251 PRINTREG32(regs, RTW_TLPDA); 252 PRINTREG32(regs, RTW_TNPDA); 253 PRINTREG32(regs, RTW_THPDA); 254 PRINTREG32(regs, RTW_TCR); 255 PRINTREG32(regs, RTW_RCR); 256 PRINTREG32(regs, RTW_TINT); 257 PRINTREG32(regs, RTW_TBDA); 258 PRINTREG32(regs, RTW_ANAPARM); 259 PRINTREG32(regs, RTW_BB); 260 PRINTREG32(regs, RTW_PHYCFG); 261 PRINTREG32(regs, RTW_WAKEUP0L); 262 PRINTREG32(regs, RTW_WAKEUP0H); 263 PRINTREG32(regs, RTW_WAKEUP1L); 264 PRINTREG32(regs, RTW_WAKEUP1H); 265 PRINTREG32(regs, RTW_WAKEUP2LL); 266 PRINTREG32(regs, RTW_WAKEUP2LH); 267 PRINTREG32(regs, RTW_WAKEUP2HL); 268 PRINTREG32(regs, RTW_WAKEUP2HH); 269 PRINTREG32(regs, RTW_WAKEUP3LL); 270 PRINTREG32(regs, RTW_WAKEUP3LH); 271 PRINTREG32(regs, RTW_WAKEUP3HL); 272 PRINTREG32(regs, RTW_WAKEUP3HH); 273 PRINTREG32(regs, RTW_WAKEUP4LL); 274 PRINTREG32(regs, RTW_WAKEUP4LH); 275 PRINTREG32(regs, RTW_WAKEUP4HL); 276 PRINTREG32(regs, RTW_WAKEUP4HH); 277 PRINTREG32(regs, RTW_DK0); 278 PRINTREG32(regs, RTW_DK1); 279 PRINTREG32(regs, RTW_DK2); 280 PRINTREG32(regs, RTW_DK3); 281 PRINTREG32(regs, RTW_RETRYCTR); 282 PRINTREG32(regs, RTW_RDSAR); 283 PRINTREG32(regs, RTW_FER); 284 PRINTREG32(regs, RTW_FEMR); 285 PRINTREG32(regs, RTW_FPSR); 286 PRINTREG32(regs, RTW_FFER); 287 288 /* 16-bit registers */ 289 PRINTREG16(regs, RTW_BRSR); 290 PRINTREG16(regs, RTW_IMR); 291 PRINTREG16(regs, RTW_ISR); 292 PRINTREG16(regs, RTW_BCNITV); 293 PRINTREG16(regs, RTW_ATIMWND); 294 PRINTREG16(regs, RTW_BINTRITV); 295 PRINTREG16(regs, RTW_ATIMTRITV); 296 PRINTREG16(regs, RTW_CRC16ERR); 297 PRINTREG16(regs, RTW_CRC0); 298 PRINTREG16(regs, RTW_CRC1); 299 PRINTREG16(regs, RTW_CRC2); 300 PRINTREG16(regs, RTW_CRC3); 301 PRINTREG16(regs, RTW_CRC4); 302 PRINTREG16(regs, RTW_CWR); 303 304 /* 8-bit registers */ 305 PRINTREG8(regs, RTW_CR); 306 PRINTREG8(regs, RTW_9346CR); 307 PRINTREG8(regs, RTW_CONFIG0); 308 PRINTREG8(regs, RTW_CONFIG1); 309 PRINTREG8(regs, RTW_CONFIG2); 310 PRINTREG8(regs, RTW_MSR); 311 PRINTREG8(regs, RTW_CONFIG3); 312 PRINTREG8(regs, RTW_CONFIG4); 313 PRINTREG8(regs, RTW_TESTR); 314 PRINTREG8(regs, RTW_PSR); 315 PRINTREG8(regs, RTW_SCR); 316 PRINTREG8(regs, RTW_PHYDELAY); 317 PRINTREG8(regs, RTW_CRCOUNT); 318 PRINTREG8(regs, RTW_PHYADDR); 319 PRINTREG8(regs, RTW_PHYDATAW); 320 PRINTREG8(regs, RTW_PHYDATAR); 321 PRINTREG8(regs, RTW_CONFIG5); 322 PRINTREG8(regs, RTW_TPPOLL); 323 324 PRINTREG16(regs, RTW_BSSID16); 325 PRINTREG32(regs, RTW_BSSID32); 326 #undef PRINTREG32 327 #undef PRINTREG16 328 #undef PRINTREG8 329 } 330 #endif /* RTW_DEBUG */ 331 332 void 333 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 334 { 335 struct rtw_regs *regs = &sc->sc_regs; 336 337 u_int32_t tcr; 338 tcr = RTW_READ(regs, RTW_TCR); 339 tcr &= ~RTW_TCR_LBK_MASK; 340 if (enable) 341 tcr |= RTW_TCR_LBK_CONT; 342 else 343 tcr |= RTW_TCR_LBK_NORMAL; 344 RTW_WRITE(regs, RTW_TCR, tcr); 345 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 346 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 347 rtw_txdac_enable(sc, !enable); 348 rtw_set_access(sc, RTW_ACCESS_ANAPARM); /* XXX Voodoo from Linux. */ 349 rtw_set_access(sc, RTW_ACCESS_NONE); 350 } 351 352 static const char * 353 rtw_access_string(enum rtw_access access) 354 { 355 switch (access) { 356 case RTW_ACCESS_NONE: 357 return "none"; 358 case RTW_ACCESS_CONFIG: 359 return "config"; 360 case RTW_ACCESS_ANAPARM: 361 return "anaparm"; 362 default: 363 return "unknown"; 364 } 365 } 366 367 static void 368 rtw_set_access1(struct rtw_regs *regs, 369 enum rtw_access oaccess, enum rtw_access naccess) 370 { 371 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 372 KASSERT(oaccess >= RTW_ACCESS_NONE && oaccess <= RTW_ACCESS_ANAPARM); 373 374 if (naccess == oaccess) 375 return; 376 377 switch (naccess) { 378 case RTW_ACCESS_NONE: 379 switch (oaccess) { 380 case RTW_ACCESS_ANAPARM: 381 rtw_anaparm_enable(regs, 0); 382 /*FALLTHROUGH*/ 383 case RTW_ACCESS_CONFIG: 384 rtw_config0123_enable(regs, 0); 385 /*FALLTHROUGH*/ 386 case RTW_ACCESS_NONE: 387 break; 388 } 389 break; 390 case RTW_ACCESS_CONFIG: 391 switch (oaccess) { 392 case RTW_ACCESS_NONE: 393 rtw_config0123_enable(regs, 1); 394 /*FALLTHROUGH*/ 395 case RTW_ACCESS_CONFIG: 396 break; 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 break; 400 } 401 break; 402 case RTW_ACCESS_ANAPARM: 403 switch (oaccess) { 404 case RTW_ACCESS_NONE: 405 rtw_config0123_enable(regs, 1); 406 /*FALLTHROUGH*/ 407 case RTW_ACCESS_CONFIG: 408 rtw_anaparm_enable(regs, 1); 409 /*FALLTHROUGH*/ 410 case RTW_ACCESS_ANAPARM: 411 break; 412 } 413 break; 414 } 415 } 416 417 void 418 rtw_set_access(struct rtw_softc *sc, enum rtw_access access) 419 { 420 rtw_set_access1(&sc->sc_regs, sc->sc_access, access); 421 RTW_DPRINTF(("%s: access %s -> %s\n", sc->sc_dev.dv_xname, 422 rtw_access_string(sc->sc_access), 423 rtw_access_string(access))); 424 sc->sc_access = access; 425 } 426 427 /* 428 * Enable registers, switch register banks. 429 */ 430 void 431 rtw_config0123_enable(struct rtw_regs *regs, int enable) 432 { 433 u_int8_t ecr; 434 ecr = RTW_READ8(regs, RTW_9346CR); 435 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 436 if (enable) 437 ecr |= RTW_9346CR_EEM_CONFIG; 438 else 439 ecr |= RTW_9346CR_EEM_NORMAL; 440 RTW_WRITE8(regs, RTW_9346CR, ecr); 441 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 442 } 443 444 /* requires rtw_config0123_enable(, 1) */ 445 void 446 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 447 { 448 u_int8_t cfg3; 449 450 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 451 cfg3 |= RTW_CONFIG3_CLKRUNEN; 452 if (enable) 453 cfg3 |= RTW_CONFIG3_PARMEN; 454 else 455 cfg3 &= ~RTW_CONFIG3_PARMEN; 456 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 457 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 458 } 459 460 /* requires rtw_anaparm_enable(, 1) */ 461 void 462 rtw_txdac_enable(struct rtw_softc *sc, int enable) 463 { 464 u_int32_t anaparm; 465 struct rtw_regs *regs = &sc->sc_regs; 466 467 anaparm = RTW_READ(regs, RTW_ANAPARM); 468 if (enable) 469 anaparm &= ~RTW_ANAPARM_TXDACOFF; 470 else 471 anaparm |= RTW_ANAPARM_TXDACOFF; 472 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 473 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 474 } 475 476 static __inline int 477 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 478 { 479 u_int8_t cr; 480 int i; 481 482 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 483 484 RTW_WBR(regs, RTW_CR, RTW_CR); 485 486 for (i = 0; i < 10000; i++) { 487 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 488 RTW_DPRINTF(("%s: reset in %dus\n", dvname, i)); 489 return 0; 490 } 491 RTW_RBR(regs, RTW_CR, RTW_CR); 492 DELAY(1); /* 1us */ 493 } 494 495 printf("%s: reset failed\n", dvname); 496 return ETIMEDOUT; 497 } 498 499 static __inline int 500 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 501 { 502 uint32_t tcr; 503 504 /* from Linux driver */ 505 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 506 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 507 508 RTW_WRITE(regs, RTW_TCR, tcr); 509 510 RTW_WBW(regs, RTW_CR, RTW_TCR); 511 512 return rtw_chip_reset1(regs, dvname); 513 } 514 515 static __inline int 516 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 517 { 518 int i; 519 u_int8_t ecr; 520 521 ecr = RTW_READ8(regs, RTW_9346CR); 522 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 523 RTW_WRITE8(regs, RTW_9346CR, ecr); 524 525 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 526 527 /* wait 2.5ms for completion */ 528 for (i = 0; i < 25; i++) { 529 ecr = RTW_READ8(regs, RTW_9346CR); 530 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 531 RTW_DPRINTF(("%s: recall EEPROM in %dus\n", dvname, 532 i * 100)); 533 return 0; 534 } 535 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 536 DELAY(100); 537 } 538 printf("%s: recall EEPROM failed\n", dvname); 539 return ETIMEDOUT; 540 } 541 542 static __inline int 543 rtw_reset(struct rtw_softc *sc) 544 { 545 int rc; 546 uint8_t config1; 547 548 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 549 return rc; 550 551 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 552 ; 553 554 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 555 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 556 /* TBD turn off maximum power saving? */ 557 558 return 0; 559 } 560 561 static __inline int 562 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txctl *descs, 563 u_int ndescs) 564 { 565 int i, rc = 0; 566 for (i = 0; i < ndescs; i++) { 567 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 568 0, 0, &descs[i].stx_dmamap); 569 if (rc != 0) 570 break; 571 } 572 return rc; 573 } 574 575 static __inline int 576 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 577 u_int ndescs) 578 { 579 int i, rc = 0; 580 for (i = 0; i < ndescs; i++) { 581 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 582 &descs[i].srx_dmamap); 583 if (rc != 0) 584 break; 585 } 586 return rc; 587 } 588 589 static __inline void 590 rtw_rxctls_setup(struct rtw_rxctl *descs) 591 { 592 int i; 593 for (i = 0; i < RTW_RXQLEN; i++) 594 descs[i].srx_mbuf = NULL; 595 } 596 597 static __inline void 598 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 599 u_int ndescs) 600 { 601 int i; 602 for (i = 0; i < ndescs; i++) { 603 if (descs[i].srx_dmamap != NULL) 604 bus_dmamap_destroy(dmat, descs[i].srx_dmamap); 605 } 606 } 607 608 static __inline void 609 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txctl *descs, 610 u_int ndescs) 611 { 612 int i; 613 for (i = 0; i < ndescs; i++) { 614 if (descs[i].stx_dmamap != NULL) 615 bus_dmamap_destroy(dmat, descs[i].stx_dmamap); 616 } 617 } 618 619 static __inline void 620 rtw_srom_free(struct rtw_srom *sr) 621 { 622 sr->sr_size = 0; 623 if (sr->sr_content == NULL) 624 return; 625 free(sr->sr_content, M_DEVBUF); 626 sr->sr_content = NULL; 627 } 628 629 static void 630 rtw_srom_defaults(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 631 enum rtw_rfchipid *rfchipid, u_int32_t *rcr) 632 { 633 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 634 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 635 *rcr |= RTW_RCR_ENCS1; 636 *rfchipid = RTW_RFCHIPID_PHILIPS; 637 } 638 639 static int 640 rtw_srom_parse(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 641 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, enum rtw_locale *locale, 642 const char *dvname) 643 { 644 int i; 645 const char *rfname, *paname; 646 char scratch[sizeof("unknown 0xXX")]; 647 u_int16_t version; 648 u_int8_t mac[IEEE80211_ADDR_LEN]; 649 650 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 651 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 652 653 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 654 printf("%s: SROM version %d.%d", dvname, version >> 8, version & 0xff); 655 656 if (version <= 0x0101) { 657 printf(" is not understood, limping along with defaults\n"); 658 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 659 return 0; 660 } 661 printf("\n"); 662 663 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 664 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 665 666 RTW_DPRINTF(("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 667 668 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 669 670 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 671 *flags |= RTW_F_ANTDIV; 672 673 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) != 0) 674 *flags |= RTW_F_DIGPHY; 675 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 676 *flags |= RTW_F_DFLANTB; 677 678 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 679 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 680 681 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 682 switch (*rfchipid) { 683 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 684 rfname = "GCT GRF5101"; 685 paname = "Winspring WS9901"; 686 break; 687 case RTW_RFCHIPID_MAXIM: 688 rfname = "Maxim MAX2820"; /* guess */ 689 paname = "Maxim MAX2422"; /* guess */ 690 break; 691 case RTW_RFCHIPID_INTERSIL: 692 rfname = "Intersil HFA3873"; /* guess */ 693 paname = "Intersil <unknown>"; 694 break; 695 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 696 rfname = "Philips SA2400A"; 697 paname = "Philips SA2411"; 698 break; 699 case RTW_RFCHIPID_RFMD: 700 /* this is the same front-end as an atw(4)! */ 701 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 702 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 703 "SYN: Silicon Labs Si4126"; /* inferred from 704 * reference driver 705 */ 706 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 707 break; 708 case RTW_RFCHIPID_RESERVED: 709 rfname = paname = "reserved"; 710 break; 711 default: 712 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 713 rfname = paname = scratch; 714 } 715 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 716 717 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 718 case RTW_CONFIG0_GL_USA: 719 *locale = RTW_LOCALE_USA; 720 break; 721 case RTW_CONFIG0_GL_EUROPE: 722 *locale = RTW_LOCALE_EUROPE; 723 break; 724 case RTW_CONFIG0_GL_JAPAN: 725 *locale = RTW_LOCALE_JAPAN; 726 break; 727 default: 728 *locale = RTW_LOCALE_UNKNOWN; 729 break; 730 } 731 return 0; 732 } 733 734 /* Returns -1 on failure. */ 735 static int 736 rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr, 737 const char *dvname) 738 { 739 int rc; 740 struct seeprom_descriptor sd; 741 u_int8_t ecr; 742 743 (void)memset(&sd, 0, sizeof(sd)); 744 745 ecr = RTW_READ8(regs, RTW_9346CR); 746 747 if ((flags & RTW_F_9356SROM) != 0) { 748 RTW_DPRINTF(("%s: 93c56 SROM\n", dvname)); 749 sr->sr_size = 256; 750 sd.sd_chip = C56_66; 751 } else { 752 RTW_DPRINTF(("%s: 93c46 SROM\n", dvname)); 753 sr->sr_size = 128; 754 sd.sd_chip = C46; 755 } 756 757 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 758 RTW_9346CR_EEM_MASK); 759 ecr |= RTW_9346CR_EEM_PROGRAM; 760 761 RTW_WRITE8(regs, RTW_9346CR, ecr); 762 763 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 764 765 if (sr->sr_content == NULL) { 766 printf("%s: unable to allocate SROM buffer\n", dvname); 767 return ENOMEM; 768 } 769 770 (void)memset(sr->sr_content, 0, sr->sr_size); 771 772 /* RTL8180 has a single 8-bit register for controlling the 773 * 93cx6 SROM. There is no "ready" bit. The RTL8180 774 * input/output sense is the reverse of read_seeprom's. 775 */ 776 sd.sd_tag = regs->r_bt; 777 sd.sd_bsh = regs->r_bh; 778 sd.sd_regsize = 1; 779 sd.sd_control_offset = RTW_9346CR; 780 sd.sd_status_offset = RTW_9346CR; 781 sd.sd_dataout_offset = RTW_9346CR; 782 sd.sd_CK = RTW_9346CR_EESK; 783 sd.sd_CS = RTW_9346CR_EECS; 784 sd.sd_DI = RTW_9346CR_EEDO; 785 sd.sd_DO = RTW_9346CR_EEDI; 786 /* make read_seeprom enter EEPROM read/write mode */ 787 sd.sd_MS = ecr; 788 sd.sd_RDY = 0; 789 #if 0 790 sd.sd_clkdelay = 50; 791 #endif 792 793 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 794 printf("%s: could not read SROM\n", dvname); 795 free(sr->sr_content, M_DEVBUF); 796 sr->sr_content = NULL; 797 return -1; /* XXX */ 798 } 799 800 /* end EEPROM read/write mode */ 801 RTW_WRITE8(regs, RTW_9346CR, 802 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 803 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 804 805 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 806 return rc; 807 808 #ifdef RTW_DEBUG 809 { 810 int i; 811 RTW_DPRINTF(("\n%s: serial ROM:\n\t", dvname)); 812 for (i = 0; i < sr->sr_size/2; i++) { 813 if (((i % 8) == 0) && (i != 0)) 814 RTW_DPRINTF(("\n\t")); 815 RTW_DPRINTF((" %04x", sr->sr_content[i])); 816 } 817 RTW_DPRINTF(("\n")); 818 } 819 #endif /* RTW_DEBUG */ 820 return 0; 821 } 822 823 static void 824 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 825 const char *dvname) 826 { 827 u_int8_t cfg4; 828 const char *method; 829 830 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 831 832 switch (rfchipid) { 833 default: 834 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 835 method = "fallback"; 836 break; 837 case RTW_RFCHIPID_INTERSIL: 838 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 839 method = "Intersil"; 840 break; 841 case RTW_RFCHIPID_PHILIPS: 842 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 843 method = "Philips"; 844 break; 845 case RTW_RFCHIPID_RFMD: 846 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 847 method = "RFMD"; 848 break; 849 } 850 851 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 852 853 printf("%s: %s RF programming method, %#02x\n", dvname, method, 854 RTW_READ8(regs, RTW_CONFIG4)); 855 } 856 857 #if 0 858 static __inline int 859 rtw_identify_rf(struct rtw_regs *regs, enum rtw_rftype *rftype, 860 const char *dvname) 861 { 862 u_int8_t cfg4; 863 const char *name; 864 865 cfg4 = RTW_READ8(regs, RTW_CONFIG4); 866 867 switch (cfg4 & RTW_CONFIG4_RFTYPE_MASK) { 868 case RTW_CONFIG4_RFTYPE_PHILIPS: 869 *rftype = RTW_RFTYPE_PHILIPS; 870 name = "Philips"; 871 break; 872 case RTW_CONFIG4_RFTYPE_INTERSIL: 873 *rftype = RTW_RFTYPE_INTERSIL; 874 name = "Intersil"; 875 break; 876 case RTW_CONFIG4_RFTYPE_RFMD: 877 *rftype = RTW_RFTYPE_RFMD; 878 name = "RFMD"; 879 break; 880 default: 881 name = "<unknown>"; 882 return ENXIO; 883 } 884 885 printf("%s: RF prog type %s\n", dvname, name); 886 return 0; 887 } 888 #endif 889 890 static __inline void 891 rtw_init_channels(enum rtw_locale locale, 892 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 893 const char *dvname) 894 { 895 int i; 896 const char *name = NULL; 897 #define ADD_CHANNEL(_chans, _chan) do { \ 898 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 899 (*_chans)[_chan].ic_freq = \ 900 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 901 } while (0) 902 903 switch (locale) { 904 case RTW_LOCALE_USA: /* 1-11 */ 905 name = "USA"; 906 for (i = 1; i <= 11; i++) 907 ADD_CHANNEL(chans, i); 908 break; 909 case RTW_LOCALE_JAPAN: /* 1-14 */ 910 name = "Japan"; 911 ADD_CHANNEL(chans, 14); 912 for (i = 1; i <= 14; i++) 913 ADD_CHANNEL(chans, i); 914 break; 915 case RTW_LOCALE_EUROPE: /* 1-13 */ 916 name = "Europe"; 917 for (i = 1; i <= 13; i++) 918 ADD_CHANNEL(chans, i); 919 break; 920 default: /* 10-11 allowed by most countries */ 921 name = "<unknown>"; 922 for (i = 10; i <= 11; i++) 923 ADD_CHANNEL(chans, i); 924 break; 925 } 926 printf("%s: Geographic Location %s\n", dvname, name); 927 #undef ADD_CHANNEL 928 } 929 930 static __inline void 931 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 932 const char *dvname) 933 { 934 u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 935 936 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 937 case RTW_CONFIG0_GL_USA: 938 *locale = RTW_LOCALE_USA; 939 break; 940 case RTW_CONFIG0_GL_JAPAN: 941 *locale = RTW_LOCALE_JAPAN; 942 break; 943 case RTW_CONFIG0_GL_EUROPE: 944 *locale = RTW_LOCALE_EUROPE; 945 break; 946 default: 947 *locale = RTW_LOCALE_UNKNOWN; 948 break; 949 } 950 } 951 952 static __inline int 953 rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN], 954 const char *dvname) 955 { 956 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 957 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 958 }; 959 u_int32_t idr0 = RTW_READ(regs, RTW_IDR0), 960 idr1 = RTW_READ(regs, RTW_IDR1); 961 962 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 963 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 964 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 965 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 966 967 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 968 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 969 970 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 971 printf("%s: could not get mac address, attach failed\n", 972 dvname); 973 return ENXIO; 974 } 975 976 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 977 978 return 0; 979 } 980 981 static u_int8_t 982 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 983 struct ieee80211_channel *chan) 984 { 985 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 986 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 987 ("%s: channel %d out of range", __func__, 988 idx - RTW_SR_TXPOWER1 + 1)); 989 return RTW_SR_GET(sr, idx); 990 } 991 992 static void 993 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *htcs) 994 { 995 int pri; 996 u_int ndesc[RTW_NTXPRI] = 997 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 998 999 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1000 htcs[pri].htc_nfree = ndesc[pri]; 1001 htcs[pri].htc_next = 0; 1002 } 1003 } 1004 1005 static int 1006 rtw_txctl_blk_init(struct rtw_txctl_blk *stc) 1007 { 1008 int i; 1009 struct rtw_txctl *stx; 1010 1011 SIMPLEQ_INIT(&stc->stc_dirtyq); 1012 SIMPLEQ_INIT(&stc->stc_freeq); 1013 for (i = 0; i < stc->stc_ndesc; i++) { 1014 stx = &stc->stc_desc[i]; 1015 stx->stx_mbuf = NULL; 1016 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1017 } 1018 return 0; 1019 } 1020 1021 static void 1022 rtw_txctl_blk_init_all(struct rtw_txctl_blk *stcs) 1023 { 1024 int pri; 1025 for (pri = 0; pri < RTW_NTXPRI; pri++) 1026 rtw_txctl_blk_init(&stcs[pri]); 1027 } 1028 1029 static __inline void 1030 rtw_rxdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, u_int desc0, u_int 1031 nsync, int ops) 1032 { 1033 /* sync to end of ring */ 1034 if (desc0 + nsync > RTW_NRXDESC) { 1035 bus_dmamap_sync(dmat, dmap, 1036 offsetof(struct rtw_descs, hd_rx[desc0]), 1037 sizeof(struct rtw_rxdesc) * (RTW_NRXDESC - desc0), ops); 1038 nsync -= (RTW_NRXDESC - desc0); 1039 desc0 = 0; 1040 } 1041 1042 /* sync what remains */ 1043 bus_dmamap_sync(dmat, dmap, 1044 offsetof(struct rtw_descs, hd_rx[desc0]), 1045 sizeof(struct rtw_rxdesc) * nsync, ops); 1046 } 1047 1048 static void 1049 rtw_txdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1050 struct rtw_txdesc_blk *htc, u_int desc0, u_int nsync, int ops) 1051 { 1052 /* sync to end of ring */ 1053 if (desc0 + nsync > htc->htc_ndesc) { 1054 bus_dmamap_sync(dmat, dmap, 1055 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1056 sizeof(struct rtw_txdesc) * (htc->htc_ndesc - desc0), 1057 ops); 1058 nsync -= (htc->htc_ndesc - desc0); 1059 desc0 = 0; 1060 } 1061 1062 /* sync what remains */ 1063 bus_dmamap_sync(dmat, dmap, 1064 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1065 sizeof(struct rtw_txdesc) * nsync, ops); 1066 } 1067 1068 static void 1069 rtw_txdescs_sync_all(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1070 struct rtw_txdesc_blk *htcs) 1071 { 1072 int pri; 1073 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1074 rtw_txdescs_sync(dmat, dmap, 1075 &htcs[pri], 0, htcs[pri].htc_ndesc, 1076 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1077 } 1078 } 1079 1080 static void 1081 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxctl *desc) 1082 { 1083 int i; 1084 struct rtw_rxctl *srx; 1085 1086 for (i = 0; i < RTW_NRXDESC; i++) { 1087 srx = &desc[i]; 1088 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, 1089 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1090 bus_dmamap_unload(dmat, srx->srx_dmamap); 1091 m_freem(srx->srx_mbuf); 1092 srx->srx_mbuf = NULL; 1093 } 1094 } 1095 1096 static __inline int 1097 rtw_rxbuf_alloc(bus_dma_tag_t dmat, struct rtw_rxctl *srx) 1098 { 1099 int rc; 1100 struct mbuf *m; 1101 1102 MGETHDR(m, M_DONTWAIT, MT_DATA); 1103 if (m == NULL) 1104 return ENOMEM; 1105 1106 MCLGET(m, M_DONTWAIT); 1107 if (m == NULL) 1108 return ENOMEM; 1109 1110 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1111 1112 rc = bus_dmamap_load_mbuf(dmat, srx->srx_dmamap, m, BUS_DMA_NOWAIT); 1113 if (rc != 0) 1114 return rc; 1115 1116 srx->srx_mbuf = m; 1117 1118 return 0; 1119 } 1120 1121 static int 1122 rtw_rxctl_init_all(bus_dma_tag_t dmat, struct rtw_rxctl *desc, 1123 u_int *next, const char *dvname) 1124 { 1125 int i, rc; 1126 struct rtw_rxctl *srx; 1127 1128 for (i = 0; i < RTW_NRXDESC; i++) { 1129 srx = &desc[i]; 1130 if ((rc = rtw_rxbuf_alloc(dmat, srx)) == 0) 1131 continue; 1132 printf("%s: failed rtw_rxbuf_alloc after %d buffers, rc = %d\n", 1133 dvname, i, rc); 1134 if (i == 0) { 1135 rtw_rxbufs_release(dmat, desc); 1136 return rc; 1137 } 1138 } 1139 *next = 0; 1140 return 0; 1141 } 1142 1143 static __inline void 1144 rtw_rxdesc_init(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1145 struct rtw_rxdesc *hrx, struct rtw_rxctl *srx, int idx) 1146 { 1147 int is_last = (idx == RTW_NRXDESC - 1); 1148 uint32_t ctl; 1149 1150 hrx->hrx_buf = htole32(srx->srx_dmamap->dm_segs[0].ds_addr); 1151 1152 ctl = LSHIFT(srx->srx_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1153 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1154 1155 if (is_last) 1156 ctl |= RTW_RXCTL_EOR; 1157 1158 hrx->hrx_ctl = htole32(ctl); 1159 1160 /* sync the mbuf */ 1161 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, srx->srx_dmamap->dm_mapsize, 1162 BUS_DMASYNC_PREREAD); 1163 1164 /* sync the descriptor */ 1165 bus_dmamap_sync(dmat, dmam, RTW_DESC_OFFSET(hd_rx, idx), 1166 sizeof(struct rtw_rxdesc), 1167 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1168 } 1169 1170 static void 1171 rtw_rxdesc_init_all(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1172 struct rtw_rxdesc *desc, struct rtw_rxctl *ctl) 1173 { 1174 int i; 1175 struct rtw_rxdesc *hrx; 1176 struct rtw_rxctl *srx; 1177 1178 for (i = 0; i < RTW_NRXDESC; i++) { 1179 hrx = &desc[i]; 1180 srx = &ctl[i]; 1181 rtw_rxdesc_init(dmat, dmam, hrx, srx, i); 1182 } 1183 } 1184 1185 static void 1186 rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable) 1187 { 1188 u_int8_t cr; 1189 1190 RTW_DPRINTF(("%s: %s 0x%02x\n", __func__, 1191 enable ? "enable" : "disable", flags)); 1192 1193 cr = RTW_READ8(regs, RTW_CR); 1194 1195 /* XXX reference source does not enable MULRW */ 1196 #if 0 1197 /* enable PCI Read/Write Multiple */ 1198 cr |= RTW_CR_MULRW; 1199 #endif 1200 1201 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1202 if (enable) 1203 cr |= flags; 1204 else 1205 cr &= ~flags; 1206 RTW_WRITE8(regs, RTW_CR, cr); 1207 RTW_SYNC(regs, RTW_CR, RTW_CR); 1208 } 1209 1210 static void 1211 rtw_intr_rx(struct rtw_softc *sc, u_int16_t isr) 1212 { 1213 u_int next; 1214 int rate, rssi; 1215 u_int32_t hrssi, hstat, htsfth, htsftl; 1216 struct rtw_rxdesc *hrx; 1217 struct rtw_rxctl *srx; 1218 struct mbuf *m; 1219 1220 struct ieee80211_node *ni; 1221 struct ieee80211_frame *wh; 1222 1223 for (next = sc->sc_rxnext; ; next = (next + 1) % RTW_RXQLEN) { 1224 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1225 next, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1226 hrx = &sc->sc_rxdesc[next]; 1227 srx = &sc->sc_rxctl[next]; 1228 1229 hstat = le32toh(hrx->hrx_stat); 1230 hrssi = le32toh(hrx->hrx_rssi); 1231 htsfth = le32toh(hrx->hrx_tsfth); 1232 htsftl = le32toh(hrx->hrx_tsftl); 1233 1234 RTW_DPRINTF2(("%s: rxdesc[%d] hstat %#08x hrssi %#08x " 1235 "htsft %#08x%08x\n", __func__, next, 1236 hstat, hrssi, htsfth, htsftl)); 1237 1238 if ((hstat & RTW_RXSTAT_OWN) != 0) /* belongs to NIC */ 1239 break; 1240 1241 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1242 printf("%s: DMA error/FIFO overflow %08x, " 1243 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1244 hstat & RTW_RXSTAT_IOERROR, next); 1245 goto next; 1246 } 1247 1248 switch (hstat & RTW_RXSTAT_RATE_MASK) { 1249 case RTW_RXSTAT_RATE_1MBPS: 1250 rate = 10; 1251 break; 1252 case RTW_RXSTAT_RATE_2MBPS: 1253 rate = 20; 1254 break; 1255 case RTW_RXSTAT_RATE_5MBPS: 1256 rate = 55; 1257 break; 1258 default: 1259 #ifdef RTW_DEBUG 1260 if (rtw_debug > 1) 1261 printf("%s: interpreting rate #%d as 11 MB/s\n", 1262 sc->sc_dev.dv_xname, 1263 MASK_AND_RSHIFT(hstat, 1264 RTW_RXSTAT_RATE_MASK)); 1265 #endif /* RTW_DEBUG */ 1266 /*FALLTHROUGH*/ 1267 case RTW_RXSTAT_RATE_11MBPS: 1268 rate = 110; 1269 break; 1270 } 1271 1272 RTW_DPRINTF2(("%s: rate %d\n", __func__, rate)); 1273 1274 #ifdef RTW_DEBUG 1275 #define PRINTSTAT(flag) do { \ 1276 if ((hstat & flag) != 0) { \ 1277 printf("%s" #flag, delim); \ 1278 delim = ","; \ 1279 } \ 1280 } while (0) 1281 if (rtw_debug > 1) { 1282 const char *delim = "<"; 1283 printf("%s: ", sc->sc_dev.dv_xname); 1284 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1285 printf("status %08x<", hstat); 1286 PRINTSTAT(RTW_RXSTAT_SPLCP); 1287 PRINTSTAT(RTW_RXSTAT_MAR); 1288 PRINTSTAT(RTW_RXSTAT_PAR); 1289 PRINTSTAT(RTW_RXSTAT_BAR); 1290 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1291 PRINTSTAT(RTW_RXSTAT_CRC32); 1292 PRINTSTAT(RTW_RXSTAT_ICV); 1293 printf(">, "); 1294 } 1295 printf("rate %d.%d Mb/s, time %08x%08x\n", 1296 rate / 10, rate % 10, htsfth, htsftl); 1297 } 1298 #endif /* RTW_DEBUG */ 1299 1300 if ((hstat & RTW_RXSTAT_RES) != 0 && 1301 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1302 goto next; 1303 1304 /* if bad flags, skip descriptor */ 1305 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1306 printf("%s: too many rx segments\n", 1307 sc->sc_dev.dv_xname); 1308 goto next; 1309 } 1310 1311 m = srx->srx_mbuf; 1312 1313 /* if temporarily out of memory, re-use mbuf */ 1314 if (rtw_rxbuf_alloc(sc->sc_dmat, srx) != 0) { 1315 printf("%s: rtw_rxbuf_alloc(, %d) failed, " 1316 "dropping this packet\n", sc->sc_dev.dv_xname, 1317 next); 1318 goto next; 1319 } 1320 1321 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1322 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1323 else { 1324 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1325 /* TBD find out each front-end's LNA gain in the 1326 * front-end's units 1327 */ 1328 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1329 rssi |= 0x80; 1330 } 1331 1332 m->m_pkthdr.len = m->m_len = 1333 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1334 m->m_flags |= M_HASFCS; 1335 1336 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 1337 sc->sc_ic.ic_stats.is_rx_tooshort++; 1338 goto next; 1339 } 1340 wh = mtod(m, struct ieee80211_frame *); 1341 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1342 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1343 1344 sc->sc_tsfth = htsfth; 1345 1346 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1347 ieee80211_release_node(&sc->sc_ic, ni); 1348 next: 1349 rtw_rxdesc_init(sc->sc_dmat, sc->sc_desc_dmamap, 1350 hrx, srx, next); 1351 } 1352 sc->sc_rxnext = next; 1353 1354 return; 1355 } 1356 1357 static void 1358 rtw_txbuf_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1359 struct rtw_txctl *stx) 1360 { 1361 struct mbuf *m; 1362 struct ieee80211_node *ni; 1363 bus_dmamap_t dmamap; 1364 1365 dmamap = stx->stx_dmamap; 1366 m = stx->stx_mbuf; 1367 ni = stx->stx_ni; 1368 stx->stx_dmamap = NULL; 1369 stx->stx_mbuf = NULL; 1370 stx->stx_ni = NULL; 1371 1372 bus_dmamap_sync(dmat, dmamap, 0, dmamap->dm_mapsize, 1373 BUS_DMASYNC_POSTWRITE); 1374 bus_dmamap_unload(dmat, dmamap); 1375 m_freem(m); 1376 ieee80211_release_node(ic, ni); 1377 } 1378 1379 static void 1380 rtw_txbufs_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1381 struct rtw_txctl_blk *stc) 1382 { 1383 struct rtw_txctl *stx; 1384 1385 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1386 rtw_txbuf_release(dmat, ic, stx); 1387 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1388 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1389 } 1390 } 1391 1392 static __inline void 1393 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *htc, 1394 struct rtw_txctl *stx, int ndesc) 1395 { 1396 int data_retry, rts_retry; 1397 struct rtw_txdesc *htx0, *htxn; 1398 const char *condstring; 1399 1400 rtw_txbuf_release(sc->sc_dmat, &sc->sc_ic, stx); 1401 1402 htc->htc_nfree += ndesc; 1403 1404 htx0 = &htc->htc_desc[stx->stx_first]; 1405 htxn = &htc->htc_desc[stx->stx_last]; 1406 1407 rts_retry = MASK_AND_RSHIFT(le32toh(htx0->htx_stat), 1408 RTW_TXSTAT_RTSRETRY_MASK); 1409 data_retry = MASK_AND_RSHIFT(le32toh(htx0->htx_stat), 1410 RTW_TXSTAT_DRC_MASK); 1411 1412 sc->sc_if.if_collisions += rts_retry + data_retry; 1413 1414 if ((htx0->htx_stat & htole32(RTW_TXSTAT_TOK)) != 0) 1415 condstring = "ok"; 1416 else { 1417 sc->sc_if.if_oerrors++; 1418 condstring = "error"; 1419 } 1420 1421 DPRINTF2(sc, ("%s: stx %p txdesc[%d, %d] %s tries rts %u data %u\n", 1422 sc->sc_dev.dv_xname, stx, stx->stx_first, stx->stx_last, 1423 condstring, rts_retry, data_retry)); 1424 } 1425 1426 /* Collect transmitted packets. */ 1427 static __inline void 1428 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txctl_blk *stc, 1429 struct rtw_txdesc_blk *htc) 1430 { 1431 int ndesc; 1432 struct rtw_txctl *stx; 1433 1434 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1435 ndesc = 1 + stx->stx_last - stx->stx_first; 1436 if (stx->stx_last < stx->stx_first) 1437 ndesc += htc->htc_ndesc; 1438 1439 KASSERT(ndesc > 0); 1440 1441 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, htc, 1442 stx->stx_first, ndesc, 1443 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1444 1445 if ((htc->htc_desc[stx->stx_first].htx_stat & 1446 htole32(RTW_TXSTAT_OWN)) != 0) 1447 break; 1448 1449 rtw_collect_txpkt(sc, htc, stx, ndesc); 1450 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1451 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1452 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1453 } 1454 if (stx == NULL) 1455 stc->stc_tx_timer = 0; 1456 } 1457 1458 static void 1459 rtw_intr_tx(struct rtw_softc *sc, u_int16_t isr) 1460 { 1461 int pri; 1462 struct rtw_txctl_blk *stc; 1463 struct rtw_txdesc_blk *htc; 1464 1465 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1466 stc = &sc->sc_txctl_blk[pri]; 1467 htc = &sc->sc_txdesc_blk[pri]; 1468 1469 rtw_collect_txring(sc, stc, htc); 1470 1471 rtw_start(&sc->sc_if); 1472 } 1473 1474 /* TBD */ 1475 return; 1476 } 1477 1478 static void 1479 rtw_intr_beacon(struct rtw_softc *sc, u_int16_t isr) 1480 { 1481 /* TBD */ 1482 return; 1483 } 1484 1485 static void 1486 rtw_intr_atim(struct rtw_softc *sc) 1487 { 1488 /* TBD */ 1489 return; 1490 } 1491 1492 static void 1493 rtw_hwring_setup(struct rtw_softc *sc) 1494 { 1495 struct rtw_regs *regs = &sc->sc_regs; 1496 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1497 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1498 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1499 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1500 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1501 } 1502 1503 static void 1504 rtw_swring_setup(struct rtw_softc *sc) 1505 { 1506 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1507 1508 rtw_txctl_blk_init_all(&sc->sc_txctl_blk[0]); 1509 1510 rtw_rxctl_init_all(sc->sc_dmat, sc->sc_rxctl, &sc->sc_rxnext, 1511 sc->sc_dev.dv_xname); 1512 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, 1513 sc->sc_rxdesc, sc->sc_rxctl); 1514 1515 rtw_txdescs_sync_all(sc->sc_dmat, sc->sc_desc_dmamap, 1516 &sc->sc_txdesc_blk[0]); 1517 #if 0 /* redundant with rtw_rxdesc_init_all */ 1518 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1519 0, RTW_NRXDESC, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1520 #endif 1521 } 1522 1523 static void 1524 rtw_kick(struct rtw_softc *sc) 1525 { 1526 int pri; 1527 struct rtw_regs *regs = &sc->sc_regs; 1528 1529 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1530 RTW_WRITE16(regs, RTW_IMR, 0); 1531 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1532 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1533 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1534 &sc->sc_txctl_blk[pri]); 1535 } 1536 rtw_swring_setup(sc); 1537 rtw_hwring_setup(sc); 1538 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1539 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1540 } 1541 1542 static void 1543 rtw_intr_ioerror(struct rtw_softc *sc, u_int16_t isr) 1544 { 1545 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) { 1546 rtw_kick(sc); 1547 } 1548 if ((isr & RTW_INTR_TXFOVW) != 0) 1549 ; /* TBD restart transmit engine */ 1550 return; 1551 } 1552 1553 static __inline void 1554 rtw_suspend_ticks(struct rtw_softc *sc) 1555 { 1556 printf("%s: suspending ticks\n", sc->sc_dev.dv_xname); 1557 sc->sc_do_tick = 0; 1558 } 1559 1560 static __inline void 1561 rtw_resume_ticks(struct rtw_softc *sc) 1562 { 1563 u_int32_t tsftrl0, tsftrl1, next_tick; 1564 1565 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1566 1567 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1568 next_tick = tsftrl1 + 1000000; 1569 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1570 1571 sc->sc_do_tick = 1; 1572 1573 printf("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1574 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick); 1575 } 1576 1577 static void 1578 rtw_intr_timeout(struct rtw_softc *sc) 1579 { 1580 printf("%s: timeout\n", sc->sc_dev.dv_xname); 1581 if (sc->sc_do_tick) 1582 rtw_resume_ticks(sc); 1583 return; 1584 } 1585 1586 int 1587 rtw_intr(void *arg) 1588 { 1589 int i; 1590 struct rtw_softc *sc = arg; 1591 struct rtw_regs *regs = &sc->sc_regs; 1592 u_int16_t isr; 1593 1594 /* 1595 * If the interface isn't running, the interrupt couldn't 1596 * possibly have come from us. 1597 */ 1598 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1599 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1600 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1601 RTW_DPRINTF2(("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1602 return (0); 1603 } 1604 1605 for (i = 0; i < 10; i++) { 1606 isr = RTW_READ16(regs, RTW_ISR); 1607 1608 RTW_WRITE16(regs, RTW_ISR, isr); 1609 1610 if (sc->sc_intr_ack != NULL) 1611 (*sc->sc_intr_ack)(regs); 1612 1613 if (isr == 0) 1614 break; 1615 1616 #ifdef RTW_DEBUG 1617 #define PRINTINTR(flag) do { \ 1618 if ((isr & flag) != 0) { \ 1619 printf("%s" #flag, delim); \ 1620 delim = ","; \ 1621 } \ 1622 } while (0) 1623 1624 if (rtw_debug > 1 && isr != 0) { 1625 const char *delim = "<"; 1626 1627 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1628 1629 PRINTINTR(RTW_INTR_TXFOVW); 1630 PRINTINTR(RTW_INTR_TIMEOUT); 1631 PRINTINTR(RTW_INTR_BCNINT); 1632 PRINTINTR(RTW_INTR_ATIMINT); 1633 PRINTINTR(RTW_INTR_TBDER); 1634 PRINTINTR(RTW_INTR_TBDOK); 1635 PRINTINTR(RTW_INTR_THPDER); 1636 PRINTINTR(RTW_INTR_THPDOK); 1637 PRINTINTR(RTW_INTR_TNPDER); 1638 PRINTINTR(RTW_INTR_TNPDOK); 1639 PRINTINTR(RTW_INTR_RXFOVW); 1640 PRINTINTR(RTW_INTR_RDU); 1641 PRINTINTR(RTW_INTR_TLPDER); 1642 PRINTINTR(RTW_INTR_TLPDOK); 1643 PRINTINTR(RTW_INTR_RER); 1644 PRINTINTR(RTW_INTR_ROK); 1645 1646 printf(">\n"); 1647 } 1648 #undef PRINTINTR 1649 #endif /* RTW_DEBUG */ 1650 1651 if ((isr & RTW_INTR_RX) != 0) 1652 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1653 if ((isr & RTW_INTR_TX) != 0) 1654 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1655 if ((isr & RTW_INTR_BEACON) != 0) 1656 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1657 if ((isr & RTW_INTR_ATIMINT) != 0) 1658 rtw_intr_atim(sc); 1659 if ((isr & RTW_INTR_IOERROR) != 0) 1660 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1661 if ((isr & RTW_INTR_TIMEOUT) != 0) 1662 rtw_intr_timeout(sc); 1663 } 1664 1665 return 1; 1666 } 1667 1668 static void 1669 rtw_stop(struct ifnet *ifp, int disable) 1670 { 1671 int pri, s; 1672 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1673 struct ieee80211com *ic = &sc->sc_ic; 1674 struct rtw_regs *regs = &sc->sc_regs; 1675 1676 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1677 return; 1678 1679 rtw_suspend_ticks(sc); 1680 1681 s = splnet(); 1682 1683 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1684 1685 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1686 /* Disable interrupts. */ 1687 RTW_WRITE16(regs, RTW_IMR, 0); 1688 1689 /* Stop the transmit and receive processes. First stop DMA, 1690 * then disable receiver and transmitter. 1691 */ 1692 RTW_WRITE8(regs, RTW_TPPOLL, 1693 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ| 1694 RTW_TPPOLL_SLPQ); 1695 1696 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1697 } 1698 1699 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1700 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1701 &sc->sc_txctl_blk[pri]); 1702 } 1703 1704 if (disable) { 1705 rtw_disable(sc); 1706 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1707 } 1708 1709 /* Mark the interface as not running. Cancel the watchdog timer. */ 1710 ifp->if_flags &= ~IFF_RUNNING; 1711 ifp->if_timer = 0; 1712 1713 splx(s); 1714 1715 return; 1716 } 1717 1718 const char * 1719 rtw_pwrstate_string(enum rtw_pwrstate power) 1720 { 1721 switch (power) { 1722 case RTW_ON: 1723 return "on"; 1724 case RTW_SLEEP: 1725 return "sleep"; 1726 case RTW_OFF: 1727 return "off"; 1728 default: 1729 return "unknown"; 1730 } 1731 } 1732 1733 /* XXX I am using the RFMD settings gleaned from the reference 1734 * driver. 1735 */ 1736 static void 1737 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1738 int before_rf) 1739 { 1740 u_int32_t anaparm; 1741 1742 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1743 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1744 1745 anaparm = RTW_READ(regs, RTW_ANAPARM); 1746 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1747 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1748 1749 switch (power) { 1750 case RTW_OFF: 1751 if (before_rf) 1752 return; 1753 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_OFF; 1754 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_OFF; 1755 anaparm |= RTW_ANAPARM_TXDACOFF; 1756 break; 1757 case RTW_SLEEP: 1758 if (!before_rf) 1759 return; 1760 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_SLEEP; 1761 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_SLEEP; 1762 anaparm |= RTW_ANAPARM_TXDACOFF; 1763 break; 1764 case RTW_ON: 1765 if (!before_rf) 1766 return; 1767 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_ON; 1768 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_ON; 1769 break; 1770 } 1771 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1772 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1773 } 1774 1775 static void 1776 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1777 int before_rf) 1778 { 1779 u_int32_t anaparm; 1780 1781 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1782 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1783 1784 anaparm = RTW_READ(regs, RTW_ANAPARM); 1785 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1786 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1787 1788 switch (power) { 1789 case RTW_OFF: 1790 if (before_rf) 1791 return; 1792 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_OFF; 1793 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_OFF; 1794 anaparm |= RTW_ANAPARM_TXDACOFF; 1795 break; 1796 case RTW_SLEEP: 1797 if (!before_rf) 1798 return; 1799 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_SLEEP; 1800 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_SLEEP; 1801 anaparm |= RTW_ANAPARM_TXDACOFF; 1802 break; 1803 case RTW_ON: 1804 if (!before_rf) 1805 return; 1806 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_ON; 1807 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_ON; 1808 break; 1809 } 1810 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1811 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1812 } 1813 1814 static void 1815 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf) 1816 { 1817 struct rtw_regs *regs = &sc->sc_regs; 1818 1819 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 1820 1821 (*sc->sc_pwrstate_cb)(regs, power, before_rf); 1822 1823 rtw_set_access(sc, RTW_ACCESS_NONE); 1824 1825 return; 1826 } 1827 1828 static int 1829 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 1830 { 1831 int rc; 1832 1833 RTW_DPRINTF2(("%s: %s->%s\n", __func__, 1834 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 1835 1836 if (sc->sc_pwrstate == power) 1837 return 0; 1838 1839 rtw_pwrstate0(sc, power, 1); 1840 rc = rtw_rf_pwrstate(sc->sc_rf, power); 1841 rtw_pwrstate0(sc, power, 0); 1842 1843 switch (power) { 1844 case RTW_ON: 1845 /* TBD set LEDs */ 1846 break; 1847 case RTW_SLEEP: 1848 /* TBD */ 1849 break; 1850 case RTW_OFF: 1851 /* TBD */ 1852 break; 1853 } 1854 if (rc == 0) 1855 sc->sc_pwrstate = power; 1856 else 1857 sc->sc_pwrstate = RTW_OFF; 1858 return rc; 1859 } 1860 1861 static int 1862 rtw_tune(struct rtw_softc *sc) 1863 { 1864 struct ieee80211com *ic = &sc->sc_ic; 1865 u_int chan; 1866 int rc; 1867 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 1868 dflantb = sc->sc_flags & RTW_F_DFLANTB; 1869 1870 KASSERT(ic->ic_bss->ni_chan != NULL); 1871 1872 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1873 if (chan == IEEE80211_CHAN_ANY) 1874 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1875 1876 if (chan == sc->sc_cur_chan) { 1877 RTW_DPRINTF(("%s: already tuned chan #%d\n", __func__, chan)); 1878 return 0; 1879 } 1880 1881 rtw_suspend_ticks(sc); 1882 1883 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 1884 1885 /* TBD wait for Tx to complete */ 1886 1887 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 1888 1889 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 1890 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 1891 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 1892 dflantb, RTW_ON)) != 0) { 1893 /* XXX condition on powersaving */ 1894 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 1895 } 1896 1897 sc->sc_cur_chan = chan; 1898 1899 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 1900 1901 rtw_resume_ticks(sc); 1902 1903 return rc; 1904 } 1905 1906 void 1907 rtw_disable(struct rtw_softc *sc) 1908 { 1909 int rc; 1910 1911 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1912 return; 1913 1914 /* turn off PHY */ 1915 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 1916 printf("%s: failed to turn off PHY (%d)\n", 1917 sc->sc_dev.dv_xname, rc); 1918 1919 if (sc->sc_disable != NULL) 1920 (*sc->sc_disable)(sc); 1921 1922 sc->sc_flags &= ~RTW_F_ENABLED; 1923 } 1924 1925 int 1926 rtw_enable(struct rtw_softc *sc) 1927 { 1928 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 1929 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 1930 printf("%s: device enable failed\n", 1931 sc->sc_dev.dv_xname); 1932 return (EIO); 1933 } 1934 sc->sc_flags |= RTW_F_ENABLED; 1935 } 1936 return (0); 1937 } 1938 1939 static void 1940 rtw_transmit_config(struct rtw_regs *regs) 1941 { 1942 u_int32_t tcr; 1943 1944 tcr = RTW_READ(regs, RTW_TCR); 1945 1946 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 1947 tcr &= ~RTW_TCR_LBK_MASK; 1948 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 1949 1950 /* set short/long retry limits */ 1951 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 1952 tcr |= LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 1953 1954 tcr |= RTW_TCR_CRC; /* NIC appends CRC32 */ 1955 1956 RTW_WRITE(regs, RTW_TCR, tcr); 1957 } 1958 1959 static __inline void 1960 rtw_enable_interrupts(struct rtw_softc *sc) 1961 { 1962 struct rtw_regs *regs = &sc->sc_regs; 1963 1964 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 1965 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 1966 1967 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1968 RTW_WRITE16(regs, RTW_ISR, 0xffff); 1969 1970 /* XXX necessary? */ 1971 if (sc->sc_intr_ack != NULL) 1972 (*sc->sc_intr_ack)(regs); 1973 } 1974 1975 /* XXX is the endianness correct? test. */ 1976 #define rtw_calchash(addr) \ 1977 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1978 1979 static void 1980 rtw_pktfilt_load(struct rtw_softc *sc) 1981 { 1982 struct rtw_regs *regs = &sc->sc_regs; 1983 struct ieee80211com *ic = &sc->sc_ic; 1984 struct ethercom *ec = &ic->ic_ec; 1985 struct ifnet *ifp = &sc->sc_ic.ic_if; 1986 int hash; 1987 u_int32_t hashes[2] = { 0, 0 }; 1988 struct ether_multi *enm; 1989 struct ether_multistep step; 1990 1991 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 1992 1993 #define RTW_RCR_MONITOR (RTW_RCR_ACRC32|RTW_RCR_APM|RTW_RCR_AAP|RTW_RCR_AB) 1994 1995 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1996 sc->sc_rcr |= RTW_RCR_MONITOR; 1997 else 1998 sc->sc_rcr &= ~RTW_RCR_MONITOR; 1999 2000 /* XXX reference sources BEGIN */ 2001 sc->sc_rcr |= RTW_RCR_ENMARP | RTW_RCR_AICV | RTW_RCR_ACRC32; 2002 sc->sc_rcr |= RTW_RCR_AB | RTW_RCR_AM | RTW_RCR_APM; 2003 #if 0 2004 /* receive broadcasts in our BSS */ 2005 sc->sc_rcr |= RTW_RCR_ADD3; 2006 #endif 2007 /* XXX reference sources END */ 2008 2009 /* receive pwrmgmt frames. */ 2010 sc->sc_rcr |= RTW_RCR_APWRMGT; 2011 /* receive mgmt/ctrl/data frames. */ 2012 sc->sc_rcr |= RTW_RCR_AMF | RTW_RCR_ACF | RTW_RCR_ADF; 2013 /* initialize Rx DMA threshold, Tx DMA burst size */ 2014 sc->sc_rcr |= RTW_RCR_RXFTH_WHOLE | RTW_RCR_MXDMA_1024; 2015 2016 ifp->if_flags &= ~IFF_ALLMULTI; 2017 2018 if (ifp->if_flags & IFF_PROMISC) { 2019 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2020 allmulti: 2021 ifp->if_flags |= IFF_ALLMULTI; 2022 goto setit; 2023 } 2024 2025 /* 2026 * Program the 64-bit multicast hash filter. 2027 */ 2028 ETHER_FIRST_MULTI(step, ec, enm); 2029 while (enm != NULL) { 2030 /* XXX */ 2031 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2032 ETHER_ADDR_LEN) != 0) 2033 goto allmulti; 2034 2035 hash = rtw_calchash(enm->enm_addrlo); 2036 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2037 ETHER_NEXT_MULTI(step, enm); 2038 } 2039 2040 if (ifp->if_flags & IFF_BROADCAST) { 2041 hash = rtw_calchash(etherbroadcastaddr); 2042 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2043 } 2044 2045 /* all bits set => hash is useless */ 2046 if (~(hashes[0] & hashes[1]) == 0) 2047 goto allmulti; 2048 2049 setit: 2050 if (ifp->if_flags & IFF_ALLMULTI) 2051 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2052 2053 if (ic->ic_state == IEEE80211_S_SCAN) 2054 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2055 2056 hashes[0] = hashes[1] = 0xffffffff; 2057 2058 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2059 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2060 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2061 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2062 2063 DPRINTF(sc, ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2064 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2065 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2066 2067 return; 2068 } 2069 2070 static int 2071 rtw_init(struct ifnet *ifp) 2072 { 2073 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2074 struct ieee80211com *ic = &sc->sc_ic; 2075 struct rtw_regs *regs = &sc->sc_regs; 2076 int rc = 0; 2077 2078 if ((rc = rtw_enable(sc)) != 0) 2079 goto out; 2080 2081 /* Cancel pending I/O and reset. */ 2082 rtw_stop(ifp, 0); 2083 2084 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2085 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 2086 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2087 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2088 2089 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2090 goto out; 2091 2092 rtw_swring_setup(sc); 2093 2094 rtw_transmit_config(regs); 2095 2096 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2097 2098 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2099 2100 /* long PLCP header, 1Mbps basic rate */ 2101 RTW_WRITE16(regs, RTW_BRSR, 0x0); 2102 2103 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 2104 rtw_set_access(sc, RTW_ACCESS_NONE); 2105 2106 #if 0 2107 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_GWAKE|RTW_FEMR_WKUP|RTW_FEMR_INTR); 2108 #endif 2109 /* XXX from reference sources */ 2110 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2111 2112 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2113 2114 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2115 /* from Linux driver */ 2116 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2117 2118 rtw_enable_interrupts(sc); 2119 2120 rtw_pktfilt_load(sc); 2121 2122 rtw_hwring_setup(sc); 2123 2124 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2125 2126 ifp->if_flags |= IFF_RUNNING; 2127 ic->ic_state = IEEE80211_S_INIT; 2128 2129 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2130 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2131 2132 rtw_resume_ticks(sc); 2133 2134 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2135 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2136 2137 switch (ic->ic_opmode) { 2138 case IEEE80211_M_AHDEMO: 2139 case IEEE80211_M_IBSS: 2140 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_ADHOC_OK); 2141 break; 2142 case IEEE80211_M_HOSTAP: 2143 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_AP_OK); 2144 break; 2145 case IEEE80211_M_MONITOR: 2146 /* XXX */ 2147 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_NOLINK); 2148 break; 2149 case IEEE80211_M_STA: 2150 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_INFRA_OK); 2151 break; 2152 } 2153 2154 rtw_set_access(sc, RTW_ACCESS_NONE); 2155 2156 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2157 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2158 else 2159 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2160 2161 out: 2162 return rc; 2163 } 2164 2165 static int 2166 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2167 { 2168 int rc = 0; 2169 struct rtw_softc *sc = ifp->if_softc; 2170 struct ifreq *ifr = (struct ifreq *)data; 2171 2172 switch (cmd) { 2173 case SIOCSIFFLAGS: 2174 if ((ifp->if_flags & IFF_UP) != 0) { 2175 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2176 rtw_pktfilt_load(sc); 2177 } else 2178 rc = rtw_init(ifp); 2179 #ifdef RTW_DEBUG 2180 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2181 #endif /* RTW_DEBUG */ 2182 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2183 #ifdef RTW_DEBUG 2184 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2185 #endif /* RTW_DEBUG */ 2186 rtw_stop(ifp, 1); 2187 } 2188 break; 2189 case SIOCADDMULTI: 2190 case SIOCDELMULTI: 2191 if (cmd == SIOCADDMULTI) 2192 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2193 else 2194 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2195 if (rc == ENETRESET) { 2196 if (ifp->if_flags & IFF_RUNNING) 2197 rtw_pktfilt_load(sc); 2198 rc = 0; 2199 } 2200 break; 2201 default: 2202 if ((rc = ieee80211_ioctl(ifp, cmd, data)) == ENETRESET) { 2203 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2204 rc = rtw_init(ifp); 2205 else 2206 rc = 0; 2207 } 2208 break; 2209 } 2210 return rc; 2211 } 2212 2213 /* Point *mp at the next 802.11 frame to transmit. Point *stcp 2214 * at the driver's selection of transmit control block for the packet. 2215 */ 2216 static __inline int 2217 rtw_dequeue(struct ifnet *ifp, struct rtw_txctl_blk **stcp, 2218 struct rtw_txdesc_blk **htcp, struct mbuf **mp, 2219 struct ieee80211_node **nip) 2220 { 2221 struct rtw_txctl_blk *stc; 2222 struct rtw_txdesc_blk *htc; 2223 struct mbuf *m0; 2224 struct rtw_softc *sc; 2225 struct ieee80211com *ic; 2226 2227 sc = (struct rtw_softc *)ifp->if_softc; 2228 2229 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2230 *mp = NULL; 2231 2232 stc = &sc->sc_txctl_blk[RTW_TXPRIMD]; 2233 htc = &sc->sc_txdesc_blk[RTW_TXPRIMD]; 2234 2235 if (SIMPLEQ_EMPTY(&stc->stc_freeq) || htc->htc_nfree == 0) { 2236 DPRINTF2(sc, ("%s: out of descriptors\n", __func__)); 2237 ifp->if_flags |= IFF_OACTIVE; 2238 return 0; 2239 } 2240 2241 ic = &sc->sc_ic; 2242 2243 if (!IF_IS_EMPTY(&ic->ic_mgtq)) { 2244 IF_DEQUEUE(&ic->ic_mgtq, m0); 2245 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2246 m0->m_pkthdr.rcvif = NULL; 2247 DPRINTF2(sc, ("%s: dequeue mgt frame\n", __func__)); 2248 } else if (ic->ic_state != IEEE80211_S_RUN) { 2249 DPRINTF2(sc, ("%s: not running\n", __func__)); 2250 return 0; 2251 } else if (!IF_IS_EMPTY(&ic->ic_pwrsaveq)) { 2252 IF_DEQUEUE(&ic->ic_pwrsaveq, m0); 2253 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2254 m0->m_pkthdr.rcvif = NULL; 2255 DPRINTF2(sc, ("%s: dequeue pwrsave frame\n", __func__)); 2256 } else { 2257 IFQ_POLL(&ifp->if_snd, m0); 2258 if (m0 == NULL) { 2259 DPRINTF2(sc, ("%s: no frame\n", __func__)); 2260 return 0; 2261 } 2262 DPRINTF2(sc, ("%s: dequeue data frame\n", __func__)); 2263 IFQ_DEQUEUE(&ifp->if_snd, m0); 2264 ifp->if_opackets++; 2265 #if NBPFILTER > 0 2266 if (ifp->if_bpf) 2267 bpf_mtap(ifp->if_bpf, m0); 2268 #endif 2269 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2270 DPRINTF2(sc, ("%s: encap error\n", __func__)); 2271 ifp->if_oerrors++; 2272 return -1; 2273 } 2274 } 2275 DPRINTF2(sc, ("%s: leave\n", __func__)); 2276 *stcp = stc; 2277 *htcp = htc; 2278 *mp = m0; 2279 return 0; 2280 } 2281 2282 /* TBD factor with atw_start */ 2283 static struct mbuf * 2284 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2285 u_int ndescfree, short *ifflagsp, const char *dvname) 2286 { 2287 int first, rc; 2288 struct mbuf *m, *m0; 2289 2290 m0 = chain; 2291 2292 /* 2293 * Load the DMA map. Copy and try (once) again if the packet 2294 * didn't fit in the alloted number of segments. 2295 */ 2296 for (first = 1; 2297 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2298 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2299 dmam->dm_nsegs > ndescfree) && first; 2300 first = 0) { 2301 if (rc == 0) 2302 bus_dmamap_unload(dmat, dmam); 2303 MGETHDR(m, M_DONTWAIT, MT_DATA); 2304 if (m == NULL) { 2305 printf("%s: unable to allocate Tx mbuf\n", 2306 dvname); 2307 break; 2308 } 2309 if (m0->m_pkthdr.len > MHLEN) { 2310 MCLGET(m, M_DONTWAIT); 2311 if ((m->m_flags & M_EXT) == 0) { 2312 printf("%s: cannot allocate Tx cluster\n", 2313 dvname); 2314 m_freem(m); 2315 break; 2316 } 2317 } 2318 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2319 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 2320 m_freem(m0); 2321 m0 = m; 2322 m = NULL; 2323 } 2324 if (rc != 0) { 2325 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 2326 m_freem(m0); 2327 return NULL; 2328 } else if (dmam->dm_nsegs > ndescfree) { 2329 *ifflagsp |= IFF_OACTIVE; 2330 bus_dmamap_unload(dmat, dmam); 2331 m_freem(m0); 2332 return NULL; 2333 } 2334 return m0; 2335 } 2336 2337 static void 2338 rtw_start(struct ifnet *ifp) 2339 { 2340 int desc, i, lastdesc, npkt, rate; 2341 uint32_t proto_txctl0, txctl0, txctl1; 2342 bus_dmamap_t dmamap; 2343 struct ieee80211com *ic; 2344 struct ieee80211_duration *d0; 2345 struct ieee80211_frame *wh; 2346 struct ieee80211_node *ni; 2347 struct mbuf *m0; 2348 struct rtw_softc *sc; 2349 struct rtw_txctl_blk *stc; 2350 struct rtw_txdesc_blk *htc; 2351 struct rtw_txctl *stx; 2352 struct rtw_txdesc *htx; 2353 2354 sc = (struct rtw_softc *)ifp->if_softc; 2355 ic = &sc->sc_ic; 2356 2357 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2358 2359 /* XXX do real rate control */ 2360 proto_txctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 2361 2362 switch (rate = MAX(2, ieee80211_get_rate(ic))) { 2363 case 2: 2364 proto_txctl0 |= RTW_TXCTL0_RATE_1MBPS; 2365 break; 2366 case 4: 2367 proto_txctl0 |= RTW_TXCTL0_RATE_2MBPS; 2368 break; 2369 case 11: 2370 proto_txctl0 |= RTW_TXCTL0_RATE_5MBPS; 2371 break; 2372 case 22: 2373 proto_txctl0 |= RTW_TXCTL0_RATE_11MBPS; 2374 break; 2375 } 2376 2377 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 2378 proto_txctl0 |= RTW_TXCTL0_SPLCP; 2379 2380 for (;;) { 2381 if (rtw_dequeue(ifp, &stc, &htc, &m0, &ni) == -1) 2382 continue; 2383 if (m0 == NULL) 2384 break; 2385 stx = SIMPLEQ_FIRST(&stc->stc_freeq); 2386 2387 dmamap = stx->stx_dmamap; 2388 2389 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 2390 htc->htc_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 2391 2392 if (m0 == NULL || dmamap->dm_nsegs == 0) { 2393 DPRINTF2(sc, ("%s: fail dmamap load\n", __func__)); 2394 goto post_dequeue_err; 2395 } 2396 2397 txctl0 = proto_txctl0 | 2398 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 2399 2400 wh = mtod(m0, struct ieee80211_frame *); 2401 2402 if (ieee80211_compute_duration(wh, 2403 m0->m_pkthdr.len - sizeof(wh), 2404 ic->ic_flags, ic->ic_fragthreshold, 2405 rate, &stx->stx_d0, &stx->stx_dn, &npkt) == -1) { 2406 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 2407 goto post_load_err; 2408 } 2409 2410 /* XXX >= ? */ 2411 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 2412 txctl0 |= RTW_TXCTL0_RTSEN; 2413 2414 d0 = &stx->stx_d0; 2415 2416 txctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 2417 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 2418 2419 if ((d0->d_plcp_svc & IEEE80211_PLCP_SERVICE_LENEXT) != 0) 2420 txctl1 |= RTW_TXCTL1_LENGEXT; 2421 2422 /* TBD fragmentation */ 2423 2424 stx->stx_first = htc->htc_next; 2425 2426 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2427 htc, stx->stx_first, dmamap->dm_nsegs, 2428 BUS_DMASYNC_PREWRITE); 2429 2430 for (i = 0, lastdesc = desc = stx->stx_first; 2431 i < dmamap->dm_nsegs; 2432 i++, desc = RTW_NEXT_IDX(htc, desc)) { 2433 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 2434 DPRINTF2(sc, ("%s: seg too long\n", __func__)); 2435 goto post_load_err; 2436 } 2437 htx = &htc->htc_desc[desc]; 2438 htx->htx_ctl0 = htole32(txctl0); 2439 if (i != 0) 2440 htx->htx_ctl0 |= htole32(RTW_TXCTL0_OWN); 2441 htx->htx_ctl1 = htole32(txctl1); 2442 htx->htx_buf = htole32(dmamap->dm_segs[i].ds_addr); 2443 htx->htx_len = htole32(dmamap->dm_segs[i].ds_len); 2444 lastdesc = desc; 2445 DPRINTF2(sc, ("%s: stx %p txdesc[%d] ctl0 %#08x " 2446 "ctl1 %#08x buf %#08x len %#08x\n", 2447 sc->sc_dev.dv_xname, stx, desc, htx->htx_ctl0, 2448 htx->htx_ctl1, htx->htx_buf, htx->htx_len)); 2449 } 2450 2451 htc->htc_desc[lastdesc].htx_ctl0 |= htole32(RTW_TXCTL0_LS); 2452 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2453 htole32(RTW_TXCTL0_FS); 2454 2455 DPRINTF2(sc, ("%s: stx %p FS on txdesc[%d], LS on txdesc[%d]\n", 2456 sc->sc_dev.dv_xname, stx, lastdesc, stx->stx_first)); 2457 2458 stx->stx_ni = ni; 2459 stx->stx_mbuf = m0; 2460 stx->stx_last = lastdesc; 2461 2462 htc->htc_nfree -= dmamap->dm_nsegs; 2463 htc->htc_next = desc; 2464 2465 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2466 htc, stx->stx_first, dmamap->dm_nsegs, 2467 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2468 2469 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2470 htole32(RTW_TXCTL0_OWN); 2471 2472 DPRINTF2(sc, ("%s: stx %p OWN on txdesc[%d]\n", 2473 sc->sc_dev.dv_xname, stx, stx->stx_first)); 2474 2475 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2476 htc, stx->stx_first, 1, 2477 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2478 2479 SIMPLEQ_REMOVE_HEAD(&stc->stc_freeq, stx_q); 2480 SIMPLEQ_INSERT_TAIL(&stc->stc_dirtyq, stx, stx_q); 2481 2482 stc->stc_tx_timer = 5; 2483 ifp->if_timer = 1; 2484 2485 /* TBD poke just one txmtr? */ 2486 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, 2487 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ | RTW_TPPOLL_HPQ | 2488 RTW_TPPOLL_BQ); 2489 } 2490 DPRINTF2(sc, ("%s: leave\n", __func__)); 2491 return; 2492 post_load_err: 2493 bus_dmamap_unload(sc->sc_dmat, dmamap); 2494 m_freem(m0); 2495 post_dequeue_err: 2496 ieee80211_release_node(&sc->sc_ic, ni); 2497 return; 2498 } 2499 2500 static void 2501 rtw_watchdog(struct ifnet *ifp) 2502 { 2503 int pri; 2504 struct rtw_softc *sc; 2505 struct rtw_txctl_blk *stc; 2506 2507 sc = ifp->if_softc; 2508 2509 ifp->if_timer = 0; 2510 2511 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2512 return; 2513 2514 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2515 stc = &sc->sc_txctl_blk[pri]; 2516 2517 if (stc->stc_tx_timer == 0) 2518 continue; 2519 2520 if (--stc->stc_tx_timer == 0) { 2521 if (SIMPLEQ_EMPTY(&stc->stc_dirtyq)) 2522 continue; 2523 printf("%s: transmit timeout, priority %d\n", 2524 ifp->if_xname, pri); 2525 ifp->if_oerrors++; 2526 /* XXX be gentle */ 2527 (void)rtw_init(ifp); 2528 rtw_start(ifp); 2529 } else 2530 ifp->if_timer = 1; 2531 } 2532 /* TBD */ 2533 return; 2534 } 2535 2536 static void 2537 rtw_start_beacon(struct rtw_softc *sc, int enable) 2538 { 2539 /* TBD */ 2540 return; 2541 } 2542 2543 static void 2544 rtw_next_scan(void *arg) 2545 { 2546 struct ieee80211com *ic = arg; 2547 int s; 2548 2549 /* don't call rtw_start w/o network interrupts blocked */ 2550 s = splnet(); 2551 if (ic->ic_state == IEEE80211_S_SCAN) 2552 ieee80211_next_scan(ic); 2553 splx(s); 2554 } 2555 2556 /* Synchronize the hardware state with the software state. */ 2557 static int 2558 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2559 { 2560 struct ifnet *ifp = &ic->ic_if; 2561 struct rtw_softc *sc = ifp->if_softc; 2562 enum ieee80211_state ostate; 2563 int error; 2564 2565 ostate = ic->ic_state; 2566 2567 if (nstate == IEEE80211_S_INIT) { 2568 callout_stop(&sc->sc_scan_ch); 2569 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2570 rtw_start_beacon(sc, 0); 2571 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2572 } 2573 2574 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 2575 rtw_pwrstate(sc, RTW_ON); 2576 2577 if ((error = rtw_tune(sc)) != 0) 2578 return error; 2579 2580 switch (nstate) { 2581 case IEEE80211_S_ASSOC: 2582 break; 2583 case IEEE80211_S_INIT: 2584 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2585 break; 2586 case IEEE80211_S_SCAN: 2587 #if 0 2588 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2589 rtw_write_bssid(sc); 2590 #endif 2591 2592 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 2593 rtw_next_scan, ic); 2594 2595 break; 2596 case IEEE80211_S_RUN: 2597 if (ic->ic_opmode == IEEE80211_M_STA) 2598 break; 2599 /*FALLTHROUGH*/ 2600 case IEEE80211_S_AUTH: 2601 #if 0 2602 rtw_write_bssid(sc); 2603 rtw_write_bcn_thresh(sc); 2604 rtw_write_ssid(sc); 2605 rtw_write_sup_rates(sc); 2606 #endif 2607 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2608 ic->ic_opmode == IEEE80211_M_MONITOR) 2609 break; 2610 2611 /* TBD set listen interval, beacon interval */ 2612 2613 #if 0 2614 rtw_tsf(sc); 2615 #endif 2616 break; 2617 } 2618 2619 if (nstate != IEEE80211_S_SCAN) 2620 callout_stop(&sc->sc_scan_ch); 2621 2622 if (nstate == IEEE80211_S_RUN && 2623 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2624 ic->ic_opmode == IEEE80211_M_IBSS)) 2625 rtw_start_beacon(sc, 1); 2626 else 2627 rtw_start_beacon(sc, 0); 2628 2629 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2630 } 2631 2632 static void 2633 rtw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2634 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2635 { 2636 /* TBD */ 2637 return; 2638 } 2639 2640 static void 2641 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2642 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2643 { 2644 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 2645 2646 switch (subtype) { 2647 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2648 /* do nothing: hardware answers probe request XXX */ 2649 break; 2650 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2651 case IEEE80211_FC0_SUBTYPE_BEACON: 2652 rtw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2653 break; 2654 default: 2655 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2656 break; 2657 } 2658 return; 2659 } 2660 2661 static struct ieee80211_node * 2662 rtw_node_alloc(struct ieee80211com *ic) 2663 { 2664 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2665 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 2666 2667 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 2668 return ni; 2669 } 2670 2671 static void 2672 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 2673 { 2674 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2675 2676 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 2677 ether_sprintf(ni->ni_bssid))); 2678 (*sc->sc_mtbl.mt_node_free)(ic, ni); 2679 } 2680 2681 static int 2682 rtw_media_change(struct ifnet *ifp) 2683 { 2684 int error; 2685 2686 error = ieee80211_media_change(ifp); 2687 if (error == ENETRESET) { 2688 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 2689 (IFF_RUNNING|IFF_UP)) 2690 rtw_init(ifp); /* XXX lose error */ 2691 error = 0; 2692 } 2693 return error; 2694 } 2695 2696 static void 2697 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 2698 { 2699 struct rtw_softc *sc = ifp->if_softc; 2700 2701 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2702 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 2703 imr->ifm_status = 0; 2704 return; 2705 } 2706 ieee80211_media_status(ifp, imr); 2707 } 2708 2709 void 2710 rtw_power(int why, void *arg) 2711 { 2712 struct rtw_softc *sc = arg; 2713 struct ifnet *ifp = &sc->sc_ic.ic_if; 2714 int s; 2715 2716 DPRINTF(sc, ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 2717 2718 s = splnet(); 2719 switch (why) { 2720 case PWR_STANDBY: 2721 /* XXX do nothing. */ 2722 break; 2723 case PWR_SUSPEND: 2724 rtw_stop(ifp, 0); 2725 if (sc->sc_power != NULL) 2726 (*sc->sc_power)(sc, why); 2727 break; 2728 case PWR_RESUME: 2729 if (ifp->if_flags & IFF_UP) { 2730 if (sc->sc_power != NULL) 2731 (*sc->sc_power)(sc, why); 2732 rtw_init(ifp); 2733 } 2734 break; 2735 case PWR_SOFTSUSPEND: 2736 case PWR_SOFTSTANDBY: 2737 case PWR_SOFTRESUME: 2738 break; 2739 } 2740 splx(s); 2741 } 2742 2743 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 2744 void 2745 rtw_shutdown(void *arg) 2746 { 2747 struct rtw_softc *sc = arg; 2748 2749 rtw_stop(&sc->sc_ic.ic_if, 1); 2750 } 2751 2752 static __inline void 2753 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 2754 { 2755 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 2756 ifp->if_softc = softc; 2757 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 2758 IFF_NOTRAILERS; 2759 ifp->if_ioctl = rtw_ioctl; 2760 ifp->if_start = rtw_start; 2761 ifp->if_watchdog = rtw_watchdog; 2762 ifp->if_init = rtw_init; 2763 ifp->if_stop = rtw_stop; 2764 } 2765 2766 static __inline void 2767 rtw_set80211props(struct ieee80211com *ic) 2768 { 2769 int nrate; 2770 ic->ic_phytype = IEEE80211_T_DS; 2771 ic->ic_opmode = IEEE80211_M_STA; 2772 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 2773 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 2774 2775 nrate = 0; 2776 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 2777 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 2778 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 2779 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 2780 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 2781 } 2782 2783 static __inline void 2784 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 2785 { 2786 mtbl->mt_newstate = ic->ic_newstate; 2787 ic->ic_newstate = rtw_newstate; 2788 2789 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 2790 ic->ic_recv_mgmt = rtw_recv_mgmt; 2791 2792 mtbl->mt_node_free = ic->ic_node_free; 2793 ic->ic_node_free = rtw_node_free; 2794 2795 mtbl->mt_node_alloc = ic->ic_node_alloc; 2796 ic->ic_node_alloc = rtw_node_alloc; 2797 } 2798 2799 static __inline void 2800 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 2801 void *arg) 2802 { 2803 /* 2804 * Make sure the interface is shutdown during reboot. 2805 */ 2806 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 2807 if (hooks->rh_shutdown == NULL) 2808 printf("%s: WARNING: unable to establish shutdown hook\n", 2809 dvname); 2810 2811 /* 2812 * Add a suspend hook to make sure we come back up after a 2813 * resume. 2814 */ 2815 hooks->rh_power = powerhook_establish(rtw_power, arg); 2816 if (hooks->rh_power == NULL) 2817 printf("%s: WARNING: unable to establish power hook\n", 2818 dvname); 2819 } 2820 2821 static __inline void 2822 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 2823 void *arg) 2824 { 2825 if (hooks->rh_shutdown != NULL) 2826 shutdownhook_disestablish(hooks->rh_shutdown); 2827 2828 if (hooks->rh_power != NULL) 2829 powerhook_disestablish(hooks->rh_power); 2830 } 2831 2832 static __inline void 2833 rtw_init_radiotap(struct rtw_softc *sc) 2834 { 2835 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 2836 sc->sc_rxtap.rr_ihdr.it_len = sizeof(sc->sc_rxtapu); 2837 sc->sc_rxtap.rr_ihdr.it_present = RTW_RX_RADIOTAP_PRESENT; 2838 2839 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 2840 sc->sc_txtap.rt_ihdr.it_len = sizeof(sc->sc_txtapu); 2841 sc->sc_txtap.rt_ihdr.it_present = RTW_TX_RADIOTAP_PRESENT; 2842 } 2843 2844 static int 2845 rtw_txctl_blk_setup(struct rtw_txctl_blk *stc, u_int qlen) 2846 { 2847 SIMPLEQ_INIT(&stc->stc_dirtyq); 2848 SIMPLEQ_INIT(&stc->stc_freeq); 2849 stc->stc_ndesc = qlen; 2850 stc->stc_desc = malloc(qlen * sizeof(*stc->stc_desc), M_DEVBUF, 2851 M_NOWAIT); 2852 if (stc->stc_desc == NULL) 2853 return ENOMEM; 2854 return 0; 2855 } 2856 2857 static void 2858 rtw_txctl_blk_cleanup_all(struct rtw_softc *sc) 2859 { 2860 struct rtw_txctl_blk *stc; 2861 int qlen[RTW_NTXPRI] = 2862 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2863 int pri; 2864 2865 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2866 stc = &sc->sc_txctl_blk[pri]; 2867 free(stc->stc_desc, M_DEVBUF); 2868 stc->stc_desc = NULL; 2869 } 2870 } 2871 2872 static int 2873 rtw_txctl_blk_setup_all(struct rtw_softc *sc) 2874 { 2875 int pri, rc = 0; 2876 int qlen[RTW_NTXPRI] = 2877 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2878 2879 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2880 rc = rtw_txctl_blk_setup(&sc->sc_txctl_blk[pri], qlen[pri]); 2881 if (rc != 0) 2882 break; 2883 } 2884 return rc; 2885 } 2886 2887 static void 2888 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *htc, struct rtw_txdesc *desc, 2889 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 2890 { 2891 int i; 2892 2893 htc->htc_ndesc = ndesc; 2894 htc->htc_desc = desc; 2895 htc->htc_physbase = physbase; 2896 htc->htc_ofs = ofs; 2897 2898 (void)memset(htc->htc_desc, 0, 2899 sizeof(htc->htc_desc[0]) * htc->htc_ndesc); 2900 2901 for (i = 0; i < htc->htc_ndesc; i++) { 2902 htc->htc_desc[i].htx_next = htole32(RTW_NEXT_DESC(htc, i)); 2903 } 2904 } 2905 2906 static void 2907 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 2908 { 2909 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 2910 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 2911 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 2912 2913 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 2914 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 2915 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 2916 2917 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 2918 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 2919 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 2920 2921 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 2922 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 2923 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 2924 } 2925 2926 static struct rtw_rf * 2927 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, 2928 rtw_rf_write_t rf_write, int digphy) 2929 { 2930 struct rtw_rf *rf; 2931 2932 switch (rfchipid) { 2933 case RTW_RFCHIPID_MAXIM: 2934 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 2935 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 2936 break; 2937 case RTW_RFCHIPID_PHILIPS: 2938 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 2939 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 2940 break; 2941 default: 2942 return NULL; 2943 } 2944 rf->rf_continuous_tx_cb = 2945 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 2946 rf->rf_continuous_tx_arg = (void *)sc; 2947 return rf; 2948 } 2949 2950 /* Revision C and later use a different PHY delay setting than 2951 * revisions A and B. 2952 */ 2953 static u_int8_t 2954 rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0) 2955 { 2956 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 2957 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 2958 2959 u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 2960 2961 RTW_WRITE(regs, RTW_RCR, REVAB); 2962 RTW_WRITE(regs, RTW_RCR, REVC); 2963 2964 RTW_WBR(regs, RTW_RCR, RTW_RCR); 2965 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 2966 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 2967 2968 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 2969 2970 return phydelay; 2971 #undef REVC 2972 } 2973 2974 void 2975 rtw_attach(struct rtw_softc *sc) 2976 { 2977 rtw_rf_write_t rf_write; 2978 struct rtw_txctl_blk *stc; 2979 int pri, rc, vers; 2980 2981 #if 0 2982 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_txdesc) == 0, 2983 "RTW_DESC_ALIGNMENT is not a multiple of " 2984 "sizeof(struct rtw_txdesc)"); 2985 2986 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_rxdesc) == 0, 2987 "RTW_DESC_ALIGNMENT is not a multiple of " 2988 "sizeof(struct rtw_rxdesc)"); 2989 2990 CASSERT(RTW_DESC_ALIGNMENT % RTW_MAXPKTSEGS == 0, 2991 "RTW_DESC_ALIGNMENT is not a multiple of RTW_MAXPKTSEGS"); 2992 #endif 2993 2994 NEXT_ATTACH_STATE(sc, DETACHED); 2995 2996 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 2997 case RTW_TCR_HWVERID_F: 2998 vers = 'F'; 2999 rf_write = rtw_rf_hostwrite; 3000 break; 3001 case RTW_TCR_HWVERID_D: 3002 vers = 'D'; 3003 if (rtw_host_rfio) 3004 rf_write = rtw_rf_hostwrite; 3005 else 3006 rf_write = rtw_rf_macwrite; 3007 break; 3008 default: 3009 vers = '?'; 3010 rf_write = rtw_rf_macwrite; 3011 break; 3012 } 3013 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, vers); 3014 3015 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3016 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3017 0); 3018 3019 if (rc != 0) { 3020 printf("%s: could not allocate hw descriptors, error %d\n", 3021 sc->sc_dev.dv_xname, rc); 3022 goto err; 3023 } 3024 3025 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3026 3027 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3028 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3029 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3030 3031 if (rc != 0) { 3032 printf("%s: could not map hw descriptors, error %d\n", 3033 sc->sc_dev.dv_xname, rc); 3034 goto err; 3035 } 3036 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3037 3038 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3039 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3040 3041 if (rc != 0) { 3042 printf("%s: could not create DMA map for hw descriptors, " 3043 "error %d\n", sc->sc_dev.dv_xname, rc); 3044 goto err; 3045 } 3046 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3047 3048 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3049 sizeof(struct rtw_descs), NULL, 0); 3050 3051 if (rc != 0) { 3052 printf("%s: could not load DMA map for hw descriptors, " 3053 "error %d\n", sc->sc_dev.dv_xname, rc); 3054 goto err; 3055 } 3056 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3057 3058 if (rtw_txctl_blk_setup_all(sc) != 0) 3059 goto err; 3060 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3061 3062 rtw_txdesc_blk_setup_all(sc); 3063 3064 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3065 3066 sc->sc_rxdesc = &sc->sc_descs->hd_rx[0]; 3067 3068 rtw_rxctls_setup(&sc->sc_rxctl[0]); 3069 3070 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3071 stc = &sc->sc_txctl_blk[pri]; 3072 3073 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3074 &stc->stc_desc[0], stc->stc_ndesc)) != 0) { 3075 printf("%s: could not load DMA map for " 3076 "hw tx descriptors, error %d\n", 3077 sc->sc_dev.dv_xname, rc); 3078 goto err; 3079 } 3080 } 3081 3082 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3083 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxctl[0], 3084 RTW_RXQLEN)) != 0) { 3085 printf("%s: could not load DMA map for hw rx descriptors, " 3086 "error %d\n", sc->sc_dev.dv_xname, rc); 3087 goto err; 3088 } 3089 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3090 3091 /* Reset the chip to a known state. */ 3092 if (rtw_reset(sc) != 0) 3093 goto err; 3094 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3095 3096 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3097 3098 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3099 sc->sc_flags |= RTW_F_9356SROM; 3100 3101 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3102 sc->sc_dev.dv_xname) != 0) 3103 goto err; 3104 3105 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3106 3107 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3108 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3109 sc->sc_dev.dv_xname) != 0) { 3110 printf("%s: attach failed, malformed serial ROM\n", 3111 sc->sc_dev.dv_xname); 3112 goto err; 3113 } 3114 3115 RTW_DPRINTF(("%s: CS threshold %u\n", sc->sc_dev.dv_xname, 3116 sc->sc_csthr)); 3117 3118 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3119 3120 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, rf_write, 3121 sc->sc_flags & RTW_F_DIGPHY); 3122 3123 if (sc->sc_rf == NULL) { 3124 printf("%s: attach failed, could not attach RF\n", 3125 sc->sc_dev.dv_xname); 3126 goto err; 3127 } 3128 3129 #if 0 3130 if (rtw_identify_rf(&sc->sc_regs, &sc->sc_rftype, 3131 sc->sc_dev.dv_xname) != 0) { 3132 printf("%s: attach failed, unknown RF unidentified\n", 3133 sc->sc_dev.dv_xname); 3134 goto err; 3135 } 3136 #endif 3137 3138 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3139 3140 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 3141 3142 RTW_DPRINTF(("%s: PHY delay %d\n", sc->sc_dev.dv_xname, 3143 sc->sc_phydelay)); 3144 3145 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 3146 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 3147 sc->sc_dev.dv_xname); 3148 3149 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 3150 sc->sc_dev.dv_xname); 3151 3152 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 3153 sc->sc_dev.dv_xname) != 0) 3154 goto err; 3155 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 3156 3157 rtw_setifprops(&sc->sc_if, sc->sc_dev.dv_xname, (void*)sc); 3158 3159 IFQ_SET_READY(&sc->sc_if.if_snd); 3160 3161 rtw_set80211props(&sc->sc_ic); 3162 3163 /* 3164 * Call MI attach routines. 3165 */ 3166 if_attach(&sc->sc_if); 3167 ieee80211_ifattach(&sc->sc_if); 3168 3169 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 3170 3171 /* possibly we should fill in our own sc_send_prresp, since 3172 * the RTL8180 is probably sending probe responses in ad hoc 3173 * mode. 3174 */ 3175 3176 /* complete initialization */ 3177 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 3178 callout_init(&sc->sc_scan_ch); 3179 3180 #if NBPFILTER > 0 3181 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 3182 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 3183 #endif 3184 3185 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 3186 3187 rtw_init_radiotap(sc); 3188 3189 NEXT_ATTACH_STATE(sc, FINISHED); 3190 3191 return; 3192 err: 3193 rtw_detach(sc); 3194 return; 3195 } 3196 3197 int 3198 rtw_detach(struct rtw_softc *sc) 3199 { 3200 int pri; 3201 3202 switch (sc->sc_attach_state) { 3203 case FINISHED: 3204 rtw_stop(&sc->sc_if, 1); 3205 3206 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 3207 (void*)sc); 3208 callout_stop(&sc->sc_scan_ch); 3209 ieee80211_ifdetach(&sc->sc_if); 3210 if_detach(&sc->sc_if); 3211 break; 3212 case FINISH_ID_STA: 3213 case FINISH_RF_ATTACH: 3214 rtw_rf_destroy(sc->sc_rf); 3215 sc->sc_rf = NULL; 3216 /*FALLTHROUGH*/ 3217 case FINISH_PARSE_SROM: 3218 case FINISH_READ_SROM: 3219 rtw_srom_free(&sc->sc_srom); 3220 /*FALLTHROUGH*/ 3221 case FINISH_RESET: 3222 case FINISH_RXMAPS_CREATE: 3223 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxctl[0], 3224 RTW_RXQLEN); 3225 /*FALLTHROUGH*/ 3226 case FINISH_TXMAPS_CREATE: 3227 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3228 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 3229 sc->sc_txctl_blk[pri].stc_desc, 3230 sc->sc_txctl_blk[pri].stc_ndesc); 3231 } 3232 /*FALLTHROUGH*/ 3233 case FINISH_TXDESCBLK_SETUP: 3234 case FINISH_TXCTLBLK_SETUP: 3235 rtw_txctl_blk_cleanup_all(sc); 3236 /*FALLTHROUGH*/ 3237 case FINISH_DESCMAP_LOAD: 3238 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 3239 /*FALLTHROUGH*/ 3240 case FINISH_DESCMAP_CREATE: 3241 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 3242 /*FALLTHROUGH*/ 3243 case FINISH_DESC_MAP: 3244 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 3245 sizeof(struct rtw_descs)); 3246 /*FALLTHROUGH*/ 3247 case FINISH_DESC_ALLOC: 3248 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 3249 sc->sc_desc_nsegs); 3250 /*FALLTHROUGH*/ 3251 case DETACHED: 3252 NEXT_ATTACH_STATE(sc, DETACHED); 3253 break; 3254 } 3255 return 0; 3256 } 3257 3258 int 3259 rtw_activate(struct device *self, enum devact act) 3260 { 3261 struct rtw_softc *sc = (struct rtw_softc *)self; 3262 int rc = 0, s; 3263 3264 s = splnet(); 3265 switch (act) { 3266 case DVACT_ACTIVATE: 3267 rc = EOPNOTSUPP; 3268 break; 3269 3270 case DVACT_DEACTIVATE: 3271 if_deactivate(&sc->sc_ic.ic_if); 3272 break; 3273 } 3274 splx(s); 3275 return rc; 3276 } 3277
Indexes created Thu Sep 25 16:09:42 GMT 2025