rtw.c revision 1.82
1 /* $NetBSD: rtw.c,v 1.82 2007/01/06 06:07:55 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.82 2007/01/06 06:07:55 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/time.h> 49 #include <sys/types.h> 50 51 #include <machine/endian.h> 52 #include <machine/bus.h> 53 #include <machine/intr.h> /* splnet */ 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <dev/ic/rtwreg.h> 70 #include <dev/ic/rtwvar.h> 71 #include <dev/ic/rtwphyio.h> 72 #include <dev/ic/rtwphy.h> 73 74 #include <dev/ic/smc93cx6var.h> 75 76 #define KASSERT2(__cond, __msg) \ 77 do { \ 78 if (!(__cond)) \ 79 panic __msg ; \ 80 } while (0) 81 82 static int rtw_rfprog_fallback = 0; 83 static int rtw_host_rfio = 0; 84 85 #ifdef RTW_DEBUG 86 int rtw_debug = 0; 87 static int rtw_rxbufs_limit = RTW_RXQLEN; 88 #endif /* RTW_DEBUG */ 89 90 #define NEXT_ATTACH_STATE(sc, state) do { \ 91 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 92 ("%s: attach state %s\n", __func__, #state)); \ 93 sc->sc_attach_state = state; \ 94 } while (0) 95 96 static int rtw_xmtr_restart = 0; 97 static int rtw_do_chip_reset = 0; 98 static int rtw_ring_reset = 0; 99 100 int rtw_dwelltime = 200; /* milliseconds */ 101 static struct ieee80211_cipher rtw_cipher_wep; 102 103 static void rtw_start(struct ifnet *); 104 static void rtw_reset_oactive(struct rtw_softc *); 105 static struct mbuf *rtw_beacon_alloc(struct rtw_softc *, 106 struct ieee80211_node *); 107 static u_int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *); 108 109 static void rtw_io_enable(struct rtw_regs *, uint8_t, int); 110 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 111 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 112 const u_int8_t[IEEE80211_ADDR_LEN]); 113 static void rtw_key_update_end(struct ieee80211com *); 114 static void rtw_key_update_begin(struct ieee80211com *); 115 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 116 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 117 118 static void rtw_led_attach(struct rtw_led_state *, void *); 119 static void rtw_led_init(struct rtw_regs *); 120 static void rtw_led_slowblink(void *); 121 static void rtw_led_fastblink(void *); 122 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 123 124 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 125 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 126 #ifdef RTW_DEBUG 127 static void rtw_print_txdesc(struct rtw_softc *, const char *, 128 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 129 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 130 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 131 #endif /* RTW_DEBUG */ 132 133 /* 134 * Setup sysctl(3) MIB, hw.rtw.* 135 * 136 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 137 */ 138 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 139 { 140 int rc; 141 const struct sysctlnode *cnode, *rnode; 142 143 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 144 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 145 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 146 goto err; 147 148 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 149 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 150 "Realtek RTL818x 802.11 controls", 151 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 152 goto err; 153 154 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 155 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 156 "chip_reset", SYSCTL_DESCR("Gratuitously reset chip on rcvr error"), 157 NULL, 0, &rtw_do_chip_reset, 0, 158 CTL_CREATE, CTL_EOL)) != 0) 159 goto err; 160 161 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 162 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 163 "ring_reset", SYSCTL_DESCR("Reset ring pointers on rcvr error"), 164 NULL, 0, &rtw_ring_reset, 0, 165 CTL_CREATE, CTL_EOL)) != 0) 166 goto err; 167 168 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 169 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 170 "xmtr_restart", 171 SYSCTL_DESCR("Gratuitously reset xmtr on rcvr error"), 172 NULL, 0, &rtw_xmtr_restart, 0, 173 CTL_CREATE, CTL_EOL)) != 0) 174 goto err; 175 176 #ifdef RTW_DEBUG 177 /* control debugging printfs */ 178 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 179 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 180 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 181 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 182 CTL_CREATE, CTL_EOL)) != 0) 183 goto err; 184 185 /* Limit rx buffers, for simulating resource exhaustion. */ 186 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 187 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 188 "rxbufs_limit", 189 SYSCTL_DESCR("Set rx buffers limit"), 190 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 191 CTL_CREATE, CTL_EOL)) != 0) 192 goto err; 193 194 #endif /* RTW_DEBUG */ 195 /* set fallback RF programming method */ 196 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 197 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 198 "rfprog_fallback", 199 SYSCTL_DESCR("Set fallback RF programming method"), 200 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 201 CTL_CREATE, CTL_EOL)) != 0) 202 goto err; 203 204 /* force host to control RF I/O bus */ 205 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 206 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 207 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 208 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 209 CTL_CREATE, CTL_EOL)) != 0) 210 goto err; 211 212 return; 213 err: 214 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 215 } 216 217 static int 218 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 219 { 220 int error, t; 221 struct sysctlnode node; 222 223 node = *rnode; 224 t = *(int*)rnode->sysctl_data; 225 node.sysctl_data = &t; 226 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 227 if (error || newp == NULL) 228 return (error); 229 230 if (t < lower || t > upper) 231 return (EINVAL); 232 233 *(int*)rnode->sysctl_data = t; 234 235 return (0); 236 } 237 238 static int 239 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 240 { 241 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 242 __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 243 } 244 245 static int 246 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 247 { 248 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 249 } 250 251 #ifdef RTW_DEBUG 252 static int 253 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 254 { 255 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 256 0, RTW_DEBUG_MAX); 257 } 258 259 static int 260 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 261 { 262 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 263 0, RTW_RXQLEN); 264 } 265 266 static void 267 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 268 { 269 #define PRINTREG32(sc, reg) \ 270 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 271 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 272 dvname, reg, RTW_READ(regs, reg))) 273 274 #define PRINTREG16(sc, reg) \ 275 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 276 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 277 dvname, reg, RTW_READ16(regs, reg))) 278 279 #define PRINTREG8(sc, reg) \ 280 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 281 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 282 dvname, reg, RTW_READ8(regs, reg))) 283 284 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 285 286 PRINTREG32(regs, RTW_IDR0); 287 PRINTREG32(regs, RTW_IDR1); 288 PRINTREG32(regs, RTW_MAR0); 289 PRINTREG32(regs, RTW_MAR1); 290 PRINTREG32(regs, RTW_TSFTRL); 291 PRINTREG32(regs, RTW_TSFTRH); 292 PRINTREG32(regs, RTW_TLPDA); 293 PRINTREG32(regs, RTW_TNPDA); 294 PRINTREG32(regs, RTW_THPDA); 295 PRINTREG32(regs, RTW_TCR); 296 PRINTREG32(regs, RTW_RCR); 297 PRINTREG32(regs, RTW_TINT); 298 PRINTREG32(regs, RTW_TBDA); 299 PRINTREG32(regs, RTW_ANAPARM); 300 PRINTREG32(regs, RTW_BB); 301 PRINTREG32(regs, RTW_PHYCFG); 302 PRINTREG32(regs, RTW_WAKEUP0L); 303 PRINTREG32(regs, RTW_WAKEUP0H); 304 PRINTREG32(regs, RTW_WAKEUP1L); 305 PRINTREG32(regs, RTW_WAKEUP1H); 306 PRINTREG32(regs, RTW_WAKEUP2LL); 307 PRINTREG32(regs, RTW_WAKEUP2LH); 308 PRINTREG32(regs, RTW_WAKEUP2HL); 309 PRINTREG32(regs, RTW_WAKEUP2HH); 310 PRINTREG32(regs, RTW_WAKEUP3LL); 311 PRINTREG32(regs, RTW_WAKEUP3LH); 312 PRINTREG32(regs, RTW_WAKEUP3HL); 313 PRINTREG32(regs, RTW_WAKEUP3HH); 314 PRINTREG32(regs, RTW_WAKEUP4LL); 315 PRINTREG32(regs, RTW_WAKEUP4LH); 316 PRINTREG32(regs, RTW_WAKEUP4HL); 317 PRINTREG32(regs, RTW_WAKEUP4HH); 318 PRINTREG32(regs, RTW_DK0); 319 PRINTREG32(regs, RTW_DK1); 320 PRINTREG32(regs, RTW_DK2); 321 PRINTREG32(regs, RTW_DK3); 322 PRINTREG32(regs, RTW_RETRYCTR); 323 PRINTREG32(regs, RTW_RDSAR); 324 PRINTREG32(regs, RTW_FER); 325 PRINTREG32(regs, RTW_FEMR); 326 PRINTREG32(regs, RTW_FPSR); 327 PRINTREG32(regs, RTW_FFER); 328 329 /* 16-bit registers */ 330 PRINTREG16(regs, RTW_BRSR); 331 PRINTREG16(regs, RTW_IMR); 332 PRINTREG16(regs, RTW_ISR); 333 PRINTREG16(regs, RTW_BCNITV); 334 PRINTREG16(regs, RTW_ATIMWND); 335 PRINTREG16(regs, RTW_BINTRITV); 336 PRINTREG16(regs, RTW_ATIMTRITV); 337 PRINTREG16(regs, RTW_CRC16ERR); 338 PRINTREG16(regs, RTW_CRC0); 339 PRINTREG16(regs, RTW_CRC1); 340 PRINTREG16(regs, RTW_CRC2); 341 PRINTREG16(regs, RTW_CRC3); 342 PRINTREG16(regs, RTW_CRC4); 343 PRINTREG16(regs, RTW_CWR); 344 345 /* 8-bit registers */ 346 PRINTREG8(regs, RTW_CR); 347 PRINTREG8(regs, RTW_9346CR); 348 PRINTREG8(regs, RTW_CONFIG0); 349 PRINTREG8(regs, RTW_CONFIG1); 350 PRINTREG8(regs, RTW_CONFIG2); 351 PRINTREG8(regs, RTW_MSR); 352 PRINTREG8(regs, RTW_CONFIG3); 353 PRINTREG8(regs, RTW_CONFIG4); 354 PRINTREG8(regs, RTW_TESTR); 355 PRINTREG8(regs, RTW_PSR); 356 PRINTREG8(regs, RTW_SCR); 357 PRINTREG8(regs, RTW_PHYDELAY); 358 PRINTREG8(regs, RTW_CRCOUNT); 359 PRINTREG8(regs, RTW_PHYADDR); 360 PRINTREG8(regs, RTW_PHYDATAW); 361 PRINTREG8(regs, RTW_PHYDATAR); 362 PRINTREG8(regs, RTW_CONFIG5); 363 PRINTREG8(regs, RTW_TPPOLL); 364 365 PRINTREG16(regs, RTW_BSSID16); 366 PRINTREG32(regs, RTW_BSSID32); 367 #undef PRINTREG32 368 #undef PRINTREG16 369 #undef PRINTREG8 370 } 371 #endif /* RTW_DEBUG */ 372 373 void 374 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 375 { 376 struct rtw_regs *regs = &sc->sc_regs; 377 378 uint32_t tcr; 379 tcr = RTW_READ(regs, RTW_TCR); 380 tcr &= ~RTW_TCR_LBK_MASK; 381 if (enable) 382 tcr |= RTW_TCR_LBK_CONT; 383 else 384 tcr |= RTW_TCR_LBK_NORMAL; 385 RTW_WRITE(regs, RTW_TCR, tcr); 386 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 387 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 388 rtw_txdac_enable(sc, !enable); 389 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 390 rtw_set_access(regs, RTW_ACCESS_NONE); 391 } 392 393 #ifdef RTW_DEBUG 394 static const char * 395 rtw_access_string(enum rtw_access access) 396 { 397 switch (access) { 398 case RTW_ACCESS_NONE: 399 return "none"; 400 case RTW_ACCESS_CONFIG: 401 return "config"; 402 case RTW_ACCESS_ANAPARM: 403 return "anaparm"; 404 default: 405 return "unknown"; 406 } 407 } 408 #endif /* RTW_DEBUG */ 409 410 static void 411 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 412 { 413 KASSERT(/* naccess >= RTW_ACCESS_NONE && */ 414 naccess <= RTW_ACCESS_ANAPARM); 415 KASSERT(/* regs->r_access >= RTW_ACCESS_NONE && */ 416 regs->r_access <= RTW_ACCESS_ANAPARM); 417 418 if (naccess == regs->r_access) 419 return; 420 421 switch (naccess) { 422 case RTW_ACCESS_NONE: 423 switch (regs->r_access) { 424 case RTW_ACCESS_ANAPARM: 425 rtw_anaparm_enable(regs, 0); 426 /*FALLTHROUGH*/ 427 case RTW_ACCESS_CONFIG: 428 rtw_config0123_enable(regs, 0); 429 /*FALLTHROUGH*/ 430 case RTW_ACCESS_NONE: 431 break; 432 } 433 break; 434 case RTW_ACCESS_CONFIG: 435 switch (regs->r_access) { 436 case RTW_ACCESS_NONE: 437 rtw_config0123_enable(regs, 1); 438 /*FALLTHROUGH*/ 439 case RTW_ACCESS_CONFIG: 440 break; 441 case RTW_ACCESS_ANAPARM: 442 rtw_anaparm_enable(regs, 0); 443 break; 444 } 445 break; 446 case RTW_ACCESS_ANAPARM: 447 switch (regs->r_access) { 448 case RTW_ACCESS_NONE: 449 rtw_config0123_enable(regs, 1); 450 /*FALLTHROUGH*/ 451 case RTW_ACCESS_CONFIG: 452 rtw_anaparm_enable(regs, 1); 453 /*FALLTHROUGH*/ 454 case RTW_ACCESS_ANAPARM: 455 break; 456 } 457 break; 458 } 459 } 460 461 void 462 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 463 { 464 rtw_set_access1(regs, access); 465 RTW_DPRINTF(RTW_DEBUG_ACCESS, 466 ("%s: access %s -> %s\n", __func__, 467 rtw_access_string(regs->r_access), 468 rtw_access_string(access))); 469 regs->r_access = access; 470 } 471 472 /* 473 * Enable registers, switch register banks. 474 */ 475 void 476 rtw_config0123_enable(struct rtw_regs *regs, int enable) 477 { 478 uint8_t ecr; 479 ecr = RTW_READ8(regs, RTW_9346CR); 480 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 481 if (enable) 482 ecr |= RTW_9346CR_EEM_CONFIG; 483 else { 484 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 485 ecr |= RTW_9346CR_EEM_NORMAL; 486 } 487 RTW_WRITE8(regs, RTW_9346CR, ecr); 488 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 489 } 490 491 /* requires rtw_config0123_enable(, 1) */ 492 void 493 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 494 { 495 uint8_t cfg3; 496 497 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 498 cfg3 |= RTW_CONFIG3_CLKRUNEN; 499 if (enable) 500 cfg3 |= RTW_CONFIG3_PARMEN; 501 else 502 cfg3 &= ~RTW_CONFIG3_PARMEN; 503 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 504 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 505 } 506 507 /* requires rtw_anaparm_enable(, 1) */ 508 void 509 rtw_txdac_enable(struct rtw_softc *sc, int enable) 510 { 511 uint32_t anaparm; 512 struct rtw_regs *regs = &sc->sc_regs; 513 514 anaparm = RTW_READ(regs, RTW_ANAPARM); 515 if (enable) 516 anaparm &= ~RTW_ANAPARM_TXDACOFF; 517 else 518 anaparm |= RTW_ANAPARM_TXDACOFF; 519 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 520 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 521 } 522 523 static inline int 524 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 525 { 526 uint8_t cr; 527 int i; 528 529 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 530 531 RTW_WBR(regs, RTW_CR, RTW_CR); 532 533 for (i = 0; i < 1000; i++) { 534 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 535 RTW_DPRINTF(RTW_DEBUG_RESET, 536 ("%s: reset in %dus\n", dvname, i)); 537 return 0; 538 } 539 RTW_RBR(regs, RTW_CR, RTW_CR); 540 DELAY(10); /* 10us */ 541 } 542 543 printf("%s: reset failed\n", dvname); 544 return ETIMEDOUT; 545 } 546 547 static inline int 548 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 549 { 550 uint32_t tcr; 551 552 /* from Linux driver */ 553 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 554 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK); 555 556 RTW_WRITE(regs, RTW_TCR, tcr); 557 558 RTW_WBW(regs, RTW_CR, RTW_TCR); 559 560 return rtw_chip_reset1(regs, dvname); 561 } 562 563 static int 564 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen) 565 { 566 struct ieee80211_key keycopy; 567 568 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 569 570 keycopy = *k; 571 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 572 573 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, hdrlen); 574 } 575 576 static int 577 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 578 { 579 struct rtw_softc *sc = ic->ic_ifp->if_softc; 580 u_int keyix = k->wk_keyix; 581 582 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix)); 583 584 if (keyix >= IEEE80211_WEP_NKID) 585 return 0; 586 if (k->wk_keylen != 0) 587 sc->sc_flags &= ~RTW_F_DK_VALID; 588 589 return 1; 590 } 591 592 static int 593 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 594 const u_int8_t mac[IEEE80211_ADDR_LEN]) 595 { 596 struct rtw_softc *sc = ic->ic_ifp->if_softc; 597 598 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 599 600 if (k->wk_keyix >= IEEE80211_WEP_NKID) 601 return 0; 602 603 sc->sc_flags &= ~RTW_F_DK_VALID; 604 605 return 1; 606 } 607 608 static void 609 rtw_key_update_begin(struct ieee80211com *ic) 610 { 611 #ifdef RTW_DEBUG 612 struct ifnet *ifp = ic->ic_ifp; 613 struct rtw_softc *sc = ifp->if_softc; 614 #endif 615 616 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 617 } 618 619 static void 620 rtw_key_update_end(struct ieee80211com *ic) 621 { 622 struct ifnet *ifp = ic->ic_ifp; 623 struct rtw_softc *sc = ifp->if_softc; 624 625 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 626 627 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 || 628 (sc->sc_flags & RTW_F_ENABLED) == 0 || 629 (sc->sc_flags & RTW_F_INVALID) != 0) 630 return; 631 632 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 633 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 634 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 635 (ifp->if_flags & IFF_RUNNING) != 0); 636 } 637 638 static inline int 639 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k) 640 { 641 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 642 return 0; 643 644 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) || 645 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13); 646 } 647 648 static void 649 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 650 { 651 uint8_t psr, scr; 652 int i, keylen; 653 struct rtw_regs *regs; 654 union rtw_keys *rk; 655 656 regs = &sc->sc_regs; 657 rk = &sc->sc_keys; 658 659 (void)memset(rk->rk_keys, 0, sizeof(rk->rk_keys)); 660 661 /* Temporarily use software crypto for all keys. */ 662 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 663 if (wk[i].wk_cipher == &rtw_cipher_wep) 664 wk[i].wk_cipher = &ieee80211_cipher_wep; 665 } 666 667 rtw_set_access(regs, RTW_ACCESS_CONFIG); 668 669 psr = RTW_READ8(regs, RTW_PSR); 670 scr = RTW_READ8(regs, RTW_SCR); 671 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 672 673 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 674 goto out; 675 676 for (keylen = i = 0; i < IEEE80211_WEP_NKID; i++) { 677 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i])) 678 continue; 679 if (i == txkey) { 680 keylen = wk[i].wk_keylen; 681 break; 682 } 683 keylen = MAX(keylen, wk[i].wk_keylen); 684 } 685 686 if (keylen == 5) 687 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON; 688 else if (keylen == 13) 689 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON; 690 691 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 692 if (wk[i].wk_keylen != keylen || 693 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 694 continue; 695 /* h/w will decrypt, s/w still strips headers */ 696 wk[i].wk_cipher = &rtw_cipher_wep; 697 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 698 } 699 700 out: 701 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 702 703 bus_space_write_region_4(regs->r_bt, regs->r_bh, 704 RTW_DK0, rk->rk_words, 705 sizeof(rk->rk_words) / sizeof(rk->rk_words[0])); 706 707 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 708 BUS_SPACE_BARRIER_SYNC); 709 710 RTW_WBW(regs, RTW_DK0, RTW_PSR); 711 RTW_WRITE8(regs, RTW_PSR, psr); 712 RTW_WBW(regs, RTW_PSR, RTW_SCR); 713 RTW_WRITE8(regs, RTW_SCR, scr); 714 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 715 rtw_set_access(regs, RTW_ACCESS_NONE); 716 sc->sc_flags |= RTW_F_DK_VALID; 717 } 718 719 static inline int 720 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 721 { 722 int i; 723 uint8_t ecr; 724 725 ecr = RTW_READ8(regs, RTW_9346CR); 726 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 727 RTW_WRITE8(regs, RTW_9346CR, ecr); 728 729 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 730 731 /* wait 25ms for completion */ 732 for (i = 0; i < 250; i++) { 733 ecr = RTW_READ8(regs, RTW_9346CR); 734 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 735 RTW_DPRINTF(RTW_DEBUG_RESET, 736 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 737 return 0; 738 } 739 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 740 DELAY(100); 741 } 742 printf("%s: recall EEPROM failed\n", dvname); 743 return ETIMEDOUT; 744 } 745 746 static inline int 747 rtw_reset(struct rtw_softc *sc) 748 { 749 int rc; 750 uint8_t config1; 751 752 sc->sc_flags &= ~RTW_F_DK_VALID; 753 754 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 755 return rc; 756 757 rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname); 758 759 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 760 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 761 /* TBD turn off maximum power saving? */ 762 763 return 0; 764 } 765 766 static inline int 767 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 768 u_int ndescs) 769 { 770 int i, rc = 0; 771 for (i = 0; i < ndescs; i++) { 772 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 773 0, 0, &descs[i].ts_dmamap); 774 if (rc != 0) 775 break; 776 } 777 return rc; 778 } 779 780 static inline int 781 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 782 u_int ndescs) 783 { 784 int i, rc = 0; 785 for (i = 0; i < ndescs; i++) { 786 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 787 &descs[i].rs_dmamap); 788 if (rc != 0) 789 break; 790 } 791 return rc; 792 } 793 794 static inline void 795 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 796 u_int ndescs) 797 { 798 int i; 799 for (i = 0; i < ndescs; i++) { 800 if (descs[i].rs_dmamap != NULL) 801 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 802 } 803 } 804 805 static inline void 806 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 807 u_int ndescs) 808 { 809 int i; 810 for (i = 0; i < ndescs; i++) { 811 if (descs[i].ts_dmamap != NULL) 812 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 813 } 814 } 815 816 static inline void 817 rtw_srom_free(struct rtw_srom *sr) 818 { 819 sr->sr_size = 0; 820 if (sr->sr_content == NULL) 821 return; 822 free(sr->sr_content, M_DEVBUF); 823 sr->sr_content = NULL; 824 } 825 826 static void 827 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, 828 uint8_t *cs_threshold, enum rtw_rfchipid *rfchipid, uint32_t *rcr) 829 { 830 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 831 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 832 *rcr |= RTW_RCR_ENCS1; 833 *rfchipid = RTW_RFCHIPID_PHILIPS; 834 } 835 836 static int 837 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 838 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 839 const char *dvname) 840 { 841 int i; 842 const char *rfname, *paname; 843 char scratch[sizeof("unknown 0xXX")]; 844 uint16_t srom_version; 845 uint8_t mac[IEEE80211_ADDR_LEN]; 846 847 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 848 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 849 850 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 851 printf("%s: SROM version %d.%d", dvname, 852 srom_version >> 8, srom_version & 0xff); 853 854 if (srom_version <= 0x0101) { 855 printf(" is not understood, limping along with defaults\n"); 856 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 857 return 0; 858 } 859 printf("\n"); 860 861 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 862 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 863 864 RTW_DPRINTF(RTW_DEBUG_ATTACH, 865 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 866 867 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 868 869 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 870 *flags |= RTW_F_ANTDIV; 871 872 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 873 * to be reversed. 874 */ 875 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 876 *flags |= RTW_F_DIGPHY; 877 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 878 *flags |= RTW_F_DFLANTB; 879 880 *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), 881 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 882 883 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0) 884 *flags |= RTW_C_RXWEP_104; 885 886 *flags |= RTW_C_RXWEP_40; /* XXX */ 887 888 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 889 switch (*rfchipid) { 890 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 891 rfname = "GCT GRF5101"; 892 paname = "Winspring WS9901"; 893 break; 894 case RTW_RFCHIPID_MAXIM: 895 rfname = "Maxim MAX2820"; /* guess */ 896 paname = "Maxim MAX2422"; /* guess */ 897 break; 898 case RTW_RFCHIPID_INTERSIL: 899 rfname = "Intersil HFA3873"; /* guess */ 900 paname = "Intersil <unknown>"; 901 break; 902 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 903 rfname = "Philips SA2400A"; 904 paname = "Philips SA2411"; 905 break; 906 case RTW_RFCHIPID_RFMD: 907 /* this is the same front-end as an atw(4)! */ 908 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 909 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 910 "SYN: Silicon Labs Si4126"; /* inferred from 911 * reference driver 912 */ 913 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 914 break; 915 case RTW_RFCHIPID_RESERVED: 916 rfname = paname = "reserved"; 917 break; 918 default: 919 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 920 rfname = paname = scratch; 921 } 922 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 923 924 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 925 case RTW_CONFIG0_GL_USA: 926 case _RTW_CONFIG0_GL_USA: 927 *locale = RTW_LOCALE_USA; 928 break; 929 case RTW_CONFIG0_GL_EUROPE: 930 *locale = RTW_LOCALE_EUROPE; 931 break; 932 case RTW_CONFIG0_GL_JAPAN: 933 *locale = RTW_LOCALE_JAPAN; 934 break; 935 default: 936 *locale = RTW_LOCALE_UNKNOWN; 937 break; 938 } 939 return 0; 940 } 941 942 /* Returns -1 on failure. */ 943 static int 944 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 945 const char *dvname) 946 { 947 int rc; 948 struct seeprom_descriptor sd; 949 uint8_t ecr; 950 951 (void)memset(&sd, 0, sizeof(sd)); 952 953 ecr = RTW_READ8(regs, RTW_9346CR); 954 955 if ((flags & RTW_F_9356SROM) != 0) { 956 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 957 sr->sr_size = 256; 958 sd.sd_chip = C56_66; 959 } else { 960 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 961 sr->sr_size = 128; 962 sd.sd_chip = C46; 963 } 964 965 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 966 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 967 ecr |= RTW_9346CR_EEM_PROGRAM; 968 969 RTW_WRITE8(regs, RTW_9346CR, ecr); 970 971 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 972 973 if (sr->sr_content == NULL) { 974 printf("%s: unable to allocate SROM buffer\n", dvname); 975 return ENOMEM; 976 } 977 978 (void)memset(sr->sr_content, 0, sr->sr_size); 979 980 /* RTL8180 has a single 8-bit register for controlling the 981 * 93cx6 SROM. There is no "ready" bit. The RTL8180 982 * input/output sense is the reverse of read_seeprom's. 983 */ 984 sd.sd_tag = regs->r_bt; 985 sd.sd_bsh = regs->r_bh; 986 sd.sd_regsize = 1; 987 sd.sd_control_offset = RTW_9346CR; 988 sd.sd_status_offset = RTW_9346CR; 989 sd.sd_dataout_offset = RTW_9346CR; 990 sd.sd_CK = RTW_9346CR_EESK; 991 sd.sd_CS = RTW_9346CR_EECS; 992 sd.sd_DI = RTW_9346CR_EEDO; 993 sd.sd_DO = RTW_9346CR_EEDI; 994 /* make read_seeprom enter EEPROM read/write mode */ 995 sd.sd_MS = ecr; 996 sd.sd_RDY = 0; 997 998 /* TBD bus barriers */ 999 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 1000 printf("%s: could not read SROM\n", dvname); 1001 free(sr->sr_content, M_DEVBUF); 1002 sr->sr_content = NULL; 1003 return -1; /* XXX */ 1004 } 1005 1006 /* end EEPROM read/write mode */ 1007 RTW_WRITE8(regs, RTW_9346CR, 1008 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 1009 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 1010 1011 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 1012 return rc; 1013 1014 #ifdef RTW_DEBUG 1015 { 1016 int i; 1017 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1018 ("\n%s: serial ROM:\n\t", dvname)); 1019 for (i = 0; i < sr->sr_size/2; i++) { 1020 if (((i % 8) == 0) && (i != 0)) 1021 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 1022 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1023 (" %04x", sr->sr_content[i])); 1024 } 1025 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 1026 } 1027 #endif /* RTW_DEBUG */ 1028 return 0; 1029 } 1030 1031 static void 1032 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 1033 const char *dvname) 1034 { 1035 uint8_t cfg4; 1036 const char *method; 1037 1038 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 1039 1040 switch (rfchipid) { 1041 default: 1042 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 1043 method = "fallback"; 1044 break; 1045 case RTW_RFCHIPID_INTERSIL: 1046 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1047 method = "Intersil"; 1048 break; 1049 case RTW_RFCHIPID_PHILIPS: 1050 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1051 method = "Philips"; 1052 break; 1053 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1054 case RTW_RFCHIPID_RFMD: 1055 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1056 method = "RFMD"; 1057 break; 1058 } 1059 1060 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1061 1062 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1063 1064 RTW_DPRINTF(RTW_DEBUG_INIT, 1065 ("%s: %s RF programming method, %#02x\n", dvname, method, 1066 RTW_READ8(regs, RTW_CONFIG4))); 1067 } 1068 1069 static inline void 1070 rtw_init_channels(enum rtw_locale locale, 1071 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 1072 const char *dvname) 1073 { 1074 int i; 1075 const char *name = NULL; 1076 #define ADD_CHANNEL(_chans, _chan) do { \ 1077 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1078 (*_chans)[_chan].ic_freq = \ 1079 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1080 } while (0) 1081 1082 switch (locale) { 1083 case RTW_LOCALE_USA: /* 1-11 */ 1084 name = "USA"; 1085 for (i = 1; i <= 11; i++) 1086 ADD_CHANNEL(chans, i); 1087 break; 1088 case RTW_LOCALE_JAPAN: /* 1-14 */ 1089 name = "Japan"; 1090 ADD_CHANNEL(chans, 14); 1091 for (i = 1; i <= 14; i++) 1092 ADD_CHANNEL(chans, i); 1093 break; 1094 case RTW_LOCALE_EUROPE: /* 1-13 */ 1095 name = "Europe"; 1096 for (i = 1; i <= 13; i++) 1097 ADD_CHANNEL(chans, i); 1098 break; 1099 default: /* 10-11 allowed by most countries */ 1100 name = "<unknown>"; 1101 for (i = 10; i <= 11; i++) 1102 ADD_CHANNEL(chans, i); 1103 break; 1104 } 1105 printf("%s: Geographic Location %s\n", dvname, name); 1106 #undef ADD_CHANNEL 1107 } 1108 1109 1110 static inline void 1111 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale) 1112 { 1113 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1114 1115 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1116 case RTW_CONFIG0_GL_USA: 1117 case _RTW_CONFIG0_GL_USA: 1118 *locale = RTW_LOCALE_USA; 1119 break; 1120 case RTW_CONFIG0_GL_JAPAN: 1121 *locale = RTW_LOCALE_JAPAN; 1122 break; 1123 case RTW_CONFIG0_GL_EUROPE: 1124 *locale = RTW_LOCALE_EUROPE; 1125 break; 1126 default: 1127 *locale = RTW_LOCALE_UNKNOWN; 1128 break; 1129 } 1130 } 1131 1132 static inline int 1133 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1134 const char *dvname) 1135 { 1136 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1138 }; 1139 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1140 idr1 = RTW_READ(regs, RTW_IDR1); 1141 1142 (*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7)); 1143 (*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15)); 1144 (*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23)); 1145 (*addr)[3] = __SHIFTOUT(idr0, __BITS(24 ,31)); 1146 1147 (*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7)); 1148 (*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15)); 1149 1150 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1151 printf("%s: could not get mac address, attach failed\n", 1152 dvname); 1153 return ENXIO; 1154 } 1155 1156 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 1157 1158 return 0; 1159 } 1160 1161 static uint8_t 1162 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1163 struct ieee80211_channel *chan) 1164 { 1165 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1166 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 1167 ("%s: channel %d out of range", __func__, 1168 idx - RTW_SR_TXPOWER1 + 1)); 1169 return RTW_SR_GET(sr, idx); 1170 } 1171 1172 static void 1173 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1174 { 1175 int pri; 1176 /* nfree: the number of free descriptors in each ring. 1177 * The beacon ring is a special case: I do not let the 1178 * driver use all of the descriptors on the beacon ring. 1179 * The reasons are two-fold: 1180 * 1181 * (1) A BEACON descriptor's OWN bit is (apparently) not 1182 * updated, so the driver cannot easily know if the descriptor 1183 * belongs to it, or if it is racing the NIC. If the NIC 1184 * does not OWN every descriptor, then the driver can safely 1185 * update the descriptors when RTW_TBDA points at tdb_next. 1186 * 1187 * (2) I hope that the NIC will process more than one BEACON 1188 * descriptor in a single beacon interval, since that will 1189 * enable multiple-BSS support. Since the NIC does not 1190 * clear the OWN bit, there is no natural place for it to 1191 * stop processing BEACON desciptors. Maybe it will *not* 1192 * stop processing them! I do not want to chance the NIC 1193 * looping around and around a saturated beacon ring, so 1194 * I will leave one descriptor unOWNed at all times. 1195 */ 1196 u_int nfree[RTW_NTXPRI] = 1197 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, 1198 RTW_NTXDESCBCN - 1}; 1199 1200 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1201 tdb[pri].tdb_nfree = nfree[pri]; 1202 tdb[pri].tdb_next = 0; 1203 } 1204 } 1205 1206 static int 1207 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1208 { 1209 int i; 1210 struct rtw_txsoft *ts; 1211 1212 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1213 SIMPLEQ_INIT(&tsb->tsb_freeq); 1214 for (i = 0; i < tsb->tsb_ndesc; i++) { 1215 ts = &tsb->tsb_desc[i]; 1216 ts->ts_mbuf = NULL; 1217 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1218 } 1219 tsb->tsb_tx_timer = 0; 1220 return 0; 1221 } 1222 1223 static void 1224 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1225 { 1226 int pri; 1227 for (pri = 0; pri < RTW_NTXPRI; pri++) 1228 rtw_txsoft_blk_init(&tsb[pri]); 1229 } 1230 1231 static inline void 1232 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1233 { 1234 KASSERT(nsync <= rdb->rdb_ndesc); 1235 /* sync to end of ring */ 1236 if (desc0 + nsync > rdb->rdb_ndesc) { 1237 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1238 offsetof(struct rtw_descs, hd_rx[desc0]), 1239 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1240 nsync -= (rdb->rdb_ndesc - desc0); 1241 desc0 = 0; 1242 } 1243 1244 KASSERT(desc0 < rdb->rdb_ndesc); 1245 KASSERT(nsync <= rdb->rdb_ndesc); 1246 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1247 1248 /* sync what remains */ 1249 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1250 offsetof(struct rtw_descs, hd_rx[desc0]), 1251 sizeof(struct rtw_rxdesc) * nsync, ops); 1252 } 1253 1254 static void 1255 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1256 { 1257 /* sync to end of ring */ 1258 if (desc0 + nsync > tdb->tdb_ndesc) { 1259 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1260 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1261 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1262 ops); 1263 nsync -= (tdb->tdb_ndesc - desc0); 1264 desc0 = 0; 1265 } 1266 1267 /* sync what remains */ 1268 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1269 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1270 sizeof(struct rtw_txdesc) * nsync, ops); 1271 } 1272 1273 static void 1274 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1275 { 1276 int pri; 1277 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1278 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1279 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1280 } 1281 } 1282 1283 static void 1284 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1285 { 1286 int i; 1287 struct rtw_rxsoft *rs; 1288 1289 for (i = 0; i < RTW_RXQLEN; i++) { 1290 rs = &desc[i]; 1291 if (rs->rs_mbuf == NULL) 1292 continue; 1293 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1294 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1295 bus_dmamap_unload(dmat, rs->rs_dmamap); 1296 m_freem(rs->rs_mbuf); 1297 rs->rs_mbuf = NULL; 1298 } 1299 } 1300 1301 static inline int 1302 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1303 { 1304 int rc; 1305 struct mbuf *m; 1306 1307 MGETHDR(m, M_DONTWAIT, MT_DATA); 1308 if (m == NULL) 1309 return ENOBUFS; 1310 1311 MCLGET(m, M_DONTWAIT); 1312 if ((m->m_flags & M_EXT) == 0) { 1313 m_freem(m); 1314 return ENOBUFS; 1315 } 1316 1317 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1318 1319 if (rs->rs_mbuf != NULL) 1320 bus_dmamap_unload(dmat, rs->rs_dmamap); 1321 1322 rs->rs_mbuf = NULL; 1323 1324 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1325 if (rc != 0) { 1326 m_freem(m); 1327 return -1; 1328 } 1329 1330 rs->rs_mbuf = m; 1331 1332 return 0; 1333 } 1334 1335 static int 1336 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1337 int *ndesc, const char *dvname) 1338 { 1339 int i, rc = 0; 1340 struct rtw_rxsoft *rs; 1341 1342 for (i = 0; i < RTW_RXQLEN; i++) { 1343 rs = &desc[i]; 1344 /* we're in rtw_init, so there should be no mbufs allocated */ 1345 KASSERT(rs->rs_mbuf == NULL); 1346 #ifdef RTW_DEBUG 1347 if (i == rtw_rxbufs_limit) { 1348 printf("%s: TEST hit %d-buffer limit\n", dvname, i); 1349 rc = ENOBUFS; 1350 break; 1351 } 1352 #endif /* RTW_DEBUG */ 1353 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1354 printf("%s: rtw_rxsoft_alloc failed, %d buffers, " 1355 "rc %d\n", dvname, i, rc); 1356 break; 1357 } 1358 } 1359 *ndesc = i; 1360 return rc; 1361 } 1362 1363 static inline void 1364 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1365 int idx, int kick) 1366 { 1367 int is_last = (idx == rdb->rdb_ndesc - 1); 1368 uint32_t ctl, octl, obuf; 1369 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1370 1371 obuf = rd->rd_buf; 1372 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1373 1374 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1375 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1376 1377 if (is_last) 1378 ctl |= RTW_RXCTL_EOR; 1379 1380 octl = rd->rd_ctl; 1381 rd->rd_ctl = htole32(ctl); 1382 1383 RTW_DPRINTF( 1384 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1385 : RTW_DEBUG_RECV_DESC, 1386 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1387 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1388 le32toh(rd->rd_ctl))); 1389 1390 /* sync the mbuf */ 1391 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1392 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1393 1394 /* sync the descriptor */ 1395 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1396 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1397 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1398 } 1399 1400 static void 1401 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1402 { 1403 int i; 1404 struct rtw_rxdesc *rd; 1405 struct rtw_rxsoft *rs; 1406 1407 for (i = 0; i < rdb->rdb_ndesc; i++) { 1408 rd = &rdb->rdb_desc[i]; 1409 rs = &ctl[i]; 1410 rtw_rxdesc_init(rdb, rs, i, kick); 1411 } 1412 } 1413 1414 static void 1415 rtw_io_enable(struct rtw_regs *regs, uint8_t flags, int enable) 1416 { 1417 uint8_t cr; 1418 1419 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1420 enable ? "enable" : "disable", flags)); 1421 1422 cr = RTW_READ8(regs, RTW_CR); 1423 1424 /* XXX reference source does not enable MULRW */ 1425 #if 0 1426 /* enable PCI Read/Write Multiple */ 1427 cr |= RTW_CR_MULRW; 1428 #endif 1429 1430 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1431 if (enable) 1432 cr |= flags; 1433 else 1434 cr &= ~flags; 1435 RTW_WRITE8(regs, RTW_CR, cr); 1436 RTW_SYNC(regs, RTW_CR, RTW_CR); 1437 } 1438 1439 static void 1440 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1441 { 1442 #define IS_BEACON(__fc0) \ 1443 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1444 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1445 1446 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1447 * hardware -> net80211 1448 */ 1449 u_int next, nproc = 0; 1450 int hwrate, len, rate, rssi, sq; 1451 uint32_t hrssi, hstat, htsfth, htsftl; 1452 struct rtw_rxdesc *rd; 1453 struct rtw_rxsoft *rs; 1454 struct rtw_rxdesc_blk *rdb; 1455 struct mbuf *m; 1456 struct ifnet *ifp = &sc->sc_if; 1457 1458 struct ieee80211_node *ni; 1459 struct ieee80211_frame_min *wh; 1460 1461 rdb = &sc->sc_rxdesc_blk; 1462 1463 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1464 1465 for (next = rdb->rdb_next; ; next = (next + 1) % rdb->rdb_ndesc) { 1466 rtw_rxdescs_sync(rdb, next, 1, 1467 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1468 rd = &rdb->rdb_desc[next]; 1469 rs = &sc->sc_rxsoft[next]; 1470 1471 hstat = le32toh(rd->rd_stat); 1472 hrssi = le32toh(rd->rd_rssi); 1473 htsfth = le32toh(rd->rd_tsfth); 1474 htsftl = le32toh(rd->rd_tsftl); 1475 1476 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1477 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1478 __func__, next, hstat, hrssi, htsfth, htsftl)); 1479 1480 ++nproc; 1481 1482 /* still belongs to NIC */ 1483 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1484 rtw_rxdescs_sync(rdb, next, 1, BUS_DMASYNC_PREREAD); 1485 if (nproc > 1) 1486 break; 1487 1488 /* sometimes the NIC skips to the 0th descriptor */ 1489 rtw_rxdescs_sync(rdb, 0, 1, 1490 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1491 rd = &rdb->rdb_desc[0]; 1492 if ((rd->rd_stat & htole32(RTW_RXSTAT_OWN)) != 0) { 1493 rtw_rxdescs_sync(rdb, 0, 1, 1494 BUS_DMASYNC_PREREAD); 1495 break; 1496 } 1497 RTW_DPRINTF(RTW_DEBUG_BUGS, 1498 ("%s: NIC skipped from rxdesc[%u] to rxdesc[0]\n", 1499 sc->sc_dev.dv_xname, next)); 1500 next = rdb->rdb_ndesc - 1; 1501 continue; 1502 } 1503 1504 #ifdef RTW_DEBUG 1505 #define PRINTSTAT(flag) do { \ 1506 if ((hstat & flag) != 0) { \ 1507 printf("%s" #flag, delim); \ 1508 delim = ","; \ 1509 } \ 1510 } while (0) 1511 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1512 const char *delim = "<"; 1513 printf("%s: ", sc->sc_dev.dv_xname); 1514 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1515 printf("status %08x", hstat); 1516 PRINTSTAT(RTW_RXSTAT_SPLCP); 1517 PRINTSTAT(RTW_RXSTAT_MAR); 1518 PRINTSTAT(RTW_RXSTAT_PAR); 1519 PRINTSTAT(RTW_RXSTAT_BAR); 1520 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1521 PRINTSTAT(RTW_RXSTAT_CRC32); 1522 PRINTSTAT(RTW_RXSTAT_ICV); 1523 printf(">, "); 1524 } 1525 } 1526 #endif /* RTW_DEBUG */ 1527 1528 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1529 printf("%s: DMA error/FIFO overflow %08" PRIx32 ", " 1530 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1531 hstat, next); 1532 ifp->if_ierrors++; 1533 goto next; 1534 } 1535 1536 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); 1537 if (len < IEEE80211_MIN_LEN) { 1538 sc->sc_ic.ic_stats.is_rx_tooshort++; 1539 goto next; 1540 } 1541 1542 /* CRC is included with the packet; trim it off. */ 1543 len -= IEEE80211_CRC_LEN; 1544 1545 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); 1546 if (hwrate >= sizeof(ratetbl) / sizeof(ratetbl[0])) { 1547 printf("%s: unknown rate #%" __PRIuBITS "\n", 1548 sc->sc_dev.dv_xname, 1549 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); 1550 ifp->if_ierrors++; 1551 goto next; 1552 } 1553 rate = ratetbl[hwrate]; 1554 1555 #ifdef RTW_DEBUG 1556 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1557 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1558 (rate * 5) % 10, htsfth, htsftl)); 1559 #endif /* RTW_DEBUG */ 1560 1561 if ((hstat & RTW_RXSTAT_RES) != 0 && 1562 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1563 goto next; 1564 1565 /* if bad flags, skip descriptor */ 1566 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1567 printf("%s: too many rx segments\n", 1568 sc->sc_dev.dv_xname); 1569 goto next; 1570 } 1571 1572 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1573 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1574 1575 m = rs->rs_mbuf; 1576 1577 /* if temporarily out of memory, re-use mbuf */ 1578 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1579 case 0: 1580 break; 1581 case ENOBUFS: 1582 printf("%s: rtw_rxsoft_alloc(, %d) failed, " 1583 "dropping packet\n", sc->sc_dev.dv_xname, next); 1584 goto next; 1585 default: 1586 /* XXX shorten rx ring, instead? */ 1587 panic("%s: could not load DMA map\n", 1588 sc->sc_dev.dv_xname); 1589 } 1590 1591 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1592 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_RSSI); 1593 else { 1594 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); 1595 /* TBD find out each front-end's LNA gain in the 1596 * front-end's units 1597 */ 1598 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1599 rssi |= 0x80; 1600 } 1601 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ); 1602 1603 /* Note well: now we cannot recycle the rs_mbuf unless 1604 * we restore its original length. 1605 */ 1606 m->m_pkthdr.rcvif = ifp; 1607 m->m_pkthdr.len = m->m_len = len; 1608 1609 wh = mtod(m, struct ieee80211_frame_min *); 1610 1611 if (!IS_BEACON(wh->i_fc[0])) 1612 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1613 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1614 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1615 1616 sc->sc_tsfth = htsfth; 1617 1618 #ifdef RTW_DEBUG 1619 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 1620 (IFF_DEBUG|IFF_LINK2)) { 1621 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1622 rate, rssi); 1623 } 1624 #endif /* RTW_DEBUG */ 1625 1626 #if NBPFILTER > 0 1627 if (sc->sc_radiobpf != NULL) { 1628 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1629 1630 rr->rr_tsft = 1631 htole64(((uint64_t)htsfth << 32) | htsftl); 1632 1633 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1634 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE; 1635 1636 rr->rr_flags = 0; 1637 rr->rr_rate = rate; 1638 rr->rr_antsignal = rssi; 1639 rr->rr_barker_lock = htole16(sq); 1640 1641 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rr, 1642 sizeof(sc->sc_rxtapu), m); 1643 } 1644 #endif /* NPBFILTER > 0 */ 1645 1646 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1647 ieee80211_free_node(ni); 1648 next: 1649 rtw_rxdesc_init(rdb, rs, next, 0); 1650 } 1651 rdb->rdb_next = next; 1652 1653 KASSERT(rdb->rdb_next < rdb->rdb_ndesc); 1654 1655 return; 1656 #undef IS_BEACON 1657 } 1658 1659 static void 1660 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1661 struct rtw_txsoft *ts) 1662 { 1663 struct mbuf *m; 1664 struct ieee80211_node *ni; 1665 1666 m = ts->ts_mbuf; 1667 ni = ts->ts_ni; 1668 KASSERT(m != NULL); 1669 KASSERT(ni != NULL); 1670 ts->ts_mbuf = NULL; 1671 ts->ts_ni = NULL; 1672 1673 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1674 BUS_DMASYNC_POSTWRITE); 1675 bus_dmamap_unload(dmat, ts->ts_dmamap); 1676 m_freem(m); 1677 ieee80211_free_node(ni); 1678 } 1679 1680 static void 1681 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1682 struct rtw_txsoft_blk *tsb) 1683 { 1684 struct rtw_txsoft *ts; 1685 1686 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1687 rtw_txsoft_release(dmat, ic, ts); 1688 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1689 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1690 } 1691 tsb->tsb_tx_timer = 0; 1692 } 1693 1694 static inline void 1695 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1696 struct rtw_txsoft *ts, int ndesc) 1697 { 1698 uint32_t hstat; 1699 int data_retry, rts_retry; 1700 struct rtw_txdesc *tdn; 1701 const char *condstring; 1702 struct ifnet *ifp = &sc->sc_if; 1703 1704 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1705 1706 tdb->tdb_nfree += ndesc; 1707 1708 tdn = &tdb->tdb_desc[ts->ts_last]; 1709 1710 hstat = le32toh(tdn->td_stat); 1711 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1712 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); 1713 1714 ifp->if_collisions += rts_retry + data_retry; 1715 1716 if ((hstat & RTW_TXSTAT_TOK) != 0) 1717 condstring = "ok"; 1718 else { 1719 ifp->if_oerrors++; 1720 condstring = "error"; 1721 } 1722 1723 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1724 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1725 sc->sc_dev.dv_xname, ts, ts->ts_first, ts->ts_last, 1726 condstring, rts_retry, data_retry)); 1727 } 1728 1729 static void 1730 rtw_reset_oactive(struct rtw_softc *sc) 1731 { 1732 short oflags; 1733 int pri; 1734 struct rtw_txsoft_blk *tsb; 1735 struct rtw_txdesc_blk *tdb; 1736 oflags = sc->sc_if.if_flags; 1737 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1738 tsb = &sc->sc_txsoft_blk[pri]; 1739 tdb = &sc->sc_txdesc_blk[pri]; 1740 if (!SIMPLEQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0) 1741 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1742 } 1743 if (oflags != sc->sc_if.if_flags) { 1744 DPRINTF(sc, RTW_DEBUG_OACTIVE, 1745 ("%s: reset OACTIVE\n", __func__)); 1746 } 1747 } 1748 1749 /* Collect transmitted packets. */ 1750 static inline void 1751 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1752 struct rtw_txdesc_blk *tdb, int force) 1753 { 1754 int ndesc; 1755 struct rtw_txsoft *ts; 1756 1757 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1758 ndesc = 1 + ts->ts_last - ts->ts_first; 1759 if (ts->ts_last < ts->ts_first) 1760 ndesc += tdb->tdb_ndesc; 1761 1762 KASSERT(ndesc > 0); 1763 1764 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1765 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1766 1767 if (force) { 1768 int i; 1769 for (i = ts->ts_first; ; i = RTW_NEXT_IDX(tdb, i)) { 1770 tdb->tdb_desc[i].td_stat &= 1771 ~htole32(RTW_TXSTAT_OWN); 1772 if (i == ts->ts_last) 1773 break; 1774 } 1775 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1776 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1777 } else if ((tdb->tdb_desc[ts->ts_last].td_stat & 1778 htole32(RTW_TXSTAT_OWN)) != 0) { 1779 rtw_txdescs_sync(tdb, ts->ts_last, 1, 1780 BUS_DMASYNC_PREREAD); 1781 break; 1782 } 1783 1784 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1785 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1786 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1787 } 1788 /* no more pending transmissions, cancel watchdog */ 1789 if (ts == NULL) 1790 tsb->tsb_tx_timer = 0; 1791 rtw_reset_oactive(sc); 1792 } 1793 1794 static void 1795 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1796 { 1797 int pri; 1798 struct rtw_txsoft_blk *tsb; 1799 struct rtw_txdesc_blk *tdb; 1800 struct ifnet *ifp = &sc->sc_if; 1801 1802 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1803 tsb = &sc->sc_txsoft_blk[pri]; 1804 tdb = &sc->sc_txdesc_blk[pri]; 1805 1806 rtw_collect_txring(sc, tsb, tdb, 0); 1807 } 1808 1809 if ((isr & RTW_INTR_TX) != 0) 1810 rtw_start(ifp); 1811 1812 return; 1813 } 1814 1815 static void 1816 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1817 { 1818 u_int next; 1819 uint32_t tsfth, tsftl; 1820 struct ieee80211com *ic; 1821 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN]; 1822 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN]; 1823 struct mbuf *m; 1824 1825 tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH); 1826 tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1827 1828 if ((isr & (RTW_INTR_TBDOK|RTW_INTR_TBDER)) != 0) { 1829 next = rtw_txring_next(&sc->sc_regs, tdb); 1830 RTW_DPRINTF(RTW_DEBUG_BEACON, 1831 ("%s: beacon ring %sprocessed, isr = %#04" PRIx16 1832 ", next %u expected %u, %" PRIu64 "\n", __func__, 1833 (next == tdb->tdb_next) ? "" : "un", isr, next, 1834 tdb->tdb_next, (uint64_t)tsfth << 32 | tsftl)); 1835 if ((RTW_READ8(&sc->sc_regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0){ 1836 rtw_collect_txring(sc, tsb, tdb, 1); 1837 tdb->tdb_next = 0; 1838 } 1839 } 1840 /* Start beacon transmission. */ 1841 1842 if ((isr & RTW_INTR_BCNINT) != 0 && 1843 sc->sc_ic.ic_state == IEEE80211_S_RUN && 1844 SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) { 1845 RTW_DPRINTF(RTW_DEBUG_BEACON, 1846 ("%s: beacon prep. time, isr = %#04" PRIx16 1847 ", %16" PRIu64 "\n", __func__, isr, 1848 (uint64_t)tsfth << 32 | tsftl)); 1849 ic = &sc->sc_ic; 1850 m = rtw_beacon_alloc(sc, ic->ic_bss); 1851 1852 if (m == NULL) { 1853 printf("%s: could not allocate beacon\n", 1854 sc->sc_dev.dv_xname); 1855 return; 1856 } 1857 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss); 1858 IF_ENQUEUE(&sc->sc_beaconq, m); 1859 rtw_start(&sc->sc_if); 1860 } 1861 } 1862 1863 static void 1864 rtw_intr_atim(struct rtw_softc *sc) 1865 { 1866 /* TBD */ 1867 return; 1868 } 1869 1870 #ifdef RTW_DEBUG 1871 static void 1872 rtw_dump_rings(struct rtw_softc *sc) 1873 { 1874 struct rtw_txdesc_blk *tdb; 1875 struct rtw_rxdesc *rd; 1876 struct rtw_rxdesc_blk *rdb; 1877 int desc, pri; 1878 1879 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1880 return; 1881 1882 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1883 tdb = &sc->sc_txdesc_blk[pri]; 1884 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1885 tdb->tdb_ndesc, tdb->tdb_nfree); 1886 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1887 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1888 } 1889 1890 rdb = &sc->sc_rxdesc_blk; 1891 1892 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1893 rd = &rdb->rdb_desc[desc]; 1894 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1895 "rsvd1/tsfth %08x\n", __func__, 1896 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1897 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1898 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1899 } 1900 } 1901 #endif /* RTW_DEBUG */ 1902 1903 static void 1904 rtw_hwring_setup(struct rtw_softc *sc) 1905 { 1906 int pri; 1907 struct rtw_regs *regs = &sc->sc_regs; 1908 struct rtw_txdesc_blk *tdb; 1909 1910 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_basereg = RTW_TLPDA; 1911 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_base = RTW_RING_BASE(sc, hd_txlo); 1912 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_basereg = RTW_TNPDA; 1913 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_base = RTW_RING_BASE(sc, hd_txmd); 1914 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_basereg = RTW_THPDA; 1915 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_base = RTW_RING_BASE(sc, hd_txhi); 1916 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_basereg = RTW_TBDA; 1917 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_base = RTW_RING_BASE(sc, hd_bcn); 1918 1919 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1920 tdb = &sc->sc_txdesc_blk[pri]; 1921 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base); 1922 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1923 ("%s: reg[tdb->tdb_basereg] <- %" PRIxPTR "\n", __func__, 1924 (uintptr_t)tdb->tdb_base)); 1925 } 1926 1927 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1928 1929 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1930 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1931 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1932 1933 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1934 1935 } 1936 1937 static int 1938 rtw_swring_setup(struct rtw_softc *sc) 1939 { 1940 int rc; 1941 struct rtw_rxdesc_blk *rdb; 1942 1943 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1944 1945 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1946 1947 rdb = &sc->sc_rxdesc_blk; 1948 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1949 sc->sc_dev.dv_xname)) != 0 && rdb->rdb_ndesc == 0) { 1950 printf("%s: could not allocate rx buffers\n", 1951 sc->sc_dev.dv_xname); 1952 return rc; 1953 } 1954 1955 rdb = &sc->sc_rxdesc_blk; 1956 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1957 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1958 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1959 rdb->rdb_next = 0; 1960 1961 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1962 return 0; 1963 } 1964 1965 static void 1966 rtw_txdesc_blk_init(struct rtw_txdesc_blk *tdb) 1967 { 1968 int i; 1969 1970 (void)memset(tdb->tdb_desc, 0, 1971 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 1972 for (i = 0; i < tdb->tdb_ndesc; i++) 1973 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 1974 } 1975 1976 static u_int 1977 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb) 1978 { 1979 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) / 1980 sizeof(struct rtw_txdesc); 1981 } 1982 1983 static void 1984 rtw_txring_fixup(struct rtw_softc *sc) 1985 { 1986 int pri; 1987 u_int next; 1988 struct rtw_txdesc_blk *tdb; 1989 struct rtw_regs *regs = &sc->sc_regs; 1990 1991 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1992 tdb = &sc->sc_txdesc_blk[pri]; 1993 next = rtw_txring_next(regs, tdb); 1994 if (tdb->tdb_next == next) 1995 continue; 1996 printf("%s: tx-ring %d expected next %u, read %u\n", __func__, 1997 pri, tdb->tdb_next, next); 1998 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1); 1999 } 2000 } 2001 2002 static void 2003 rtw_rxring_fixup(struct rtw_softc *sc) 2004 { 2005 u_int next; 2006 uint32_t rdsar; 2007 struct rtw_rxdesc_blk *rdb; 2008 2009 rdsar = le32toh(RTW_READ(&sc->sc_regs, RTW_RDSAR)); 2010 next = (rdsar - RTW_RING_BASE(sc, hd_rx)) / sizeof(struct rtw_rxdesc); 2011 2012 rdb = &sc->sc_rxdesc_blk; 2013 if (rdb->rdb_next != next) { 2014 printf("%s: rx-ring expected next %u, read %u\n", __func__, 2015 rdb->rdb_next, next); 2016 rdb->rdb_next = MIN(next, rdb->rdb_ndesc - 1); 2017 } 2018 } 2019 2020 static void 2021 rtw_txdescs_reset(struct rtw_softc *sc) 2022 { 2023 int pri; 2024 2025 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2026 rtw_collect_txring(sc, &sc->sc_txsoft_blk[pri], 2027 &sc->sc_txdesc_blk[pri], 1); 2028 } 2029 } 2030 2031 static void 2032 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 2033 { 2034 uint8_t cr = 0; 2035 int xmtr = 0, rcvr = 0; 2036 struct rtw_regs *regs = &sc->sc_regs; 2037 2038 if ((isr & RTW_INTR_TXFOVW) != 0) { 2039 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 2040 rcvr = xmtr = 1; 2041 cr |= RTW_CR_TE | RTW_CR_RE; 2042 } 2043 2044 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) { 2045 cr |= RTW_CR_RE; 2046 rcvr = 1; 2047 } 2048 2049 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: restarting xmit/recv, isr %" PRIx16 2050 "\n", sc->sc_dev.dv_xname, isr)); 2051 2052 #ifdef RTW_DEBUG 2053 rtw_dump_rings(sc); 2054 #endif /* RTW_DEBUG */ 2055 2056 rtw_io_enable(regs, cr, 0); 2057 2058 /* Collect rx'd packets. Refresh rx buffers. */ 2059 if (rcvr) 2060 rtw_intr_rx(sc, 0); 2061 /* Collect tx'd packets. XXX let's hope this stops the transmit 2062 * timeouts. 2063 */ 2064 if (xmtr) 2065 rtw_txdescs_reset(sc); 2066 2067 RTW_WRITE16(regs, RTW_IMR, 0); 2068 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 2069 2070 if (rtw_do_chip_reset) { 2071 rtw_chip_reset1(regs, sc->sc_dev.dv_xname); 2072 rtw_wep_setkeys(sc, sc->sc_ic.ic_nw_keys, 2073 sc->sc_ic.ic_def_txkey); 2074 } 2075 2076 rtw_rxdesc_init_all(&sc->sc_rxdesc_blk, &sc->sc_rxsoft[0], 1); 2077 2078 #ifdef RTW_DEBUG 2079 rtw_dump_rings(sc); 2080 #endif /* RTW_DEBUG */ 2081 2082 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2083 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 2084 if (rcvr) 2085 rtw_rxring_fixup(sc); 2086 rtw_io_enable(regs, cr, 1); 2087 if (xmtr) 2088 rtw_txring_fixup(sc); 2089 } 2090 2091 static inline void 2092 rtw_suspend_ticks(struct rtw_softc *sc) 2093 { 2094 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2095 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 2096 sc->sc_do_tick = 0; 2097 } 2098 2099 static inline void 2100 rtw_resume_ticks(struct rtw_softc *sc) 2101 { 2102 uint32_t tsftrl0, tsftrl1, next_tick; 2103 2104 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2105 2106 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2107 next_tick = tsftrl1 + 1000000; 2108 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 2109 2110 sc->sc_do_tick = 1; 2111 2112 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2113 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 2114 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 2115 } 2116 2117 static void 2118 rtw_intr_timeout(struct rtw_softc *sc) 2119 { 2120 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 2121 if (sc->sc_do_tick) 2122 rtw_resume_ticks(sc); 2123 return; 2124 } 2125 2126 int 2127 rtw_intr(void *arg) 2128 { 2129 int i; 2130 struct rtw_softc *sc = arg; 2131 struct rtw_regs *regs = &sc->sc_regs; 2132 uint16_t isr; 2133 struct ifnet *ifp = &sc->sc_if; 2134 2135 /* 2136 * If the interface isn't running, the interrupt couldn't 2137 * possibly have come from us. 2138 */ 2139 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 2140 (ifp->if_flags & IFF_RUNNING) == 0 || 2141 !device_is_active(&sc->sc_dev)) { 2142 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 2143 return (0); 2144 } 2145 2146 for (i = 0; i < 10; i++) { 2147 isr = RTW_READ16(regs, RTW_ISR); 2148 2149 RTW_WRITE16(regs, RTW_ISR, isr); 2150 RTW_WBR(regs, RTW_ISR, RTW_ISR); 2151 2152 if (sc->sc_intr_ack != NULL) 2153 (*sc->sc_intr_ack)(regs); 2154 2155 if (isr == 0) 2156 break; 2157 2158 #ifdef RTW_DEBUG 2159 #define PRINTINTR(flag) do { \ 2160 if ((isr & flag) != 0) { \ 2161 printf("%s" #flag, delim); \ 2162 delim = ","; \ 2163 } \ 2164 } while (0) 2165 2166 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 2167 const char *delim = "<"; 2168 2169 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 2170 2171 PRINTINTR(RTW_INTR_TXFOVW); 2172 PRINTINTR(RTW_INTR_TIMEOUT); 2173 PRINTINTR(RTW_INTR_BCNINT); 2174 PRINTINTR(RTW_INTR_ATIMINT); 2175 PRINTINTR(RTW_INTR_TBDER); 2176 PRINTINTR(RTW_INTR_TBDOK); 2177 PRINTINTR(RTW_INTR_THPDER); 2178 PRINTINTR(RTW_INTR_THPDOK); 2179 PRINTINTR(RTW_INTR_TNPDER); 2180 PRINTINTR(RTW_INTR_TNPDOK); 2181 PRINTINTR(RTW_INTR_RXFOVW); 2182 PRINTINTR(RTW_INTR_RDU); 2183 PRINTINTR(RTW_INTR_TLPDER); 2184 PRINTINTR(RTW_INTR_TLPDOK); 2185 PRINTINTR(RTW_INTR_RER); 2186 PRINTINTR(RTW_INTR_ROK); 2187 2188 printf(">\n"); 2189 } 2190 #undef PRINTINTR 2191 #endif /* RTW_DEBUG */ 2192 2193 if ((isr & RTW_INTR_RX) != 0) 2194 rtw_intr_rx(sc, isr & RTW_INTR_RX); 2195 if ((isr & RTW_INTR_TX) != 0) 2196 rtw_intr_tx(sc, isr & RTW_INTR_TX); 2197 if ((isr & RTW_INTR_BEACON) != 0) 2198 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 2199 if ((isr & RTW_INTR_ATIMINT) != 0) 2200 rtw_intr_atim(sc); 2201 if ((isr & RTW_INTR_IOERROR) != 0) 2202 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 2203 if ((isr & RTW_INTR_TIMEOUT) != 0) 2204 rtw_intr_timeout(sc); 2205 } 2206 2207 return 1; 2208 } 2209 2210 /* Must be called at splnet. */ 2211 static void 2212 rtw_stop(struct ifnet *ifp, int disable) 2213 { 2214 int pri; 2215 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2216 struct ieee80211com *ic = &sc->sc_ic; 2217 struct rtw_regs *regs = &sc->sc_regs; 2218 2219 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2220 return; 2221 2222 rtw_suspend_ticks(sc); 2223 2224 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2225 2226 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 2227 /* Disable interrupts. */ 2228 RTW_WRITE16(regs, RTW_IMR, 0); 2229 2230 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2231 2232 /* Stop the transmit and receive processes. First stop DMA, 2233 * then disable receiver and transmitter. 2234 */ 2235 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2236 2237 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2238 2239 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 2240 } 2241 2242 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2243 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2244 &sc->sc_txsoft_blk[pri]); 2245 } 2246 2247 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2248 2249 if (disable) 2250 rtw_disable(sc); 2251 2252 /* Mark the interface as not running. Cancel the watchdog timer. */ 2253 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2254 ifp->if_timer = 0; 2255 2256 return; 2257 } 2258 2259 const char * 2260 rtw_pwrstate_string(enum rtw_pwrstate power) 2261 { 2262 switch (power) { 2263 case RTW_ON: 2264 return "on"; 2265 case RTW_SLEEP: 2266 return "sleep"; 2267 case RTW_OFF: 2268 return "off"; 2269 default: 2270 return "unknown"; 2271 } 2272 } 2273 2274 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2275 * reference driver, plus a magic Maxim "ON" value that comes from 2276 * the Realtek document "Windows PG for Rtl8180." 2277 */ 2278 static void 2279 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2280 int before_rf, int digphy) 2281 { 2282 uint32_t anaparm; 2283 2284 anaparm = RTW_READ(regs, RTW_ANAPARM); 2285 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2286 2287 switch (power) { 2288 case RTW_OFF: 2289 if (before_rf) 2290 return; 2291 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2292 anaparm |= RTW_ANAPARM_TXDACOFF; 2293 break; 2294 case RTW_SLEEP: 2295 if (!before_rf) 2296 return; 2297 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2298 anaparm |= RTW_ANAPARM_TXDACOFF; 2299 break; 2300 case RTW_ON: 2301 if (!before_rf) 2302 return; 2303 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2304 break; 2305 } 2306 RTW_DPRINTF(RTW_DEBUG_PWR, 2307 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2308 __func__, rtw_pwrstate_string(power), 2309 (before_rf) ? "before" : "after", anaparm)); 2310 2311 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2312 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2313 } 2314 2315 /* XXX I am using the RFMD settings gleaned from the reference 2316 * driver. They agree 2317 */ 2318 static void 2319 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2320 int before_rf, int digphy) 2321 { 2322 uint32_t anaparm; 2323 2324 anaparm = RTW_READ(regs, RTW_ANAPARM); 2325 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2326 2327 switch (power) { 2328 case RTW_OFF: 2329 if (before_rf) 2330 return; 2331 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2332 anaparm |= RTW_ANAPARM_TXDACOFF; 2333 break; 2334 case RTW_SLEEP: 2335 if (!before_rf) 2336 return; 2337 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2338 anaparm |= RTW_ANAPARM_TXDACOFF; 2339 break; 2340 case RTW_ON: 2341 if (!before_rf) 2342 return; 2343 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2344 break; 2345 } 2346 RTW_DPRINTF(RTW_DEBUG_PWR, 2347 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2348 __func__, rtw_pwrstate_string(power), 2349 (before_rf) ? "before" : "after", anaparm)); 2350 2351 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2352 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2353 } 2354 2355 static void 2356 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2357 int before_rf, int digphy) 2358 { 2359 uint32_t anaparm; 2360 2361 anaparm = RTW_READ(regs, RTW_ANAPARM); 2362 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2363 2364 switch (power) { 2365 case RTW_OFF: 2366 if (before_rf) 2367 return; 2368 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2369 anaparm |= RTW_ANAPARM_TXDACOFF; 2370 break; 2371 case RTW_SLEEP: 2372 if (!before_rf) 2373 return; 2374 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2375 anaparm |= RTW_ANAPARM_TXDACOFF; 2376 break; 2377 case RTW_ON: 2378 if (!before_rf) 2379 return; 2380 if (digphy) { 2381 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2382 /* XXX guess */ 2383 anaparm |= RTW_ANAPARM_TXDACOFF; 2384 } else 2385 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2386 break; 2387 } 2388 RTW_DPRINTF(RTW_DEBUG_PWR, 2389 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2390 __func__, rtw_pwrstate_string(power), 2391 (before_rf) ? "before" : "after", anaparm)); 2392 2393 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2394 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2395 } 2396 2397 static void 2398 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2399 int digphy) 2400 { 2401 struct rtw_regs *regs = &sc->sc_regs; 2402 2403 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2404 2405 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2406 2407 rtw_set_access(regs, RTW_ACCESS_NONE); 2408 2409 return; 2410 } 2411 2412 static int 2413 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2414 { 2415 int rc; 2416 2417 RTW_DPRINTF(RTW_DEBUG_PWR, 2418 ("%s: %s->%s\n", __func__, 2419 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2420 2421 if (sc->sc_pwrstate == power) 2422 return 0; 2423 2424 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2425 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2426 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2427 2428 switch (power) { 2429 case RTW_ON: 2430 /* TBD set LEDs */ 2431 break; 2432 case RTW_SLEEP: 2433 /* TBD */ 2434 break; 2435 case RTW_OFF: 2436 /* TBD */ 2437 break; 2438 } 2439 if (rc == 0) 2440 sc->sc_pwrstate = power; 2441 else 2442 sc->sc_pwrstate = RTW_OFF; 2443 return rc; 2444 } 2445 2446 static int 2447 rtw_tune(struct rtw_softc *sc) 2448 { 2449 struct ieee80211com *ic = &sc->sc_ic; 2450 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 2451 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 2452 u_int chan; 2453 int rc; 2454 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2455 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2456 2457 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2458 if (chan == IEEE80211_CHAN_ANY) 2459 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 2460 2461 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2462 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2463 2464 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2465 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2466 2467 if (chan == sc->sc_cur_chan) { 2468 RTW_DPRINTF(RTW_DEBUG_TUNE, 2469 ("%s: already tuned chan #%d\n", __func__, chan)); 2470 return 0; 2471 } 2472 2473 rtw_suspend_ticks(sc); 2474 2475 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 2476 2477 /* TBD wait for Tx to complete */ 2478 2479 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2480 2481 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2482 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr, 2483 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) { 2484 /* XXX condition on powersaving */ 2485 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2486 } 2487 2488 sc->sc_cur_chan = chan; 2489 2490 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 2491 2492 rtw_resume_ticks(sc); 2493 2494 return rc; 2495 } 2496 2497 void 2498 rtw_disable(struct rtw_softc *sc) 2499 { 2500 int rc; 2501 2502 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2503 return; 2504 2505 /* turn off PHY */ 2506 if ((sc->sc_flags & RTW_F_INVALID) == 0 && 2507 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2508 printf("%s: failed to turn off PHY (%d)\n", 2509 sc->sc_dev.dv_xname, rc); 2510 } 2511 2512 if (sc->sc_disable != NULL) 2513 (*sc->sc_disable)(sc); 2514 2515 sc->sc_flags &= ~RTW_F_ENABLED; 2516 } 2517 2518 int 2519 rtw_enable(struct rtw_softc *sc) 2520 { 2521 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2522 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2523 printf("%s: device enable failed\n", 2524 sc->sc_dev.dv_xname); 2525 return (EIO); 2526 } 2527 sc->sc_flags |= RTW_F_ENABLED; 2528 /* Power may have been removed, and WEP keys thus 2529 * reset. 2530 */ 2531 sc->sc_flags &= ~RTW_F_DK_VALID; 2532 } 2533 return (0); 2534 } 2535 2536 static void 2537 rtw_transmit_config(struct rtw_regs *regs) 2538 { 2539 uint32_t tcr; 2540 2541 tcr = RTW_READ(regs, RTW_TCR); 2542 2543 tcr |= RTW_TCR_CWMIN; 2544 tcr &= ~RTW_TCR_MXDMA_MASK; 2545 tcr |= RTW_TCR_MXDMA_256; 2546 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2547 tcr &= ~RTW_TCR_LBK_MASK; 2548 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2549 2550 /* set short/long retry limits */ 2551 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2552 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK); 2553 2554 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2555 2556 RTW_WRITE(regs, RTW_TCR, tcr); 2557 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2558 } 2559 2560 static inline void 2561 rtw_enable_interrupts(struct rtw_softc *sc) 2562 { 2563 struct rtw_regs *regs = &sc->sc_regs; 2564 2565 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2566 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2567 2568 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2569 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2570 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2571 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2572 2573 /* XXX necessary? */ 2574 if (sc->sc_intr_ack != NULL) 2575 (*sc->sc_intr_ack)(regs); 2576 } 2577 2578 static void 2579 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2580 { 2581 uint8_t msr; 2582 2583 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2584 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2585 2586 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2587 2588 switch (opmode) { 2589 case IEEE80211_M_AHDEMO: 2590 case IEEE80211_M_IBSS: 2591 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2592 break; 2593 case IEEE80211_M_HOSTAP: 2594 msr |= RTW_MSR_NETYPE_AP_OK; 2595 break; 2596 case IEEE80211_M_MONITOR: 2597 /* XXX */ 2598 msr |= RTW_MSR_NETYPE_NOLINK; 2599 break; 2600 case IEEE80211_M_STA: 2601 msr |= RTW_MSR_NETYPE_INFRA_OK; 2602 break; 2603 } 2604 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2605 2606 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2607 } 2608 2609 #define rtw_calchash(addr) \ 2610 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2611 2612 static void 2613 rtw_pktfilt_load(struct rtw_softc *sc) 2614 { 2615 struct rtw_regs *regs = &sc->sc_regs; 2616 struct ieee80211com *ic = &sc->sc_ic; 2617 struct ethercom *ec = &sc->sc_ec; 2618 struct ifnet *ifp = &sc->sc_if; 2619 int hash; 2620 uint32_t hashes[2] = { 0, 0 }; 2621 struct ether_multi *enm; 2622 struct ether_multistep step; 2623 2624 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2625 2626 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2627 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2628 2629 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2630 /* MAC auto-reset PHY (huh?) */ 2631 sc->sc_rcr |= RTW_RCR_ENMARP; 2632 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2633 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2634 2635 switch (ic->ic_opmode) { 2636 case IEEE80211_M_MONITOR: 2637 sc->sc_rcr |= RTW_RCR_MONITOR; 2638 break; 2639 case IEEE80211_M_AHDEMO: 2640 case IEEE80211_M_IBSS: 2641 /* receive broadcasts in our BSS */ 2642 sc->sc_rcr |= RTW_RCR_ADD3; 2643 break; 2644 default: 2645 break; 2646 } 2647 2648 ifp->if_flags &= ~IFF_ALLMULTI; 2649 2650 /* XXX accept all broadcast if scanning */ 2651 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2652 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2653 2654 if (ifp->if_flags & IFF_PROMISC) { 2655 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2656 allmulti: 2657 ifp->if_flags |= IFF_ALLMULTI; 2658 goto setit; 2659 } 2660 2661 /* 2662 * Program the 64-bit multicast hash filter. 2663 */ 2664 ETHER_FIRST_MULTI(step, ec, enm); 2665 while (enm != NULL) { 2666 /* XXX */ 2667 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2668 ETHER_ADDR_LEN) != 0) 2669 goto allmulti; 2670 2671 hash = rtw_calchash(enm->enm_addrlo); 2672 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2673 sc->sc_rcr |= RTW_RCR_AM; 2674 ETHER_NEXT_MULTI(step, enm); 2675 } 2676 2677 /* all bits set => hash is useless */ 2678 if (~(hashes[0] & hashes[1]) == 0) 2679 goto allmulti; 2680 2681 setit: 2682 if (ifp->if_flags & IFF_ALLMULTI) { 2683 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2684 hashes[0] = hashes[1] = 0xffffffff; 2685 } 2686 2687 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2688 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2689 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2690 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2691 2692 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2693 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2694 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2695 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2696 2697 return; 2698 } 2699 2700 static struct mbuf * 2701 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2702 { 2703 struct ieee80211com *ic = &sc->sc_ic; 2704 struct mbuf *m; 2705 struct ieee80211_beacon_offsets boff; 2706 2707 if ((m = ieee80211_beacon_alloc(ic, ni, &boff)) != NULL) { 2708 RTW_DPRINTF(RTW_DEBUG_BEACON, 2709 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2710 } 2711 return m; 2712 } 2713 2714 /* Must be called at splnet. */ 2715 static int 2716 rtw_init(struct ifnet *ifp) 2717 { 2718 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2719 struct ieee80211com *ic = &sc->sc_ic; 2720 struct rtw_regs *regs = &sc->sc_regs; 2721 int rc = 0; 2722 2723 if ((rc = rtw_enable(sc)) != 0) 2724 goto out; 2725 2726 /* Cancel pending I/O and reset. */ 2727 rtw_stop(ifp, 0); 2728 2729 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2730 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 2731 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 2732 2733 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2734 goto out; 2735 2736 if ((rc = rtw_swring_setup(sc)) != 0) 2737 goto out; 2738 2739 rtw_transmit_config(regs); 2740 2741 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2742 2743 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2744 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2745 2746 /* long PLCP header, 1Mb/2Mb basic rate */ 2747 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2748 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2749 2750 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2751 rtw_set_access(regs, RTW_ACCESS_NONE); 2752 2753 /* XXX from reference sources */ 2754 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2755 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2756 2757 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2758 2759 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2760 /* from Linux driver */ 2761 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2762 2763 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2764 2765 rtw_enable_interrupts(sc); 2766 2767 rtw_pktfilt_load(sc); 2768 2769 rtw_hwring_setup(sc); 2770 2771 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2772 2773 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2774 2775 ifp->if_flags |= IFF_RUNNING; 2776 ic->ic_state = IEEE80211_S_INIT; 2777 2778 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2779 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2780 2781 rtw_resume_ticks(sc); 2782 2783 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2784 2785 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2786 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2787 else 2788 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2789 2790 out: 2791 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2792 return rc; 2793 } 2794 2795 static inline void 2796 rtw_led_init(struct rtw_regs *regs) 2797 { 2798 uint8_t cfg0, cfg1; 2799 2800 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2801 2802 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2803 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2804 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2805 2806 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2807 RTW_DPRINTF(RTW_DEBUG_LED, 2808 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2809 2810 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2811 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2812 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2813 2814 rtw_set_access(regs, RTW_ACCESS_NONE); 2815 } 2816 2817 /* 2818 * IEEE80211_S_INIT: LED1 off 2819 * 2820 * IEEE80211_S_AUTH, 2821 * IEEE80211_S_ASSOC, 2822 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2823 * 2824 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2825 */ 2826 static void 2827 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2828 { 2829 struct rtw_led_state *ls; 2830 2831 ls = &sc->sc_led_state; 2832 2833 switch (nstate) { 2834 case IEEE80211_S_INIT: 2835 rtw_led_init(&sc->sc_regs); 2836 callout_stop(&ls->ls_slow_ch); 2837 callout_stop(&ls->ls_fast_ch); 2838 ls->ls_slowblink = 0; 2839 ls->ls_actblink = 0; 2840 ls->ls_default = 0; 2841 break; 2842 case IEEE80211_S_SCAN: 2843 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2844 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2845 /*FALLTHROUGH*/ 2846 case IEEE80211_S_AUTH: 2847 case IEEE80211_S_ASSOC: 2848 ls->ls_default = RTW_LED1; 2849 ls->ls_actblink = RTW_LED1; 2850 ls->ls_slowblink = RTW_LED1; 2851 break; 2852 case IEEE80211_S_RUN: 2853 ls->ls_slowblink = 0; 2854 break; 2855 } 2856 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2857 } 2858 2859 static void 2860 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2861 { 2862 uint8_t led_condition; 2863 bus_size_t ofs; 2864 uint8_t mask, newval, val; 2865 2866 led_condition = ls->ls_default; 2867 2868 if (ls->ls_state & RTW_LED_S_SLOW) 2869 led_condition ^= ls->ls_slowblink; 2870 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2871 led_condition ^= ls->ls_actblink; 2872 2873 RTW_DPRINTF(RTW_DEBUG_LED, 2874 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2875 2876 switch (hwverid) { 2877 default: 2878 case 'F': 2879 ofs = RTW_PSR; 2880 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2881 if (led_condition & RTW_LED0) 2882 newval &= ~RTW_PSR_LEDGPO0; 2883 if (led_condition & RTW_LED1) 2884 newval &= ~RTW_PSR_LEDGPO1; 2885 break; 2886 case 'D': 2887 ofs = RTW_9346CR; 2888 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2889 newval = RTW_9346CR_EEM_PROGRAM; 2890 if (led_condition & RTW_LED0) 2891 newval |= RTW_9346CR_EEDI; 2892 if (led_condition & RTW_LED1) 2893 newval |= RTW_9346CR_EECS; 2894 break; 2895 } 2896 val = RTW_READ8(regs, ofs); 2897 RTW_DPRINTF(RTW_DEBUG_LED, 2898 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2899 (uintptr_t)ofs)); 2900 val &= ~mask; 2901 val |= newval; 2902 RTW_WRITE8(regs, ofs, val); 2903 RTW_DPRINTF(RTW_DEBUG_LED, 2904 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2905 (uintptr_t)ofs)); 2906 RTW_SYNC(regs, ofs, ofs); 2907 } 2908 2909 static void 2910 rtw_led_fastblink(void *arg) 2911 { 2912 int ostate, s; 2913 struct rtw_softc *sc = (struct rtw_softc *)arg; 2914 struct rtw_led_state *ls = &sc->sc_led_state; 2915 2916 s = splnet(); 2917 ostate = ls->ls_state; 2918 ls->ls_state ^= ls->ls_event; 2919 2920 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2921 ls->ls_state &= ~RTW_LED_S_TX; 2922 2923 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2924 ls->ls_state &= ~RTW_LED_S_RX; 2925 2926 ls->ls_event = 0; 2927 2928 if (ostate != ls->ls_state) 2929 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2930 splx(s); 2931 2932 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2933 } 2934 2935 static void 2936 rtw_led_slowblink(void *arg) 2937 { 2938 int s; 2939 struct rtw_softc *sc = (struct rtw_softc *)arg; 2940 struct rtw_led_state *ls = &sc->sc_led_state; 2941 2942 s = splnet(); 2943 ls->ls_state ^= RTW_LED_S_SLOW; 2944 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2945 splx(s); 2946 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2947 } 2948 2949 static inline void 2950 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2951 { 2952 callout_init(&ls->ls_fast_ch); 2953 callout_init(&ls->ls_slow_ch); 2954 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2955 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2956 } 2957 2958 static int 2959 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2960 { 2961 int rc = 0, s; 2962 struct rtw_softc *sc = ifp->if_softc; 2963 struct ifreq *ifr = (struct ifreq *)data; 2964 2965 s = splnet(); 2966 switch (cmd) { 2967 case SIOCSIFFLAGS: 2968 if ((ifp->if_flags & IFF_UP) != 0) { 2969 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2970 rtw_pktfilt_load(sc); 2971 } else 2972 rc = rtw_init(ifp); 2973 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2974 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2975 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2976 rtw_stop(ifp, 1); 2977 } 2978 break; 2979 case SIOCADDMULTI: 2980 case SIOCDELMULTI: 2981 if (cmd == SIOCADDMULTI) 2982 rc = ether_addmulti(ifr, &sc->sc_ec); 2983 else 2984 rc = ether_delmulti(ifr, &sc->sc_ec); 2985 if (rc != ENETRESET) 2986 break; 2987 if (ifp->if_flags & IFF_RUNNING) 2988 rtw_pktfilt_load(sc); 2989 rc = 0; 2990 break; 2991 default: 2992 if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 2993 break; 2994 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2995 rc = rtw_init(ifp); 2996 else 2997 rc = 0; 2998 break; 2999 } 3000 splx(s); 3001 return rc; 3002 } 3003 3004 /* Select a transmit ring with at least one h/w and s/w descriptor free. 3005 * Return 0 on success, -1 on failure. 3006 */ 3007 static inline int 3008 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 3009 struct rtw_txdesc_blk **tdbp, int pri) 3010 { 3011 struct rtw_txsoft_blk *tsb; 3012 struct rtw_txdesc_blk *tdb; 3013 3014 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 3015 3016 tsb = &sc->sc_txsoft_blk[pri]; 3017 tdb = &sc->sc_txdesc_blk[pri]; 3018 3019 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 3020 if (tsb->tsb_tx_timer == 0) 3021 tsb->tsb_tx_timer = 5; 3022 *tsbp = NULL; 3023 *tdbp = NULL; 3024 return -1; 3025 } 3026 *tsbp = tsb; 3027 *tdbp = tdb; 3028 return 0; 3029 } 3030 3031 static inline struct mbuf * 3032 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 3033 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 3034 struct ieee80211_node **nip, short *if_flagsp) 3035 { 3036 struct mbuf *m; 3037 3038 if (IF_IS_EMPTY(ifq)) 3039 return NULL; 3040 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3041 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3042 __func__, pri)); 3043 *if_flagsp |= IFF_OACTIVE; 3044 sc->sc_if.if_timer = 1; 3045 return NULL; 3046 } 3047 IF_DEQUEUE(ifq, m); 3048 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3049 m->m_pkthdr.rcvif = NULL; 3050 KASSERT(*nip != NULL); 3051 return m; 3052 } 3053 3054 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 3055 * at the driver's selection of transmit control block for the packet. 3056 */ 3057 static inline int 3058 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 3059 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 3060 struct ieee80211_node **nip) 3061 { 3062 int pri; 3063 struct ether_header *eh; 3064 struct mbuf *m0; 3065 struct rtw_softc *sc; 3066 short *if_flagsp; 3067 3068 sc = (struct rtw_softc *)ifp->if_softc; 3069 3070 DPRINTF(sc, RTW_DEBUG_XMIT, 3071 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3072 3073 if_flagsp = &ifp->if_flags; 3074 3075 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 3076 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 3077 tdbp, nip, if_flagsp)) != NULL) { 3078 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 3079 __func__)); 3080 return 0; 3081 } 3082 3083 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 3084 tdbp, nip, if_flagsp)) != NULL) { 3085 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 3086 __func__)); 3087 return 0; 3088 } 3089 3090 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 3091 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 3092 return 0; 3093 } 3094 3095 *mp = NULL; 3096 3097 IFQ_POLL(&ifp->if_snd, m0); 3098 if (m0 == NULL) { 3099 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3100 __func__)); 3101 return 0; 3102 } 3103 3104 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 3105 3106 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3107 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3108 __func__, pri)); 3109 *if_flagsp |= IFF_OACTIVE; 3110 sc->sc_if.if_timer = 1; 3111 return 0; 3112 } 3113 3114 IFQ_DEQUEUE(&ifp->if_snd, m0); 3115 if (m0 == NULL) { 3116 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3117 __func__)); 3118 return 0; 3119 } 3120 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 3121 ifp->if_opackets++; 3122 #if NBPFILTER > 0 3123 if (ifp->if_bpf) 3124 bpf_mtap(ifp->if_bpf, m0); 3125 #endif 3126 eh = mtod(m0, struct ether_header *); 3127 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 3128 if (*nip == NULL) { 3129 /* NB: ieee80211_find_txnode does stat+msg */ 3130 m_freem(m0); 3131 return -1; 3132 } 3133 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 3134 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 3135 ifp->if_oerrors++; 3136 return -1; 3137 } 3138 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3139 *mp = m0; 3140 return 0; 3141 } 3142 3143 static int 3144 rtw_seg_too_short(bus_dmamap_t dmamap) 3145 { 3146 int i; 3147 for (i = 0; i < dmamap->dm_nsegs; i++) { 3148 if (dmamap->dm_segs[i].ds_len < 4) { 3149 printf("%s: segment too short\n", __func__); 3150 return 1; 3151 } 3152 } 3153 return 0; 3154 } 3155 3156 /* TBD factor with atw_start */ 3157 static struct mbuf * 3158 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 3159 u_int ndescfree, const char *dvname) 3160 { 3161 int first, rc; 3162 struct mbuf *m, *m0; 3163 3164 m0 = chain; 3165 3166 /* 3167 * Load the DMA map. Copy and try (once) again if the packet 3168 * didn't fit in the alloted number of segments. 3169 */ 3170 for (first = 1; 3171 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 3172 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 3173 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 3174 first = 0) { 3175 if (rc == 0) 3176 bus_dmamap_unload(dmat, dmam); 3177 MGETHDR(m, M_DONTWAIT, MT_DATA); 3178 if (m == NULL) { 3179 printf("%s: unable to allocate Tx mbuf\n", 3180 dvname); 3181 break; 3182 } 3183 if (m0->m_pkthdr.len > MHLEN) { 3184 MCLGET(m, M_DONTWAIT); 3185 if ((m->m_flags & M_EXT) == 0) { 3186 printf("%s: cannot allocate Tx cluster\n", 3187 dvname); 3188 m_freem(m); 3189 break; 3190 } 3191 } 3192 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3193 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3194 m_freem(m0); 3195 m0 = m; 3196 m = NULL; 3197 } 3198 if (rc != 0) { 3199 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 3200 m_freem(m0); 3201 return NULL; 3202 } else if (rtw_seg_too_short(dmam)) { 3203 printf("%s: cannot load Tx buffer, segment too short\n", 3204 dvname); 3205 bus_dmamap_unload(dmat, dmam); 3206 m_freem(m0); 3207 return NULL; 3208 } else if (dmam->dm_nsegs > ndescfree) { 3209 printf("%s: too many tx segments\n", dvname); 3210 bus_dmamap_unload(dmat, dmam); 3211 m_freem(m0); 3212 return NULL; 3213 } 3214 return m0; 3215 } 3216 3217 #ifdef RTW_DEBUG 3218 static void 3219 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3220 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3221 { 3222 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3223 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] next %#08x " 3224 "buf %#08x ctl0 %#08x ctl1 %#08x len %#08x\n", 3225 sc->sc_dev.dv_xname, ts, action, desc, 3226 le32toh(td->td_buf), le32toh(td->td_next), 3227 le32toh(td->td_ctl0), le32toh(td->td_ctl1), 3228 le32toh(td->td_len))); 3229 } 3230 #endif /* RTW_DEBUG */ 3231 3232 static void 3233 rtw_start(struct ifnet *ifp) 3234 { 3235 uint8_t tppoll; 3236 int desc, i, lastdesc, npkt, rate; 3237 uint32_t proto_ctl0, ctl0, ctl1; 3238 bus_dmamap_t dmamap; 3239 struct ieee80211com *ic; 3240 struct ieee80211_duration *d0; 3241 struct ieee80211_frame_min *wh; 3242 struct ieee80211_node *ni = NULL; /* XXX: GCC */ 3243 struct mbuf *m0; 3244 struct rtw_softc *sc; 3245 struct rtw_txsoft_blk *tsb = NULL; /* XXX: GCC */ 3246 struct rtw_txdesc_blk *tdb = NULL; /* XXX: GCC */ 3247 struct rtw_txsoft *ts; 3248 struct rtw_txdesc *td; 3249 struct ieee80211_key *k; 3250 3251 sc = (struct rtw_softc *)ifp->if_softc; 3252 ic = &sc->sc_ic; 3253 3254 DPRINTF(sc, RTW_DEBUG_XMIT, 3255 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3256 3257 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3258 goto out; 3259 3260 /* XXX do real rate control */ 3261 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3262 3263 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3264 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3265 3266 for (;;) { 3267 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3268 continue; 3269 if (m0 == NULL) 3270 break; 3271 3272 wh = mtod(m0, struct ieee80211_frame_min *); 3273 3274 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3275 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3276 m_freem(m0); 3277 break; 3278 } else 3279 k = NULL; 3280 3281 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3282 3283 dmamap = ts->ts_dmamap; 3284 3285 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3286 tdb->tdb_nfree, sc->sc_dev.dv_xname); 3287 3288 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3289 DPRINTF(sc, RTW_DEBUG_XMIT, 3290 ("%s: fail dmamap load\n", __func__)); 3291 goto post_dequeue_err; 3292 } 3293 3294 /* Note well: rtw_dmamap_load_txbuf may have created 3295 * a new chain, so we must find the header once 3296 * more. 3297 */ 3298 wh = mtod(m0, struct ieee80211_frame_min *); 3299 3300 /* XXX do real rate control */ 3301 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3302 IEEE80211_FC0_TYPE_MGT) 3303 rate = 2; 3304 else 3305 rate = MAX(2, ieee80211_get_rate(ni)); 3306 3307 #ifdef RTW_DEBUG 3308 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3309 (IFF_DEBUG|IFF_LINK2)) { 3310 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3311 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3312 : sizeof(wh), 3313 rate, 0); 3314 } 3315 #endif /* RTW_DEBUG */ 3316 ctl0 = proto_ctl0 | 3317 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3318 3319 switch (rate) { 3320 default: 3321 case 2: 3322 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3323 break; 3324 case 4: 3325 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3326 break; 3327 case 11: 3328 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3329 break; 3330 case 22: 3331 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3332 break; 3333 } 3334 /* XXX >= ? Compare after fragmentation? */ 3335 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3336 ctl0 |= RTW_TXCTL0_RTSEN; 3337 3338 /* XXX Sometimes writes a bogus keyid; h/w doesn't 3339 * seem to care, since we don't activate h/w Tx 3340 * encryption. 3341 */ 3342 if (k != NULL) { 3343 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3344 RTW_TXCTL0_KEYID_MASK; 3345 } 3346 3347 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3348 IEEE80211_FC0_TYPE_MGT) { 3349 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3350 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3351 IEEE80211_FC0_SUBTYPE_BEACON) 3352 ctl0 |= RTW_TXCTL0_BEACON; 3353 } 3354 3355 if (ieee80211_compute_duration(wh, k, m0->m_pkthdr.len, 3356 ic->ic_flags, ic->ic_fragthreshold, 3357 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3358 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3359 (IFF_DEBUG|IFF_LINK2)) == -1) { 3360 DPRINTF(sc, RTW_DEBUG_XMIT, 3361 ("%s: fail compute duration\n", __func__)); 3362 goto post_load_err; 3363 } 3364 3365 d0 = &ts->ts_d0; 3366 3367 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3368 3369 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3370 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3371 3372 if (d0->d_residue) 3373 ctl1 |= RTW_TXCTL1_LENGEXT; 3374 3375 /* TBD fragmentation */ 3376 3377 ts->ts_first = tdb->tdb_next; 3378 3379 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3380 BUS_DMASYNC_PREWRITE); 3381 3382 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3383 3384 #if NBPFILTER > 0 3385 if (ic->ic_rawbpf != NULL) 3386 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3387 3388 if (sc->sc_radiobpf != NULL) { 3389 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3390 3391 rt->rt_flags = 0; 3392 rt->rt_rate = rate; 3393 3394 bpf_mtap2(sc->sc_radiobpf, (caddr_t)rt, 3395 sizeof(sc->sc_txtapu), m0); 3396 } 3397 #endif /* NPBFILTER > 0 */ 3398 3399 for (i = 0, lastdesc = desc = ts->ts_first; 3400 i < dmamap->dm_nsegs; 3401 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3402 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3403 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3404 ("%s: seg too long\n", __func__)); 3405 goto post_load_err; 3406 } 3407 td = &tdb->tdb_desc[desc]; 3408 td->td_ctl0 = htole32(ctl0); 3409 if (i != 0) 3410 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3411 td->td_ctl1 = htole32(ctl1); 3412 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3413 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3414 lastdesc = desc; 3415 #ifdef RTW_DEBUG 3416 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3417 #endif /* RTW_DEBUG */ 3418 } 3419 3420 KASSERT(desc < tdb->tdb_ndesc); 3421 3422 ts->ts_ni = ni; 3423 KASSERT(ni != NULL); 3424 ts->ts_mbuf = m0; 3425 ts->ts_last = lastdesc; 3426 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3427 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3428 htole32(RTW_TXCTL0_FS); 3429 3430 #ifdef RTW_DEBUG 3431 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3432 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3433 #endif /* RTW_DEBUG */ 3434 3435 tdb->tdb_nfree -= dmamap->dm_nsegs; 3436 tdb->tdb_next = desc; 3437 3438 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3439 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3440 3441 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3442 htole32(RTW_TXCTL0_OWN); 3443 3444 #ifdef RTW_DEBUG 3445 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3446 #endif /* RTW_DEBUG */ 3447 3448 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3449 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3450 3451 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3452 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3453 3454 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) 3455 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3456 tsb->tsb_tx_timer = 5; 3457 ifp->if_timer = 1; 3458 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3459 tppoll &= ~RTW_TPPOLL_SALL; 3460 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL; 3461 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3462 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3463 } 3464 out: 3465 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3466 return; 3467 post_load_err: 3468 bus_dmamap_unload(sc->sc_dmat, dmamap); 3469 m_freem(m0); 3470 post_dequeue_err: 3471 ieee80211_free_node(ni); 3472 return; 3473 } 3474 3475 static void 3476 rtw_idle(struct rtw_regs *regs) 3477 { 3478 int active; 3479 3480 /* request stop DMA; wait for packets to stop transmitting. */ 3481 3482 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3483 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL); 3484 3485 for (active = 0; active < 300 && 3486 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0; active++) 3487 DELAY(10); 3488 printf("%s: transmit DMA idle in %dus\n", __func__, active * 10); 3489 } 3490 3491 static void 3492 rtw_watchdog(struct ifnet *ifp) 3493 { 3494 int pri, tx_timeouts = 0; 3495 struct rtw_softc *sc; 3496 struct rtw_txsoft_blk *tsb; 3497 3498 sc = ifp->if_softc; 3499 3500 ifp->if_timer = 0; 3501 3502 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 3503 return; 3504 3505 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3506 tsb = &sc->sc_txsoft_blk[pri]; 3507 3508 if (tsb->tsb_tx_timer == 0) 3509 continue; 3510 else if (--tsb->tsb_tx_timer == 0) { 3511 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3512 continue; 3513 printf("%s: transmit timeout, priority %d\n", 3514 ifp->if_xname, pri); 3515 ifp->if_oerrors++; 3516 tx_timeouts++; 3517 } else 3518 ifp->if_timer = 1; 3519 } 3520 3521 if (tx_timeouts > 0) { 3522 /* Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr, 3523 * reset s/w tx-ring pointers, and start transmission. 3524 * 3525 * TBD Stop/restart just the broken rings? 3526 */ 3527 rtw_idle(&sc->sc_regs); 3528 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 0); 3529 rtw_txdescs_reset(sc); 3530 rtw_io_enable(&sc->sc_regs, RTW_CR_TE, 1); 3531 rtw_txring_fixup(sc); 3532 rtw_start(ifp); 3533 } 3534 ieee80211_watchdog(&sc->sc_ic); 3535 return; 3536 } 3537 3538 static void 3539 rtw_next_scan(void *arg) 3540 { 3541 struct ieee80211com *ic = arg; 3542 int s; 3543 3544 /* don't call rtw_start w/o network interrupts blocked */ 3545 s = splnet(); 3546 if (ic->ic_state == IEEE80211_S_SCAN) 3547 ieee80211_next_scan(ic); 3548 splx(s); 3549 } 3550 3551 static void 3552 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3553 { 3554 uint16_t bcnitv, bintritv, intval; 3555 int i; 3556 struct rtw_regs *regs = &sc->sc_regs; 3557 3558 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3559 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3560 3561 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3562 3563 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3564 3565 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); 3566 3567 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3568 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); 3569 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3570 /* interrupt host 1ms before the TBTT */ 3571 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV; 3572 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV); 3573 RTW_WRITE16(regs, RTW_BINTRITV, bintritv); 3574 /* magic from Linux */ 3575 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND)); 3576 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); 3577 rtw_set_access(regs, RTW_ACCESS_NONE); 3578 3579 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 3580 } 3581 3582 /* Synchronize the hardware state with the software state. */ 3583 static int 3584 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3585 { 3586 struct ifnet *ifp = ic->ic_ifp; 3587 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3588 enum ieee80211_state ostate; 3589 int error; 3590 3591 ostate = ic->ic_state; 3592 3593 rtw_led_newstate(sc, nstate); 3594 3595 if (nstate == IEEE80211_S_INIT) { 3596 callout_stop(&sc->sc_scan_ch); 3597 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3598 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3599 } 3600 3601 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3602 rtw_pwrstate(sc, RTW_ON); 3603 3604 if ((error = rtw_tune(sc)) != 0) 3605 return error; 3606 3607 switch (nstate) { 3608 case IEEE80211_S_INIT: 3609 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3610 break; 3611 case IEEE80211_S_SCAN: 3612 if (ostate != IEEE80211_S_SCAN) { 3613 (void)memset(ic->ic_bss->ni_bssid, 0, 3614 IEEE80211_ADDR_LEN); 3615 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3616 } 3617 3618 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3619 rtw_next_scan, ic); 3620 3621 break; 3622 case IEEE80211_S_RUN: 3623 switch (ic->ic_opmode) { 3624 case IEEE80211_M_HOSTAP: 3625 case IEEE80211_M_IBSS: 3626 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3627 /*FALLTHROUGH*/ 3628 case IEEE80211_M_AHDEMO: 3629 case IEEE80211_M_STA: 3630 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3631 ic->ic_bss->ni_intval); 3632 break; 3633 case IEEE80211_M_MONITOR: 3634 break; 3635 } 3636 rtw_set_nettype(sc, ic->ic_opmode); 3637 break; 3638 case IEEE80211_S_ASSOC: 3639 case IEEE80211_S_AUTH: 3640 break; 3641 } 3642 3643 if (nstate != IEEE80211_S_SCAN) 3644 callout_stop(&sc->sc_scan_ch); 3645 3646 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3647 } 3648 3649 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3650 static uint64_t 3651 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3652 { 3653 uint32_t tsftl, tsfth; 3654 3655 tsfth = RTW_READ(regs, RTW_TSFTRH); 3656 tsftl = RTW_READ(regs, RTW_TSFTRL); 3657 if (tsftl < rstamp) /* Compensate for rollover. */ 3658 tsfth--; 3659 return ((uint64_t)tsfth << 32) | rstamp; 3660 } 3661 3662 static void 3663 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3664 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3665 { 3666 struct ifnet *ifp = ic->ic_ifp; 3667 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3668 3669 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3670 3671 switch (subtype) { 3672 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3673 case IEEE80211_FC0_SUBTYPE_BEACON: 3674 if (ic->ic_opmode == IEEE80211_M_IBSS && 3675 ic->ic_state == IEEE80211_S_RUN) { 3676 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp); 3677 if (le64toh(ni->ni_tstamp.tsf) >= tsf) 3678 (void)ieee80211_ibss_merge(ni); 3679 } 3680 break; 3681 default: 3682 break; 3683 } 3684 return; 3685 } 3686 3687 static struct ieee80211_node * 3688 rtw_node_alloc(struct ieee80211_node_table *nt) 3689 { 3690 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3691 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3692 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3693 3694 DPRINTF(sc, RTW_DEBUG_NODE, 3695 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3696 return ni; 3697 } 3698 3699 static void 3700 rtw_node_free(struct ieee80211_node *ni) 3701 { 3702 struct ieee80211com *ic = ni->ni_ic; 3703 struct ifnet *ifp = ic->ic_ifp; 3704 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3705 3706 DPRINTF(sc, RTW_DEBUG_NODE, 3707 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3708 ether_sprintf(ni->ni_bssid))); 3709 (*sc->sc_mtbl.mt_node_free)(ni); 3710 } 3711 3712 static int 3713 rtw_media_change(struct ifnet *ifp) 3714 { 3715 int error; 3716 3717 error = ieee80211_media_change(ifp); 3718 if (error == ENETRESET) { 3719 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3720 (IFF_RUNNING|IFF_UP)) 3721 rtw_init(ifp); /* XXX lose error */ 3722 error = 0; 3723 } 3724 return error; 3725 } 3726 3727 static void 3728 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3729 { 3730 struct rtw_softc *sc = ifp->if_softc; 3731 3732 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3733 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3734 imr->ifm_status = 0; 3735 return; 3736 } 3737 ieee80211_media_status(ifp, imr); 3738 } 3739 3740 void 3741 rtw_power(int why, void *arg) 3742 { 3743 struct rtw_softc *sc = arg; 3744 struct ifnet *ifp = &sc->sc_if; 3745 int s; 3746 3747 DPRINTF(sc, RTW_DEBUG_PWR, 3748 ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3749 3750 s = splnet(); 3751 switch (why) { 3752 case PWR_STANDBY: 3753 /* XXX do nothing. */ 3754 break; 3755 case PWR_SUSPEND: 3756 rtw_stop(ifp, 0); 3757 if (sc->sc_power != NULL) 3758 (*sc->sc_power)(sc, why); 3759 break; 3760 case PWR_RESUME: 3761 if (ifp->if_flags & IFF_UP) { 3762 if (sc->sc_power != NULL) 3763 (*sc->sc_power)(sc, why); 3764 rtw_init(ifp); 3765 } 3766 break; 3767 case PWR_SOFTSUSPEND: 3768 case PWR_SOFTSTANDBY: 3769 case PWR_SOFTRESUME: 3770 break; 3771 } 3772 splx(s); 3773 } 3774 3775 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 3776 void 3777 rtw_shutdown(void *arg) 3778 { 3779 struct rtw_softc *sc = arg; 3780 3781 rtw_stop(&sc->sc_if, 1); 3782 } 3783 3784 static inline void 3785 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3786 { 3787 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3788 ifp->if_softc = softc; 3789 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3790 IFF_NOTRAILERS; 3791 ifp->if_ioctl = rtw_ioctl; 3792 ifp->if_start = rtw_start; 3793 ifp->if_watchdog = rtw_watchdog; 3794 ifp->if_init = rtw_init; 3795 ifp->if_stop = rtw_stop; 3796 } 3797 3798 static inline void 3799 rtw_set80211props(struct ieee80211com *ic) 3800 { 3801 int nrate; 3802 ic->ic_phytype = IEEE80211_T_DS; 3803 ic->ic_opmode = IEEE80211_M_STA; 3804 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3805 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 3806 3807 nrate = 0; 3808 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3809 IEEE80211_RATE_BASIC | 2; 3810 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3811 IEEE80211_RATE_BASIC | 4; 3812 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3813 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3814 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3815 } 3816 3817 static inline void 3818 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3819 { 3820 mtbl->mt_newstate = ic->ic_newstate; 3821 ic->ic_newstate = rtw_newstate; 3822 3823 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3824 ic->ic_recv_mgmt = rtw_recv_mgmt; 3825 3826 mtbl->mt_node_free = ic->ic_node_free; 3827 ic->ic_node_free = rtw_node_free; 3828 3829 mtbl->mt_node_alloc = ic->ic_node_alloc; 3830 ic->ic_node_alloc = rtw_node_alloc; 3831 3832 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3833 ic->ic_crypto.cs_key_set = rtw_key_set; 3834 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3835 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3836 } 3837 3838 static inline void 3839 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 3840 void *arg) 3841 { 3842 /* 3843 * Make sure the interface is shutdown during reboot. 3844 */ 3845 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 3846 if (hooks->rh_shutdown == NULL) 3847 printf("%s: WARNING: unable to establish shutdown hook\n", 3848 dvname); 3849 3850 /* 3851 * Add a suspend hook to make sure we come back up after a 3852 * resume. 3853 */ 3854 hooks->rh_power = powerhook_establish(dvname, rtw_power, arg); 3855 if (hooks->rh_power == NULL) 3856 printf("%s: WARNING: unable to establish power hook\n", 3857 dvname); 3858 } 3859 3860 static inline void 3861 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 3862 void *arg) 3863 { 3864 if (hooks->rh_shutdown != NULL) 3865 shutdownhook_disestablish(hooks->rh_shutdown); 3866 3867 if (hooks->rh_power != NULL) 3868 powerhook_disestablish(hooks->rh_power); 3869 } 3870 3871 static inline void 3872 rtw_init_radiotap(struct rtw_softc *sc) 3873 { 3874 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3875 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3876 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT); 3877 3878 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3879 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3880 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3881 } 3882 3883 static int 3884 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3885 { 3886 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3887 SIMPLEQ_INIT(&tsb->tsb_freeq); 3888 tsb->tsb_ndesc = qlen; 3889 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3890 M_NOWAIT); 3891 if (tsb->tsb_desc == NULL) 3892 return ENOMEM; 3893 return 0; 3894 } 3895 3896 static void 3897 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3898 { 3899 int pri; 3900 struct rtw_txsoft_blk *tsb; 3901 3902 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3903 tsb = &sc->sc_txsoft_blk[pri]; 3904 free(tsb->tsb_desc, M_DEVBUF); 3905 tsb->tsb_desc = NULL; 3906 } 3907 } 3908 3909 static int 3910 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3911 { 3912 int pri, rc = 0; 3913 int qlen[RTW_NTXPRI] = 3914 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3915 struct rtw_txsoft_blk *tsbs; 3916 3917 tsbs = sc->sc_txsoft_blk; 3918 3919 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3920 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3921 if (rc != 0) 3922 break; 3923 } 3924 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3925 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3926 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3927 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3928 return rc; 3929 } 3930 3931 static void 3932 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3933 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3934 { 3935 tdb->tdb_ndesc = ndesc; 3936 tdb->tdb_desc = desc; 3937 tdb->tdb_physbase = physbase; 3938 tdb->tdb_ofs = ofs; 3939 3940 (void)memset(tdb->tdb_desc, 0, 3941 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3942 3943 rtw_txdesc_blk_init(tdb); 3944 tdb->tdb_next = 0; 3945 } 3946 3947 static void 3948 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3949 { 3950 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3951 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3952 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3953 3954 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3955 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3956 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3957 3958 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3959 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3960 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3961 3962 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3963 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3964 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3965 } 3966 3967 static struct rtw_rf * 3968 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3969 { 3970 rtw_rf_write_t rf_write; 3971 struct rtw_rf *rf; 3972 3973 switch (rfchipid) { 3974 default: 3975 rf_write = rtw_rf_hostwrite; 3976 break; 3977 case RTW_RFCHIPID_INTERSIL: 3978 case RTW_RFCHIPID_PHILIPS: 3979 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3980 case RTW_RFCHIPID_RFMD: 3981 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3982 break; 3983 } 3984 3985 switch (rfchipid) { 3986 case RTW_RFCHIPID_GCT: 3987 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0); 3988 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3989 break; 3990 case RTW_RFCHIPID_MAXIM: 3991 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3992 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3993 break; 3994 case RTW_RFCHIPID_PHILIPS: 3995 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3996 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3997 break; 3998 case RTW_RFCHIPID_RFMD: 3999 /* XXX RFMD has no RF constructor */ 4000 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 4001 /*FALLTHROUGH*/ 4002 default: 4003 return NULL; 4004 } 4005 rf->rf_continuous_tx_cb = 4006 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 4007 rf->rf_continuous_tx_arg = (void *)sc; 4008 return rf; 4009 } 4010 4011 /* Revision C and later use a different PHY delay setting than 4012 * revisions A and B. 4013 */ 4014 static uint8_t 4015 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 4016 { 4017 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 4018 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 4019 4020 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); 4021 4022 RTW_WRITE(regs, RTW_RCR, REVAB); 4023 RTW_WBW(regs, RTW_RCR, RTW_RCR); 4024 RTW_WRITE(regs, RTW_RCR, REVC); 4025 4026 RTW_WBR(regs, RTW_RCR, RTW_RCR); 4027 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 4028 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 4029 4030 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 4031 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 4032 4033 return phydelay; 4034 #undef REVC 4035 } 4036 4037 void 4038 rtw_attach(struct rtw_softc *sc) 4039 { 4040 struct ifnet *ifp = &sc->sc_if; 4041 struct ieee80211com *ic = &sc->sc_ic; 4042 struct rtw_txsoft_blk *tsb; 4043 int pri, rc; 4044 4045 rtw_cipher_wep = ieee80211_cipher_wep; 4046 rtw_cipher_wep.ic_decap = rtw_wep_decap; 4047 4048 NEXT_ATTACH_STATE(sc, DETACHED); 4049 4050 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 4051 case RTW_TCR_HWVERID_F: 4052 sc->sc_hwverid = 'F'; 4053 break; 4054 case RTW_TCR_HWVERID_D: 4055 sc->sc_hwverid = 'D'; 4056 break; 4057 default: 4058 sc->sc_hwverid = '?'; 4059 break; 4060 } 4061 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, 4062 sc->sc_hwverid); 4063 4064 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 4065 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 4066 0); 4067 4068 if (rc != 0) { 4069 printf("%s: could not allocate hw descriptors, error %d\n", 4070 sc->sc_dev.dv_xname, rc); 4071 goto err; 4072 } 4073 4074 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 4075 4076 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 4077 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 4078 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 4079 4080 if (rc != 0) { 4081 printf("%s: could not map hw descriptors, error %d\n", 4082 sc->sc_dev.dv_xname, rc); 4083 goto err; 4084 } 4085 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 4086 4087 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 4088 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 4089 4090 if (rc != 0) { 4091 printf("%s: could not create DMA map for hw descriptors, " 4092 "error %d\n", sc->sc_dev.dv_xname, rc); 4093 goto err; 4094 } 4095 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 4096 4097 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 4098 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 4099 4100 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4101 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 4102 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 4103 } 4104 4105 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 4106 sizeof(struct rtw_descs), NULL, 0); 4107 4108 if (rc != 0) { 4109 printf("%s: could not load DMA map for hw descriptors, " 4110 "error %d\n", sc->sc_dev.dv_xname, rc); 4111 goto err; 4112 } 4113 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 4114 4115 if (rtw_txsoft_blk_setup_all(sc) != 0) 4116 goto err; 4117 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 4118 4119 rtw_txdesc_blk_setup_all(sc); 4120 4121 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 4122 4123 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 4124 4125 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4126 tsb = &sc->sc_txsoft_blk[pri]; 4127 4128 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 4129 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 4130 printf("%s: could not load DMA map for " 4131 "hw tx descriptors, error %d\n", 4132 sc->sc_dev.dv_xname, rc); 4133 goto err; 4134 } 4135 } 4136 4137 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 4138 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 4139 RTW_RXQLEN)) != 0) { 4140 printf("%s: could not load DMA map for hw rx descriptors, " 4141 "error %d\n", sc->sc_dev.dv_xname, rc); 4142 goto err; 4143 } 4144 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 4145 4146 /* Reset the chip to a known state. */ 4147 if (rtw_reset(sc) != 0) 4148 goto err; 4149 NEXT_ATTACH_STATE(sc, FINISH_RESET); 4150 4151 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 4152 4153 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 4154 sc->sc_flags |= RTW_F_9356SROM; 4155 4156 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 4157 sc->sc_dev.dv_xname) != 0) 4158 goto err; 4159 4160 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 4161 4162 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 4163 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 4164 sc->sc_dev.dv_xname) != 0) { 4165 printf("%s: attach failed, malformed serial ROM\n", 4166 sc->sc_dev.dv_xname); 4167 goto err; 4168 } 4169 4170 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 4171 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 4172 4173 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 4174 4175 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 4176 4177 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 4178 sc->sc_flags & RTW_F_DIGPHY); 4179 4180 if (sc->sc_rf == NULL) { 4181 printf("%s: attach failed, could not attach RF\n", 4182 sc->sc_dev.dv_xname); 4183 goto err; 4184 } 4185 4186 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 4187 4188 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4189 4190 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4191 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 4192 4193 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4194 rtw_identify_country(&sc->sc_regs, &sc->sc_locale); 4195 4196 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 4197 sc->sc_dev.dv_xname); 4198 4199 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4200 sc->sc_dev.dv_xname) != 0) 4201 goto err; 4202 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4203 4204 rtw_setifprops(ifp, sc->sc_dev.dv_xname, (void*)sc); 4205 4206 IFQ_SET_READY(&ifp->if_snd); 4207 4208 sc->sc_ic.ic_ifp = ifp; 4209 rtw_set80211props(&sc->sc_ic); 4210 4211 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4212 4213 /* 4214 * Call MI attach routines. 4215 */ 4216 if_attach(ifp); 4217 ieee80211_ifattach(&sc->sc_ic); 4218 4219 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4220 4221 /* possibly we should fill in our own sc_send_prresp, since 4222 * the RTL8180 is probably sending probe responses in ad hoc 4223 * mode. 4224 */ 4225 4226 /* complete initialization */ 4227 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4228 callout_init(&sc->sc_scan_ch); 4229 4230 rtw_init_radiotap(sc); 4231 4232 #if NBPFILTER > 0 4233 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4234 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4235 #endif 4236 4237 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 4238 4239 NEXT_ATTACH_STATE(sc, FINISHED); 4240 4241 ieee80211_announce(ic); 4242 return; 4243 err: 4244 rtw_detach(sc); 4245 return; 4246 } 4247 4248 int 4249 rtw_detach(struct rtw_softc *sc) 4250 { 4251 struct ifnet *ifp = &sc->sc_if; 4252 int pri; 4253 4254 sc->sc_flags |= RTW_F_INVALID; 4255 4256 switch (sc->sc_attach_state) { 4257 case FINISHED: 4258 rtw_stop(ifp, 1); 4259 4260 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 4261 (void*)sc); 4262 callout_stop(&sc->sc_scan_ch); 4263 ieee80211_ifdetach(&sc->sc_ic); 4264 if_detach(ifp); 4265 break; 4266 case FINISH_ID_STA: 4267 case FINISH_RF_ATTACH: 4268 rtw_rf_destroy(sc->sc_rf); 4269 sc->sc_rf = NULL; 4270 /*FALLTHROUGH*/ 4271 case FINISH_PARSE_SROM: 4272 case FINISH_READ_SROM: 4273 rtw_srom_free(&sc->sc_srom); 4274 /*FALLTHROUGH*/ 4275 case FINISH_RESET: 4276 case FINISH_RXMAPS_CREATE: 4277 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4278 RTW_RXQLEN); 4279 /*FALLTHROUGH*/ 4280 case FINISH_TXMAPS_CREATE: 4281 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4282 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4283 sc->sc_txsoft_blk[pri].tsb_desc, 4284 sc->sc_txsoft_blk[pri].tsb_ndesc); 4285 } 4286 /*FALLTHROUGH*/ 4287 case FINISH_TXDESCBLK_SETUP: 4288 case FINISH_TXCTLBLK_SETUP: 4289 rtw_txsoft_blk_cleanup_all(sc); 4290 /*FALLTHROUGH*/ 4291 case FINISH_DESCMAP_LOAD: 4292 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4293 /*FALLTHROUGH*/ 4294 case FINISH_DESCMAP_CREATE: 4295 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4296 /*FALLTHROUGH*/ 4297 case FINISH_DESC_MAP: 4298 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 4299 sizeof(struct rtw_descs)); 4300 /*FALLTHROUGH*/ 4301 case FINISH_DESC_ALLOC: 4302 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4303 sc->sc_desc_nsegs); 4304 /*FALLTHROUGH*/ 4305 case DETACHED: 4306 NEXT_ATTACH_STATE(sc, DETACHED); 4307 break; 4308 } 4309 return 0; 4310 } 4311 4312 int 4313 rtw_activate(struct device *self, enum devact act) 4314 { 4315 struct rtw_softc *sc = (struct rtw_softc *)self; 4316 int rc = 0, s; 4317 4318 s = splnet(); 4319 switch (act) { 4320 case DVACT_ACTIVATE: 4321 rc = EOPNOTSUPP; 4322 break; 4323 4324 case DVACT_DEACTIVATE: 4325 if_deactivate(&sc->sc_if); 4326 break; 4327 } 4328 splx(s); 4329 return rc; 4330 } 4331
Indexes created Tue Sep 30 07:10:03 GMT 2025