rtw.c revision 1.88
1 /* $NetBSD: rtw.c,v 1.88 2007/05/29 18:38:20 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.88 2007/05/29 18:38:20 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/time.h> 49 #include <sys/types.h> 50 51 #include <machine/endian.h> 52 #include <machine/bus.h> 53 #include <machine/intr.h> /* splnet */ 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <dev/ic/rtwreg.h> 70 #include <dev/ic/rtwvar.h> 71 #include <dev/ic/rtwphyio.h> 72 #include <dev/ic/rtwphy.h> 73 74 #include <dev/ic/smc93cx6var.h> 75 76 #define KASSERT2(__cond, __msg) \ 77 do { \ 78 if (!(__cond)) \ 79 panic __msg ; \ 80 } while (0) 81 82 static int rtw_rfprog_fallback = 0; 83 static int rtw_host_rfio = 0; 84 85 #ifdef RTW_DEBUG 86 int rtw_debug = 0; 87 static int rtw_rxbufs_limit = RTW_RXQLEN; 88 #endif /* RTW_DEBUG */ 89 90 #define NEXT_ATTACH_STATE(sc, state) do { \ 91 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 92 ("%s: attach state %s\n", __func__, #state)); \ 93 sc->sc_attach_state = state; \ 94 } while (0) 95 96 int rtw_dwelltime = 200; /* milliseconds */ 97 static struct ieee80211_cipher rtw_cipher_wep; 98 99 static void rtw_start(struct ifnet *); 100 static void rtw_reset_oactive(struct rtw_softc *); 101 static struct mbuf *rtw_beacon_alloc(struct rtw_softc *, 102 struct ieee80211_node *); 103 static u_int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *); 104 105 static void rtw_io_enable(struct rtw_softc *, uint8_t, int); 106 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 107 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 108 const u_int8_t[IEEE80211_ADDR_LEN]); 109 static void rtw_key_update_end(struct ieee80211com *); 110 static void rtw_key_update_begin(struct ieee80211com *); 111 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 112 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 113 114 static void rtw_led_attach(struct rtw_led_state *, void *); 115 static void rtw_led_init(struct rtw_regs *); 116 static void rtw_led_slowblink(void *); 117 static void rtw_led_fastblink(void *); 118 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 119 120 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 121 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 122 #ifdef RTW_DEBUG 123 static void rtw_dump_rings(struct rtw_softc *sc); 124 static void rtw_print_txdesc(struct rtw_softc *, const char *, 125 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 126 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 127 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 128 #endif /* RTW_DEBUG */ 129 #ifdef RTW_DIAG 130 static void rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln); 131 #endif /* RTW_DIAG */ 132 133 /* 134 * Setup sysctl(3) MIB, hw.rtw.* 135 * 136 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 137 */ 138 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 139 { 140 int rc; 141 const struct sysctlnode *cnode, *rnode; 142 143 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 144 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 145 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 146 goto err; 147 148 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 149 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 150 "Realtek RTL818x 802.11 controls", 151 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 152 goto err; 153 154 #ifdef RTW_DEBUG 155 /* control debugging printfs */ 156 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 157 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 158 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 159 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 160 CTL_CREATE, CTL_EOL)) != 0) 161 goto err; 162 163 /* Limit rx buffers, for simulating resource exhaustion. */ 164 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 165 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 166 "rxbufs_limit", 167 SYSCTL_DESCR("Set rx buffers limit"), 168 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 169 CTL_CREATE, CTL_EOL)) != 0) 170 goto err; 171 172 #endif /* RTW_DEBUG */ 173 /* set fallback RF programming method */ 174 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 175 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 176 "rfprog_fallback", 177 SYSCTL_DESCR("Set fallback RF programming method"), 178 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 179 CTL_CREATE, CTL_EOL)) != 0) 180 goto err; 181 182 /* force host to control RF I/O bus */ 183 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 184 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 185 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 186 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 187 CTL_CREATE, CTL_EOL)) != 0) 188 goto err; 189 190 return; 191 err: 192 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 193 } 194 195 static int 196 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 197 { 198 int error, t; 199 struct sysctlnode node; 200 201 node = *rnode; 202 t = *(int*)rnode->sysctl_data; 203 node.sysctl_data = &t; 204 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 205 if (error || newp == NULL) 206 return (error); 207 208 if (t < lower || t > upper) 209 return (EINVAL); 210 211 *(int*)rnode->sysctl_data = t; 212 213 return (0); 214 } 215 216 static int 217 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 218 { 219 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 220 __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 221 } 222 223 static int 224 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 225 { 226 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 227 } 228 229 #ifdef RTW_DEBUG 230 static int 231 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 232 { 233 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 234 0, RTW_DEBUG_MAX); 235 } 236 237 static int 238 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 239 { 240 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 241 0, RTW_RXQLEN); 242 } 243 244 static void 245 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 246 { 247 #define PRINTREG32(sc, reg) \ 248 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 249 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 250 dvname, reg, RTW_READ(regs, reg))) 251 252 #define PRINTREG16(sc, reg) \ 253 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 254 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 255 dvname, reg, RTW_READ16(regs, reg))) 256 257 #define PRINTREG8(sc, reg) \ 258 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 259 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 260 dvname, reg, RTW_READ8(regs, reg))) 261 262 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 263 264 PRINTREG32(regs, RTW_IDR0); 265 PRINTREG32(regs, RTW_IDR1); 266 PRINTREG32(regs, RTW_MAR0); 267 PRINTREG32(regs, RTW_MAR1); 268 PRINTREG32(regs, RTW_TSFTRL); 269 PRINTREG32(regs, RTW_TSFTRH); 270 PRINTREG32(regs, RTW_TLPDA); 271 PRINTREG32(regs, RTW_TNPDA); 272 PRINTREG32(regs, RTW_THPDA); 273 PRINTREG32(regs, RTW_TCR); 274 PRINTREG32(regs, RTW_RCR); 275 PRINTREG32(regs, RTW_TINT); 276 PRINTREG32(regs, RTW_TBDA); 277 PRINTREG32(regs, RTW_ANAPARM); 278 PRINTREG32(regs, RTW_BB); 279 PRINTREG32(regs, RTW_PHYCFG); 280 PRINTREG32(regs, RTW_WAKEUP0L); 281 PRINTREG32(regs, RTW_WAKEUP0H); 282 PRINTREG32(regs, RTW_WAKEUP1L); 283 PRINTREG32(regs, RTW_WAKEUP1H); 284 PRINTREG32(regs, RTW_WAKEUP2LL); 285 PRINTREG32(regs, RTW_WAKEUP2LH); 286 PRINTREG32(regs, RTW_WAKEUP2HL); 287 PRINTREG32(regs, RTW_WAKEUP2HH); 288 PRINTREG32(regs, RTW_WAKEUP3LL); 289 PRINTREG32(regs, RTW_WAKEUP3LH); 290 PRINTREG32(regs, RTW_WAKEUP3HL); 291 PRINTREG32(regs, RTW_WAKEUP3HH); 292 PRINTREG32(regs, RTW_WAKEUP4LL); 293 PRINTREG32(regs, RTW_WAKEUP4LH); 294 PRINTREG32(regs, RTW_WAKEUP4HL); 295 PRINTREG32(regs, RTW_WAKEUP4HH); 296 PRINTREG32(regs, RTW_DK0); 297 PRINTREG32(regs, RTW_DK1); 298 PRINTREG32(regs, RTW_DK2); 299 PRINTREG32(regs, RTW_DK3); 300 PRINTREG32(regs, RTW_RETRYCTR); 301 PRINTREG32(regs, RTW_RDSAR); 302 PRINTREG32(regs, RTW_FER); 303 PRINTREG32(regs, RTW_FEMR); 304 PRINTREG32(regs, RTW_FPSR); 305 PRINTREG32(regs, RTW_FFER); 306 307 /* 16-bit registers */ 308 PRINTREG16(regs, RTW_BRSR); 309 PRINTREG16(regs, RTW_IMR); 310 PRINTREG16(regs, RTW_ISR); 311 PRINTREG16(regs, RTW_BCNITV); 312 PRINTREG16(regs, RTW_ATIMWND); 313 PRINTREG16(regs, RTW_BINTRITV); 314 PRINTREG16(regs, RTW_ATIMTRITV); 315 PRINTREG16(regs, RTW_CRC16ERR); 316 PRINTREG16(regs, RTW_CRC0); 317 PRINTREG16(regs, RTW_CRC1); 318 PRINTREG16(regs, RTW_CRC2); 319 PRINTREG16(regs, RTW_CRC3); 320 PRINTREG16(regs, RTW_CRC4); 321 PRINTREG16(regs, RTW_CWR); 322 323 /* 8-bit registers */ 324 PRINTREG8(regs, RTW_CR); 325 PRINTREG8(regs, RTW_9346CR); 326 PRINTREG8(regs, RTW_CONFIG0); 327 PRINTREG8(regs, RTW_CONFIG1); 328 PRINTREG8(regs, RTW_CONFIG2); 329 PRINTREG8(regs, RTW_MSR); 330 PRINTREG8(regs, RTW_CONFIG3); 331 PRINTREG8(regs, RTW_CONFIG4); 332 PRINTREG8(regs, RTW_TESTR); 333 PRINTREG8(regs, RTW_PSR); 334 PRINTREG8(regs, RTW_SCR); 335 PRINTREG8(regs, RTW_PHYDELAY); 336 PRINTREG8(regs, RTW_CRCOUNT); 337 PRINTREG8(regs, RTW_PHYADDR); 338 PRINTREG8(regs, RTW_PHYDATAW); 339 PRINTREG8(regs, RTW_PHYDATAR); 340 PRINTREG8(regs, RTW_CONFIG5); 341 PRINTREG8(regs, RTW_TPPOLL); 342 343 PRINTREG16(regs, RTW_BSSID16); 344 PRINTREG32(regs, RTW_BSSID32); 345 #undef PRINTREG32 346 #undef PRINTREG16 347 #undef PRINTREG8 348 } 349 #endif /* RTW_DEBUG */ 350 351 void 352 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 353 { 354 struct rtw_regs *regs = &sc->sc_regs; 355 356 uint32_t tcr; 357 tcr = RTW_READ(regs, RTW_TCR); 358 tcr &= ~RTW_TCR_LBK_MASK; 359 if (enable) 360 tcr |= RTW_TCR_LBK_CONT; 361 else 362 tcr |= RTW_TCR_LBK_NORMAL; 363 RTW_WRITE(regs, RTW_TCR, tcr); 364 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 365 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 366 rtw_txdac_enable(sc, !enable); 367 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 368 rtw_set_access(regs, RTW_ACCESS_NONE); 369 } 370 371 #ifdef RTW_DEBUG 372 static const char * 373 rtw_access_string(enum rtw_access access) 374 { 375 switch (access) { 376 case RTW_ACCESS_NONE: 377 return "none"; 378 case RTW_ACCESS_CONFIG: 379 return "config"; 380 case RTW_ACCESS_ANAPARM: 381 return "anaparm"; 382 default: 383 return "unknown"; 384 } 385 } 386 #endif /* RTW_DEBUG */ 387 388 static void 389 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 390 { 391 KASSERT(/* naccess >= RTW_ACCESS_NONE && */ 392 naccess <= RTW_ACCESS_ANAPARM); 393 KASSERT(/* regs->r_access >= RTW_ACCESS_NONE && */ 394 regs->r_access <= RTW_ACCESS_ANAPARM); 395 396 if (naccess == regs->r_access) 397 return; 398 399 switch (naccess) { 400 case RTW_ACCESS_NONE: 401 switch (regs->r_access) { 402 case RTW_ACCESS_ANAPARM: 403 rtw_anaparm_enable(regs, 0); 404 /*FALLTHROUGH*/ 405 case RTW_ACCESS_CONFIG: 406 rtw_config0123_enable(regs, 0); 407 /*FALLTHROUGH*/ 408 case RTW_ACCESS_NONE: 409 break; 410 } 411 break; 412 case RTW_ACCESS_CONFIG: 413 switch (regs->r_access) { 414 case RTW_ACCESS_NONE: 415 rtw_config0123_enable(regs, 1); 416 /*FALLTHROUGH*/ 417 case RTW_ACCESS_CONFIG: 418 break; 419 case RTW_ACCESS_ANAPARM: 420 rtw_anaparm_enable(regs, 0); 421 break; 422 } 423 break; 424 case RTW_ACCESS_ANAPARM: 425 switch (regs->r_access) { 426 case RTW_ACCESS_NONE: 427 rtw_config0123_enable(regs, 1); 428 /*FALLTHROUGH*/ 429 case RTW_ACCESS_CONFIG: 430 rtw_anaparm_enable(regs, 1); 431 /*FALLTHROUGH*/ 432 case RTW_ACCESS_ANAPARM: 433 break; 434 } 435 break; 436 } 437 } 438 439 void 440 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 441 { 442 rtw_set_access1(regs, access); 443 RTW_DPRINTF(RTW_DEBUG_ACCESS, 444 ("%s: access %s -> %s\n", __func__, 445 rtw_access_string(regs->r_access), 446 rtw_access_string(access))); 447 regs->r_access = access; 448 } 449 450 /* 451 * Enable registers, switch register banks. 452 */ 453 void 454 rtw_config0123_enable(struct rtw_regs *regs, int enable) 455 { 456 uint8_t ecr; 457 ecr = RTW_READ8(regs, RTW_9346CR); 458 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 459 if (enable) 460 ecr |= RTW_9346CR_EEM_CONFIG; 461 else { 462 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 463 ecr |= RTW_9346CR_EEM_NORMAL; 464 } 465 RTW_WRITE8(regs, RTW_9346CR, ecr); 466 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 467 } 468 469 /* requires rtw_config0123_enable(, 1) */ 470 void 471 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 472 { 473 uint8_t cfg3; 474 475 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 476 cfg3 |= RTW_CONFIG3_CLKRUNEN; 477 if (enable) 478 cfg3 |= RTW_CONFIG3_PARMEN; 479 else 480 cfg3 &= ~RTW_CONFIG3_PARMEN; 481 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 482 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 483 } 484 485 /* requires rtw_anaparm_enable(, 1) */ 486 void 487 rtw_txdac_enable(struct rtw_softc *sc, int enable) 488 { 489 uint32_t anaparm; 490 struct rtw_regs *regs = &sc->sc_regs; 491 492 anaparm = RTW_READ(regs, RTW_ANAPARM); 493 if (enable) 494 anaparm &= ~RTW_ANAPARM_TXDACOFF; 495 else 496 anaparm |= RTW_ANAPARM_TXDACOFF; 497 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 498 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 499 } 500 501 static inline int 502 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 503 { 504 uint8_t cr; 505 int i; 506 507 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 508 509 RTW_WBR(regs, RTW_CR, RTW_CR); 510 511 for (i = 0; i < 1000; i++) { 512 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 513 RTW_DPRINTF(RTW_DEBUG_RESET, 514 ("%s: reset in %dus\n", dvname, i)); 515 return 0; 516 } 517 RTW_RBR(regs, RTW_CR, RTW_CR); 518 DELAY(10); /* 10us */ 519 } 520 521 printf("%s: reset failed\n", dvname); 522 return ETIMEDOUT; 523 } 524 525 static inline int 526 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 527 { 528 uint32_t tcr; 529 530 /* from Linux driver */ 531 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 532 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK); 533 534 RTW_WRITE(regs, RTW_TCR, tcr); 535 536 RTW_WBW(regs, RTW_CR, RTW_TCR); 537 538 return rtw_chip_reset1(regs, dvname); 539 } 540 541 static int 542 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen) 543 { 544 struct ieee80211_key keycopy; 545 546 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 547 548 keycopy = *k; 549 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 550 551 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, hdrlen); 552 } 553 554 static int 555 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 556 { 557 struct rtw_softc *sc = ic->ic_ifp->if_softc; 558 u_int keyix = k->wk_keyix; 559 560 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix)); 561 562 if (keyix >= IEEE80211_WEP_NKID) 563 return 0; 564 if (k->wk_keylen != 0) 565 sc->sc_flags &= ~RTW_F_DK_VALID; 566 567 return 1; 568 } 569 570 static int 571 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 572 const u_int8_t mac[IEEE80211_ADDR_LEN]) 573 { 574 struct rtw_softc *sc = ic->ic_ifp->if_softc; 575 576 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 577 578 if (k->wk_keyix >= IEEE80211_WEP_NKID) 579 return 0; 580 581 sc->sc_flags &= ~RTW_F_DK_VALID; 582 583 return 1; 584 } 585 586 static void 587 rtw_key_update_begin(struct ieee80211com *ic) 588 { 589 #ifdef RTW_DEBUG 590 struct ifnet *ifp = ic->ic_ifp; 591 struct rtw_softc *sc = ifp->if_softc; 592 #endif 593 594 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 595 } 596 597 static void 598 rtw_key_update_end(struct ieee80211com *ic) 599 { 600 struct ifnet *ifp = ic->ic_ifp; 601 struct rtw_softc *sc = ifp->if_softc; 602 603 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 604 605 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 || 606 (sc->sc_flags & RTW_F_ENABLED) == 0 || 607 (sc->sc_flags & RTW_F_INVALID) != 0) 608 return; 609 610 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 611 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 612 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 613 (ifp->if_flags & IFF_RUNNING) != 0); 614 } 615 616 static inline int 617 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k) 618 { 619 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 620 return 0; 621 622 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) || 623 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13); 624 } 625 626 static void 627 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 628 { 629 uint8_t psr, scr; 630 int i, keylen; 631 struct rtw_regs *regs; 632 union rtw_keys *rk; 633 634 regs = &sc->sc_regs; 635 rk = &sc->sc_keys; 636 637 (void)memset(rk, 0, sizeof(rk)); 638 639 /* Temporarily use software crypto for all keys. */ 640 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 641 if (wk[i].wk_cipher == &rtw_cipher_wep) 642 wk[i].wk_cipher = &ieee80211_cipher_wep; 643 } 644 645 rtw_set_access(regs, RTW_ACCESS_CONFIG); 646 647 psr = RTW_READ8(regs, RTW_PSR); 648 scr = RTW_READ8(regs, RTW_SCR); 649 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 650 651 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 652 goto out; 653 654 for (keylen = i = 0; i < IEEE80211_WEP_NKID; i++) { 655 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i])) 656 continue; 657 if (i == txkey) { 658 keylen = wk[i].wk_keylen; 659 break; 660 } 661 keylen = MAX(keylen, wk[i].wk_keylen); 662 } 663 664 if (keylen == 5) 665 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON; 666 else if (keylen == 13) 667 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON; 668 669 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 670 if (wk[i].wk_keylen != keylen || 671 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 672 continue; 673 /* h/w will decrypt, s/w still strips headers */ 674 wk[i].wk_cipher = &rtw_cipher_wep; 675 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 676 } 677 678 out: 679 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 680 681 bus_space_write_region_stream_4(regs->r_bt, regs->r_bh, 682 RTW_DK0, rk->rk_words, __arraycount(rk->rk_words)); 683 684 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 685 BUS_SPACE_BARRIER_SYNC); 686 687 RTW_WBW(regs, RTW_DK0, RTW_PSR); 688 RTW_WRITE8(regs, RTW_PSR, psr); 689 RTW_WBW(regs, RTW_PSR, RTW_SCR); 690 RTW_WRITE8(regs, RTW_SCR, scr); 691 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 692 rtw_set_access(regs, RTW_ACCESS_NONE); 693 sc->sc_flags |= RTW_F_DK_VALID; 694 } 695 696 static inline int 697 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 698 { 699 int i; 700 uint8_t ecr; 701 702 ecr = RTW_READ8(regs, RTW_9346CR); 703 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 704 RTW_WRITE8(regs, RTW_9346CR, ecr); 705 706 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 707 708 /* wait 25ms for completion */ 709 for (i = 0; i < 250; i++) { 710 ecr = RTW_READ8(regs, RTW_9346CR); 711 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 712 RTW_DPRINTF(RTW_DEBUG_RESET, 713 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 714 return 0; 715 } 716 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 717 DELAY(100); 718 } 719 printf("%s: recall EEPROM failed\n", dvname); 720 return ETIMEDOUT; 721 } 722 723 static inline int 724 rtw_reset(struct rtw_softc *sc) 725 { 726 int rc; 727 uint8_t config1; 728 729 sc->sc_flags &= ~RTW_F_DK_VALID; 730 731 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 732 return rc; 733 734 rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname); 735 736 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 737 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 738 /* TBD turn off maximum power saving? */ 739 740 return 0; 741 } 742 743 static inline int 744 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 745 u_int ndescs) 746 { 747 int i, rc = 0; 748 for (i = 0; i < ndescs; i++) { 749 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 750 0, 0, &descs[i].ts_dmamap); 751 if (rc != 0) 752 break; 753 } 754 return rc; 755 } 756 757 static inline int 758 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 759 u_int ndescs) 760 { 761 int i, rc = 0; 762 for (i = 0; i < ndescs; i++) { 763 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 764 &descs[i].rs_dmamap); 765 if (rc != 0) 766 break; 767 } 768 return rc; 769 } 770 771 static inline void 772 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 773 u_int ndescs) 774 { 775 int i; 776 for (i = 0; i < ndescs; i++) { 777 if (descs[i].rs_dmamap != NULL) 778 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 779 } 780 } 781 782 static inline void 783 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 784 u_int ndescs) 785 { 786 int i; 787 for (i = 0; i < ndescs; i++) { 788 if (descs[i].ts_dmamap != NULL) 789 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 790 } 791 } 792 793 static inline void 794 rtw_srom_free(struct rtw_srom *sr) 795 { 796 sr->sr_size = 0; 797 if (sr->sr_content == NULL) 798 return; 799 free(sr->sr_content, M_DEVBUF); 800 sr->sr_content = NULL; 801 } 802 803 static void 804 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, 805 uint8_t *cs_threshold, enum rtw_rfchipid *rfchipid, uint32_t *rcr) 806 { 807 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 808 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 809 *rcr |= RTW_RCR_ENCS1; 810 *rfchipid = RTW_RFCHIPID_PHILIPS; 811 } 812 813 static int 814 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 815 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 816 const char *dvname) 817 { 818 int i; 819 const char *rfname, *paname; 820 char scratch[sizeof("unknown 0xXX")]; 821 uint16_t srom_version; 822 uint8_t mac[IEEE80211_ADDR_LEN]; 823 824 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 825 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 826 827 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 828 printf("%s: SROM version %d.%d", dvname, 829 srom_version >> 8, srom_version & 0xff); 830 831 if (srom_version <= 0x0101) { 832 printf(" is not understood, limping along with defaults\n"); 833 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 834 return 0; 835 } 836 printf("\n"); 837 838 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 839 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 840 841 RTW_DPRINTF(RTW_DEBUG_ATTACH, 842 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 843 844 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 845 846 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 847 *flags |= RTW_F_ANTDIV; 848 849 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 850 * to be reversed. 851 */ 852 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 853 *flags |= RTW_F_DIGPHY; 854 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 855 *flags |= RTW_F_DFLANTB; 856 857 *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), 858 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 859 860 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0) 861 *flags |= RTW_C_RXWEP_104; 862 863 *flags |= RTW_C_RXWEP_40; /* XXX */ 864 865 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 866 switch (*rfchipid) { 867 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 868 rfname = "GCT GRF5101"; 869 paname = "Winspring WS9901"; 870 break; 871 case RTW_RFCHIPID_MAXIM: 872 rfname = "Maxim MAX2820"; /* guess */ 873 paname = "Maxim MAX2422"; /* guess */ 874 break; 875 case RTW_RFCHIPID_INTERSIL: 876 rfname = "Intersil HFA3873"; /* guess */ 877 paname = "Intersil <unknown>"; 878 break; 879 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 880 rfname = "Philips SA2400A"; 881 paname = "Philips SA2411"; 882 break; 883 case RTW_RFCHIPID_RFMD: 884 /* this is the same front-end as an atw(4)! */ 885 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 886 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 887 "SYN: Silicon Labs Si4126"; /* inferred from 888 * reference driver 889 */ 890 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 891 break; 892 case RTW_RFCHIPID_RESERVED: 893 rfname = paname = "reserved"; 894 break; 895 default: 896 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 897 rfname = paname = scratch; 898 } 899 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 900 901 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 902 case RTW_CONFIG0_GL_USA: 903 case _RTW_CONFIG0_GL_USA: 904 *locale = RTW_LOCALE_USA; 905 break; 906 case RTW_CONFIG0_GL_EUROPE: 907 *locale = RTW_LOCALE_EUROPE; 908 break; 909 case RTW_CONFIG0_GL_JAPAN: 910 *locale = RTW_LOCALE_JAPAN; 911 break; 912 default: 913 *locale = RTW_LOCALE_UNKNOWN; 914 break; 915 } 916 return 0; 917 } 918 919 /* Returns -1 on failure. */ 920 static int 921 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 922 const char *dvname) 923 { 924 int rc; 925 struct seeprom_descriptor sd; 926 uint8_t ecr; 927 928 (void)memset(&sd, 0, sizeof(sd)); 929 930 ecr = RTW_READ8(regs, RTW_9346CR); 931 932 if ((flags & RTW_F_9356SROM) != 0) { 933 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 934 sr->sr_size = 256; 935 sd.sd_chip = C56_66; 936 } else { 937 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 938 sr->sr_size = 128; 939 sd.sd_chip = C46; 940 } 941 942 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 943 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 944 ecr |= RTW_9346CR_EEM_PROGRAM; 945 946 RTW_WRITE8(regs, RTW_9346CR, ecr); 947 948 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 949 950 if (sr->sr_content == NULL) { 951 printf("%s: unable to allocate SROM buffer\n", dvname); 952 return ENOMEM; 953 } 954 955 (void)memset(sr->sr_content, 0, sr->sr_size); 956 957 /* RTL8180 has a single 8-bit register for controlling the 958 * 93cx6 SROM. There is no "ready" bit. The RTL8180 959 * input/output sense is the reverse of read_seeprom's. 960 */ 961 sd.sd_tag = regs->r_bt; 962 sd.sd_bsh = regs->r_bh; 963 sd.sd_regsize = 1; 964 sd.sd_control_offset = RTW_9346CR; 965 sd.sd_status_offset = RTW_9346CR; 966 sd.sd_dataout_offset = RTW_9346CR; 967 sd.sd_CK = RTW_9346CR_EESK; 968 sd.sd_CS = RTW_9346CR_EECS; 969 sd.sd_DI = RTW_9346CR_EEDO; 970 sd.sd_DO = RTW_9346CR_EEDI; 971 /* make read_seeprom enter EEPROM read/write mode */ 972 sd.sd_MS = ecr; 973 sd.sd_RDY = 0; 974 975 /* TBD bus barriers */ 976 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 977 printf("%s: could not read SROM\n", dvname); 978 free(sr->sr_content, M_DEVBUF); 979 sr->sr_content = NULL; 980 return -1; /* XXX */ 981 } 982 983 /* end EEPROM read/write mode */ 984 RTW_WRITE8(regs, RTW_9346CR, 985 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 986 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 987 988 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 989 return rc; 990 991 #ifdef RTW_DEBUG 992 { 993 int i; 994 RTW_DPRINTF(RTW_DEBUG_ATTACH, 995 ("\n%s: serial ROM:\n\t", dvname)); 996 for (i = 0; i < sr->sr_size/2; i++) { 997 if (((i % 8) == 0) && (i != 0)) 998 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 999 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1000 (" %04x", sr->sr_content[i])); 1001 } 1002 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 1003 } 1004 #endif /* RTW_DEBUG */ 1005 return 0; 1006 } 1007 1008 static void 1009 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 1010 const char *dvname) 1011 { 1012 uint8_t cfg4; 1013 const char *method; 1014 1015 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 1016 1017 switch (rfchipid) { 1018 default: 1019 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 1020 method = "fallback"; 1021 break; 1022 case RTW_RFCHIPID_INTERSIL: 1023 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1024 method = "Intersil"; 1025 break; 1026 case RTW_RFCHIPID_PHILIPS: 1027 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1028 method = "Philips"; 1029 break; 1030 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1031 case RTW_RFCHIPID_RFMD: 1032 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1033 method = "RFMD"; 1034 break; 1035 } 1036 1037 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1038 1039 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1040 1041 RTW_DPRINTF(RTW_DEBUG_INIT, 1042 ("%s: %s RF programming method, %#02x\n", dvname, method, 1043 RTW_READ8(regs, RTW_CONFIG4))); 1044 } 1045 1046 static inline void 1047 rtw_init_channels(enum rtw_locale locale, 1048 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 1049 const char *dvname) 1050 { 1051 int i; 1052 const char *name = NULL; 1053 #define ADD_CHANNEL(_chans, _chan) do { \ 1054 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1055 (*_chans)[_chan].ic_freq = \ 1056 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1057 } while (0) 1058 1059 switch (locale) { 1060 case RTW_LOCALE_USA: /* 1-11 */ 1061 name = "USA"; 1062 for (i = 1; i <= 11; i++) 1063 ADD_CHANNEL(chans, i); 1064 break; 1065 case RTW_LOCALE_JAPAN: /* 1-14 */ 1066 name = "Japan"; 1067 ADD_CHANNEL(chans, 14); 1068 for (i = 1; i <= 14; i++) 1069 ADD_CHANNEL(chans, i); 1070 break; 1071 case RTW_LOCALE_EUROPE: /* 1-13 */ 1072 name = "Europe"; 1073 for (i = 1; i <= 13; i++) 1074 ADD_CHANNEL(chans, i); 1075 break; 1076 default: /* 10-11 allowed by most countries */ 1077 name = "<unknown>"; 1078 for (i = 10; i <= 11; i++) 1079 ADD_CHANNEL(chans, i); 1080 break; 1081 } 1082 printf("%s: Geographic Location %s\n", dvname, name); 1083 #undef ADD_CHANNEL 1084 } 1085 1086 1087 static inline void 1088 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale) 1089 { 1090 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1091 1092 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1093 case RTW_CONFIG0_GL_USA: 1094 case _RTW_CONFIG0_GL_USA: 1095 *locale = RTW_LOCALE_USA; 1096 break; 1097 case RTW_CONFIG0_GL_JAPAN: 1098 *locale = RTW_LOCALE_JAPAN; 1099 break; 1100 case RTW_CONFIG0_GL_EUROPE: 1101 *locale = RTW_LOCALE_EUROPE; 1102 break; 1103 default: 1104 *locale = RTW_LOCALE_UNKNOWN; 1105 break; 1106 } 1107 } 1108 1109 static inline int 1110 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1111 const char *dvname) 1112 { 1113 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1114 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1115 }; 1116 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1117 idr1 = RTW_READ(regs, RTW_IDR1); 1118 1119 (*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7)); 1120 (*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15)); 1121 (*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23)); 1122 (*addr)[3] = __SHIFTOUT(idr0, __BITS(24 ,31)); 1123 1124 (*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7)); 1125 (*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15)); 1126 1127 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1128 printf("%s: could not get mac address, attach failed\n", 1129 dvname); 1130 return ENXIO; 1131 } 1132 1133 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 1134 1135 return 0; 1136 } 1137 1138 static uint8_t 1139 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1140 struct ieee80211_channel *chan) 1141 { 1142 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1143 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 1144 ("%s: channel %d out of range", __func__, 1145 idx - RTW_SR_TXPOWER1 + 1)); 1146 return RTW_SR_GET(sr, idx); 1147 } 1148 1149 static void 1150 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1151 { 1152 int pri; 1153 /* nfree: the number of free descriptors in each ring. 1154 * The beacon ring is a special case: I do not let the 1155 * driver use all of the descriptors on the beacon ring. 1156 * The reasons are two-fold: 1157 * 1158 * (1) A BEACON descriptor's OWN bit is (apparently) not 1159 * updated, so the driver cannot easily know if the descriptor 1160 * belongs to it, or if it is racing the NIC. If the NIC 1161 * does not OWN every descriptor, then the driver can safely 1162 * update the descriptors when RTW_TBDA points at tdb_next. 1163 * 1164 * (2) I hope that the NIC will process more than one BEACON 1165 * descriptor in a single beacon interval, since that will 1166 * enable multiple-BSS support. Since the NIC does not 1167 * clear the OWN bit, there is no natural place for it to 1168 * stop processing BEACON desciptors. Maybe it will *not* 1169 * stop processing them! I do not want to chance the NIC 1170 * looping around and around a saturated beacon ring, so 1171 * I will leave one descriptor unOWNed at all times. 1172 */ 1173 u_int nfree[RTW_NTXPRI] = 1174 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, 1175 RTW_NTXDESCBCN - 1}; 1176 1177 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1178 tdb[pri].tdb_nfree = nfree[pri]; 1179 tdb[pri].tdb_next = 0; 1180 } 1181 } 1182 1183 static int 1184 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1185 { 1186 int i; 1187 struct rtw_txsoft *ts; 1188 1189 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1190 SIMPLEQ_INIT(&tsb->tsb_freeq); 1191 for (i = 0; i < tsb->tsb_ndesc; i++) { 1192 ts = &tsb->tsb_desc[i]; 1193 ts->ts_mbuf = NULL; 1194 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1195 } 1196 tsb->tsb_tx_timer = 0; 1197 return 0; 1198 } 1199 1200 static void 1201 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1202 { 1203 int pri; 1204 for (pri = 0; pri < RTW_NTXPRI; pri++) 1205 rtw_txsoft_blk_init(&tsb[pri]); 1206 } 1207 1208 static inline void 1209 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1210 { 1211 KASSERT(nsync <= rdb->rdb_ndesc); 1212 /* sync to end of ring */ 1213 if (desc0 + nsync > rdb->rdb_ndesc) { 1214 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1215 offsetof(struct rtw_descs, hd_rx[desc0]), 1216 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1217 nsync -= (rdb->rdb_ndesc - desc0); 1218 desc0 = 0; 1219 } 1220 1221 KASSERT(desc0 < rdb->rdb_ndesc); 1222 KASSERT(nsync <= rdb->rdb_ndesc); 1223 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1224 1225 /* sync what remains */ 1226 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1227 offsetof(struct rtw_descs, hd_rx[desc0]), 1228 sizeof(struct rtw_rxdesc) * nsync, ops); 1229 } 1230 1231 static void 1232 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1233 { 1234 /* sync to end of ring */ 1235 if (desc0 + nsync > tdb->tdb_ndesc) { 1236 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1237 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1238 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1239 ops); 1240 nsync -= (tdb->tdb_ndesc - desc0); 1241 desc0 = 0; 1242 } 1243 1244 /* sync what remains */ 1245 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1246 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1247 sizeof(struct rtw_txdesc) * nsync, ops); 1248 } 1249 1250 static void 1251 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1252 { 1253 int pri; 1254 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1255 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1256 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1257 } 1258 } 1259 1260 static void 1261 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1262 { 1263 int i; 1264 struct rtw_rxsoft *rs; 1265 1266 for (i = 0; i < RTW_RXQLEN; i++) { 1267 rs = &desc[i]; 1268 if (rs->rs_mbuf == NULL) 1269 continue; 1270 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1271 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1272 bus_dmamap_unload(dmat, rs->rs_dmamap); 1273 m_freem(rs->rs_mbuf); 1274 rs->rs_mbuf = NULL; 1275 } 1276 } 1277 1278 static inline int 1279 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1280 { 1281 int rc; 1282 struct mbuf *m; 1283 1284 MGETHDR(m, M_DONTWAIT, MT_DATA); 1285 if (m == NULL) 1286 return ENOBUFS; 1287 1288 MCLGET(m, M_DONTWAIT); 1289 if ((m->m_flags & M_EXT) == 0) { 1290 m_freem(m); 1291 return ENOBUFS; 1292 } 1293 1294 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1295 1296 if (rs->rs_mbuf != NULL) 1297 bus_dmamap_unload(dmat, rs->rs_dmamap); 1298 1299 rs->rs_mbuf = NULL; 1300 1301 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1302 if (rc != 0) { 1303 m_freem(m); 1304 return -1; 1305 } 1306 1307 rs->rs_mbuf = m; 1308 1309 return 0; 1310 } 1311 1312 static int 1313 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1314 int *ndesc, const char *dvname) 1315 { 1316 int i, rc = 0; 1317 struct rtw_rxsoft *rs; 1318 1319 for (i = 0; i < RTW_RXQLEN; i++) { 1320 rs = &desc[i]; 1321 /* we're in rtw_init, so there should be no mbufs allocated */ 1322 KASSERT(rs->rs_mbuf == NULL); 1323 #ifdef RTW_DEBUG 1324 if (i == rtw_rxbufs_limit) { 1325 printf("%s: TEST hit %d-buffer limit\n", dvname, i); 1326 rc = ENOBUFS; 1327 break; 1328 } 1329 #endif /* RTW_DEBUG */ 1330 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1331 printf("%s: rtw_rxsoft_alloc failed, %d buffers, " 1332 "rc %d\n", dvname, i, rc); 1333 break; 1334 } 1335 } 1336 *ndesc = i; 1337 return rc; 1338 } 1339 1340 static inline void 1341 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1342 int idx, int kick) 1343 { 1344 int is_last = (idx == rdb->rdb_ndesc - 1); 1345 uint32_t ctl, octl, obuf; 1346 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1347 1348 obuf = rd->rd_buf; 1349 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1350 1351 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1352 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1353 1354 if (is_last) 1355 ctl |= RTW_RXCTL_EOR; 1356 1357 octl = rd->rd_ctl; 1358 rd->rd_ctl = htole32(ctl); 1359 1360 RTW_DPRINTF( 1361 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1362 : RTW_DEBUG_RECV_DESC, 1363 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1364 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1365 le32toh(rd->rd_ctl))); 1366 1367 /* sync the mbuf */ 1368 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1369 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1370 1371 /* sync the descriptor */ 1372 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1373 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1374 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1375 } 1376 1377 static void 1378 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1379 { 1380 int i; 1381 struct rtw_rxdesc *rd; 1382 struct rtw_rxsoft *rs; 1383 1384 for (i = 0; i < rdb->rdb_ndesc; i++) { 1385 rd = &rdb->rdb_desc[i]; 1386 rs = &ctl[i]; 1387 rtw_rxdesc_init(rdb, rs, i, kick); 1388 } 1389 } 1390 1391 static void 1392 rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable) 1393 { 1394 struct rtw_regs *regs = &sc->sc_regs; 1395 uint8_t cr; 1396 1397 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1398 enable ? "enable" : "disable", flags)); 1399 1400 cr = RTW_READ8(regs, RTW_CR); 1401 1402 /* XXX reference source does not enable MULRW */ 1403 /* enable PCI Read/Write Multiple */ 1404 cr |= RTW_CR_MULRW; 1405 1406 /* The receive engine will always start at RDSAR. */ 1407 if (enable && (flags & ~cr & RTW_CR_RE)) { 1408 struct rtw_rxdesc_blk *rdb; 1409 rdb = &sc->sc_rxdesc_blk; 1410 rdb->rdb_next = 0; 1411 } 1412 1413 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1414 if (enable) 1415 cr |= flags; 1416 else 1417 cr &= ~flags; 1418 RTW_WRITE8(regs, RTW_CR, cr); 1419 RTW_SYNC(regs, RTW_CR, RTW_CR); 1420 1421 #ifdef RTW_DIAG 1422 if (cr & RTW_CR_TE) 1423 rtw_txring_fixup(sc, __func__, __LINE__); 1424 #endif 1425 } 1426 1427 static void 1428 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1429 { 1430 #define IS_BEACON(__fc0) \ 1431 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1432 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1433 1434 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1435 * hardware -> net80211 1436 */ 1437 u_int next, nproc = 0; 1438 int hwrate, len, rate, rssi, sq; 1439 uint32_t hrssi, hstat, htsfth, htsftl; 1440 struct rtw_rxdesc *rd; 1441 struct rtw_rxsoft *rs; 1442 struct rtw_rxdesc_blk *rdb; 1443 struct mbuf *m; 1444 struct ifnet *ifp = &sc->sc_if; 1445 1446 struct ieee80211_node *ni; 1447 struct ieee80211_frame_min *wh; 1448 1449 rdb = &sc->sc_rxdesc_blk; 1450 1451 for (next = rdb->rdb_next; ; next = rdb->rdb_next) { 1452 KASSERT(next < rdb->rdb_ndesc); 1453 1454 rtw_rxdescs_sync(rdb, next, 1, 1455 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1456 rd = &rdb->rdb_desc[next]; 1457 rs = &sc->sc_rxsoft[next]; 1458 1459 hstat = le32toh(rd->rd_stat); 1460 hrssi = le32toh(rd->rd_rssi); 1461 htsfth = le32toh(rd->rd_tsfth); 1462 htsftl = le32toh(rd->rd_tsftl); 1463 1464 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1465 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1466 __func__, next, hstat, hrssi, htsfth, htsftl)); 1467 1468 ++nproc; 1469 1470 /* still belongs to NIC */ 1471 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1472 rtw_rxdescs_sync(rdb, next, 1, BUS_DMASYNC_PREREAD); 1473 break; 1474 } 1475 1476 /* ieee80211_input() might reset the receive engine 1477 * (e.g. by indirectly calling rtw_tune()), so save 1478 * the next pointer here and retrieve it again on 1479 * the next round. 1480 */ 1481 rdb->rdb_next = (next + 1) % rdb->rdb_ndesc; 1482 1483 #ifdef RTW_DEBUG 1484 #define PRINTSTAT(flag) do { \ 1485 if ((hstat & flag) != 0) { \ 1486 printf("%s" #flag, delim); \ 1487 delim = ","; \ 1488 } \ 1489 } while (0) 1490 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1491 const char *delim = "<"; 1492 printf("%s: ", sc->sc_dev.dv_xname); 1493 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1494 printf("status %08x", hstat); 1495 PRINTSTAT(RTW_RXSTAT_SPLCP); 1496 PRINTSTAT(RTW_RXSTAT_MAR); 1497 PRINTSTAT(RTW_RXSTAT_PAR); 1498 PRINTSTAT(RTW_RXSTAT_BAR); 1499 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1500 PRINTSTAT(RTW_RXSTAT_CRC32); 1501 PRINTSTAT(RTW_RXSTAT_ICV); 1502 printf(">, "); 1503 } 1504 } 1505 #endif /* RTW_DEBUG */ 1506 1507 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1508 printf("%s: DMA error/FIFO overflow %08" PRIx32 ", " 1509 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1510 hstat, next); 1511 ifp->if_ierrors++; 1512 goto next; 1513 } 1514 1515 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); 1516 if (len < IEEE80211_MIN_LEN) { 1517 sc->sc_ic.ic_stats.is_rx_tooshort++; 1518 goto next; 1519 } 1520 1521 /* CRC is included with the packet; trim it off. */ 1522 len -= IEEE80211_CRC_LEN; 1523 1524 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); 1525 if (hwrate >= __arraycount(ratetbl)) { 1526 printf("%s: unknown rate #%" __PRIuBITS "\n", 1527 sc->sc_dev.dv_xname, 1528 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); 1529 ifp->if_ierrors++; 1530 goto next; 1531 } 1532 rate = ratetbl[hwrate]; 1533 1534 #ifdef RTW_DEBUG 1535 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1536 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1537 (rate * 5) % 10, htsfth, htsftl)); 1538 #endif /* RTW_DEBUG */ 1539 1540 if ((hstat & RTW_RXSTAT_RES) != 0 && 1541 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1542 goto next; 1543 1544 /* if bad flags, skip descriptor */ 1545 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1546 printf("%s: too many rx segments, " 1547 "next=%d, %08" PRIx32 "\n", 1548 sc->sc_dev.dv_xname, next, hstat); 1549 goto next; 1550 } 1551 1552 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1553 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1554 1555 m = rs->rs_mbuf; 1556 1557 /* if temporarily out of memory, re-use mbuf */ 1558 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1559 case 0: 1560 break; 1561 case ENOBUFS: 1562 printf("%s: rtw_rxsoft_alloc(, %d) failed, " 1563 "dropping packet\n", sc->sc_dev.dv_xname, next); 1564 goto next; 1565 default: 1566 /* XXX shorten rx ring, instead? */ 1567 panic("%s: could not load DMA map\n", 1568 sc->sc_dev.dv_xname); 1569 } 1570 1571 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1572 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_RSSI); 1573 else { 1574 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); 1575 /* TBD find out each front-end's LNA gain in the 1576 * front-end's units 1577 */ 1578 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1579 rssi |= 0x80; 1580 } 1581 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ); 1582 1583 /* Note well: now we cannot recycle the rs_mbuf unless 1584 * we restore its original length. 1585 */ 1586 m->m_pkthdr.rcvif = ifp; 1587 m->m_pkthdr.len = m->m_len = len; 1588 1589 wh = mtod(m, struct ieee80211_frame_min *); 1590 1591 if (!IS_BEACON(wh->i_fc[0])) 1592 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1593 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1594 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1595 1596 sc->sc_tsfth = htsfth; 1597 1598 #ifdef RTW_DEBUG 1599 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 1600 (IFF_DEBUG|IFF_LINK2)) { 1601 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1602 rate, rssi); 1603 } 1604 #endif /* RTW_DEBUG */ 1605 1606 #if NBPFILTER > 0 1607 if (sc->sc_radiobpf != NULL) { 1608 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1609 1610 rr->rr_tsft = 1611 htole64(((uint64_t)htsfth << 32) | htsftl); 1612 1613 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1614 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE; 1615 1616 rr->rr_flags = 0; 1617 rr->rr_rate = rate; 1618 rr->rr_antsignal = rssi; 1619 rr->rr_barker_lock = htole16(sq); 1620 1621 bpf_mtap2(sc->sc_radiobpf, (void *)rr, 1622 sizeof(sc->sc_rxtapu), m); 1623 } 1624 #endif /* NPBFILTER > 0 */ 1625 1626 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1627 ieee80211_free_node(ni); 1628 next: 1629 rtw_rxdesc_init(rdb, rs, next, 0); 1630 } 1631 #undef IS_BEACON 1632 } 1633 1634 static void 1635 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1636 struct rtw_txsoft *ts) 1637 { 1638 struct mbuf *m; 1639 struct ieee80211_node *ni; 1640 1641 m = ts->ts_mbuf; 1642 ni = ts->ts_ni; 1643 KASSERT(m != NULL); 1644 KASSERT(ni != NULL); 1645 ts->ts_mbuf = NULL; 1646 ts->ts_ni = NULL; 1647 1648 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1649 BUS_DMASYNC_POSTWRITE); 1650 bus_dmamap_unload(dmat, ts->ts_dmamap); 1651 m_freem(m); 1652 ieee80211_free_node(ni); 1653 } 1654 1655 static void 1656 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1657 struct rtw_txsoft_blk *tsb) 1658 { 1659 struct rtw_txsoft *ts; 1660 1661 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1662 rtw_txsoft_release(dmat, ic, ts); 1663 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1664 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1665 } 1666 tsb->tsb_tx_timer = 0; 1667 } 1668 1669 static inline void 1670 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1671 struct rtw_txsoft *ts, int ndesc) 1672 { 1673 uint32_t hstat; 1674 int data_retry, rts_retry; 1675 struct rtw_txdesc *tdn; 1676 const char *condstring; 1677 struct ifnet *ifp = &sc->sc_if; 1678 1679 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1680 1681 tdb->tdb_nfree += ndesc; 1682 1683 tdn = &tdb->tdb_desc[ts->ts_last]; 1684 1685 hstat = le32toh(tdn->td_stat); 1686 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1687 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); 1688 1689 ifp->if_collisions += rts_retry + data_retry; 1690 1691 if ((hstat & RTW_TXSTAT_TOK) != 0) 1692 condstring = "ok"; 1693 else { 1694 ifp->if_oerrors++; 1695 condstring = "error"; 1696 } 1697 1698 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1699 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1700 sc->sc_dev.dv_xname, ts, ts->ts_first, ts->ts_last, 1701 condstring, rts_retry, data_retry)); 1702 } 1703 1704 static void 1705 rtw_reset_oactive(struct rtw_softc *sc) 1706 { 1707 short oflags; 1708 int pri; 1709 struct rtw_txsoft_blk *tsb; 1710 struct rtw_txdesc_blk *tdb; 1711 oflags = sc->sc_if.if_flags; 1712 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1713 tsb = &sc->sc_txsoft_blk[pri]; 1714 tdb = &sc->sc_txdesc_blk[pri]; 1715 if (!SIMPLEQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0) 1716 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1717 } 1718 if (oflags != sc->sc_if.if_flags) { 1719 DPRINTF(sc, RTW_DEBUG_OACTIVE, 1720 ("%s: reset OACTIVE\n", __func__)); 1721 } 1722 } 1723 1724 /* Collect transmitted packets. */ 1725 static inline void 1726 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1727 struct rtw_txdesc_blk *tdb, int force) 1728 { 1729 int ndesc; 1730 struct rtw_txsoft *ts; 1731 1732 #ifdef RTW_DEBUG 1733 rtw_dump_rings(sc); 1734 #endif 1735 1736 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1737 /* If we're clearing a failed transmission, only clear 1738 up to the last packet the hardware has processed. */ 1739 if (ts->ts_first == rtw_txring_next(&sc->sc_regs, tdb)) 1740 break; 1741 1742 ndesc = 1 + ts->ts_last - ts->ts_first; 1743 if (ts->ts_last < ts->ts_first) 1744 ndesc += tdb->tdb_ndesc; 1745 1746 KASSERT(ndesc > 0); 1747 1748 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1749 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1750 1751 if (force) { 1752 int next; 1753 #ifdef RTW_DIAG 1754 printf("%s: clearing packet, stats", __func__); 1755 #endif 1756 for (next = ts->ts_first; ; 1757 next = RTW_NEXT_IDX(tdb, next)) { 1758 #ifdef RTW_DIAG 1759 printf(" %" PRIx32 "/%" PRIx32 "/%" PRIx32 "/%" PRIu32 "/%" PRIx32, le32toh(tdb->tdb_desc[next].td_stat), le32toh(tdb->tdb_desc[next].td_ctl1), le32toh(tdb->tdb_desc[next].td_buf), le32toh(tdb->tdb_desc[next].td_len), le32toh(tdb->tdb_desc[next].td_next)); 1760 #endif 1761 tdb->tdb_desc[next].td_stat &= 1762 ~htole32(RTW_TXSTAT_OWN); 1763 if (next == ts->ts_last) 1764 break; 1765 } 1766 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1767 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1768 #ifdef RTW_DIAG 1769 next = RTW_NEXT_IDX(tdb, next); 1770 printf(" -> end %u stat %" PRIx32 ", was %u\n", next, 1771 le32toh(tdb->tdb_desc[next].td_stat), 1772 rtw_txring_next(&sc->sc_regs, tdb)); 1773 #endif 1774 } else if ((tdb->tdb_desc[ts->ts_last].td_stat & 1775 htole32(RTW_TXSTAT_OWN)) != 0) { 1776 rtw_txdescs_sync(tdb, ts->ts_last, 1, 1777 BUS_DMASYNC_PREREAD); 1778 break; 1779 } 1780 1781 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1782 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1783 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1784 } 1785 1786 /* no more pending transmissions, cancel watchdog */ 1787 if (ts == NULL) 1788 tsb->tsb_tx_timer = 0; 1789 rtw_reset_oactive(sc); 1790 } 1791 1792 static void 1793 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1794 { 1795 int pri; 1796 struct rtw_txsoft_blk *tsb; 1797 struct rtw_txdesc_blk *tdb; 1798 struct ifnet *ifp = &sc->sc_if; 1799 1800 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1801 tsb = &sc->sc_txsoft_blk[pri]; 1802 tdb = &sc->sc_txdesc_blk[pri]; 1803 rtw_collect_txring(sc, tsb, tdb, 0); 1804 } 1805 1806 if ((isr & RTW_INTR_TX) != 0) 1807 rtw_start(ifp); 1808 1809 return; 1810 } 1811 1812 static void 1813 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1814 { 1815 u_int next; 1816 uint32_t tsfth, tsftl; 1817 struct ieee80211com *ic; 1818 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN]; 1819 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN]; 1820 struct mbuf *m; 1821 1822 tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH); 1823 tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1824 1825 if ((isr & (RTW_INTR_TBDOK|RTW_INTR_TBDER)) != 0) { 1826 next = rtw_txring_next(&sc->sc_regs, tdb); 1827 RTW_DPRINTF(RTW_DEBUG_BEACON, 1828 ("%s: beacon ring %sprocessed, isr = %#04" PRIx16 1829 ", next %u expected %u, %" PRIu64 "\n", __func__, 1830 (next == tdb->tdb_next) ? "" : "un", isr, next, 1831 tdb->tdb_next, (uint64_t)tsfth << 32 | tsftl)); 1832 if ((RTW_READ8(&sc->sc_regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0) 1833 rtw_collect_txring(sc, tsb, tdb, 1); 1834 } 1835 /* Start beacon transmission. */ 1836 1837 if ((isr & RTW_INTR_BCNINT) != 0 && 1838 sc->sc_ic.ic_state == IEEE80211_S_RUN && 1839 SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) { 1840 RTW_DPRINTF(RTW_DEBUG_BEACON, 1841 ("%s: beacon prep. time, isr = %#04" PRIx16 1842 ", %16" PRIu64 "\n", __func__, isr, 1843 (uint64_t)tsfth << 32 | tsftl)); 1844 ic = &sc->sc_ic; 1845 m = rtw_beacon_alloc(sc, ic->ic_bss); 1846 1847 if (m == NULL) { 1848 printf("%s: could not allocate beacon\n", 1849 sc->sc_dev.dv_xname); 1850 return; 1851 } 1852 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss); 1853 IF_ENQUEUE(&sc->sc_beaconq, m); 1854 rtw_start(&sc->sc_if); 1855 } 1856 } 1857 1858 static void 1859 rtw_intr_atim(struct rtw_softc *sc) 1860 { 1861 /* TBD */ 1862 return; 1863 } 1864 1865 #ifdef RTW_DEBUG 1866 static void 1867 rtw_dump_rings(struct rtw_softc *sc) 1868 { 1869 struct rtw_txdesc_blk *tdb; 1870 struct rtw_rxdesc *rd; 1871 struct rtw_rxdesc_blk *rdb; 1872 int desc, pri; 1873 1874 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1875 return; 1876 1877 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1878 tdb = &sc->sc_txdesc_blk[pri]; 1879 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1880 tdb->tdb_ndesc, tdb->tdb_nfree); 1881 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1882 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1883 } 1884 1885 rdb = &sc->sc_rxdesc_blk; 1886 1887 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1888 rd = &rdb->rdb_desc[desc]; 1889 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1890 "rsvd1/tsfth %08x\n", __func__, 1891 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1892 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1893 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1894 } 1895 } 1896 #endif /* RTW_DEBUG */ 1897 1898 static void 1899 rtw_hwring_setup(struct rtw_softc *sc) 1900 { 1901 int pri; 1902 struct rtw_regs *regs = &sc->sc_regs; 1903 struct rtw_txdesc_blk *tdb; 1904 1905 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_basereg = RTW_TLPDA; 1906 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_base = RTW_RING_BASE(sc, hd_txlo); 1907 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_basereg = RTW_TNPDA; 1908 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_base = RTW_RING_BASE(sc, hd_txmd); 1909 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_basereg = RTW_THPDA; 1910 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_base = RTW_RING_BASE(sc, hd_txhi); 1911 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_basereg = RTW_TBDA; 1912 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_base = RTW_RING_BASE(sc, hd_bcn); 1913 1914 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1915 tdb = &sc->sc_txdesc_blk[pri]; 1916 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base); 1917 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1918 ("%s: reg[tdb->tdb_basereg] <- %" PRIxPTR "\n", __func__, 1919 (uintptr_t)tdb->tdb_base)); 1920 } 1921 1922 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1923 1924 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1925 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1926 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1927 1928 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1929 1930 } 1931 1932 static int 1933 rtw_swring_setup(struct rtw_softc *sc) 1934 { 1935 int rc; 1936 struct rtw_rxdesc_blk *rdb; 1937 1938 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1939 1940 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1941 1942 rdb = &sc->sc_rxdesc_blk; 1943 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1944 sc->sc_dev.dv_xname)) != 0 && rdb->rdb_ndesc == 0) { 1945 printf("%s: could not allocate rx buffers\n", 1946 sc->sc_dev.dv_xname); 1947 return rc; 1948 } 1949 1950 rdb = &sc->sc_rxdesc_blk; 1951 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1952 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1953 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1954 rdb->rdb_next = 0; 1955 1956 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1957 return 0; 1958 } 1959 1960 static void 1961 rtw_txdesc_blk_init(struct rtw_txdesc_blk *tdb) 1962 { 1963 int i; 1964 1965 (void)memset(tdb->tdb_desc, 0, 1966 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 1967 for (i = 0; i < tdb->tdb_ndesc; i++) 1968 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 1969 } 1970 1971 static u_int 1972 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb) 1973 { 1974 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) / 1975 sizeof(struct rtw_txdesc); 1976 } 1977 1978 #ifdef RTW_DIAG 1979 static void 1980 rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln) 1981 { 1982 int pri; 1983 u_int next; 1984 struct rtw_txdesc_blk *tdb; 1985 struct rtw_regs *regs = &sc->sc_regs; 1986 1987 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1988 int i; 1989 tdb = &sc->sc_txdesc_blk[pri]; 1990 next = rtw_txring_next(regs, tdb); 1991 if (tdb->tdb_next == next) 1992 continue; 1993 for (i = 0; next != tdb->tdb_next; 1994 next = RTW_NEXT_IDX(tdb, next), i++) { 1995 if ((tdb->tdb_desc[next].td_stat & htole32(RTW_TXSTAT_OWN)) == 0) 1996 break; 1997 } 1998 printf("%s:%d: tx-ring %d expected next %u, read %u+%d -> %s\n", fn, 1999 ln, pri, tdb->tdb_next, next, i, tdb->tdb_next == next ? "okay" : "BAD"); 2000 if (tdb->tdb_next == next) 2001 continue; 2002 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1); 2003 } 2004 } 2005 #endif 2006 2007 static void 2008 rtw_txdescs_reset(struct rtw_softc *sc) 2009 { 2010 int pri; 2011 struct rtw_txsoft_blk *tsb; 2012 struct rtw_txdesc_blk *tdb; 2013 2014 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2015 tsb = &sc->sc_txsoft_blk[pri]; 2016 tdb = &sc->sc_txdesc_blk[pri]; 2017 rtw_collect_txring(sc, tsb, tdb, 1); 2018 #ifdef RTW_DIAG 2019 if (!SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 2020 printf("%s: packets left in ring %d\n", __func__, pri); 2021 #endif 2022 } 2023 } 2024 2025 static void 2026 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 2027 { 2028 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 2029 2030 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: cleaning up xmit, isr %" PRIx16 2031 "\n", sc->sc_dev.dv_xname, isr)); 2032 2033 #ifdef RTW_DEBUG 2034 rtw_dump_rings(sc); 2035 #endif /* RTW_DEBUG */ 2036 2037 /* Collect tx'd packets. XXX let's hope this stops the transmit 2038 * timeouts. 2039 */ 2040 rtw_txdescs_reset(sc); 2041 2042 #ifdef RTW_DEBUG 2043 rtw_dump_rings(sc); 2044 #endif /* RTW_DEBUG */ 2045 } 2046 2047 static inline void 2048 rtw_suspend_ticks(struct rtw_softc *sc) 2049 { 2050 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2051 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 2052 sc->sc_do_tick = 0; 2053 } 2054 2055 static inline void 2056 rtw_resume_ticks(struct rtw_softc *sc) 2057 { 2058 uint32_t tsftrl0, tsftrl1, next_tick; 2059 2060 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2061 2062 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2063 next_tick = tsftrl1 + 1000000; 2064 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 2065 2066 sc->sc_do_tick = 1; 2067 2068 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2069 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 2070 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 2071 } 2072 2073 static void 2074 rtw_intr_timeout(struct rtw_softc *sc) 2075 { 2076 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 2077 if (sc->sc_do_tick) 2078 rtw_resume_ticks(sc); 2079 return; 2080 } 2081 2082 int 2083 rtw_intr(void *arg) 2084 { 2085 int i; 2086 struct rtw_softc *sc = arg; 2087 struct rtw_regs *regs = &sc->sc_regs; 2088 uint16_t isr; 2089 struct ifnet *ifp = &sc->sc_if; 2090 2091 /* 2092 * If the interface isn't running, the interrupt couldn't 2093 * possibly have come from us. 2094 */ 2095 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 2096 (ifp->if_flags & IFF_RUNNING) == 0 || 2097 !device_is_active(&sc->sc_dev)) { 2098 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 2099 return (0); 2100 } 2101 2102 for (i = 0; i < 10; i++) { 2103 isr = RTW_READ16(regs, RTW_ISR); 2104 2105 RTW_WRITE16(regs, RTW_ISR, isr); 2106 RTW_WBR(regs, RTW_ISR, RTW_ISR); 2107 2108 if (sc->sc_intr_ack != NULL) 2109 (*sc->sc_intr_ack)(regs); 2110 2111 if (isr == 0) 2112 break; 2113 2114 #ifdef RTW_DEBUG 2115 #define PRINTINTR(flag) do { \ 2116 if ((isr & flag) != 0) { \ 2117 printf("%s" #flag, delim); \ 2118 delim = ","; \ 2119 } \ 2120 } while (0) 2121 2122 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 2123 const char *delim = "<"; 2124 2125 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 2126 2127 PRINTINTR(RTW_INTR_TXFOVW); 2128 PRINTINTR(RTW_INTR_TIMEOUT); 2129 PRINTINTR(RTW_INTR_BCNINT); 2130 PRINTINTR(RTW_INTR_ATIMINT); 2131 PRINTINTR(RTW_INTR_TBDER); 2132 PRINTINTR(RTW_INTR_TBDOK); 2133 PRINTINTR(RTW_INTR_THPDER); 2134 PRINTINTR(RTW_INTR_THPDOK); 2135 PRINTINTR(RTW_INTR_TNPDER); 2136 PRINTINTR(RTW_INTR_TNPDOK); 2137 PRINTINTR(RTW_INTR_RXFOVW); 2138 PRINTINTR(RTW_INTR_RDU); 2139 PRINTINTR(RTW_INTR_TLPDER); 2140 PRINTINTR(RTW_INTR_TLPDOK); 2141 PRINTINTR(RTW_INTR_RER); 2142 PRINTINTR(RTW_INTR_ROK); 2143 2144 printf(">\n"); 2145 } 2146 #undef PRINTINTR 2147 #endif /* RTW_DEBUG */ 2148 2149 if ((isr & RTW_INTR_RX) != 0) 2150 rtw_intr_rx(sc, isr); 2151 if ((isr & RTW_INTR_TX) != 0) 2152 rtw_intr_tx(sc, isr); 2153 if ((isr & RTW_INTR_BEACON) != 0) 2154 rtw_intr_beacon(sc, isr); 2155 if ((isr & RTW_INTR_ATIMINT) != 0) 2156 rtw_intr_atim(sc); 2157 if ((isr & RTW_INTR_IOERROR) != 0) 2158 rtw_intr_ioerror(sc, isr); 2159 if ((isr & RTW_INTR_TIMEOUT) != 0) 2160 rtw_intr_timeout(sc); 2161 } 2162 2163 return 1; 2164 } 2165 2166 /* Must be called at splnet. */ 2167 static void 2168 rtw_stop(struct ifnet *ifp, int disable) 2169 { 2170 int pri; 2171 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2172 struct ieee80211com *ic = &sc->sc_ic; 2173 struct rtw_regs *regs = &sc->sc_regs; 2174 2175 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2176 return; 2177 2178 rtw_suspend_ticks(sc); 2179 2180 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2181 2182 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 2183 /* Disable interrupts. */ 2184 RTW_WRITE16(regs, RTW_IMR, 0); 2185 2186 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2187 2188 /* Stop the transmit and receive processes. First stop DMA, 2189 * then disable receiver and transmitter. 2190 */ 2191 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2192 2193 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2194 2195 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2196 } 2197 2198 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2199 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2200 &sc->sc_txsoft_blk[pri]); 2201 } 2202 2203 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2204 2205 if (disable) 2206 rtw_disable(sc); 2207 2208 /* Mark the interface as not running. Cancel the watchdog timer. */ 2209 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2210 ifp->if_timer = 0; 2211 2212 return; 2213 } 2214 2215 const char * 2216 rtw_pwrstate_string(enum rtw_pwrstate power) 2217 { 2218 switch (power) { 2219 case RTW_ON: 2220 return "on"; 2221 case RTW_SLEEP: 2222 return "sleep"; 2223 case RTW_OFF: 2224 return "off"; 2225 default: 2226 return "unknown"; 2227 } 2228 } 2229 2230 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2231 * reference driver, plus a magic Maxim "ON" value that comes from 2232 * the Realtek document "Windows PG for Rtl8180." 2233 */ 2234 static void 2235 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2236 int before_rf, int digphy) 2237 { 2238 uint32_t anaparm; 2239 2240 anaparm = RTW_READ(regs, RTW_ANAPARM); 2241 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2242 2243 switch (power) { 2244 case RTW_OFF: 2245 if (before_rf) 2246 return; 2247 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2248 anaparm |= RTW_ANAPARM_TXDACOFF; 2249 break; 2250 case RTW_SLEEP: 2251 if (!before_rf) 2252 return; 2253 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2254 anaparm |= RTW_ANAPARM_TXDACOFF; 2255 break; 2256 case RTW_ON: 2257 if (!before_rf) 2258 return; 2259 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2260 break; 2261 } 2262 RTW_DPRINTF(RTW_DEBUG_PWR, 2263 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2264 __func__, rtw_pwrstate_string(power), 2265 (before_rf) ? "before" : "after", anaparm)); 2266 2267 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2268 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2269 } 2270 2271 /* XXX I am using the RFMD settings gleaned from the reference 2272 * driver. They agree 2273 */ 2274 static void 2275 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2276 int before_rf, int digphy) 2277 { 2278 uint32_t anaparm; 2279 2280 anaparm = RTW_READ(regs, RTW_ANAPARM); 2281 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2282 2283 switch (power) { 2284 case RTW_OFF: 2285 if (before_rf) 2286 return; 2287 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2288 anaparm |= RTW_ANAPARM_TXDACOFF; 2289 break; 2290 case RTW_SLEEP: 2291 if (!before_rf) 2292 return; 2293 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2294 anaparm |= RTW_ANAPARM_TXDACOFF; 2295 break; 2296 case RTW_ON: 2297 if (!before_rf) 2298 return; 2299 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2300 break; 2301 } 2302 RTW_DPRINTF(RTW_DEBUG_PWR, 2303 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2304 __func__, rtw_pwrstate_string(power), 2305 (before_rf) ? "before" : "after", anaparm)); 2306 2307 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2308 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2309 } 2310 2311 static void 2312 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2313 int before_rf, int digphy) 2314 { 2315 uint32_t anaparm; 2316 2317 anaparm = RTW_READ(regs, RTW_ANAPARM); 2318 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2319 2320 switch (power) { 2321 case RTW_OFF: 2322 if (before_rf) 2323 return; 2324 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2325 anaparm |= RTW_ANAPARM_TXDACOFF; 2326 break; 2327 case RTW_SLEEP: 2328 if (!before_rf) 2329 return; 2330 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2331 anaparm |= RTW_ANAPARM_TXDACOFF; 2332 break; 2333 case RTW_ON: 2334 if (!before_rf) 2335 return; 2336 if (digphy) { 2337 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2338 /* XXX guess */ 2339 anaparm |= RTW_ANAPARM_TXDACOFF; 2340 } else 2341 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2342 break; 2343 } 2344 RTW_DPRINTF(RTW_DEBUG_PWR, 2345 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2346 __func__, rtw_pwrstate_string(power), 2347 (before_rf) ? "before" : "after", anaparm)); 2348 2349 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2350 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2351 } 2352 2353 static void 2354 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2355 int digphy) 2356 { 2357 struct rtw_regs *regs = &sc->sc_regs; 2358 2359 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2360 2361 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2362 2363 rtw_set_access(regs, RTW_ACCESS_NONE); 2364 2365 return; 2366 } 2367 2368 static int 2369 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2370 { 2371 int rc; 2372 2373 RTW_DPRINTF(RTW_DEBUG_PWR, 2374 ("%s: %s->%s\n", __func__, 2375 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2376 2377 if (sc->sc_pwrstate == power) 2378 return 0; 2379 2380 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2381 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2382 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2383 2384 switch (power) { 2385 case RTW_ON: 2386 /* TBD set LEDs */ 2387 break; 2388 case RTW_SLEEP: 2389 /* TBD */ 2390 break; 2391 case RTW_OFF: 2392 /* TBD */ 2393 break; 2394 } 2395 if (rc == 0) 2396 sc->sc_pwrstate = power; 2397 else 2398 sc->sc_pwrstate = RTW_OFF; 2399 return rc; 2400 } 2401 2402 static int 2403 rtw_tune(struct rtw_softc *sc) 2404 { 2405 struct ieee80211com *ic = &sc->sc_ic; 2406 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 2407 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 2408 u_int chan; 2409 int rc; 2410 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2411 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2412 2413 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2414 if (chan == IEEE80211_CHAN_ANY) 2415 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 2416 2417 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2418 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2419 2420 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2421 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2422 2423 if (chan == sc->sc_cur_chan) { 2424 RTW_DPRINTF(RTW_DEBUG_TUNE, 2425 ("%s: already tuned chan #%d\n", __func__, chan)); 2426 return 0; 2427 } 2428 2429 rtw_suspend_ticks(sc); 2430 2431 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2432 2433 /* TBD wait for Tx to complete */ 2434 2435 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2436 2437 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2438 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr, 2439 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) { 2440 /* XXX condition on powersaving */ 2441 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2442 } 2443 2444 sc->sc_cur_chan = chan; 2445 2446 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2447 2448 rtw_resume_ticks(sc); 2449 2450 return rc; 2451 } 2452 2453 void 2454 rtw_disable(struct rtw_softc *sc) 2455 { 2456 int rc; 2457 2458 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2459 return; 2460 2461 /* turn off PHY */ 2462 if ((sc->sc_flags & RTW_F_INVALID) == 0 && 2463 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2464 printf("%s: failed to turn off PHY (%d)\n", 2465 sc->sc_dev.dv_xname, rc); 2466 } 2467 2468 if (sc->sc_disable != NULL) 2469 (*sc->sc_disable)(sc); 2470 2471 sc->sc_flags &= ~RTW_F_ENABLED; 2472 } 2473 2474 int 2475 rtw_enable(struct rtw_softc *sc) 2476 { 2477 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2478 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2479 printf("%s: device enable failed\n", 2480 sc->sc_dev.dv_xname); 2481 return (EIO); 2482 } 2483 sc->sc_flags |= RTW_F_ENABLED; 2484 /* Power may have been removed, and WEP keys thus 2485 * reset. 2486 */ 2487 sc->sc_flags &= ~RTW_F_DK_VALID; 2488 } 2489 return (0); 2490 } 2491 2492 static void 2493 rtw_transmit_config(struct rtw_regs *regs) 2494 { 2495 uint32_t tcr; 2496 2497 tcr = RTW_READ(regs, RTW_TCR); 2498 2499 tcr |= RTW_TCR_CWMIN; 2500 tcr &= ~RTW_TCR_MXDMA_MASK; 2501 tcr |= RTW_TCR_MXDMA_256; 2502 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2503 tcr &= ~RTW_TCR_LBK_MASK; 2504 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2505 2506 /* set short/long retry limits */ 2507 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2508 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK); 2509 2510 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2511 2512 RTW_WRITE(regs, RTW_TCR, tcr); 2513 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2514 } 2515 2516 static inline void 2517 rtw_enable_interrupts(struct rtw_softc *sc) 2518 { 2519 struct rtw_regs *regs = &sc->sc_regs; 2520 2521 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2522 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2523 2524 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2525 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2526 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2527 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2528 2529 /* XXX necessary? */ 2530 if (sc->sc_intr_ack != NULL) 2531 (*sc->sc_intr_ack)(regs); 2532 } 2533 2534 static void 2535 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2536 { 2537 uint8_t msr; 2538 2539 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2540 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2541 2542 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2543 2544 switch (opmode) { 2545 case IEEE80211_M_AHDEMO: 2546 case IEEE80211_M_IBSS: 2547 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2548 break; 2549 case IEEE80211_M_HOSTAP: 2550 msr |= RTW_MSR_NETYPE_AP_OK; 2551 break; 2552 case IEEE80211_M_MONITOR: 2553 /* XXX */ 2554 msr |= RTW_MSR_NETYPE_NOLINK; 2555 break; 2556 case IEEE80211_M_STA: 2557 msr |= RTW_MSR_NETYPE_INFRA_OK; 2558 break; 2559 } 2560 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2561 2562 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2563 } 2564 2565 #define rtw_calchash(addr) \ 2566 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2567 2568 static void 2569 rtw_pktfilt_load(struct rtw_softc *sc) 2570 { 2571 struct rtw_regs *regs = &sc->sc_regs; 2572 struct ieee80211com *ic = &sc->sc_ic; 2573 struct ethercom *ec = &sc->sc_ec; 2574 struct ifnet *ifp = &sc->sc_if; 2575 int hash; 2576 uint32_t hashes[2] = { 0, 0 }; 2577 struct ether_multi *enm; 2578 struct ether_multistep step; 2579 2580 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2581 2582 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2583 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2584 2585 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2586 /* MAC auto-reset PHY (huh?) */ 2587 sc->sc_rcr |= RTW_RCR_ENMARP; 2588 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2589 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2590 2591 switch (ic->ic_opmode) { 2592 case IEEE80211_M_MONITOR: 2593 sc->sc_rcr |= RTW_RCR_MONITOR; 2594 break; 2595 case IEEE80211_M_AHDEMO: 2596 case IEEE80211_M_IBSS: 2597 /* receive broadcasts in our BSS */ 2598 sc->sc_rcr |= RTW_RCR_ADD3; 2599 break; 2600 default: 2601 break; 2602 } 2603 2604 ifp->if_flags &= ~IFF_ALLMULTI; 2605 2606 /* 2607 * Program the 64-bit multicast hash filter. 2608 */ 2609 ETHER_FIRST_MULTI(step, ec, enm); 2610 while (enm != NULL) { 2611 /* XXX */ 2612 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2613 ETHER_ADDR_LEN) != 0) { 2614 ifp->if_flags |= IFF_ALLMULTI; 2615 break; 2616 } 2617 2618 hash = rtw_calchash(enm->enm_addrlo); 2619 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2620 ETHER_NEXT_MULTI(step, enm); 2621 } 2622 2623 /* XXX accept all broadcast if scanning */ 2624 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2625 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2626 2627 if (ifp->if_flags & IFF_PROMISC) { 2628 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2629 ifp->if_flags |= IFF_ALLMULTI; 2630 } 2631 2632 if (ifp->if_flags & IFF_ALLMULTI) 2633 hashes[0] = hashes[1] = 0xffffffff; 2634 2635 if ((hashes[0] | hashes[1]) != 0) 2636 sc->sc_rcr |= RTW_RCR_AM; /* accept multicast */ 2637 2638 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2639 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2640 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2641 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2642 2643 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2644 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2645 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2646 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2647 } 2648 2649 static struct mbuf * 2650 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2651 { 2652 struct ieee80211com *ic = &sc->sc_ic; 2653 struct mbuf *m; 2654 struct ieee80211_beacon_offsets boff; 2655 2656 if ((m = ieee80211_beacon_alloc(ic, ni, &boff)) != NULL) { 2657 RTW_DPRINTF(RTW_DEBUG_BEACON, 2658 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2659 } 2660 return m; 2661 } 2662 2663 /* Must be called at splnet. */ 2664 static int 2665 rtw_init(struct ifnet *ifp) 2666 { 2667 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2668 struct ieee80211com *ic = &sc->sc_ic; 2669 struct rtw_regs *regs = &sc->sc_regs; 2670 int rc = 0; 2671 2672 if ((rc = rtw_enable(sc)) != 0) 2673 goto out; 2674 2675 /* Cancel pending I/O and reset. */ 2676 rtw_stop(ifp, 0); 2677 2678 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2679 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 2680 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 2681 2682 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2683 goto out; 2684 2685 if ((rc = rtw_swring_setup(sc)) != 0) 2686 goto out; 2687 2688 rtw_transmit_config(regs); 2689 2690 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2691 2692 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2693 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2694 2695 /* long PLCP header, 1Mb/2Mb basic rate */ 2696 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2697 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2698 2699 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2700 rtw_set_access(regs, RTW_ACCESS_NONE); 2701 2702 /* XXX from reference sources */ 2703 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2704 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2705 2706 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2707 2708 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2709 /* from Linux driver */ 2710 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2711 2712 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2713 2714 rtw_enable_interrupts(sc); 2715 2716 rtw_pktfilt_load(sc); 2717 2718 rtw_hwring_setup(sc); 2719 2720 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2721 2722 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2723 2724 ifp->if_flags |= IFF_RUNNING; 2725 ic->ic_state = IEEE80211_S_INIT; 2726 2727 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2728 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2729 2730 rtw_resume_ticks(sc); 2731 2732 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2733 2734 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2735 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2736 else 2737 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2738 2739 out: 2740 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2741 return rc; 2742 } 2743 2744 static inline void 2745 rtw_led_init(struct rtw_regs *regs) 2746 { 2747 uint8_t cfg0, cfg1; 2748 2749 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2750 2751 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2752 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2753 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2754 2755 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2756 RTW_DPRINTF(RTW_DEBUG_LED, 2757 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2758 2759 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2760 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2761 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2762 2763 rtw_set_access(regs, RTW_ACCESS_NONE); 2764 } 2765 2766 /* 2767 * IEEE80211_S_INIT: LED1 off 2768 * 2769 * IEEE80211_S_AUTH, 2770 * IEEE80211_S_ASSOC, 2771 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2772 * 2773 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2774 */ 2775 static void 2776 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2777 { 2778 struct rtw_led_state *ls; 2779 2780 ls = &sc->sc_led_state; 2781 2782 switch (nstate) { 2783 case IEEE80211_S_INIT: 2784 rtw_led_init(&sc->sc_regs); 2785 callout_stop(&ls->ls_slow_ch); 2786 callout_stop(&ls->ls_fast_ch); 2787 ls->ls_slowblink = 0; 2788 ls->ls_actblink = 0; 2789 ls->ls_default = 0; 2790 break; 2791 case IEEE80211_S_SCAN: 2792 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2793 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2794 /*FALLTHROUGH*/ 2795 case IEEE80211_S_AUTH: 2796 case IEEE80211_S_ASSOC: 2797 ls->ls_default = RTW_LED1; 2798 ls->ls_actblink = RTW_LED1; 2799 ls->ls_slowblink = RTW_LED1; 2800 break; 2801 case IEEE80211_S_RUN: 2802 ls->ls_slowblink = 0; 2803 break; 2804 } 2805 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2806 } 2807 2808 static void 2809 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2810 { 2811 uint8_t led_condition; 2812 bus_size_t ofs; 2813 uint8_t mask, newval, val; 2814 2815 led_condition = ls->ls_default; 2816 2817 if (ls->ls_state & RTW_LED_S_SLOW) 2818 led_condition ^= ls->ls_slowblink; 2819 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2820 led_condition ^= ls->ls_actblink; 2821 2822 RTW_DPRINTF(RTW_DEBUG_LED, 2823 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2824 2825 switch (hwverid) { 2826 default: 2827 case 'F': 2828 ofs = RTW_PSR; 2829 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2830 if (led_condition & RTW_LED0) 2831 newval &= ~RTW_PSR_LEDGPO0; 2832 if (led_condition & RTW_LED1) 2833 newval &= ~RTW_PSR_LEDGPO1; 2834 break; 2835 case 'D': 2836 ofs = RTW_9346CR; 2837 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2838 newval = RTW_9346CR_EEM_PROGRAM; 2839 if (led_condition & RTW_LED0) 2840 newval |= RTW_9346CR_EEDI; 2841 if (led_condition & RTW_LED1) 2842 newval |= RTW_9346CR_EECS; 2843 break; 2844 } 2845 val = RTW_READ8(regs, ofs); 2846 RTW_DPRINTF(RTW_DEBUG_LED, 2847 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2848 (uintptr_t)ofs)); 2849 val &= ~mask; 2850 val |= newval; 2851 RTW_WRITE8(regs, ofs, val); 2852 RTW_DPRINTF(RTW_DEBUG_LED, 2853 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2854 (uintptr_t)ofs)); 2855 RTW_SYNC(regs, ofs, ofs); 2856 } 2857 2858 static void 2859 rtw_led_fastblink(void *arg) 2860 { 2861 int ostate, s; 2862 struct rtw_softc *sc = (struct rtw_softc *)arg; 2863 struct rtw_led_state *ls = &sc->sc_led_state; 2864 2865 s = splnet(); 2866 ostate = ls->ls_state; 2867 ls->ls_state ^= ls->ls_event; 2868 2869 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2870 ls->ls_state &= ~RTW_LED_S_TX; 2871 2872 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2873 ls->ls_state &= ~RTW_LED_S_RX; 2874 2875 ls->ls_event = 0; 2876 2877 if (ostate != ls->ls_state) 2878 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2879 splx(s); 2880 2881 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2882 } 2883 2884 static void 2885 rtw_led_slowblink(void *arg) 2886 { 2887 int s; 2888 struct rtw_softc *sc = (struct rtw_softc *)arg; 2889 struct rtw_led_state *ls = &sc->sc_led_state; 2890 2891 s = splnet(); 2892 ls->ls_state ^= RTW_LED_S_SLOW; 2893 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2894 splx(s); 2895 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2896 } 2897 2898 static inline void 2899 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2900 { 2901 callout_init(&ls->ls_fast_ch); 2902 callout_init(&ls->ls_slow_ch); 2903 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2904 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2905 } 2906 2907 static int 2908 rtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2909 { 2910 int rc = 0, s; 2911 struct rtw_softc *sc = ifp->if_softc; 2912 2913 s = splnet(); 2914 if (cmd == SIOCSIFFLAGS) { 2915 if ((ifp->if_flags & IFF_UP) != 0) { 2916 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2917 rtw_pktfilt_load(sc); 2918 else 2919 rc = rtw_init(ifp); 2920 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2921 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2922 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2923 rtw_stop(ifp, 1); 2924 } 2925 } else if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 2926 ; /* nothing to do */ 2927 else if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 2928 /* reload packet filter if running */ 2929 if (ifp->if_flags & IFF_RUNNING) 2930 rtw_pktfilt_load(sc); 2931 rc = 0; 2932 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2933 /* reinitialize h/w if activated */ 2934 rc = rtw_init(ifp); 2935 else 2936 rc = 0; 2937 splx(s); 2938 return rc; 2939 } 2940 2941 /* Select a transmit ring with at least one h/w and s/w descriptor free. 2942 * Return 0 on success, -1 on failure. 2943 */ 2944 static inline int 2945 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 2946 struct rtw_txdesc_blk **tdbp, int pri) 2947 { 2948 struct rtw_txsoft_blk *tsb; 2949 struct rtw_txdesc_blk *tdb; 2950 2951 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 2952 2953 tsb = &sc->sc_txsoft_blk[pri]; 2954 tdb = &sc->sc_txdesc_blk[pri]; 2955 2956 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 2957 if (tsb->tsb_tx_timer == 0) 2958 tsb->tsb_tx_timer = 5; 2959 *tsbp = NULL; 2960 *tdbp = NULL; 2961 return -1; 2962 } 2963 *tsbp = tsb; 2964 *tdbp = tdb; 2965 return 0; 2966 } 2967 2968 static inline struct mbuf * 2969 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 2970 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 2971 struct ieee80211_node **nip, short *if_flagsp) 2972 { 2973 struct mbuf *m; 2974 2975 if (IF_IS_EMPTY(ifq)) 2976 return NULL; 2977 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 2978 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 2979 __func__, pri)); 2980 *if_flagsp |= IFF_OACTIVE; 2981 sc->sc_if.if_timer = 1; 2982 return NULL; 2983 } 2984 IF_DEQUEUE(ifq, m); 2985 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2986 m->m_pkthdr.rcvif = NULL; 2987 KASSERT(*nip != NULL); 2988 return m; 2989 } 2990 2991 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 2992 * at the driver's selection of transmit control block for the packet. 2993 */ 2994 static inline int 2995 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 2996 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 2997 struct ieee80211_node **nip) 2998 { 2999 int pri; 3000 struct ether_header *eh; 3001 struct mbuf *m0; 3002 struct rtw_softc *sc; 3003 short *if_flagsp; 3004 3005 *mp = NULL; 3006 3007 sc = (struct rtw_softc *)ifp->if_softc; 3008 3009 DPRINTF(sc, RTW_DEBUG_XMIT, 3010 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3011 3012 if_flagsp = &ifp->if_flags; 3013 3014 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 3015 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 3016 tdbp, nip, if_flagsp)) != NULL) { 3017 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 3018 __func__)); 3019 return 0; 3020 } 3021 3022 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 3023 tdbp, nip, if_flagsp)) != NULL) { 3024 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 3025 __func__)); 3026 return 0; 3027 } 3028 3029 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 3030 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 3031 return 0; 3032 } 3033 3034 IFQ_POLL(&ifp->if_snd, m0); 3035 if (m0 == NULL) { 3036 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3037 __func__)); 3038 return 0; 3039 } 3040 3041 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 3042 3043 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3044 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3045 __func__, pri)); 3046 *if_flagsp |= IFF_OACTIVE; 3047 sc->sc_if.if_timer = 1; 3048 return 0; 3049 } 3050 3051 IFQ_DEQUEUE(&ifp->if_snd, m0); 3052 if (m0 == NULL) { 3053 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3054 __func__)); 3055 return 0; 3056 } 3057 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 3058 ifp->if_opackets++; 3059 #if NBPFILTER > 0 3060 if (ifp->if_bpf) 3061 bpf_mtap(ifp->if_bpf, m0); 3062 #endif 3063 eh = mtod(m0, struct ether_header *); 3064 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 3065 if (*nip == NULL) { 3066 /* NB: ieee80211_find_txnode does stat+msg */ 3067 m_freem(m0); 3068 return -1; 3069 } 3070 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 3071 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 3072 ifp->if_oerrors++; 3073 return -1; 3074 } 3075 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3076 *mp = m0; 3077 return 0; 3078 } 3079 3080 static int 3081 rtw_seg_too_short(bus_dmamap_t dmamap) 3082 { 3083 int i; 3084 for (i = 0; i < dmamap->dm_nsegs; i++) { 3085 if (dmamap->dm_segs[i].ds_len < 4) 3086 return 1; 3087 } 3088 return 0; 3089 } 3090 3091 /* TBD factor with atw_start */ 3092 static struct mbuf * 3093 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 3094 u_int ndescfree, const char *dvname) 3095 { 3096 int first, rc; 3097 struct mbuf *m, *m0; 3098 3099 m0 = chain; 3100 3101 /* 3102 * Load the DMA map. Copy and try (once) again if the packet 3103 * didn't fit in the alloted number of segments. 3104 */ 3105 for (first = 1; 3106 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 3107 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 3108 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 3109 first = 0) { 3110 if (rc == 0) { 3111 #ifdef RTW_DIAGxxx 3112 if (rtw_seg_too_short(dmam)) { 3113 printf("%s: short segment, mbuf lengths:", __func__); 3114 for (m = m0; m; m = m->m_next) 3115 printf(" %d", m->m_len); 3116 printf("\n"); 3117 } 3118 #endif 3119 bus_dmamap_unload(dmat, dmam); 3120 } 3121 MGETHDR(m, M_DONTWAIT, MT_DATA); 3122 if (m == NULL) { 3123 printf("%s: unable to allocate Tx mbuf\n", 3124 dvname); 3125 break; 3126 } 3127 if (m0->m_pkthdr.len > MHLEN) { 3128 MCLGET(m, M_DONTWAIT); 3129 if ((m->m_flags & M_EXT) == 0) { 3130 printf("%s: cannot allocate Tx cluster\n", 3131 dvname); 3132 m_freem(m); 3133 break; 3134 } 3135 } 3136 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3137 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3138 m_freem(m0); 3139 m0 = m; 3140 m = NULL; 3141 } 3142 if (rc != 0) { 3143 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 3144 m_freem(m0); 3145 return NULL; 3146 } else if (rtw_seg_too_short(dmam)) { 3147 printf("%s: cannot load Tx buffer, segment too short\n", 3148 dvname); 3149 bus_dmamap_unload(dmat, dmam); 3150 m_freem(m0); 3151 return NULL; 3152 } else if (dmam->dm_nsegs > ndescfree) { 3153 printf("%s: too many tx segments\n", dvname); 3154 bus_dmamap_unload(dmat, dmam); 3155 m_freem(m0); 3156 return NULL; 3157 } 3158 return m0; 3159 } 3160 3161 #ifdef RTW_DEBUG 3162 static void 3163 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3164 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3165 { 3166 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3167 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] next %#08x " 3168 "buf %#08x ctl0 %#08x ctl1 %#08x len %#08x\n", 3169 sc->sc_dev.dv_xname, ts, action, desc, 3170 le32toh(td->td_buf), le32toh(td->td_next), 3171 le32toh(td->td_ctl0), le32toh(td->td_ctl1), 3172 le32toh(td->td_len))); 3173 } 3174 #endif /* RTW_DEBUG */ 3175 3176 static void 3177 rtw_start(struct ifnet *ifp) 3178 { 3179 uint8_t tppoll; 3180 int desc, i, lastdesc, npkt, rate; 3181 uint32_t proto_ctl0, ctl0, ctl1; 3182 bus_dmamap_t dmamap; 3183 struct ieee80211com *ic; 3184 struct ieee80211_duration *d0; 3185 struct ieee80211_frame_min *wh; 3186 struct ieee80211_node *ni = NULL; /* XXX: GCC */ 3187 struct mbuf *m0; 3188 struct rtw_softc *sc; 3189 struct rtw_txsoft_blk *tsb = NULL; /* XXX: GCC */ 3190 struct rtw_txdesc_blk *tdb = NULL; /* XXX: GCC */ 3191 struct rtw_txsoft *ts; 3192 struct rtw_txdesc *td; 3193 struct ieee80211_key *k; 3194 3195 sc = (struct rtw_softc *)ifp->if_softc; 3196 ic = &sc->sc_ic; 3197 3198 DPRINTF(sc, RTW_DEBUG_XMIT, 3199 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3200 3201 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3202 goto out; 3203 3204 /* XXX do real rate control */ 3205 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3206 3207 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3208 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3209 3210 for (;;) { 3211 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3212 continue; 3213 if (m0 == NULL) 3214 break; 3215 3216 wh = mtod(m0, struct ieee80211_frame_min *); 3217 3218 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3219 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3220 m_freem(m0); 3221 break; 3222 } else 3223 k = NULL; 3224 3225 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3226 3227 dmamap = ts->ts_dmamap; 3228 3229 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3230 tdb->tdb_nfree, sc->sc_dev.dv_xname); 3231 3232 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3233 DPRINTF(sc, RTW_DEBUG_XMIT, 3234 ("%s: fail dmamap load\n", __func__)); 3235 goto post_dequeue_err; 3236 } 3237 3238 /* Note well: rtw_dmamap_load_txbuf may have created 3239 * a new chain, so we must find the header once 3240 * more. 3241 */ 3242 wh = mtod(m0, struct ieee80211_frame_min *); 3243 3244 /* XXX do real rate control */ 3245 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3246 IEEE80211_FC0_TYPE_MGT) 3247 rate = 2; 3248 else 3249 rate = MAX(2, ieee80211_get_rate(ni)); 3250 3251 #ifdef RTW_DEBUG 3252 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3253 (IFF_DEBUG|IFF_LINK2)) { 3254 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3255 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3256 : sizeof(wh), 3257 rate, 0); 3258 } 3259 #endif /* RTW_DEBUG */ 3260 ctl0 = proto_ctl0 | 3261 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3262 3263 switch (rate) { 3264 default: 3265 case 2: 3266 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3267 break; 3268 case 4: 3269 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3270 break; 3271 case 11: 3272 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3273 break; 3274 case 22: 3275 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3276 break; 3277 } 3278 /* XXX >= ? Compare after fragmentation? */ 3279 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3280 ctl0 |= RTW_TXCTL0_RTSEN; 3281 3282 /* XXX Sometimes writes a bogus keyid; h/w doesn't 3283 * seem to care, since we don't activate h/w Tx 3284 * encryption. 3285 */ 3286 if (k != NULL) { 3287 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3288 RTW_TXCTL0_KEYID_MASK; 3289 } 3290 3291 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3292 IEEE80211_FC0_TYPE_MGT) { 3293 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3294 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3295 IEEE80211_FC0_SUBTYPE_BEACON) 3296 ctl0 |= RTW_TXCTL0_BEACON; 3297 } 3298 3299 if (ieee80211_compute_duration(wh, k, m0->m_pkthdr.len, 3300 ic->ic_flags, ic->ic_fragthreshold, 3301 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3302 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3303 (IFF_DEBUG|IFF_LINK2)) == -1) { 3304 DPRINTF(sc, RTW_DEBUG_XMIT, 3305 ("%s: fail compute duration\n", __func__)); 3306 goto post_load_err; 3307 } 3308 3309 d0 = &ts->ts_d0; 3310 3311 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3312 3313 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3314 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3315 3316 if (d0->d_residue) 3317 ctl1 |= RTW_TXCTL1_LENGEXT; 3318 3319 /* TBD fragmentation */ 3320 3321 ts->ts_first = tdb->tdb_next; 3322 3323 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3324 BUS_DMASYNC_PREWRITE); 3325 3326 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3327 3328 #if NBPFILTER > 0 3329 if (ic->ic_rawbpf != NULL) 3330 bpf_mtap((void *)ic->ic_rawbpf, m0); 3331 3332 if (sc->sc_radiobpf != NULL) { 3333 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3334 3335 rt->rt_flags = 0; 3336 rt->rt_rate = rate; 3337 3338 bpf_mtap2(sc->sc_radiobpf, (void *)rt, 3339 sizeof(sc->sc_txtapu), m0); 3340 } 3341 #endif /* NPBFILTER > 0 */ 3342 3343 for (i = 0, lastdesc = desc = ts->ts_first; 3344 i < dmamap->dm_nsegs; 3345 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3346 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3347 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3348 ("%s: seg too long\n", __func__)); 3349 goto post_load_err; 3350 } 3351 td = &tdb->tdb_desc[desc]; 3352 td->td_ctl0 = htole32(ctl0); 3353 if (i != 0) 3354 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3355 td->td_ctl1 = htole32(ctl1); 3356 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3357 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3358 lastdesc = desc; 3359 #ifdef RTW_DEBUG 3360 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3361 #endif /* RTW_DEBUG */ 3362 } 3363 3364 KASSERT(desc < tdb->tdb_ndesc); 3365 3366 ts->ts_ni = ni; 3367 KASSERT(ni != NULL); 3368 ts->ts_mbuf = m0; 3369 ts->ts_last = lastdesc; 3370 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3371 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3372 htole32(RTW_TXCTL0_FS); 3373 3374 #ifdef RTW_DEBUG 3375 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3376 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3377 #endif /* RTW_DEBUG */ 3378 3379 tdb->tdb_nfree -= dmamap->dm_nsegs; 3380 tdb->tdb_next = desc; 3381 3382 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3383 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3384 3385 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3386 htole32(RTW_TXCTL0_OWN); 3387 3388 #ifdef RTW_DEBUG 3389 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3390 #endif /* RTW_DEBUG */ 3391 3392 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3393 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3394 3395 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3396 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3397 3398 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) 3399 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3400 tsb->tsb_tx_timer = 5; 3401 ifp->if_timer = 1; 3402 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3403 tppoll &= ~RTW_TPPOLL_SALL; 3404 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL; 3405 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3406 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3407 } 3408 out: 3409 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3410 return; 3411 post_load_err: 3412 bus_dmamap_unload(sc->sc_dmat, dmamap); 3413 m_freem(m0); 3414 post_dequeue_err: 3415 ieee80211_free_node(ni); 3416 return; 3417 } 3418 3419 static void 3420 rtw_idle(struct rtw_regs *regs) 3421 { 3422 int active; 3423 3424 /* request stop DMA; wait for packets to stop transmitting. */ 3425 3426 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3427 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL); 3428 3429 for (active = 0; active < 300 && 3430 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0; active++) 3431 DELAY(10); 3432 printf("%s: transmit DMA idle in %dus\n", __func__, active * 10); 3433 } 3434 3435 static void 3436 rtw_watchdog(struct ifnet *ifp) 3437 { 3438 int pri, tx_timeouts = 0; 3439 struct rtw_softc *sc; 3440 struct rtw_txsoft_blk *tsb; 3441 3442 sc = ifp->if_softc; 3443 3444 ifp->if_timer = 0; 3445 3446 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 3447 return; 3448 3449 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3450 tsb = &sc->sc_txsoft_blk[pri]; 3451 3452 if (tsb->tsb_tx_timer == 0) 3453 continue; 3454 else if (--tsb->tsb_tx_timer == 0) { 3455 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3456 continue; 3457 printf("%s: transmit timeout, priority %d\n", 3458 ifp->if_xname, pri); 3459 ifp->if_oerrors++; 3460 if (pri != RTW_TXPRIBCN) 3461 tx_timeouts++; 3462 } else 3463 ifp->if_timer = 1; 3464 } 3465 3466 if (tx_timeouts > 0) { 3467 /* Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr, 3468 * reset s/w tx-ring pointers, and start transmission. 3469 * 3470 * TBD Stop/restart just the broken rings? 3471 */ 3472 rtw_idle(&sc->sc_regs); 3473 rtw_io_enable(sc, RTW_CR_TE, 0); 3474 rtw_txdescs_reset(sc); 3475 rtw_io_enable(sc, RTW_CR_TE, 1); 3476 rtw_start(ifp); 3477 } 3478 ieee80211_watchdog(&sc->sc_ic); 3479 return; 3480 } 3481 3482 static void 3483 rtw_next_scan(void *arg) 3484 { 3485 struct ieee80211com *ic = arg; 3486 int s; 3487 3488 /* don't call rtw_start w/o network interrupts blocked */ 3489 s = splnet(); 3490 if (ic->ic_state == IEEE80211_S_SCAN) 3491 ieee80211_next_scan(ic); 3492 splx(s); 3493 } 3494 3495 static void 3496 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3497 { 3498 uint16_t bcnitv, bintritv, intval; 3499 int i; 3500 struct rtw_regs *regs = &sc->sc_regs; 3501 3502 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3503 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3504 3505 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3506 3507 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3508 3509 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); 3510 3511 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3512 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); 3513 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3514 /* interrupt host 1ms before the TBTT */ 3515 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV; 3516 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV); 3517 RTW_WRITE16(regs, RTW_BINTRITV, bintritv); 3518 /* magic from Linux */ 3519 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND)); 3520 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); 3521 rtw_set_access(regs, RTW_ACCESS_NONE); 3522 3523 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 3524 } 3525 3526 /* Synchronize the hardware state with the software state. */ 3527 static int 3528 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3529 { 3530 struct ifnet *ifp = ic->ic_ifp; 3531 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3532 enum ieee80211_state ostate; 3533 int error; 3534 3535 ostate = ic->ic_state; 3536 3537 rtw_led_newstate(sc, nstate); 3538 3539 if (nstate == IEEE80211_S_INIT) { 3540 callout_stop(&sc->sc_scan_ch); 3541 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3542 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3543 } 3544 3545 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3546 rtw_pwrstate(sc, RTW_ON); 3547 3548 if ((error = rtw_tune(sc)) != 0) 3549 return error; 3550 3551 switch (nstate) { 3552 case IEEE80211_S_INIT: 3553 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3554 break; 3555 case IEEE80211_S_SCAN: 3556 if (ostate != IEEE80211_S_SCAN) { 3557 (void)memset(ic->ic_bss->ni_bssid, 0, 3558 IEEE80211_ADDR_LEN); 3559 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3560 } 3561 3562 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3563 rtw_next_scan, ic); 3564 3565 break; 3566 case IEEE80211_S_RUN: 3567 switch (ic->ic_opmode) { 3568 case IEEE80211_M_HOSTAP: 3569 case IEEE80211_M_IBSS: 3570 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3571 /*FALLTHROUGH*/ 3572 case IEEE80211_M_AHDEMO: 3573 case IEEE80211_M_STA: 3574 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3575 ic->ic_bss->ni_intval); 3576 break; 3577 case IEEE80211_M_MONITOR: 3578 break; 3579 } 3580 rtw_set_nettype(sc, ic->ic_opmode); 3581 break; 3582 case IEEE80211_S_ASSOC: 3583 case IEEE80211_S_AUTH: 3584 break; 3585 } 3586 3587 if (nstate != IEEE80211_S_SCAN) 3588 callout_stop(&sc->sc_scan_ch); 3589 3590 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3591 } 3592 3593 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3594 static uint64_t 3595 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3596 { 3597 uint32_t tsftl, tsfth; 3598 3599 tsfth = RTW_READ(regs, RTW_TSFTRH); 3600 tsftl = RTW_READ(regs, RTW_TSFTRL); 3601 if (tsftl < rstamp) /* Compensate for rollover. */ 3602 tsfth--; 3603 return ((uint64_t)tsfth << 32) | rstamp; 3604 } 3605 3606 static void 3607 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3608 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3609 { 3610 struct ifnet *ifp = ic->ic_ifp; 3611 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3612 3613 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3614 3615 switch (subtype) { 3616 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3617 case IEEE80211_FC0_SUBTYPE_BEACON: 3618 if (ic->ic_opmode == IEEE80211_M_IBSS && 3619 ic->ic_state == IEEE80211_S_RUN) { 3620 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp); 3621 if (le64toh(ni->ni_tstamp.tsf) >= tsf) 3622 (void)ieee80211_ibss_merge(ni); 3623 } 3624 break; 3625 default: 3626 break; 3627 } 3628 return; 3629 } 3630 3631 static struct ieee80211_node * 3632 rtw_node_alloc(struct ieee80211_node_table *nt) 3633 { 3634 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3635 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3636 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3637 3638 DPRINTF(sc, RTW_DEBUG_NODE, 3639 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3640 return ni; 3641 } 3642 3643 static void 3644 rtw_node_free(struct ieee80211_node *ni) 3645 { 3646 struct ieee80211com *ic = ni->ni_ic; 3647 struct ifnet *ifp = ic->ic_ifp; 3648 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3649 3650 DPRINTF(sc, RTW_DEBUG_NODE, 3651 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3652 ether_sprintf(ni->ni_bssid))); 3653 (*sc->sc_mtbl.mt_node_free)(ni); 3654 } 3655 3656 static int 3657 rtw_media_change(struct ifnet *ifp) 3658 { 3659 int error; 3660 3661 error = ieee80211_media_change(ifp); 3662 if (error == ENETRESET) { 3663 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3664 (IFF_RUNNING|IFF_UP)) 3665 rtw_init(ifp); /* XXX lose error */ 3666 error = 0; 3667 } 3668 return error; 3669 } 3670 3671 static void 3672 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3673 { 3674 struct rtw_softc *sc = ifp->if_softc; 3675 3676 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3677 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3678 imr->ifm_status = 0; 3679 return; 3680 } 3681 ieee80211_media_status(ifp, imr); 3682 } 3683 3684 void 3685 rtw_power(int why, void *arg) 3686 { 3687 struct rtw_softc *sc = arg; 3688 struct ifnet *ifp = &sc->sc_if; 3689 int s; 3690 3691 DPRINTF(sc, RTW_DEBUG_PWR, 3692 ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3693 3694 s = splnet(); 3695 switch (why) { 3696 case PWR_STANDBY: 3697 /* XXX do nothing. */ 3698 break; 3699 case PWR_SUSPEND: 3700 rtw_stop(ifp, 0); 3701 if (sc->sc_power != NULL) 3702 (*sc->sc_power)(sc, why); 3703 break; 3704 case PWR_RESUME: 3705 if (ifp->if_flags & IFF_UP) { 3706 if (sc->sc_power != NULL) 3707 (*sc->sc_power)(sc, why); 3708 rtw_init(ifp); 3709 } 3710 break; 3711 case PWR_SOFTSUSPEND: 3712 case PWR_SOFTSTANDBY: 3713 case PWR_SOFTRESUME: 3714 break; 3715 } 3716 splx(s); 3717 } 3718 3719 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 3720 void 3721 rtw_shutdown(void *arg) 3722 { 3723 struct rtw_softc *sc = arg; 3724 3725 rtw_stop(&sc->sc_if, 1); 3726 } 3727 3728 static inline void 3729 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3730 { 3731 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3732 ifp->if_softc = softc; 3733 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3734 IFF_NOTRAILERS; 3735 ifp->if_ioctl = rtw_ioctl; 3736 ifp->if_start = rtw_start; 3737 ifp->if_watchdog = rtw_watchdog; 3738 ifp->if_init = rtw_init; 3739 ifp->if_stop = rtw_stop; 3740 } 3741 3742 static inline void 3743 rtw_set80211props(struct ieee80211com *ic) 3744 { 3745 int nrate; 3746 ic->ic_phytype = IEEE80211_T_DS; 3747 ic->ic_opmode = IEEE80211_M_STA; 3748 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3749 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 3750 3751 nrate = 0; 3752 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3753 IEEE80211_RATE_BASIC | 2; 3754 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3755 IEEE80211_RATE_BASIC | 4; 3756 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3757 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3758 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3759 } 3760 3761 static inline void 3762 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3763 { 3764 mtbl->mt_newstate = ic->ic_newstate; 3765 ic->ic_newstate = rtw_newstate; 3766 3767 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3768 ic->ic_recv_mgmt = rtw_recv_mgmt; 3769 3770 mtbl->mt_node_free = ic->ic_node_free; 3771 ic->ic_node_free = rtw_node_free; 3772 3773 mtbl->mt_node_alloc = ic->ic_node_alloc; 3774 ic->ic_node_alloc = rtw_node_alloc; 3775 3776 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3777 ic->ic_crypto.cs_key_set = rtw_key_set; 3778 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3779 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3780 } 3781 3782 static inline void 3783 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 3784 void *arg) 3785 { 3786 /* 3787 * Make sure the interface is shutdown during reboot. 3788 */ 3789 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 3790 if (hooks->rh_shutdown == NULL) 3791 printf("%s: WARNING: unable to establish shutdown hook\n", 3792 dvname); 3793 3794 /* 3795 * Add a suspend hook to make sure we come back up after a 3796 * resume. 3797 */ 3798 hooks->rh_power = powerhook_establish(dvname, rtw_power, arg); 3799 if (hooks->rh_power == NULL) 3800 printf("%s: WARNING: unable to establish power hook\n", 3801 dvname); 3802 } 3803 3804 static inline void 3805 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 3806 void *arg) 3807 { 3808 if (hooks->rh_shutdown != NULL) 3809 shutdownhook_disestablish(hooks->rh_shutdown); 3810 3811 if (hooks->rh_power != NULL) 3812 powerhook_disestablish(hooks->rh_power); 3813 } 3814 3815 static inline void 3816 rtw_init_radiotap(struct rtw_softc *sc) 3817 { 3818 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3819 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3820 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT); 3821 3822 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3823 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3824 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3825 } 3826 3827 static int 3828 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3829 { 3830 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3831 SIMPLEQ_INIT(&tsb->tsb_freeq); 3832 tsb->tsb_ndesc = qlen; 3833 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3834 M_NOWAIT); 3835 if (tsb->tsb_desc == NULL) 3836 return ENOMEM; 3837 return 0; 3838 } 3839 3840 static void 3841 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3842 { 3843 int pri; 3844 struct rtw_txsoft_blk *tsb; 3845 3846 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3847 tsb = &sc->sc_txsoft_blk[pri]; 3848 free(tsb->tsb_desc, M_DEVBUF); 3849 tsb->tsb_desc = NULL; 3850 } 3851 } 3852 3853 static int 3854 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3855 { 3856 int pri, rc = 0; 3857 int qlen[RTW_NTXPRI] = 3858 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3859 struct rtw_txsoft_blk *tsbs; 3860 3861 tsbs = sc->sc_txsoft_blk; 3862 3863 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3864 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3865 if (rc != 0) 3866 break; 3867 } 3868 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3869 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3870 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3871 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3872 return rc; 3873 } 3874 3875 static void 3876 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3877 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3878 { 3879 tdb->tdb_ndesc = ndesc; 3880 tdb->tdb_desc = desc; 3881 tdb->tdb_physbase = physbase; 3882 tdb->tdb_ofs = ofs; 3883 3884 (void)memset(tdb->tdb_desc, 0, 3885 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3886 3887 rtw_txdesc_blk_init(tdb); 3888 tdb->tdb_next = 0; 3889 } 3890 3891 static void 3892 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3893 { 3894 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3895 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3896 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3897 3898 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3899 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3900 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3901 3902 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3903 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3904 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3905 3906 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3907 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3908 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3909 } 3910 3911 static struct rtw_rf * 3912 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3913 { 3914 rtw_rf_write_t rf_write; 3915 struct rtw_rf *rf; 3916 3917 switch (rfchipid) { 3918 default: 3919 rf_write = rtw_rf_hostwrite; 3920 break; 3921 case RTW_RFCHIPID_INTERSIL: 3922 case RTW_RFCHIPID_PHILIPS: 3923 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3924 case RTW_RFCHIPID_RFMD: 3925 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3926 break; 3927 } 3928 3929 switch (rfchipid) { 3930 case RTW_RFCHIPID_GCT: 3931 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0); 3932 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3933 break; 3934 case RTW_RFCHIPID_MAXIM: 3935 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3936 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3937 break; 3938 case RTW_RFCHIPID_PHILIPS: 3939 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3940 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3941 break; 3942 case RTW_RFCHIPID_RFMD: 3943 /* XXX RFMD has no RF constructor */ 3944 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3945 /*FALLTHROUGH*/ 3946 default: 3947 return NULL; 3948 } 3949 rf->rf_continuous_tx_cb = 3950 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3951 rf->rf_continuous_tx_arg = (void *)sc; 3952 return rf; 3953 } 3954 3955 /* Revision C and later use a different PHY delay setting than 3956 * revisions A and B. 3957 */ 3958 static uint8_t 3959 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 3960 { 3961 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3962 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3963 3964 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); 3965 3966 RTW_WRITE(regs, RTW_RCR, REVAB); 3967 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3968 RTW_WRITE(regs, RTW_RCR, REVC); 3969 3970 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3971 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3972 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3973 3974 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 3975 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3976 3977 return phydelay; 3978 #undef REVC 3979 } 3980 3981 void 3982 rtw_attach(struct rtw_softc *sc) 3983 { 3984 struct ifnet *ifp = &sc->sc_if; 3985 struct ieee80211com *ic = &sc->sc_ic; 3986 struct rtw_txsoft_blk *tsb; 3987 int pri, rc; 3988 3989 rtw_cipher_wep = ieee80211_cipher_wep; 3990 rtw_cipher_wep.ic_decap = rtw_wep_decap; 3991 3992 NEXT_ATTACH_STATE(sc, DETACHED); 3993 3994 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3995 case RTW_TCR_HWVERID_F: 3996 sc->sc_hwverid = 'F'; 3997 break; 3998 case RTW_TCR_HWVERID_D: 3999 sc->sc_hwverid = 'D'; 4000 break; 4001 default: 4002 sc->sc_hwverid = '?'; 4003 break; 4004 } 4005 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, 4006 sc->sc_hwverid); 4007 4008 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 4009 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 4010 0); 4011 4012 if (rc != 0) { 4013 printf("%s: could not allocate hw descriptors, error %d\n", 4014 sc->sc_dev.dv_xname, rc); 4015 goto err; 4016 } 4017 4018 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 4019 4020 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 4021 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 4022 (void **)&sc->sc_descs, BUS_DMA_COHERENT); 4023 4024 if (rc != 0) { 4025 printf("%s: could not map hw descriptors, error %d\n", 4026 sc->sc_dev.dv_xname, rc); 4027 goto err; 4028 } 4029 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 4030 4031 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 4032 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 4033 4034 if (rc != 0) { 4035 printf("%s: could not create DMA map for hw descriptors, " 4036 "error %d\n", sc->sc_dev.dv_xname, rc); 4037 goto err; 4038 } 4039 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 4040 4041 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 4042 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 4043 4044 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4045 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 4046 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 4047 } 4048 4049 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 4050 sizeof(struct rtw_descs), NULL, 0); 4051 4052 if (rc != 0) { 4053 printf("%s: could not load DMA map for hw descriptors, " 4054 "error %d\n", sc->sc_dev.dv_xname, rc); 4055 goto err; 4056 } 4057 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 4058 4059 if (rtw_txsoft_blk_setup_all(sc) != 0) 4060 goto err; 4061 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 4062 4063 rtw_txdesc_blk_setup_all(sc); 4064 4065 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 4066 4067 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 4068 4069 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4070 tsb = &sc->sc_txsoft_blk[pri]; 4071 4072 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 4073 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 4074 printf("%s: could not load DMA map for " 4075 "hw tx descriptors, error %d\n", 4076 sc->sc_dev.dv_xname, rc); 4077 goto err; 4078 } 4079 } 4080 4081 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 4082 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 4083 RTW_RXQLEN)) != 0) { 4084 printf("%s: could not load DMA map for hw rx descriptors, " 4085 "error %d\n", sc->sc_dev.dv_xname, rc); 4086 goto err; 4087 } 4088 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 4089 4090 /* Reset the chip to a known state. */ 4091 if (rtw_reset(sc) != 0) 4092 goto err; 4093 NEXT_ATTACH_STATE(sc, FINISH_RESET); 4094 4095 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 4096 4097 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 4098 sc->sc_flags |= RTW_F_9356SROM; 4099 4100 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 4101 sc->sc_dev.dv_xname) != 0) 4102 goto err; 4103 4104 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 4105 4106 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 4107 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 4108 sc->sc_dev.dv_xname) != 0) { 4109 printf("%s: attach failed, malformed serial ROM\n", 4110 sc->sc_dev.dv_xname); 4111 goto err; 4112 } 4113 4114 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 4115 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 4116 4117 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 4118 4119 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 4120 4121 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 4122 sc->sc_flags & RTW_F_DIGPHY); 4123 4124 if (sc->sc_rf == NULL) { 4125 printf("%s: attach failed, could not attach RF\n", 4126 sc->sc_dev.dv_xname); 4127 goto err; 4128 } 4129 4130 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 4131 4132 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4133 4134 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4135 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 4136 4137 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4138 rtw_identify_country(&sc->sc_regs, &sc->sc_locale); 4139 4140 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 4141 sc->sc_dev.dv_xname); 4142 4143 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4144 sc->sc_dev.dv_xname) != 0) 4145 goto err; 4146 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4147 4148 rtw_setifprops(ifp, sc->sc_dev.dv_xname, (void*)sc); 4149 4150 IFQ_SET_READY(&ifp->if_snd); 4151 4152 sc->sc_ic.ic_ifp = ifp; 4153 rtw_set80211props(&sc->sc_ic); 4154 4155 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4156 4157 /* 4158 * Call MI attach routines. 4159 */ 4160 if_attach(ifp); 4161 ieee80211_ifattach(&sc->sc_ic); 4162 4163 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4164 4165 /* possibly we should fill in our own sc_send_prresp, since 4166 * the RTL8180 is probably sending probe responses in ad hoc 4167 * mode. 4168 */ 4169 4170 /* complete initialization */ 4171 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4172 callout_init(&sc->sc_scan_ch); 4173 4174 rtw_init_radiotap(sc); 4175 4176 #if NBPFILTER > 0 4177 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4178 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4179 #endif 4180 4181 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 4182 4183 NEXT_ATTACH_STATE(sc, FINISHED); 4184 4185 ieee80211_announce(ic); 4186 return; 4187 err: 4188 rtw_detach(sc); 4189 return; 4190 } 4191 4192 int 4193 rtw_detach(struct rtw_softc *sc) 4194 { 4195 struct ifnet *ifp = &sc->sc_if; 4196 int pri; 4197 4198 sc->sc_flags |= RTW_F_INVALID; 4199 4200 switch (sc->sc_attach_state) { 4201 case FINISHED: 4202 rtw_stop(ifp, 1); 4203 4204 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 4205 (void*)sc); 4206 callout_stop(&sc->sc_scan_ch); 4207 ieee80211_ifdetach(&sc->sc_ic); 4208 if_detach(ifp); 4209 break; 4210 case FINISH_ID_STA: 4211 case FINISH_RF_ATTACH: 4212 rtw_rf_destroy(sc->sc_rf); 4213 sc->sc_rf = NULL; 4214 /*FALLTHROUGH*/ 4215 case FINISH_PARSE_SROM: 4216 case FINISH_READ_SROM: 4217 rtw_srom_free(&sc->sc_srom); 4218 /*FALLTHROUGH*/ 4219 case FINISH_RESET: 4220 case FINISH_RXMAPS_CREATE: 4221 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4222 RTW_RXQLEN); 4223 /*FALLTHROUGH*/ 4224 case FINISH_TXMAPS_CREATE: 4225 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4226 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4227 sc->sc_txsoft_blk[pri].tsb_desc, 4228 sc->sc_txsoft_blk[pri].tsb_ndesc); 4229 } 4230 /*FALLTHROUGH*/ 4231 case FINISH_TXDESCBLK_SETUP: 4232 case FINISH_TXCTLBLK_SETUP: 4233 rtw_txsoft_blk_cleanup_all(sc); 4234 /*FALLTHROUGH*/ 4235 case FINISH_DESCMAP_LOAD: 4236 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4237 /*FALLTHROUGH*/ 4238 case FINISH_DESCMAP_CREATE: 4239 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4240 /*FALLTHROUGH*/ 4241 case FINISH_DESC_MAP: 4242 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 4243 sizeof(struct rtw_descs)); 4244 /*FALLTHROUGH*/ 4245 case FINISH_DESC_ALLOC: 4246 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4247 sc->sc_desc_nsegs); 4248 /*FALLTHROUGH*/ 4249 case DETACHED: 4250 NEXT_ATTACH_STATE(sc, DETACHED); 4251 break; 4252 } 4253 return 0; 4254 } 4255 4256 int 4257 rtw_activate(struct device *self, enum devact act) 4258 { 4259 struct rtw_softc *sc = (struct rtw_softc *)self; 4260 int rc = 0, s; 4261 4262 s = splnet(); 4263 switch (act) { 4264 case DVACT_ACTIVATE: 4265 rc = EOPNOTSUPP; 4266 break; 4267 4268 case DVACT_DEACTIVATE: 4269 if_deactivate(&sc->sc_if); 4270 break; 4271 } 4272 splx(s); 4273 return rc; 4274 } 4275
Indexes created Sun Sep 28 07:09:56 GMT 2025