rtw.c revision 1.9
1 /* $NetBSD: rtw.c,v 1.9 2004/12/20 01:28:24 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.9 2004/12/20 01:28:24 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #if 0 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #endif 54 #include <sys/time.h> 55 #include <sys/types.h> 56 57 #include <machine/endian.h> 58 #include <machine/bus.h> 59 #include <machine/intr.h> /* splnet */ 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_compat.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <dev/ic/rtwreg.h> 76 #include <dev/ic/rtwvar.h> 77 #include <dev/ic/rtwphyio.h> 78 #include <dev/ic/rtwphy.h> 79 80 #include <dev/ic/smc93cx6var.h> 81 82 #define KASSERT2(__cond, __msg) \ 83 do { \ 84 if (!(__cond)) \ 85 panic __msg ; \ 86 } while (0) 87 88 int rtw_rfprog_fallback = 0; 89 int rtw_host_rfio = 0; 90 int rtw_flush_rfio = 1; 91 int rtw_rfio_delay = 0; 92 93 #ifdef RTW_DEBUG 94 int rtw_debug = 2; 95 #endif /* RTW_DEBUG */ 96 97 #define NEXT_ATTACH_STATE(sc, state) do { \ 98 DPRINTF(sc, ("%s: attach state %s\n", __func__, #state)); \ 99 sc->sc_attach_state = state; \ 100 } while (0) 101 102 int rtw_dwelltime = 1000; /* milliseconds */ 103 104 static void rtw_start(struct ifnet *); 105 106 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 107 static int rtw_sysctl_verify_rfio_delay(SYSCTLFN_PROTO); 108 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 109 #ifdef RTW_DEBUG 110 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 111 #endif /* RTW_DEBUG */ 112 113 /* 114 * Setup sysctl(3) MIB, hw.rtw.* 115 * 116 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 117 */ 118 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 119 { 120 int rc; 121 struct sysctlnode *cnode, *rnode; 122 123 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 124 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 125 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 126 goto err; 127 128 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 129 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 130 "Realtek RTL818x 802.11 controls", 131 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 132 goto err; 133 134 #ifdef RTW_DEBUG 135 /* control debugging printfs */ 136 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 137 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 138 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 139 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 140 CTL_CREATE, CTL_EOL)) != 0) 141 goto err; 142 #endif /* RTW_DEBUG */ 143 /* set fallback RF programming method */ 144 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 145 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 146 "rfprog_fallback", 147 SYSCTL_DESCR("Set fallback RF programming method"), 148 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 149 CTL_CREATE, CTL_EOL)) != 0) 150 goto err; 151 152 /* force host to flush I/O by reading RTW_PHYADDR */ 153 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 154 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 155 "flush_rfio", SYSCTL_DESCR("Enable RF I/O flushing"), 156 rtw_sysctl_verify_rfio, 0, &rtw_flush_rfio, 0, 157 CTL_CREATE, CTL_EOL)) != 0) 158 goto err; 159 160 /* force host to control RF I/O bus */ 161 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 162 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 163 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 164 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 165 CTL_CREATE, CTL_EOL)) != 0) 166 goto err; 167 168 /* control RF I/O delay */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfio_delay", SYSCTL_DESCR("Set RF I/O delay"), 172 rtw_sysctl_verify_rfio_delay, 0, &rtw_rfio_delay, 0, 173 CTL_CREATE, CTL_EOL)) != 0) 174 goto err; 175 176 return; 177 err: 178 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 179 } 180 181 static int 182 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 183 { 184 int error, t; 185 struct sysctlnode node; 186 187 node = *rnode; 188 t = *(int*)rnode->sysctl_data; 189 node.sysctl_data = &t; 190 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 191 if (error || newp == NULL) 192 return (error); 193 194 if (t < lower || t > upper) 195 return (EINVAL); 196 197 *(int*)rnode->sysctl_data = t; 198 199 return (0); 200 } 201 202 static int 203 rtw_sysctl_verify_rfio_delay(SYSCTLFN_ARGS) 204 { 205 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1000000); 206 } 207 208 static int 209 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 210 { 211 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 212 MASK_AND_RSHIFT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 213 } 214 215 static int 216 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 217 { 218 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 1); 219 } 220 221 #ifdef RTW_DEBUG 222 static int 223 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 224 { 225 return rtw_sysctl_verify(SYSCTLFN_CALL(rnode), 0, 2); 226 } 227 228 static void 229 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 230 { 231 #define PRINTREG32(sc, reg) \ 232 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 233 dvname, reg, RTW_READ(regs, reg))) 234 235 #define PRINTREG16(sc, reg) \ 236 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %04x\n", \ 237 dvname, reg, RTW_READ16(regs, reg))) 238 239 #define PRINTREG8(sc, reg) \ 240 RTW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %02x\n", \ 241 dvname, reg, RTW_READ8(regs, reg))) 242 243 RTW_DPRINTF2(("%s: %s\n", dvname, where)); 244 245 PRINTREG32(regs, RTW_IDR0); 246 PRINTREG32(regs, RTW_IDR1); 247 PRINTREG32(regs, RTW_MAR0); 248 PRINTREG32(regs, RTW_MAR1); 249 PRINTREG32(regs, RTW_TSFTRL); 250 PRINTREG32(regs, RTW_TSFTRH); 251 PRINTREG32(regs, RTW_TLPDA); 252 PRINTREG32(regs, RTW_TNPDA); 253 PRINTREG32(regs, RTW_THPDA); 254 PRINTREG32(regs, RTW_TCR); 255 PRINTREG32(regs, RTW_RCR); 256 PRINTREG32(regs, RTW_TINT); 257 PRINTREG32(regs, RTW_TBDA); 258 PRINTREG32(regs, RTW_ANAPARM); 259 PRINTREG32(regs, RTW_BB); 260 PRINTREG32(regs, RTW_PHYCFG); 261 PRINTREG32(regs, RTW_WAKEUP0L); 262 PRINTREG32(regs, RTW_WAKEUP0H); 263 PRINTREG32(regs, RTW_WAKEUP1L); 264 PRINTREG32(regs, RTW_WAKEUP1H); 265 PRINTREG32(regs, RTW_WAKEUP2LL); 266 PRINTREG32(regs, RTW_WAKEUP2LH); 267 PRINTREG32(regs, RTW_WAKEUP2HL); 268 PRINTREG32(regs, RTW_WAKEUP2HH); 269 PRINTREG32(regs, RTW_WAKEUP3LL); 270 PRINTREG32(regs, RTW_WAKEUP3LH); 271 PRINTREG32(regs, RTW_WAKEUP3HL); 272 PRINTREG32(regs, RTW_WAKEUP3HH); 273 PRINTREG32(regs, RTW_WAKEUP4LL); 274 PRINTREG32(regs, RTW_WAKEUP4LH); 275 PRINTREG32(regs, RTW_WAKEUP4HL); 276 PRINTREG32(regs, RTW_WAKEUP4HH); 277 PRINTREG32(regs, RTW_DK0); 278 PRINTREG32(regs, RTW_DK1); 279 PRINTREG32(regs, RTW_DK2); 280 PRINTREG32(regs, RTW_DK3); 281 PRINTREG32(regs, RTW_RETRYCTR); 282 PRINTREG32(regs, RTW_RDSAR); 283 PRINTREG32(regs, RTW_FER); 284 PRINTREG32(regs, RTW_FEMR); 285 PRINTREG32(regs, RTW_FPSR); 286 PRINTREG32(regs, RTW_FFER); 287 288 /* 16-bit registers */ 289 PRINTREG16(regs, RTW_BRSR); 290 PRINTREG16(regs, RTW_IMR); 291 PRINTREG16(regs, RTW_ISR); 292 PRINTREG16(regs, RTW_BCNITV); 293 PRINTREG16(regs, RTW_ATIMWND); 294 PRINTREG16(regs, RTW_BINTRITV); 295 PRINTREG16(regs, RTW_ATIMTRITV); 296 PRINTREG16(regs, RTW_CRC16ERR); 297 PRINTREG16(regs, RTW_CRC0); 298 PRINTREG16(regs, RTW_CRC1); 299 PRINTREG16(regs, RTW_CRC2); 300 PRINTREG16(regs, RTW_CRC3); 301 PRINTREG16(regs, RTW_CRC4); 302 PRINTREG16(regs, RTW_CWR); 303 304 /* 8-bit registers */ 305 PRINTREG8(regs, RTW_CR); 306 PRINTREG8(regs, RTW_9346CR); 307 PRINTREG8(regs, RTW_CONFIG0); 308 PRINTREG8(regs, RTW_CONFIG1); 309 PRINTREG8(regs, RTW_CONFIG2); 310 PRINTREG8(regs, RTW_MSR); 311 PRINTREG8(regs, RTW_CONFIG3); 312 PRINTREG8(regs, RTW_CONFIG4); 313 PRINTREG8(regs, RTW_TESTR); 314 PRINTREG8(regs, RTW_PSR); 315 PRINTREG8(regs, RTW_SCR); 316 PRINTREG8(regs, RTW_PHYDELAY); 317 PRINTREG8(regs, RTW_CRCOUNT); 318 PRINTREG8(regs, RTW_PHYADDR); 319 PRINTREG8(regs, RTW_PHYDATAW); 320 PRINTREG8(regs, RTW_PHYDATAR); 321 PRINTREG8(regs, RTW_CONFIG5); 322 PRINTREG8(regs, RTW_TPPOLL); 323 324 PRINTREG16(regs, RTW_BSSID16); 325 PRINTREG32(regs, RTW_BSSID32); 326 #undef PRINTREG32 327 #undef PRINTREG16 328 #undef PRINTREG8 329 } 330 #endif /* RTW_DEBUG */ 331 332 void 333 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 334 { 335 struct rtw_regs *regs = &sc->sc_regs; 336 337 u_int32_t tcr; 338 tcr = RTW_READ(regs, RTW_TCR); 339 tcr &= ~RTW_TCR_LBK_MASK; 340 if (enable) 341 tcr |= RTW_TCR_LBK_CONT; 342 else 343 tcr |= RTW_TCR_LBK_NORMAL; 344 RTW_WRITE(regs, RTW_TCR, tcr); 345 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 346 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 347 rtw_txdac_enable(sc, !enable); 348 rtw_set_access(sc, RTW_ACCESS_ANAPARM); /* XXX Voodoo from Linux. */ 349 rtw_set_access(sc, RTW_ACCESS_NONE); 350 } 351 352 static const char * 353 rtw_access_string(enum rtw_access access) 354 { 355 switch (access) { 356 case RTW_ACCESS_NONE: 357 return "none"; 358 case RTW_ACCESS_CONFIG: 359 return "config"; 360 case RTW_ACCESS_ANAPARM: 361 return "anaparm"; 362 default: 363 return "unknown"; 364 } 365 } 366 367 static void 368 rtw_set_access1(struct rtw_regs *regs, 369 enum rtw_access oaccess, enum rtw_access naccess) 370 { 371 KASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM); 372 KASSERT(oaccess >= RTW_ACCESS_NONE && oaccess <= RTW_ACCESS_ANAPARM); 373 374 if (naccess == oaccess) 375 return; 376 377 switch (naccess) { 378 case RTW_ACCESS_NONE: 379 switch (oaccess) { 380 case RTW_ACCESS_ANAPARM: 381 rtw_anaparm_enable(regs, 0); 382 /*FALLTHROUGH*/ 383 case RTW_ACCESS_CONFIG: 384 rtw_config0123_enable(regs, 0); 385 /*FALLTHROUGH*/ 386 case RTW_ACCESS_NONE: 387 break; 388 } 389 break; 390 case RTW_ACCESS_CONFIG: 391 switch (oaccess) { 392 case RTW_ACCESS_NONE: 393 rtw_config0123_enable(regs, 1); 394 /*FALLTHROUGH*/ 395 case RTW_ACCESS_CONFIG: 396 break; 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 break; 400 } 401 break; 402 case RTW_ACCESS_ANAPARM: 403 switch (oaccess) { 404 case RTW_ACCESS_NONE: 405 rtw_config0123_enable(regs, 1); 406 /*FALLTHROUGH*/ 407 case RTW_ACCESS_CONFIG: 408 rtw_anaparm_enable(regs, 1); 409 /*FALLTHROUGH*/ 410 case RTW_ACCESS_ANAPARM: 411 break; 412 } 413 break; 414 } 415 } 416 417 void 418 rtw_set_access(struct rtw_softc *sc, enum rtw_access access) 419 { 420 rtw_set_access1(&sc->sc_regs, sc->sc_access, access); 421 RTW_DPRINTF(("%s: access %s -> %s\n", sc->sc_dev.dv_xname, 422 rtw_access_string(sc->sc_access), 423 rtw_access_string(access))); 424 sc->sc_access = access; 425 } 426 427 /* 428 * Enable registers, switch register banks. 429 */ 430 void 431 rtw_config0123_enable(struct rtw_regs *regs, int enable) 432 { 433 u_int8_t ecr; 434 ecr = RTW_READ8(regs, RTW_9346CR); 435 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 436 if (enable) 437 ecr |= RTW_9346CR_EEM_CONFIG; 438 else { 439 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 440 ecr |= RTW_9346CR_EEM_NORMAL; 441 } 442 RTW_WRITE8(regs, RTW_9346CR, ecr); 443 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 444 } 445 446 /* requires rtw_config0123_enable(, 1) */ 447 void 448 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 449 { 450 u_int8_t cfg3; 451 452 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 453 cfg3 |= RTW_CONFIG3_CLKRUNEN; 454 if (enable) 455 cfg3 |= RTW_CONFIG3_PARMEN; 456 else 457 cfg3 &= ~RTW_CONFIG3_PARMEN; 458 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 459 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 460 } 461 462 /* requires rtw_anaparm_enable(, 1) */ 463 void 464 rtw_txdac_enable(struct rtw_softc *sc, int enable) 465 { 466 u_int32_t anaparm; 467 struct rtw_regs *regs = &sc->sc_regs; 468 469 anaparm = RTW_READ(regs, RTW_ANAPARM); 470 if (enable) 471 anaparm &= ~RTW_ANAPARM_TXDACOFF; 472 else 473 anaparm |= RTW_ANAPARM_TXDACOFF; 474 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 475 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 476 } 477 478 static __inline int 479 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 480 { 481 u_int8_t cr; 482 int i; 483 484 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 485 486 RTW_WBR(regs, RTW_CR, RTW_CR); 487 488 for (i = 0; i < 10000; i++) { 489 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 490 RTW_DPRINTF(("%s: reset in %dus\n", dvname, i)); 491 return 0; 492 } 493 RTW_RBR(regs, RTW_CR, RTW_CR); 494 DELAY(1); /* 1us */ 495 } 496 497 printf("%s: reset failed\n", dvname); 498 return ETIMEDOUT; 499 } 500 501 static __inline int 502 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 503 { 504 uint32_t tcr; 505 506 /* from Linux driver */ 507 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 508 LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 509 510 RTW_WRITE(regs, RTW_TCR, tcr); 511 512 RTW_WBW(regs, RTW_CR, RTW_TCR); 513 514 return rtw_chip_reset1(regs, dvname); 515 } 516 517 static __inline int 518 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 519 { 520 int i; 521 u_int8_t ecr; 522 523 ecr = RTW_READ8(regs, RTW_9346CR); 524 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 525 RTW_WRITE8(regs, RTW_9346CR, ecr); 526 527 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 528 529 /* wait 2.5ms for completion */ 530 for (i = 0; i < 25; i++) { 531 ecr = RTW_READ8(regs, RTW_9346CR); 532 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 533 RTW_DPRINTF(("%s: recall EEPROM in %dus\n", dvname, 534 i * 100)); 535 return 0; 536 } 537 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 538 DELAY(100); 539 } 540 printf("%s: recall EEPROM failed\n", dvname); 541 return ETIMEDOUT; 542 } 543 544 static __inline int 545 rtw_reset(struct rtw_softc *sc) 546 { 547 int rc; 548 uint8_t config1; 549 550 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 551 return rc; 552 553 if ((rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 554 ; 555 556 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 557 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 558 /* TBD turn off maximum power saving? */ 559 560 return 0; 561 } 562 563 static __inline int 564 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txctl *descs, 565 u_int ndescs) 566 { 567 int i, rc = 0; 568 for (i = 0; i < ndescs; i++) { 569 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 570 0, 0, &descs[i].stx_dmamap); 571 if (rc != 0) 572 break; 573 } 574 return rc; 575 } 576 577 static __inline int 578 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 579 u_int ndescs) 580 { 581 int i, rc = 0; 582 for (i = 0; i < ndescs; i++) { 583 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 584 &descs[i].srx_dmamap); 585 if (rc != 0) 586 break; 587 } 588 return rc; 589 } 590 591 static __inline void 592 rtw_rxctls_setup(struct rtw_rxctl *descs) 593 { 594 int i; 595 for (i = 0; i < RTW_RXQLEN; i++) 596 descs[i].srx_mbuf = NULL; 597 } 598 599 static __inline void 600 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxctl *descs, 601 u_int ndescs) 602 { 603 int i; 604 for (i = 0; i < ndescs; i++) { 605 if (descs[i].srx_dmamap != NULL) 606 bus_dmamap_destroy(dmat, descs[i].srx_dmamap); 607 } 608 } 609 610 static __inline void 611 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txctl *descs, 612 u_int ndescs) 613 { 614 int i; 615 for (i = 0; i < ndescs; i++) { 616 if (descs[i].stx_dmamap != NULL) 617 bus_dmamap_destroy(dmat, descs[i].stx_dmamap); 618 } 619 } 620 621 static __inline void 622 rtw_srom_free(struct rtw_srom *sr) 623 { 624 sr->sr_size = 0; 625 if (sr->sr_content == NULL) 626 return; 627 free(sr->sr_content, M_DEVBUF); 628 sr->sr_content = NULL; 629 } 630 631 static void 632 rtw_srom_defaults(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 633 enum rtw_rfchipid *rfchipid, u_int32_t *rcr) 634 { 635 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 636 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 637 *rcr |= RTW_RCR_ENCS1; 638 *rfchipid = RTW_RFCHIPID_PHILIPS; 639 } 640 641 static int 642 rtw_srom_parse(struct rtw_srom *sr, u_int32_t *flags, u_int8_t *cs_threshold, 643 enum rtw_rfchipid *rfchipid, u_int32_t *rcr, enum rtw_locale *locale, 644 const char *dvname) 645 { 646 int i; 647 const char *rfname, *paname; 648 char scratch[sizeof("unknown 0xXX")]; 649 u_int16_t version; 650 u_int8_t mac[IEEE80211_ADDR_LEN]; 651 652 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 653 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 654 655 version = RTW_SR_GET16(sr, RTW_SR_VERSION); 656 printf("%s: SROM version %d.%d", dvname, version >> 8, version & 0xff); 657 658 if (version <= 0x0101) { 659 printf(" is not understood, limping along with defaults\n"); 660 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 661 return 0; 662 } 663 printf("\n"); 664 665 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 666 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 667 668 RTW_DPRINTF(("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 669 670 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 671 672 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 673 *flags |= RTW_F_ANTDIV; 674 675 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) != 0) 676 *flags |= RTW_F_DIGPHY; 677 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 678 *flags |= RTW_F_DFLANTB; 679 680 *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM), 681 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 682 683 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 684 switch (*rfchipid) { 685 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 686 rfname = "GCT GRF5101"; 687 paname = "Winspring WS9901"; 688 break; 689 case RTW_RFCHIPID_MAXIM: 690 rfname = "Maxim MAX2820"; /* guess */ 691 paname = "Maxim MAX2422"; /* guess */ 692 break; 693 case RTW_RFCHIPID_INTERSIL: 694 rfname = "Intersil HFA3873"; /* guess */ 695 paname = "Intersil <unknown>"; 696 break; 697 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 698 rfname = "Philips SA2400A"; 699 paname = "Philips SA2411"; 700 break; 701 case RTW_RFCHIPID_RFMD: 702 /* this is the same front-end as an atw(4)! */ 703 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 704 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 705 "SYN: Silicon Labs Si4126"; /* inferred from 706 * reference driver 707 */ 708 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 709 break; 710 case RTW_RFCHIPID_RESERVED: 711 rfname = paname = "reserved"; 712 break; 713 default: 714 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 715 rfname = paname = scratch; 716 } 717 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 718 719 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 720 case RTW_CONFIG0_GL_USA: 721 *locale = RTW_LOCALE_USA; 722 break; 723 case RTW_CONFIG0_GL_EUROPE: 724 *locale = RTW_LOCALE_EUROPE; 725 break; 726 case RTW_CONFIG0_GL_JAPAN: 727 *locale = RTW_LOCALE_JAPAN; 728 break; 729 default: 730 *locale = RTW_LOCALE_UNKNOWN; 731 break; 732 } 733 return 0; 734 } 735 736 /* Returns -1 on failure. */ 737 static int 738 rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr, 739 const char *dvname) 740 { 741 int rc; 742 struct seeprom_descriptor sd; 743 u_int8_t ecr; 744 745 (void)memset(&sd, 0, sizeof(sd)); 746 747 ecr = RTW_READ8(regs, RTW_9346CR); 748 749 if ((flags & RTW_F_9356SROM) != 0) { 750 RTW_DPRINTF(("%s: 93c56 SROM\n", dvname)); 751 sr->sr_size = 256; 752 sd.sd_chip = C56_66; 753 } else { 754 RTW_DPRINTF(("%s: 93c46 SROM\n", dvname)); 755 sr->sr_size = 128; 756 sd.sd_chip = C46; 757 } 758 759 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 760 RTW_9346CR_EEM_MASK); 761 ecr |= RTW_9346CR_EEM_PROGRAM; 762 763 RTW_WRITE8(regs, RTW_9346CR, ecr); 764 765 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 766 767 if (sr->sr_content == NULL) { 768 printf("%s: unable to allocate SROM buffer\n", dvname); 769 return ENOMEM; 770 } 771 772 (void)memset(sr->sr_content, 0, sr->sr_size); 773 774 /* RTL8180 has a single 8-bit register for controlling the 775 * 93cx6 SROM. There is no "ready" bit. The RTL8180 776 * input/output sense is the reverse of read_seeprom's. 777 */ 778 sd.sd_tag = regs->r_bt; 779 sd.sd_bsh = regs->r_bh; 780 sd.sd_regsize = 1; 781 sd.sd_control_offset = RTW_9346CR; 782 sd.sd_status_offset = RTW_9346CR; 783 sd.sd_dataout_offset = RTW_9346CR; 784 sd.sd_CK = RTW_9346CR_EESK; 785 sd.sd_CS = RTW_9346CR_EECS; 786 sd.sd_DI = RTW_9346CR_EEDO; 787 sd.sd_DO = RTW_9346CR_EEDI; 788 /* make read_seeprom enter EEPROM read/write mode */ 789 sd.sd_MS = ecr; 790 sd.sd_RDY = 0; 791 #if 0 792 sd.sd_clkdelay = 50; 793 #endif 794 795 /* TBD bus barriers */ 796 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 797 printf("%s: could not read SROM\n", dvname); 798 free(sr->sr_content, M_DEVBUF); 799 sr->sr_content = NULL; 800 return -1; /* XXX */ 801 } 802 803 /* end EEPROM read/write mode */ 804 RTW_WRITE8(regs, RTW_9346CR, 805 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 806 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 807 808 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 809 return rc; 810 811 #ifdef RTW_DEBUG 812 { 813 int i; 814 RTW_DPRINTF(("\n%s: serial ROM:\n\t", dvname)); 815 for (i = 0; i < sr->sr_size/2; i++) { 816 if (((i % 8) == 0) && (i != 0)) 817 RTW_DPRINTF(("\n\t")); 818 RTW_DPRINTF((" %04x", sr->sr_content[i])); 819 } 820 RTW_DPRINTF(("\n")); 821 } 822 #endif /* RTW_DEBUG */ 823 return 0; 824 } 825 826 static void 827 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 828 const char *dvname) 829 { 830 u_int8_t cfg4; 831 const char *method; 832 833 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 834 835 switch (rfchipid) { 836 default: 837 cfg4 |= LSHIFT(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 838 method = "fallback"; 839 break; 840 case RTW_RFCHIPID_INTERSIL: 841 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 842 method = "Intersil"; 843 break; 844 case RTW_RFCHIPID_PHILIPS: 845 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 846 method = "Philips"; 847 break; 848 case RTW_RFCHIPID_RFMD: 849 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 850 method = "RFMD"; 851 break; 852 } 853 854 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 855 856 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 857 858 printf("%s: %s RF programming method, %#02x\n", dvname, method, 859 RTW_READ8(regs, RTW_CONFIG4)); 860 } 861 862 #if 0 863 static __inline int 864 rtw_identify_rf(struct rtw_regs *regs, enum rtw_rftype *rftype, 865 const char *dvname) 866 { 867 u_int8_t cfg4; 868 const char *name; 869 870 cfg4 = RTW_READ8(regs, RTW_CONFIG4); 871 872 switch (cfg4 & RTW_CONFIG4_RFTYPE_MASK) { 873 case RTW_CONFIG4_RFTYPE_PHILIPS: 874 *rftype = RTW_RFTYPE_PHILIPS; 875 name = "Philips"; 876 break; 877 case RTW_CONFIG4_RFTYPE_INTERSIL: 878 *rftype = RTW_RFTYPE_INTERSIL; 879 name = "Intersil"; 880 break; 881 case RTW_CONFIG4_RFTYPE_RFMD: 882 *rftype = RTW_RFTYPE_RFMD; 883 name = "RFMD"; 884 break; 885 default: 886 name = "<unknown>"; 887 return ENXIO; 888 } 889 890 printf("%s: RF prog type %s\n", dvname, name); 891 return 0; 892 } 893 #endif 894 895 static __inline void 896 rtw_init_channels(enum rtw_locale locale, 897 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 898 const char *dvname) 899 { 900 int i; 901 const char *name = NULL; 902 #define ADD_CHANNEL(_chans, _chan) do { \ 903 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 904 (*_chans)[_chan].ic_freq = \ 905 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 906 } while (0) 907 908 switch (locale) { 909 case RTW_LOCALE_USA: /* 1-11 */ 910 name = "USA"; 911 for (i = 1; i <= 11; i++) 912 ADD_CHANNEL(chans, i); 913 break; 914 case RTW_LOCALE_JAPAN: /* 1-14 */ 915 name = "Japan"; 916 ADD_CHANNEL(chans, 14); 917 for (i = 1; i <= 14; i++) 918 ADD_CHANNEL(chans, i); 919 break; 920 case RTW_LOCALE_EUROPE: /* 1-13 */ 921 name = "Europe"; 922 for (i = 1; i <= 13; i++) 923 ADD_CHANNEL(chans, i); 924 break; 925 default: /* 10-11 allowed by most countries */ 926 name = "<unknown>"; 927 for (i = 10; i <= 11; i++) 928 ADD_CHANNEL(chans, i); 929 break; 930 } 931 printf("%s: Geographic Location %s\n", dvname, name); 932 #undef ADD_CHANNEL 933 } 934 935 static __inline void 936 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, 937 const char *dvname) 938 { 939 u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 940 941 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 942 case RTW_CONFIG0_GL_USA: 943 *locale = RTW_LOCALE_USA; 944 break; 945 case RTW_CONFIG0_GL_JAPAN: 946 *locale = RTW_LOCALE_JAPAN; 947 break; 948 case RTW_CONFIG0_GL_EUROPE: 949 *locale = RTW_LOCALE_EUROPE; 950 break; 951 default: 952 *locale = RTW_LOCALE_UNKNOWN; 953 break; 954 } 955 } 956 957 static __inline int 958 rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN], 959 const char *dvname) 960 { 961 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 962 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 963 }; 964 u_int32_t idr0 = RTW_READ(regs, RTW_IDR0), 965 idr1 = RTW_READ(regs, RTW_IDR1); 966 967 (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7)); 968 (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15)); 969 (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23)); 970 (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31)); 971 972 (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7)); 973 (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15)); 974 975 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 976 printf("%s: could not get mac address, attach failed\n", 977 dvname); 978 return ENXIO; 979 } 980 981 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 982 983 return 0; 984 } 985 986 static u_int8_t 987 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 988 struct ieee80211_channel *chan) 989 { 990 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 991 KASSERT2(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14, 992 ("%s: channel %d out of range", __func__, 993 idx - RTW_SR_TXPOWER1 + 1)); 994 return RTW_SR_GET(sr, idx); 995 } 996 997 static void 998 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *htcs) 999 { 1000 int pri; 1001 u_int ndesc[RTW_NTXPRI] = 1002 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, RTW_NTXDESCBCN}; 1003 1004 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1005 htcs[pri].htc_nfree = ndesc[pri]; 1006 htcs[pri].htc_next = 0; 1007 } 1008 } 1009 1010 static int 1011 rtw_txctl_blk_init(struct rtw_txctl_blk *stc) 1012 { 1013 int i; 1014 struct rtw_txctl *stx; 1015 1016 SIMPLEQ_INIT(&stc->stc_dirtyq); 1017 SIMPLEQ_INIT(&stc->stc_freeq); 1018 for (i = 0; i < stc->stc_ndesc; i++) { 1019 stx = &stc->stc_desc[i]; 1020 stx->stx_mbuf = NULL; 1021 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1022 } 1023 return 0; 1024 } 1025 1026 static void 1027 rtw_txctl_blk_init_all(struct rtw_txctl_blk *stcs) 1028 { 1029 int pri; 1030 for (pri = 0; pri < RTW_NTXPRI; pri++) 1031 rtw_txctl_blk_init(&stcs[pri]); 1032 } 1033 1034 static __inline void 1035 rtw_rxdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, u_int desc0, u_int 1036 nsync, int ops) 1037 { 1038 /* sync to end of ring */ 1039 if (desc0 + nsync > RTW_NRXDESC) { 1040 bus_dmamap_sync(dmat, dmap, 1041 offsetof(struct rtw_descs, hd_rx[desc0]), 1042 sizeof(struct rtw_rxdesc) * (RTW_NRXDESC - desc0), ops); 1043 nsync -= (RTW_NRXDESC - desc0); 1044 desc0 = 0; 1045 } 1046 1047 /* sync what remains */ 1048 bus_dmamap_sync(dmat, dmap, 1049 offsetof(struct rtw_descs, hd_rx[desc0]), 1050 sizeof(struct rtw_rxdesc) * nsync, ops); 1051 } 1052 1053 static void 1054 rtw_txdescs_sync(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1055 struct rtw_txdesc_blk *htc, u_int desc0, u_int nsync, int ops) 1056 { 1057 /* sync to end of ring */ 1058 if (desc0 + nsync > htc->htc_ndesc) { 1059 bus_dmamap_sync(dmat, dmap, 1060 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1061 sizeof(struct rtw_txdesc) * (htc->htc_ndesc - desc0), 1062 ops); 1063 nsync -= (htc->htc_ndesc - desc0); 1064 desc0 = 0; 1065 } 1066 1067 /* sync what remains */ 1068 bus_dmamap_sync(dmat, dmap, 1069 htc->htc_ofs + sizeof(struct rtw_txdesc) * desc0, 1070 sizeof(struct rtw_txdesc) * nsync, ops); 1071 } 1072 1073 static void 1074 rtw_txdescs_sync_all(bus_dma_tag_t dmat, bus_dmamap_t dmap, 1075 struct rtw_txdesc_blk *htcs) 1076 { 1077 int pri; 1078 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1079 rtw_txdescs_sync(dmat, dmap, 1080 &htcs[pri], 0, htcs[pri].htc_ndesc, 1081 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1082 } 1083 } 1084 1085 static void 1086 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxctl *desc) 1087 { 1088 int i; 1089 struct rtw_rxctl *srx; 1090 1091 for (i = 0; i < RTW_NRXDESC; i++) { 1092 srx = &desc[i]; 1093 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, 1094 srx->srx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1095 bus_dmamap_unload(dmat, srx->srx_dmamap); 1096 m_freem(srx->srx_mbuf); 1097 srx->srx_mbuf = NULL; 1098 } 1099 } 1100 1101 static __inline int 1102 rtw_rxbuf_alloc(bus_dma_tag_t dmat, struct rtw_rxctl *srx) 1103 { 1104 int rc; 1105 struct mbuf *m; 1106 1107 MGETHDR(m, M_DONTWAIT, MT_DATA); 1108 if (m == NULL) 1109 return ENOMEM; 1110 1111 MCLGET(m, M_DONTWAIT); 1112 if (m == NULL) 1113 return ENOMEM; 1114 1115 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1116 1117 rc = bus_dmamap_load_mbuf(dmat, srx->srx_dmamap, m, BUS_DMA_NOWAIT); 1118 if (rc != 0) 1119 return rc; 1120 1121 srx->srx_mbuf = m; 1122 1123 return 0; 1124 } 1125 1126 static int 1127 rtw_rxctl_init_all(bus_dma_tag_t dmat, struct rtw_rxctl *desc, 1128 u_int *next, const char *dvname) 1129 { 1130 int i, rc; 1131 struct rtw_rxctl *srx; 1132 1133 for (i = 0; i < RTW_NRXDESC; i++) { 1134 srx = &desc[i]; 1135 if ((rc = rtw_rxbuf_alloc(dmat, srx)) == 0) 1136 continue; 1137 printf("%s: failed rtw_rxbuf_alloc after %d buffers, rc = %d\n", 1138 dvname, i, rc); 1139 if (i == 0) { 1140 rtw_rxbufs_release(dmat, desc); 1141 return rc; 1142 } 1143 } 1144 *next = 0; 1145 return 0; 1146 } 1147 1148 static __inline void 1149 rtw_rxdesc_init(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1150 struct rtw_rxdesc *hrx, struct rtw_rxctl *srx, int idx) 1151 { 1152 int is_last = (idx == RTW_NRXDESC - 1); 1153 uint32_t ctl; 1154 1155 hrx->hrx_buf = htole32(srx->srx_dmamap->dm_segs[0].ds_addr); 1156 1157 ctl = LSHIFT(srx->srx_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1158 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1159 1160 if (is_last) 1161 ctl |= RTW_RXCTL_EOR; 1162 1163 hrx->hrx_ctl = htole32(ctl); 1164 1165 /* sync the mbuf */ 1166 bus_dmamap_sync(dmat, srx->srx_dmamap, 0, srx->srx_dmamap->dm_mapsize, 1167 BUS_DMASYNC_PREREAD); 1168 1169 /* sync the descriptor */ 1170 bus_dmamap_sync(dmat, dmam, RTW_DESC_OFFSET(hd_rx, idx), 1171 sizeof(struct rtw_rxdesc), 1172 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1173 } 1174 1175 static void 1176 rtw_rxdesc_init_all(bus_dma_tag_t dmat, bus_dmamap_t dmam, 1177 struct rtw_rxdesc *desc, struct rtw_rxctl *ctl) 1178 { 1179 int i; 1180 struct rtw_rxdesc *hrx; 1181 struct rtw_rxctl *srx; 1182 1183 for (i = 0; i < RTW_NRXDESC; i++) { 1184 hrx = &desc[i]; 1185 srx = &ctl[i]; 1186 rtw_rxdesc_init(dmat, dmam, hrx, srx, i); 1187 } 1188 } 1189 1190 static void 1191 rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable) 1192 { 1193 u_int8_t cr; 1194 1195 RTW_DPRINTF(("%s: %s 0x%02x\n", __func__, 1196 enable ? "enable" : "disable", flags)); 1197 1198 cr = RTW_READ8(regs, RTW_CR); 1199 1200 /* XXX reference source does not enable MULRW */ 1201 #if 0 1202 /* enable PCI Read/Write Multiple */ 1203 cr |= RTW_CR_MULRW; 1204 #endif 1205 1206 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1207 if (enable) 1208 cr |= flags; 1209 else 1210 cr &= ~flags; 1211 RTW_WRITE8(regs, RTW_CR, cr); 1212 RTW_SYNC(regs, RTW_CR, RTW_CR); 1213 } 1214 1215 static void 1216 rtw_intr_rx(struct rtw_softc *sc, u_int16_t isr) 1217 { 1218 u_int next; 1219 int rate, rssi; 1220 u_int32_t hrssi, hstat, htsfth, htsftl; 1221 struct rtw_rxdesc *hrx; 1222 struct rtw_rxctl *srx; 1223 struct mbuf *m; 1224 1225 struct ieee80211_node *ni; 1226 struct ieee80211_frame *wh; 1227 1228 for (next = sc->sc_rxnext; ; next = (next + 1) % RTW_RXQLEN) { 1229 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1230 next, 1, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1231 hrx = &sc->sc_rxdesc[next]; 1232 srx = &sc->sc_rxctl[next]; 1233 1234 hstat = le32toh(hrx->hrx_stat); 1235 hrssi = le32toh(hrx->hrx_rssi); 1236 htsfth = le32toh(hrx->hrx_tsfth); 1237 htsftl = le32toh(hrx->hrx_tsftl); 1238 1239 RTW_DPRINTF2(("%s: rxdesc[%d] hstat %#08x hrssi %#08x " 1240 "htsft %#08x%08x\n", __func__, next, 1241 hstat, hrssi, htsfth, htsftl)); 1242 1243 if ((hstat & RTW_RXSTAT_OWN) != 0) /* belongs to NIC */ 1244 break; 1245 1246 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1247 printf("%s: DMA error/FIFO overflow %08x, " 1248 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1249 hstat & RTW_RXSTAT_IOERROR, next); 1250 goto next; 1251 } 1252 1253 switch (hstat & RTW_RXSTAT_RATE_MASK) { 1254 case RTW_RXSTAT_RATE_1MBPS: 1255 rate = 10; 1256 break; 1257 case RTW_RXSTAT_RATE_2MBPS: 1258 rate = 20; 1259 break; 1260 case RTW_RXSTAT_RATE_5MBPS: 1261 rate = 55; 1262 break; 1263 default: 1264 #ifdef RTW_DEBUG 1265 if (rtw_debug > 1) 1266 printf("%s: interpreting rate #%d as 11 MB/s\n", 1267 sc->sc_dev.dv_xname, 1268 MASK_AND_RSHIFT(hstat, 1269 RTW_RXSTAT_RATE_MASK)); 1270 #endif /* RTW_DEBUG */ 1271 /*FALLTHROUGH*/ 1272 case RTW_RXSTAT_RATE_11MBPS: 1273 rate = 110; 1274 break; 1275 } 1276 1277 RTW_DPRINTF2(("%s: rate %d\n", __func__, rate)); 1278 1279 #ifdef RTW_DEBUG 1280 #define PRINTSTAT(flag) do { \ 1281 if ((hstat & flag) != 0) { \ 1282 printf("%s" #flag, delim); \ 1283 delim = ","; \ 1284 } \ 1285 } while (0) 1286 if (rtw_debug > 1) { 1287 const char *delim = "<"; 1288 printf("%s: ", sc->sc_dev.dv_xname); 1289 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1290 printf("status %08x<", hstat); 1291 PRINTSTAT(RTW_RXSTAT_SPLCP); 1292 PRINTSTAT(RTW_RXSTAT_MAR); 1293 PRINTSTAT(RTW_RXSTAT_PAR); 1294 PRINTSTAT(RTW_RXSTAT_BAR); 1295 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1296 PRINTSTAT(RTW_RXSTAT_CRC32); 1297 PRINTSTAT(RTW_RXSTAT_ICV); 1298 printf(">, "); 1299 } 1300 printf("rate %d.%d Mb/s, time %08x%08x\n", 1301 rate / 10, rate % 10, htsfth, htsftl); 1302 } 1303 #endif /* RTW_DEBUG */ 1304 1305 if ((hstat & RTW_RXSTAT_RES) != 0 && 1306 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 1307 goto next; 1308 1309 /* if bad flags, skip descriptor */ 1310 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1311 printf("%s: too many rx segments\n", 1312 sc->sc_dev.dv_xname); 1313 goto next; 1314 } 1315 1316 m = srx->srx_mbuf; 1317 1318 /* if temporarily out of memory, re-use mbuf */ 1319 if (rtw_rxbuf_alloc(sc->sc_dmat, srx) != 0) { 1320 printf("%s: rtw_rxbuf_alloc(, %d) failed, " 1321 "dropping this packet\n", sc->sc_dev.dv_xname, 1322 next); 1323 goto next; 1324 } 1325 1326 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1327 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_RSSI); 1328 else { 1329 rssi = MASK_AND_RSHIFT(hrssi, RTW_RXRSSI_IMR_RSSI); 1330 /* TBD find out each front-end's LNA gain in the 1331 * front-end's units 1332 */ 1333 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1334 rssi |= 0x80; 1335 } 1336 1337 m->m_pkthdr.len = m->m_len = 1338 MASK_AND_RSHIFT(hstat, RTW_RXSTAT_LENGTH_MASK); 1339 m->m_flags |= M_HASFCS; 1340 1341 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 1342 sc->sc_ic.ic_stats.is_rx_tooshort++; 1343 goto next; 1344 } 1345 wh = mtod(m, struct ieee80211_frame *); 1346 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1347 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1348 1349 sc->sc_tsfth = htsfth; 1350 1351 ieee80211_input(&sc->sc_if, m, ni, rssi, htsftl); 1352 ieee80211_release_node(&sc->sc_ic, ni); 1353 next: 1354 rtw_rxdesc_init(sc->sc_dmat, sc->sc_desc_dmamap, 1355 hrx, srx, next); 1356 } 1357 sc->sc_rxnext = next; 1358 1359 return; 1360 } 1361 1362 static void 1363 rtw_txbuf_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1364 struct rtw_txctl *stx) 1365 { 1366 struct mbuf *m; 1367 struct ieee80211_node *ni; 1368 bus_dmamap_t dmamap; 1369 1370 dmamap = stx->stx_dmamap; 1371 m = stx->stx_mbuf; 1372 ni = stx->stx_ni; 1373 stx->stx_dmamap = NULL; 1374 stx->stx_mbuf = NULL; 1375 stx->stx_ni = NULL; 1376 1377 bus_dmamap_sync(dmat, dmamap, 0, dmamap->dm_mapsize, 1378 BUS_DMASYNC_POSTWRITE); 1379 bus_dmamap_unload(dmat, dmamap); 1380 m_freem(m); 1381 ieee80211_release_node(ic, ni); 1382 } 1383 1384 static void 1385 rtw_txbufs_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1386 struct rtw_txctl_blk *stc) 1387 { 1388 struct rtw_txctl *stx; 1389 1390 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1391 rtw_txbuf_release(dmat, ic, stx); 1392 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1393 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1394 } 1395 } 1396 1397 static __inline void 1398 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *htc, 1399 struct rtw_txctl *stx, int ndesc) 1400 { 1401 int data_retry, rts_retry; 1402 struct rtw_txdesc *htx0, *htxn; 1403 const char *condstring; 1404 1405 rtw_txbuf_release(sc->sc_dmat, &sc->sc_ic, stx); 1406 1407 htc->htc_nfree += ndesc; 1408 1409 htx0 = &htc->htc_desc[stx->stx_first]; 1410 htxn = &htc->htc_desc[stx->stx_last]; 1411 1412 rts_retry = MASK_AND_RSHIFT(le32toh(htx0->htx_stat), 1413 RTW_TXSTAT_RTSRETRY_MASK); 1414 data_retry = MASK_AND_RSHIFT(le32toh(htx0->htx_stat), 1415 RTW_TXSTAT_DRC_MASK); 1416 1417 sc->sc_if.if_collisions += rts_retry + data_retry; 1418 1419 if ((htx0->htx_stat & htole32(RTW_TXSTAT_TOK)) != 0) 1420 condstring = "ok"; 1421 else { 1422 sc->sc_if.if_oerrors++; 1423 condstring = "error"; 1424 } 1425 1426 DPRINTF2(sc, ("%s: stx %p txdesc[%d, %d] %s tries rts %u data %u\n", 1427 sc->sc_dev.dv_xname, stx, stx->stx_first, stx->stx_last, 1428 condstring, rts_retry, data_retry)); 1429 } 1430 1431 /* Collect transmitted packets. */ 1432 static __inline void 1433 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txctl_blk *stc, 1434 struct rtw_txdesc_blk *htc) 1435 { 1436 int ndesc; 1437 struct rtw_txctl *stx; 1438 1439 while ((stx = SIMPLEQ_FIRST(&stc->stc_dirtyq)) != NULL) { 1440 ndesc = 1 + stx->stx_last - stx->stx_first; 1441 if (stx->stx_last < stx->stx_first) 1442 ndesc += htc->htc_ndesc; 1443 1444 KASSERT(ndesc > 0); 1445 1446 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, htc, 1447 stx->stx_first, ndesc, 1448 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1449 1450 if ((htc->htc_desc[stx->stx_first].htx_stat & 1451 htole32(RTW_TXSTAT_OWN)) != 0) 1452 break; 1453 1454 rtw_collect_txpkt(sc, htc, stx, ndesc); 1455 SIMPLEQ_REMOVE_HEAD(&stc->stc_dirtyq, stx_q); 1456 SIMPLEQ_INSERT_TAIL(&stc->stc_freeq, stx, stx_q); 1457 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1458 } 1459 if (stx == NULL) 1460 stc->stc_tx_timer = 0; 1461 } 1462 1463 static void 1464 rtw_intr_tx(struct rtw_softc *sc, u_int16_t isr) 1465 { 1466 int pri; 1467 struct rtw_txctl_blk *stc; 1468 struct rtw_txdesc_blk *htc; 1469 1470 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1471 stc = &sc->sc_txctl_blk[pri]; 1472 htc = &sc->sc_txdesc_blk[pri]; 1473 1474 rtw_collect_txring(sc, stc, htc); 1475 1476 rtw_start(&sc->sc_if); 1477 } 1478 1479 /* TBD */ 1480 return; 1481 } 1482 1483 static void 1484 rtw_intr_beacon(struct rtw_softc *sc, u_int16_t isr) 1485 { 1486 /* TBD */ 1487 return; 1488 } 1489 1490 static void 1491 rtw_intr_atim(struct rtw_softc *sc) 1492 { 1493 /* TBD */ 1494 return; 1495 } 1496 1497 static void 1498 rtw_hwring_setup(struct rtw_softc *sc) 1499 { 1500 struct rtw_regs *regs = &sc->sc_regs; 1501 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1502 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(sc, hd_txlo)); 1503 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(sc, hd_txmd)); 1504 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(sc, hd_txhi)); 1505 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(sc, hd_bcn)); 1506 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1507 } 1508 1509 static void 1510 rtw_swring_setup(struct rtw_softc *sc) 1511 { 1512 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1513 1514 rtw_txctl_blk_init_all(&sc->sc_txctl_blk[0]); 1515 1516 rtw_rxctl_init_all(sc->sc_dmat, sc->sc_rxctl, &sc->sc_rxnext, 1517 sc->sc_dev.dv_xname); 1518 rtw_rxdesc_init_all(sc->sc_dmat, sc->sc_desc_dmamap, 1519 sc->sc_rxdesc, sc->sc_rxctl); 1520 1521 rtw_txdescs_sync_all(sc->sc_dmat, sc->sc_desc_dmamap, 1522 &sc->sc_txdesc_blk[0]); 1523 #if 0 /* redundant with rtw_rxdesc_init_all */ 1524 rtw_rxdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 1525 0, RTW_NRXDESC, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1526 #endif 1527 } 1528 1529 static void 1530 rtw_kick(struct rtw_softc *sc) 1531 { 1532 int pri; 1533 struct rtw_regs *regs = &sc->sc_regs; 1534 1535 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 0); 1536 RTW_WRITE16(regs, RTW_IMR, 0); 1537 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1538 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1539 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1540 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1541 &sc->sc_txctl_blk[pri]); 1542 } 1543 rtw_swring_setup(sc); 1544 rtw_hwring_setup(sc); 1545 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1546 RTW_SYNC(regs, RTW_IMR, RTW_IMR); 1547 rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); 1548 } 1549 1550 static void 1551 rtw_intr_ioerror(struct rtw_softc *sc, u_int16_t isr) 1552 { 1553 if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) 1554 rtw_kick(sc); 1555 if ((isr & RTW_INTR_TXFOVW) != 0) 1556 ; /* TBD restart transmit engine */ 1557 return; 1558 } 1559 1560 static __inline void 1561 rtw_suspend_ticks(struct rtw_softc *sc) 1562 { 1563 RTW_DPRINTF2(("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 1564 sc->sc_do_tick = 0; 1565 } 1566 1567 static __inline void 1568 rtw_resume_ticks(struct rtw_softc *sc) 1569 { 1570 u_int32_t tsftrl0, tsftrl1, next_tick; 1571 1572 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1573 1574 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1575 next_tick = tsftrl1 + 1000000; 1576 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 1577 1578 sc->sc_do_tick = 1; 1579 1580 RTW_DPRINTF2(("%s: resume ticks delta %#08x now %#08x next %#08x\n", 1581 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 1582 } 1583 1584 static void 1585 rtw_intr_timeout(struct rtw_softc *sc) 1586 { 1587 RTW_DPRINTF2(("%s: timeout\n", sc->sc_dev.dv_xname)); 1588 if (sc->sc_do_tick) 1589 rtw_resume_ticks(sc); 1590 return; 1591 } 1592 1593 int 1594 rtw_intr(void *arg) 1595 { 1596 int i; 1597 struct rtw_softc *sc = arg; 1598 struct rtw_regs *regs = &sc->sc_regs; 1599 u_int16_t isr; 1600 1601 /* 1602 * If the interface isn't running, the interrupt couldn't 1603 * possibly have come from us. 1604 */ 1605 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 1606 (sc->sc_if.if_flags & IFF_RUNNING) == 0 || 1607 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1608 RTW_DPRINTF2(("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 1609 return (0); 1610 } 1611 1612 for (i = 0; i < 10; i++) { 1613 isr = RTW_READ16(regs, RTW_ISR); 1614 1615 RTW_WRITE16(regs, RTW_ISR, isr); 1616 RTW_WBR(regs, RTW_ISR, RTW_ISR); 1617 1618 if (sc->sc_intr_ack != NULL) 1619 (*sc->sc_intr_ack)(regs); 1620 1621 if (isr == 0) 1622 break; 1623 1624 #ifdef RTW_DEBUG 1625 #define PRINTINTR(flag) do { \ 1626 if ((isr & flag) != 0) { \ 1627 printf("%s" #flag, delim); \ 1628 delim = ","; \ 1629 } \ 1630 } while (0) 1631 1632 if (rtw_debug > 1 && isr != 0) { 1633 const char *delim = "<"; 1634 1635 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 1636 1637 PRINTINTR(RTW_INTR_TXFOVW); 1638 PRINTINTR(RTW_INTR_TIMEOUT); 1639 PRINTINTR(RTW_INTR_BCNINT); 1640 PRINTINTR(RTW_INTR_ATIMINT); 1641 PRINTINTR(RTW_INTR_TBDER); 1642 PRINTINTR(RTW_INTR_TBDOK); 1643 PRINTINTR(RTW_INTR_THPDER); 1644 PRINTINTR(RTW_INTR_THPDOK); 1645 PRINTINTR(RTW_INTR_TNPDER); 1646 PRINTINTR(RTW_INTR_TNPDOK); 1647 PRINTINTR(RTW_INTR_RXFOVW); 1648 PRINTINTR(RTW_INTR_RDU); 1649 PRINTINTR(RTW_INTR_TLPDER); 1650 PRINTINTR(RTW_INTR_TLPDOK); 1651 PRINTINTR(RTW_INTR_RER); 1652 PRINTINTR(RTW_INTR_ROK); 1653 1654 printf(">\n"); 1655 } 1656 #undef PRINTINTR 1657 #endif /* RTW_DEBUG */ 1658 1659 if ((isr & RTW_INTR_RX) != 0) 1660 rtw_intr_rx(sc, isr & RTW_INTR_RX); 1661 if ((isr & RTW_INTR_TX) != 0) 1662 rtw_intr_tx(sc, isr & RTW_INTR_TX); 1663 if ((isr & RTW_INTR_BEACON) != 0) 1664 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON); 1665 if ((isr & RTW_INTR_ATIMINT) != 0) 1666 rtw_intr_atim(sc); 1667 if ((isr & RTW_INTR_IOERROR) != 0) 1668 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR); 1669 if ((isr & RTW_INTR_TIMEOUT) != 0) 1670 rtw_intr_timeout(sc); 1671 } 1672 1673 return 1; 1674 } 1675 1676 static void 1677 rtw_stop(struct ifnet *ifp, int disable) 1678 { 1679 int pri, s; 1680 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 1681 struct ieee80211com *ic = &sc->sc_ic; 1682 struct rtw_regs *regs = &sc->sc_regs; 1683 1684 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1685 return; 1686 1687 rtw_suspend_ticks(sc); 1688 1689 s = splnet(); 1690 1691 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1692 1693 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 1694 /* Disable interrupts. */ 1695 RTW_WRITE16(regs, RTW_IMR, 0); 1696 1697 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 1698 1699 /* Stop the transmit and receive processes. First stop DMA, 1700 * then disable receiver and transmitter. 1701 */ 1702 RTW_WRITE8(regs, RTW_TPPOLL, 1703 RTW_TPPOLL_SBQ|RTW_TPPOLL_SHPQ|RTW_TPPOLL_SNPQ| 1704 RTW_TPPOLL_SLPQ); 1705 1706 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 1707 1708 rtw_io_enable(&sc->sc_regs, RTW_CR_RE|RTW_CR_TE, 0); 1709 } 1710 1711 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1712 rtw_txbufs_release(sc->sc_dmat, &sc->sc_ic, 1713 &sc->sc_txctl_blk[pri]); 1714 } 1715 1716 if (disable) { 1717 rtw_disable(sc); 1718 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxctl[0]); 1719 } 1720 1721 /* Mark the interface as not running. Cancel the watchdog timer. */ 1722 ifp->if_flags &= ~IFF_RUNNING; 1723 ifp->if_timer = 0; 1724 1725 splx(s); 1726 1727 return; 1728 } 1729 1730 const char * 1731 rtw_pwrstate_string(enum rtw_pwrstate power) 1732 { 1733 switch (power) { 1734 case RTW_ON: 1735 return "on"; 1736 case RTW_SLEEP: 1737 return "sleep"; 1738 case RTW_OFF: 1739 return "off"; 1740 default: 1741 return "unknown"; 1742 } 1743 } 1744 1745 /* XXX I am using the RFMD settings gleaned from the reference 1746 * driver. 1747 */ 1748 static void 1749 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1750 int before_rf) 1751 { 1752 u_int32_t anaparm; 1753 1754 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1755 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1756 1757 anaparm = RTW_READ(regs, RTW_ANAPARM); 1758 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1759 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1760 1761 switch (power) { 1762 case RTW_OFF: 1763 if (before_rf) 1764 return; 1765 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_OFF; 1766 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_OFF; 1767 anaparm |= RTW_ANAPARM_TXDACOFF; 1768 break; 1769 case RTW_SLEEP: 1770 if (!before_rf) 1771 return; 1772 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_SLEEP; 1773 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_SLEEP; 1774 anaparm |= RTW_ANAPARM_TXDACOFF; 1775 break; 1776 case RTW_ON: 1777 if (!before_rf) 1778 return; 1779 anaparm |= RTW_ANAPARM_RFPOW0_RFMD_ON; 1780 anaparm |= RTW_ANAPARM_RFPOW1_RFMD_ON; 1781 break; 1782 } 1783 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1784 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1785 } 1786 1787 static void 1788 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 1789 int before_rf) 1790 { 1791 u_int32_t anaparm; 1792 1793 RTW_DPRINTF(("%s: power state %s, %s RF\n", __func__, 1794 rtw_pwrstate_string(power), (before_rf) ? "before" : "after")); 1795 1796 anaparm = RTW_READ(regs, RTW_ANAPARM); 1797 anaparm &= ~(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK); 1798 anaparm &= ~RTW_ANAPARM_TXDACOFF; 1799 1800 switch (power) { 1801 case RTW_OFF: 1802 if (before_rf) 1803 return; 1804 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_OFF; 1805 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_OFF; 1806 anaparm |= RTW_ANAPARM_TXDACOFF; 1807 break; 1808 case RTW_SLEEP: 1809 if (!before_rf) 1810 return; 1811 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_SLEEP; 1812 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_SLEEP; 1813 anaparm |= RTW_ANAPARM_TXDACOFF; 1814 break; 1815 case RTW_ON: 1816 if (!before_rf) 1817 return; 1818 anaparm |= RTW_ANAPARM_RFPOW0_PHILIPS_ON; 1819 anaparm |= RTW_ANAPARM_RFPOW1_PHILIPS_ON; 1820 break; 1821 } 1822 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 1823 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 1824 } 1825 1826 static void 1827 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf) 1828 { 1829 struct rtw_regs *regs = &sc->sc_regs; 1830 1831 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 1832 1833 (*sc->sc_pwrstate_cb)(regs, power, before_rf); 1834 1835 rtw_set_access(sc, RTW_ACCESS_NONE); 1836 1837 return; 1838 } 1839 1840 static int 1841 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 1842 { 1843 int rc; 1844 1845 RTW_DPRINTF2(("%s: %s->%s\n", __func__, 1846 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 1847 1848 if (sc->sc_pwrstate == power) 1849 return 0; 1850 1851 rtw_pwrstate0(sc, power, 1); 1852 rc = rtw_rf_pwrstate(sc->sc_rf, power); 1853 rtw_pwrstate0(sc, power, 0); 1854 1855 switch (power) { 1856 case RTW_ON: 1857 /* TBD set LEDs */ 1858 break; 1859 case RTW_SLEEP: 1860 /* TBD */ 1861 break; 1862 case RTW_OFF: 1863 /* TBD */ 1864 break; 1865 } 1866 if (rc == 0) 1867 sc->sc_pwrstate = power; 1868 else 1869 sc->sc_pwrstate = RTW_OFF; 1870 return rc; 1871 } 1872 1873 static int 1874 rtw_tune(struct rtw_softc *sc) 1875 { 1876 struct ieee80211com *ic = &sc->sc_ic; 1877 u_int chan; 1878 int rc; 1879 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 1880 dflantb = sc->sc_flags & RTW_F_DFLANTB; 1881 1882 KASSERT(ic->ic_bss->ni_chan != NULL); 1883 1884 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1885 if (chan == IEEE80211_CHAN_ANY) 1886 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1887 1888 if (chan == sc->sc_cur_chan) { 1889 RTW_DPRINTF(("%s: already tuned chan #%d\n", __func__, chan)); 1890 return 0; 1891 } 1892 1893 rtw_suspend_ticks(sc); 1894 1895 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 0); 1896 1897 /* TBD wait for Tx to complete */ 1898 1899 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 1900 1901 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 1902 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_bss->ni_chan), 1903 sc->sc_csthr, ic->ic_bss->ni_chan->ic_freq, antdiv, 1904 dflantb, RTW_ON)) != 0) { 1905 /* XXX condition on powersaving */ 1906 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 1907 } 1908 1909 sc->sc_cur_chan = chan; 1910 1911 rtw_io_enable(&sc->sc_regs, RTW_CR_RE | RTW_CR_TE, 1); 1912 1913 rtw_resume_ticks(sc); 1914 1915 return rc; 1916 } 1917 1918 void 1919 rtw_disable(struct rtw_softc *sc) 1920 { 1921 int rc; 1922 1923 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 1924 return; 1925 1926 /* turn off PHY */ 1927 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 1928 printf("%s: failed to turn off PHY (%d)\n", 1929 sc->sc_dev.dv_xname, rc); 1930 1931 if (sc->sc_disable != NULL) 1932 (*sc->sc_disable)(sc); 1933 1934 sc->sc_flags &= ~RTW_F_ENABLED; 1935 } 1936 1937 int 1938 rtw_enable(struct rtw_softc *sc) 1939 { 1940 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 1941 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 1942 printf("%s: device enable failed\n", 1943 sc->sc_dev.dv_xname); 1944 return (EIO); 1945 } 1946 sc->sc_flags |= RTW_F_ENABLED; 1947 } 1948 return (0); 1949 } 1950 1951 static void 1952 rtw_transmit_config(struct rtw_regs *regs) 1953 { 1954 u_int32_t tcr; 1955 1956 tcr = RTW_READ(regs, RTW_TCR); 1957 1958 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 1959 tcr &= ~RTW_TCR_LBK_MASK; 1960 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 1961 1962 /* set short/long retry limits */ 1963 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 1964 tcr |= LSHIFT(7, RTW_TCR_SRL_MASK) | LSHIFT(7, RTW_TCR_LRL_MASK); 1965 1966 tcr |= RTW_TCR_CRC; /* NIC appends CRC32 */ 1967 1968 RTW_WRITE(regs, RTW_TCR, tcr); 1969 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 1970 } 1971 1972 static __inline void 1973 rtw_enable_interrupts(struct rtw_softc *sc) 1974 { 1975 struct rtw_regs *regs = &sc->sc_regs; 1976 1977 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 1978 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 1979 1980 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 1981 RTW_WBW(regs, RTW_IMR, RTW_ISR); 1982 RTW_WRITE16(regs, RTW_ISR, 0xffff); 1983 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 1984 1985 /* XXX necessary? */ 1986 if (sc->sc_intr_ack != NULL) 1987 (*sc->sc_intr_ack)(regs); 1988 } 1989 1990 /* XXX is the endianness correct? test. */ 1991 #define rtw_calchash(addr) \ 1992 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1993 1994 static void 1995 rtw_pktfilt_load(struct rtw_softc *sc) 1996 { 1997 struct rtw_regs *regs = &sc->sc_regs; 1998 struct ieee80211com *ic = &sc->sc_ic; 1999 struct ethercom *ec = &ic->ic_ec; 2000 struct ifnet *ifp = &sc->sc_ic.ic_if; 2001 int hash; 2002 u_int32_t hashes[2] = { 0, 0 }; 2003 struct ether_multi *enm; 2004 struct ether_multistep step; 2005 2006 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2007 2008 #define RTW_RCR_MONITOR (RTW_RCR_ACRC32|RTW_RCR_APM|RTW_RCR_AAP|RTW_RCR_AB) 2009 2010 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2011 sc->sc_rcr |= RTW_RCR_MONITOR; 2012 else 2013 sc->sc_rcr &= ~RTW_RCR_MONITOR; 2014 2015 /* XXX reference sources BEGIN */ 2016 sc->sc_rcr |= RTW_RCR_ENMARP | RTW_RCR_AICV | RTW_RCR_ACRC32; 2017 sc->sc_rcr |= RTW_RCR_AB | RTW_RCR_AM | RTW_RCR_APM; 2018 #if 0 2019 /* receive broadcasts in our BSS */ 2020 sc->sc_rcr |= RTW_RCR_ADD3; 2021 #endif 2022 /* XXX reference sources END */ 2023 2024 /* receive pwrmgmt frames. */ 2025 sc->sc_rcr |= RTW_RCR_APWRMGT; 2026 /* receive mgmt/ctrl/data frames. */ 2027 sc->sc_rcr |= RTW_RCR_AMF | RTW_RCR_ACF | RTW_RCR_ADF; 2028 /* initialize Rx DMA threshold, Tx DMA burst size */ 2029 sc->sc_rcr |= RTW_RCR_RXFTH_WHOLE | RTW_RCR_MXDMA_1024; 2030 2031 ifp->if_flags &= ~IFF_ALLMULTI; 2032 2033 if (ifp->if_flags & IFF_PROMISC) { 2034 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2035 allmulti: 2036 ifp->if_flags |= IFF_ALLMULTI; 2037 goto setit; 2038 } 2039 2040 /* 2041 * Program the 64-bit multicast hash filter. 2042 */ 2043 ETHER_FIRST_MULTI(step, ec, enm); 2044 while (enm != NULL) { 2045 /* XXX */ 2046 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2047 ETHER_ADDR_LEN) != 0) 2048 goto allmulti; 2049 2050 hash = rtw_calchash(enm->enm_addrlo); 2051 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2052 ETHER_NEXT_MULTI(step, enm); 2053 } 2054 2055 if (ifp->if_flags & IFF_BROADCAST) { 2056 hash = rtw_calchash(etherbroadcastaddr); 2057 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2058 } 2059 2060 /* all bits set => hash is useless */ 2061 if (~(hashes[0] & hashes[1]) == 0) 2062 goto allmulti; 2063 2064 setit: 2065 if (ifp->if_flags & IFF_ALLMULTI) 2066 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */ 2067 2068 if (ic->ic_state == IEEE80211_S_SCAN) 2069 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2070 2071 hashes[0] = hashes[1] = 0xffffffff; 2072 2073 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2074 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2075 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2076 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2077 2078 DPRINTF(sc, ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2079 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2080 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2081 2082 return; 2083 } 2084 2085 static int 2086 rtw_init(struct ifnet *ifp) 2087 { 2088 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2089 struct ieee80211com *ic = &sc->sc_ic; 2090 struct rtw_regs *regs = &sc->sc_regs; 2091 int rc = 0; 2092 2093 if ((rc = rtw_enable(sc)) != 0) 2094 goto out; 2095 2096 /* Cancel pending I/O and reset. */ 2097 rtw_stop(ifp, 0); 2098 2099 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2100 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 2101 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 2102 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 2103 2104 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2105 goto out; 2106 2107 rtw_swring_setup(sc); 2108 2109 rtw_transmit_config(regs); 2110 2111 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2112 2113 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2114 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2115 2116 /* long PLCP header, 1Mbps basic rate */ 2117 RTW_WRITE16(regs, RTW_BRSR, 0x0); 2118 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2119 2120 rtw_set_access(sc, RTW_ACCESS_ANAPARM); 2121 rtw_set_access(sc, RTW_ACCESS_NONE); 2122 2123 #if 0 2124 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_GWAKE|RTW_FEMR_WKUP|RTW_FEMR_INTR); 2125 #endif 2126 /* XXX from reference sources */ 2127 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2128 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2129 2130 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2131 2132 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2133 /* from Linux driver */ 2134 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2135 2136 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2137 2138 rtw_enable_interrupts(sc); 2139 2140 rtw_pktfilt_load(sc); 2141 2142 rtw_hwring_setup(sc); 2143 2144 rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1); 2145 2146 ifp->if_flags |= IFF_RUNNING; 2147 ic->ic_state = IEEE80211_S_INIT; 2148 2149 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2150 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2151 2152 rtw_resume_ticks(sc); 2153 2154 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2155 rtw_set_access(sc, RTW_ACCESS_CONFIG); 2156 2157 switch (ic->ic_opmode) { 2158 case IEEE80211_M_AHDEMO: 2159 case IEEE80211_M_IBSS: 2160 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_ADHOC_OK); 2161 break; 2162 case IEEE80211_M_HOSTAP: 2163 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_AP_OK); 2164 break; 2165 case IEEE80211_M_MONITOR: 2166 /* XXX */ 2167 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_NOLINK); 2168 break; 2169 case IEEE80211_M_STA: 2170 RTW_WRITE8(regs, RTW_MSR, RTW_MSR_NETYPE_INFRA_OK); 2171 break; 2172 } 2173 2174 rtw_set_access(sc, RTW_ACCESS_NONE); 2175 2176 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2177 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2178 else 2179 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2180 2181 out: 2182 return rc; 2183 } 2184 2185 static int 2186 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2187 { 2188 int rc = 0; 2189 struct rtw_softc *sc = ifp->if_softc; 2190 struct ifreq *ifr = (struct ifreq *)data; 2191 2192 switch (cmd) { 2193 case SIOCSIFFLAGS: 2194 if ((ifp->if_flags & IFF_UP) != 0) { 2195 if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2196 rtw_pktfilt_load(sc); 2197 } else 2198 rc = rtw_init(ifp); 2199 #ifdef RTW_DEBUG 2200 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2201 #endif /* RTW_DEBUG */ 2202 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2203 #ifdef RTW_DEBUG 2204 rtw_print_regs(&sc->sc_regs, ifp->if_xname, __func__); 2205 #endif /* RTW_DEBUG */ 2206 rtw_stop(ifp, 1); 2207 } 2208 break; 2209 case SIOCADDMULTI: 2210 case SIOCDELMULTI: 2211 if (cmd == SIOCADDMULTI) 2212 rc = ether_addmulti(ifr, &sc->sc_ic.ic_ec); 2213 else 2214 rc = ether_delmulti(ifr, &sc->sc_ic.ic_ec); 2215 if (rc == ENETRESET) { 2216 if (ifp->if_flags & IFF_RUNNING) 2217 rtw_pktfilt_load(sc); 2218 rc = 0; 2219 } 2220 break; 2221 default: 2222 if ((rc = ieee80211_ioctl(ifp, cmd, data)) == ENETRESET) { 2223 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2224 rc = rtw_init(ifp); 2225 else 2226 rc = 0; 2227 } 2228 break; 2229 } 2230 return rc; 2231 } 2232 2233 /* Point *mp at the next 802.11 frame to transmit. Point *stcp 2234 * at the driver's selection of transmit control block for the packet. 2235 */ 2236 static __inline int 2237 rtw_dequeue(struct ifnet *ifp, struct rtw_txctl_blk **stcp, 2238 struct rtw_txdesc_blk **htcp, struct mbuf **mp, 2239 struct ieee80211_node **nip) 2240 { 2241 struct rtw_txctl_blk *stc; 2242 struct rtw_txdesc_blk *htc; 2243 struct mbuf *m0; 2244 struct rtw_softc *sc; 2245 struct ieee80211com *ic; 2246 2247 sc = (struct rtw_softc *)ifp->if_softc; 2248 2249 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2250 *mp = NULL; 2251 2252 stc = &sc->sc_txctl_blk[RTW_TXPRIMD]; 2253 htc = &sc->sc_txdesc_blk[RTW_TXPRIMD]; 2254 2255 if (SIMPLEQ_EMPTY(&stc->stc_freeq) || htc->htc_nfree == 0) { 2256 DPRINTF2(sc, ("%s: out of descriptors\n", __func__)); 2257 ifp->if_flags |= IFF_OACTIVE; 2258 return 0; 2259 } 2260 2261 ic = &sc->sc_ic; 2262 2263 if (!IF_IS_EMPTY(&ic->ic_mgtq)) { 2264 IF_DEQUEUE(&ic->ic_mgtq, m0); 2265 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2266 m0->m_pkthdr.rcvif = NULL; 2267 DPRINTF2(sc, ("%s: dequeue mgt frame\n", __func__)); 2268 } else if (ic->ic_state != IEEE80211_S_RUN) { 2269 DPRINTF2(sc, ("%s: not running\n", __func__)); 2270 return 0; 2271 } else if (!IF_IS_EMPTY(&ic->ic_pwrsaveq)) { 2272 IF_DEQUEUE(&ic->ic_pwrsaveq, m0); 2273 *nip = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2274 m0->m_pkthdr.rcvif = NULL; 2275 DPRINTF2(sc, ("%s: dequeue pwrsave frame\n", __func__)); 2276 } else { 2277 IFQ_POLL(&ifp->if_snd, m0); 2278 if (m0 == NULL) { 2279 DPRINTF2(sc, ("%s: no frame\n", __func__)); 2280 return 0; 2281 } 2282 DPRINTF2(sc, ("%s: dequeue data frame\n", __func__)); 2283 IFQ_DEQUEUE(&ifp->if_snd, m0); 2284 ifp->if_opackets++; 2285 #if NBPFILTER > 0 2286 if (ifp->if_bpf) 2287 bpf_mtap(ifp->if_bpf, m0); 2288 #endif 2289 if ((m0 = ieee80211_encap(ifp, m0, nip)) == NULL) { 2290 DPRINTF2(sc, ("%s: encap error\n", __func__)); 2291 ifp->if_oerrors++; 2292 return -1; 2293 } 2294 } 2295 DPRINTF2(sc, ("%s: leave\n", __func__)); 2296 *stcp = stc; 2297 *htcp = htc; 2298 *mp = m0; 2299 return 0; 2300 } 2301 2302 /* TBD factor with atw_start */ 2303 static struct mbuf * 2304 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 2305 u_int ndescfree, short *ifflagsp, const char *dvname) 2306 { 2307 int first, rc; 2308 struct mbuf *m, *m0; 2309 2310 m0 = chain; 2311 2312 /* 2313 * Load the DMA map. Copy and try (once) again if the packet 2314 * didn't fit in the alloted number of segments. 2315 */ 2316 for (first = 1; 2317 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 2318 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 2319 dmam->dm_nsegs > ndescfree) && first; 2320 first = 0) { 2321 if (rc == 0) 2322 bus_dmamap_unload(dmat, dmam); 2323 MGETHDR(m, M_DONTWAIT, MT_DATA); 2324 if (m == NULL) { 2325 printf("%s: unable to allocate Tx mbuf\n", 2326 dvname); 2327 break; 2328 } 2329 if (m0->m_pkthdr.len > MHLEN) { 2330 MCLGET(m, M_DONTWAIT); 2331 if ((m->m_flags & M_EXT) == 0) { 2332 printf("%s: cannot allocate Tx cluster\n", 2333 dvname); 2334 m_freem(m); 2335 break; 2336 } 2337 } 2338 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2339 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 2340 m_freem(m0); 2341 m0 = m; 2342 m = NULL; 2343 } 2344 if (rc != 0) { 2345 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 2346 m_freem(m0); 2347 return NULL; 2348 } else if (dmam->dm_nsegs > ndescfree) { 2349 *ifflagsp |= IFF_OACTIVE; 2350 bus_dmamap_unload(dmat, dmam); 2351 m_freem(m0); 2352 return NULL; 2353 } 2354 return m0; 2355 } 2356 2357 static void 2358 rtw_start(struct ifnet *ifp) 2359 { 2360 int desc, i, lastdesc, npkt, rate; 2361 uint32_t proto_txctl0, txctl0, txctl1; 2362 bus_dmamap_t dmamap; 2363 struct ieee80211com *ic; 2364 struct ieee80211_duration *d0; 2365 struct ieee80211_frame *wh; 2366 struct ieee80211_node *ni; 2367 struct mbuf *m0; 2368 struct rtw_softc *sc; 2369 struct rtw_txctl_blk *stc; 2370 struct rtw_txdesc_blk *htc; 2371 struct rtw_txctl *stx; 2372 struct rtw_txdesc *htx; 2373 2374 sc = (struct rtw_softc *)ifp->if_softc; 2375 ic = &sc->sc_ic; 2376 2377 DPRINTF2(sc, ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 2378 2379 /* XXX do real rate control */ 2380 proto_txctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 2381 2382 switch (rate = MAX(2, ieee80211_get_rate(ic))) { 2383 case 2: 2384 proto_txctl0 |= RTW_TXCTL0_RATE_1MBPS; 2385 break; 2386 case 4: 2387 proto_txctl0 |= RTW_TXCTL0_RATE_2MBPS; 2388 break; 2389 case 11: 2390 proto_txctl0 |= RTW_TXCTL0_RATE_5MBPS; 2391 break; 2392 case 22: 2393 proto_txctl0 |= RTW_TXCTL0_RATE_11MBPS; 2394 break; 2395 } 2396 2397 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 2398 proto_txctl0 |= RTW_TXCTL0_SPLCP; 2399 2400 for (;;) { 2401 if (rtw_dequeue(ifp, &stc, &htc, &m0, &ni) == -1) 2402 continue; 2403 if (m0 == NULL) 2404 break; 2405 stx = SIMPLEQ_FIRST(&stc->stc_freeq); 2406 2407 dmamap = stx->stx_dmamap; 2408 2409 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 2410 htc->htc_nfree, &ifp->if_flags, sc->sc_dev.dv_xname); 2411 2412 if (m0 == NULL || dmamap->dm_nsegs == 0) { 2413 DPRINTF2(sc, ("%s: fail dmamap load\n", __func__)); 2414 goto post_dequeue_err; 2415 } 2416 2417 txctl0 = proto_txctl0 | 2418 LSHIFT(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 2419 2420 wh = mtod(m0, struct ieee80211_frame *); 2421 2422 if (ieee80211_compute_duration(wh, 2423 m0->m_pkthdr.len - sizeof(wh), 2424 ic->ic_flags, ic->ic_fragthreshold, 2425 rate, &stx->stx_d0, &stx->stx_dn, &npkt) == -1) { 2426 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 2427 goto post_load_err; 2428 } 2429 2430 /* XXX >= ? */ 2431 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 2432 txctl0 |= RTW_TXCTL0_RTSEN; 2433 2434 d0 = &stx->stx_d0; 2435 2436 txctl1 = LSHIFT(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 2437 LSHIFT(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 2438 2439 if ((d0->d_plcp_svc & IEEE80211_PLCP_SERVICE_LENEXT) != 0) 2440 txctl1 |= RTW_TXCTL1_LENGEXT; 2441 2442 /* TBD fragmentation */ 2443 2444 stx->stx_first = htc->htc_next; 2445 2446 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2447 htc, stx->stx_first, dmamap->dm_nsegs, 2448 BUS_DMASYNC_PREWRITE); 2449 2450 for (i = 0, lastdesc = desc = stx->stx_first; 2451 i < dmamap->dm_nsegs; 2452 i++, desc = RTW_NEXT_IDX(htc, desc)) { 2453 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 2454 DPRINTF2(sc, ("%s: seg too long\n", __func__)); 2455 goto post_load_err; 2456 } 2457 htx = &htc->htc_desc[desc]; 2458 htx->htx_ctl0 = htole32(txctl0); 2459 if (i != 0) 2460 htx->htx_ctl0 |= htole32(RTW_TXCTL0_OWN); 2461 htx->htx_ctl1 = htole32(txctl1); 2462 htx->htx_buf = htole32(dmamap->dm_segs[i].ds_addr); 2463 htx->htx_len = htole32(dmamap->dm_segs[i].ds_len); 2464 lastdesc = desc; 2465 DPRINTF2(sc, ("%s: stx %p txdesc[%d] ctl0 %#08x " 2466 "ctl1 %#08x buf %#08x len %#08x\n", 2467 sc->sc_dev.dv_xname, stx, desc, htx->htx_ctl0, 2468 htx->htx_ctl1, htx->htx_buf, htx->htx_len)); 2469 } 2470 2471 htc->htc_desc[lastdesc].htx_ctl0 |= htole32(RTW_TXCTL0_LS); 2472 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2473 htole32(RTW_TXCTL0_FS); 2474 2475 DPRINTF2(sc, ("%s: stx %p FS on txdesc[%d], LS on txdesc[%d]\n", 2476 sc->sc_dev.dv_xname, stx, lastdesc, stx->stx_first)); 2477 2478 stx->stx_ni = ni; 2479 stx->stx_mbuf = m0; 2480 stx->stx_last = lastdesc; 2481 2482 htc->htc_nfree -= dmamap->dm_nsegs; 2483 htc->htc_next = desc; 2484 2485 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2486 htc, stx->stx_first, dmamap->dm_nsegs, 2487 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2488 2489 htc->htc_desc[stx->stx_first].htx_ctl0 |= 2490 htole32(RTW_TXCTL0_OWN); 2491 2492 DPRINTF2(sc, ("%s: stx %p OWN on txdesc[%d]\n", 2493 sc->sc_dev.dv_xname, stx, stx->stx_first)); 2494 2495 rtw_txdescs_sync(sc->sc_dmat, sc->sc_desc_dmamap, 2496 htc, stx->stx_first, 1, 2497 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2498 2499 SIMPLEQ_REMOVE_HEAD(&stc->stc_freeq, stx_q); 2500 SIMPLEQ_INSERT_TAIL(&stc->stc_dirtyq, stx, stx_q); 2501 2502 stc->stc_tx_timer = 5; 2503 ifp->if_timer = 1; 2504 2505 /* TBD poke just one txmtr? */ 2506 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, 2507 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ | RTW_TPPOLL_HPQ | 2508 RTW_TPPOLL_BQ); 2509 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 2510 } 2511 DPRINTF2(sc, ("%s: leave\n", __func__)); 2512 return; 2513 post_load_err: 2514 bus_dmamap_unload(sc->sc_dmat, dmamap); 2515 m_freem(m0); 2516 post_dequeue_err: 2517 ieee80211_release_node(&sc->sc_ic, ni); 2518 return; 2519 } 2520 2521 static void 2522 rtw_watchdog(struct ifnet *ifp) 2523 { 2524 int pri; 2525 struct rtw_softc *sc; 2526 struct rtw_txctl_blk *stc; 2527 2528 sc = ifp->if_softc; 2529 2530 ifp->if_timer = 0; 2531 2532 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2533 return; 2534 2535 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2536 stc = &sc->sc_txctl_blk[pri]; 2537 2538 if (stc->stc_tx_timer == 0) 2539 continue; 2540 2541 if (--stc->stc_tx_timer == 0) { 2542 if (SIMPLEQ_EMPTY(&stc->stc_dirtyq)) 2543 continue; 2544 printf("%s: transmit timeout, priority %d\n", 2545 ifp->if_xname, pri); 2546 ifp->if_oerrors++; 2547 /* XXX be gentle */ 2548 (void)rtw_init(ifp); 2549 rtw_start(ifp); 2550 } else 2551 ifp->if_timer = 1; 2552 } 2553 /* TBD */ 2554 return; 2555 } 2556 2557 static void 2558 rtw_start_beacon(struct rtw_softc *sc, int enable) 2559 { 2560 /* TBD */ 2561 return; 2562 } 2563 2564 static void 2565 rtw_next_scan(void *arg) 2566 { 2567 struct ieee80211com *ic = arg; 2568 int s; 2569 2570 /* don't call rtw_start w/o network interrupts blocked */ 2571 s = splnet(); 2572 if (ic->ic_state == IEEE80211_S_SCAN) 2573 ieee80211_next_scan(ic); 2574 splx(s); 2575 } 2576 2577 /* Synchronize the hardware state with the software state. */ 2578 static int 2579 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2580 { 2581 struct ifnet *ifp = &ic->ic_if; 2582 struct rtw_softc *sc = ifp->if_softc; 2583 enum ieee80211_state ostate; 2584 int error; 2585 2586 ostate = ic->ic_state; 2587 2588 if (nstate == IEEE80211_S_INIT) { 2589 callout_stop(&sc->sc_scan_ch); 2590 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2591 rtw_start_beacon(sc, 0); 2592 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2593 } 2594 2595 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 2596 rtw_pwrstate(sc, RTW_ON); 2597 2598 if ((error = rtw_tune(sc)) != 0) 2599 return error; 2600 2601 switch (nstate) { 2602 case IEEE80211_S_ASSOC: 2603 break; 2604 case IEEE80211_S_INIT: 2605 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2606 break; 2607 case IEEE80211_S_SCAN: 2608 #if 0 2609 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2610 rtw_write_bssid(sc); 2611 #endif 2612 2613 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 2614 rtw_next_scan, ic); 2615 2616 break; 2617 case IEEE80211_S_RUN: 2618 if (ic->ic_opmode == IEEE80211_M_STA) 2619 break; 2620 /*FALLTHROUGH*/ 2621 case IEEE80211_S_AUTH: 2622 #if 0 2623 rtw_write_bssid(sc); 2624 rtw_write_bcn_thresh(sc); 2625 rtw_write_ssid(sc); 2626 rtw_write_sup_rates(sc); 2627 #endif 2628 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2629 ic->ic_opmode == IEEE80211_M_MONITOR) 2630 break; 2631 2632 /* TBD set listen interval, beacon interval */ 2633 2634 #if 0 2635 rtw_tsf(sc); 2636 #endif 2637 break; 2638 } 2639 2640 if (nstate != IEEE80211_S_SCAN) 2641 callout_stop(&sc->sc_scan_ch); 2642 2643 if (nstate == IEEE80211_S_RUN && 2644 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2645 ic->ic_opmode == IEEE80211_M_IBSS)) 2646 rtw_start_beacon(sc, 1); 2647 else 2648 rtw_start_beacon(sc, 0); 2649 2650 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 2651 } 2652 2653 static void 2654 rtw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2655 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2656 { 2657 /* TBD */ 2658 return; 2659 } 2660 2661 static void 2662 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2663 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2664 { 2665 struct rtw_softc *sc = (struct rtw_softc*)ic->ic_softc; 2666 2667 switch (subtype) { 2668 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2669 /* do nothing: hardware answers probe request XXX */ 2670 break; 2671 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2672 case IEEE80211_FC0_SUBTYPE_BEACON: 2673 rtw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2674 break; 2675 default: 2676 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2677 break; 2678 } 2679 return; 2680 } 2681 2682 static struct ieee80211_node * 2683 rtw_node_alloc(struct ieee80211com *ic) 2684 { 2685 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2686 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(ic); 2687 2688 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 2689 return ni; 2690 } 2691 2692 static void 2693 rtw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 2694 { 2695 struct rtw_softc *sc = (struct rtw_softc *)ic->ic_if.if_softc; 2696 2697 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 2698 ether_sprintf(ni->ni_bssid))); 2699 (*sc->sc_mtbl.mt_node_free)(ic, ni); 2700 } 2701 2702 static int 2703 rtw_media_change(struct ifnet *ifp) 2704 { 2705 int error; 2706 2707 error = ieee80211_media_change(ifp); 2708 if (error == ENETRESET) { 2709 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 2710 (IFF_RUNNING|IFF_UP)) 2711 rtw_init(ifp); /* XXX lose error */ 2712 error = 0; 2713 } 2714 return error; 2715 } 2716 2717 static void 2718 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 2719 { 2720 struct rtw_softc *sc = ifp->if_softc; 2721 2722 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2723 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 2724 imr->ifm_status = 0; 2725 return; 2726 } 2727 ieee80211_media_status(ifp, imr); 2728 } 2729 2730 void 2731 rtw_power(int why, void *arg) 2732 { 2733 struct rtw_softc *sc = arg; 2734 struct ifnet *ifp = &sc->sc_ic.ic_if; 2735 int s; 2736 2737 DPRINTF(sc, ("%s: rtw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 2738 2739 s = splnet(); 2740 switch (why) { 2741 case PWR_STANDBY: 2742 /* XXX do nothing. */ 2743 break; 2744 case PWR_SUSPEND: 2745 rtw_stop(ifp, 0); 2746 if (sc->sc_power != NULL) 2747 (*sc->sc_power)(sc, why); 2748 break; 2749 case PWR_RESUME: 2750 if (ifp->if_flags & IFF_UP) { 2751 if (sc->sc_power != NULL) 2752 (*sc->sc_power)(sc, why); 2753 rtw_init(ifp); 2754 } 2755 break; 2756 case PWR_SOFTSUSPEND: 2757 case PWR_SOFTSTANDBY: 2758 case PWR_SOFTRESUME: 2759 break; 2760 } 2761 splx(s); 2762 } 2763 2764 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 2765 void 2766 rtw_shutdown(void *arg) 2767 { 2768 struct rtw_softc *sc = arg; 2769 2770 rtw_stop(&sc->sc_ic.ic_if, 1); 2771 } 2772 2773 static __inline void 2774 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 2775 { 2776 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 2777 ifp->if_softc = softc; 2778 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 2779 IFF_NOTRAILERS; 2780 ifp->if_ioctl = rtw_ioctl; 2781 ifp->if_start = rtw_start; 2782 ifp->if_watchdog = rtw_watchdog; 2783 ifp->if_init = rtw_init; 2784 ifp->if_stop = rtw_stop; 2785 } 2786 2787 static __inline void 2788 rtw_set80211props(struct ieee80211com *ic) 2789 { 2790 int nrate; 2791 ic->ic_phytype = IEEE80211_T_DS; 2792 ic->ic_opmode = IEEE80211_M_STA; 2793 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 2794 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 2795 2796 nrate = 0; 2797 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 2798 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 2799 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 2800 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 2801 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 2802 } 2803 2804 static __inline void 2805 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 2806 { 2807 mtbl->mt_newstate = ic->ic_newstate; 2808 ic->ic_newstate = rtw_newstate; 2809 2810 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 2811 ic->ic_recv_mgmt = rtw_recv_mgmt; 2812 2813 mtbl->mt_node_free = ic->ic_node_free; 2814 ic->ic_node_free = rtw_node_free; 2815 2816 mtbl->mt_node_alloc = ic->ic_node_alloc; 2817 ic->ic_node_alloc = rtw_node_alloc; 2818 } 2819 2820 static __inline void 2821 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 2822 void *arg) 2823 { 2824 /* 2825 * Make sure the interface is shutdown during reboot. 2826 */ 2827 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 2828 if (hooks->rh_shutdown == NULL) 2829 printf("%s: WARNING: unable to establish shutdown hook\n", 2830 dvname); 2831 2832 /* 2833 * Add a suspend hook to make sure we come back up after a 2834 * resume. 2835 */ 2836 hooks->rh_power = powerhook_establish(rtw_power, arg); 2837 if (hooks->rh_power == NULL) 2838 printf("%s: WARNING: unable to establish power hook\n", 2839 dvname); 2840 } 2841 2842 static __inline void 2843 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 2844 void *arg) 2845 { 2846 if (hooks->rh_shutdown != NULL) 2847 shutdownhook_disestablish(hooks->rh_shutdown); 2848 2849 if (hooks->rh_power != NULL) 2850 powerhook_disestablish(hooks->rh_power); 2851 } 2852 2853 static __inline void 2854 rtw_init_radiotap(struct rtw_softc *sc) 2855 { 2856 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 2857 sc->sc_rxtap.rr_ihdr.it_len = sizeof(sc->sc_rxtapu); 2858 sc->sc_rxtap.rr_ihdr.it_present = RTW_RX_RADIOTAP_PRESENT; 2859 2860 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 2861 sc->sc_txtap.rt_ihdr.it_len = sizeof(sc->sc_txtapu); 2862 sc->sc_txtap.rt_ihdr.it_present = RTW_TX_RADIOTAP_PRESENT; 2863 } 2864 2865 static int 2866 rtw_txctl_blk_setup(struct rtw_txctl_blk *stc, u_int qlen) 2867 { 2868 SIMPLEQ_INIT(&stc->stc_dirtyq); 2869 SIMPLEQ_INIT(&stc->stc_freeq); 2870 stc->stc_ndesc = qlen; 2871 stc->stc_desc = malloc(qlen * sizeof(*stc->stc_desc), M_DEVBUF, 2872 M_NOWAIT); 2873 if (stc->stc_desc == NULL) 2874 return ENOMEM; 2875 return 0; 2876 } 2877 2878 static void 2879 rtw_txctl_blk_cleanup_all(struct rtw_softc *sc) 2880 { 2881 struct rtw_txctl_blk *stc; 2882 int qlen[RTW_NTXPRI] = 2883 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2884 int pri; 2885 2886 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2887 stc = &sc->sc_txctl_blk[pri]; 2888 free(stc->stc_desc, M_DEVBUF); 2889 stc->stc_desc = NULL; 2890 } 2891 } 2892 2893 static int 2894 rtw_txctl_blk_setup_all(struct rtw_softc *sc) 2895 { 2896 int pri, rc = 0; 2897 int qlen[RTW_NTXPRI] = 2898 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 2899 2900 for (pri = 0; pri < sizeof(qlen)/sizeof(qlen[0]); pri++) { 2901 rc = rtw_txctl_blk_setup(&sc->sc_txctl_blk[pri], qlen[pri]); 2902 if (rc != 0) 2903 break; 2904 } 2905 return rc; 2906 } 2907 2908 static void 2909 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *htc, struct rtw_txdesc *desc, 2910 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 2911 { 2912 int i; 2913 2914 htc->htc_ndesc = ndesc; 2915 htc->htc_desc = desc; 2916 htc->htc_physbase = physbase; 2917 htc->htc_ofs = ofs; 2918 2919 (void)memset(htc->htc_desc, 0, 2920 sizeof(htc->htc_desc[0]) * htc->htc_ndesc); 2921 2922 for (i = 0; i < htc->htc_ndesc; i++) { 2923 htc->htc_desc[i].htx_next = htole32(RTW_NEXT_DESC(htc, i)); 2924 } 2925 } 2926 2927 static void 2928 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 2929 { 2930 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 2931 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 2932 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 2933 2934 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 2935 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 2936 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 2937 2938 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 2939 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 2940 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 2941 2942 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 2943 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 2944 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 2945 } 2946 2947 static struct rtw_rf * 2948 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, 2949 rtw_rf_write_t rf_write, int digphy) 2950 { 2951 struct rtw_rf *rf; 2952 2953 switch (rfchipid) { 2954 case RTW_RFCHIPID_MAXIM: 2955 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 2956 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 2957 break; 2958 case RTW_RFCHIPID_PHILIPS: 2959 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 2960 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 2961 break; 2962 default: 2963 return NULL; 2964 } 2965 rf->rf_continuous_tx_cb = 2966 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 2967 rf->rf_continuous_tx_arg = (void *)sc; 2968 return rf; 2969 } 2970 2971 /* Revision C and later use a different PHY delay setting than 2972 * revisions A and B. 2973 */ 2974 static u_int8_t 2975 rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0) 2976 { 2977 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 2978 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 2979 2980 u_int8_t phydelay = LSHIFT(0x6, RTW_PHYDELAY_PHYDELAY); 2981 2982 RTW_WRITE(regs, RTW_RCR, REVAB); 2983 RTW_WBW(regs, RTW_RCR, RTW_RCR); 2984 RTW_WRITE(regs, RTW_RCR, REVC); 2985 2986 RTW_WBR(regs, RTW_RCR, RTW_RCR); 2987 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 2988 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 2989 2990 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */ 2991 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 2992 2993 return phydelay; 2994 #undef REVC 2995 } 2996 2997 void 2998 rtw_attach(struct rtw_softc *sc) 2999 { 3000 rtw_rf_write_t rf_write; 3001 struct rtw_txctl_blk *stc; 3002 int pri, rc, vers; 3003 3004 #if 0 3005 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_txdesc) == 0, 3006 "RTW_DESC_ALIGNMENT is not a multiple of " 3007 "sizeof(struct rtw_txdesc)"); 3008 3009 CASSERT(RTW_DESC_ALIGNMENT % sizeof(struct rtw_rxdesc) == 0, 3010 "RTW_DESC_ALIGNMENT is not a multiple of " 3011 "sizeof(struct rtw_rxdesc)"); 3012 3013 CASSERT(RTW_DESC_ALIGNMENT % RTW_MAXPKTSEGS == 0, 3014 "RTW_DESC_ALIGNMENT is not a multiple of RTW_MAXPKTSEGS"); 3015 #endif 3016 3017 NEXT_ATTACH_STATE(sc, DETACHED); 3018 3019 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3020 case RTW_TCR_HWVERID_F: 3021 vers = 'F'; 3022 rf_write = rtw_rf_hostwrite; 3023 break; 3024 case RTW_TCR_HWVERID_D: 3025 vers = 'D'; 3026 if (rtw_host_rfio) 3027 rf_write = rtw_rf_hostwrite; 3028 else 3029 rf_write = rtw_rf_macwrite; 3030 break; 3031 default: 3032 vers = '?'; 3033 rf_write = rtw_rf_macwrite; 3034 break; 3035 } 3036 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, vers); 3037 3038 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3039 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3040 0); 3041 3042 if (rc != 0) { 3043 printf("%s: could not allocate hw descriptors, error %d\n", 3044 sc->sc_dev.dv_xname, rc); 3045 goto err; 3046 } 3047 3048 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3049 3050 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3051 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3052 (caddr_t*)&sc->sc_descs, BUS_DMA_COHERENT); 3053 3054 if (rc != 0) { 3055 printf("%s: could not map hw descriptors, error %d\n", 3056 sc->sc_dev.dv_xname, rc); 3057 goto err; 3058 } 3059 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3060 3061 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3062 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3063 3064 if (rc != 0) { 3065 printf("%s: could not create DMA map for hw descriptors, " 3066 "error %d\n", sc->sc_dev.dv_xname, rc); 3067 goto err; 3068 } 3069 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3070 3071 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3072 sizeof(struct rtw_descs), NULL, 0); 3073 3074 if (rc != 0) { 3075 printf("%s: could not load DMA map for hw descriptors, " 3076 "error %d\n", sc->sc_dev.dv_xname, rc); 3077 goto err; 3078 } 3079 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3080 3081 if (rtw_txctl_blk_setup_all(sc) != 0) 3082 goto err; 3083 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3084 3085 rtw_txdesc_blk_setup_all(sc); 3086 3087 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 3088 3089 sc->sc_rxdesc = &sc->sc_descs->hd_rx[0]; 3090 3091 rtw_rxctls_setup(&sc->sc_rxctl[0]); 3092 3093 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3094 stc = &sc->sc_txctl_blk[pri]; 3095 3096 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 3097 &stc->stc_desc[0], stc->stc_ndesc)) != 0) { 3098 printf("%s: could not load DMA map for " 3099 "hw tx descriptors, error %d\n", 3100 sc->sc_dev.dv_xname, rc); 3101 goto err; 3102 } 3103 } 3104 3105 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 3106 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxctl[0], 3107 RTW_RXQLEN)) != 0) { 3108 printf("%s: could not load DMA map for hw rx descriptors, " 3109 "error %d\n", sc->sc_dev.dv_xname, rc); 3110 goto err; 3111 } 3112 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 3113 3114 /* Reset the chip to a known state. */ 3115 if (rtw_reset(sc) != 0) 3116 goto err; 3117 NEXT_ATTACH_STATE(sc, FINISH_RESET); 3118 3119 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 3120 3121 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 3122 sc->sc_flags |= RTW_F_9356SROM; 3123 3124 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 3125 sc->sc_dev.dv_xname) != 0) 3126 goto err; 3127 3128 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 3129 3130 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 3131 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 3132 sc->sc_dev.dv_xname) != 0) { 3133 printf("%s: attach failed, malformed serial ROM\n", 3134 sc->sc_dev.dv_xname); 3135 goto err; 3136 } 3137 3138 RTW_DPRINTF(("%s: CS threshold %u\n", sc->sc_dev.dv_xname, 3139 sc->sc_csthr)); 3140 3141 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 3142 3143 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, rf_write, 3144 sc->sc_flags & RTW_F_DIGPHY); 3145 3146 if (sc->sc_rf == NULL) { 3147 printf("%s: attach failed, could not attach RF\n", 3148 sc->sc_dev.dv_xname); 3149 goto err; 3150 } 3151 3152 #if 0 3153 if (rtw_identify_rf(&sc->sc_regs, &sc->sc_rftype, 3154 sc->sc_dev.dv_xname) != 0) { 3155 printf("%s: attach failed, unknown RF unidentified\n", 3156 sc->sc_dev.dv_xname); 3157 goto err; 3158 } 3159 #endif 3160 3161 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 3162 3163 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 3164 3165 RTW_DPRINTF(("%s: PHY delay %d\n", sc->sc_dev.dv_xname, 3166 sc->sc_phydelay)); 3167 3168 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 3169 rtw_identify_country(&sc->sc_regs, &sc->sc_locale, 3170 sc->sc_dev.dv_xname); 3171 3172 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 3173 sc->sc_dev.dv_xname); 3174 3175 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 3176 sc->sc_dev.dv_xname) != 0) 3177 goto err; 3178 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 3179 3180 rtw_setifprops(&sc->sc_if, sc->sc_dev.dv_xname, (void*)sc); 3181 3182 IFQ_SET_READY(&sc->sc_if.if_snd); 3183 3184 rtw_set80211props(&sc->sc_ic); 3185 3186 /* 3187 * Call MI attach routines. 3188 */ 3189 if_attach(&sc->sc_if); 3190 ieee80211_ifattach(&sc->sc_if); 3191 3192 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 3193 3194 /* possibly we should fill in our own sc_send_prresp, since 3195 * the RTL8180 is probably sending probe responses in ad hoc 3196 * mode. 3197 */ 3198 3199 /* complete initialization */ 3200 ieee80211_media_init(&sc->sc_if, rtw_media_change, rtw_media_status); 3201 callout_init(&sc->sc_scan_ch); 3202 3203 #if NBPFILTER > 0 3204 bpfattach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 3205 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 3206 #endif 3207 3208 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 3209 3210 rtw_init_radiotap(sc); 3211 3212 NEXT_ATTACH_STATE(sc, FINISHED); 3213 3214 return; 3215 err: 3216 rtw_detach(sc); 3217 return; 3218 } 3219 3220 int 3221 rtw_detach(struct rtw_softc *sc) 3222 { 3223 int pri; 3224 3225 switch (sc->sc_attach_state) { 3226 case FINISHED: 3227 rtw_stop(&sc->sc_if, 1); 3228 3229 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 3230 (void*)sc); 3231 callout_stop(&sc->sc_scan_ch); 3232 ieee80211_ifdetach(&sc->sc_if); 3233 if_detach(&sc->sc_if); 3234 break; 3235 case FINISH_ID_STA: 3236 case FINISH_RF_ATTACH: 3237 rtw_rf_destroy(sc->sc_rf); 3238 sc->sc_rf = NULL; 3239 /*FALLTHROUGH*/ 3240 case FINISH_PARSE_SROM: 3241 case FINISH_READ_SROM: 3242 rtw_srom_free(&sc->sc_srom); 3243 /*FALLTHROUGH*/ 3244 case FINISH_RESET: 3245 case FINISH_RXMAPS_CREATE: 3246 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxctl[0], 3247 RTW_RXQLEN); 3248 /*FALLTHROUGH*/ 3249 case FINISH_TXMAPS_CREATE: 3250 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3251 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 3252 sc->sc_txctl_blk[pri].stc_desc, 3253 sc->sc_txctl_blk[pri].stc_ndesc); 3254 } 3255 /*FALLTHROUGH*/ 3256 case FINISH_TXDESCBLK_SETUP: 3257 case FINISH_TXCTLBLK_SETUP: 3258 rtw_txctl_blk_cleanup_all(sc); 3259 /*FALLTHROUGH*/ 3260 case FINISH_DESCMAP_LOAD: 3261 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 3262 /*FALLTHROUGH*/ 3263 case FINISH_DESCMAP_CREATE: 3264 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 3265 /*FALLTHROUGH*/ 3266 case FINISH_DESC_MAP: 3267 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_descs, 3268 sizeof(struct rtw_descs)); 3269 /*FALLTHROUGH*/ 3270 case FINISH_DESC_ALLOC: 3271 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 3272 sc->sc_desc_nsegs); 3273 /*FALLTHROUGH*/ 3274 case DETACHED: 3275 NEXT_ATTACH_STATE(sc, DETACHED); 3276 break; 3277 } 3278 return 0; 3279 } 3280 3281 int 3282 rtw_activate(struct device *self, enum devact act) 3283 { 3284 struct rtw_softc *sc = (struct rtw_softc *)self; 3285 int rc = 0, s; 3286 3287 s = splnet(); 3288 switch (act) { 3289 case DVACT_ACTIVATE: 3290 rc = EOPNOTSUPP; 3291 break; 3292 3293 case DVACT_DEACTIVATE: 3294 if_deactivate(&sc->sc_ic.ic_if); 3295 break; 3296 } 3297 splx(s); 3298 return rc; 3299 } 3300
Indexes created Thu Sep 25 16:09:42 GMT 2025