rtw.c revision 1.96
1 /* $NetBSD: rtw.c,v 1.96 2007/12/16 21:39:33 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005, 2006, 2007 David Young. All rights 4 * reserved. 5 * 6 * Programmed for NetBSD by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of David Young may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 24 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 26 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /* 34 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.96 2007/12/16 21:39:33 dyoung Exp $"); 39 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/sysctl.h> 44 #include <sys/systm.h> 45 #include <sys/callout.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/time.h> 50 #include <sys/types.h> 51 52 #include <machine/endian.h> 53 #include <sys/bus.h> 54 #include <sys/intr.h> /* splnet */ 55 56 #include <uvm/uvm_extern.h> 57 58 #include <net/if.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #include <net80211/ieee80211_netbsd.h> 63 #include <net80211/ieee80211_var.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <dev/ic/rtwreg.h> 71 #include <dev/ic/rtwvar.h> 72 #include <dev/ic/rtwphyio.h> 73 #include <dev/ic/rtwphy.h> 74 75 #include <dev/ic/smc93cx6var.h> 76 77 static int rtw_rfprog_fallback = 0; 78 static int rtw_host_rfio = 0; 79 80 #ifdef RTW_DEBUG 81 int rtw_debug = 0; 82 static int rtw_rxbufs_limit = RTW_RXQLEN; 83 #endif /* RTW_DEBUG */ 84 85 #define NEXT_ATTACH_STATE(sc, state) do { \ 86 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 87 ("%s: attach state %s\n", __func__, #state)); \ 88 sc->sc_attach_state = state; \ 89 } while (0) 90 91 int rtw_dwelltime = 200; /* milliseconds */ 92 static struct ieee80211_cipher rtw_cipher_wep; 93 94 static void rtw_start(struct ifnet *); 95 static void rtw_reset_oactive(struct rtw_softc *); 96 static struct mbuf *rtw_beacon_alloc(struct rtw_softc *, 97 struct ieee80211_node *); 98 static u_int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *); 99 100 static void rtw_io_enable(struct rtw_softc *, uint8_t, int); 101 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 102 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 103 const u_int8_t[IEEE80211_ADDR_LEN]); 104 static void rtw_key_update_end(struct ieee80211com *); 105 static void rtw_key_update_begin(struct ieee80211com *); 106 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 107 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 108 109 static void rtw_led_attach(struct rtw_led_state *, void *); 110 static void rtw_led_init(struct rtw_regs *); 111 static void rtw_led_slowblink(void *); 112 static void rtw_led_fastblink(void *); 113 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 114 115 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 116 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 117 #ifdef RTW_DEBUG 118 static void rtw_dump_rings(struct rtw_softc *sc); 119 static void rtw_print_txdesc(struct rtw_softc *, const char *, 120 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 121 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 122 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 123 #endif /* RTW_DEBUG */ 124 #ifdef RTW_DIAG 125 static void rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln); 126 #endif /* RTW_DIAG */ 127 128 /* 129 * Setup sysctl(3) MIB, hw.rtw.* 130 * 131 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 132 */ 133 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 134 { 135 int rc; 136 const struct sysctlnode *cnode, *rnode; 137 138 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 139 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 140 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 141 goto err; 142 143 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 144 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 145 "Realtek RTL818x 802.11 controls", 146 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 147 goto err; 148 149 #ifdef RTW_DEBUG 150 /* control debugging printfs */ 151 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 152 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 153 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 154 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 155 CTL_CREATE, CTL_EOL)) != 0) 156 goto err; 157 158 /* Limit rx buffers, for simulating resource exhaustion. */ 159 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 160 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 161 "rxbufs_limit", 162 SYSCTL_DESCR("Set rx buffers limit"), 163 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 164 CTL_CREATE, CTL_EOL)) != 0) 165 goto err; 166 167 #endif /* RTW_DEBUG */ 168 /* set fallback RF programming method */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfprog_fallback", 172 SYSCTL_DESCR("Set fallback RF programming method"), 173 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 174 CTL_CREATE, CTL_EOL)) != 0) 175 goto err; 176 177 /* force host to control RF I/O bus */ 178 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 179 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 180 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 181 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 182 CTL_CREATE, CTL_EOL)) != 0) 183 goto err; 184 185 return; 186 err: 187 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 188 } 189 190 static int 191 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 192 { 193 int error, t; 194 struct sysctlnode node; 195 196 node = *rnode; 197 t = *(int*)rnode->sysctl_data; 198 node.sysctl_data = &t; 199 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 200 if (error || newp == NULL) 201 return (error); 202 203 if (t < lower || t > upper) 204 return (EINVAL); 205 206 *(int*)rnode->sysctl_data = t; 207 208 return (0); 209 } 210 211 static int 212 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 213 { 214 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 215 __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 216 } 217 218 static int 219 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 220 { 221 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 222 } 223 224 #ifdef RTW_DEBUG 225 static int 226 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 227 { 228 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 229 0, RTW_DEBUG_MAX); 230 } 231 232 static int 233 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 234 { 235 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 236 0, RTW_RXQLEN); 237 } 238 239 static void 240 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 241 { 242 #define PRINTREG32(sc, reg) \ 243 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 244 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 245 dvname, reg, RTW_READ(regs, reg))) 246 247 #define PRINTREG16(sc, reg) \ 248 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 249 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 250 dvname, reg, RTW_READ16(regs, reg))) 251 252 #define PRINTREG8(sc, reg) \ 253 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 254 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 255 dvname, reg, RTW_READ8(regs, reg))) 256 257 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 258 259 PRINTREG32(regs, RTW_IDR0); 260 PRINTREG32(regs, RTW_IDR1); 261 PRINTREG32(regs, RTW_MAR0); 262 PRINTREG32(regs, RTW_MAR1); 263 PRINTREG32(regs, RTW_TSFTRL); 264 PRINTREG32(regs, RTW_TSFTRH); 265 PRINTREG32(regs, RTW_TLPDA); 266 PRINTREG32(regs, RTW_TNPDA); 267 PRINTREG32(regs, RTW_THPDA); 268 PRINTREG32(regs, RTW_TCR); 269 PRINTREG32(regs, RTW_RCR); 270 PRINTREG32(regs, RTW_TINT); 271 PRINTREG32(regs, RTW_TBDA); 272 PRINTREG32(regs, RTW_ANAPARM); 273 PRINTREG32(regs, RTW_BB); 274 PRINTREG32(regs, RTW_PHYCFG); 275 PRINTREG32(regs, RTW_WAKEUP0L); 276 PRINTREG32(regs, RTW_WAKEUP0H); 277 PRINTREG32(regs, RTW_WAKEUP1L); 278 PRINTREG32(regs, RTW_WAKEUP1H); 279 PRINTREG32(regs, RTW_WAKEUP2LL); 280 PRINTREG32(regs, RTW_WAKEUP2LH); 281 PRINTREG32(regs, RTW_WAKEUP2HL); 282 PRINTREG32(regs, RTW_WAKEUP2HH); 283 PRINTREG32(regs, RTW_WAKEUP3LL); 284 PRINTREG32(regs, RTW_WAKEUP3LH); 285 PRINTREG32(regs, RTW_WAKEUP3HL); 286 PRINTREG32(regs, RTW_WAKEUP3HH); 287 PRINTREG32(regs, RTW_WAKEUP4LL); 288 PRINTREG32(regs, RTW_WAKEUP4LH); 289 PRINTREG32(regs, RTW_WAKEUP4HL); 290 PRINTREG32(regs, RTW_WAKEUP4HH); 291 PRINTREG32(regs, RTW_DK0); 292 PRINTREG32(regs, RTW_DK1); 293 PRINTREG32(regs, RTW_DK2); 294 PRINTREG32(regs, RTW_DK3); 295 PRINTREG32(regs, RTW_RETRYCTR); 296 PRINTREG32(regs, RTW_RDSAR); 297 PRINTREG32(regs, RTW_FER); 298 PRINTREG32(regs, RTW_FEMR); 299 PRINTREG32(regs, RTW_FPSR); 300 PRINTREG32(regs, RTW_FFER); 301 302 /* 16-bit registers */ 303 PRINTREG16(regs, RTW_BRSR); 304 PRINTREG16(regs, RTW_IMR); 305 PRINTREG16(regs, RTW_ISR); 306 PRINTREG16(regs, RTW_BCNITV); 307 PRINTREG16(regs, RTW_ATIMWND); 308 PRINTREG16(regs, RTW_BINTRITV); 309 PRINTREG16(regs, RTW_ATIMTRITV); 310 PRINTREG16(regs, RTW_CRC16ERR); 311 PRINTREG16(regs, RTW_CRC0); 312 PRINTREG16(regs, RTW_CRC1); 313 PRINTREG16(regs, RTW_CRC2); 314 PRINTREG16(regs, RTW_CRC3); 315 PRINTREG16(regs, RTW_CRC4); 316 PRINTREG16(regs, RTW_CWR); 317 318 /* 8-bit registers */ 319 PRINTREG8(regs, RTW_CR); 320 PRINTREG8(regs, RTW_9346CR); 321 PRINTREG8(regs, RTW_CONFIG0); 322 PRINTREG8(regs, RTW_CONFIG1); 323 PRINTREG8(regs, RTW_CONFIG2); 324 PRINTREG8(regs, RTW_MSR); 325 PRINTREG8(regs, RTW_CONFIG3); 326 PRINTREG8(regs, RTW_CONFIG4); 327 PRINTREG8(regs, RTW_TESTR); 328 PRINTREG8(regs, RTW_PSR); 329 PRINTREG8(regs, RTW_SCR); 330 PRINTREG8(regs, RTW_PHYDELAY); 331 PRINTREG8(regs, RTW_CRCOUNT); 332 PRINTREG8(regs, RTW_PHYADDR); 333 PRINTREG8(regs, RTW_PHYDATAW); 334 PRINTREG8(regs, RTW_PHYDATAR); 335 PRINTREG8(regs, RTW_CONFIG5); 336 PRINTREG8(regs, RTW_TPPOLL); 337 338 PRINTREG16(regs, RTW_BSSID16); 339 PRINTREG32(regs, RTW_BSSID32); 340 #undef PRINTREG32 341 #undef PRINTREG16 342 #undef PRINTREG8 343 } 344 #endif /* RTW_DEBUG */ 345 346 void 347 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 348 { 349 struct rtw_regs *regs = &sc->sc_regs; 350 351 uint32_t tcr; 352 tcr = RTW_READ(regs, RTW_TCR); 353 tcr &= ~RTW_TCR_LBK_MASK; 354 if (enable) 355 tcr |= RTW_TCR_LBK_CONT; 356 else 357 tcr |= RTW_TCR_LBK_NORMAL; 358 RTW_WRITE(regs, RTW_TCR, tcr); 359 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 360 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 361 rtw_txdac_enable(sc, !enable); 362 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 363 rtw_set_access(regs, RTW_ACCESS_NONE); 364 } 365 366 #ifdef RTW_DEBUG 367 static const char * 368 rtw_access_string(enum rtw_access access) 369 { 370 switch (access) { 371 case RTW_ACCESS_NONE: 372 return "none"; 373 case RTW_ACCESS_CONFIG: 374 return "config"; 375 case RTW_ACCESS_ANAPARM: 376 return "anaparm"; 377 default: 378 return "unknown"; 379 } 380 } 381 #endif /* RTW_DEBUG */ 382 383 static void 384 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 385 { 386 KASSERT(/* naccess >= RTW_ACCESS_NONE && */ 387 naccess <= RTW_ACCESS_ANAPARM); 388 KASSERT(/* regs->r_access >= RTW_ACCESS_NONE && */ 389 regs->r_access <= RTW_ACCESS_ANAPARM); 390 391 if (naccess == regs->r_access) 392 return; 393 394 switch (naccess) { 395 case RTW_ACCESS_NONE: 396 switch (regs->r_access) { 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 /*FALLTHROUGH*/ 400 case RTW_ACCESS_CONFIG: 401 rtw_config0123_enable(regs, 0); 402 /*FALLTHROUGH*/ 403 case RTW_ACCESS_NONE: 404 break; 405 } 406 break; 407 case RTW_ACCESS_CONFIG: 408 switch (regs->r_access) { 409 case RTW_ACCESS_NONE: 410 rtw_config0123_enable(regs, 1); 411 /*FALLTHROUGH*/ 412 case RTW_ACCESS_CONFIG: 413 break; 414 case RTW_ACCESS_ANAPARM: 415 rtw_anaparm_enable(regs, 0); 416 break; 417 } 418 break; 419 case RTW_ACCESS_ANAPARM: 420 switch (regs->r_access) { 421 case RTW_ACCESS_NONE: 422 rtw_config0123_enable(regs, 1); 423 /*FALLTHROUGH*/ 424 case RTW_ACCESS_CONFIG: 425 rtw_anaparm_enable(regs, 1); 426 /*FALLTHROUGH*/ 427 case RTW_ACCESS_ANAPARM: 428 break; 429 } 430 break; 431 } 432 } 433 434 void 435 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 436 { 437 rtw_set_access1(regs, access); 438 RTW_DPRINTF(RTW_DEBUG_ACCESS, 439 ("%s: access %s -> %s\n", __func__, 440 rtw_access_string(regs->r_access), 441 rtw_access_string(access))); 442 regs->r_access = access; 443 } 444 445 /* 446 * Enable registers, switch register banks. 447 */ 448 void 449 rtw_config0123_enable(struct rtw_regs *regs, int enable) 450 { 451 uint8_t ecr; 452 ecr = RTW_READ8(regs, RTW_9346CR); 453 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 454 if (enable) 455 ecr |= RTW_9346CR_EEM_CONFIG; 456 else { 457 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 458 ecr |= RTW_9346CR_EEM_NORMAL; 459 } 460 RTW_WRITE8(regs, RTW_9346CR, ecr); 461 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 462 } 463 464 /* requires rtw_config0123_enable(, 1) */ 465 void 466 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 467 { 468 uint8_t cfg3; 469 470 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 471 cfg3 |= RTW_CONFIG3_CLKRUNEN; 472 if (enable) 473 cfg3 |= RTW_CONFIG3_PARMEN; 474 else 475 cfg3 &= ~RTW_CONFIG3_PARMEN; 476 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 477 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 478 } 479 480 /* requires rtw_anaparm_enable(, 1) */ 481 void 482 rtw_txdac_enable(struct rtw_softc *sc, int enable) 483 { 484 uint32_t anaparm; 485 struct rtw_regs *regs = &sc->sc_regs; 486 487 anaparm = RTW_READ(regs, RTW_ANAPARM); 488 if (enable) 489 anaparm &= ~RTW_ANAPARM_TXDACOFF; 490 else 491 anaparm |= RTW_ANAPARM_TXDACOFF; 492 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 493 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 494 } 495 496 static inline int 497 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 498 { 499 uint8_t cr; 500 int i; 501 502 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 503 504 RTW_WBR(regs, RTW_CR, RTW_CR); 505 506 for (i = 0; i < 1000; i++) { 507 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 508 RTW_DPRINTF(RTW_DEBUG_RESET, 509 ("%s: reset in %dus\n", dvname, i)); 510 return 0; 511 } 512 RTW_RBR(regs, RTW_CR, RTW_CR); 513 DELAY(10); /* 10us */ 514 } 515 516 printf("%s: reset failed\n", dvname); 517 return ETIMEDOUT; 518 } 519 520 static inline int 521 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 522 { 523 uint32_t tcr; 524 525 /* from Linux driver */ 526 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 527 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK); 528 529 RTW_WRITE(regs, RTW_TCR, tcr); 530 531 RTW_WBW(regs, RTW_CR, RTW_TCR); 532 533 return rtw_chip_reset1(regs, dvname); 534 } 535 536 static int 537 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen) 538 { 539 struct ieee80211_key keycopy; 540 541 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 542 543 keycopy = *k; 544 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 545 546 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, hdrlen); 547 } 548 549 static int 550 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 551 { 552 struct rtw_softc *sc = ic->ic_ifp->if_softc; 553 u_int keyix = k->wk_keyix; 554 555 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix)); 556 557 if (keyix >= IEEE80211_WEP_NKID) 558 return 0; 559 if (k->wk_keylen != 0) 560 sc->sc_flags &= ~RTW_F_DK_VALID; 561 562 return 1; 563 } 564 565 static int 566 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 567 const u_int8_t mac[IEEE80211_ADDR_LEN]) 568 { 569 struct rtw_softc *sc = ic->ic_ifp->if_softc; 570 571 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 572 573 if (k->wk_keyix >= IEEE80211_WEP_NKID) 574 return 0; 575 576 sc->sc_flags &= ~RTW_F_DK_VALID; 577 578 return 1; 579 } 580 581 static void 582 rtw_key_update_begin(struct ieee80211com *ic) 583 { 584 #ifdef RTW_DEBUG 585 struct ifnet *ifp = ic->ic_ifp; 586 struct rtw_softc *sc = ifp->if_softc; 587 #endif 588 589 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 590 } 591 592 static void 593 rtw_key_update_end(struct ieee80211com *ic) 594 { 595 struct ifnet *ifp = ic->ic_ifp; 596 struct rtw_softc *sc = ifp->if_softc; 597 598 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 599 600 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 || 601 (sc->sc_flags & RTW_F_ENABLED) == 0 || 602 (sc->sc_flags & RTW_F_INVALID) != 0) 603 return; 604 605 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 606 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 607 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 608 (ifp->if_flags & IFF_RUNNING) != 0); 609 } 610 611 static inline int 612 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k) 613 { 614 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 615 return 0; 616 617 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) || 618 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13); 619 } 620 621 static void 622 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 623 { 624 uint8_t psr, scr; 625 int i, keylen; 626 struct rtw_regs *regs; 627 union rtw_keys *rk; 628 629 regs = &sc->sc_regs; 630 rk = &sc->sc_keys; 631 632 (void)memset(rk, 0, sizeof(rk)); 633 634 /* Temporarily use software crypto for all keys. */ 635 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 636 if (wk[i].wk_cipher == &rtw_cipher_wep) 637 wk[i].wk_cipher = &ieee80211_cipher_wep; 638 } 639 640 rtw_set_access(regs, RTW_ACCESS_CONFIG); 641 642 psr = RTW_READ8(regs, RTW_PSR); 643 scr = RTW_READ8(regs, RTW_SCR); 644 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 645 646 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 647 goto out; 648 649 for (keylen = i = 0; i < IEEE80211_WEP_NKID; i++) { 650 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i])) 651 continue; 652 if (i == txkey) { 653 keylen = wk[i].wk_keylen; 654 break; 655 } 656 keylen = MAX(keylen, wk[i].wk_keylen); 657 } 658 659 if (keylen == 5) 660 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON; 661 else if (keylen == 13) 662 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON; 663 664 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 665 if (wk[i].wk_keylen != keylen || 666 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 667 continue; 668 /* h/w will decrypt, s/w still strips headers */ 669 wk[i].wk_cipher = &rtw_cipher_wep; 670 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 671 } 672 673 out: 674 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 675 676 bus_space_write_region_stream_4(regs->r_bt, regs->r_bh, 677 RTW_DK0, rk->rk_words, __arraycount(rk->rk_words)); 678 679 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 680 BUS_SPACE_BARRIER_SYNC); 681 682 RTW_WBW(regs, RTW_DK0, RTW_PSR); 683 RTW_WRITE8(regs, RTW_PSR, psr); 684 RTW_WBW(regs, RTW_PSR, RTW_SCR); 685 RTW_WRITE8(regs, RTW_SCR, scr); 686 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 687 rtw_set_access(regs, RTW_ACCESS_NONE); 688 sc->sc_flags |= RTW_F_DK_VALID; 689 } 690 691 static inline int 692 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 693 { 694 int i; 695 uint8_t ecr; 696 697 ecr = RTW_READ8(regs, RTW_9346CR); 698 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 699 RTW_WRITE8(regs, RTW_9346CR, ecr); 700 701 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 702 703 /* wait 25ms for completion */ 704 for (i = 0; i < 250; i++) { 705 ecr = RTW_READ8(regs, RTW_9346CR); 706 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 707 RTW_DPRINTF(RTW_DEBUG_RESET, 708 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 709 return 0; 710 } 711 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 712 DELAY(100); 713 } 714 printf("%s: recall EEPROM failed\n", dvname); 715 return ETIMEDOUT; 716 } 717 718 static inline int 719 rtw_reset(struct rtw_softc *sc) 720 { 721 int rc; 722 uint8_t config1; 723 724 sc->sc_flags &= ~RTW_F_DK_VALID; 725 726 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 727 return rc; 728 729 rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname); 730 731 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 732 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 733 /* TBD turn off maximum power saving? */ 734 735 return 0; 736 } 737 738 static inline int 739 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 740 u_int ndescs) 741 { 742 int i, rc = 0; 743 for (i = 0; i < ndescs; i++) { 744 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 745 0, 0, &descs[i].ts_dmamap); 746 if (rc != 0) 747 break; 748 } 749 return rc; 750 } 751 752 static inline int 753 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 754 u_int ndescs) 755 { 756 int i, rc = 0; 757 for (i = 0; i < ndescs; i++) { 758 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 759 &descs[i].rs_dmamap); 760 if (rc != 0) 761 break; 762 } 763 return rc; 764 } 765 766 static inline void 767 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 768 u_int ndescs) 769 { 770 int i; 771 for (i = 0; i < ndescs; i++) { 772 if (descs[i].rs_dmamap != NULL) 773 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 774 } 775 } 776 777 static inline void 778 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 779 u_int ndescs) 780 { 781 int i; 782 for (i = 0; i < ndescs; i++) { 783 if (descs[i].ts_dmamap != NULL) 784 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 785 } 786 } 787 788 static inline void 789 rtw_srom_free(struct rtw_srom *sr) 790 { 791 sr->sr_size = 0; 792 if (sr->sr_content == NULL) 793 return; 794 free(sr->sr_content, M_DEVBUF); 795 sr->sr_content = NULL; 796 } 797 798 static void 799 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, 800 uint8_t *cs_threshold, enum rtw_rfchipid *rfchipid, uint32_t *rcr) 801 { 802 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 803 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 804 *rcr |= RTW_RCR_ENCS1; 805 *rfchipid = RTW_RFCHIPID_PHILIPS; 806 } 807 808 static int 809 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 810 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 811 const char *dvname) 812 { 813 int i; 814 const char *rfname, *paname; 815 char scratch[sizeof("unknown 0xXX")]; 816 uint16_t srom_version; 817 uint8_t mac[IEEE80211_ADDR_LEN]; 818 819 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 820 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 821 822 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 823 printf("%s: SROM version %d.%d", dvname, 824 srom_version >> 8, srom_version & 0xff); 825 826 if (srom_version <= 0x0101) { 827 printf(" is not understood, limping along with defaults\n"); 828 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 829 return 0; 830 } 831 printf("\n"); 832 833 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 834 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 835 836 RTW_DPRINTF(RTW_DEBUG_ATTACH, 837 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 838 839 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 840 841 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 842 *flags |= RTW_F_ANTDIV; 843 844 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 845 * to be reversed. 846 */ 847 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 848 *flags |= RTW_F_DIGPHY; 849 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 850 *flags |= RTW_F_DFLANTB; 851 852 *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), 853 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 854 855 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0) 856 *flags |= RTW_C_RXWEP_104; 857 858 *flags |= RTW_C_RXWEP_40; /* XXX */ 859 860 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 861 switch (*rfchipid) { 862 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 863 rfname = "GCT GRF5101"; 864 paname = "Winspring WS9901"; 865 break; 866 case RTW_RFCHIPID_MAXIM: 867 rfname = "Maxim MAX2820"; /* guess */ 868 paname = "Maxim MAX2422"; /* guess */ 869 break; 870 case RTW_RFCHIPID_INTERSIL: 871 rfname = "Intersil HFA3873"; /* guess */ 872 paname = "Intersil <unknown>"; 873 break; 874 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 875 rfname = "Philips SA2400A"; 876 paname = "Philips SA2411"; 877 break; 878 case RTW_RFCHIPID_RFMD: 879 /* this is the same front-end as an atw(4)! */ 880 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 881 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 882 "SYN: Silicon Labs Si4126"; /* inferred from 883 * reference driver 884 */ 885 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 886 break; 887 case RTW_RFCHIPID_RESERVED: 888 rfname = paname = "reserved"; 889 break; 890 default: 891 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 892 rfname = paname = scratch; 893 } 894 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 895 896 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 897 case RTW_CONFIG0_GL_USA: 898 case _RTW_CONFIG0_GL_USA: 899 *locale = RTW_LOCALE_USA; 900 break; 901 case RTW_CONFIG0_GL_EUROPE: 902 *locale = RTW_LOCALE_EUROPE; 903 break; 904 case RTW_CONFIG0_GL_JAPAN: 905 *locale = RTW_LOCALE_JAPAN; 906 break; 907 default: 908 *locale = RTW_LOCALE_UNKNOWN; 909 break; 910 } 911 return 0; 912 } 913 914 /* Returns -1 on failure. */ 915 static int 916 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 917 const char *dvname) 918 { 919 int rc; 920 struct seeprom_descriptor sd; 921 uint8_t ecr; 922 923 (void)memset(&sd, 0, sizeof(sd)); 924 925 ecr = RTW_READ8(regs, RTW_9346CR); 926 927 if ((flags & RTW_F_9356SROM) != 0) { 928 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 929 sr->sr_size = 256; 930 sd.sd_chip = C56_66; 931 } else { 932 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 933 sr->sr_size = 128; 934 sd.sd_chip = C46; 935 } 936 937 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 938 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 939 ecr |= RTW_9346CR_EEM_PROGRAM; 940 941 RTW_WRITE8(regs, RTW_9346CR, ecr); 942 943 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 944 945 if (sr->sr_content == NULL) { 946 printf("%s: unable to allocate SROM buffer\n", dvname); 947 return ENOMEM; 948 } 949 950 (void)memset(sr->sr_content, 0, sr->sr_size); 951 952 /* RTL8180 has a single 8-bit register for controlling the 953 * 93cx6 SROM. There is no "ready" bit. The RTL8180 954 * input/output sense is the reverse of read_seeprom's. 955 */ 956 sd.sd_tag = regs->r_bt; 957 sd.sd_bsh = regs->r_bh; 958 sd.sd_regsize = 1; 959 sd.sd_control_offset = RTW_9346CR; 960 sd.sd_status_offset = RTW_9346CR; 961 sd.sd_dataout_offset = RTW_9346CR; 962 sd.sd_CK = RTW_9346CR_EESK; 963 sd.sd_CS = RTW_9346CR_EECS; 964 sd.sd_DI = RTW_9346CR_EEDO; 965 sd.sd_DO = RTW_9346CR_EEDI; 966 /* make read_seeprom enter EEPROM read/write mode */ 967 sd.sd_MS = ecr; 968 sd.sd_RDY = 0; 969 970 /* TBD bus barriers */ 971 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 972 printf("%s: could not read SROM\n", dvname); 973 free(sr->sr_content, M_DEVBUF); 974 sr->sr_content = NULL; 975 return -1; /* XXX */ 976 } 977 978 /* end EEPROM read/write mode */ 979 RTW_WRITE8(regs, RTW_9346CR, 980 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 981 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 982 983 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 984 return rc; 985 986 #ifdef RTW_DEBUG 987 { 988 int i; 989 RTW_DPRINTF(RTW_DEBUG_ATTACH, 990 ("\n%s: serial ROM:\n\t", dvname)); 991 for (i = 0; i < sr->sr_size/2; i++) { 992 if (((i % 8) == 0) && (i != 0)) 993 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 994 RTW_DPRINTF(RTW_DEBUG_ATTACH, 995 (" %04x", sr->sr_content[i])); 996 } 997 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 998 } 999 #endif /* RTW_DEBUG */ 1000 return 0; 1001 } 1002 1003 static void 1004 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 1005 const char *dvname) 1006 { 1007 uint8_t cfg4; 1008 const char *method; 1009 1010 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 1011 1012 switch (rfchipid) { 1013 default: 1014 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 1015 method = "fallback"; 1016 break; 1017 case RTW_RFCHIPID_INTERSIL: 1018 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1019 method = "Intersil"; 1020 break; 1021 case RTW_RFCHIPID_PHILIPS: 1022 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1023 method = "Philips"; 1024 break; 1025 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1026 case RTW_RFCHIPID_RFMD: 1027 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1028 method = "RFMD"; 1029 break; 1030 } 1031 1032 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1033 1034 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1035 1036 RTW_DPRINTF(RTW_DEBUG_INIT, 1037 ("%s: %s RF programming method, %#02x\n", dvname, method, 1038 RTW_READ8(regs, RTW_CONFIG4))); 1039 } 1040 1041 static inline void 1042 rtw_init_channels(enum rtw_locale locale, 1043 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 1044 const char *dvname) 1045 { 1046 int i; 1047 const char *name = NULL; 1048 #define ADD_CHANNEL(_chans, _chan) do { \ 1049 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1050 (*_chans)[_chan].ic_freq = \ 1051 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1052 } while (0) 1053 1054 switch (locale) { 1055 case RTW_LOCALE_USA: /* 1-11 */ 1056 name = "USA"; 1057 for (i = 1; i <= 11; i++) 1058 ADD_CHANNEL(chans, i); 1059 break; 1060 case RTW_LOCALE_JAPAN: /* 1-14 */ 1061 name = "Japan"; 1062 ADD_CHANNEL(chans, 14); 1063 for (i = 1; i <= 14; i++) 1064 ADD_CHANNEL(chans, i); 1065 break; 1066 case RTW_LOCALE_EUROPE: /* 1-13 */ 1067 name = "Europe"; 1068 for (i = 1; i <= 13; i++) 1069 ADD_CHANNEL(chans, i); 1070 break; 1071 default: /* 10-11 allowed by most countries */ 1072 name = "<unknown>"; 1073 for (i = 10; i <= 11; i++) 1074 ADD_CHANNEL(chans, i); 1075 break; 1076 } 1077 printf("%s: Geographic Location %s\n", dvname, name); 1078 #undef ADD_CHANNEL 1079 } 1080 1081 1082 static inline void 1083 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale) 1084 { 1085 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1086 1087 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1088 case RTW_CONFIG0_GL_USA: 1089 case _RTW_CONFIG0_GL_USA: 1090 *locale = RTW_LOCALE_USA; 1091 break; 1092 case RTW_CONFIG0_GL_JAPAN: 1093 *locale = RTW_LOCALE_JAPAN; 1094 break; 1095 case RTW_CONFIG0_GL_EUROPE: 1096 *locale = RTW_LOCALE_EUROPE; 1097 break; 1098 default: 1099 *locale = RTW_LOCALE_UNKNOWN; 1100 break; 1101 } 1102 } 1103 1104 static inline int 1105 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1106 const char *dvname) 1107 { 1108 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1109 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1110 }; 1111 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1112 idr1 = RTW_READ(regs, RTW_IDR1); 1113 1114 (*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7)); 1115 (*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15)); 1116 (*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23)); 1117 (*addr)[3] = __SHIFTOUT(idr0, __BITS(24 ,31)); 1118 1119 (*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7)); 1120 (*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15)); 1121 1122 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1123 printf("%s: could not get mac address, attach failed\n", 1124 dvname); 1125 return ENXIO; 1126 } 1127 1128 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 1129 1130 return 0; 1131 } 1132 1133 static uint8_t 1134 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1135 struct ieee80211_channel *chan) 1136 { 1137 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1138 if (idx < RTW_SR_TXPOWER1 || idx > RTW_SR_TXPOWER14) { 1139 panic("%s: channel %d out of range", __func__, 1140 idx - RTW_SR_TXPOWER1 + 1); 1141 } 1142 return RTW_SR_GET(sr, idx); 1143 } 1144 1145 static void 1146 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1147 { 1148 int pri; 1149 /* nfree: the number of free descriptors in each ring. 1150 * The beacon ring is a special case: I do not let the 1151 * driver use all of the descriptors on the beacon ring. 1152 * The reasons are two-fold: 1153 * 1154 * (1) A BEACON descriptor's OWN bit is (apparently) not 1155 * updated, so the driver cannot easily know if the descriptor 1156 * belongs to it, or if it is racing the NIC. If the NIC 1157 * does not OWN every descriptor, then the driver can safely 1158 * update the descriptors when RTW_TBDA points at tdb_next. 1159 * 1160 * (2) I hope that the NIC will process more than one BEACON 1161 * descriptor in a single beacon interval, since that will 1162 * enable multiple-BSS support. Since the NIC does not 1163 * clear the OWN bit, there is no natural place for it to 1164 * stop processing BEACON desciptors. Maybe it will *not* 1165 * stop processing them! I do not want to chance the NIC 1166 * looping around and around a saturated beacon ring, so 1167 * I will leave one descriptor unOWNed at all times. 1168 */ 1169 u_int nfree[RTW_NTXPRI] = 1170 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, 1171 RTW_NTXDESCBCN - 1}; 1172 1173 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1174 tdb[pri].tdb_nfree = nfree[pri]; 1175 tdb[pri].tdb_next = 0; 1176 } 1177 } 1178 1179 static int 1180 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1181 { 1182 int i; 1183 struct rtw_txsoft *ts; 1184 1185 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1186 SIMPLEQ_INIT(&tsb->tsb_freeq); 1187 for (i = 0; i < tsb->tsb_ndesc; i++) { 1188 ts = &tsb->tsb_desc[i]; 1189 ts->ts_mbuf = NULL; 1190 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1191 } 1192 tsb->tsb_tx_timer = 0; 1193 return 0; 1194 } 1195 1196 static void 1197 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1198 { 1199 int pri; 1200 for (pri = 0; pri < RTW_NTXPRI; pri++) 1201 rtw_txsoft_blk_init(&tsb[pri]); 1202 } 1203 1204 static inline void 1205 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1206 { 1207 KASSERT(nsync <= rdb->rdb_ndesc); 1208 /* sync to end of ring */ 1209 if (desc0 + nsync > rdb->rdb_ndesc) { 1210 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1211 offsetof(struct rtw_descs, hd_rx[desc0]), 1212 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1213 nsync -= (rdb->rdb_ndesc - desc0); 1214 desc0 = 0; 1215 } 1216 1217 KASSERT(desc0 < rdb->rdb_ndesc); 1218 KASSERT(nsync <= rdb->rdb_ndesc); 1219 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1220 1221 /* sync what remains */ 1222 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1223 offsetof(struct rtw_descs, hd_rx[desc0]), 1224 sizeof(struct rtw_rxdesc) * nsync, ops); 1225 } 1226 1227 static void 1228 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1229 { 1230 /* sync to end of ring */ 1231 if (desc0 + nsync > tdb->tdb_ndesc) { 1232 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1233 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1234 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1235 ops); 1236 nsync -= (tdb->tdb_ndesc - desc0); 1237 desc0 = 0; 1238 } 1239 1240 /* sync what remains */ 1241 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1242 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1243 sizeof(struct rtw_txdesc) * nsync, ops); 1244 } 1245 1246 static void 1247 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1248 { 1249 int pri; 1250 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1251 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1252 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1253 } 1254 } 1255 1256 static void 1257 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1258 { 1259 int i; 1260 struct rtw_rxsoft *rs; 1261 1262 for (i = 0; i < RTW_RXQLEN; i++) { 1263 rs = &desc[i]; 1264 if (rs->rs_mbuf == NULL) 1265 continue; 1266 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1267 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1268 bus_dmamap_unload(dmat, rs->rs_dmamap); 1269 m_freem(rs->rs_mbuf); 1270 rs->rs_mbuf = NULL; 1271 } 1272 } 1273 1274 static inline int 1275 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1276 { 1277 int rc; 1278 struct mbuf *m; 1279 1280 MGETHDR(m, M_DONTWAIT, MT_DATA); 1281 if (m == NULL) 1282 return ENOBUFS; 1283 1284 MCLGET(m, M_DONTWAIT); 1285 if ((m->m_flags & M_EXT) == 0) { 1286 m_freem(m); 1287 return ENOBUFS; 1288 } 1289 1290 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1291 1292 if (rs->rs_mbuf != NULL) 1293 bus_dmamap_unload(dmat, rs->rs_dmamap); 1294 1295 rs->rs_mbuf = NULL; 1296 1297 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1298 if (rc != 0) { 1299 m_freem(m); 1300 return -1; 1301 } 1302 1303 rs->rs_mbuf = m; 1304 1305 return 0; 1306 } 1307 1308 static int 1309 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1310 int *ndesc, const char *dvname) 1311 { 1312 int i, rc = 0; 1313 struct rtw_rxsoft *rs; 1314 1315 for (i = 0; i < RTW_RXQLEN; i++) { 1316 rs = &desc[i]; 1317 /* we're in rtw_init, so there should be no mbufs allocated */ 1318 KASSERT(rs->rs_mbuf == NULL); 1319 #ifdef RTW_DEBUG 1320 if (i == rtw_rxbufs_limit) { 1321 printf("%s: TEST hit %d-buffer limit\n", dvname, i); 1322 rc = ENOBUFS; 1323 break; 1324 } 1325 #endif /* RTW_DEBUG */ 1326 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1327 printf("%s: rtw_rxsoft_alloc failed, %d buffers, " 1328 "rc %d\n", dvname, i, rc); 1329 break; 1330 } 1331 } 1332 *ndesc = i; 1333 return rc; 1334 } 1335 1336 static inline void 1337 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1338 int idx, int kick) 1339 { 1340 int is_last = (idx == rdb->rdb_ndesc - 1); 1341 uint32_t ctl, octl, obuf; 1342 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1343 1344 /* sync the mbuf before the descriptor */ 1345 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1346 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1347 1348 obuf = rd->rd_buf; 1349 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1350 1351 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1352 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1353 1354 if (is_last) 1355 ctl |= RTW_RXCTL_EOR; 1356 1357 octl = rd->rd_ctl; 1358 rd->rd_ctl = htole32(ctl); 1359 1360 RTW_DPRINTF( 1361 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1362 : RTW_DEBUG_RECV_DESC, 1363 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1364 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1365 le32toh(rd->rd_ctl))); 1366 1367 /* sync the descriptor */ 1368 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1369 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1370 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1371 } 1372 1373 static void 1374 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1375 { 1376 int i; 1377 struct rtw_rxdesc *rd; 1378 struct rtw_rxsoft *rs; 1379 1380 for (i = 0; i < rdb->rdb_ndesc; i++) { 1381 rd = &rdb->rdb_desc[i]; 1382 rs = &ctl[i]; 1383 rtw_rxdesc_init(rdb, rs, i, kick); 1384 } 1385 } 1386 1387 static void 1388 rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable) 1389 { 1390 struct rtw_regs *regs = &sc->sc_regs; 1391 uint8_t cr; 1392 1393 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1394 enable ? "enable" : "disable", flags)); 1395 1396 cr = RTW_READ8(regs, RTW_CR); 1397 1398 /* XXX reference source does not enable MULRW */ 1399 /* enable PCI Read/Write Multiple */ 1400 cr |= RTW_CR_MULRW; 1401 1402 /* The receive engine will always start at RDSAR. */ 1403 if (enable && (flags & ~cr & RTW_CR_RE)) { 1404 struct rtw_rxdesc_blk *rdb; 1405 rdb = &sc->sc_rxdesc_blk; 1406 rdb->rdb_next = 0; 1407 } 1408 1409 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1410 if (enable) 1411 cr |= flags; 1412 else 1413 cr &= ~flags; 1414 RTW_WRITE8(regs, RTW_CR, cr); 1415 RTW_SYNC(regs, RTW_CR, RTW_CR); 1416 1417 #ifdef RTW_DIAG 1418 if (cr & RTW_CR_TE) 1419 rtw_txring_fixup(sc, __func__, __LINE__); 1420 #endif 1421 } 1422 1423 static void 1424 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1425 { 1426 #define IS_BEACON(__fc0) \ 1427 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1428 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1429 1430 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1431 * hardware -> net80211 1432 */ 1433 u_int next, nproc = 0; 1434 int hwrate, len, rate, rssi, sq; 1435 uint32_t hrssi, hstat, htsfth, htsftl; 1436 struct rtw_rxdesc *rd; 1437 struct rtw_rxsoft *rs; 1438 struct rtw_rxdesc_blk *rdb; 1439 struct mbuf *m; 1440 struct ifnet *ifp = &sc->sc_if; 1441 1442 struct ieee80211_node *ni; 1443 struct ieee80211_frame_min *wh; 1444 1445 rdb = &sc->sc_rxdesc_blk; 1446 1447 for (next = rdb->rdb_next; ; next = rdb->rdb_next) { 1448 KASSERT(next < rdb->rdb_ndesc); 1449 1450 rtw_rxdescs_sync(rdb, next, 1, 1451 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1452 rd = &rdb->rdb_desc[next]; 1453 rs = &sc->sc_rxsoft[next]; 1454 1455 hstat = le32toh(rd->rd_stat); 1456 hrssi = le32toh(rd->rd_rssi); 1457 htsfth = le32toh(rd->rd_tsfth); 1458 htsftl = le32toh(rd->rd_tsftl); 1459 1460 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1461 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1462 __func__, next, hstat, hrssi, htsfth, htsftl)); 1463 1464 ++nproc; 1465 1466 /* still belongs to NIC */ 1467 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1468 rtw_rxdescs_sync(rdb, next, 1, BUS_DMASYNC_PREREAD); 1469 break; 1470 } 1471 1472 /* ieee80211_input() might reset the receive engine 1473 * (e.g. by indirectly calling rtw_tune()), so save 1474 * the next pointer here and retrieve it again on 1475 * the next round. 1476 */ 1477 rdb->rdb_next = (next + 1) % rdb->rdb_ndesc; 1478 1479 #ifdef RTW_DEBUG 1480 #define PRINTSTAT(flag) do { \ 1481 if ((hstat & flag) != 0) { \ 1482 printf("%s" #flag, delim); \ 1483 delim = ","; \ 1484 } \ 1485 } while (0) 1486 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1487 const char *delim = "<"; 1488 printf("%s: ", sc->sc_dev.dv_xname); 1489 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1490 printf("status %08x", hstat); 1491 PRINTSTAT(RTW_RXSTAT_SPLCP); 1492 PRINTSTAT(RTW_RXSTAT_MAR); 1493 PRINTSTAT(RTW_RXSTAT_PAR); 1494 PRINTSTAT(RTW_RXSTAT_BAR); 1495 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1496 PRINTSTAT(RTW_RXSTAT_CRC32); 1497 PRINTSTAT(RTW_RXSTAT_ICV); 1498 printf(">, "); 1499 } 1500 } 1501 #endif /* RTW_DEBUG */ 1502 1503 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1504 printf("%s: DMA error/FIFO overflow %08" PRIx32 ", " 1505 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1506 hstat, next); 1507 ifp->if_ierrors++; 1508 goto next; 1509 } 1510 1511 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); 1512 if (len < IEEE80211_MIN_LEN) { 1513 sc->sc_ic.ic_stats.is_rx_tooshort++; 1514 goto next; 1515 } 1516 KASSERT(len <= rs->rs_mbuf->m_pkthdr.len); 1517 KASSERT(len <= rs->rs_mbuf->m_len); 1518 1519 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); 1520 if (hwrate >= __arraycount(ratetbl)) { 1521 printf("%s: unknown rate #%" __PRIuBITS "\n", 1522 sc->sc_dev.dv_xname, 1523 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); 1524 ifp->if_ierrors++; 1525 goto next; 1526 } 1527 rate = ratetbl[hwrate]; 1528 1529 #ifdef RTW_DEBUG 1530 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1531 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1532 (rate * 5) % 10, htsfth, htsftl)); 1533 #endif /* RTW_DEBUG */ 1534 1535 /* if bad flags, skip descriptor */ 1536 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1537 printf("%s: too many rx segments, " 1538 "next=%d, %08" PRIx32 "\n", 1539 sc->sc_dev.dv_xname, next, hstat); 1540 goto next; 1541 } 1542 1543 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1544 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1545 1546 m = rs->rs_mbuf; 1547 1548 /* if temporarily out of memory, re-use mbuf */ 1549 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1550 case 0: 1551 break; 1552 case ENOBUFS: 1553 printf("%s: rtw_rxsoft_alloc(, %d) failed, " 1554 "dropping packet\n", sc->sc_dev.dv_xname, next); 1555 goto next; 1556 default: 1557 /* XXX shorten rx ring, instead? */ 1558 panic("%s: could not load DMA map\n", 1559 sc->sc_dev.dv_xname); 1560 } 1561 1562 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ); 1563 1564 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1565 rssi = UINT8_MAX - sq; 1566 else { 1567 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); 1568 /* TBD find out each front-end's LNA gain in the 1569 * front-end's units 1570 */ 1571 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1572 rssi |= 0x80; 1573 } 1574 1575 /* Note well: now we cannot recycle the rs_mbuf unless 1576 * we restore its original length. 1577 */ 1578 m->m_pkthdr.rcvif = ifp; 1579 m->m_pkthdr.len = m->m_len = len; 1580 1581 wh = mtod(m, struct ieee80211_frame_min *); 1582 1583 if (!IS_BEACON(wh->i_fc[0])) 1584 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1585 1586 sc->sc_tsfth = htsfth; 1587 1588 #ifdef RTW_DEBUG 1589 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 1590 (IFF_DEBUG|IFF_LINK2)) { 1591 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1592 rate, rssi); 1593 } 1594 #endif /* RTW_DEBUG */ 1595 1596 #if NBPFILTER > 0 1597 if (sc->sc_radiobpf != NULL) { 1598 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1599 1600 rr->rr_tsft = 1601 htole64(((uint64_t)htsfth << 32) | htsftl); 1602 1603 rr->rr_flags = IEEE80211_RADIOTAP_F_FCS; 1604 1605 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1606 rr->rr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1607 if ((hstat & RTW_RXSTAT_CRC32) != 0) 1608 rr->rr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 1609 1610 rr->rr_rate = rate; 1611 1612 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1613 rr->rr_u.u_philips.p_antsignal = rssi; 1614 else { 1615 rr->rr_u.u_other.o_antsignal = rssi; 1616 rr->rr_u.u_other.o_barker_lock = 1617 htole16(UINT8_MAX - sq); 1618 } 1619 1620 bpf_mtap2(sc->sc_radiobpf, rr, 1621 sizeof(sc->sc_rxtapu), m); 1622 } 1623 #endif /* NBPFILTER > 0 */ 1624 1625 if ((hstat & RTW_RXSTAT_RES) != 0) { 1626 m_freem(m); 1627 goto next; 1628 } 1629 1630 /* CRC is included with the packet; trim it off. */ 1631 m_adj(m, -IEEE80211_CRC_LEN); 1632 1633 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1634 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1635 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1636 ieee80211_free_node(ni); 1637 next: 1638 rtw_rxdesc_init(rdb, rs, next, 0); 1639 } 1640 #undef IS_BEACON 1641 } 1642 1643 static void 1644 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1645 struct rtw_txsoft *ts) 1646 { 1647 struct mbuf *m; 1648 struct ieee80211_node *ni; 1649 1650 m = ts->ts_mbuf; 1651 ni = ts->ts_ni; 1652 KASSERT(m != NULL); 1653 KASSERT(ni != NULL); 1654 ts->ts_mbuf = NULL; 1655 ts->ts_ni = NULL; 1656 1657 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1658 BUS_DMASYNC_POSTWRITE); 1659 bus_dmamap_unload(dmat, ts->ts_dmamap); 1660 m_freem(m); 1661 ieee80211_free_node(ni); 1662 } 1663 1664 static void 1665 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1666 struct rtw_txsoft_blk *tsb) 1667 { 1668 struct rtw_txsoft *ts; 1669 1670 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1671 rtw_txsoft_release(dmat, ic, ts); 1672 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1673 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1674 } 1675 tsb->tsb_tx_timer = 0; 1676 } 1677 1678 static inline void 1679 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1680 struct rtw_txsoft *ts, int ndesc) 1681 { 1682 uint32_t hstat; 1683 int data_retry, rts_retry; 1684 struct rtw_txdesc *tdn; 1685 const char *condstring; 1686 struct ifnet *ifp = &sc->sc_if; 1687 1688 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1689 1690 tdb->tdb_nfree += ndesc; 1691 1692 tdn = &tdb->tdb_desc[ts->ts_last]; 1693 1694 hstat = le32toh(tdn->td_stat); 1695 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1696 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); 1697 1698 ifp->if_collisions += rts_retry + data_retry; 1699 1700 if ((hstat & RTW_TXSTAT_TOK) != 0) 1701 condstring = "ok"; 1702 else { 1703 ifp->if_oerrors++; 1704 condstring = "error"; 1705 } 1706 1707 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1708 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1709 sc->sc_dev.dv_xname, ts, ts->ts_first, ts->ts_last, 1710 condstring, rts_retry, data_retry)); 1711 } 1712 1713 static void 1714 rtw_reset_oactive(struct rtw_softc *sc) 1715 { 1716 short oflags; 1717 int pri; 1718 struct rtw_txsoft_blk *tsb; 1719 struct rtw_txdesc_blk *tdb; 1720 oflags = sc->sc_if.if_flags; 1721 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1722 tsb = &sc->sc_txsoft_blk[pri]; 1723 tdb = &sc->sc_txdesc_blk[pri]; 1724 if (!SIMPLEQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0) 1725 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1726 } 1727 if (oflags != sc->sc_if.if_flags) { 1728 DPRINTF(sc, RTW_DEBUG_OACTIVE, 1729 ("%s: reset OACTIVE\n", __func__)); 1730 } 1731 } 1732 1733 /* Collect transmitted packets. */ 1734 static void 1735 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1736 struct rtw_txdesc_blk *tdb, int force) 1737 { 1738 int ndesc; 1739 struct rtw_txsoft *ts; 1740 1741 #ifdef RTW_DEBUG 1742 rtw_dump_rings(sc); 1743 #endif 1744 1745 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1746 /* If we're clearing a failed transmission, only clear 1747 up to the last packet the hardware has processed. */ 1748 if (ts->ts_first == rtw_txring_next(&sc->sc_regs, tdb)) 1749 break; 1750 1751 ndesc = 1 + ts->ts_last - ts->ts_first; 1752 if (ts->ts_last < ts->ts_first) 1753 ndesc += tdb->tdb_ndesc; 1754 1755 KASSERT(ndesc > 0); 1756 1757 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1758 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1759 1760 if (force) { 1761 int next; 1762 #ifdef RTW_DIAG 1763 printf("%s: clearing packet, stats", __func__); 1764 #endif 1765 for (next = ts->ts_first; ; 1766 next = RTW_NEXT_IDX(tdb, next)) { 1767 #ifdef RTW_DIAG 1768 printf(" %" PRIx32 "/%" PRIx32 "/%" PRIx32 "/%" PRIu32 "/%" PRIx32, le32toh(tdb->tdb_desc[next].td_stat), le32toh(tdb->tdb_desc[next].td_ctl1), le32toh(tdb->tdb_desc[next].td_buf), le32toh(tdb->tdb_desc[next].td_len), le32toh(tdb->tdb_desc[next].td_next)); 1769 #endif 1770 tdb->tdb_desc[next].td_stat &= 1771 ~htole32(RTW_TXSTAT_OWN); 1772 if (next == ts->ts_last) 1773 break; 1774 } 1775 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1776 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1777 #ifdef RTW_DIAG 1778 next = RTW_NEXT_IDX(tdb, next); 1779 printf(" -> end %u stat %" PRIx32 ", was %u\n", next, 1780 le32toh(tdb->tdb_desc[next].td_stat), 1781 rtw_txring_next(&sc->sc_regs, tdb)); 1782 #endif 1783 } else if ((tdb->tdb_desc[ts->ts_last].td_stat & 1784 htole32(RTW_TXSTAT_OWN)) != 0) { 1785 rtw_txdescs_sync(tdb, ts->ts_last, 1, 1786 BUS_DMASYNC_PREREAD); 1787 break; 1788 } 1789 1790 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1791 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1792 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1793 } 1794 1795 /* no more pending transmissions, cancel watchdog */ 1796 if (ts == NULL) 1797 tsb->tsb_tx_timer = 0; 1798 rtw_reset_oactive(sc); 1799 } 1800 1801 static void 1802 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1803 { 1804 int pri; 1805 struct rtw_txsoft_blk *tsb; 1806 struct rtw_txdesc_blk *tdb; 1807 struct ifnet *ifp = &sc->sc_if; 1808 1809 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1810 tsb = &sc->sc_txsoft_blk[pri]; 1811 tdb = &sc->sc_txdesc_blk[pri]; 1812 rtw_collect_txring(sc, tsb, tdb, 0); 1813 } 1814 1815 if ((isr & RTW_INTR_TX) != 0) 1816 rtw_start(ifp); 1817 1818 return; 1819 } 1820 1821 static void 1822 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1823 { 1824 u_int next; 1825 uint32_t tsfth, tsftl; 1826 struct ieee80211com *ic; 1827 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN]; 1828 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN]; 1829 struct mbuf *m; 1830 1831 tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH); 1832 tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1833 1834 if ((isr & (RTW_INTR_TBDOK|RTW_INTR_TBDER)) != 0) { 1835 next = rtw_txring_next(&sc->sc_regs, tdb); 1836 RTW_DPRINTF(RTW_DEBUG_BEACON, 1837 ("%s: beacon ring %sprocessed, isr = %#04" PRIx16 1838 ", next %u expected %u, %" PRIu64 "\n", __func__, 1839 (next == tdb->tdb_next) ? "" : "un", isr, next, 1840 tdb->tdb_next, (uint64_t)tsfth << 32 | tsftl)); 1841 if ((RTW_READ8(&sc->sc_regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0) 1842 rtw_collect_txring(sc, tsb, tdb, 1); 1843 } 1844 /* Start beacon transmission. */ 1845 1846 if ((isr & RTW_INTR_BCNINT) != 0 && 1847 sc->sc_ic.ic_state == IEEE80211_S_RUN && 1848 SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) { 1849 RTW_DPRINTF(RTW_DEBUG_BEACON, 1850 ("%s: beacon prep. time, isr = %#04" PRIx16 1851 ", %16" PRIu64 "\n", __func__, isr, 1852 (uint64_t)tsfth << 32 | tsftl)); 1853 ic = &sc->sc_ic; 1854 m = rtw_beacon_alloc(sc, ic->ic_bss); 1855 1856 if (m == NULL) { 1857 printf("%s: could not allocate beacon\n", 1858 sc->sc_dev.dv_xname); 1859 return; 1860 } 1861 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss); 1862 IF_ENQUEUE(&sc->sc_beaconq, m); 1863 rtw_start(&sc->sc_if); 1864 } 1865 } 1866 1867 static void 1868 rtw_intr_atim(struct rtw_softc *sc) 1869 { 1870 /* TBD */ 1871 return; 1872 } 1873 1874 #ifdef RTW_DEBUG 1875 static void 1876 rtw_dump_rings(struct rtw_softc *sc) 1877 { 1878 struct rtw_txdesc_blk *tdb; 1879 struct rtw_rxdesc *rd; 1880 struct rtw_rxdesc_blk *rdb; 1881 int desc, pri; 1882 1883 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1884 return; 1885 1886 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1887 tdb = &sc->sc_txdesc_blk[pri]; 1888 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1889 tdb->tdb_ndesc, tdb->tdb_nfree); 1890 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1891 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1892 } 1893 1894 rdb = &sc->sc_rxdesc_blk; 1895 1896 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1897 rd = &rdb->rdb_desc[desc]; 1898 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1899 "rsvd1/tsfth %08x\n", __func__, 1900 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1901 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1902 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1903 } 1904 } 1905 #endif /* RTW_DEBUG */ 1906 1907 static void 1908 rtw_hwring_setup(struct rtw_softc *sc) 1909 { 1910 int pri; 1911 struct rtw_regs *regs = &sc->sc_regs; 1912 struct rtw_txdesc_blk *tdb; 1913 1914 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_basereg = RTW_TLPDA; 1915 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_base = RTW_RING_BASE(sc, hd_txlo); 1916 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_basereg = RTW_TNPDA; 1917 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_base = RTW_RING_BASE(sc, hd_txmd); 1918 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_basereg = RTW_THPDA; 1919 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_base = RTW_RING_BASE(sc, hd_txhi); 1920 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_basereg = RTW_TBDA; 1921 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_base = RTW_RING_BASE(sc, hd_bcn); 1922 1923 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1924 tdb = &sc->sc_txdesc_blk[pri]; 1925 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base); 1926 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1927 ("%s: reg[tdb->tdb_basereg] <- %" PRIxPTR "\n", __func__, 1928 (uintptr_t)tdb->tdb_base)); 1929 } 1930 1931 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1932 1933 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1934 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1935 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1936 1937 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1938 1939 } 1940 1941 static int 1942 rtw_swring_setup(struct rtw_softc *sc) 1943 { 1944 int rc; 1945 struct rtw_rxdesc_blk *rdb; 1946 1947 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1948 1949 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1950 1951 rdb = &sc->sc_rxdesc_blk; 1952 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1953 sc->sc_dev.dv_xname)) != 0 && rdb->rdb_ndesc == 0) { 1954 printf("%s: could not allocate rx buffers\n", 1955 sc->sc_dev.dv_xname); 1956 return rc; 1957 } 1958 1959 rdb = &sc->sc_rxdesc_blk; 1960 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1961 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1962 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1963 rdb->rdb_next = 0; 1964 1965 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1966 return 0; 1967 } 1968 1969 static void 1970 rtw_txdesc_blk_init(struct rtw_txdesc_blk *tdb) 1971 { 1972 int i; 1973 1974 (void)memset(tdb->tdb_desc, 0, 1975 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 1976 for (i = 0; i < tdb->tdb_ndesc; i++) 1977 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 1978 } 1979 1980 static u_int 1981 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb) 1982 { 1983 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) / 1984 sizeof(struct rtw_txdesc); 1985 } 1986 1987 #ifdef RTW_DIAG 1988 static void 1989 rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln) 1990 { 1991 int pri; 1992 u_int next; 1993 struct rtw_txdesc_blk *tdb; 1994 struct rtw_regs *regs = &sc->sc_regs; 1995 1996 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1997 int i; 1998 tdb = &sc->sc_txdesc_blk[pri]; 1999 next = rtw_txring_next(regs, tdb); 2000 if (tdb->tdb_next == next) 2001 continue; 2002 for (i = 0; next != tdb->tdb_next; 2003 next = RTW_NEXT_IDX(tdb, next), i++) { 2004 if ((tdb->tdb_desc[next].td_stat & htole32(RTW_TXSTAT_OWN)) == 0) 2005 break; 2006 } 2007 printf("%s:%d: tx-ring %d expected next %u, read %u+%d -> %s\n", fn, 2008 ln, pri, tdb->tdb_next, next, i, tdb->tdb_next == next ? "okay" : "BAD"); 2009 if (tdb->tdb_next == next) 2010 continue; 2011 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1); 2012 } 2013 } 2014 #endif 2015 2016 static void 2017 rtw_txdescs_reset(struct rtw_softc *sc) 2018 { 2019 int pri; 2020 struct rtw_txsoft_blk *tsb; 2021 struct rtw_txdesc_blk *tdb; 2022 2023 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2024 tsb = &sc->sc_txsoft_blk[pri]; 2025 tdb = &sc->sc_txdesc_blk[pri]; 2026 rtw_collect_txring(sc, tsb, tdb, 1); 2027 #ifdef RTW_DIAG 2028 if (!SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 2029 printf("%s: packets left in ring %d\n", __func__, pri); 2030 #endif 2031 } 2032 } 2033 2034 static void 2035 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 2036 { 2037 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 2038 2039 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: cleaning up xmit, isr %" PRIx16 2040 "\n", sc->sc_dev.dv_xname, isr)); 2041 2042 #ifdef RTW_DEBUG 2043 rtw_dump_rings(sc); 2044 #endif /* RTW_DEBUG */ 2045 2046 /* Collect tx'd packets. XXX let's hope this stops the transmit 2047 * timeouts. 2048 */ 2049 rtw_txdescs_reset(sc); 2050 2051 #ifdef RTW_DEBUG 2052 rtw_dump_rings(sc); 2053 #endif /* RTW_DEBUG */ 2054 } 2055 2056 static inline void 2057 rtw_suspend_ticks(struct rtw_softc *sc) 2058 { 2059 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2060 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 2061 sc->sc_do_tick = 0; 2062 } 2063 2064 static inline void 2065 rtw_resume_ticks(struct rtw_softc *sc) 2066 { 2067 uint32_t tsftrl0, tsftrl1, next_tick; 2068 2069 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2070 2071 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2072 next_tick = tsftrl1 + 1000000; 2073 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 2074 2075 sc->sc_do_tick = 1; 2076 2077 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2078 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 2079 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 2080 } 2081 2082 static void 2083 rtw_intr_timeout(struct rtw_softc *sc) 2084 { 2085 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 2086 if (sc->sc_do_tick) 2087 rtw_resume_ticks(sc); 2088 return; 2089 } 2090 2091 int 2092 rtw_intr(void *arg) 2093 { 2094 int i; 2095 struct rtw_softc *sc = arg; 2096 struct rtw_regs *regs = &sc->sc_regs; 2097 uint16_t isr; 2098 struct ifnet *ifp = &sc->sc_if; 2099 2100 /* 2101 * If the interface isn't running, the interrupt couldn't 2102 * possibly have come from us. 2103 */ 2104 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 2105 (ifp->if_flags & IFF_RUNNING) == 0 || 2106 !device_is_active(&sc->sc_dev)) { 2107 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 2108 return (0); 2109 } 2110 2111 for (i = 0; i < 10; i++) { 2112 isr = RTW_READ16(regs, RTW_ISR); 2113 2114 RTW_WRITE16(regs, RTW_ISR, isr); 2115 RTW_WBR(regs, RTW_ISR, RTW_ISR); 2116 2117 if (sc->sc_intr_ack != NULL) 2118 (*sc->sc_intr_ack)(regs); 2119 2120 if (isr == 0) 2121 break; 2122 2123 #ifdef RTW_DEBUG 2124 #define PRINTINTR(flag) do { \ 2125 if ((isr & flag) != 0) { \ 2126 printf("%s" #flag, delim); \ 2127 delim = ","; \ 2128 } \ 2129 } while (0) 2130 2131 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 2132 const char *delim = "<"; 2133 2134 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 2135 2136 PRINTINTR(RTW_INTR_TXFOVW); 2137 PRINTINTR(RTW_INTR_TIMEOUT); 2138 PRINTINTR(RTW_INTR_BCNINT); 2139 PRINTINTR(RTW_INTR_ATIMINT); 2140 PRINTINTR(RTW_INTR_TBDER); 2141 PRINTINTR(RTW_INTR_TBDOK); 2142 PRINTINTR(RTW_INTR_THPDER); 2143 PRINTINTR(RTW_INTR_THPDOK); 2144 PRINTINTR(RTW_INTR_TNPDER); 2145 PRINTINTR(RTW_INTR_TNPDOK); 2146 PRINTINTR(RTW_INTR_RXFOVW); 2147 PRINTINTR(RTW_INTR_RDU); 2148 PRINTINTR(RTW_INTR_TLPDER); 2149 PRINTINTR(RTW_INTR_TLPDOK); 2150 PRINTINTR(RTW_INTR_RER); 2151 PRINTINTR(RTW_INTR_ROK); 2152 2153 printf(">\n"); 2154 } 2155 #undef PRINTINTR 2156 #endif /* RTW_DEBUG */ 2157 2158 if ((isr & RTW_INTR_RX) != 0) 2159 rtw_intr_rx(sc, isr); 2160 if ((isr & RTW_INTR_TX) != 0) 2161 rtw_intr_tx(sc, isr); 2162 if ((isr & RTW_INTR_BEACON) != 0) 2163 rtw_intr_beacon(sc, isr); 2164 if ((isr & RTW_INTR_ATIMINT) != 0) 2165 rtw_intr_atim(sc); 2166 if ((isr & RTW_INTR_IOERROR) != 0) 2167 rtw_intr_ioerror(sc, isr); 2168 if ((isr & RTW_INTR_TIMEOUT) != 0) 2169 rtw_intr_timeout(sc); 2170 } 2171 2172 return 1; 2173 } 2174 2175 /* Must be called at splnet. */ 2176 static void 2177 rtw_stop(struct ifnet *ifp, int disable) 2178 { 2179 int pri; 2180 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2181 struct ieee80211com *ic = &sc->sc_ic; 2182 struct rtw_regs *regs = &sc->sc_regs; 2183 2184 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2185 return; 2186 2187 rtw_suspend_ticks(sc); 2188 2189 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2190 2191 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 2192 /* Disable interrupts. */ 2193 RTW_WRITE16(regs, RTW_IMR, 0); 2194 2195 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2196 2197 /* Stop the transmit and receive processes. First stop DMA, 2198 * then disable receiver and transmitter. 2199 */ 2200 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2201 2202 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2203 2204 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2205 } 2206 2207 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2208 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2209 &sc->sc_txsoft_blk[pri]); 2210 } 2211 2212 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2213 2214 if (disable) 2215 rtw_disable(sc); 2216 2217 /* Mark the interface as not running. Cancel the watchdog timer. */ 2218 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2219 ifp->if_timer = 0; 2220 2221 return; 2222 } 2223 2224 const char * 2225 rtw_pwrstate_string(enum rtw_pwrstate power) 2226 { 2227 switch (power) { 2228 case RTW_ON: 2229 return "on"; 2230 case RTW_SLEEP: 2231 return "sleep"; 2232 case RTW_OFF: 2233 return "off"; 2234 default: 2235 return "unknown"; 2236 } 2237 } 2238 2239 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2240 * reference driver, plus a magic Maxim "ON" value that comes from 2241 * the Realtek document "Windows PG for Rtl8180." 2242 */ 2243 static void 2244 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2245 int before_rf, int digphy) 2246 { 2247 uint32_t anaparm; 2248 2249 anaparm = RTW_READ(regs, RTW_ANAPARM); 2250 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2251 2252 switch (power) { 2253 case RTW_OFF: 2254 if (before_rf) 2255 return; 2256 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2257 anaparm |= RTW_ANAPARM_TXDACOFF; 2258 break; 2259 case RTW_SLEEP: 2260 if (!before_rf) 2261 return; 2262 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2263 anaparm |= RTW_ANAPARM_TXDACOFF; 2264 break; 2265 case RTW_ON: 2266 if (!before_rf) 2267 return; 2268 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2269 break; 2270 } 2271 RTW_DPRINTF(RTW_DEBUG_PWR, 2272 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2273 __func__, rtw_pwrstate_string(power), 2274 (before_rf) ? "before" : "after", anaparm)); 2275 2276 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2277 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2278 } 2279 2280 /* XXX I am using the RFMD settings gleaned from the reference 2281 * driver. They agree 2282 */ 2283 static void 2284 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2285 int before_rf, int digphy) 2286 { 2287 uint32_t anaparm; 2288 2289 anaparm = RTW_READ(regs, RTW_ANAPARM); 2290 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2291 2292 switch (power) { 2293 case RTW_OFF: 2294 if (before_rf) 2295 return; 2296 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2297 anaparm |= RTW_ANAPARM_TXDACOFF; 2298 break; 2299 case RTW_SLEEP: 2300 if (!before_rf) 2301 return; 2302 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2303 anaparm |= RTW_ANAPARM_TXDACOFF; 2304 break; 2305 case RTW_ON: 2306 if (!before_rf) 2307 return; 2308 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2309 break; 2310 } 2311 RTW_DPRINTF(RTW_DEBUG_PWR, 2312 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2313 __func__, rtw_pwrstate_string(power), 2314 (before_rf) ? "before" : "after", anaparm)); 2315 2316 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2317 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2318 } 2319 2320 static void 2321 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2322 int before_rf, int digphy) 2323 { 2324 uint32_t anaparm; 2325 2326 anaparm = RTW_READ(regs, RTW_ANAPARM); 2327 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2328 2329 switch (power) { 2330 case RTW_OFF: 2331 if (before_rf) 2332 return; 2333 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2334 anaparm |= RTW_ANAPARM_TXDACOFF; 2335 break; 2336 case RTW_SLEEP: 2337 if (!before_rf) 2338 return; 2339 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2340 anaparm |= RTW_ANAPARM_TXDACOFF; 2341 break; 2342 case RTW_ON: 2343 if (!before_rf) 2344 return; 2345 if (digphy) { 2346 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2347 /* XXX guess */ 2348 anaparm |= RTW_ANAPARM_TXDACOFF; 2349 } else 2350 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2351 break; 2352 } 2353 RTW_DPRINTF(RTW_DEBUG_PWR, 2354 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2355 __func__, rtw_pwrstate_string(power), 2356 (before_rf) ? "before" : "after", anaparm)); 2357 2358 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2359 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2360 } 2361 2362 static void 2363 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2364 int digphy) 2365 { 2366 struct rtw_regs *regs = &sc->sc_regs; 2367 2368 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2369 2370 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2371 2372 rtw_set_access(regs, RTW_ACCESS_NONE); 2373 2374 return; 2375 } 2376 2377 static int 2378 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2379 { 2380 int rc; 2381 2382 RTW_DPRINTF(RTW_DEBUG_PWR, 2383 ("%s: %s->%s\n", __func__, 2384 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2385 2386 if (sc->sc_pwrstate == power) 2387 return 0; 2388 2389 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2390 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2391 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2392 2393 switch (power) { 2394 case RTW_ON: 2395 /* TBD set LEDs */ 2396 break; 2397 case RTW_SLEEP: 2398 /* TBD */ 2399 break; 2400 case RTW_OFF: 2401 /* TBD */ 2402 break; 2403 } 2404 if (rc == 0) 2405 sc->sc_pwrstate = power; 2406 else 2407 sc->sc_pwrstate = RTW_OFF; 2408 return rc; 2409 } 2410 2411 static int 2412 rtw_tune(struct rtw_softc *sc) 2413 { 2414 struct ieee80211com *ic = &sc->sc_ic; 2415 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 2416 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 2417 u_int chan; 2418 int rc; 2419 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2420 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2421 2422 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2423 if (chan == IEEE80211_CHAN_ANY) 2424 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 2425 2426 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2427 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2428 2429 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2430 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2431 2432 if (chan == sc->sc_cur_chan) { 2433 RTW_DPRINTF(RTW_DEBUG_TUNE, 2434 ("%s: already tuned chan #%d\n", __func__, chan)); 2435 return 0; 2436 } 2437 2438 rtw_suspend_ticks(sc); 2439 2440 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2441 2442 /* TBD wait for Tx to complete */ 2443 2444 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2445 2446 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2447 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr, 2448 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) { 2449 /* XXX condition on powersaving */ 2450 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2451 } 2452 2453 sc->sc_cur_chan = chan; 2454 2455 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2456 2457 rtw_resume_ticks(sc); 2458 2459 return rc; 2460 } 2461 2462 void 2463 rtw_disable(struct rtw_softc *sc) 2464 { 2465 int rc; 2466 2467 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2468 return; 2469 2470 /* turn off PHY */ 2471 if ((sc->sc_flags & RTW_F_INVALID) == 0 && 2472 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2473 printf("%s: failed to turn off PHY (%d)\n", 2474 sc->sc_dev.dv_xname, rc); 2475 } 2476 2477 if (sc->sc_disable != NULL) 2478 (*sc->sc_disable)(sc); 2479 2480 sc->sc_flags &= ~RTW_F_ENABLED; 2481 } 2482 2483 int 2484 rtw_enable(struct rtw_softc *sc) 2485 { 2486 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2487 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2488 printf("%s: device enable failed\n", 2489 sc->sc_dev.dv_xname); 2490 return (EIO); 2491 } 2492 sc->sc_flags |= RTW_F_ENABLED; 2493 /* Power may have been removed, and WEP keys thus 2494 * reset. 2495 */ 2496 sc->sc_flags &= ~RTW_F_DK_VALID; 2497 } 2498 return (0); 2499 } 2500 2501 static void 2502 rtw_transmit_config(struct rtw_regs *regs) 2503 { 2504 uint32_t tcr; 2505 2506 tcr = RTW_READ(regs, RTW_TCR); 2507 2508 tcr |= RTW_TCR_CWMIN; 2509 tcr &= ~RTW_TCR_MXDMA_MASK; 2510 tcr |= RTW_TCR_MXDMA_256; 2511 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2512 tcr &= ~RTW_TCR_LBK_MASK; 2513 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2514 2515 /* set short/long retry limits */ 2516 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2517 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK); 2518 2519 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2520 2521 RTW_WRITE(regs, RTW_TCR, tcr); 2522 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2523 } 2524 2525 static inline void 2526 rtw_enable_interrupts(struct rtw_softc *sc) 2527 { 2528 struct rtw_regs *regs = &sc->sc_regs; 2529 2530 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2531 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2532 2533 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2534 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2535 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2536 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2537 2538 /* XXX necessary? */ 2539 if (sc->sc_intr_ack != NULL) 2540 (*sc->sc_intr_ack)(regs); 2541 } 2542 2543 static void 2544 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2545 { 2546 uint8_t msr; 2547 2548 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2549 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2550 2551 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2552 2553 switch (opmode) { 2554 case IEEE80211_M_AHDEMO: 2555 case IEEE80211_M_IBSS: 2556 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2557 break; 2558 case IEEE80211_M_HOSTAP: 2559 msr |= RTW_MSR_NETYPE_AP_OK; 2560 break; 2561 case IEEE80211_M_MONITOR: 2562 /* XXX */ 2563 msr |= RTW_MSR_NETYPE_NOLINK; 2564 break; 2565 case IEEE80211_M_STA: 2566 msr |= RTW_MSR_NETYPE_INFRA_OK; 2567 break; 2568 } 2569 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2570 2571 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2572 } 2573 2574 #define rtw_calchash(addr) \ 2575 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2576 2577 static void 2578 rtw_pktfilt_load(struct rtw_softc *sc) 2579 { 2580 struct rtw_regs *regs = &sc->sc_regs; 2581 struct ieee80211com *ic = &sc->sc_ic; 2582 struct ethercom *ec = &sc->sc_ec; 2583 struct ifnet *ifp = &sc->sc_if; 2584 int hash; 2585 uint32_t hashes[2] = { 0, 0 }; 2586 struct ether_multi *enm; 2587 struct ether_multistep step; 2588 2589 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2590 2591 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2592 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2593 2594 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2595 /* MAC auto-reset PHY (huh?) */ 2596 sc->sc_rcr |= RTW_RCR_ENMARP; 2597 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2598 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2599 2600 switch (ic->ic_opmode) { 2601 case IEEE80211_M_MONITOR: 2602 sc->sc_rcr |= RTW_RCR_MONITOR; 2603 break; 2604 case IEEE80211_M_AHDEMO: 2605 case IEEE80211_M_IBSS: 2606 /* receive broadcasts in our BSS */ 2607 sc->sc_rcr |= RTW_RCR_ADD3; 2608 break; 2609 default: 2610 break; 2611 } 2612 2613 ifp->if_flags &= ~IFF_ALLMULTI; 2614 2615 /* 2616 * Program the 64-bit multicast hash filter. 2617 */ 2618 ETHER_FIRST_MULTI(step, ec, enm); 2619 while (enm != NULL) { 2620 /* XXX */ 2621 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2622 ETHER_ADDR_LEN) != 0) { 2623 ifp->if_flags |= IFF_ALLMULTI; 2624 break; 2625 } 2626 2627 hash = rtw_calchash(enm->enm_addrlo); 2628 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2629 ETHER_NEXT_MULTI(step, enm); 2630 } 2631 2632 /* XXX accept all broadcast if scanning */ 2633 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2634 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2635 2636 if (ifp->if_flags & IFF_PROMISC) { 2637 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2638 sc->sc_rcr |= RTW_RCR_ACRC32; /* accept frames failing CRC */ 2639 sc->sc_rcr |= RTW_RCR_AICV; /* accept frames failing ICV */ 2640 ifp->if_flags |= IFF_ALLMULTI; 2641 } 2642 2643 if (ifp->if_flags & IFF_ALLMULTI) 2644 hashes[0] = hashes[1] = 0xffffffff; 2645 2646 if ((hashes[0] | hashes[1]) != 0) 2647 sc->sc_rcr |= RTW_RCR_AM; /* accept multicast */ 2648 2649 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2650 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2651 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2652 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2653 2654 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2655 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2656 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2657 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2658 } 2659 2660 static struct mbuf * 2661 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2662 { 2663 struct ieee80211com *ic = &sc->sc_ic; 2664 struct mbuf *m; 2665 struct ieee80211_beacon_offsets boff; 2666 2667 if ((m = ieee80211_beacon_alloc(ic, ni, &boff)) != NULL) { 2668 RTW_DPRINTF(RTW_DEBUG_BEACON, 2669 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2670 } 2671 return m; 2672 } 2673 2674 /* Must be called at splnet. */ 2675 static int 2676 rtw_init(struct ifnet *ifp) 2677 { 2678 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2679 struct ieee80211com *ic = &sc->sc_ic; 2680 struct rtw_regs *regs = &sc->sc_regs; 2681 int rc = 0; 2682 2683 if ((rc = rtw_enable(sc)) != 0) 2684 goto out; 2685 2686 /* Cancel pending I/O and reset. */ 2687 rtw_stop(ifp, 0); 2688 2689 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2690 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 2691 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 2692 2693 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2694 goto out; 2695 2696 if ((rc = rtw_swring_setup(sc)) != 0) 2697 goto out; 2698 2699 rtw_transmit_config(regs); 2700 2701 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2702 2703 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2704 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2705 2706 /* long PLCP header, 1Mb/2Mb basic rate */ 2707 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2708 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2709 2710 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2711 rtw_set_access(regs, RTW_ACCESS_NONE); 2712 2713 /* XXX from reference sources */ 2714 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2715 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2716 2717 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2718 2719 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2720 /* from Linux driver */ 2721 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2722 2723 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2724 2725 rtw_enable_interrupts(sc); 2726 2727 rtw_pktfilt_load(sc); 2728 2729 rtw_hwring_setup(sc); 2730 2731 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2732 2733 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2734 2735 ifp->if_flags |= IFF_RUNNING; 2736 ic->ic_state = IEEE80211_S_INIT; 2737 2738 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2739 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2740 2741 rtw_resume_ticks(sc); 2742 2743 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2744 2745 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2746 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2747 else 2748 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2749 2750 out: 2751 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2752 return rc; 2753 } 2754 2755 static inline void 2756 rtw_led_init(struct rtw_regs *regs) 2757 { 2758 uint8_t cfg0, cfg1; 2759 2760 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2761 2762 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2763 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2764 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2765 2766 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2767 RTW_DPRINTF(RTW_DEBUG_LED, 2768 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2769 2770 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2771 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2772 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2773 2774 rtw_set_access(regs, RTW_ACCESS_NONE); 2775 } 2776 2777 /* 2778 * IEEE80211_S_INIT: LED1 off 2779 * 2780 * IEEE80211_S_AUTH, 2781 * IEEE80211_S_ASSOC, 2782 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2783 * 2784 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2785 */ 2786 static void 2787 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2788 { 2789 struct rtw_led_state *ls; 2790 2791 ls = &sc->sc_led_state; 2792 2793 switch (nstate) { 2794 case IEEE80211_S_INIT: 2795 rtw_led_init(&sc->sc_regs); 2796 callout_stop(&ls->ls_slow_ch); 2797 callout_stop(&ls->ls_fast_ch); 2798 ls->ls_slowblink = 0; 2799 ls->ls_actblink = 0; 2800 ls->ls_default = 0; 2801 break; 2802 case IEEE80211_S_SCAN: 2803 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2804 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2805 /*FALLTHROUGH*/ 2806 case IEEE80211_S_AUTH: 2807 case IEEE80211_S_ASSOC: 2808 ls->ls_default = RTW_LED1; 2809 ls->ls_actblink = RTW_LED1; 2810 ls->ls_slowblink = RTW_LED1; 2811 break; 2812 case IEEE80211_S_RUN: 2813 ls->ls_slowblink = 0; 2814 break; 2815 } 2816 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2817 } 2818 2819 static void 2820 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2821 { 2822 uint8_t led_condition; 2823 bus_size_t ofs; 2824 uint8_t mask, newval, val; 2825 2826 led_condition = ls->ls_default; 2827 2828 if (ls->ls_state & RTW_LED_S_SLOW) 2829 led_condition ^= ls->ls_slowblink; 2830 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2831 led_condition ^= ls->ls_actblink; 2832 2833 RTW_DPRINTF(RTW_DEBUG_LED, 2834 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2835 2836 switch (hwverid) { 2837 default: 2838 case 'F': 2839 ofs = RTW_PSR; 2840 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2841 if (led_condition & RTW_LED0) 2842 newval &= ~RTW_PSR_LEDGPO0; 2843 if (led_condition & RTW_LED1) 2844 newval &= ~RTW_PSR_LEDGPO1; 2845 break; 2846 case 'D': 2847 ofs = RTW_9346CR; 2848 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2849 newval = RTW_9346CR_EEM_PROGRAM; 2850 if (led_condition & RTW_LED0) 2851 newval |= RTW_9346CR_EEDI; 2852 if (led_condition & RTW_LED1) 2853 newval |= RTW_9346CR_EECS; 2854 break; 2855 } 2856 val = RTW_READ8(regs, ofs); 2857 RTW_DPRINTF(RTW_DEBUG_LED, 2858 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2859 (uintptr_t)ofs)); 2860 val &= ~mask; 2861 val |= newval; 2862 RTW_WRITE8(regs, ofs, val); 2863 RTW_DPRINTF(RTW_DEBUG_LED, 2864 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2865 (uintptr_t)ofs)); 2866 RTW_SYNC(regs, ofs, ofs); 2867 } 2868 2869 static void 2870 rtw_led_fastblink(void *arg) 2871 { 2872 int ostate, s; 2873 struct rtw_softc *sc = (struct rtw_softc *)arg; 2874 struct rtw_led_state *ls = &sc->sc_led_state; 2875 2876 s = splnet(); 2877 ostate = ls->ls_state; 2878 ls->ls_state ^= ls->ls_event; 2879 2880 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2881 ls->ls_state &= ~RTW_LED_S_TX; 2882 2883 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2884 ls->ls_state &= ~RTW_LED_S_RX; 2885 2886 ls->ls_event = 0; 2887 2888 if (ostate != ls->ls_state) 2889 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2890 splx(s); 2891 2892 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2893 } 2894 2895 static void 2896 rtw_led_slowblink(void *arg) 2897 { 2898 int s; 2899 struct rtw_softc *sc = (struct rtw_softc *)arg; 2900 struct rtw_led_state *ls = &sc->sc_led_state; 2901 2902 s = splnet(); 2903 ls->ls_state ^= RTW_LED_S_SLOW; 2904 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2905 splx(s); 2906 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2907 } 2908 2909 static inline void 2910 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2911 { 2912 callout_init(&ls->ls_fast_ch, 0); 2913 callout_init(&ls->ls_slow_ch, 0); 2914 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2915 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2916 } 2917 2918 static int 2919 rtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2920 { 2921 int rc = 0, s; 2922 struct rtw_softc *sc = ifp->if_softc; 2923 2924 s = splnet(); 2925 if (cmd == SIOCSIFFLAGS) { 2926 if ((ifp->if_flags & IFF_UP) != 0) { 2927 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2928 rtw_pktfilt_load(sc); 2929 else 2930 rc = rtw_init(ifp); 2931 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2932 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2933 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2934 rtw_stop(ifp, 1); 2935 } 2936 } else if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 2937 ; /* nothing to do */ 2938 else if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 2939 /* reload packet filter if running */ 2940 if (ifp->if_flags & IFF_RUNNING) 2941 rtw_pktfilt_load(sc); 2942 rc = 0; 2943 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2944 /* reinitialize h/w if activated */ 2945 rc = rtw_init(ifp); 2946 else 2947 rc = 0; 2948 splx(s); 2949 return rc; 2950 } 2951 2952 /* Select a transmit ring with at least one h/w and s/w descriptor free. 2953 * Return 0 on success, -1 on failure. 2954 */ 2955 static inline int 2956 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 2957 struct rtw_txdesc_blk **tdbp, int pri) 2958 { 2959 struct rtw_txsoft_blk *tsb; 2960 struct rtw_txdesc_blk *tdb; 2961 2962 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 2963 2964 tsb = &sc->sc_txsoft_blk[pri]; 2965 tdb = &sc->sc_txdesc_blk[pri]; 2966 2967 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 2968 if (tsb->tsb_tx_timer == 0) 2969 tsb->tsb_tx_timer = 5; 2970 *tsbp = NULL; 2971 *tdbp = NULL; 2972 return -1; 2973 } 2974 *tsbp = tsb; 2975 *tdbp = tdb; 2976 return 0; 2977 } 2978 2979 static inline struct mbuf * 2980 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 2981 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 2982 struct ieee80211_node **nip, short *if_flagsp) 2983 { 2984 struct mbuf *m; 2985 2986 if (IF_IS_EMPTY(ifq)) 2987 return NULL; 2988 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 2989 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 2990 __func__, pri)); 2991 *if_flagsp |= IFF_OACTIVE; 2992 sc->sc_if.if_timer = 1; 2993 return NULL; 2994 } 2995 IF_DEQUEUE(ifq, m); 2996 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2997 m->m_pkthdr.rcvif = NULL; 2998 KASSERT(*nip != NULL); 2999 return m; 3000 } 3001 3002 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 3003 * at the driver's selection of transmit control block for the packet. 3004 */ 3005 static inline int 3006 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 3007 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 3008 struct ieee80211_node **nip) 3009 { 3010 int pri; 3011 struct ether_header *eh; 3012 struct mbuf *m0; 3013 struct rtw_softc *sc; 3014 short *if_flagsp; 3015 3016 *mp = NULL; 3017 3018 sc = (struct rtw_softc *)ifp->if_softc; 3019 3020 DPRINTF(sc, RTW_DEBUG_XMIT, 3021 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3022 3023 if_flagsp = &ifp->if_flags; 3024 3025 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 3026 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 3027 tdbp, nip, if_flagsp)) != NULL) { 3028 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 3029 __func__)); 3030 return 0; 3031 } 3032 3033 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 3034 tdbp, nip, if_flagsp)) != NULL) { 3035 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 3036 __func__)); 3037 return 0; 3038 } 3039 3040 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 3041 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 3042 return 0; 3043 } 3044 3045 IFQ_POLL(&ifp->if_snd, m0); 3046 if (m0 == NULL) { 3047 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3048 __func__)); 3049 return 0; 3050 } 3051 3052 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 3053 3054 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3055 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3056 __func__, pri)); 3057 *if_flagsp |= IFF_OACTIVE; 3058 sc->sc_if.if_timer = 1; 3059 return 0; 3060 } 3061 3062 IFQ_DEQUEUE(&ifp->if_snd, m0); 3063 if (m0 == NULL) { 3064 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3065 __func__)); 3066 return 0; 3067 } 3068 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 3069 ifp->if_opackets++; 3070 #if NBPFILTER > 0 3071 if (ifp->if_bpf) 3072 bpf_mtap(ifp->if_bpf, m0); 3073 #endif 3074 eh = mtod(m0, struct ether_header *); 3075 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 3076 if (*nip == NULL) { 3077 /* NB: ieee80211_find_txnode does stat+msg */ 3078 m_freem(m0); 3079 return -1; 3080 } 3081 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 3082 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 3083 ifp->if_oerrors++; 3084 return -1; 3085 } 3086 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3087 *mp = m0; 3088 return 0; 3089 } 3090 3091 static int 3092 rtw_seg_too_short(bus_dmamap_t dmamap) 3093 { 3094 int i; 3095 for (i = 0; i < dmamap->dm_nsegs; i++) { 3096 if (dmamap->dm_segs[i].ds_len < 4) 3097 return 1; 3098 } 3099 return 0; 3100 } 3101 3102 /* TBD factor with atw_start */ 3103 static struct mbuf * 3104 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 3105 u_int ndescfree, const char *dvname) 3106 { 3107 int first, rc; 3108 struct mbuf *m, *m0; 3109 3110 m0 = chain; 3111 3112 /* 3113 * Load the DMA map. Copy and try (once) again if the packet 3114 * didn't fit in the alloted number of segments. 3115 */ 3116 for (first = 1; 3117 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 3118 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 3119 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 3120 first = 0) { 3121 if (rc == 0) { 3122 #ifdef RTW_DIAGxxx 3123 if (rtw_seg_too_short(dmam)) { 3124 printf("%s: short segment, mbuf lengths:", __func__); 3125 for (m = m0; m; m = m->m_next) 3126 printf(" %d", m->m_len); 3127 printf("\n"); 3128 } 3129 #endif 3130 bus_dmamap_unload(dmat, dmam); 3131 } 3132 MGETHDR(m, M_DONTWAIT, MT_DATA); 3133 if (m == NULL) { 3134 printf("%s: unable to allocate Tx mbuf\n", 3135 dvname); 3136 break; 3137 } 3138 if (m0->m_pkthdr.len > MHLEN) { 3139 MCLGET(m, M_DONTWAIT); 3140 if ((m->m_flags & M_EXT) == 0) { 3141 printf("%s: cannot allocate Tx cluster\n", 3142 dvname); 3143 m_freem(m); 3144 break; 3145 } 3146 } 3147 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3148 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3149 m_freem(m0); 3150 m0 = m; 3151 m = NULL; 3152 } 3153 if (rc != 0) { 3154 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 3155 m_freem(m0); 3156 return NULL; 3157 } else if (rtw_seg_too_short(dmam)) { 3158 printf("%s: cannot load Tx buffer, segment too short\n", 3159 dvname); 3160 bus_dmamap_unload(dmat, dmam); 3161 m_freem(m0); 3162 return NULL; 3163 } else if (dmam->dm_nsegs > ndescfree) { 3164 printf("%s: too many tx segments\n", dvname); 3165 bus_dmamap_unload(dmat, dmam); 3166 m_freem(m0); 3167 return NULL; 3168 } 3169 return m0; 3170 } 3171 3172 #ifdef RTW_DEBUG 3173 static void 3174 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3175 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3176 { 3177 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3178 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] next %#08x " 3179 "buf %#08x ctl0 %#08x ctl1 %#08x len %#08x\n", 3180 sc->sc_dev.dv_xname, ts, action, desc, 3181 le32toh(td->td_buf), le32toh(td->td_next), 3182 le32toh(td->td_ctl0), le32toh(td->td_ctl1), 3183 le32toh(td->td_len))); 3184 } 3185 #endif /* RTW_DEBUG */ 3186 3187 static void 3188 rtw_start(struct ifnet *ifp) 3189 { 3190 uint8_t tppoll; 3191 int desc, i, lastdesc, npkt, rate; 3192 uint32_t proto_ctl0, ctl0, ctl1; 3193 bus_dmamap_t dmamap; 3194 struct ieee80211com *ic; 3195 struct ieee80211_duration *d0; 3196 struct ieee80211_frame_min *wh; 3197 struct ieee80211_node *ni = NULL; /* XXX: GCC */ 3198 struct mbuf *m0; 3199 struct rtw_softc *sc; 3200 struct rtw_txsoft_blk *tsb = NULL; /* XXX: GCC */ 3201 struct rtw_txdesc_blk *tdb = NULL; /* XXX: GCC */ 3202 struct rtw_txsoft *ts; 3203 struct rtw_txdesc *td; 3204 struct ieee80211_key *k; 3205 3206 sc = (struct rtw_softc *)ifp->if_softc; 3207 ic = &sc->sc_ic; 3208 3209 DPRINTF(sc, RTW_DEBUG_XMIT, 3210 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3211 3212 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3213 goto out; 3214 3215 /* XXX do real rate control */ 3216 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3217 3218 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3219 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3220 3221 for (;;) { 3222 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3223 continue; 3224 if (m0 == NULL) 3225 break; 3226 3227 wh = mtod(m0, struct ieee80211_frame_min *); 3228 3229 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3230 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3231 m_freem(m0); 3232 break; 3233 } else 3234 k = NULL; 3235 3236 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3237 3238 dmamap = ts->ts_dmamap; 3239 3240 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3241 tdb->tdb_nfree, sc->sc_dev.dv_xname); 3242 3243 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3244 DPRINTF(sc, RTW_DEBUG_XMIT, 3245 ("%s: fail dmamap load\n", __func__)); 3246 goto post_dequeue_err; 3247 } 3248 3249 /* Note well: rtw_dmamap_load_txbuf may have created 3250 * a new chain, so we must find the header once 3251 * more. 3252 */ 3253 wh = mtod(m0, struct ieee80211_frame_min *); 3254 3255 /* XXX do real rate control */ 3256 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3257 IEEE80211_FC0_TYPE_MGT) 3258 rate = 2; 3259 else 3260 rate = MAX(2, ieee80211_get_rate(ni)); 3261 3262 #ifdef RTW_DEBUG 3263 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3264 (IFF_DEBUG|IFF_LINK2)) { 3265 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3266 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3267 : sizeof(wh), 3268 rate, 0); 3269 } 3270 #endif /* RTW_DEBUG */ 3271 ctl0 = proto_ctl0 | 3272 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3273 3274 switch (rate) { 3275 default: 3276 case 2: 3277 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3278 break; 3279 case 4: 3280 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3281 break; 3282 case 11: 3283 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3284 break; 3285 case 22: 3286 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3287 break; 3288 } 3289 /* XXX >= ? Compare after fragmentation? */ 3290 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3291 ctl0 |= RTW_TXCTL0_RTSEN; 3292 3293 /* XXX Sometimes writes a bogus keyid; h/w doesn't 3294 * seem to care, since we don't activate h/w Tx 3295 * encryption. 3296 */ 3297 if (k != NULL) { 3298 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3299 RTW_TXCTL0_KEYID_MASK; 3300 } 3301 3302 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3303 IEEE80211_FC0_TYPE_MGT) { 3304 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3305 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3306 IEEE80211_FC0_SUBTYPE_BEACON) 3307 ctl0 |= RTW_TXCTL0_BEACON; 3308 } 3309 3310 if (ieee80211_compute_duration(wh, k, m0->m_pkthdr.len, 3311 ic->ic_flags, ic->ic_fragthreshold, 3312 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3313 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3314 (IFF_DEBUG|IFF_LINK2)) == -1) { 3315 DPRINTF(sc, RTW_DEBUG_XMIT, 3316 ("%s: fail compute duration\n", __func__)); 3317 goto post_load_err; 3318 } 3319 3320 d0 = &ts->ts_d0; 3321 3322 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3323 3324 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3325 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3326 3327 if (d0->d_residue) 3328 ctl1 |= RTW_TXCTL1_LENGEXT; 3329 3330 /* TBD fragmentation */ 3331 3332 ts->ts_first = tdb->tdb_next; 3333 3334 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3335 BUS_DMASYNC_PREWRITE); 3336 3337 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3338 3339 #if NBPFILTER > 0 3340 if (ic->ic_rawbpf != NULL) 3341 bpf_mtap((void *)ic->ic_rawbpf, m0); 3342 3343 if (sc->sc_radiobpf != NULL) { 3344 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3345 3346 rt->rt_rate = rate; 3347 3348 bpf_mtap2(sc->sc_radiobpf, (void *)rt, 3349 sizeof(sc->sc_txtapu), m0); 3350 } 3351 #endif /* NBPFILTER > 0 */ 3352 3353 for (i = 0, lastdesc = desc = ts->ts_first; 3354 i < dmamap->dm_nsegs; 3355 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3356 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3357 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3358 ("%s: seg too long\n", __func__)); 3359 goto post_load_err; 3360 } 3361 td = &tdb->tdb_desc[desc]; 3362 td->td_ctl0 = htole32(ctl0); 3363 td->td_ctl1 = htole32(ctl1); 3364 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3365 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3366 td->td_next = htole32(RTW_NEXT_DESC(tdb, desc)); 3367 if (i != 0) 3368 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3369 lastdesc = desc; 3370 #ifdef RTW_DEBUG 3371 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3372 #endif /* RTW_DEBUG */ 3373 } 3374 3375 KASSERT(desc < tdb->tdb_ndesc); 3376 3377 ts->ts_ni = ni; 3378 KASSERT(ni != NULL); 3379 ts->ts_mbuf = m0; 3380 ts->ts_last = lastdesc; 3381 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3382 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3383 htole32(RTW_TXCTL0_FS); 3384 3385 #ifdef RTW_DEBUG 3386 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3387 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3388 #endif /* RTW_DEBUG */ 3389 3390 tdb->tdb_nfree -= dmamap->dm_nsegs; 3391 tdb->tdb_next = desc; 3392 3393 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3394 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3395 3396 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3397 htole32(RTW_TXCTL0_OWN); 3398 3399 #ifdef RTW_DEBUG 3400 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3401 #endif /* RTW_DEBUG */ 3402 3403 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3404 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3405 3406 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3407 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3408 3409 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) 3410 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3411 tsb->tsb_tx_timer = 5; 3412 ifp->if_timer = 1; 3413 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3414 tppoll &= ~RTW_TPPOLL_SALL; 3415 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL; 3416 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3417 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3418 } 3419 out: 3420 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3421 return; 3422 post_load_err: 3423 bus_dmamap_unload(sc->sc_dmat, dmamap); 3424 m_freem(m0); 3425 post_dequeue_err: 3426 ieee80211_free_node(ni); 3427 return; 3428 } 3429 3430 static void 3431 rtw_idle(struct rtw_regs *regs) 3432 { 3433 int active; 3434 3435 /* request stop DMA; wait for packets to stop transmitting. */ 3436 3437 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3438 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL); 3439 3440 for (active = 0; active < 300 && 3441 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0; active++) 3442 DELAY(10); 3443 printf("%s: transmit DMA idle in %dus\n", __func__, active * 10); 3444 } 3445 3446 static void 3447 rtw_watchdog(struct ifnet *ifp) 3448 { 3449 int pri, tx_timeouts = 0; 3450 struct rtw_softc *sc; 3451 struct rtw_txsoft_blk *tsb; 3452 3453 sc = ifp->if_softc; 3454 3455 ifp->if_timer = 0; 3456 3457 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 3458 return; 3459 3460 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3461 tsb = &sc->sc_txsoft_blk[pri]; 3462 3463 if (tsb->tsb_tx_timer == 0) 3464 continue; 3465 else if (--tsb->tsb_tx_timer == 0) { 3466 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3467 continue; 3468 printf("%s: transmit timeout, priority %d\n", 3469 ifp->if_xname, pri); 3470 ifp->if_oerrors++; 3471 if (pri != RTW_TXPRIBCN) 3472 tx_timeouts++; 3473 } else 3474 ifp->if_timer = 1; 3475 } 3476 3477 if (tx_timeouts > 0) { 3478 /* Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr, 3479 * reset s/w tx-ring pointers, and start transmission. 3480 * 3481 * TBD Stop/restart just the broken rings? 3482 */ 3483 rtw_idle(&sc->sc_regs); 3484 rtw_io_enable(sc, RTW_CR_TE, 0); 3485 rtw_txdescs_reset(sc); 3486 rtw_io_enable(sc, RTW_CR_TE, 1); 3487 rtw_start(ifp); 3488 } 3489 ieee80211_watchdog(&sc->sc_ic); 3490 return; 3491 } 3492 3493 static void 3494 rtw_next_scan(void *arg) 3495 { 3496 struct ieee80211com *ic = arg; 3497 int s; 3498 3499 /* don't call rtw_start w/o network interrupts blocked */ 3500 s = splnet(); 3501 if (ic->ic_state == IEEE80211_S_SCAN) 3502 ieee80211_next_scan(ic); 3503 splx(s); 3504 } 3505 3506 static void 3507 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3508 { 3509 uint16_t bcnitv, bintritv, intval; 3510 int i; 3511 struct rtw_regs *regs = &sc->sc_regs; 3512 3513 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3514 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3515 3516 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3517 3518 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3519 3520 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); 3521 3522 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3523 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); 3524 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3525 /* interrupt host 1ms before the TBTT */ 3526 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV; 3527 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV); 3528 RTW_WRITE16(regs, RTW_BINTRITV, bintritv); 3529 /* magic from Linux */ 3530 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND)); 3531 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); 3532 rtw_set_access(regs, RTW_ACCESS_NONE); 3533 3534 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 3535 } 3536 3537 /* Synchronize the hardware state with the software state. */ 3538 static int 3539 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3540 { 3541 struct ifnet *ifp = ic->ic_ifp; 3542 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3543 enum ieee80211_state ostate; 3544 int error; 3545 3546 ostate = ic->ic_state; 3547 3548 rtw_led_newstate(sc, nstate); 3549 3550 if (nstate == IEEE80211_S_INIT) { 3551 callout_stop(&sc->sc_scan_ch); 3552 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3553 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3554 } 3555 3556 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3557 rtw_pwrstate(sc, RTW_ON); 3558 3559 if ((error = rtw_tune(sc)) != 0) 3560 return error; 3561 3562 switch (nstate) { 3563 case IEEE80211_S_INIT: 3564 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3565 break; 3566 case IEEE80211_S_SCAN: 3567 if (ostate != IEEE80211_S_SCAN) { 3568 (void)memset(ic->ic_bss->ni_bssid, 0, 3569 IEEE80211_ADDR_LEN); 3570 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3571 } 3572 3573 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3574 rtw_next_scan, ic); 3575 3576 break; 3577 case IEEE80211_S_RUN: 3578 switch (ic->ic_opmode) { 3579 case IEEE80211_M_HOSTAP: 3580 case IEEE80211_M_IBSS: 3581 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3582 /*FALLTHROUGH*/ 3583 case IEEE80211_M_AHDEMO: 3584 case IEEE80211_M_STA: 3585 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3586 ic->ic_bss->ni_intval); 3587 break; 3588 case IEEE80211_M_MONITOR: 3589 break; 3590 } 3591 rtw_set_nettype(sc, ic->ic_opmode); 3592 break; 3593 case IEEE80211_S_ASSOC: 3594 case IEEE80211_S_AUTH: 3595 break; 3596 } 3597 3598 if (nstate != IEEE80211_S_SCAN) 3599 callout_stop(&sc->sc_scan_ch); 3600 3601 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3602 } 3603 3604 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3605 static uint64_t 3606 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3607 { 3608 uint32_t tsftl, tsfth; 3609 3610 tsfth = RTW_READ(regs, RTW_TSFTRH); 3611 tsftl = RTW_READ(regs, RTW_TSFTRL); 3612 if (tsftl < rstamp) /* Compensate for rollover. */ 3613 tsfth--; 3614 return ((uint64_t)tsfth << 32) | rstamp; 3615 } 3616 3617 static void 3618 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3619 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3620 { 3621 struct ifnet *ifp = ic->ic_ifp; 3622 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3623 3624 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3625 3626 switch (subtype) { 3627 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3628 case IEEE80211_FC0_SUBTYPE_BEACON: 3629 if (ic->ic_opmode == IEEE80211_M_IBSS && 3630 ic->ic_state == IEEE80211_S_RUN) { 3631 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp); 3632 if (le64toh(ni->ni_tstamp.tsf) >= tsf) 3633 (void)ieee80211_ibss_merge(ni); 3634 } 3635 break; 3636 default: 3637 break; 3638 } 3639 return; 3640 } 3641 3642 static struct ieee80211_node * 3643 rtw_node_alloc(struct ieee80211_node_table *nt) 3644 { 3645 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3646 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3647 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3648 3649 DPRINTF(sc, RTW_DEBUG_NODE, 3650 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3651 return ni; 3652 } 3653 3654 static void 3655 rtw_node_free(struct ieee80211_node *ni) 3656 { 3657 struct ieee80211com *ic = ni->ni_ic; 3658 struct ifnet *ifp = ic->ic_ifp; 3659 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3660 3661 DPRINTF(sc, RTW_DEBUG_NODE, 3662 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3663 ether_sprintf(ni->ni_bssid))); 3664 (*sc->sc_mtbl.mt_node_free)(ni); 3665 } 3666 3667 static int 3668 rtw_media_change(struct ifnet *ifp) 3669 { 3670 int error; 3671 3672 error = ieee80211_media_change(ifp); 3673 if (error == ENETRESET) { 3674 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3675 (IFF_RUNNING|IFF_UP)) 3676 rtw_init(ifp); /* XXX lose error */ 3677 error = 0; 3678 } 3679 return error; 3680 } 3681 3682 static void 3683 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3684 { 3685 struct rtw_softc *sc = ifp->if_softc; 3686 3687 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3688 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3689 imr->ifm_status = 0; 3690 return; 3691 } 3692 ieee80211_media_status(ifp, imr); 3693 } 3694 3695 /* rtw_shutdown: make sure the interface is stopped at reboot time. */ 3696 void 3697 rtw_shutdown(void *arg) 3698 { 3699 struct rtw_softc *sc = arg; 3700 3701 rtw_stop(&sc->sc_if, 1); 3702 } 3703 3704 static inline void 3705 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3706 { 3707 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3708 ifp->if_softc = softc; 3709 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3710 IFF_NOTRAILERS; 3711 ifp->if_ioctl = rtw_ioctl; 3712 ifp->if_start = rtw_start; 3713 ifp->if_watchdog = rtw_watchdog; 3714 ifp->if_init = rtw_init; 3715 ifp->if_stop = rtw_stop; 3716 } 3717 3718 static inline void 3719 rtw_set80211props(struct ieee80211com *ic) 3720 { 3721 int nrate; 3722 ic->ic_phytype = IEEE80211_T_DS; 3723 ic->ic_opmode = IEEE80211_M_STA; 3724 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3725 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 3726 3727 nrate = 0; 3728 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3729 IEEE80211_RATE_BASIC | 2; 3730 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3731 IEEE80211_RATE_BASIC | 4; 3732 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3733 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3734 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3735 } 3736 3737 static inline void 3738 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3739 { 3740 mtbl->mt_newstate = ic->ic_newstate; 3741 ic->ic_newstate = rtw_newstate; 3742 3743 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3744 ic->ic_recv_mgmt = rtw_recv_mgmt; 3745 3746 mtbl->mt_node_free = ic->ic_node_free; 3747 ic->ic_node_free = rtw_node_free; 3748 3749 mtbl->mt_node_alloc = ic->ic_node_alloc; 3750 ic->ic_node_alloc = rtw_node_alloc; 3751 3752 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3753 ic->ic_crypto.cs_key_set = rtw_key_set; 3754 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3755 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3756 } 3757 3758 static inline void 3759 rtw_establish_hooks(struct rtw_hooks *hooks, const char *dvname, 3760 void *arg) 3761 { 3762 /* 3763 * Make sure the interface is shutdown during reboot. 3764 */ 3765 hooks->rh_shutdown = shutdownhook_establish(rtw_shutdown, arg); 3766 if (hooks->rh_shutdown == NULL) 3767 printf("%s: WARNING: unable to establish shutdown hook\n", 3768 dvname); 3769 } 3770 3771 static inline void 3772 rtw_disestablish_hooks(struct rtw_hooks *hooks, const char *dvname, 3773 void *arg) 3774 { 3775 if (hooks->rh_shutdown != NULL) 3776 shutdownhook_disestablish(hooks->rh_shutdown); 3777 } 3778 3779 static inline void 3780 rtw_init_radiotap(struct rtw_softc *sc) 3781 { 3782 uint32_t present; 3783 3784 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3785 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3786 3787 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 3788 present = htole32(RTW_PHILIPS_RX_RADIOTAP_PRESENT); 3789 else 3790 present = htole32(RTW_RX_RADIOTAP_PRESENT); 3791 sc->sc_rxtap.rr_ihdr.it_present = present; 3792 3793 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3794 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3795 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3796 } 3797 3798 static int 3799 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3800 { 3801 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3802 SIMPLEQ_INIT(&tsb->tsb_freeq); 3803 tsb->tsb_ndesc = qlen; 3804 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3805 M_NOWAIT); 3806 if (tsb->tsb_desc == NULL) 3807 return ENOMEM; 3808 return 0; 3809 } 3810 3811 static void 3812 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3813 { 3814 int pri; 3815 struct rtw_txsoft_blk *tsb; 3816 3817 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3818 tsb = &sc->sc_txsoft_blk[pri]; 3819 free(tsb->tsb_desc, M_DEVBUF); 3820 tsb->tsb_desc = NULL; 3821 } 3822 } 3823 3824 static int 3825 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3826 { 3827 int pri, rc = 0; 3828 int qlen[RTW_NTXPRI] = 3829 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3830 struct rtw_txsoft_blk *tsbs; 3831 3832 tsbs = sc->sc_txsoft_blk; 3833 3834 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3835 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3836 if (rc != 0) 3837 break; 3838 } 3839 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3840 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3841 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3842 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3843 return rc; 3844 } 3845 3846 static void 3847 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3848 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3849 { 3850 tdb->tdb_ndesc = ndesc; 3851 tdb->tdb_desc = desc; 3852 tdb->tdb_physbase = physbase; 3853 tdb->tdb_ofs = ofs; 3854 3855 (void)memset(tdb->tdb_desc, 0, 3856 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3857 3858 rtw_txdesc_blk_init(tdb); 3859 tdb->tdb_next = 0; 3860 } 3861 3862 static void 3863 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3864 { 3865 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3866 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3867 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3868 3869 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3870 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3871 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3872 3873 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3874 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3875 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3876 3877 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3878 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3879 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3880 } 3881 3882 static struct rtw_rf * 3883 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3884 { 3885 rtw_rf_write_t rf_write; 3886 struct rtw_rf *rf; 3887 3888 switch (rfchipid) { 3889 default: 3890 rf_write = rtw_rf_hostwrite; 3891 break; 3892 case RTW_RFCHIPID_INTERSIL: 3893 case RTW_RFCHIPID_PHILIPS: 3894 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3895 case RTW_RFCHIPID_RFMD: 3896 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3897 break; 3898 } 3899 3900 switch (rfchipid) { 3901 case RTW_RFCHIPID_GCT: 3902 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0); 3903 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3904 break; 3905 case RTW_RFCHIPID_MAXIM: 3906 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3907 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3908 break; 3909 case RTW_RFCHIPID_PHILIPS: 3910 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3911 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3912 break; 3913 case RTW_RFCHIPID_RFMD: 3914 /* XXX RFMD has no RF constructor */ 3915 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3916 /*FALLTHROUGH*/ 3917 default: 3918 return NULL; 3919 } 3920 rf->rf_continuous_tx_cb = 3921 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3922 rf->rf_continuous_tx_arg = (void *)sc; 3923 return rf; 3924 } 3925 3926 /* Revision C and later use a different PHY delay setting than 3927 * revisions A and B. 3928 */ 3929 static uint8_t 3930 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 3931 { 3932 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3933 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3934 3935 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); 3936 3937 RTW_WRITE(regs, RTW_RCR, REVAB); 3938 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3939 RTW_WRITE(regs, RTW_RCR, REVC); 3940 3941 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3942 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3943 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3944 3945 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 3946 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3947 3948 return phydelay; 3949 #undef REVC 3950 } 3951 3952 void 3953 rtw_attach(struct rtw_softc *sc) 3954 { 3955 struct ifnet *ifp = &sc->sc_if; 3956 struct ieee80211com *ic = &sc->sc_ic; 3957 struct rtw_txsoft_blk *tsb; 3958 int pri, rc; 3959 3960 rtw_cipher_wep = ieee80211_cipher_wep; 3961 rtw_cipher_wep.ic_decap = rtw_wep_decap; 3962 3963 NEXT_ATTACH_STATE(sc, DETACHED); 3964 3965 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3966 case RTW_TCR_HWVERID_F: 3967 sc->sc_hwverid = 'F'; 3968 break; 3969 case RTW_TCR_HWVERID_D: 3970 sc->sc_hwverid = 'D'; 3971 break; 3972 default: 3973 sc->sc_hwverid = '?'; 3974 break; 3975 } 3976 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, 3977 sc->sc_hwverid); 3978 3979 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3980 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3981 0); 3982 3983 if (rc != 0) { 3984 printf("%s: could not allocate hw descriptors, error %d\n", 3985 sc->sc_dev.dv_xname, rc); 3986 goto err; 3987 } 3988 3989 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3990 3991 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3992 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3993 (void **)&sc->sc_descs, BUS_DMA_COHERENT); 3994 3995 if (rc != 0) { 3996 printf("%s: could not map hw descriptors, error %d\n", 3997 sc->sc_dev.dv_xname, rc); 3998 goto err; 3999 } 4000 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 4001 4002 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 4003 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 4004 4005 if (rc != 0) { 4006 printf("%s: could not create DMA map for hw descriptors, " 4007 "error %d\n", sc->sc_dev.dv_xname, rc); 4008 goto err; 4009 } 4010 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 4011 4012 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 4013 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 4014 4015 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4016 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 4017 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 4018 } 4019 4020 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 4021 sizeof(struct rtw_descs), NULL, 0); 4022 4023 if (rc != 0) { 4024 printf("%s: could not load DMA map for hw descriptors, " 4025 "error %d\n", sc->sc_dev.dv_xname, rc); 4026 goto err; 4027 } 4028 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 4029 4030 if (rtw_txsoft_blk_setup_all(sc) != 0) 4031 goto err; 4032 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 4033 4034 rtw_txdesc_blk_setup_all(sc); 4035 4036 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 4037 4038 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 4039 4040 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4041 tsb = &sc->sc_txsoft_blk[pri]; 4042 4043 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 4044 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 4045 printf("%s: could not load DMA map for " 4046 "hw tx descriptors, error %d\n", 4047 sc->sc_dev.dv_xname, rc); 4048 goto err; 4049 } 4050 } 4051 4052 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 4053 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 4054 RTW_RXQLEN)) != 0) { 4055 printf("%s: could not load DMA map for hw rx descriptors, " 4056 "error %d\n", sc->sc_dev.dv_xname, rc); 4057 goto err; 4058 } 4059 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 4060 4061 /* Reset the chip to a known state. */ 4062 if (rtw_reset(sc) != 0) 4063 goto err; 4064 NEXT_ATTACH_STATE(sc, FINISH_RESET); 4065 4066 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 4067 4068 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 4069 sc->sc_flags |= RTW_F_9356SROM; 4070 4071 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 4072 sc->sc_dev.dv_xname) != 0) 4073 goto err; 4074 4075 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 4076 4077 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 4078 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 4079 sc->sc_dev.dv_xname) != 0) { 4080 printf("%s: attach failed, malformed serial ROM\n", 4081 sc->sc_dev.dv_xname); 4082 goto err; 4083 } 4084 4085 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 4086 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 4087 4088 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 4089 4090 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 4091 4092 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 4093 sc->sc_flags & RTW_F_DIGPHY); 4094 4095 if (sc->sc_rf == NULL) { 4096 printf("%s: attach failed, could not attach RF\n", 4097 sc->sc_dev.dv_xname); 4098 goto err; 4099 } 4100 4101 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 4102 4103 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4104 4105 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4106 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 4107 4108 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4109 rtw_identify_country(&sc->sc_regs, &sc->sc_locale); 4110 4111 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 4112 sc->sc_dev.dv_xname); 4113 4114 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4115 sc->sc_dev.dv_xname) != 0) 4116 goto err; 4117 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4118 4119 rtw_setifprops(ifp, sc->sc_dev.dv_xname, (void*)sc); 4120 4121 IFQ_SET_READY(&ifp->if_snd); 4122 4123 sc->sc_ic.ic_ifp = ifp; 4124 rtw_set80211props(&sc->sc_ic); 4125 4126 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4127 4128 /* 4129 * Call MI attach routines. 4130 */ 4131 if_attach(ifp); 4132 ieee80211_ifattach(&sc->sc_ic); 4133 4134 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4135 4136 /* possibly we should fill in our own sc_send_prresp, since 4137 * the RTL8180 is probably sending probe responses in ad hoc 4138 * mode. 4139 */ 4140 4141 /* complete initialization */ 4142 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4143 callout_init(&sc->sc_scan_ch, 0); 4144 4145 rtw_init_radiotap(sc); 4146 4147 #if NBPFILTER > 0 4148 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4149 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4150 #endif 4151 4152 rtw_establish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, (void*)sc); 4153 4154 if (!pmf_device_register(&sc->sc_dev, NULL, NULL)) { 4155 aprint_error_dev(&sc->sc_dev, 4156 "couldn't establish power handler\n"); 4157 } else 4158 pmf_class_network_register(&sc->sc_dev, &sc->sc_if); 4159 4160 NEXT_ATTACH_STATE(sc, FINISHED); 4161 4162 ieee80211_announce(ic); 4163 return; 4164 err: 4165 rtw_detach(sc); 4166 return; 4167 } 4168 4169 int 4170 rtw_detach(struct rtw_softc *sc) 4171 { 4172 struct ifnet *ifp = &sc->sc_if; 4173 int pri, s; 4174 4175 s = splnet(); 4176 sc->sc_flags |= RTW_F_INVALID; 4177 4178 switch (sc->sc_attach_state) { 4179 case FINISHED: 4180 rtw_stop(ifp, 1); 4181 4182 pmf_device_deregister(&sc->sc_dev); 4183 rtw_disestablish_hooks(&sc->sc_hooks, sc->sc_dev.dv_xname, 4184 (void*)sc); 4185 callout_stop(&sc->sc_scan_ch); 4186 ieee80211_ifdetach(&sc->sc_ic); 4187 if_detach(ifp); 4188 /*FALLTHROUGH*/ 4189 case FINISH_ID_STA: 4190 case FINISH_RF_ATTACH: 4191 rtw_rf_destroy(sc->sc_rf); 4192 sc->sc_rf = NULL; 4193 /*FALLTHROUGH*/ 4194 case FINISH_PARSE_SROM: 4195 case FINISH_READ_SROM: 4196 rtw_srom_free(&sc->sc_srom); 4197 /*FALLTHROUGH*/ 4198 case FINISH_RESET: 4199 case FINISH_RXMAPS_CREATE: 4200 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4201 RTW_RXQLEN); 4202 /*FALLTHROUGH*/ 4203 case FINISH_TXMAPS_CREATE: 4204 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4205 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4206 sc->sc_txsoft_blk[pri].tsb_desc, 4207 sc->sc_txsoft_blk[pri].tsb_ndesc); 4208 } 4209 /*FALLTHROUGH*/ 4210 case FINISH_TXDESCBLK_SETUP: 4211 case FINISH_TXCTLBLK_SETUP: 4212 rtw_txsoft_blk_cleanup_all(sc); 4213 /*FALLTHROUGH*/ 4214 case FINISH_DESCMAP_LOAD: 4215 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4216 /*FALLTHROUGH*/ 4217 case FINISH_DESCMAP_CREATE: 4218 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4219 /*FALLTHROUGH*/ 4220 case FINISH_DESC_MAP: 4221 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 4222 sizeof(struct rtw_descs)); 4223 /*FALLTHROUGH*/ 4224 case FINISH_DESC_ALLOC: 4225 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4226 sc->sc_desc_nsegs); 4227 /*FALLTHROUGH*/ 4228 case DETACHED: 4229 NEXT_ATTACH_STATE(sc, DETACHED); 4230 break; 4231 } 4232 splx(s); 4233 return 0; 4234 } 4235 4236 int 4237 rtw_activate(struct device *self, enum devact act) 4238 { 4239 struct rtw_softc *sc = (struct rtw_softc *)self; 4240 int rc = 0, s; 4241 4242 s = splnet(); 4243 switch (act) { 4244 case DVACT_ACTIVATE: 4245 rc = EOPNOTSUPP; 4246 break; 4247 4248 case DVACT_DEACTIVATE: 4249 if_deactivate(&sc->sc_if); 4250 break; 4251 } 4252 splx(s); 4253 return rc; 4254 } 4255
Indexes created Sat Sep 27 22:09:54 GMT 2025