rtw.c revision 1.97
1 /* $NetBSD: rtw.c,v 1.97 2007/12/20 18:47:23 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005, 2006, 2007 David Young. All rights 4 * reserved. 5 * 6 * Programmed for NetBSD by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of David Young may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 24 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 26 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /* 34 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.97 2007/12/20 18:47:23 dyoung Exp $"); 39 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/sysctl.h> 44 #include <sys/systm.h> 45 #include <sys/callout.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/time.h> 50 #include <sys/types.h> 51 52 #include <machine/endian.h> 53 #include <sys/bus.h> 54 #include <sys/intr.h> /* splnet */ 55 56 #include <uvm/uvm_extern.h> 57 58 #include <net/if.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #include <net80211/ieee80211_netbsd.h> 63 #include <net80211/ieee80211_var.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <dev/ic/rtwreg.h> 71 #include <dev/ic/rtwvar.h> 72 #include <dev/ic/rtwphyio.h> 73 #include <dev/ic/rtwphy.h> 74 75 #include <dev/ic/smc93cx6var.h> 76 77 static int rtw_rfprog_fallback = 0; 78 static int rtw_host_rfio = 0; 79 80 #ifdef RTW_DEBUG 81 int rtw_debug = 0; 82 static int rtw_rxbufs_limit = RTW_RXQLEN; 83 #endif /* RTW_DEBUG */ 84 85 #define NEXT_ATTACH_STATE(sc, state) do { \ 86 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 87 ("%s: attach state %s\n", __func__, #state)); \ 88 sc->sc_attach_state = state; \ 89 } while (0) 90 91 int rtw_dwelltime = 200; /* milliseconds */ 92 static struct ieee80211_cipher rtw_cipher_wep; 93 94 static void rtw_start(struct ifnet *); 95 static void rtw_reset_oactive(struct rtw_softc *); 96 static struct mbuf *rtw_beacon_alloc(struct rtw_softc *, 97 struct ieee80211_node *); 98 static u_int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *); 99 100 static void rtw_io_enable(struct rtw_softc *, uint8_t, int); 101 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 102 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 103 const u_int8_t[IEEE80211_ADDR_LEN]); 104 static void rtw_key_update_end(struct ieee80211com *); 105 static void rtw_key_update_begin(struct ieee80211com *); 106 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 107 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 108 109 static void rtw_led_attach(struct rtw_led_state *, void *); 110 static void rtw_led_init(struct rtw_regs *); 111 static void rtw_led_slowblink(void *); 112 static void rtw_led_fastblink(void *); 113 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 114 115 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 116 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 117 #ifdef RTW_DEBUG 118 static void rtw_dump_rings(struct rtw_softc *sc); 119 static void rtw_print_txdesc(struct rtw_softc *, const char *, 120 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 121 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 122 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 123 #endif /* RTW_DEBUG */ 124 #ifdef RTW_DIAG 125 static void rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln); 126 #endif /* RTW_DIAG */ 127 128 /* 129 * Setup sysctl(3) MIB, hw.rtw.* 130 * 131 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 132 */ 133 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 134 { 135 int rc; 136 const struct sysctlnode *cnode, *rnode; 137 138 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 139 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 140 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 141 goto err; 142 143 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 144 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 145 "Realtek RTL818x 802.11 controls", 146 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 147 goto err; 148 149 #ifdef RTW_DEBUG 150 /* control debugging printfs */ 151 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 152 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 153 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 154 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 155 CTL_CREATE, CTL_EOL)) != 0) 156 goto err; 157 158 /* Limit rx buffers, for simulating resource exhaustion. */ 159 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 160 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 161 "rxbufs_limit", 162 SYSCTL_DESCR("Set rx buffers limit"), 163 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 164 CTL_CREATE, CTL_EOL)) != 0) 165 goto err; 166 167 #endif /* RTW_DEBUG */ 168 /* set fallback RF programming method */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfprog_fallback", 172 SYSCTL_DESCR("Set fallback RF programming method"), 173 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 174 CTL_CREATE, CTL_EOL)) != 0) 175 goto err; 176 177 /* force host to control RF I/O bus */ 178 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 179 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 180 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 181 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 182 CTL_CREATE, CTL_EOL)) != 0) 183 goto err; 184 185 return; 186 err: 187 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 188 } 189 190 static int 191 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 192 { 193 int error, t; 194 struct sysctlnode node; 195 196 node = *rnode; 197 t = *(int*)rnode->sysctl_data; 198 node.sysctl_data = &t; 199 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 200 if (error || newp == NULL) 201 return (error); 202 203 if (t < lower || t > upper) 204 return (EINVAL); 205 206 *(int*)rnode->sysctl_data = t; 207 208 return (0); 209 } 210 211 static int 212 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 213 { 214 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 215 __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 216 } 217 218 static int 219 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 220 { 221 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 222 } 223 224 #ifdef RTW_DEBUG 225 static int 226 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 227 { 228 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 229 0, RTW_DEBUG_MAX); 230 } 231 232 static int 233 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 234 { 235 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 236 0, RTW_RXQLEN); 237 } 238 239 static void 240 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 241 { 242 #define PRINTREG32(sc, reg) \ 243 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 244 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 245 dvname, reg, RTW_READ(regs, reg))) 246 247 #define PRINTREG16(sc, reg) \ 248 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 249 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 250 dvname, reg, RTW_READ16(regs, reg))) 251 252 #define PRINTREG8(sc, reg) \ 253 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 254 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 255 dvname, reg, RTW_READ8(regs, reg))) 256 257 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 258 259 PRINTREG32(regs, RTW_IDR0); 260 PRINTREG32(regs, RTW_IDR1); 261 PRINTREG32(regs, RTW_MAR0); 262 PRINTREG32(regs, RTW_MAR1); 263 PRINTREG32(regs, RTW_TSFTRL); 264 PRINTREG32(regs, RTW_TSFTRH); 265 PRINTREG32(regs, RTW_TLPDA); 266 PRINTREG32(regs, RTW_TNPDA); 267 PRINTREG32(regs, RTW_THPDA); 268 PRINTREG32(regs, RTW_TCR); 269 PRINTREG32(regs, RTW_RCR); 270 PRINTREG32(regs, RTW_TINT); 271 PRINTREG32(regs, RTW_TBDA); 272 PRINTREG32(regs, RTW_ANAPARM); 273 PRINTREG32(regs, RTW_BB); 274 PRINTREG32(regs, RTW_PHYCFG); 275 PRINTREG32(regs, RTW_WAKEUP0L); 276 PRINTREG32(regs, RTW_WAKEUP0H); 277 PRINTREG32(regs, RTW_WAKEUP1L); 278 PRINTREG32(regs, RTW_WAKEUP1H); 279 PRINTREG32(regs, RTW_WAKEUP2LL); 280 PRINTREG32(regs, RTW_WAKEUP2LH); 281 PRINTREG32(regs, RTW_WAKEUP2HL); 282 PRINTREG32(regs, RTW_WAKEUP2HH); 283 PRINTREG32(regs, RTW_WAKEUP3LL); 284 PRINTREG32(regs, RTW_WAKEUP3LH); 285 PRINTREG32(regs, RTW_WAKEUP3HL); 286 PRINTREG32(regs, RTW_WAKEUP3HH); 287 PRINTREG32(regs, RTW_WAKEUP4LL); 288 PRINTREG32(regs, RTW_WAKEUP4LH); 289 PRINTREG32(regs, RTW_WAKEUP4HL); 290 PRINTREG32(regs, RTW_WAKEUP4HH); 291 PRINTREG32(regs, RTW_DK0); 292 PRINTREG32(regs, RTW_DK1); 293 PRINTREG32(regs, RTW_DK2); 294 PRINTREG32(regs, RTW_DK3); 295 PRINTREG32(regs, RTW_RETRYCTR); 296 PRINTREG32(regs, RTW_RDSAR); 297 PRINTREG32(regs, RTW_FER); 298 PRINTREG32(regs, RTW_FEMR); 299 PRINTREG32(regs, RTW_FPSR); 300 PRINTREG32(regs, RTW_FFER); 301 302 /* 16-bit registers */ 303 PRINTREG16(regs, RTW_BRSR); 304 PRINTREG16(regs, RTW_IMR); 305 PRINTREG16(regs, RTW_ISR); 306 PRINTREG16(regs, RTW_BCNITV); 307 PRINTREG16(regs, RTW_ATIMWND); 308 PRINTREG16(regs, RTW_BINTRITV); 309 PRINTREG16(regs, RTW_ATIMTRITV); 310 PRINTREG16(regs, RTW_CRC16ERR); 311 PRINTREG16(regs, RTW_CRC0); 312 PRINTREG16(regs, RTW_CRC1); 313 PRINTREG16(regs, RTW_CRC2); 314 PRINTREG16(regs, RTW_CRC3); 315 PRINTREG16(regs, RTW_CRC4); 316 PRINTREG16(regs, RTW_CWR); 317 318 /* 8-bit registers */ 319 PRINTREG8(regs, RTW_CR); 320 PRINTREG8(regs, RTW_9346CR); 321 PRINTREG8(regs, RTW_CONFIG0); 322 PRINTREG8(regs, RTW_CONFIG1); 323 PRINTREG8(regs, RTW_CONFIG2); 324 PRINTREG8(regs, RTW_MSR); 325 PRINTREG8(regs, RTW_CONFIG3); 326 PRINTREG8(regs, RTW_CONFIG4); 327 PRINTREG8(regs, RTW_TESTR); 328 PRINTREG8(regs, RTW_PSR); 329 PRINTREG8(regs, RTW_SCR); 330 PRINTREG8(regs, RTW_PHYDELAY); 331 PRINTREG8(regs, RTW_CRCOUNT); 332 PRINTREG8(regs, RTW_PHYADDR); 333 PRINTREG8(regs, RTW_PHYDATAW); 334 PRINTREG8(regs, RTW_PHYDATAR); 335 PRINTREG8(regs, RTW_CONFIG5); 336 PRINTREG8(regs, RTW_TPPOLL); 337 338 PRINTREG16(regs, RTW_BSSID16); 339 PRINTREG32(regs, RTW_BSSID32); 340 #undef PRINTREG32 341 #undef PRINTREG16 342 #undef PRINTREG8 343 } 344 #endif /* RTW_DEBUG */ 345 346 void 347 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 348 { 349 struct rtw_regs *regs = &sc->sc_regs; 350 351 uint32_t tcr; 352 tcr = RTW_READ(regs, RTW_TCR); 353 tcr &= ~RTW_TCR_LBK_MASK; 354 if (enable) 355 tcr |= RTW_TCR_LBK_CONT; 356 else 357 tcr |= RTW_TCR_LBK_NORMAL; 358 RTW_WRITE(regs, RTW_TCR, tcr); 359 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 360 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 361 rtw_txdac_enable(sc, !enable); 362 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 363 rtw_set_access(regs, RTW_ACCESS_NONE); 364 } 365 366 #ifdef RTW_DEBUG 367 static const char * 368 rtw_access_string(enum rtw_access access) 369 { 370 switch (access) { 371 case RTW_ACCESS_NONE: 372 return "none"; 373 case RTW_ACCESS_CONFIG: 374 return "config"; 375 case RTW_ACCESS_ANAPARM: 376 return "anaparm"; 377 default: 378 return "unknown"; 379 } 380 } 381 #endif /* RTW_DEBUG */ 382 383 static void 384 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 385 { 386 KASSERT(/* naccess >= RTW_ACCESS_NONE && */ 387 naccess <= RTW_ACCESS_ANAPARM); 388 KASSERT(/* regs->r_access >= RTW_ACCESS_NONE && */ 389 regs->r_access <= RTW_ACCESS_ANAPARM); 390 391 if (naccess == regs->r_access) 392 return; 393 394 switch (naccess) { 395 case RTW_ACCESS_NONE: 396 switch (regs->r_access) { 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 /*FALLTHROUGH*/ 400 case RTW_ACCESS_CONFIG: 401 rtw_config0123_enable(regs, 0); 402 /*FALLTHROUGH*/ 403 case RTW_ACCESS_NONE: 404 break; 405 } 406 break; 407 case RTW_ACCESS_CONFIG: 408 switch (regs->r_access) { 409 case RTW_ACCESS_NONE: 410 rtw_config0123_enable(regs, 1); 411 /*FALLTHROUGH*/ 412 case RTW_ACCESS_CONFIG: 413 break; 414 case RTW_ACCESS_ANAPARM: 415 rtw_anaparm_enable(regs, 0); 416 break; 417 } 418 break; 419 case RTW_ACCESS_ANAPARM: 420 switch (regs->r_access) { 421 case RTW_ACCESS_NONE: 422 rtw_config0123_enable(regs, 1); 423 /*FALLTHROUGH*/ 424 case RTW_ACCESS_CONFIG: 425 rtw_anaparm_enable(regs, 1); 426 /*FALLTHROUGH*/ 427 case RTW_ACCESS_ANAPARM: 428 break; 429 } 430 break; 431 } 432 } 433 434 void 435 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 436 { 437 rtw_set_access1(regs, access); 438 RTW_DPRINTF(RTW_DEBUG_ACCESS, 439 ("%s: access %s -> %s\n", __func__, 440 rtw_access_string(regs->r_access), 441 rtw_access_string(access))); 442 regs->r_access = access; 443 } 444 445 /* 446 * Enable registers, switch register banks. 447 */ 448 void 449 rtw_config0123_enable(struct rtw_regs *regs, int enable) 450 { 451 uint8_t ecr; 452 ecr = RTW_READ8(regs, RTW_9346CR); 453 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 454 if (enable) 455 ecr |= RTW_9346CR_EEM_CONFIG; 456 else { 457 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 458 ecr |= RTW_9346CR_EEM_NORMAL; 459 } 460 RTW_WRITE8(regs, RTW_9346CR, ecr); 461 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 462 } 463 464 /* requires rtw_config0123_enable(, 1) */ 465 void 466 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 467 { 468 uint8_t cfg3; 469 470 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 471 cfg3 |= RTW_CONFIG3_CLKRUNEN; 472 if (enable) 473 cfg3 |= RTW_CONFIG3_PARMEN; 474 else 475 cfg3 &= ~RTW_CONFIG3_PARMEN; 476 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 477 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 478 } 479 480 /* requires rtw_anaparm_enable(, 1) */ 481 void 482 rtw_txdac_enable(struct rtw_softc *sc, int enable) 483 { 484 uint32_t anaparm; 485 struct rtw_regs *regs = &sc->sc_regs; 486 487 anaparm = RTW_READ(regs, RTW_ANAPARM); 488 if (enable) 489 anaparm &= ~RTW_ANAPARM_TXDACOFF; 490 else 491 anaparm |= RTW_ANAPARM_TXDACOFF; 492 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 493 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 494 } 495 496 static inline int 497 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) 498 { 499 uint8_t cr; 500 int i; 501 502 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 503 504 RTW_WBR(regs, RTW_CR, RTW_CR); 505 506 for (i = 0; i < 1000; i++) { 507 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 508 RTW_DPRINTF(RTW_DEBUG_RESET, 509 ("%s: reset in %dus\n", dvname, i)); 510 return 0; 511 } 512 RTW_RBR(regs, RTW_CR, RTW_CR); 513 DELAY(10); /* 10us */ 514 } 515 516 printf("%s: reset failed\n", dvname); 517 return ETIMEDOUT; 518 } 519 520 static inline int 521 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) 522 { 523 uint32_t tcr; 524 525 /* from Linux driver */ 526 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 527 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK); 528 529 RTW_WRITE(regs, RTW_TCR, tcr); 530 531 RTW_WBW(regs, RTW_CR, RTW_TCR); 532 533 return rtw_chip_reset1(regs, dvname); 534 } 535 536 static int 537 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen) 538 { 539 struct ieee80211_key keycopy; 540 541 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 542 543 keycopy = *k; 544 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 545 546 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, hdrlen); 547 } 548 549 static int 550 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 551 { 552 struct rtw_softc *sc = ic->ic_ifp->if_softc; 553 u_int keyix = k->wk_keyix; 554 555 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix)); 556 557 if (keyix >= IEEE80211_WEP_NKID) 558 return 0; 559 if (k->wk_keylen != 0) 560 sc->sc_flags &= ~RTW_F_DK_VALID; 561 562 return 1; 563 } 564 565 static int 566 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 567 const u_int8_t mac[IEEE80211_ADDR_LEN]) 568 { 569 struct rtw_softc *sc = ic->ic_ifp->if_softc; 570 571 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 572 573 if (k->wk_keyix >= IEEE80211_WEP_NKID) 574 return 0; 575 576 sc->sc_flags &= ~RTW_F_DK_VALID; 577 578 return 1; 579 } 580 581 static void 582 rtw_key_update_begin(struct ieee80211com *ic) 583 { 584 #ifdef RTW_DEBUG 585 struct ifnet *ifp = ic->ic_ifp; 586 struct rtw_softc *sc = ifp->if_softc; 587 #endif 588 589 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 590 } 591 592 static void 593 rtw_key_update_end(struct ieee80211com *ic) 594 { 595 struct ifnet *ifp = ic->ic_ifp; 596 struct rtw_softc *sc = ifp->if_softc; 597 598 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 599 600 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 || 601 (sc->sc_flags & RTW_F_ENABLED) == 0 || 602 (sc->sc_flags & RTW_F_INVALID) != 0) 603 return; 604 605 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 606 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 607 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 608 (ifp->if_flags & IFF_RUNNING) != 0); 609 } 610 611 static inline int 612 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k) 613 { 614 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 615 return 0; 616 617 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) || 618 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13); 619 } 620 621 static void 622 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 623 { 624 uint8_t psr, scr; 625 int i, keylen; 626 struct rtw_regs *regs; 627 union rtw_keys *rk; 628 629 regs = &sc->sc_regs; 630 rk = &sc->sc_keys; 631 632 (void)memset(rk, 0, sizeof(rk)); 633 634 /* Temporarily use software crypto for all keys. */ 635 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 636 if (wk[i].wk_cipher == &rtw_cipher_wep) 637 wk[i].wk_cipher = &ieee80211_cipher_wep; 638 } 639 640 rtw_set_access(regs, RTW_ACCESS_CONFIG); 641 642 psr = RTW_READ8(regs, RTW_PSR); 643 scr = RTW_READ8(regs, RTW_SCR); 644 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 645 646 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 647 goto out; 648 649 for (keylen = i = 0; i < IEEE80211_WEP_NKID; i++) { 650 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i])) 651 continue; 652 if (i == txkey) { 653 keylen = wk[i].wk_keylen; 654 break; 655 } 656 keylen = MAX(keylen, wk[i].wk_keylen); 657 } 658 659 if (keylen == 5) 660 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON; 661 else if (keylen == 13) 662 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON; 663 664 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 665 if (wk[i].wk_keylen != keylen || 666 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 667 continue; 668 /* h/w will decrypt, s/w still strips headers */ 669 wk[i].wk_cipher = &rtw_cipher_wep; 670 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 671 } 672 673 out: 674 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 675 676 bus_space_write_region_stream_4(regs->r_bt, regs->r_bh, 677 RTW_DK0, rk->rk_words, __arraycount(rk->rk_words)); 678 679 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 680 BUS_SPACE_BARRIER_SYNC); 681 682 RTW_WBW(regs, RTW_DK0, RTW_PSR); 683 RTW_WRITE8(regs, RTW_PSR, psr); 684 RTW_WBW(regs, RTW_PSR, RTW_SCR); 685 RTW_WRITE8(regs, RTW_SCR, scr); 686 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 687 rtw_set_access(regs, RTW_ACCESS_NONE); 688 sc->sc_flags |= RTW_F_DK_VALID; 689 } 690 691 static inline int 692 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) 693 { 694 int i; 695 uint8_t ecr; 696 697 ecr = RTW_READ8(regs, RTW_9346CR); 698 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 699 RTW_WRITE8(regs, RTW_9346CR, ecr); 700 701 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 702 703 /* wait 25ms for completion */ 704 for (i = 0; i < 250; i++) { 705 ecr = RTW_READ8(regs, RTW_9346CR); 706 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 707 RTW_DPRINTF(RTW_DEBUG_RESET, 708 ("%s: recall EEPROM in %dus\n", dvname, i * 100)); 709 return 0; 710 } 711 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 712 DELAY(100); 713 } 714 printf("%s: recall EEPROM failed\n", dvname); 715 return ETIMEDOUT; 716 } 717 718 static inline int 719 rtw_reset(struct rtw_softc *sc) 720 { 721 int rc; 722 uint8_t config1; 723 724 sc->sc_flags &= ~RTW_F_DK_VALID; 725 726 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev.dv_xname)) != 0) 727 return rc; 728 729 rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev.dv_xname); 730 731 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 732 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 733 /* TBD turn off maximum power saving? */ 734 735 return 0; 736 } 737 738 static inline int 739 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 740 u_int ndescs) 741 { 742 int i, rc = 0; 743 for (i = 0; i < ndescs; i++) { 744 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 745 0, 0, &descs[i].ts_dmamap); 746 if (rc != 0) 747 break; 748 } 749 return rc; 750 } 751 752 static inline int 753 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 754 u_int ndescs) 755 { 756 int i, rc = 0; 757 for (i = 0; i < ndescs; i++) { 758 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 759 &descs[i].rs_dmamap); 760 if (rc != 0) 761 break; 762 } 763 return rc; 764 } 765 766 static inline void 767 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 768 u_int ndescs) 769 { 770 int i; 771 for (i = 0; i < ndescs; i++) { 772 if (descs[i].rs_dmamap != NULL) 773 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 774 } 775 } 776 777 static inline void 778 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 779 u_int ndescs) 780 { 781 int i; 782 for (i = 0; i < ndescs; i++) { 783 if (descs[i].ts_dmamap != NULL) 784 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 785 } 786 } 787 788 static inline void 789 rtw_srom_free(struct rtw_srom *sr) 790 { 791 sr->sr_size = 0; 792 if (sr->sr_content == NULL) 793 return; 794 free(sr->sr_content, M_DEVBUF); 795 sr->sr_content = NULL; 796 } 797 798 static void 799 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, 800 uint8_t *cs_threshold, enum rtw_rfchipid *rfchipid, uint32_t *rcr) 801 { 802 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 803 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 804 *rcr |= RTW_RCR_ENCS1; 805 *rfchipid = RTW_RFCHIPID_PHILIPS; 806 } 807 808 static int 809 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 810 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 811 const char *dvname) 812 { 813 int i; 814 const char *rfname, *paname; 815 char scratch[sizeof("unknown 0xXX")]; 816 uint16_t srom_version; 817 uint8_t mac[IEEE80211_ADDR_LEN]; 818 819 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 820 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 821 822 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 823 printf("%s: SROM version %d.%d", dvname, 824 srom_version >> 8, srom_version & 0xff); 825 826 if (srom_version <= 0x0101) { 827 printf(" is not understood, limping along with defaults\n"); 828 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 829 return 0; 830 } 831 printf("\n"); 832 833 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 834 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 835 836 RTW_DPRINTF(RTW_DEBUG_ATTACH, 837 ("%s: EEPROM MAC %s\n", dvname, ether_sprintf(mac))); 838 839 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 840 841 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 842 *flags |= RTW_F_ANTDIV; 843 844 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 845 * to be reversed. 846 */ 847 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 848 *flags |= RTW_F_DIGPHY; 849 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 850 *flags |= RTW_F_DFLANTB; 851 852 *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), 853 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 854 855 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0) 856 *flags |= RTW_C_RXWEP_104; 857 858 *flags |= RTW_C_RXWEP_40; /* XXX */ 859 860 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 861 switch (*rfchipid) { 862 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 863 rfname = "GCT GRF5101"; 864 paname = "Winspring WS9901"; 865 break; 866 case RTW_RFCHIPID_MAXIM: 867 rfname = "Maxim MAX2820"; /* guess */ 868 paname = "Maxim MAX2422"; /* guess */ 869 break; 870 case RTW_RFCHIPID_INTERSIL: 871 rfname = "Intersil HFA3873"; /* guess */ 872 paname = "Intersil <unknown>"; 873 break; 874 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 875 rfname = "Philips SA2400A"; 876 paname = "Philips SA2411"; 877 break; 878 case RTW_RFCHIPID_RFMD: 879 /* this is the same front-end as an atw(4)! */ 880 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 881 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 882 "SYN: Silicon Labs Si4126"; /* inferred from 883 * reference driver 884 */ 885 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 886 break; 887 case RTW_RFCHIPID_RESERVED: 888 rfname = paname = "reserved"; 889 break; 890 default: 891 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 892 rfname = paname = scratch; 893 } 894 printf("%s: RF: %s, PA: %s\n", dvname, rfname, paname); 895 896 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 897 case RTW_CONFIG0_GL_USA: 898 case _RTW_CONFIG0_GL_USA: 899 *locale = RTW_LOCALE_USA; 900 break; 901 case RTW_CONFIG0_GL_EUROPE: 902 *locale = RTW_LOCALE_EUROPE; 903 break; 904 case RTW_CONFIG0_GL_JAPAN: 905 *locale = RTW_LOCALE_JAPAN; 906 break; 907 default: 908 *locale = RTW_LOCALE_UNKNOWN; 909 break; 910 } 911 return 0; 912 } 913 914 /* Returns -1 on failure. */ 915 static int 916 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 917 const char *dvname) 918 { 919 int rc; 920 struct seeprom_descriptor sd; 921 uint8_t ecr; 922 923 (void)memset(&sd, 0, sizeof(sd)); 924 925 ecr = RTW_READ8(regs, RTW_9346CR); 926 927 if ((flags & RTW_F_9356SROM) != 0) { 928 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", dvname)); 929 sr->sr_size = 256; 930 sd.sd_chip = C56_66; 931 } else { 932 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", dvname)); 933 sr->sr_size = 128; 934 sd.sd_chip = C46; 935 } 936 937 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 938 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 939 ecr |= RTW_9346CR_EEM_PROGRAM; 940 941 RTW_WRITE8(regs, RTW_9346CR, ecr); 942 943 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 944 945 if (sr->sr_content == NULL) { 946 printf("%s: unable to allocate SROM buffer\n", dvname); 947 return ENOMEM; 948 } 949 950 (void)memset(sr->sr_content, 0, sr->sr_size); 951 952 /* RTL8180 has a single 8-bit register for controlling the 953 * 93cx6 SROM. There is no "ready" bit. The RTL8180 954 * input/output sense is the reverse of read_seeprom's. 955 */ 956 sd.sd_tag = regs->r_bt; 957 sd.sd_bsh = regs->r_bh; 958 sd.sd_regsize = 1; 959 sd.sd_control_offset = RTW_9346CR; 960 sd.sd_status_offset = RTW_9346CR; 961 sd.sd_dataout_offset = RTW_9346CR; 962 sd.sd_CK = RTW_9346CR_EESK; 963 sd.sd_CS = RTW_9346CR_EECS; 964 sd.sd_DI = RTW_9346CR_EEDO; 965 sd.sd_DO = RTW_9346CR_EEDI; 966 /* make read_seeprom enter EEPROM read/write mode */ 967 sd.sd_MS = ecr; 968 sd.sd_RDY = 0; 969 970 /* TBD bus barriers */ 971 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 972 printf("%s: could not read SROM\n", dvname); 973 free(sr->sr_content, M_DEVBUF); 974 sr->sr_content = NULL; 975 return -1; /* XXX */ 976 } 977 978 /* end EEPROM read/write mode */ 979 RTW_WRITE8(regs, RTW_9346CR, 980 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 981 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 982 983 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0) 984 return rc; 985 986 #ifdef RTW_DEBUG 987 { 988 int i; 989 RTW_DPRINTF(RTW_DEBUG_ATTACH, 990 ("\n%s: serial ROM:\n\t", dvname)); 991 for (i = 0; i < sr->sr_size/2; i++) { 992 if (((i % 8) == 0) && (i != 0)) 993 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 994 RTW_DPRINTF(RTW_DEBUG_ATTACH, 995 (" %04x", sr->sr_content[i])); 996 } 997 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 998 } 999 #endif /* RTW_DEBUG */ 1000 return 0; 1001 } 1002 1003 static void 1004 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 1005 const char *dvname) 1006 { 1007 uint8_t cfg4; 1008 const char *method; 1009 1010 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 1011 1012 switch (rfchipid) { 1013 default: 1014 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 1015 method = "fallback"; 1016 break; 1017 case RTW_RFCHIPID_INTERSIL: 1018 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1019 method = "Intersil"; 1020 break; 1021 case RTW_RFCHIPID_PHILIPS: 1022 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1023 method = "Philips"; 1024 break; 1025 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1026 case RTW_RFCHIPID_RFMD: 1027 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1028 method = "RFMD"; 1029 break; 1030 } 1031 1032 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1033 1034 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1035 1036 RTW_DPRINTF(RTW_DEBUG_INIT, 1037 ("%s: %s RF programming method, %#02x\n", dvname, method, 1038 RTW_READ8(regs, RTW_CONFIG4))); 1039 } 1040 1041 static inline void 1042 rtw_init_channels(enum rtw_locale locale, 1043 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], 1044 const char *dvname) 1045 { 1046 int i; 1047 const char *name = NULL; 1048 #define ADD_CHANNEL(_chans, _chan) do { \ 1049 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1050 (*_chans)[_chan].ic_freq = \ 1051 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1052 } while (0) 1053 1054 switch (locale) { 1055 case RTW_LOCALE_USA: /* 1-11 */ 1056 name = "USA"; 1057 for (i = 1; i <= 11; i++) 1058 ADD_CHANNEL(chans, i); 1059 break; 1060 case RTW_LOCALE_JAPAN: /* 1-14 */ 1061 name = "Japan"; 1062 ADD_CHANNEL(chans, 14); 1063 for (i = 1; i <= 14; i++) 1064 ADD_CHANNEL(chans, i); 1065 break; 1066 case RTW_LOCALE_EUROPE: /* 1-13 */ 1067 name = "Europe"; 1068 for (i = 1; i <= 13; i++) 1069 ADD_CHANNEL(chans, i); 1070 break; 1071 default: /* 10-11 allowed by most countries */ 1072 name = "<unknown>"; 1073 for (i = 10; i <= 11; i++) 1074 ADD_CHANNEL(chans, i); 1075 break; 1076 } 1077 printf("%s: Geographic Location %s\n", dvname, name); 1078 #undef ADD_CHANNEL 1079 } 1080 1081 1082 static inline void 1083 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale) 1084 { 1085 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1086 1087 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1088 case RTW_CONFIG0_GL_USA: 1089 case _RTW_CONFIG0_GL_USA: 1090 *locale = RTW_LOCALE_USA; 1091 break; 1092 case RTW_CONFIG0_GL_JAPAN: 1093 *locale = RTW_LOCALE_JAPAN; 1094 break; 1095 case RTW_CONFIG0_GL_EUROPE: 1096 *locale = RTW_LOCALE_EUROPE; 1097 break; 1098 default: 1099 *locale = RTW_LOCALE_UNKNOWN; 1100 break; 1101 } 1102 } 1103 1104 static inline int 1105 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1106 const char *dvname) 1107 { 1108 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1109 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1110 }; 1111 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1112 idr1 = RTW_READ(regs, RTW_IDR1); 1113 1114 (*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7)); 1115 (*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15)); 1116 (*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23)); 1117 (*addr)[3] = __SHIFTOUT(idr0, __BITS(24 ,31)); 1118 1119 (*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7)); 1120 (*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15)); 1121 1122 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1123 printf("%s: could not get mac address, attach failed\n", 1124 dvname); 1125 return ENXIO; 1126 } 1127 1128 printf("%s: 802.11 address %s\n", dvname, ether_sprintf(*addr)); 1129 1130 return 0; 1131 } 1132 1133 static uint8_t 1134 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1135 struct ieee80211_channel *chan) 1136 { 1137 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1138 KASSERT(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14); 1139 return RTW_SR_GET(sr, idx); 1140 } 1141 1142 static void 1143 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1144 { 1145 int pri; 1146 /* nfree: the number of free descriptors in each ring. 1147 * The beacon ring is a special case: I do not let the 1148 * driver use all of the descriptors on the beacon ring. 1149 * The reasons are two-fold: 1150 * 1151 * (1) A BEACON descriptor's OWN bit is (apparently) not 1152 * updated, so the driver cannot easily know if the descriptor 1153 * belongs to it, or if it is racing the NIC. If the NIC 1154 * does not OWN every descriptor, then the driver can safely 1155 * update the descriptors when RTW_TBDA points at tdb_next. 1156 * 1157 * (2) I hope that the NIC will process more than one BEACON 1158 * descriptor in a single beacon interval, since that will 1159 * enable multiple-BSS support. Since the NIC does not 1160 * clear the OWN bit, there is no natural place for it to 1161 * stop processing BEACON desciptors. Maybe it will *not* 1162 * stop processing them! I do not want to chance the NIC 1163 * looping around and around a saturated beacon ring, so 1164 * I will leave one descriptor unOWNed at all times. 1165 */ 1166 u_int nfree[RTW_NTXPRI] = 1167 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, 1168 RTW_NTXDESCBCN - 1}; 1169 1170 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1171 tdb[pri].tdb_nfree = nfree[pri]; 1172 tdb[pri].tdb_next = 0; 1173 } 1174 } 1175 1176 static int 1177 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1178 { 1179 int i; 1180 struct rtw_txsoft *ts; 1181 1182 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1183 SIMPLEQ_INIT(&tsb->tsb_freeq); 1184 for (i = 0; i < tsb->tsb_ndesc; i++) { 1185 ts = &tsb->tsb_desc[i]; 1186 ts->ts_mbuf = NULL; 1187 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1188 } 1189 tsb->tsb_tx_timer = 0; 1190 return 0; 1191 } 1192 1193 static void 1194 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1195 { 1196 int pri; 1197 for (pri = 0; pri < RTW_NTXPRI; pri++) 1198 rtw_txsoft_blk_init(&tsb[pri]); 1199 } 1200 1201 static inline void 1202 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1203 { 1204 KASSERT(nsync <= rdb->rdb_ndesc); 1205 /* sync to end of ring */ 1206 if (desc0 + nsync > rdb->rdb_ndesc) { 1207 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1208 offsetof(struct rtw_descs, hd_rx[desc0]), 1209 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1210 nsync -= (rdb->rdb_ndesc - desc0); 1211 desc0 = 0; 1212 } 1213 1214 KASSERT(desc0 < rdb->rdb_ndesc); 1215 KASSERT(nsync <= rdb->rdb_ndesc); 1216 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1217 1218 /* sync what remains */ 1219 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1220 offsetof(struct rtw_descs, hd_rx[desc0]), 1221 sizeof(struct rtw_rxdesc) * nsync, ops); 1222 } 1223 1224 static void 1225 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1226 { 1227 /* sync to end of ring */ 1228 if (desc0 + nsync > tdb->tdb_ndesc) { 1229 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1230 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1231 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1232 ops); 1233 nsync -= (tdb->tdb_ndesc - desc0); 1234 desc0 = 0; 1235 } 1236 1237 /* sync what remains */ 1238 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1239 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1240 sizeof(struct rtw_txdesc) * nsync, ops); 1241 } 1242 1243 static void 1244 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1245 { 1246 int pri; 1247 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1248 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1249 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1250 } 1251 } 1252 1253 static void 1254 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1255 { 1256 int i; 1257 struct rtw_rxsoft *rs; 1258 1259 for (i = 0; i < RTW_RXQLEN; i++) { 1260 rs = &desc[i]; 1261 if (rs->rs_mbuf == NULL) 1262 continue; 1263 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1264 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1265 bus_dmamap_unload(dmat, rs->rs_dmamap); 1266 m_freem(rs->rs_mbuf); 1267 rs->rs_mbuf = NULL; 1268 } 1269 } 1270 1271 static inline int 1272 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1273 { 1274 int rc; 1275 struct mbuf *m; 1276 1277 MGETHDR(m, M_DONTWAIT, MT_DATA); 1278 if (m == NULL) 1279 return ENOBUFS; 1280 1281 MCLGET(m, M_DONTWAIT); 1282 if ((m->m_flags & M_EXT) == 0) { 1283 m_freem(m); 1284 return ENOBUFS; 1285 } 1286 1287 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1288 1289 if (rs->rs_mbuf != NULL) 1290 bus_dmamap_unload(dmat, rs->rs_dmamap); 1291 1292 rs->rs_mbuf = NULL; 1293 1294 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1295 if (rc != 0) { 1296 m_freem(m); 1297 return -1; 1298 } 1299 1300 rs->rs_mbuf = m; 1301 1302 return 0; 1303 } 1304 1305 static int 1306 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1307 int *ndesc, const char *dvname) 1308 { 1309 int i, rc = 0; 1310 struct rtw_rxsoft *rs; 1311 1312 for (i = 0; i < RTW_RXQLEN; i++) { 1313 rs = &desc[i]; 1314 /* we're in rtw_init, so there should be no mbufs allocated */ 1315 KASSERT(rs->rs_mbuf == NULL); 1316 #ifdef RTW_DEBUG 1317 if (i == rtw_rxbufs_limit) { 1318 printf("%s: TEST hit %d-buffer limit\n", dvname, i); 1319 rc = ENOBUFS; 1320 break; 1321 } 1322 #endif /* RTW_DEBUG */ 1323 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1324 printf("%s: rtw_rxsoft_alloc failed, %d buffers, " 1325 "rc %d\n", dvname, i, rc); 1326 break; 1327 } 1328 } 1329 *ndesc = i; 1330 return rc; 1331 } 1332 1333 static inline void 1334 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1335 int idx, int kick) 1336 { 1337 int is_last = (idx == rdb->rdb_ndesc - 1); 1338 uint32_t ctl, octl, obuf; 1339 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1340 1341 /* sync the mbuf before the descriptor */ 1342 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1343 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1344 1345 obuf = rd->rd_buf; 1346 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1347 1348 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1349 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1350 1351 if (is_last) 1352 ctl |= RTW_RXCTL_EOR; 1353 1354 octl = rd->rd_ctl; 1355 rd->rd_ctl = htole32(ctl); 1356 1357 RTW_DPRINTF( 1358 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1359 : RTW_DEBUG_RECV_DESC, 1360 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1361 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1362 le32toh(rd->rd_ctl))); 1363 1364 /* sync the descriptor */ 1365 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1366 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1367 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1368 } 1369 1370 static void 1371 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1372 { 1373 int i; 1374 struct rtw_rxdesc *rd; 1375 struct rtw_rxsoft *rs; 1376 1377 for (i = 0; i < rdb->rdb_ndesc; i++) { 1378 rd = &rdb->rdb_desc[i]; 1379 rs = &ctl[i]; 1380 rtw_rxdesc_init(rdb, rs, i, kick); 1381 } 1382 } 1383 1384 static void 1385 rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable) 1386 { 1387 struct rtw_regs *regs = &sc->sc_regs; 1388 uint8_t cr; 1389 1390 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1391 enable ? "enable" : "disable", flags)); 1392 1393 cr = RTW_READ8(regs, RTW_CR); 1394 1395 /* XXX reference source does not enable MULRW */ 1396 /* enable PCI Read/Write Multiple */ 1397 cr |= RTW_CR_MULRW; 1398 1399 /* The receive engine will always start at RDSAR. */ 1400 if (enable && (flags & ~cr & RTW_CR_RE)) { 1401 struct rtw_rxdesc_blk *rdb; 1402 rdb = &sc->sc_rxdesc_blk; 1403 rdb->rdb_next = 0; 1404 } 1405 1406 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1407 if (enable) 1408 cr |= flags; 1409 else 1410 cr &= ~flags; 1411 RTW_WRITE8(regs, RTW_CR, cr); 1412 RTW_SYNC(regs, RTW_CR, RTW_CR); 1413 1414 #ifdef RTW_DIAG 1415 if (cr & RTW_CR_TE) 1416 rtw_txring_fixup(sc, __func__, __LINE__); 1417 #endif 1418 } 1419 1420 static void 1421 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1422 { 1423 #define IS_BEACON(__fc0) \ 1424 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1425 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1426 1427 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1428 * hardware -> net80211 1429 */ 1430 u_int next, nproc = 0; 1431 int hwrate, len, rate, rssi, sq; 1432 uint32_t hrssi, hstat, htsfth, htsftl; 1433 struct rtw_rxdesc *rd; 1434 struct rtw_rxsoft *rs; 1435 struct rtw_rxdesc_blk *rdb; 1436 struct mbuf *m; 1437 struct ifnet *ifp = &sc->sc_if; 1438 1439 struct ieee80211_node *ni; 1440 struct ieee80211_frame_min *wh; 1441 1442 rdb = &sc->sc_rxdesc_blk; 1443 1444 for (next = rdb->rdb_next; ; next = rdb->rdb_next) { 1445 KASSERT(next < rdb->rdb_ndesc); 1446 1447 rtw_rxdescs_sync(rdb, next, 1, 1448 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1449 rd = &rdb->rdb_desc[next]; 1450 rs = &sc->sc_rxsoft[next]; 1451 1452 hstat = le32toh(rd->rd_stat); 1453 hrssi = le32toh(rd->rd_rssi); 1454 htsfth = le32toh(rd->rd_tsfth); 1455 htsftl = le32toh(rd->rd_tsftl); 1456 1457 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1458 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1459 __func__, next, hstat, hrssi, htsfth, htsftl)); 1460 1461 ++nproc; 1462 1463 /* still belongs to NIC */ 1464 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1465 rtw_rxdescs_sync(rdb, next, 1, BUS_DMASYNC_PREREAD); 1466 break; 1467 } 1468 1469 /* ieee80211_input() might reset the receive engine 1470 * (e.g. by indirectly calling rtw_tune()), so save 1471 * the next pointer here and retrieve it again on 1472 * the next round. 1473 */ 1474 rdb->rdb_next = (next + 1) % rdb->rdb_ndesc; 1475 1476 #ifdef RTW_DEBUG 1477 #define PRINTSTAT(flag) do { \ 1478 if ((hstat & flag) != 0) { \ 1479 printf("%s" #flag, delim); \ 1480 delim = ","; \ 1481 } \ 1482 } while (0) 1483 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1484 const char *delim = "<"; 1485 printf("%s: ", sc->sc_dev.dv_xname); 1486 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1487 printf("status %08x", hstat); 1488 PRINTSTAT(RTW_RXSTAT_SPLCP); 1489 PRINTSTAT(RTW_RXSTAT_MAR); 1490 PRINTSTAT(RTW_RXSTAT_PAR); 1491 PRINTSTAT(RTW_RXSTAT_BAR); 1492 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1493 PRINTSTAT(RTW_RXSTAT_CRC32); 1494 PRINTSTAT(RTW_RXSTAT_ICV); 1495 printf(">, "); 1496 } 1497 } 1498 #endif /* RTW_DEBUG */ 1499 1500 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1501 printf("%s: DMA error/FIFO overflow %08" PRIx32 ", " 1502 "rx descriptor %d\n", sc->sc_dev.dv_xname, 1503 hstat, next); 1504 ifp->if_ierrors++; 1505 goto next; 1506 } 1507 1508 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); 1509 if (len < IEEE80211_MIN_LEN) { 1510 sc->sc_ic.ic_stats.is_rx_tooshort++; 1511 goto next; 1512 } 1513 KASSERT(len <= rs->rs_mbuf->m_pkthdr.len); 1514 KASSERT(len <= rs->rs_mbuf->m_len); 1515 1516 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); 1517 if (hwrate >= __arraycount(ratetbl)) { 1518 printf("%s: unknown rate #%" __PRIuBITS "\n", 1519 sc->sc_dev.dv_xname, 1520 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); 1521 ifp->if_ierrors++; 1522 goto next; 1523 } 1524 rate = ratetbl[hwrate]; 1525 1526 #ifdef RTW_DEBUG 1527 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1528 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1529 (rate * 5) % 10, htsfth, htsftl)); 1530 #endif /* RTW_DEBUG */ 1531 1532 /* if bad flags, skip descriptor */ 1533 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1534 printf("%s: too many rx segments, " 1535 "next=%d, %08" PRIx32 "\n", 1536 sc->sc_dev.dv_xname, next, hstat); 1537 goto next; 1538 } 1539 1540 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1541 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1542 1543 m = rs->rs_mbuf; 1544 1545 /* if temporarily out of memory, re-use mbuf */ 1546 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1547 case 0: 1548 break; 1549 case ENOBUFS: 1550 printf("%s: rtw_rxsoft_alloc(, %d) failed, " 1551 "dropping packet\n", sc->sc_dev.dv_xname, next); 1552 goto next; 1553 default: 1554 /* XXX shorten rx ring, instead? */ 1555 panic("%s: could not load DMA map\n", 1556 sc->sc_dev.dv_xname); 1557 } 1558 1559 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ); 1560 1561 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1562 rssi = UINT8_MAX - sq; 1563 else { 1564 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); 1565 /* TBD find out each front-end's LNA gain in the 1566 * front-end's units 1567 */ 1568 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1569 rssi |= 0x80; 1570 } 1571 1572 /* Note well: now we cannot recycle the rs_mbuf unless 1573 * we restore its original length. 1574 */ 1575 m->m_pkthdr.rcvif = ifp; 1576 m->m_pkthdr.len = m->m_len = len; 1577 1578 wh = mtod(m, struct ieee80211_frame_min *); 1579 1580 if (!IS_BEACON(wh->i_fc[0])) 1581 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1582 1583 sc->sc_tsfth = htsfth; 1584 1585 #ifdef RTW_DEBUG 1586 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 1587 (IFF_DEBUG|IFF_LINK2)) { 1588 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1589 rate, rssi); 1590 } 1591 #endif /* RTW_DEBUG */ 1592 1593 #if NBPFILTER > 0 1594 if (sc->sc_radiobpf != NULL) { 1595 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1596 1597 rr->rr_tsft = 1598 htole64(((uint64_t)htsfth << 32) | htsftl); 1599 1600 rr->rr_flags = IEEE80211_RADIOTAP_F_FCS; 1601 1602 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1603 rr->rr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1604 if ((hstat & RTW_RXSTAT_CRC32) != 0) 1605 rr->rr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 1606 1607 rr->rr_rate = rate; 1608 1609 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1610 rr->rr_u.u_philips.p_antsignal = rssi; 1611 else { 1612 rr->rr_u.u_other.o_antsignal = rssi; 1613 rr->rr_u.u_other.o_barker_lock = 1614 htole16(UINT8_MAX - sq); 1615 } 1616 1617 bpf_mtap2(sc->sc_radiobpf, rr, 1618 sizeof(sc->sc_rxtapu), m); 1619 } 1620 #endif /* NBPFILTER > 0 */ 1621 1622 if ((hstat & RTW_RXSTAT_RES) != 0) { 1623 m_freem(m); 1624 goto next; 1625 } 1626 1627 /* CRC is included with the packet; trim it off. */ 1628 m_adj(m, -IEEE80211_CRC_LEN); 1629 1630 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1631 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1632 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1633 ieee80211_free_node(ni); 1634 next: 1635 rtw_rxdesc_init(rdb, rs, next, 0); 1636 } 1637 #undef IS_BEACON 1638 } 1639 1640 static void 1641 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1642 struct rtw_txsoft *ts) 1643 { 1644 struct mbuf *m; 1645 struct ieee80211_node *ni; 1646 1647 m = ts->ts_mbuf; 1648 ni = ts->ts_ni; 1649 KASSERT(m != NULL); 1650 KASSERT(ni != NULL); 1651 ts->ts_mbuf = NULL; 1652 ts->ts_ni = NULL; 1653 1654 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1655 BUS_DMASYNC_POSTWRITE); 1656 bus_dmamap_unload(dmat, ts->ts_dmamap); 1657 m_freem(m); 1658 ieee80211_free_node(ni); 1659 } 1660 1661 static void 1662 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1663 struct rtw_txsoft_blk *tsb) 1664 { 1665 struct rtw_txsoft *ts; 1666 1667 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1668 rtw_txsoft_release(dmat, ic, ts); 1669 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1670 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1671 } 1672 tsb->tsb_tx_timer = 0; 1673 } 1674 1675 static inline void 1676 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1677 struct rtw_txsoft *ts, int ndesc) 1678 { 1679 uint32_t hstat; 1680 int data_retry, rts_retry; 1681 struct rtw_txdesc *tdn; 1682 const char *condstring; 1683 struct ifnet *ifp = &sc->sc_if; 1684 1685 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1686 1687 tdb->tdb_nfree += ndesc; 1688 1689 tdn = &tdb->tdb_desc[ts->ts_last]; 1690 1691 hstat = le32toh(tdn->td_stat); 1692 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1693 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); 1694 1695 ifp->if_collisions += rts_retry + data_retry; 1696 1697 if ((hstat & RTW_TXSTAT_TOK) != 0) 1698 condstring = "ok"; 1699 else { 1700 ifp->if_oerrors++; 1701 condstring = "error"; 1702 } 1703 1704 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1705 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1706 sc->sc_dev.dv_xname, ts, ts->ts_first, ts->ts_last, 1707 condstring, rts_retry, data_retry)); 1708 } 1709 1710 static void 1711 rtw_reset_oactive(struct rtw_softc *sc) 1712 { 1713 short oflags; 1714 int pri; 1715 struct rtw_txsoft_blk *tsb; 1716 struct rtw_txdesc_blk *tdb; 1717 oflags = sc->sc_if.if_flags; 1718 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1719 tsb = &sc->sc_txsoft_blk[pri]; 1720 tdb = &sc->sc_txdesc_blk[pri]; 1721 if (!SIMPLEQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0) 1722 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1723 } 1724 if (oflags != sc->sc_if.if_flags) { 1725 DPRINTF(sc, RTW_DEBUG_OACTIVE, 1726 ("%s: reset OACTIVE\n", __func__)); 1727 } 1728 } 1729 1730 /* Collect transmitted packets. */ 1731 static void 1732 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1733 struct rtw_txdesc_blk *tdb, int force) 1734 { 1735 int ndesc; 1736 struct rtw_txsoft *ts; 1737 1738 #ifdef RTW_DEBUG 1739 rtw_dump_rings(sc); 1740 #endif 1741 1742 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1743 /* If we're clearing a failed transmission, only clear 1744 up to the last packet the hardware has processed. */ 1745 if (ts->ts_first == rtw_txring_next(&sc->sc_regs, tdb)) 1746 break; 1747 1748 ndesc = 1 + ts->ts_last - ts->ts_first; 1749 if (ts->ts_last < ts->ts_first) 1750 ndesc += tdb->tdb_ndesc; 1751 1752 KASSERT(ndesc > 0); 1753 1754 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1755 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1756 1757 if (force) { 1758 int next; 1759 #ifdef RTW_DIAG 1760 printf("%s: clearing packet, stats", __func__); 1761 #endif 1762 for (next = ts->ts_first; ; 1763 next = RTW_NEXT_IDX(tdb, next)) { 1764 #ifdef RTW_DIAG 1765 printf(" %" PRIx32 "/%" PRIx32 "/%" PRIx32 "/%" PRIu32 "/%" PRIx32, le32toh(tdb->tdb_desc[next].td_stat), le32toh(tdb->tdb_desc[next].td_ctl1), le32toh(tdb->tdb_desc[next].td_buf), le32toh(tdb->tdb_desc[next].td_len), le32toh(tdb->tdb_desc[next].td_next)); 1766 #endif 1767 tdb->tdb_desc[next].td_stat &= 1768 ~htole32(RTW_TXSTAT_OWN); 1769 if (next == ts->ts_last) 1770 break; 1771 } 1772 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1773 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1774 #ifdef RTW_DIAG 1775 next = RTW_NEXT_IDX(tdb, next); 1776 printf(" -> end %u stat %" PRIx32 ", was %u\n", next, 1777 le32toh(tdb->tdb_desc[next].td_stat), 1778 rtw_txring_next(&sc->sc_regs, tdb)); 1779 #endif 1780 } else if ((tdb->tdb_desc[ts->ts_last].td_stat & 1781 htole32(RTW_TXSTAT_OWN)) != 0) { 1782 rtw_txdescs_sync(tdb, ts->ts_last, 1, 1783 BUS_DMASYNC_PREREAD); 1784 break; 1785 } 1786 1787 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1788 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1789 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1790 } 1791 1792 /* no more pending transmissions, cancel watchdog */ 1793 if (ts == NULL) 1794 tsb->tsb_tx_timer = 0; 1795 rtw_reset_oactive(sc); 1796 } 1797 1798 static void 1799 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1800 { 1801 int pri; 1802 struct rtw_txsoft_blk *tsb; 1803 struct rtw_txdesc_blk *tdb; 1804 struct ifnet *ifp = &sc->sc_if; 1805 1806 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1807 tsb = &sc->sc_txsoft_blk[pri]; 1808 tdb = &sc->sc_txdesc_blk[pri]; 1809 rtw_collect_txring(sc, tsb, tdb, 0); 1810 } 1811 1812 if ((isr & RTW_INTR_TX) != 0) 1813 rtw_start(ifp); 1814 1815 return; 1816 } 1817 1818 static void 1819 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1820 { 1821 u_int next; 1822 uint32_t tsfth, tsftl; 1823 struct ieee80211com *ic; 1824 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN]; 1825 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN]; 1826 struct mbuf *m; 1827 1828 tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH); 1829 tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1830 1831 if ((isr & (RTW_INTR_TBDOK|RTW_INTR_TBDER)) != 0) { 1832 next = rtw_txring_next(&sc->sc_regs, tdb); 1833 RTW_DPRINTF(RTW_DEBUG_BEACON, 1834 ("%s: beacon ring %sprocessed, isr = %#04" PRIx16 1835 ", next %u expected %u, %" PRIu64 "\n", __func__, 1836 (next == tdb->tdb_next) ? "" : "un", isr, next, 1837 tdb->tdb_next, (uint64_t)tsfth << 32 | tsftl)); 1838 if ((RTW_READ8(&sc->sc_regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0) 1839 rtw_collect_txring(sc, tsb, tdb, 1); 1840 } 1841 /* Start beacon transmission. */ 1842 1843 if ((isr & RTW_INTR_BCNINT) != 0 && 1844 sc->sc_ic.ic_state == IEEE80211_S_RUN && 1845 SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) { 1846 RTW_DPRINTF(RTW_DEBUG_BEACON, 1847 ("%s: beacon prep. time, isr = %#04" PRIx16 1848 ", %16" PRIu64 "\n", __func__, isr, 1849 (uint64_t)tsfth << 32 | tsftl)); 1850 ic = &sc->sc_ic; 1851 m = rtw_beacon_alloc(sc, ic->ic_bss); 1852 1853 if (m == NULL) { 1854 printf("%s: could not allocate beacon\n", 1855 sc->sc_dev.dv_xname); 1856 return; 1857 } 1858 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss); 1859 IF_ENQUEUE(&sc->sc_beaconq, m); 1860 rtw_start(&sc->sc_if); 1861 } 1862 } 1863 1864 static void 1865 rtw_intr_atim(struct rtw_softc *sc) 1866 { 1867 /* TBD */ 1868 return; 1869 } 1870 1871 #ifdef RTW_DEBUG 1872 static void 1873 rtw_dump_rings(struct rtw_softc *sc) 1874 { 1875 struct rtw_txdesc_blk *tdb; 1876 struct rtw_rxdesc *rd; 1877 struct rtw_rxdesc_blk *rdb; 1878 int desc, pri; 1879 1880 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1881 return; 1882 1883 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1884 tdb = &sc->sc_txdesc_blk[pri]; 1885 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1886 tdb->tdb_ndesc, tdb->tdb_nfree); 1887 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1888 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1889 } 1890 1891 rdb = &sc->sc_rxdesc_blk; 1892 1893 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1894 rd = &rdb->rdb_desc[desc]; 1895 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1896 "rsvd1/tsfth %08x\n", __func__, 1897 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1898 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1899 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1900 } 1901 } 1902 #endif /* RTW_DEBUG */ 1903 1904 static void 1905 rtw_hwring_setup(struct rtw_softc *sc) 1906 { 1907 int pri; 1908 struct rtw_regs *regs = &sc->sc_regs; 1909 struct rtw_txdesc_blk *tdb; 1910 1911 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_basereg = RTW_TLPDA; 1912 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_base = RTW_RING_BASE(sc, hd_txlo); 1913 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_basereg = RTW_TNPDA; 1914 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_base = RTW_RING_BASE(sc, hd_txmd); 1915 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_basereg = RTW_THPDA; 1916 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_base = RTW_RING_BASE(sc, hd_txhi); 1917 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_basereg = RTW_TBDA; 1918 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_base = RTW_RING_BASE(sc, hd_bcn); 1919 1920 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1921 tdb = &sc->sc_txdesc_blk[pri]; 1922 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base); 1923 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1924 ("%s: reg[tdb->tdb_basereg] <- %" PRIxPTR "\n", __func__, 1925 (uintptr_t)tdb->tdb_base)); 1926 } 1927 1928 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1929 1930 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1931 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1932 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1933 1934 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1935 1936 } 1937 1938 static int 1939 rtw_swring_setup(struct rtw_softc *sc) 1940 { 1941 int rc; 1942 struct rtw_rxdesc_blk *rdb; 1943 1944 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1945 1946 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1947 1948 rdb = &sc->sc_rxdesc_blk; 1949 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1950 sc->sc_dev.dv_xname)) != 0 && rdb->rdb_ndesc == 0) { 1951 printf("%s: could not allocate rx buffers\n", 1952 sc->sc_dev.dv_xname); 1953 return rc; 1954 } 1955 1956 rdb = &sc->sc_rxdesc_blk; 1957 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1958 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1959 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1960 rdb->rdb_next = 0; 1961 1962 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1963 return 0; 1964 } 1965 1966 static void 1967 rtw_txdesc_blk_init(struct rtw_txdesc_blk *tdb) 1968 { 1969 int i; 1970 1971 (void)memset(tdb->tdb_desc, 0, 1972 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 1973 for (i = 0; i < tdb->tdb_ndesc; i++) 1974 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 1975 } 1976 1977 static u_int 1978 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb) 1979 { 1980 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) / 1981 sizeof(struct rtw_txdesc); 1982 } 1983 1984 #ifdef RTW_DIAG 1985 static void 1986 rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln) 1987 { 1988 int pri; 1989 u_int next; 1990 struct rtw_txdesc_blk *tdb; 1991 struct rtw_regs *regs = &sc->sc_regs; 1992 1993 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1994 int i; 1995 tdb = &sc->sc_txdesc_blk[pri]; 1996 next = rtw_txring_next(regs, tdb); 1997 if (tdb->tdb_next == next) 1998 continue; 1999 for (i = 0; next != tdb->tdb_next; 2000 next = RTW_NEXT_IDX(tdb, next), i++) { 2001 if ((tdb->tdb_desc[next].td_stat & htole32(RTW_TXSTAT_OWN)) == 0) 2002 break; 2003 } 2004 printf("%s:%d: tx-ring %d expected next %u, read %u+%d -> %s\n", fn, 2005 ln, pri, tdb->tdb_next, next, i, tdb->tdb_next == next ? "okay" : "BAD"); 2006 if (tdb->tdb_next == next) 2007 continue; 2008 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1); 2009 } 2010 } 2011 #endif 2012 2013 static void 2014 rtw_txdescs_reset(struct rtw_softc *sc) 2015 { 2016 int pri; 2017 struct rtw_txsoft_blk *tsb; 2018 struct rtw_txdesc_blk *tdb; 2019 2020 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2021 tsb = &sc->sc_txsoft_blk[pri]; 2022 tdb = &sc->sc_txdesc_blk[pri]; 2023 rtw_collect_txring(sc, tsb, tdb, 1); 2024 #ifdef RTW_DIAG 2025 if (!SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 2026 printf("%s: packets left in ring %d\n", __func__, pri); 2027 #endif 2028 } 2029 } 2030 2031 static void 2032 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 2033 { 2034 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 2035 2036 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: cleaning up xmit, isr %" PRIx16 2037 "\n", sc->sc_dev.dv_xname, isr)); 2038 2039 #ifdef RTW_DEBUG 2040 rtw_dump_rings(sc); 2041 #endif /* RTW_DEBUG */ 2042 2043 /* Collect tx'd packets. XXX let's hope this stops the transmit 2044 * timeouts. 2045 */ 2046 rtw_txdescs_reset(sc); 2047 2048 #ifdef RTW_DEBUG 2049 rtw_dump_rings(sc); 2050 #endif /* RTW_DEBUG */ 2051 } 2052 2053 static inline void 2054 rtw_suspend_ticks(struct rtw_softc *sc) 2055 { 2056 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2057 ("%s: suspending ticks\n", sc->sc_dev.dv_xname)); 2058 sc->sc_do_tick = 0; 2059 } 2060 2061 static inline void 2062 rtw_resume_ticks(struct rtw_softc *sc) 2063 { 2064 uint32_t tsftrl0, tsftrl1, next_tick; 2065 2066 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2067 2068 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2069 next_tick = tsftrl1 + 1000000; 2070 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 2071 2072 sc->sc_do_tick = 1; 2073 2074 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2075 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 2076 sc->sc_dev.dv_xname, tsftrl1 - tsftrl0, tsftrl1, next_tick)); 2077 } 2078 2079 static void 2080 rtw_intr_timeout(struct rtw_softc *sc) 2081 { 2082 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", sc->sc_dev.dv_xname)); 2083 if (sc->sc_do_tick) 2084 rtw_resume_ticks(sc); 2085 return; 2086 } 2087 2088 int 2089 rtw_intr(void *arg) 2090 { 2091 int i; 2092 struct rtw_softc *sc = arg; 2093 struct rtw_regs *regs = &sc->sc_regs; 2094 uint16_t isr; 2095 struct ifnet *ifp = &sc->sc_if; 2096 2097 /* 2098 * If the interface isn't running, the interrupt couldn't 2099 * possibly have come from us. 2100 */ 2101 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 2102 (ifp->if_flags & IFF_RUNNING) == 0 || 2103 !device_is_active(&sc->sc_dev)) { 2104 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", sc->sc_dev.dv_xname)); 2105 return (0); 2106 } 2107 2108 for (i = 0; i < 10; i++) { 2109 isr = RTW_READ16(regs, RTW_ISR); 2110 2111 RTW_WRITE16(regs, RTW_ISR, isr); 2112 RTW_WBR(regs, RTW_ISR, RTW_ISR); 2113 2114 if (sc->sc_intr_ack != NULL) 2115 (*sc->sc_intr_ack)(regs); 2116 2117 if (isr == 0) 2118 break; 2119 2120 #ifdef RTW_DEBUG 2121 #define PRINTINTR(flag) do { \ 2122 if ((isr & flag) != 0) { \ 2123 printf("%s" #flag, delim); \ 2124 delim = ","; \ 2125 } \ 2126 } while (0) 2127 2128 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 2129 const char *delim = "<"; 2130 2131 printf("%s: reg[ISR] = %x", sc->sc_dev.dv_xname, isr); 2132 2133 PRINTINTR(RTW_INTR_TXFOVW); 2134 PRINTINTR(RTW_INTR_TIMEOUT); 2135 PRINTINTR(RTW_INTR_BCNINT); 2136 PRINTINTR(RTW_INTR_ATIMINT); 2137 PRINTINTR(RTW_INTR_TBDER); 2138 PRINTINTR(RTW_INTR_TBDOK); 2139 PRINTINTR(RTW_INTR_THPDER); 2140 PRINTINTR(RTW_INTR_THPDOK); 2141 PRINTINTR(RTW_INTR_TNPDER); 2142 PRINTINTR(RTW_INTR_TNPDOK); 2143 PRINTINTR(RTW_INTR_RXFOVW); 2144 PRINTINTR(RTW_INTR_RDU); 2145 PRINTINTR(RTW_INTR_TLPDER); 2146 PRINTINTR(RTW_INTR_TLPDOK); 2147 PRINTINTR(RTW_INTR_RER); 2148 PRINTINTR(RTW_INTR_ROK); 2149 2150 printf(">\n"); 2151 } 2152 #undef PRINTINTR 2153 #endif /* RTW_DEBUG */ 2154 2155 if ((isr & RTW_INTR_RX) != 0) 2156 rtw_intr_rx(sc, isr); 2157 if ((isr & RTW_INTR_TX) != 0) 2158 rtw_intr_tx(sc, isr); 2159 if ((isr & RTW_INTR_BEACON) != 0) 2160 rtw_intr_beacon(sc, isr); 2161 if ((isr & RTW_INTR_ATIMINT) != 0) 2162 rtw_intr_atim(sc); 2163 if ((isr & RTW_INTR_IOERROR) != 0) 2164 rtw_intr_ioerror(sc, isr); 2165 if ((isr & RTW_INTR_TIMEOUT) != 0) 2166 rtw_intr_timeout(sc); 2167 } 2168 2169 return 1; 2170 } 2171 2172 /* Must be called at splnet. */ 2173 static void 2174 rtw_stop(struct ifnet *ifp, int disable) 2175 { 2176 int pri; 2177 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2178 struct ieee80211com *ic = &sc->sc_ic; 2179 struct rtw_regs *regs = &sc->sc_regs; 2180 2181 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2182 return; 2183 2184 rtw_suspend_ticks(sc); 2185 2186 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2187 2188 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 2189 /* Disable interrupts. */ 2190 RTW_WRITE16(regs, RTW_IMR, 0); 2191 2192 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2193 2194 /* Stop the transmit and receive processes. First stop DMA, 2195 * then disable receiver and transmitter. 2196 */ 2197 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2198 2199 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2200 2201 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2202 } 2203 2204 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2205 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2206 &sc->sc_txsoft_blk[pri]); 2207 } 2208 2209 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2210 2211 if (disable) 2212 rtw_disable(sc); 2213 2214 /* Mark the interface as not running. Cancel the watchdog timer. */ 2215 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2216 ifp->if_timer = 0; 2217 2218 return; 2219 } 2220 2221 const char * 2222 rtw_pwrstate_string(enum rtw_pwrstate power) 2223 { 2224 switch (power) { 2225 case RTW_ON: 2226 return "on"; 2227 case RTW_SLEEP: 2228 return "sleep"; 2229 case RTW_OFF: 2230 return "off"; 2231 default: 2232 return "unknown"; 2233 } 2234 } 2235 2236 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2237 * reference driver, plus a magic Maxim "ON" value that comes from 2238 * the Realtek document "Windows PG for Rtl8180." 2239 */ 2240 static void 2241 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2242 int before_rf, int digphy) 2243 { 2244 uint32_t anaparm; 2245 2246 anaparm = RTW_READ(regs, RTW_ANAPARM); 2247 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2248 2249 switch (power) { 2250 case RTW_OFF: 2251 if (before_rf) 2252 return; 2253 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2254 anaparm |= RTW_ANAPARM_TXDACOFF; 2255 break; 2256 case RTW_SLEEP: 2257 if (!before_rf) 2258 return; 2259 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2260 anaparm |= RTW_ANAPARM_TXDACOFF; 2261 break; 2262 case RTW_ON: 2263 if (!before_rf) 2264 return; 2265 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2266 break; 2267 } 2268 RTW_DPRINTF(RTW_DEBUG_PWR, 2269 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2270 __func__, rtw_pwrstate_string(power), 2271 (before_rf) ? "before" : "after", anaparm)); 2272 2273 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2274 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2275 } 2276 2277 /* XXX I am using the RFMD settings gleaned from the reference 2278 * driver. They agree 2279 */ 2280 static void 2281 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2282 int before_rf, int digphy) 2283 { 2284 uint32_t anaparm; 2285 2286 anaparm = RTW_READ(regs, RTW_ANAPARM); 2287 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2288 2289 switch (power) { 2290 case RTW_OFF: 2291 if (before_rf) 2292 return; 2293 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2294 anaparm |= RTW_ANAPARM_TXDACOFF; 2295 break; 2296 case RTW_SLEEP: 2297 if (!before_rf) 2298 return; 2299 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2300 anaparm |= RTW_ANAPARM_TXDACOFF; 2301 break; 2302 case RTW_ON: 2303 if (!before_rf) 2304 return; 2305 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2306 break; 2307 } 2308 RTW_DPRINTF(RTW_DEBUG_PWR, 2309 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2310 __func__, rtw_pwrstate_string(power), 2311 (before_rf) ? "before" : "after", anaparm)); 2312 2313 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2314 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2315 } 2316 2317 static void 2318 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2319 int before_rf, int digphy) 2320 { 2321 uint32_t anaparm; 2322 2323 anaparm = RTW_READ(regs, RTW_ANAPARM); 2324 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2325 2326 switch (power) { 2327 case RTW_OFF: 2328 if (before_rf) 2329 return; 2330 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2331 anaparm |= RTW_ANAPARM_TXDACOFF; 2332 break; 2333 case RTW_SLEEP: 2334 if (!before_rf) 2335 return; 2336 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2337 anaparm |= RTW_ANAPARM_TXDACOFF; 2338 break; 2339 case RTW_ON: 2340 if (!before_rf) 2341 return; 2342 if (digphy) { 2343 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2344 /* XXX guess */ 2345 anaparm |= RTW_ANAPARM_TXDACOFF; 2346 } else 2347 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2348 break; 2349 } 2350 RTW_DPRINTF(RTW_DEBUG_PWR, 2351 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2352 __func__, rtw_pwrstate_string(power), 2353 (before_rf) ? "before" : "after", anaparm)); 2354 2355 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2356 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2357 } 2358 2359 static void 2360 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2361 int digphy) 2362 { 2363 struct rtw_regs *regs = &sc->sc_regs; 2364 2365 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2366 2367 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2368 2369 rtw_set_access(regs, RTW_ACCESS_NONE); 2370 2371 return; 2372 } 2373 2374 static int 2375 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2376 { 2377 int rc; 2378 2379 RTW_DPRINTF(RTW_DEBUG_PWR, 2380 ("%s: %s->%s\n", __func__, 2381 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2382 2383 if (sc->sc_pwrstate == power) 2384 return 0; 2385 2386 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2387 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2388 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2389 2390 switch (power) { 2391 case RTW_ON: 2392 /* TBD set LEDs */ 2393 break; 2394 case RTW_SLEEP: 2395 /* TBD */ 2396 break; 2397 case RTW_OFF: 2398 /* TBD */ 2399 break; 2400 } 2401 if (rc == 0) 2402 sc->sc_pwrstate = power; 2403 else 2404 sc->sc_pwrstate = RTW_OFF; 2405 return rc; 2406 } 2407 2408 static int 2409 rtw_tune(struct rtw_softc *sc) 2410 { 2411 struct ieee80211com *ic = &sc->sc_ic; 2412 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 2413 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 2414 u_int chan; 2415 int rc; 2416 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2417 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2418 2419 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2420 KASSERT(chan != IEEE80211_CHAN_ANY); 2421 2422 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2423 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2424 2425 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2426 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2427 2428 if (chan == sc->sc_cur_chan) { 2429 RTW_DPRINTF(RTW_DEBUG_TUNE, 2430 ("%s: already tuned chan #%d\n", __func__, chan)); 2431 return 0; 2432 } 2433 2434 rtw_suspend_ticks(sc); 2435 2436 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2437 2438 /* TBD wait for Tx to complete */ 2439 2440 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2441 2442 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2443 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr, 2444 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) { 2445 /* XXX condition on powersaving */ 2446 printf("%s: phy init failed\n", sc->sc_dev.dv_xname); 2447 } 2448 2449 sc->sc_cur_chan = chan; 2450 2451 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2452 2453 rtw_resume_ticks(sc); 2454 2455 return rc; 2456 } 2457 2458 void 2459 rtw_disable(struct rtw_softc *sc) 2460 { 2461 int rc; 2462 2463 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2464 return; 2465 2466 /* turn off PHY */ 2467 if ((sc->sc_flags & RTW_F_INVALID) == 0 && 2468 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2469 printf("%s: failed to turn off PHY (%d)\n", 2470 sc->sc_dev.dv_xname, rc); 2471 } 2472 2473 if (sc->sc_disable != NULL) 2474 (*sc->sc_disable)(sc); 2475 2476 sc->sc_flags &= ~RTW_F_ENABLED; 2477 } 2478 2479 int 2480 rtw_enable(struct rtw_softc *sc) 2481 { 2482 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2483 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2484 printf("%s: device enable failed\n", 2485 sc->sc_dev.dv_xname); 2486 return (EIO); 2487 } 2488 sc->sc_flags |= RTW_F_ENABLED; 2489 /* Power may have been removed, and WEP keys thus 2490 * reset. 2491 */ 2492 sc->sc_flags &= ~RTW_F_DK_VALID; 2493 } 2494 return (0); 2495 } 2496 2497 static void 2498 rtw_transmit_config(struct rtw_regs *regs) 2499 { 2500 uint32_t tcr; 2501 2502 tcr = RTW_READ(regs, RTW_TCR); 2503 2504 tcr |= RTW_TCR_CWMIN; 2505 tcr &= ~RTW_TCR_MXDMA_MASK; 2506 tcr |= RTW_TCR_MXDMA_256; 2507 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2508 tcr &= ~RTW_TCR_LBK_MASK; 2509 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2510 2511 /* set short/long retry limits */ 2512 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2513 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK); 2514 2515 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2516 2517 RTW_WRITE(regs, RTW_TCR, tcr); 2518 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2519 } 2520 2521 static inline void 2522 rtw_enable_interrupts(struct rtw_softc *sc) 2523 { 2524 struct rtw_regs *regs = &sc->sc_regs; 2525 2526 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2527 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2528 2529 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2530 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2531 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2532 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2533 2534 /* XXX necessary? */ 2535 if (sc->sc_intr_ack != NULL) 2536 (*sc->sc_intr_ack)(regs); 2537 } 2538 2539 static void 2540 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2541 { 2542 uint8_t msr; 2543 2544 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2545 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2546 2547 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2548 2549 switch (opmode) { 2550 case IEEE80211_M_AHDEMO: 2551 case IEEE80211_M_IBSS: 2552 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2553 break; 2554 case IEEE80211_M_HOSTAP: 2555 msr |= RTW_MSR_NETYPE_AP_OK; 2556 break; 2557 case IEEE80211_M_MONITOR: 2558 /* XXX */ 2559 msr |= RTW_MSR_NETYPE_NOLINK; 2560 break; 2561 case IEEE80211_M_STA: 2562 msr |= RTW_MSR_NETYPE_INFRA_OK; 2563 break; 2564 } 2565 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2566 2567 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2568 } 2569 2570 #define rtw_calchash(addr) \ 2571 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2572 2573 static void 2574 rtw_pktfilt_load(struct rtw_softc *sc) 2575 { 2576 struct rtw_regs *regs = &sc->sc_regs; 2577 struct ieee80211com *ic = &sc->sc_ic; 2578 struct ethercom *ec = &sc->sc_ec; 2579 struct ifnet *ifp = &sc->sc_if; 2580 int hash; 2581 uint32_t hashes[2] = { 0, 0 }; 2582 struct ether_multi *enm; 2583 struct ether_multistep step; 2584 2585 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2586 2587 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2588 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2589 2590 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2591 /* MAC auto-reset PHY (huh?) */ 2592 sc->sc_rcr |= RTW_RCR_ENMARP; 2593 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2594 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2595 2596 switch (ic->ic_opmode) { 2597 case IEEE80211_M_MONITOR: 2598 sc->sc_rcr |= RTW_RCR_MONITOR; 2599 break; 2600 case IEEE80211_M_AHDEMO: 2601 case IEEE80211_M_IBSS: 2602 /* receive broadcasts in our BSS */ 2603 sc->sc_rcr |= RTW_RCR_ADD3; 2604 break; 2605 default: 2606 break; 2607 } 2608 2609 ifp->if_flags &= ~IFF_ALLMULTI; 2610 2611 /* 2612 * Program the 64-bit multicast hash filter. 2613 */ 2614 ETHER_FIRST_MULTI(step, ec, enm); 2615 while (enm != NULL) { 2616 /* XXX */ 2617 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2618 ETHER_ADDR_LEN) != 0) { 2619 ifp->if_flags |= IFF_ALLMULTI; 2620 break; 2621 } 2622 2623 hash = rtw_calchash(enm->enm_addrlo); 2624 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2625 ETHER_NEXT_MULTI(step, enm); 2626 } 2627 2628 /* XXX accept all broadcast if scanning */ 2629 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2630 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2631 2632 if (ifp->if_flags & IFF_PROMISC) { 2633 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2634 sc->sc_rcr |= RTW_RCR_ACRC32; /* accept frames failing CRC */ 2635 sc->sc_rcr |= RTW_RCR_AICV; /* accept frames failing ICV */ 2636 ifp->if_flags |= IFF_ALLMULTI; 2637 } 2638 2639 if (ifp->if_flags & IFF_ALLMULTI) 2640 hashes[0] = hashes[1] = 0xffffffff; 2641 2642 if ((hashes[0] | hashes[1]) != 0) 2643 sc->sc_rcr |= RTW_RCR_AM; /* accept multicast */ 2644 2645 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2646 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2647 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2648 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2649 2650 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2651 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2652 sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0), 2653 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2654 } 2655 2656 static struct mbuf * 2657 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2658 { 2659 struct ieee80211com *ic = &sc->sc_ic; 2660 struct mbuf *m; 2661 struct ieee80211_beacon_offsets boff; 2662 2663 if ((m = ieee80211_beacon_alloc(ic, ni, &boff)) != NULL) { 2664 RTW_DPRINTF(RTW_DEBUG_BEACON, 2665 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2666 } 2667 return m; 2668 } 2669 2670 /* Must be called at splnet. */ 2671 static int 2672 rtw_init(struct ifnet *ifp) 2673 { 2674 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2675 struct ieee80211com *ic = &sc->sc_ic; 2676 struct rtw_regs *regs = &sc->sc_regs; 2677 int rc = 0; 2678 2679 if ((rc = rtw_enable(sc)) != 0) 2680 goto out; 2681 2682 /* Cancel pending I/O and reset. */ 2683 rtw_stop(ifp, 0); 2684 2685 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2686 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 2687 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 2688 2689 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2690 goto out; 2691 2692 if ((rc = rtw_swring_setup(sc)) != 0) 2693 goto out; 2694 2695 rtw_transmit_config(regs); 2696 2697 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2698 2699 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2700 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2701 2702 /* long PLCP header, 1Mb/2Mb basic rate */ 2703 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2704 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2705 2706 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2707 rtw_set_access(regs, RTW_ACCESS_NONE); 2708 2709 /* XXX from reference sources */ 2710 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2711 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2712 2713 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname); 2714 2715 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2716 /* from Linux driver */ 2717 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2718 2719 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2720 2721 rtw_enable_interrupts(sc); 2722 2723 rtw_pktfilt_load(sc); 2724 2725 rtw_hwring_setup(sc); 2726 2727 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2728 2729 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2730 2731 ifp->if_flags |= IFF_RUNNING; 2732 ic->ic_state = IEEE80211_S_INIT; 2733 2734 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2735 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2736 2737 rtw_resume_ticks(sc); 2738 2739 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2740 2741 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2742 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2743 else 2744 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2745 2746 out: 2747 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2748 return rc; 2749 } 2750 2751 static inline void 2752 rtw_led_init(struct rtw_regs *regs) 2753 { 2754 uint8_t cfg0, cfg1; 2755 2756 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2757 2758 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2759 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2760 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2761 2762 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2763 RTW_DPRINTF(RTW_DEBUG_LED, 2764 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2765 2766 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2767 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2768 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2769 2770 rtw_set_access(regs, RTW_ACCESS_NONE); 2771 } 2772 2773 /* 2774 * IEEE80211_S_INIT: LED1 off 2775 * 2776 * IEEE80211_S_AUTH, 2777 * IEEE80211_S_ASSOC, 2778 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2779 * 2780 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2781 */ 2782 static void 2783 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2784 { 2785 struct rtw_led_state *ls; 2786 2787 ls = &sc->sc_led_state; 2788 2789 switch (nstate) { 2790 case IEEE80211_S_INIT: 2791 rtw_led_init(&sc->sc_regs); 2792 callout_stop(&ls->ls_slow_ch); 2793 callout_stop(&ls->ls_fast_ch); 2794 ls->ls_slowblink = 0; 2795 ls->ls_actblink = 0; 2796 ls->ls_default = 0; 2797 break; 2798 case IEEE80211_S_SCAN: 2799 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2800 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2801 /*FALLTHROUGH*/ 2802 case IEEE80211_S_AUTH: 2803 case IEEE80211_S_ASSOC: 2804 ls->ls_default = RTW_LED1; 2805 ls->ls_actblink = RTW_LED1; 2806 ls->ls_slowblink = RTW_LED1; 2807 break; 2808 case IEEE80211_S_RUN: 2809 ls->ls_slowblink = 0; 2810 break; 2811 } 2812 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2813 } 2814 2815 static void 2816 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2817 { 2818 uint8_t led_condition; 2819 bus_size_t ofs; 2820 uint8_t mask, newval, val; 2821 2822 led_condition = ls->ls_default; 2823 2824 if (ls->ls_state & RTW_LED_S_SLOW) 2825 led_condition ^= ls->ls_slowblink; 2826 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2827 led_condition ^= ls->ls_actblink; 2828 2829 RTW_DPRINTF(RTW_DEBUG_LED, 2830 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2831 2832 switch (hwverid) { 2833 default: 2834 case 'F': 2835 ofs = RTW_PSR; 2836 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2837 if (led_condition & RTW_LED0) 2838 newval &= ~RTW_PSR_LEDGPO0; 2839 if (led_condition & RTW_LED1) 2840 newval &= ~RTW_PSR_LEDGPO1; 2841 break; 2842 case 'D': 2843 ofs = RTW_9346CR; 2844 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2845 newval = RTW_9346CR_EEM_PROGRAM; 2846 if (led_condition & RTW_LED0) 2847 newval |= RTW_9346CR_EEDI; 2848 if (led_condition & RTW_LED1) 2849 newval |= RTW_9346CR_EECS; 2850 break; 2851 } 2852 val = RTW_READ8(regs, ofs); 2853 RTW_DPRINTF(RTW_DEBUG_LED, 2854 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2855 (uintptr_t)ofs)); 2856 val &= ~mask; 2857 val |= newval; 2858 RTW_WRITE8(regs, ofs, val); 2859 RTW_DPRINTF(RTW_DEBUG_LED, 2860 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2861 (uintptr_t)ofs)); 2862 RTW_SYNC(regs, ofs, ofs); 2863 } 2864 2865 static void 2866 rtw_led_fastblink(void *arg) 2867 { 2868 int ostate, s; 2869 struct rtw_softc *sc = (struct rtw_softc *)arg; 2870 struct rtw_led_state *ls = &sc->sc_led_state; 2871 2872 s = splnet(); 2873 ostate = ls->ls_state; 2874 ls->ls_state ^= ls->ls_event; 2875 2876 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2877 ls->ls_state &= ~RTW_LED_S_TX; 2878 2879 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2880 ls->ls_state &= ~RTW_LED_S_RX; 2881 2882 ls->ls_event = 0; 2883 2884 if (ostate != ls->ls_state) 2885 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2886 splx(s); 2887 2888 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2889 } 2890 2891 static void 2892 rtw_led_slowblink(void *arg) 2893 { 2894 int s; 2895 struct rtw_softc *sc = (struct rtw_softc *)arg; 2896 struct rtw_led_state *ls = &sc->sc_led_state; 2897 2898 s = splnet(); 2899 ls->ls_state ^= RTW_LED_S_SLOW; 2900 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2901 splx(s); 2902 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2903 } 2904 2905 static inline void 2906 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2907 { 2908 callout_init(&ls->ls_fast_ch, 0); 2909 callout_init(&ls->ls_slow_ch, 0); 2910 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2911 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2912 } 2913 2914 static int 2915 rtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2916 { 2917 int rc = 0, s; 2918 struct rtw_softc *sc = ifp->if_softc; 2919 2920 s = splnet(); 2921 if (cmd == SIOCSIFFLAGS) { 2922 if ((ifp->if_flags & IFF_UP) != 0) { 2923 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2924 rtw_pktfilt_load(sc); 2925 else 2926 rc = rtw_init(ifp); 2927 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2928 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2929 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2930 rtw_stop(ifp, 1); 2931 } 2932 } else if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 2933 ; /* nothing to do */ 2934 else if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 2935 /* reload packet filter if running */ 2936 if (ifp->if_flags & IFF_RUNNING) 2937 rtw_pktfilt_load(sc); 2938 rc = 0; 2939 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2940 /* reinitialize h/w if activated */ 2941 rc = rtw_init(ifp); 2942 else 2943 rc = 0; 2944 splx(s); 2945 return rc; 2946 } 2947 2948 /* Select a transmit ring with at least one h/w and s/w descriptor free. 2949 * Return 0 on success, -1 on failure. 2950 */ 2951 static inline int 2952 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 2953 struct rtw_txdesc_blk **tdbp, int pri) 2954 { 2955 struct rtw_txsoft_blk *tsb; 2956 struct rtw_txdesc_blk *tdb; 2957 2958 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 2959 2960 tsb = &sc->sc_txsoft_blk[pri]; 2961 tdb = &sc->sc_txdesc_blk[pri]; 2962 2963 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 2964 if (tsb->tsb_tx_timer == 0) 2965 tsb->tsb_tx_timer = 5; 2966 *tsbp = NULL; 2967 *tdbp = NULL; 2968 return -1; 2969 } 2970 *tsbp = tsb; 2971 *tdbp = tdb; 2972 return 0; 2973 } 2974 2975 static inline struct mbuf * 2976 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 2977 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 2978 struct ieee80211_node **nip, short *if_flagsp) 2979 { 2980 struct mbuf *m; 2981 2982 if (IF_IS_EMPTY(ifq)) 2983 return NULL; 2984 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 2985 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 2986 __func__, pri)); 2987 *if_flagsp |= IFF_OACTIVE; 2988 sc->sc_if.if_timer = 1; 2989 return NULL; 2990 } 2991 IF_DEQUEUE(ifq, m); 2992 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2993 m->m_pkthdr.rcvif = NULL; 2994 KASSERT(*nip != NULL); 2995 return m; 2996 } 2997 2998 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 2999 * at the driver's selection of transmit control block for the packet. 3000 */ 3001 static inline int 3002 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 3003 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 3004 struct ieee80211_node **nip) 3005 { 3006 int pri; 3007 struct ether_header *eh; 3008 struct mbuf *m0; 3009 struct rtw_softc *sc; 3010 short *if_flagsp; 3011 3012 *mp = NULL; 3013 3014 sc = (struct rtw_softc *)ifp->if_softc; 3015 3016 DPRINTF(sc, RTW_DEBUG_XMIT, 3017 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3018 3019 if_flagsp = &ifp->if_flags; 3020 3021 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 3022 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 3023 tdbp, nip, if_flagsp)) != NULL) { 3024 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 3025 __func__)); 3026 return 0; 3027 } 3028 3029 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 3030 tdbp, nip, if_flagsp)) != NULL) { 3031 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 3032 __func__)); 3033 return 0; 3034 } 3035 3036 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 3037 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 3038 return 0; 3039 } 3040 3041 IFQ_POLL(&ifp->if_snd, m0); 3042 if (m0 == NULL) { 3043 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3044 __func__)); 3045 return 0; 3046 } 3047 3048 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 3049 3050 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3051 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3052 __func__, pri)); 3053 *if_flagsp |= IFF_OACTIVE; 3054 sc->sc_if.if_timer = 1; 3055 return 0; 3056 } 3057 3058 IFQ_DEQUEUE(&ifp->if_snd, m0); 3059 if (m0 == NULL) { 3060 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3061 __func__)); 3062 return 0; 3063 } 3064 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 3065 ifp->if_opackets++; 3066 #if NBPFILTER > 0 3067 if (ifp->if_bpf) 3068 bpf_mtap(ifp->if_bpf, m0); 3069 #endif 3070 eh = mtod(m0, struct ether_header *); 3071 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 3072 if (*nip == NULL) { 3073 /* NB: ieee80211_find_txnode does stat+msg */ 3074 m_freem(m0); 3075 return -1; 3076 } 3077 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 3078 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 3079 ifp->if_oerrors++; 3080 return -1; 3081 } 3082 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3083 *mp = m0; 3084 return 0; 3085 } 3086 3087 static int 3088 rtw_seg_too_short(bus_dmamap_t dmamap) 3089 { 3090 int i; 3091 for (i = 0; i < dmamap->dm_nsegs; i++) { 3092 if (dmamap->dm_segs[i].ds_len < 4) 3093 return 1; 3094 } 3095 return 0; 3096 } 3097 3098 /* TBD factor with atw_start */ 3099 static struct mbuf * 3100 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 3101 u_int ndescfree, const char *dvname) 3102 { 3103 int first, rc; 3104 struct mbuf *m, *m0; 3105 3106 m0 = chain; 3107 3108 /* 3109 * Load the DMA map. Copy and try (once) again if the packet 3110 * didn't fit in the alloted number of segments. 3111 */ 3112 for (first = 1; 3113 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 3114 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 3115 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 3116 first = 0) { 3117 if (rc == 0) { 3118 #ifdef RTW_DIAGxxx 3119 if (rtw_seg_too_short(dmam)) { 3120 printf("%s: short segment, mbuf lengths:", __func__); 3121 for (m = m0; m; m = m->m_next) 3122 printf(" %d", m->m_len); 3123 printf("\n"); 3124 } 3125 #endif 3126 bus_dmamap_unload(dmat, dmam); 3127 } 3128 MGETHDR(m, M_DONTWAIT, MT_DATA); 3129 if (m == NULL) { 3130 printf("%s: unable to allocate Tx mbuf\n", 3131 dvname); 3132 break; 3133 } 3134 if (m0->m_pkthdr.len > MHLEN) { 3135 MCLGET(m, M_DONTWAIT); 3136 if ((m->m_flags & M_EXT) == 0) { 3137 printf("%s: cannot allocate Tx cluster\n", 3138 dvname); 3139 m_freem(m); 3140 break; 3141 } 3142 } 3143 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3144 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3145 m_freem(m0); 3146 m0 = m; 3147 m = NULL; 3148 } 3149 if (rc != 0) { 3150 printf("%s: cannot load Tx buffer, rc = %d\n", dvname, rc); 3151 m_freem(m0); 3152 return NULL; 3153 } else if (rtw_seg_too_short(dmam)) { 3154 printf("%s: cannot load Tx buffer, segment too short\n", 3155 dvname); 3156 bus_dmamap_unload(dmat, dmam); 3157 m_freem(m0); 3158 return NULL; 3159 } else if (dmam->dm_nsegs > ndescfree) { 3160 printf("%s: too many tx segments\n", dvname); 3161 bus_dmamap_unload(dmat, dmam); 3162 m_freem(m0); 3163 return NULL; 3164 } 3165 return m0; 3166 } 3167 3168 #ifdef RTW_DEBUG 3169 static void 3170 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3171 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3172 { 3173 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3174 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] next %#08x " 3175 "buf %#08x ctl0 %#08x ctl1 %#08x len %#08x\n", 3176 sc->sc_dev.dv_xname, ts, action, desc, 3177 le32toh(td->td_buf), le32toh(td->td_next), 3178 le32toh(td->td_ctl0), le32toh(td->td_ctl1), 3179 le32toh(td->td_len))); 3180 } 3181 #endif /* RTW_DEBUG */ 3182 3183 static void 3184 rtw_start(struct ifnet *ifp) 3185 { 3186 uint8_t tppoll; 3187 int desc, i, lastdesc, npkt, rate; 3188 uint32_t proto_ctl0, ctl0, ctl1; 3189 bus_dmamap_t dmamap; 3190 struct ieee80211com *ic; 3191 struct ieee80211_duration *d0; 3192 struct ieee80211_frame_min *wh; 3193 struct ieee80211_node *ni = NULL; /* XXX: GCC */ 3194 struct mbuf *m0; 3195 struct rtw_softc *sc; 3196 struct rtw_txsoft_blk *tsb = NULL; /* XXX: GCC */ 3197 struct rtw_txdesc_blk *tdb = NULL; /* XXX: GCC */ 3198 struct rtw_txsoft *ts; 3199 struct rtw_txdesc *td; 3200 struct ieee80211_key *k; 3201 3202 sc = (struct rtw_softc *)ifp->if_softc; 3203 ic = &sc->sc_ic; 3204 3205 DPRINTF(sc, RTW_DEBUG_XMIT, 3206 ("%s: enter %s\n", sc->sc_dev.dv_xname, __func__)); 3207 3208 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3209 goto out; 3210 3211 /* XXX do real rate control */ 3212 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3213 3214 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3215 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3216 3217 for (;;) { 3218 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3219 continue; 3220 if (m0 == NULL) 3221 break; 3222 3223 wh = mtod(m0, struct ieee80211_frame_min *); 3224 3225 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3226 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3227 m_freem(m0); 3228 break; 3229 } else 3230 k = NULL; 3231 3232 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3233 3234 dmamap = ts->ts_dmamap; 3235 3236 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3237 tdb->tdb_nfree, sc->sc_dev.dv_xname); 3238 3239 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3240 DPRINTF(sc, RTW_DEBUG_XMIT, 3241 ("%s: fail dmamap load\n", __func__)); 3242 goto post_dequeue_err; 3243 } 3244 3245 /* Note well: rtw_dmamap_load_txbuf may have created 3246 * a new chain, so we must find the header once 3247 * more. 3248 */ 3249 wh = mtod(m0, struct ieee80211_frame_min *); 3250 3251 /* XXX do real rate control */ 3252 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3253 IEEE80211_FC0_TYPE_MGT) 3254 rate = 2; 3255 else 3256 rate = MAX(2, ieee80211_get_rate(ni)); 3257 3258 #ifdef RTW_DEBUG 3259 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3260 (IFF_DEBUG|IFF_LINK2)) { 3261 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3262 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3263 : sizeof(wh), 3264 rate, 0); 3265 } 3266 #endif /* RTW_DEBUG */ 3267 ctl0 = proto_ctl0 | 3268 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3269 3270 switch (rate) { 3271 default: 3272 case 2: 3273 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3274 break; 3275 case 4: 3276 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3277 break; 3278 case 11: 3279 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3280 break; 3281 case 22: 3282 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3283 break; 3284 } 3285 /* XXX >= ? Compare after fragmentation? */ 3286 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3287 ctl0 |= RTW_TXCTL0_RTSEN; 3288 3289 /* XXX Sometimes writes a bogus keyid; h/w doesn't 3290 * seem to care, since we don't activate h/w Tx 3291 * encryption. 3292 */ 3293 if (k != NULL) { 3294 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3295 RTW_TXCTL0_KEYID_MASK; 3296 } 3297 3298 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3299 IEEE80211_FC0_TYPE_MGT) { 3300 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3301 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3302 IEEE80211_FC0_SUBTYPE_BEACON) 3303 ctl0 |= RTW_TXCTL0_BEACON; 3304 } 3305 3306 if (ieee80211_compute_duration(wh, k, m0->m_pkthdr.len, 3307 ic->ic_flags, ic->ic_fragthreshold, 3308 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3309 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3310 (IFF_DEBUG|IFF_LINK2)) == -1) { 3311 DPRINTF(sc, RTW_DEBUG_XMIT, 3312 ("%s: fail compute duration\n", __func__)); 3313 goto post_load_err; 3314 } 3315 3316 d0 = &ts->ts_d0; 3317 3318 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3319 3320 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3321 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3322 3323 if (d0->d_residue) 3324 ctl1 |= RTW_TXCTL1_LENGEXT; 3325 3326 /* TBD fragmentation */ 3327 3328 ts->ts_first = tdb->tdb_next; 3329 3330 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3331 BUS_DMASYNC_PREWRITE); 3332 3333 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3334 3335 #if NBPFILTER > 0 3336 if (ic->ic_rawbpf != NULL) 3337 bpf_mtap((void *)ic->ic_rawbpf, m0); 3338 3339 if (sc->sc_radiobpf != NULL) { 3340 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3341 3342 rt->rt_rate = rate; 3343 3344 bpf_mtap2(sc->sc_radiobpf, (void *)rt, 3345 sizeof(sc->sc_txtapu), m0); 3346 } 3347 #endif /* NBPFILTER > 0 */ 3348 3349 for (i = 0, lastdesc = desc = ts->ts_first; 3350 i < dmamap->dm_nsegs; 3351 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3352 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3353 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3354 ("%s: seg too long\n", __func__)); 3355 goto post_load_err; 3356 } 3357 td = &tdb->tdb_desc[desc]; 3358 td->td_ctl0 = htole32(ctl0); 3359 td->td_ctl1 = htole32(ctl1); 3360 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3361 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3362 td->td_next = htole32(RTW_NEXT_DESC(tdb, desc)); 3363 if (i != 0) 3364 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3365 lastdesc = desc; 3366 #ifdef RTW_DEBUG 3367 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3368 #endif /* RTW_DEBUG */ 3369 } 3370 3371 KASSERT(desc < tdb->tdb_ndesc); 3372 3373 ts->ts_ni = ni; 3374 KASSERT(ni != NULL); 3375 ts->ts_mbuf = m0; 3376 ts->ts_last = lastdesc; 3377 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3378 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3379 htole32(RTW_TXCTL0_FS); 3380 3381 #ifdef RTW_DEBUG 3382 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3383 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3384 #endif /* RTW_DEBUG */ 3385 3386 tdb->tdb_nfree -= dmamap->dm_nsegs; 3387 tdb->tdb_next = desc; 3388 3389 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3390 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3391 3392 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3393 htole32(RTW_TXCTL0_OWN); 3394 3395 #ifdef RTW_DEBUG 3396 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3397 #endif /* RTW_DEBUG */ 3398 3399 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3400 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3401 3402 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3403 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3404 3405 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) 3406 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3407 tsb->tsb_tx_timer = 5; 3408 ifp->if_timer = 1; 3409 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3410 tppoll &= ~RTW_TPPOLL_SALL; 3411 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL; 3412 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3413 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3414 } 3415 out: 3416 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3417 return; 3418 post_load_err: 3419 bus_dmamap_unload(sc->sc_dmat, dmamap); 3420 m_freem(m0); 3421 post_dequeue_err: 3422 ieee80211_free_node(ni); 3423 return; 3424 } 3425 3426 static void 3427 rtw_idle(struct rtw_regs *regs) 3428 { 3429 int active; 3430 3431 /* request stop DMA; wait for packets to stop transmitting. */ 3432 3433 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3434 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL); 3435 3436 for (active = 0; active < 300 && 3437 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0; active++) 3438 DELAY(10); 3439 printf("%s: transmit DMA idle in %dus\n", __func__, active * 10); 3440 } 3441 3442 static void 3443 rtw_watchdog(struct ifnet *ifp) 3444 { 3445 int pri, tx_timeouts = 0; 3446 struct rtw_softc *sc; 3447 struct rtw_txsoft_blk *tsb; 3448 3449 sc = ifp->if_softc; 3450 3451 ifp->if_timer = 0; 3452 3453 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 3454 return; 3455 3456 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3457 tsb = &sc->sc_txsoft_blk[pri]; 3458 3459 if (tsb->tsb_tx_timer == 0) 3460 continue; 3461 else if (--tsb->tsb_tx_timer == 0) { 3462 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3463 continue; 3464 printf("%s: transmit timeout, priority %d\n", 3465 ifp->if_xname, pri); 3466 ifp->if_oerrors++; 3467 if (pri != RTW_TXPRIBCN) 3468 tx_timeouts++; 3469 } else 3470 ifp->if_timer = 1; 3471 } 3472 3473 if (tx_timeouts > 0) { 3474 /* Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr, 3475 * reset s/w tx-ring pointers, and start transmission. 3476 * 3477 * TBD Stop/restart just the broken rings? 3478 */ 3479 rtw_idle(&sc->sc_regs); 3480 rtw_io_enable(sc, RTW_CR_TE, 0); 3481 rtw_txdescs_reset(sc); 3482 rtw_io_enable(sc, RTW_CR_TE, 1); 3483 rtw_start(ifp); 3484 } 3485 ieee80211_watchdog(&sc->sc_ic); 3486 return; 3487 } 3488 3489 static void 3490 rtw_next_scan(void *arg) 3491 { 3492 struct ieee80211com *ic = arg; 3493 int s; 3494 3495 /* don't call rtw_start w/o network interrupts blocked */ 3496 s = splnet(); 3497 if (ic->ic_state == IEEE80211_S_SCAN) 3498 ieee80211_next_scan(ic); 3499 splx(s); 3500 } 3501 3502 static void 3503 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3504 { 3505 uint16_t bcnitv, bintritv, intval; 3506 int i; 3507 struct rtw_regs *regs = &sc->sc_regs; 3508 3509 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3510 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3511 3512 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3513 3514 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3515 3516 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); 3517 3518 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3519 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); 3520 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3521 /* interrupt host 1ms before the TBTT */ 3522 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV; 3523 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV); 3524 RTW_WRITE16(regs, RTW_BINTRITV, bintritv); 3525 /* magic from Linux */ 3526 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND)); 3527 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); 3528 rtw_set_access(regs, RTW_ACCESS_NONE); 3529 3530 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 3531 } 3532 3533 /* Synchronize the hardware state with the software state. */ 3534 static int 3535 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3536 { 3537 struct ifnet *ifp = ic->ic_ifp; 3538 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3539 enum ieee80211_state ostate; 3540 int error; 3541 3542 ostate = ic->ic_state; 3543 3544 rtw_led_newstate(sc, nstate); 3545 3546 if (nstate == IEEE80211_S_INIT) { 3547 callout_stop(&sc->sc_scan_ch); 3548 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3549 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3550 } 3551 3552 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3553 rtw_pwrstate(sc, RTW_ON); 3554 3555 if ((error = rtw_tune(sc)) != 0) 3556 return error; 3557 3558 switch (nstate) { 3559 case IEEE80211_S_INIT: 3560 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3561 break; 3562 case IEEE80211_S_SCAN: 3563 if (ostate != IEEE80211_S_SCAN) { 3564 (void)memset(ic->ic_bss->ni_bssid, 0, 3565 IEEE80211_ADDR_LEN); 3566 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3567 } 3568 3569 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3570 rtw_next_scan, ic); 3571 3572 break; 3573 case IEEE80211_S_RUN: 3574 switch (ic->ic_opmode) { 3575 case IEEE80211_M_HOSTAP: 3576 case IEEE80211_M_IBSS: 3577 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3578 /*FALLTHROUGH*/ 3579 case IEEE80211_M_AHDEMO: 3580 case IEEE80211_M_STA: 3581 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3582 ic->ic_bss->ni_intval); 3583 break; 3584 case IEEE80211_M_MONITOR: 3585 break; 3586 } 3587 rtw_set_nettype(sc, ic->ic_opmode); 3588 break; 3589 case IEEE80211_S_ASSOC: 3590 case IEEE80211_S_AUTH: 3591 break; 3592 } 3593 3594 if (nstate != IEEE80211_S_SCAN) 3595 callout_stop(&sc->sc_scan_ch); 3596 3597 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3598 } 3599 3600 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3601 static uint64_t 3602 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3603 { 3604 uint32_t tsftl, tsfth; 3605 3606 tsfth = RTW_READ(regs, RTW_TSFTRH); 3607 tsftl = RTW_READ(regs, RTW_TSFTRL); 3608 if (tsftl < rstamp) /* Compensate for rollover. */ 3609 tsfth--; 3610 return ((uint64_t)tsfth << 32) | rstamp; 3611 } 3612 3613 static void 3614 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3615 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3616 { 3617 struct ifnet *ifp = ic->ic_ifp; 3618 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3619 3620 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3621 3622 switch (subtype) { 3623 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3624 case IEEE80211_FC0_SUBTYPE_BEACON: 3625 if (ic->ic_opmode == IEEE80211_M_IBSS && 3626 ic->ic_state == IEEE80211_S_RUN) { 3627 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp); 3628 if (le64toh(ni->ni_tstamp.tsf) >= tsf) 3629 (void)ieee80211_ibss_merge(ni); 3630 } 3631 break; 3632 default: 3633 break; 3634 } 3635 return; 3636 } 3637 3638 static struct ieee80211_node * 3639 rtw_node_alloc(struct ieee80211_node_table *nt) 3640 { 3641 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3642 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3643 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3644 3645 DPRINTF(sc, RTW_DEBUG_NODE, 3646 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 3647 return ni; 3648 } 3649 3650 static void 3651 rtw_node_free(struct ieee80211_node *ni) 3652 { 3653 struct ieee80211com *ic = ni->ni_ic; 3654 struct ifnet *ifp = ic->ic_ifp; 3655 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3656 3657 DPRINTF(sc, RTW_DEBUG_NODE, 3658 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 3659 ether_sprintf(ni->ni_bssid))); 3660 (*sc->sc_mtbl.mt_node_free)(ni); 3661 } 3662 3663 static int 3664 rtw_media_change(struct ifnet *ifp) 3665 { 3666 int error; 3667 3668 error = ieee80211_media_change(ifp); 3669 if (error == ENETRESET) { 3670 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3671 (IFF_RUNNING|IFF_UP)) 3672 rtw_init(ifp); /* XXX lose error */ 3673 error = 0; 3674 } 3675 return error; 3676 } 3677 3678 static void 3679 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3680 { 3681 struct rtw_softc *sc = ifp->if_softc; 3682 3683 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3684 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3685 imr->ifm_status = 0; 3686 return; 3687 } 3688 ieee80211_media_status(ifp, imr); 3689 } 3690 3691 static inline void 3692 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3693 { 3694 (void)memcpy(ifp->if_xname, dvname, IFNAMSIZ); 3695 ifp->if_softc = softc; 3696 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3697 IFF_NOTRAILERS; 3698 ifp->if_ioctl = rtw_ioctl; 3699 ifp->if_start = rtw_start; 3700 ifp->if_watchdog = rtw_watchdog; 3701 ifp->if_init = rtw_init; 3702 ifp->if_stop = rtw_stop; 3703 } 3704 3705 static inline void 3706 rtw_set80211props(struct ieee80211com *ic) 3707 { 3708 int nrate; 3709 ic->ic_phytype = IEEE80211_T_DS; 3710 ic->ic_opmode = IEEE80211_M_STA; 3711 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3712 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 3713 3714 nrate = 0; 3715 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3716 IEEE80211_RATE_BASIC | 2; 3717 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3718 IEEE80211_RATE_BASIC | 4; 3719 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3720 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3721 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3722 } 3723 3724 static inline void 3725 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3726 { 3727 mtbl->mt_newstate = ic->ic_newstate; 3728 ic->ic_newstate = rtw_newstate; 3729 3730 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3731 ic->ic_recv_mgmt = rtw_recv_mgmt; 3732 3733 mtbl->mt_node_free = ic->ic_node_free; 3734 ic->ic_node_free = rtw_node_free; 3735 3736 mtbl->mt_node_alloc = ic->ic_node_alloc; 3737 ic->ic_node_alloc = rtw_node_alloc; 3738 3739 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3740 ic->ic_crypto.cs_key_set = rtw_key_set; 3741 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3742 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3743 } 3744 3745 static inline void 3746 rtw_init_radiotap(struct rtw_softc *sc) 3747 { 3748 uint32_t present; 3749 3750 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3751 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3752 3753 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 3754 present = htole32(RTW_PHILIPS_RX_RADIOTAP_PRESENT); 3755 else 3756 present = htole32(RTW_RX_RADIOTAP_PRESENT); 3757 sc->sc_rxtap.rr_ihdr.it_present = present; 3758 3759 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3760 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3761 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3762 } 3763 3764 static int 3765 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3766 { 3767 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3768 SIMPLEQ_INIT(&tsb->tsb_freeq); 3769 tsb->tsb_ndesc = qlen; 3770 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3771 M_NOWAIT); 3772 if (tsb->tsb_desc == NULL) 3773 return ENOMEM; 3774 return 0; 3775 } 3776 3777 static void 3778 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3779 { 3780 int pri; 3781 struct rtw_txsoft_blk *tsb; 3782 3783 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3784 tsb = &sc->sc_txsoft_blk[pri]; 3785 free(tsb->tsb_desc, M_DEVBUF); 3786 tsb->tsb_desc = NULL; 3787 } 3788 } 3789 3790 static int 3791 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3792 { 3793 int pri, rc = 0; 3794 int qlen[RTW_NTXPRI] = 3795 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3796 struct rtw_txsoft_blk *tsbs; 3797 3798 tsbs = sc->sc_txsoft_blk; 3799 3800 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3801 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3802 if (rc != 0) 3803 break; 3804 } 3805 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3806 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3807 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3808 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3809 return rc; 3810 } 3811 3812 static void 3813 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3814 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3815 { 3816 tdb->tdb_ndesc = ndesc; 3817 tdb->tdb_desc = desc; 3818 tdb->tdb_physbase = physbase; 3819 tdb->tdb_ofs = ofs; 3820 3821 (void)memset(tdb->tdb_desc, 0, 3822 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3823 3824 rtw_txdesc_blk_init(tdb); 3825 tdb->tdb_next = 0; 3826 } 3827 3828 static void 3829 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3830 { 3831 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3832 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3833 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3834 3835 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3836 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3837 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3838 3839 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3840 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3841 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3842 3843 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3844 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3845 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3846 } 3847 3848 static struct rtw_rf * 3849 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3850 { 3851 rtw_rf_write_t rf_write; 3852 struct rtw_rf *rf; 3853 3854 switch (rfchipid) { 3855 default: 3856 rf_write = rtw_rf_hostwrite; 3857 break; 3858 case RTW_RFCHIPID_INTERSIL: 3859 case RTW_RFCHIPID_PHILIPS: 3860 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3861 case RTW_RFCHIPID_RFMD: 3862 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3863 break; 3864 } 3865 3866 switch (rfchipid) { 3867 case RTW_RFCHIPID_GCT: 3868 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0); 3869 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3870 break; 3871 case RTW_RFCHIPID_MAXIM: 3872 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3873 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3874 break; 3875 case RTW_RFCHIPID_PHILIPS: 3876 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3877 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3878 break; 3879 case RTW_RFCHIPID_RFMD: 3880 /* XXX RFMD has no RF constructor */ 3881 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3882 /*FALLTHROUGH*/ 3883 default: 3884 return NULL; 3885 } 3886 rf->rf_continuous_tx_cb = 3887 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3888 rf->rf_continuous_tx_arg = (void *)sc; 3889 return rf; 3890 } 3891 3892 /* Revision C and later use a different PHY delay setting than 3893 * revisions A and B. 3894 */ 3895 static uint8_t 3896 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 3897 { 3898 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3899 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3900 3901 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); 3902 3903 RTW_WRITE(regs, RTW_RCR, REVAB); 3904 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3905 RTW_WRITE(regs, RTW_RCR, REVC); 3906 3907 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3908 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3909 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3910 3911 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 3912 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3913 3914 return phydelay; 3915 #undef REVC 3916 } 3917 3918 void 3919 rtw_attach(struct rtw_softc *sc) 3920 { 3921 struct ifnet *ifp = &sc->sc_if; 3922 struct ieee80211com *ic = &sc->sc_ic; 3923 struct rtw_txsoft_blk *tsb; 3924 int pri, rc; 3925 3926 rtw_cipher_wep = ieee80211_cipher_wep; 3927 rtw_cipher_wep.ic_decap = rtw_wep_decap; 3928 3929 NEXT_ATTACH_STATE(sc, DETACHED); 3930 3931 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3932 case RTW_TCR_HWVERID_F: 3933 sc->sc_hwverid = 'F'; 3934 break; 3935 case RTW_TCR_HWVERID_D: 3936 sc->sc_hwverid = 'D'; 3937 break; 3938 default: 3939 sc->sc_hwverid = '?'; 3940 break; 3941 } 3942 printf("%s: hardware version %c\n", sc->sc_dev.dv_xname, 3943 sc->sc_hwverid); 3944 3945 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3946 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3947 0); 3948 3949 if (rc != 0) { 3950 printf("%s: could not allocate hw descriptors, error %d\n", 3951 sc->sc_dev.dv_xname, rc); 3952 goto err; 3953 } 3954 3955 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3956 3957 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3958 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3959 (void **)&sc->sc_descs, BUS_DMA_COHERENT); 3960 3961 if (rc != 0) { 3962 printf("%s: could not map hw descriptors, error %d\n", 3963 sc->sc_dev.dv_xname, rc); 3964 goto err; 3965 } 3966 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3967 3968 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3969 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3970 3971 if (rc != 0) { 3972 printf("%s: could not create DMA map for hw descriptors, " 3973 "error %d\n", sc->sc_dev.dv_xname, rc); 3974 goto err; 3975 } 3976 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3977 3978 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 3979 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 3980 3981 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3982 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 3983 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 3984 } 3985 3986 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3987 sizeof(struct rtw_descs), NULL, 0); 3988 3989 if (rc != 0) { 3990 printf("%s: could not load DMA map for hw descriptors, " 3991 "error %d\n", sc->sc_dev.dv_xname, rc); 3992 goto err; 3993 } 3994 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 3995 3996 if (rtw_txsoft_blk_setup_all(sc) != 0) 3997 goto err; 3998 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 3999 4000 rtw_txdesc_blk_setup_all(sc); 4001 4002 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 4003 4004 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 4005 4006 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4007 tsb = &sc->sc_txsoft_blk[pri]; 4008 4009 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 4010 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 4011 printf("%s: could not load DMA map for " 4012 "hw tx descriptors, error %d\n", 4013 sc->sc_dev.dv_xname, rc); 4014 goto err; 4015 } 4016 } 4017 4018 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 4019 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 4020 RTW_RXQLEN)) != 0) { 4021 printf("%s: could not load DMA map for hw rx descriptors, " 4022 "error %d\n", sc->sc_dev.dv_xname, rc); 4023 goto err; 4024 } 4025 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 4026 4027 /* Reset the chip to a known state. */ 4028 if (rtw_reset(sc) != 0) 4029 goto err; 4030 NEXT_ATTACH_STATE(sc, FINISH_RESET); 4031 4032 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 4033 4034 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 4035 sc->sc_flags |= RTW_F_9356SROM; 4036 4037 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 4038 sc->sc_dev.dv_xname) != 0) 4039 goto err; 4040 4041 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 4042 4043 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 4044 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 4045 sc->sc_dev.dv_xname) != 0) { 4046 printf("%s: attach failed, malformed serial ROM\n", 4047 sc->sc_dev.dv_xname); 4048 goto err; 4049 } 4050 4051 printf("%s: %s PHY\n", sc->sc_dev.dv_xname, 4052 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 4053 4054 printf("%s: CS threshold %u\n", sc->sc_dev.dv_xname, sc->sc_csthr); 4055 4056 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 4057 4058 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 4059 sc->sc_flags & RTW_F_DIGPHY); 4060 4061 if (sc->sc_rf == NULL) { 4062 printf("%s: attach failed, could not attach RF\n", 4063 sc->sc_dev.dv_xname); 4064 goto err; 4065 } 4066 4067 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 4068 4069 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4070 4071 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4072 ("%s: PHY delay %d\n", sc->sc_dev.dv_xname, sc->sc_phydelay)); 4073 4074 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4075 rtw_identify_country(&sc->sc_regs, &sc->sc_locale); 4076 4077 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, 4078 sc->sc_dev.dv_xname); 4079 4080 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4081 sc->sc_dev.dv_xname) != 0) 4082 goto err; 4083 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4084 4085 rtw_setifprops(ifp, sc->sc_dev.dv_xname, (void*)sc); 4086 4087 IFQ_SET_READY(&ifp->if_snd); 4088 4089 sc->sc_ic.ic_ifp = ifp; 4090 rtw_set80211props(&sc->sc_ic); 4091 4092 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4093 4094 /* 4095 * Call MI attach routines. 4096 */ 4097 if_attach(ifp); 4098 ieee80211_ifattach(&sc->sc_ic); 4099 4100 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4101 4102 /* possibly we should fill in our own sc_send_prresp, since 4103 * the RTL8180 is probably sending probe responses in ad hoc 4104 * mode. 4105 */ 4106 4107 /* complete initialization */ 4108 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4109 callout_init(&sc->sc_scan_ch, 0); 4110 4111 rtw_init_radiotap(sc); 4112 4113 #if NBPFILTER > 0 4114 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4115 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4116 #endif 4117 4118 if (!pmf_device_register(&sc->sc_dev, NULL, NULL)) { 4119 aprint_error_dev(&sc->sc_dev, 4120 "couldn't establish power handler\n"); 4121 } else 4122 pmf_class_network_register(&sc->sc_dev, &sc->sc_if); 4123 4124 NEXT_ATTACH_STATE(sc, FINISHED); 4125 4126 ieee80211_announce(ic); 4127 return; 4128 err: 4129 rtw_detach(sc); 4130 return; 4131 } 4132 4133 int 4134 rtw_detach(struct rtw_softc *sc) 4135 { 4136 struct ifnet *ifp = &sc->sc_if; 4137 int pri, s; 4138 4139 s = splnet(); 4140 sc->sc_flags |= RTW_F_INVALID; 4141 4142 switch (sc->sc_attach_state) { 4143 case FINISHED: 4144 rtw_stop(ifp, 1); 4145 4146 pmf_device_deregister(&sc->sc_dev); 4147 callout_stop(&sc->sc_scan_ch); 4148 ieee80211_ifdetach(&sc->sc_ic); 4149 if_detach(ifp); 4150 /*FALLTHROUGH*/ 4151 case FINISH_ID_STA: 4152 case FINISH_RF_ATTACH: 4153 rtw_rf_destroy(sc->sc_rf); 4154 sc->sc_rf = NULL; 4155 /*FALLTHROUGH*/ 4156 case FINISH_PARSE_SROM: 4157 case FINISH_READ_SROM: 4158 rtw_srom_free(&sc->sc_srom); 4159 /*FALLTHROUGH*/ 4160 case FINISH_RESET: 4161 case FINISH_RXMAPS_CREATE: 4162 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4163 RTW_RXQLEN); 4164 /*FALLTHROUGH*/ 4165 case FINISH_TXMAPS_CREATE: 4166 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4167 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4168 sc->sc_txsoft_blk[pri].tsb_desc, 4169 sc->sc_txsoft_blk[pri].tsb_ndesc); 4170 } 4171 /*FALLTHROUGH*/ 4172 case FINISH_TXDESCBLK_SETUP: 4173 case FINISH_TXCTLBLK_SETUP: 4174 rtw_txsoft_blk_cleanup_all(sc); 4175 /*FALLTHROUGH*/ 4176 case FINISH_DESCMAP_LOAD: 4177 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4178 /*FALLTHROUGH*/ 4179 case FINISH_DESCMAP_CREATE: 4180 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4181 /*FALLTHROUGH*/ 4182 case FINISH_DESC_MAP: 4183 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 4184 sizeof(struct rtw_descs)); 4185 /*FALLTHROUGH*/ 4186 case FINISH_DESC_ALLOC: 4187 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4188 sc->sc_desc_nsegs); 4189 /*FALLTHROUGH*/ 4190 case DETACHED: 4191 NEXT_ATTACH_STATE(sc, DETACHED); 4192 break; 4193 } 4194 splx(s); 4195 return 0; 4196 } 4197 4198 int 4199 rtw_activate(struct device *self, enum devact act) 4200 { 4201 struct rtw_softc *sc = (struct rtw_softc *)self; 4202 int rc = 0, s; 4203 4204 s = splnet(); 4205 switch (act) { 4206 case DVACT_ACTIVATE: 4207 rc = EOPNOTSUPP; 4208 break; 4209 4210 case DVACT_DEACTIVATE: 4211 if_deactivate(&sc->sc_if); 4212 break; 4213 } 4214 splx(s); 4215 return rc; 4216 } 4217
Indexes created Sun Sep 28 07:09:56 GMT 2025