rtw.c revision 1.98
1 /* $NetBSD: rtw.c,v 1.98 2007/12/21 18:22:43 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005, 2006, 2007 David Young. All rights 4 * reserved. 5 * 6 * Programmed for NetBSD by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of David Young may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 24 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 26 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /* 34 * Device driver for the Realtek RTL8180 802.11 MAC/BBP. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.98 2007/12/21 18:22:43 dyoung Exp $"); 39 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/sysctl.h> 44 #include <sys/systm.h> 45 #include <sys/callout.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/time.h> 50 #include <sys/types.h> 51 52 #include <machine/endian.h> 53 #include <sys/bus.h> 54 #include <sys/intr.h> /* splnet */ 55 56 #include <uvm/uvm_extern.h> 57 58 #include <net/if.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #include <net80211/ieee80211_netbsd.h> 63 #include <net80211/ieee80211_var.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <dev/ic/rtwreg.h> 71 #include <dev/ic/rtwvar.h> 72 #include <dev/ic/rtwphyio.h> 73 #include <dev/ic/rtwphy.h> 74 75 #include <dev/ic/smc93cx6var.h> 76 77 static int rtw_rfprog_fallback = 0; 78 static int rtw_host_rfio = 0; 79 80 #ifdef RTW_DEBUG 81 int rtw_debug = 0; 82 static int rtw_rxbufs_limit = RTW_RXQLEN; 83 #endif /* RTW_DEBUG */ 84 85 #define NEXT_ATTACH_STATE(sc, state) do { \ 86 DPRINTF(sc, RTW_DEBUG_ATTACH, \ 87 ("%s: attach state %s\n", __func__, #state)); \ 88 sc->sc_attach_state = state; \ 89 } while (0) 90 91 int rtw_dwelltime = 200; /* milliseconds */ 92 static struct ieee80211_cipher rtw_cipher_wep; 93 94 static void rtw_start(struct ifnet *); 95 static void rtw_reset_oactive(struct rtw_softc *); 96 static struct mbuf *rtw_beacon_alloc(struct rtw_softc *, 97 struct ieee80211_node *); 98 static u_int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *); 99 100 static void rtw_io_enable(struct rtw_softc *, uint8_t, int); 101 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 102 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *, 103 const u_int8_t[IEEE80211_ADDR_LEN]); 104 static void rtw_key_update_end(struct ieee80211com *); 105 static void rtw_key_update_begin(struct ieee80211com *); 106 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int); 107 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int); 108 109 static void rtw_led_attach(struct rtw_led_state *, void *); 110 static void rtw_led_init(struct rtw_regs *); 111 static void rtw_led_slowblink(void *); 112 static void rtw_led_fastblink(void *); 113 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int); 114 115 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO); 116 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO); 117 #ifdef RTW_DEBUG 118 static void rtw_dump_rings(struct rtw_softc *sc); 119 static void rtw_print_txdesc(struct rtw_softc *, const char *, 120 struct rtw_txsoft *, struct rtw_txdesc_blk *, int); 121 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO); 122 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO); 123 #endif /* RTW_DEBUG */ 124 #ifdef RTW_DIAG 125 static void rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln); 126 #endif /* RTW_DIAG */ 127 128 /* 129 * Setup sysctl(3) MIB, hw.rtw.* 130 * 131 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 132 */ 133 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup") 134 { 135 int rc; 136 const struct sysctlnode *cnode, *rnode; 137 138 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 139 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 140 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 141 goto err; 142 143 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, 144 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw", 145 "Realtek RTL818x 802.11 controls", 146 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 147 goto err; 148 149 #ifdef RTW_DEBUG 150 /* control debugging printfs */ 151 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 152 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 153 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"), 154 rtw_sysctl_verify_debug, 0, &rtw_debug, 0, 155 CTL_CREATE, CTL_EOL)) != 0) 156 goto err; 157 158 /* Limit rx buffers, for simulating resource exhaustion. */ 159 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 160 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 161 "rxbufs_limit", 162 SYSCTL_DESCR("Set rx buffers limit"), 163 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0, 164 CTL_CREATE, CTL_EOL)) != 0) 165 goto err; 166 167 #endif /* RTW_DEBUG */ 168 /* set fallback RF programming method */ 169 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 170 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 171 "rfprog_fallback", 172 SYSCTL_DESCR("Set fallback RF programming method"), 173 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0, 174 CTL_CREATE, CTL_EOL)) != 0) 175 goto err; 176 177 /* force host to control RF I/O bus */ 178 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 179 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 180 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"), 181 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0, 182 CTL_CREATE, CTL_EOL)) != 0) 183 goto err; 184 185 return; 186 err: 187 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 188 } 189 190 static int 191 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper) 192 { 193 int error, t; 194 struct sysctlnode node; 195 196 node = *rnode; 197 t = *(int*)rnode->sysctl_data; 198 node.sysctl_data = &t; 199 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 200 if (error || newp == NULL) 201 return (error); 202 203 if (t < lower || t > upper) 204 return (EINVAL); 205 206 *(int*)rnode->sysctl_data = t; 207 208 return (0); 209 } 210 211 static int 212 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) 213 { 214 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 215 __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); 216 } 217 218 static int 219 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS) 220 { 221 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1); 222 } 223 224 #ifdef RTW_DEBUG 225 static int 226 rtw_sysctl_verify_debug(SYSCTLFN_ARGS) 227 { 228 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 229 0, RTW_DEBUG_MAX); 230 } 231 232 static int 233 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS) 234 { 235 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 236 0, RTW_RXQLEN); 237 } 238 239 static void 240 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) 241 { 242 #define PRINTREG32(sc, reg) \ 243 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 244 ("%s: reg[ " #reg " / %03x ] = %08x\n", \ 245 dvname, reg, RTW_READ(regs, reg))) 246 247 #define PRINTREG16(sc, reg) \ 248 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 249 ("%s: reg[ " #reg " / %03x ] = %04x\n", \ 250 dvname, reg, RTW_READ16(regs, reg))) 251 252 #define PRINTREG8(sc, reg) \ 253 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \ 254 ("%s: reg[ " #reg " / %03x ] = %02x\n", \ 255 dvname, reg, RTW_READ8(regs, reg))) 256 257 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where)); 258 259 PRINTREG32(regs, RTW_IDR0); 260 PRINTREG32(regs, RTW_IDR1); 261 PRINTREG32(regs, RTW_MAR0); 262 PRINTREG32(regs, RTW_MAR1); 263 PRINTREG32(regs, RTW_TSFTRL); 264 PRINTREG32(regs, RTW_TSFTRH); 265 PRINTREG32(regs, RTW_TLPDA); 266 PRINTREG32(regs, RTW_TNPDA); 267 PRINTREG32(regs, RTW_THPDA); 268 PRINTREG32(regs, RTW_TCR); 269 PRINTREG32(regs, RTW_RCR); 270 PRINTREG32(regs, RTW_TINT); 271 PRINTREG32(regs, RTW_TBDA); 272 PRINTREG32(regs, RTW_ANAPARM); 273 PRINTREG32(regs, RTW_BB); 274 PRINTREG32(regs, RTW_PHYCFG); 275 PRINTREG32(regs, RTW_WAKEUP0L); 276 PRINTREG32(regs, RTW_WAKEUP0H); 277 PRINTREG32(regs, RTW_WAKEUP1L); 278 PRINTREG32(regs, RTW_WAKEUP1H); 279 PRINTREG32(regs, RTW_WAKEUP2LL); 280 PRINTREG32(regs, RTW_WAKEUP2LH); 281 PRINTREG32(regs, RTW_WAKEUP2HL); 282 PRINTREG32(regs, RTW_WAKEUP2HH); 283 PRINTREG32(regs, RTW_WAKEUP3LL); 284 PRINTREG32(regs, RTW_WAKEUP3LH); 285 PRINTREG32(regs, RTW_WAKEUP3HL); 286 PRINTREG32(regs, RTW_WAKEUP3HH); 287 PRINTREG32(regs, RTW_WAKEUP4LL); 288 PRINTREG32(regs, RTW_WAKEUP4LH); 289 PRINTREG32(regs, RTW_WAKEUP4HL); 290 PRINTREG32(regs, RTW_WAKEUP4HH); 291 PRINTREG32(regs, RTW_DK0); 292 PRINTREG32(regs, RTW_DK1); 293 PRINTREG32(regs, RTW_DK2); 294 PRINTREG32(regs, RTW_DK3); 295 PRINTREG32(regs, RTW_RETRYCTR); 296 PRINTREG32(regs, RTW_RDSAR); 297 PRINTREG32(regs, RTW_FER); 298 PRINTREG32(regs, RTW_FEMR); 299 PRINTREG32(regs, RTW_FPSR); 300 PRINTREG32(regs, RTW_FFER); 301 302 /* 16-bit registers */ 303 PRINTREG16(regs, RTW_BRSR); 304 PRINTREG16(regs, RTW_IMR); 305 PRINTREG16(regs, RTW_ISR); 306 PRINTREG16(regs, RTW_BCNITV); 307 PRINTREG16(regs, RTW_ATIMWND); 308 PRINTREG16(regs, RTW_BINTRITV); 309 PRINTREG16(regs, RTW_ATIMTRITV); 310 PRINTREG16(regs, RTW_CRC16ERR); 311 PRINTREG16(regs, RTW_CRC0); 312 PRINTREG16(regs, RTW_CRC1); 313 PRINTREG16(regs, RTW_CRC2); 314 PRINTREG16(regs, RTW_CRC3); 315 PRINTREG16(regs, RTW_CRC4); 316 PRINTREG16(regs, RTW_CWR); 317 318 /* 8-bit registers */ 319 PRINTREG8(regs, RTW_CR); 320 PRINTREG8(regs, RTW_9346CR); 321 PRINTREG8(regs, RTW_CONFIG0); 322 PRINTREG8(regs, RTW_CONFIG1); 323 PRINTREG8(regs, RTW_CONFIG2); 324 PRINTREG8(regs, RTW_MSR); 325 PRINTREG8(regs, RTW_CONFIG3); 326 PRINTREG8(regs, RTW_CONFIG4); 327 PRINTREG8(regs, RTW_TESTR); 328 PRINTREG8(regs, RTW_PSR); 329 PRINTREG8(regs, RTW_SCR); 330 PRINTREG8(regs, RTW_PHYDELAY); 331 PRINTREG8(regs, RTW_CRCOUNT); 332 PRINTREG8(regs, RTW_PHYADDR); 333 PRINTREG8(regs, RTW_PHYDATAW); 334 PRINTREG8(regs, RTW_PHYDATAR); 335 PRINTREG8(regs, RTW_CONFIG5); 336 PRINTREG8(regs, RTW_TPPOLL); 337 338 PRINTREG16(regs, RTW_BSSID16); 339 PRINTREG32(regs, RTW_BSSID32); 340 #undef PRINTREG32 341 #undef PRINTREG16 342 #undef PRINTREG8 343 } 344 #endif /* RTW_DEBUG */ 345 346 void 347 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable) 348 { 349 struct rtw_regs *regs = &sc->sc_regs; 350 351 uint32_t tcr; 352 tcr = RTW_READ(regs, RTW_TCR); 353 tcr &= ~RTW_TCR_LBK_MASK; 354 if (enable) 355 tcr |= RTW_TCR_LBK_CONT; 356 else 357 tcr |= RTW_TCR_LBK_NORMAL; 358 RTW_WRITE(regs, RTW_TCR, tcr); 359 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 360 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 361 rtw_txdac_enable(sc, !enable); 362 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */ 363 rtw_set_access(regs, RTW_ACCESS_NONE); 364 } 365 366 #ifdef RTW_DEBUG 367 static const char * 368 rtw_access_string(enum rtw_access access) 369 { 370 switch (access) { 371 case RTW_ACCESS_NONE: 372 return "none"; 373 case RTW_ACCESS_CONFIG: 374 return "config"; 375 case RTW_ACCESS_ANAPARM: 376 return "anaparm"; 377 default: 378 return "unknown"; 379 } 380 } 381 #endif /* RTW_DEBUG */ 382 383 static void 384 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) 385 { 386 KASSERT(/* naccess >= RTW_ACCESS_NONE && */ 387 naccess <= RTW_ACCESS_ANAPARM); 388 KASSERT(/* regs->r_access >= RTW_ACCESS_NONE && */ 389 regs->r_access <= RTW_ACCESS_ANAPARM); 390 391 if (naccess == regs->r_access) 392 return; 393 394 switch (naccess) { 395 case RTW_ACCESS_NONE: 396 switch (regs->r_access) { 397 case RTW_ACCESS_ANAPARM: 398 rtw_anaparm_enable(regs, 0); 399 /*FALLTHROUGH*/ 400 case RTW_ACCESS_CONFIG: 401 rtw_config0123_enable(regs, 0); 402 /*FALLTHROUGH*/ 403 case RTW_ACCESS_NONE: 404 break; 405 } 406 break; 407 case RTW_ACCESS_CONFIG: 408 switch (regs->r_access) { 409 case RTW_ACCESS_NONE: 410 rtw_config0123_enable(regs, 1); 411 /*FALLTHROUGH*/ 412 case RTW_ACCESS_CONFIG: 413 break; 414 case RTW_ACCESS_ANAPARM: 415 rtw_anaparm_enable(regs, 0); 416 break; 417 } 418 break; 419 case RTW_ACCESS_ANAPARM: 420 switch (regs->r_access) { 421 case RTW_ACCESS_NONE: 422 rtw_config0123_enable(regs, 1); 423 /*FALLTHROUGH*/ 424 case RTW_ACCESS_CONFIG: 425 rtw_anaparm_enable(regs, 1); 426 /*FALLTHROUGH*/ 427 case RTW_ACCESS_ANAPARM: 428 break; 429 } 430 break; 431 } 432 } 433 434 void 435 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) 436 { 437 rtw_set_access1(regs, access); 438 RTW_DPRINTF(RTW_DEBUG_ACCESS, 439 ("%s: access %s -> %s\n", __func__, 440 rtw_access_string(regs->r_access), 441 rtw_access_string(access))); 442 regs->r_access = access; 443 } 444 445 /* 446 * Enable registers, switch register banks. 447 */ 448 void 449 rtw_config0123_enable(struct rtw_regs *regs, int enable) 450 { 451 uint8_t ecr; 452 ecr = RTW_READ8(regs, RTW_9346CR); 453 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK); 454 if (enable) 455 ecr |= RTW_9346CR_EEM_CONFIG; 456 else { 457 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3)); 458 ecr |= RTW_9346CR_EEM_NORMAL; 459 } 460 RTW_WRITE8(regs, RTW_9346CR, ecr); 461 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR); 462 } 463 464 /* requires rtw_config0123_enable(, 1) */ 465 void 466 rtw_anaparm_enable(struct rtw_regs *regs, int enable) 467 { 468 uint8_t cfg3; 469 470 cfg3 = RTW_READ8(regs, RTW_CONFIG3); 471 cfg3 |= RTW_CONFIG3_CLKRUNEN; 472 if (enable) 473 cfg3 |= RTW_CONFIG3_PARMEN; 474 else 475 cfg3 &= ~RTW_CONFIG3_PARMEN; 476 RTW_WRITE8(regs, RTW_CONFIG3, cfg3); 477 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3); 478 } 479 480 /* requires rtw_anaparm_enable(, 1) */ 481 void 482 rtw_txdac_enable(struct rtw_softc *sc, int enable) 483 { 484 uint32_t anaparm; 485 struct rtw_regs *regs = &sc->sc_regs; 486 487 anaparm = RTW_READ(regs, RTW_ANAPARM); 488 if (enable) 489 anaparm &= ~RTW_ANAPARM_TXDACOFF; 490 else 491 anaparm |= RTW_ANAPARM_TXDACOFF; 492 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 493 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 494 } 495 496 static inline int 497 rtw_chip_reset1(struct rtw_regs *regs, device_t dev) 498 { 499 uint8_t cr; 500 int i; 501 502 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST); 503 504 RTW_WBR(regs, RTW_CR, RTW_CR); 505 506 for (i = 0; i < 1000; i++) { 507 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) { 508 RTW_DPRINTF(RTW_DEBUG_RESET, 509 ("%s: reset in %dus\n", device_xname(dev), i)); 510 return 0; 511 } 512 RTW_RBR(regs, RTW_CR, RTW_CR); 513 DELAY(10); /* 10us */ 514 } 515 516 aprint_error_dev(dev, "reset failed\n"); 517 return ETIMEDOUT; 518 } 519 520 static inline int 521 rtw_chip_reset(struct rtw_regs *regs, device_t dev) 522 { 523 uint32_t tcr; 524 525 /* from Linux driver */ 526 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 527 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK); 528 529 RTW_WRITE(regs, RTW_TCR, tcr); 530 531 RTW_WBW(regs, RTW_CR, RTW_TCR); 532 533 return rtw_chip_reset1(regs, dev); 534 } 535 536 static int 537 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen) 538 { 539 struct ieee80211_key keycopy; 540 541 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__)); 542 543 keycopy = *k; 544 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT; 545 546 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, hdrlen); 547 } 548 549 static int 550 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 551 { 552 struct rtw_softc *sc = ic->ic_ifp->if_softc; 553 u_int keyix = k->wk_keyix; 554 555 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix)); 556 557 if (keyix >= IEEE80211_WEP_NKID) 558 return 0; 559 if (k->wk_keylen != 0) 560 sc->sc_flags &= ~RTW_F_DK_VALID; 561 562 return 1; 563 } 564 565 static int 566 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 567 const u_int8_t mac[IEEE80211_ADDR_LEN]) 568 { 569 struct rtw_softc *sc = ic->ic_ifp->if_softc; 570 571 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix)); 572 573 if (k->wk_keyix >= IEEE80211_WEP_NKID) 574 return 0; 575 576 sc->sc_flags &= ~RTW_F_DK_VALID; 577 578 return 1; 579 } 580 581 static void 582 rtw_key_update_begin(struct ieee80211com *ic) 583 { 584 #ifdef RTW_DEBUG 585 struct ifnet *ifp = ic->ic_ifp; 586 struct rtw_softc *sc = ifp->if_softc; 587 #endif 588 589 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 590 } 591 592 static void 593 rtw_key_update_end(struct ieee80211com *ic) 594 { 595 struct ifnet *ifp = ic->ic_ifp; 596 struct rtw_softc *sc = ifp->if_softc; 597 598 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__)); 599 600 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 || 601 (sc->sc_flags & RTW_F_ENABLED) == 0 || 602 (sc->sc_flags & RTW_F_INVALID) != 0) 603 return; 604 605 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 606 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 607 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 608 (ifp->if_flags & IFF_RUNNING) != 0); 609 } 610 611 static inline int 612 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k) 613 { 614 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 615 return 0; 616 617 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) || 618 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13); 619 } 620 621 static void 622 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey) 623 { 624 uint8_t psr, scr; 625 int i, keylen; 626 struct rtw_regs *regs; 627 union rtw_keys *rk; 628 629 regs = &sc->sc_regs; 630 rk = &sc->sc_keys; 631 632 (void)memset(rk, 0, sizeof(rk)); 633 634 /* Temporarily use software crypto for all keys. */ 635 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 636 if (wk[i].wk_cipher == &rtw_cipher_wep) 637 wk[i].wk_cipher = &ieee80211_cipher_wep; 638 } 639 640 rtw_set_access(regs, RTW_ACCESS_CONFIG); 641 642 psr = RTW_READ8(regs, RTW_PSR); 643 scr = RTW_READ8(regs, RTW_SCR); 644 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON); 645 646 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 647 goto out; 648 649 for (keylen = i = 0; i < IEEE80211_WEP_NKID; i++) { 650 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i])) 651 continue; 652 if (i == txkey) { 653 keylen = wk[i].wk_keylen; 654 break; 655 } 656 keylen = MAX(keylen, wk[i].wk_keylen); 657 } 658 659 if (keylen == 5) 660 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON; 661 else if (keylen == 13) 662 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON; 663 664 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 665 if (wk[i].wk_keylen != keylen || 666 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) 667 continue; 668 /* h/w will decrypt, s/w still strips headers */ 669 wk[i].wk_cipher = &rtw_cipher_wep; 670 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen); 671 } 672 673 out: 674 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN); 675 676 bus_space_write_region_stream_4(regs->r_bt, regs->r_bh, 677 RTW_DK0, rk->rk_words, __arraycount(rk->rk_words)); 678 679 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words), 680 BUS_SPACE_BARRIER_SYNC); 681 682 RTW_WBW(regs, RTW_DK0, RTW_PSR); 683 RTW_WRITE8(regs, RTW_PSR, psr); 684 RTW_WBW(regs, RTW_PSR, RTW_SCR); 685 RTW_WRITE8(regs, RTW_SCR, scr); 686 RTW_SYNC(regs, RTW_SCR, RTW_SCR); 687 rtw_set_access(regs, RTW_ACCESS_NONE); 688 sc->sc_flags |= RTW_F_DK_VALID; 689 } 690 691 static inline int 692 rtw_recall_eeprom(struct rtw_regs *regs, device_t dev) 693 { 694 int i; 695 uint8_t ecr; 696 697 ecr = RTW_READ8(regs, RTW_9346CR); 698 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD; 699 RTW_WRITE8(regs, RTW_9346CR, ecr); 700 701 RTW_WBR(regs, RTW_9346CR, RTW_9346CR); 702 703 /* wait 25ms for completion */ 704 for (i = 0; i < 250; i++) { 705 ecr = RTW_READ8(regs, RTW_9346CR); 706 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) { 707 RTW_DPRINTF(RTW_DEBUG_RESET, 708 ("%s: recall EEPROM in %dus\n", device_xname(dev), 709 i * 100)); 710 return 0; 711 } 712 RTW_RBR(regs, RTW_9346CR, RTW_9346CR); 713 DELAY(100); 714 } 715 aprint_error_dev(dev, "recall EEPROM failed\n"); 716 return ETIMEDOUT; 717 } 718 719 static inline int 720 rtw_reset(struct rtw_softc *sc) 721 { 722 int rc; 723 uint8_t config1; 724 725 sc->sc_flags &= ~RTW_F_DK_VALID; 726 727 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev)) != 0) 728 return rc; 729 730 rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev); 731 732 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1); 733 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN); 734 /* TBD turn off maximum power saving? */ 735 736 return 0; 737 } 738 739 static inline int 740 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 741 u_int ndescs) 742 { 743 int i, rc = 0; 744 for (i = 0; i < ndescs; i++) { 745 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES, 746 0, 0, &descs[i].ts_dmamap); 747 if (rc != 0) 748 break; 749 } 750 return rc; 751 } 752 753 static inline int 754 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 755 u_int ndescs) 756 { 757 int i, rc = 0; 758 for (i = 0; i < ndescs; i++) { 759 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 760 &descs[i].rs_dmamap); 761 if (rc != 0) 762 break; 763 } 764 return rc; 765 } 766 767 static inline void 768 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs, 769 u_int ndescs) 770 { 771 int i; 772 for (i = 0; i < ndescs; i++) { 773 if (descs[i].rs_dmamap != NULL) 774 bus_dmamap_destroy(dmat, descs[i].rs_dmamap); 775 } 776 } 777 778 static inline void 779 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs, 780 u_int ndescs) 781 { 782 int i; 783 for (i = 0; i < ndescs; i++) { 784 if (descs[i].ts_dmamap != NULL) 785 bus_dmamap_destroy(dmat, descs[i].ts_dmamap); 786 } 787 } 788 789 static inline void 790 rtw_srom_free(struct rtw_srom *sr) 791 { 792 sr->sr_size = 0; 793 if (sr->sr_content == NULL) 794 return; 795 free(sr->sr_content, M_DEVBUF); 796 sr->sr_content = NULL; 797 } 798 799 static void 800 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, 801 uint8_t *cs_threshold, enum rtw_rfchipid *rfchipid, uint32_t *rcr) 802 { 803 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV); 804 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT; 805 *rcr |= RTW_RCR_ENCS1; 806 *rfchipid = RTW_RFCHIPID_PHILIPS; 807 } 808 809 static int 810 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, 811 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale, 812 device_t dev) 813 { 814 int i; 815 const char *rfname, *paname; 816 char scratch[sizeof("unknown 0xXX")]; 817 uint16_t srom_version; 818 uint8_t mac[IEEE80211_ADDR_LEN]; 819 820 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV); 821 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2); 822 823 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION); 824 825 if (srom_version <= 0x0101) { 826 aprint_error_dev(dev, 827 "SROM version %d.%d is not understood, " 828 "limping along with defaults\n", 829 srom_version >> 8, srom_version & 0xff); 830 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr); 831 return 0; 832 } else { 833 aprint_verbose_dev(dev, "SROM version %d.%d", 834 srom_version >> 8, srom_version & 0xff); 835 } 836 837 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 838 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i); 839 840 RTW_DPRINTF(RTW_DEBUG_ATTACH, 841 ("%s: EEPROM MAC %s\n", device_xname(dev), ether_sprintf(mac))); 842 843 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR); 844 845 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0) 846 *flags |= RTW_F_ANTDIV; 847 848 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems 849 * to be reversed. 850 */ 851 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0) 852 *flags |= RTW_F_DIGPHY; 853 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) 854 *flags |= RTW_F_DFLANTB; 855 856 *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), 857 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); 858 859 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0) 860 *flags |= RTW_C_RXWEP_104; 861 862 *flags |= RTW_C_RXWEP_40; /* XXX */ 863 864 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID); 865 switch (*rfchipid) { 866 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */ 867 rfname = "GCT GRF5101"; 868 paname = "Winspring WS9901"; 869 break; 870 case RTW_RFCHIPID_MAXIM: 871 rfname = "Maxim MAX2820"; /* guess */ 872 paname = "Maxim MAX2422"; /* guess */ 873 break; 874 case RTW_RFCHIPID_INTERSIL: 875 rfname = "Intersil HFA3873"; /* guess */ 876 paname = "Intersil <unknown>"; 877 break; 878 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */ 879 rfname = "Philips SA2400A"; 880 paname = "Philips SA2411"; 881 break; 882 case RTW_RFCHIPID_RFMD: 883 /* this is the same front-end as an atw(4)! */ 884 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */ 885 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */ 886 "SYN: Silicon Labs Si4126"; /* inferred from 887 * reference driver 888 */ 889 paname = "RFMD RF2189"; /* mentioned in Realtek docs */ 890 break; 891 case RTW_RFCHIPID_RESERVED: 892 rfname = paname = "reserved"; 893 break; 894 default: 895 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid); 896 rfname = paname = scratch; 897 } 898 aprint_normal_dev(dev, "RF: %s, PA: %s\n", rfname, paname); 899 900 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) { 901 case RTW_CONFIG0_GL_USA: 902 case _RTW_CONFIG0_GL_USA: 903 *locale = RTW_LOCALE_USA; 904 break; 905 case RTW_CONFIG0_GL_EUROPE: 906 *locale = RTW_LOCALE_EUROPE; 907 break; 908 case RTW_CONFIG0_GL_JAPAN: 909 *locale = RTW_LOCALE_JAPAN; 910 break; 911 default: 912 *locale = RTW_LOCALE_UNKNOWN; 913 break; 914 } 915 return 0; 916 } 917 918 /* Returns -1 on failure. */ 919 static int 920 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, 921 device_t dev) 922 { 923 int rc; 924 struct seeprom_descriptor sd; 925 uint8_t ecr; 926 927 (void)memset(&sd, 0, sizeof(sd)); 928 929 ecr = RTW_READ8(regs, RTW_9346CR); 930 931 if ((flags & RTW_F_9356SROM) != 0) { 932 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n", 933 device_xname(dev))); 934 sr->sr_size = 256; 935 sd.sd_chip = C56_66; 936 } else { 937 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n", 938 device_xname(dev))); 939 sr->sr_size = 128; 940 sd.sd_chip = C46; 941 } 942 943 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK | 944 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS); 945 ecr |= RTW_9346CR_EEM_PROGRAM; 946 947 RTW_WRITE8(regs, RTW_9346CR, ecr); 948 949 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT); 950 951 if (sr->sr_content == NULL) { 952 aprint_error_dev(dev, "unable to allocate SROM buffer\n"); 953 return ENOMEM; 954 } 955 956 (void)memset(sr->sr_content, 0, sr->sr_size); 957 958 /* RTL8180 has a single 8-bit register for controlling the 959 * 93cx6 SROM. There is no "ready" bit. The RTL8180 960 * input/output sense is the reverse of read_seeprom's. 961 */ 962 sd.sd_tag = regs->r_bt; 963 sd.sd_bsh = regs->r_bh; 964 sd.sd_regsize = 1; 965 sd.sd_control_offset = RTW_9346CR; 966 sd.sd_status_offset = RTW_9346CR; 967 sd.sd_dataout_offset = RTW_9346CR; 968 sd.sd_CK = RTW_9346CR_EESK; 969 sd.sd_CS = RTW_9346CR_EECS; 970 sd.sd_DI = RTW_9346CR_EEDO; 971 sd.sd_DO = RTW_9346CR_EEDI; 972 /* make read_seeprom enter EEPROM read/write mode */ 973 sd.sd_MS = ecr; 974 sd.sd_RDY = 0; 975 976 /* TBD bus barriers */ 977 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) { 978 aprint_error_dev(dev, "could not read SROM\n"); 979 free(sr->sr_content, M_DEVBUF); 980 sr->sr_content = NULL; 981 return -1; /* XXX */ 982 } 983 984 /* end EEPROM read/write mode */ 985 RTW_WRITE8(regs, RTW_9346CR, 986 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL); 987 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR); 988 989 if ((rc = rtw_recall_eeprom(regs, dev)) != 0) 990 return rc; 991 992 #ifdef RTW_DEBUG 993 { 994 int i; 995 RTW_DPRINTF(RTW_DEBUG_ATTACH, 996 ("\n%s: serial ROM:\n\t", device_xname(dev))); 997 for (i = 0; i < sr->sr_size/2; i++) { 998 if (((i % 8) == 0) && (i != 0)) 999 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t")); 1000 RTW_DPRINTF(RTW_DEBUG_ATTACH, 1001 (" %04x", sr->sr_content[i])); 1002 } 1003 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n")); 1004 } 1005 #endif /* RTW_DEBUG */ 1006 return 0; 1007 } 1008 1009 static void 1010 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 1011 device_t dev) 1012 { 1013 uint8_t cfg4; 1014 const char *method; 1015 1016 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK; 1017 1018 switch (rfchipid) { 1019 default: 1020 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); 1021 method = "fallback"; 1022 break; 1023 case RTW_RFCHIPID_INTERSIL: 1024 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL; 1025 method = "Intersil"; 1026 break; 1027 case RTW_RFCHIPID_PHILIPS: 1028 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS; 1029 method = "Philips"; 1030 break; 1031 case RTW_RFCHIPID_GCT: /* XXX a guess */ 1032 case RTW_RFCHIPID_RFMD: 1033 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD; 1034 method = "RFMD"; 1035 break; 1036 } 1037 1038 RTW_WRITE8(regs, RTW_CONFIG4, cfg4); 1039 1040 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4); 1041 1042 RTW_DPRINTF(RTW_DEBUG_INIT, 1043 ("%s: %s RF programming method, %#02x\n", device_xname(dev), method, 1044 RTW_READ8(regs, RTW_CONFIG4))); 1045 } 1046 1047 static inline void 1048 rtw_init_channels(enum rtw_locale locale, 1049 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], device_t dev) 1050 { 1051 int i; 1052 const char *name = NULL; 1053 #define ADD_CHANNEL(_chans, _chan) do { \ 1054 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \ 1055 (*_chans)[_chan].ic_freq = \ 1056 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\ 1057 } while (0) 1058 1059 switch (locale) { 1060 case RTW_LOCALE_USA: /* 1-11 */ 1061 name = "USA"; 1062 for (i = 1; i <= 11; i++) 1063 ADD_CHANNEL(chans, i); 1064 break; 1065 case RTW_LOCALE_JAPAN: /* 1-14 */ 1066 name = "Japan"; 1067 ADD_CHANNEL(chans, 14); 1068 for (i = 1; i <= 14; i++) 1069 ADD_CHANNEL(chans, i); 1070 break; 1071 case RTW_LOCALE_EUROPE: /* 1-13 */ 1072 name = "Europe"; 1073 for (i = 1; i <= 13; i++) 1074 ADD_CHANNEL(chans, i); 1075 break; 1076 default: /* 10-11 allowed by most countries */ 1077 name = "<unknown>"; 1078 for (i = 10; i <= 11; i++) 1079 ADD_CHANNEL(chans, i); 1080 break; 1081 } 1082 aprint_normal_dev(dev, "Geographic Location %s\n", name); 1083 #undef ADD_CHANNEL 1084 } 1085 1086 1087 static inline void 1088 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale) 1089 { 1090 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0); 1091 1092 switch (cfg0 & RTW_CONFIG0_GL_MASK) { 1093 case RTW_CONFIG0_GL_USA: 1094 case _RTW_CONFIG0_GL_USA: 1095 *locale = RTW_LOCALE_USA; 1096 break; 1097 case RTW_CONFIG0_GL_JAPAN: 1098 *locale = RTW_LOCALE_JAPAN; 1099 break; 1100 case RTW_CONFIG0_GL_EUROPE: 1101 *locale = RTW_LOCALE_EUROPE; 1102 break; 1103 default: 1104 *locale = RTW_LOCALE_UNKNOWN; 1105 break; 1106 } 1107 } 1108 1109 static inline int 1110 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], 1111 device_t dev) 1112 { 1113 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 1114 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1115 }; 1116 uint32_t idr0 = RTW_READ(regs, RTW_IDR0), 1117 idr1 = RTW_READ(regs, RTW_IDR1); 1118 1119 (*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7)); 1120 (*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15)); 1121 (*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23)); 1122 (*addr)[3] = __SHIFTOUT(idr0, __BITS(24 ,31)); 1123 1124 (*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7)); 1125 (*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15)); 1126 1127 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { 1128 aprint_error_dev(dev, 1129 "could not get mac address, attach failed\n"); 1130 return ENXIO; 1131 } 1132 1133 aprint_normal_dev(dev, "802.11 address %s\n", ether_sprintf(*addr)); 1134 1135 return 0; 1136 } 1137 1138 static uint8_t 1139 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic, 1140 struct ieee80211_channel *chan) 1141 { 1142 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1; 1143 KASSERT(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14); 1144 return RTW_SR_GET(sr, idx); 1145 } 1146 1147 static void 1148 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb) 1149 { 1150 int pri; 1151 /* nfree: the number of free descriptors in each ring. 1152 * The beacon ring is a special case: I do not let the 1153 * driver use all of the descriptors on the beacon ring. 1154 * The reasons are two-fold: 1155 * 1156 * (1) A BEACON descriptor's OWN bit is (apparently) not 1157 * updated, so the driver cannot easily know if the descriptor 1158 * belongs to it, or if it is racing the NIC. If the NIC 1159 * does not OWN every descriptor, then the driver can safely 1160 * update the descriptors when RTW_TBDA points at tdb_next. 1161 * 1162 * (2) I hope that the NIC will process more than one BEACON 1163 * descriptor in a single beacon interval, since that will 1164 * enable multiple-BSS support. Since the NIC does not 1165 * clear the OWN bit, there is no natural place for it to 1166 * stop processing BEACON desciptors. Maybe it will *not* 1167 * stop processing them! I do not want to chance the NIC 1168 * looping around and around a saturated beacon ring, so 1169 * I will leave one descriptor unOWNed at all times. 1170 */ 1171 u_int nfree[RTW_NTXPRI] = 1172 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI, 1173 RTW_NTXDESCBCN - 1}; 1174 1175 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1176 tdb[pri].tdb_nfree = nfree[pri]; 1177 tdb[pri].tdb_next = 0; 1178 } 1179 } 1180 1181 static int 1182 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb) 1183 { 1184 int i; 1185 struct rtw_txsoft *ts; 1186 1187 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 1188 SIMPLEQ_INIT(&tsb->tsb_freeq); 1189 for (i = 0; i < tsb->tsb_ndesc; i++) { 1190 ts = &tsb->tsb_desc[i]; 1191 ts->ts_mbuf = NULL; 1192 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1193 } 1194 tsb->tsb_tx_timer = 0; 1195 return 0; 1196 } 1197 1198 static void 1199 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb) 1200 { 1201 int pri; 1202 for (pri = 0; pri < RTW_NTXPRI; pri++) 1203 rtw_txsoft_blk_init(&tsb[pri]); 1204 } 1205 1206 static inline void 1207 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops) 1208 { 1209 KASSERT(nsync <= rdb->rdb_ndesc); 1210 /* sync to end of ring */ 1211 if (desc0 + nsync > rdb->rdb_ndesc) { 1212 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1213 offsetof(struct rtw_descs, hd_rx[desc0]), 1214 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops); 1215 nsync -= (rdb->rdb_ndesc - desc0); 1216 desc0 = 0; 1217 } 1218 1219 KASSERT(desc0 < rdb->rdb_ndesc); 1220 KASSERT(nsync <= rdb->rdb_ndesc); 1221 KASSERT(desc0 + nsync <= rdb->rdb_ndesc); 1222 1223 /* sync what remains */ 1224 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1225 offsetof(struct rtw_descs, hd_rx[desc0]), 1226 sizeof(struct rtw_rxdesc) * nsync, ops); 1227 } 1228 1229 static void 1230 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops) 1231 { 1232 /* sync to end of ring */ 1233 if (desc0 + nsync > tdb->tdb_ndesc) { 1234 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1235 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1236 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0), 1237 ops); 1238 nsync -= (tdb->tdb_ndesc - desc0); 1239 desc0 = 0; 1240 } 1241 1242 /* sync what remains */ 1243 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap, 1244 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0, 1245 sizeof(struct rtw_txdesc) * nsync, ops); 1246 } 1247 1248 static void 1249 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb) 1250 { 1251 int pri; 1252 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1253 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc, 1254 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1255 } 1256 } 1257 1258 static void 1259 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc) 1260 { 1261 int i; 1262 struct rtw_rxsoft *rs; 1263 1264 for (i = 0; i < RTW_RXQLEN; i++) { 1265 rs = &desc[i]; 1266 if (rs->rs_mbuf == NULL) 1267 continue; 1268 bus_dmamap_sync(dmat, rs->rs_dmamap, 0, 1269 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1270 bus_dmamap_unload(dmat, rs->rs_dmamap); 1271 m_freem(rs->rs_mbuf); 1272 rs->rs_mbuf = NULL; 1273 } 1274 } 1275 1276 static inline int 1277 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs) 1278 { 1279 int rc; 1280 struct mbuf *m; 1281 1282 MGETHDR(m, M_DONTWAIT, MT_DATA); 1283 if (m == NULL) 1284 return ENOBUFS; 1285 1286 MCLGET(m, M_DONTWAIT); 1287 if ((m->m_flags & M_EXT) == 0) { 1288 m_freem(m); 1289 return ENOBUFS; 1290 } 1291 1292 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1293 1294 if (rs->rs_mbuf != NULL) 1295 bus_dmamap_unload(dmat, rs->rs_dmamap); 1296 1297 rs->rs_mbuf = NULL; 1298 1299 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT); 1300 if (rc != 0) { 1301 m_freem(m); 1302 return -1; 1303 } 1304 1305 rs->rs_mbuf = m; 1306 1307 return 0; 1308 } 1309 1310 static int 1311 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc, 1312 int *ndesc, device_t dev) 1313 { 1314 int i, rc = 0; 1315 struct rtw_rxsoft *rs; 1316 1317 for (i = 0; i < RTW_RXQLEN; i++) { 1318 rs = &desc[i]; 1319 /* we're in rtw_init, so there should be no mbufs allocated */ 1320 KASSERT(rs->rs_mbuf == NULL); 1321 #ifdef RTW_DEBUG 1322 if (i == rtw_rxbufs_limit) { 1323 aprint_error_dev(dev, "TEST hit %d-buffer limit\n", i); 1324 rc = ENOBUFS; 1325 break; 1326 } 1327 #endif /* RTW_DEBUG */ 1328 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) { 1329 aprint_error_dev(dev, 1330 "rtw_rxsoft_alloc failed, %d buffers, rc %d\n", 1331 i, rc); 1332 break; 1333 } 1334 } 1335 *ndesc = i; 1336 return rc; 1337 } 1338 1339 static inline void 1340 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, 1341 int idx, int kick) 1342 { 1343 int is_last = (idx == rdb->rdb_ndesc - 1); 1344 uint32_t ctl, octl, obuf; 1345 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx]; 1346 1347 /* sync the mbuf before the descriptor */ 1348 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0, 1349 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1350 1351 obuf = rd->rd_buf; 1352 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); 1353 1354 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | 1355 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; 1356 1357 if (is_last) 1358 ctl |= RTW_RXCTL_EOR; 1359 1360 octl = rd->rd_ctl; 1361 rd->rd_ctl = htole32(ctl); 1362 1363 RTW_DPRINTF( 1364 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK) 1365 : RTW_DEBUG_RECV_DESC, 1366 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd, 1367 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl), 1368 le32toh(rd->rd_ctl))); 1369 1370 /* sync the descriptor */ 1371 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, 1372 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc), 1373 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1374 } 1375 1376 static void 1377 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick) 1378 { 1379 int i; 1380 struct rtw_rxdesc *rd; 1381 struct rtw_rxsoft *rs; 1382 1383 for (i = 0; i < rdb->rdb_ndesc; i++) { 1384 rd = &rdb->rdb_desc[i]; 1385 rs = &ctl[i]; 1386 rtw_rxdesc_init(rdb, rs, i, kick); 1387 } 1388 } 1389 1390 static void 1391 rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable) 1392 { 1393 struct rtw_regs *regs = &sc->sc_regs; 1394 uint8_t cr; 1395 1396 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__, 1397 enable ? "enable" : "disable", flags)); 1398 1399 cr = RTW_READ8(regs, RTW_CR); 1400 1401 /* XXX reference source does not enable MULRW */ 1402 /* enable PCI Read/Write Multiple */ 1403 cr |= RTW_CR_MULRW; 1404 1405 /* The receive engine will always start at RDSAR. */ 1406 if (enable && (flags & ~cr & RTW_CR_RE)) { 1407 struct rtw_rxdesc_blk *rdb; 1408 rdb = &sc->sc_rxdesc_blk; 1409 rdb->rdb_next = 0; 1410 } 1411 1412 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */ 1413 if (enable) 1414 cr |= flags; 1415 else 1416 cr &= ~flags; 1417 RTW_WRITE8(regs, RTW_CR, cr); 1418 RTW_SYNC(regs, RTW_CR, RTW_CR); 1419 1420 #ifdef RTW_DIAG 1421 if (cr & RTW_CR_TE) 1422 rtw_txring_fixup(sc, __func__, __LINE__); 1423 #endif 1424 } 1425 1426 static void 1427 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) 1428 { 1429 #define IS_BEACON(__fc0) \ 1430 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\ 1431 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON)) 1432 1433 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates: 1434 * hardware -> net80211 1435 */ 1436 u_int next, nproc = 0; 1437 int hwrate, len, rate, rssi, sq; 1438 uint32_t hrssi, hstat, htsfth, htsftl; 1439 struct rtw_rxdesc *rd; 1440 struct rtw_rxsoft *rs; 1441 struct rtw_rxdesc_blk *rdb; 1442 struct mbuf *m; 1443 struct ifnet *ifp = &sc->sc_if; 1444 1445 struct ieee80211_node *ni; 1446 struct ieee80211_frame_min *wh; 1447 1448 rdb = &sc->sc_rxdesc_blk; 1449 1450 for (next = rdb->rdb_next; ; next = rdb->rdb_next) { 1451 KASSERT(next < rdb->rdb_ndesc); 1452 1453 rtw_rxdescs_sync(rdb, next, 1, 1454 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1455 rd = &rdb->rdb_desc[next]; 1456 rs = &sc->sc_rxsoft[next]; 1457 1458 hstat = le32toh(rd->rd_stat); 1459 hrssi = le32toh(rd->rd_rssi); 1460 htsfth = le32toh(rd->rd_tsfth); 1461 htsftl = le32toh(rd->rd_tsftl); 1462 1463 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1464 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n", 1465 __func__, next, hstat, hrssi, htsfth, htsftl)); 1466 1467 ++nproc; 1468 1469 /* still belongs to NIC */ 1470 if ((hstat & RTW_RXSTAT_OWN) != 0) { 1471 rtw_rxdescs_sync(rdb, next, 1, BUS_DMASYNC_PREREAD); 1472 break; 1473 } 1474 1475 /* ieee80211_input() might reset the receive engine 1476 * (e.g. by indirectly calling rtw_tune()), so save 1477 * the next pointer here and retrieve it again on 1478 * the next round. 1479 */ 1480 rdb->rdb_next = (next + 1) % rdb->rdb_ndesc; 1481 1482 #ifdef RTW_DEBUG 1483 #define PRINTSTAT(flag) do { \ 1484 if ((hstat & flag) != 0) { \ 1485 printf("%s" #flag, delim); \ 1486 delim = ","; \ 1487 } \ 1488 } while (0) 1489 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) { 1490 const char *delim = "<"; 1491 printf("%s: ", device_xname(sc->sc_dev)); 1492 if ((hstat & RTW_RXSTAT_DEBUG) != 0) { 1493 printf("status %08x", hstat); 1494 PRINTSTAT(RTW_RXSTAT_SPLCP); 1495 PRINTSTAT(RTW_RXSTAT_MAR); 1496 PRINTSTAT(RTW_RXSTAT_PAR); 1497 PRINTSTAT(RTW_RXSTAT_BAR); 1498 PRINTSTAT(RTW_RXSTAT_PWRMGT); 1499 PRINTSTAT(RTW_RXSTAT_CRC32); 1500 PRINTSTAT(RTW_RXSTAT_ICV); 1501 printf(">, "); 1502 } 1503 } 1504 #endif /* RTW_DEBUG */ 1505 1506 if ((hstat & RTW_RXSTAT_IOERROR) != 0) { 1507 aprint_error_dev(sc->sc_dev, 1508 "DMA error/FIFO overflow %08" PRIx32 ", " 1509 "rx descriptor %d\n", hstat, next); 1510 ifp->if_ierrors++; 1511 goto next; 1512 } 1513 1514 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); 1515 if (len < IEEE80211_MIN_LEN) { 1516 sc->sc_ic.ic_stats.is_rx_tooshort++; 1517 goto next; 1518 } 1519 if (len > rs->rs_mbuf->m_len) { 1520 aprint_error_dev(sc->sc_dev, "rx frame too long\n"); 1521 ifp->if_ierrors++; 1522 goto next; 1523 } 1524 1525 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); 1526 if (hwrate >= __arraycount(ratetbl)) { 1527 aprint_error_dev(sc->sc_dev, 1528 "unknown rate #%" __PRIuBITS "\n", 1529 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); 1530 ifp->if_ierrors++; 1531 goto next; 1532 } 1533 rate = ratetbl[hwrate]; 1534 1535 #ifdef RTW_DEBUG 1536 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1537 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10, 1538 (rate * 5) % 10, htsfth, htsftl)); 1539 #endif /* RTW_DEBUG */ 1540 1541 /* if bad flags, skip descriptor */ 1542 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) { 1543 aprint_error_dev(sc->sc_dev, "too many rx segments, " 1544 "next=%d, %08" PRIx32 "\n", next, hstat); 1545 goto next; 1546 } 1547 1548 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0, 1549 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1550 1551 m = rs->rs_mbuf; 1552 1553 /* if temporarily out of memory, re-use mbuf */ 1554 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) { 1555 case 0: 1556 break; 1557 case ENOBUFS: 1558 aprint_error_dev(sc->sc_dev, 1559 "rtw_rxsoft_alloc(, %d) failed, dropping packet\n", 1560 next); 1561 goto next; 1562 default: 1563 /* XXX shorten rx ring, instead? */ 1564 aprint_error_dev(sc->sc_dev, 1565 "could not load DMA map\n"); 1566 } 1567 1568 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ); 1569 1570 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1571 rssi = UINT8_MAX - sq; 1572 else { 1573 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); 1574 /* TBD find out each front-end's LNA gain in the 1575 * front-end's units 1576 */ 1577 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) 1578 rssi |= 0x80; 1579 } 1580 1581 /* Note well: now we cannot recycle the rs_mbuf unless 1582 * we restore its original length. 1583 */ 1584 m->m_pkthdr.rcvif = ifp; 1585 m->m_pkthdr.len = m->m_len = len; 1586 1587 wh = mtod(m, struct ieee80211_frame_min *); 1588 1589 if (!IS_BEACON(wh->i_fc[0])) 1590 sc->sc_led_state.ls_event |= RTW_LED_S_RX; 1591 1592 sc->sc_tsfth = htsfth; 1593 1594 #ifdef RTW_DEBUG 1595 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 1596 (IFF_DEBUG|IFF_LINK2)) { 1597 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len, 1598 rate, rssi); 1599 } 1600 #endif /* RTW_DEBUG */ 1601 1602 #if NBPFILTER > 0 1603 if (sc->sc_radiobpf != NULL) { 1604 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 1605 1606 rr->rr_tsft = 1607 htole64(((uint64_t)htsfth << 32) | htsftl); 1608 1609 rr->rr_flags = IEEE80211_RADIOTAP_F_FCS; 1610 1611 if ((hstat & RTW_RXSTAT_SPLCP) != 0) 1612 rr->rr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1613 if ((hstat & RTW_RXSTAT_CRC32) != 0) 1614 rr->rr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 1615 1616 rr->rr_rate = rate; 1617 1618 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 1619 rr->rr_u.u_philips.p_antsignal = rssi; 1620 else { 1621 rr->rr_u.u_other.o_antsignal = rssi; 1622 rr->rr_u.u_other.o_barker_lock = 1623 htole16(UINT8_MAX - sq); 1624 } 1625 1626 bpf_mtap2(sc->sc_radiobpf, rr, 1627 sizeof(sc->sc_rxtapu), m); 1628 } 1629 #endif /* NBPFILTER > 0 */ 1630 1631 if ((hstat & RTW_RXSTAT_RES) != 0) { 1632 m_freem(m); 1633 goto next; 1634 } 1635 1636 /* CRC is included with the packet; trim it off. */ 1637 m_adj(m, -IEEE80211_CRC_LEN); 1638 1639 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */ 1640 ni = ieee80211_find_rxnode(&sc->sc_ic, wh); 1641 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl); 1642 ieee80211_free_node(ni); 1643 next: 1644 rtw_rxdesc_init(rdb, rs, next, 0); 1645 } 1646 #undef IS_BEACON 1647 } 1648 1649 static void 1650 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1651 struct rtw_txsoft *ts) 1652 { 1653 struct mbuf *m; 1654 struct ieee80211_node *ni; 1655 1656 m = ts->ts_mbuf; 1657 ni = ts->ts_ni; 1658 KASSERT(m != NULL); 1659 KASSERT(ni != NULL); 1660 ts->ts_mbuf = NULL; 1661 ts->ts_ni = NULL; 1662 1663 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize, 1664 BUS_DMASYNC_POSTWRITE); 1665 bus_dmamap_unload(dmat, ts->ts_dmamap); 1666 m_freem(m); 1667 ieee80211_free_node(ni); 1668 } 1669 1670 static void 1671 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic, 1672 struct rtw_txsoft_blk *tsb) 1673 { 1674 struct rtw_txsoft *ts; 1675 1676 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1677 rtw_txsoft_release(dmat, ic, ts); 1678 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1679 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1680 } 1681 tsb->tsb_tx_timer = 0; 1682 } 1683 1684 static inline void 1685 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, 1686 struct rtw_txsoft *ts, int ndesc) 1687 { 1688 uint32_t hstat; 1689 int data_retry, rts_retry; 1690 struct rtw_txdesc *tdn; 1691 const char *condstring; 1692 struct ifnet *ifp = &sc->sc_if; 1693 1694 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts); 1695 1696 tdb->tdb_nfree += ndesc; 1697 1698 tdn = &tdb->tdb_desc[ts->ts_last]; 1699 1700 hstat = le32toh(tdn->td_stat); 1701 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); 1702 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); 1703 1704 ifp->if_collisions += rts_retry + data_retry; 1705 1706 if ((hstat & RTW_TXSTAT_TOK) != 0) 1707 condstring = "ok"; 1708 else { 1709 ifp->if_oerrors++; 1710 condstring = "error"; 1711 } 1712 1713 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 1714 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n", 1715 device_xname(sc->sc_dev), ts, ts->ts_first, ts->ts_last, 1716 condstring, rts_retry, data_retry)); 1717 } 1718 1719 static void 1720 rtw_reset_oactive(struct rtw_softc *sc) 1721 { 1722 short oflags; 1723 int pri; 1724 struct rtw_txsoft_blk *tsb; 1725 struct rtw_txdesc_blk *tdb; 1726 oflags = sc->sc_if.if_flags; 1727 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1728 tsb = &sc->sc_txsoft_blk[pri]; 1729 tdb = &sc->sc_txdesc_blk[pri]; 1730 if (!SIMPLEQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0) 1731 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1732 } 1733 if (oflags != sc->sc_if.if_flags) { 1734 DPRINTF(sc, RTW_DEBUG_OACTIVE, 1735 ("%s: reset OACTIVE\n", __func__)); 1736 } 1737 } 1738 1739 /* Collect transmitted packets. */ 1740 static void 1741 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb, 1742 struct rtw_txdesc_blk *tdb, int force) 1743 { 1744 int ndesc; 1745 struct rtw_txsoft *ts; 1746 1747 #ifdef RTW_DEBUG 1748 rtw_dump_rings(sc); 1749 #endif 1750 1751 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) { 1752 /* If we're clearing a failed transmission, only clear 1753 up to the last packet the hardware has processed. */ 1754 if (ts->ts_first == rtw_txring_next(&sc->sc_regs, tdb)) 1755 break; 1756 1757 ndesc = 1 + ts->ts_last - ts->ts_first; 1758 if (ts->ts_last < ts->ts_first) 1759 ndesc += tdb->tdb_ndesc; 1760 1761 KASSERT(ndesc > 0); 1762 1763 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1764 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1765 1766 if (force) { 1767 int next; 1768 #ifdef RTW_DIAG 1769 printf("%s: clearing packet, stats", __func__); 1770 #endif 1771 for (next = ts->ts_first; ; 1772 next = RTW_NEXT_IDX(tdb, next)) { 1773 #ifdef RTW_DIAG 1774 printf(" %" PRIx32 "/%" PRIx32 "/%" PRIx32 "/%" PRIu32 "/%" PRIx32, le32toh(tdb->tdb_desc[next].td_stat), le32toh(tdb->tdb_desc[next].td_ctl1), le32toh(tdb->tdb_desc[next].td_buf), le32toh(tdb->tdb_desc[next].td_len), le32toh(tdb->tdb_desc[next].td_next)); 1775 #endif 1776 tdb->tdb_desc[next].td_stat &= 1777 ~htole32(RTW_TXSTAT_OWN); 1778 if (next == ts->ts_last) 1779 break; 1780 } 1781 rtw_txdescs_sync(tdb, ts->ts_first, ndesc, 1782 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1783 #ifdef RTW_DIAG 1784 next = RTW_NEXT_IDX(tdb, next); 1785 printf(" -> end %u stat %" PRIx32 ", was %u\n", next, 1786 le32toh(tdb->tdb_desc[next].td_stat), 1787 rtw_txring_next(&sc->sc_regs, tdb)); 1788 #endif 1789 } else if ((tdb->tdb_desc[ts->ts_last].td_stat & 1790 htole32(RTW_TXSTAT_OWN)) != 0) { 1791 rtw_txdescs_sync(tdb, ts->ts_last, 1, 1792 BUS_DMASYNC_PREREAD); 1793 break; 1794 } 1795 1796 rtw_collect_txpkt(sc, tdb, ts, ndesc); 1797 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q); 1798 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q); 1799 } 1800 1801 /* no more pending transmissions, cancel watchdog */ 1802 if (ts == NULL) 1803 tsb->tsb_tx_timer = 0; 1804 rtw_reset_oactive(sc); 1805 } 1806 1807 static void 1808 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr) 1809 { 1810 int pri; 1811 struct rtw_txsoft_blk *tsb; 1812 struct rtw_txdesc_blk *tdb; 1813 struct ifnet *ifp = &sc->sc_if; 1814 1815 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1816 tsb = &sc->sc_txsoft_blk[pri]; 1817 tdb = &sc->sc_txdesc_blk[pri]; 1818 rtw_collect_txring(sc, tsb, tdb, 0); 1819 } 1820 1821 if ((isr & RTW_INTR_TX) != 0) 1822 rtw_start(ifp); 1823 1824 return; 1825 } 1826 1827 static void 1828 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr) 1829 { 1830 u_int next; 1831 uint32_t tsfth, tsftl; 1832 struct ieee80211com *ic; 1833 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN]; 1834 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN]; 1835 struct mbuf *m; 1836 1837 tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH); 1838 tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 1839 1840 if ((isr & (RTW_INTR_TBDOK|RTW_INTR_TBDER)) != 0) { 1841 next = rtw_txring_next(&sc->sc_regs, tdb); 1842 RTW_DPRINTF(RTW_DEBUG_BEACON, 1843 ("%s: beacon ring %sprocessed, isr = %#04" PRIx16 1844 ", next %u expected %u, %" PRIu64 "\n", __func__, 1845 (next == tdb->tdb_next) ? "" : "un", isr, next, 1846 tdb->tdb_next, (uint64_t)tsfth << 32 | tsftl)); 1847 if ((RTW_READ8(&sc->sc_regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0) 1848 rtw_collect_txring(sc, tsb, tdb, 1); 1849 } 1850 /* Start beacon transmission. */ 1851 1852 if ((isr & RTW_INTR_BCNINT) != 0 && 1853 sc->sc_ic.ic_state == IEEE80211_S_RUN && 1854 SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) { 1855 RTW_DPRINTF(RTW_DEBUG_BEACON, 1856 ("%s: beacon prep. time, isr = %#04" PRIx16 1857 ", %16" PRIu64 "\n", __func__, isr, 1858 (uint64_t)tsfth << 32 | tsftl)); 1859 ic = &sc->sc_ic; 1860 m = rtw_beacon_alloc(sc, ic->ic_bss); 1861 1862 if (m == NULL) { 1863 aprint_error_dev(sc->sc_dev, 1864 "could not allocate beacon\n"); 1865 return; 1866 } 1867 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss); 1868 IF_ENQUEUE(&sc->sc_beaconq, m); 1869 rtw_start(&sc->sc_if); 1870 } 1871 } 1872 1873 static void 1874 rtw_intr_atim(struct rtw_softc *sc) 1875 { 1876 /* TBD */ 1877 return; 1878 } 1879 1880 #ifdef RTW_DEBUG 1881 static void 1882 rtw_dump_rings(struct rtw_softc *sc) 1883 { 1884 struct rtw_txdesc_blk *tdb; 1885 struct rtw_rxdesc *rd; 1886 struct rtw_rxdesc_blk *rdb; 1887 int desc, pri; 1888 1889 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0) 1890 return; 1891 1892 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1893 tdb = &sc->sc_txdesc_blk[pri]; 1894 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri, 1895 tdb->tdb_ndesc, tdb->tdb_nfree); 1896 for (desc = 0; desc < tdb->tdb_ndesc; desc++) 1897 rtw_print_txdesc(sc, ".", NULL, tdb, desc); 1898 } 1899 1900 rdb = &sc->sc_rxdesc_blk; 1901 1902 for (desc = 0; desc < RTW_RXQLEN; desc++) { 1903 rd = &rdb->rdb_desc[desc]; 1904 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x " 1905 "rsvd1/tsfth %08x\n", __func__, 1906 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "", 1907 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi), 1908 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth)); 1909 } 1910 } 1911 #endif /* RTW_DEBUG */ 1912 1913 static void 1914 rtw_hwring_setup(struct rtw_softc *sc) 1915 { 1916 int pri; 1917 struct rtw_regs *regs = &sc->sc_regs; 1918 struct rtw_txdesc_blk *tdb; 1919 1920 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_basereg = RTW_TLPDA; 1921 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_base = RTW_RING_BASE(sc, hd_txlo); 1922 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_basereg = RTW_TNPDA; 1923 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_base = RTW_RING_BASE(sc, hd_txmd); 1924 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_basereg = RTW_THPDA; 1925 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_base = RTW_RING_BASE(sc, hd_txhi); 1926 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_basereg = RTW_TBDA; 1927 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_base = RTW_RING_BASE(sc, hd_bcn); 1928 1929 for (pri = 0; pri < RTW_NTXPRI; pri++) { 1930 tdb = &sc->sc_txdesc_blk[pri]; 1931 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base); 1932 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC, 1933 ("%s: reg[tdb->tdb_basereg] <- %" PRIxPTR "\n", __func__, 1934 (uintptr_t)tdb->tdb_base)); 1935 } 1936 1937 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx)); 1938 1939 RTW_DPRINTF(RTW_DEBUG_RECV_DESC, 1940 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__, 1941 (uintptr_t)RTW_RING_BASE(sc, hd_rx))); 1942 1943 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR); 1944 1945 } 1946 1947 static int 1948 rtw_swring_setup(struct rtw_softc *sc) 1949 { 1950 int rc; 1951 struct rtw_rxdesc_blk *rdb; 1952 1953 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]); 1954 1955 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]); 1956 1957 rdb = &sc->sc_rxdesc_blk; 1958 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc, 1959 sc->sc_dev)) != 0 && rdb->rdb_ndesc == 0) { 1960 aprint_error_dev(sc->sc_dev, "could not allocate rx buffers\n"); 1961 return rc; 1962 } 1963 1964 rdb = &sc->sc_rxdesc_blk; 1965 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc, 1966 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1967 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1); 1968 rdb->rdb_next = 0; 1969 1970 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]); 1971 return 0; 1972 } 1973 1974 static void 1975 rtw_txdesc_blk_init(struct rtw_txdesc_blk *tdb) 1976 { 1977 int i; 1978 1979 (void)memset(tdb->tdb_desc, 0, 1980 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 1981 for (i = 0; i < tdb->tdb_ndesc; i++) 1982 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i)); 1983 } 1984 1985 static u_int 1986 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb) 1987 { 1988 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) / 1989 sizeof(struct rtw_txdesc); 1990 } 1991 1992 #ifdef RTW_DIAG 1993 static void 1994 rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln) 1995 { 1996 int pri; 1997 u_int next; 1998 struct rtw_txdesc_blk *tdb; 1999 struct rtw_regs *regs = &sc->sc_regs; 2000 2001 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2002 int i; 2003 tdb = &sc->sc_txdesc_blk[pri]; 2004 next = rtw_txring_next(regs, tdb); 2005 if (tdb->tdb_next == next) 2006 continue; 2007 for (i = 0; next != tdb->tdb_next; 2008 next = RTW_NEXT_IDX(tdb, next), i++) { 2009 if ((tdb->tdb_desc[next].td_stat & htole32(RTW_TXSTAT_OWN)) == 0) 2010 break; 2011 } 2012 printf("%s:%d: tx-ring %d expected next %u, read %u+%d -> %s\n", fn, 2013 ln, pri, tdb->tdb_next, next, i, tdb->tdb_next == next ? "okay" : "BAD"); 2014 if (tdb->tdb_next == next) 2015 continue; 2016 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1); 2017 } 2018 } 2019 #endif 2020 2021 static void 2022 rtw_txdescs_reset(struct rtw_softc *sc) 2023 { 2024 int pri; 2025 struct rtw_txsoft_blk *tsb; 2026 struct rtw_txdesc_blk *tdb; 2027 2028 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2029 tsb = &sc->sc_txsoft_blk[pri]; 2030 tdb = &sc->sc_txdesc_blk[pri]; 2031 rtw_collect_txring(sc, tsb, tdb, 1); 2032 #ifdef RTW_DIAG 2033 if (!SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 2034 printf("%s: packets left in ring %d\n", __func__, pri); 2035 #endif 2036 } 2037 } 2038 2039 static void 2040 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr) 2041 { 2042 aprint_error_dev(sc->sc_dev, "tx fifo underflow\n"); 2043 2044 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: cleaning up xmit, isr %" PRIx16 2045 "\n", device_xname(sc->sc_dev), isr)); 2046 2047 #ifdef RTW_DEBUG 2048 rtw_dump_rings(sc); 2049 #endif /* RTW_DEBUG */ 2050 2051 /* Collect tx'd packets. XXX let's hope this stops the transmit 2052 * timeouts. 2053 */ 2054 rtw_txdescs_reset(sc); 2055 2056 #ifdef RTW_DEBUG 2057 rtw_dump_rings(sc); 2058 #endif /* RTW_DEBUG */ 2059 } 2060 2061 static inline void 2062 rtw_suspend_ticks(struct rtw_softc *sc) 2063 { 2064 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2065 ("%s: suspending ticks\n", device_xname(sc->sc_dev))); 2066 sc->sc_do_tick = 0; 2067 } 2068 2069 static inline void 2070 rtw_resume_ticks(struct rtw_softc *sc) 2071 { 2072 uint32_t tsftrl0, tsftrl1, next_tick; 2073 2074 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2075 2076 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL); 2077 next_tick = tsftrl1 + 1000000; 2078 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick); 2079 2080 sc->sc_do_tick = 1; 2081 2082 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, 2083 ("%s: resume ticks delta %#08x now %#08x next %#08x\n", 2084 device_xname(sc->sc_dev), tsftrl1 - tsftrl0, tsftrl1, next_tick)); 2085 } 2086 2087 static void 2088 rtw_intr_timeout(struct rtw_softc *sc) 2089 { 2090 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", device_xname(sc->sc_dev))); 2091 if (sc->sc_do_tick) 2092 rtw_resume_ticks(sc); 2093 return; 2094 } 2095 2096 int 2097 rtw_intr(void *arg) 2098 { 2099 int i; 2100 struct rtw_softc *sc = arg; 2101 struct rtw_regs *regs = &sc->sc_regs; 2102 uint16_t isr; 2103 struct ifnet *ifp = &sc->sc_if; 2104 2105 /* 2106 * If the interface isn't running, the interrupt couldn't 2107 * possibly have come from us. 2108 */ 2109 if ((sc->sc_flags & RTW_F_ENABLED) == 0 || 2110 (ifp->if_flags & IFF_RUNNING) == 0 || 2111 !device_is_active(sc->sc_dev)) { 2112 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n", 2113 device_xname(sc->sc_dev))); 2114 return (0); 2115 } 2116 2117 for (i = 0; i < 10; i++) { 2118 isr = RTW_READ16(regs, RTW_ISR); 2119 2120 RTW_WRITE16(regs, RTW_ISR, isr); 2121 RTW_WBR(regs, RTW_ISR, RTW_ISR); 2122 2123 if (sc->sc_intr_ack != NULL) 2124 (*sc->sc_intr_ack)(regs); 2125 2126 if (isr == 0) 2127 break; 2128 2129 #ifdef RTW_DEBUG 2130 #define PRINTINTR(flag) do { \ 2131 if ((isr & flag) != 0) { \ 2132 printf("%s" #flag, delim); \ 2133 delim = ","; \ 2134 } \ 2135 } while (0) 2136 2137 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) { 2138 const char *delim = "<"; 2139 2140 printf("%s: reg[ISR] = %x", device_xname(sc->sc_dev), 2141 isr); 2142 2143 PRINTINTR(RTW_INTR_TXFOVW); 2144 PRINTINTR(RTW_INTR_TIMEOUT); 2145 PRINTINTR(RTW_INTR_BCNINT); 2146 PRINTINTR(RTW_INTR_ATIMINT); 2147 PRINTINTR(RTW_INTR_TBDER); 2148 PRINTINTR(RTW_INTR_TBDOK); 2149 PRINTINTR(RTW_INTR_THPDER); 2150 PRINTINTR(RTW_INTR_THPDOK); 2151 PRINTINTR(RTW_INTR_TNPDER); 2152 PRINTINTR(RTW_INTR_TNPDOK); 2153 PRINTINTR(RTW_INTR_RXFOVW); 2154 PRINTINTR(RTW_INTR_RDU); 2155 PRINTINTR(RTW_INTR_TLPDER); 2156 PRINTINTR(RTW_INTR_TLPDOK); 2157 PRINTINTR(RTW_INTR_RER); 2158 PRINTINTR(RTW_INTR_ROK); 2159 2160 printf(">\n"); 2161 } 2162 #undef PRINTINTR 2163 #endif /* RTW_DEBUG */ 2164 2165 if ((isr & RTW_INTR_RX) != 0) 2166 rtw_intr_rx(sc, isr); 2167 if ((isr & RTW_INTR_TX) != 0) 2168 rtw_intr_tx(sc, isr); 2169 if ((isr & RTW_INTR_BEACON) != 0) 2170 rtw_intr_beacon(sc, isr); 2171 if ((isr & RTW_INTR_ATIMINT) != 0) 2172 rtw_intr_atim(sc); 2173 if ((isr & RTW_INTR_IOERROR) != 0) 2174 rtw_intr_ioerror(sc, isr); 2175 if ((isr & RTW_INTR_TIMEOUT) != 0) 2176 rtw_intr_timeout(sc); 2177 } 2178 2179 return 1; 2180 } 2181 2182 /* Must be called at splnet. */ 2183 static void 2184 rtw_stop(struct ifnet *ifp, int disable) 2185 { 2186 int pri; 2187 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2188 struct ieee80211com *ic = &sc->sc_ic; 2189 struct rtw_regs *regs = &sc->sc_regs; 2190 2191 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2192 return; 2193 2194 rtw_suspend_ticks(sc); 2195 2196 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2197 2198 if ((sc->sc_flags & RTW_F_INVALID) == 0) { 2199 /* Disable interrupts. */ 2200 RTW_WRITE16(regs, RTW_IMR, 0); 2201 2202 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR); 2203 2204 /* Stop the transmit and receive processes. First stop DMA, 2205 * then disable receiver and transmitter. 2206 */ 2207 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 2208 2209 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR); 2210 2211 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2212 } 2213 2214 for (pri = 0; pri < RTW_NTXPRI; pri++) { 2215 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic, 2216 &sc->sc_txsoft_blk[pri]); 2217 } 2218 2219 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]); 2220 2221 if (disable) 2222 rtw_disable(sc); 2223 2224 /* Mark the interface as not running. Cancel the watchdog timer. */ 2225 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2226 ifp->if_timer = 0; 2227 2228 return; 2229 } 2230 2231 const char * 2232 rtw_pwrstate_string(enum rtw_pwrstate power) 2233 { 2234 switch (power) { 2235 case RTW_ON: 2236 return "on"; 2237 case RTW_SLEEP: 2238 return "sleep"; 2239 case RTW_OFF: 2240 return "off"; 2241 default: 2242 return "unknown"; 2243 } 2244 } 2245 2246 /* XXX For Maxim, I am using the RFMD settings gleaned from the 2247 * reference driver, plus a magic Maxim "ON" value that comes from 2248 * the Realtek document "Windows PG for Rtl8180." 2249 */ 2250 static void 2251 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2252 int before_rf, int digphy) 2253 { 2254 uint32_t anaparm; 2255 2256 anaparm = RTW_READ(regs, RTW_ANAPARM); 2257 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2258 2259 switch (power) { 2260 case RTW_OFF: 2261 if (before_rf) 2262 return; 2263 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF; 2264 anaparm |= RTW_ANAPARM_TXDACOFF; 2265 break; 2266 case RTW_SLEEP: 2267 if (!before_rf) 2268 return; 2269 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP; 2270 anaparm |= RTW_ANAPARM_TXDACOFF; 2271 break; 2272 case RTW_ON: 2273 if (!before_rf) 2274 return; 2275 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON; 2276 break; 2277 } 2278 RTW_DPRINTF(RTW_DEBUG_PWR, 2279 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2280 __func__, rtw_pwrstate_string(power), 2281 (before_rf) ? "before" : "after", anaparm)); 2282 2283 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2284 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2285 } 2286 2287 /* XXX I am using the RFMD settings gleaned from the reference 2288 * driver. They agree 2289 */ 2290 static void 2291 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2292 int before_rf, int digphy) 2293 { 2294 uint32_t anaparm; 2295 2296 anaparm = RTW_READ(regs, RTW_ANAPARM); 2297 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2298 2299 switch (power) { 2300 case RTW_OFF: 2301 if (before_rf) 2302 return; 2303 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF; 2304 anaparm |= RTW_ANAPARM_TXDACOFF; 2305 break; 2306 case RTW_SLEEP: 2307 if (!before_rf) 2308 return; 2309 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP; 2310 anaparm |= RTW_ANAPARM_TXDACOFF; 2311 break; 2312 case RTW_ON: 2313 if (!before_rf) 2314 return; 2315 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON; 2316 break; 2317 } 2318 RTW_DPRINTF(RTW_DEBUG_PWR, 2319 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2320 __func__, rtw_pwrstate_string(power), 2321 (before_rf) ? "before" : "after", anaparm)); 2322 2323 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2324 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2325 } 2326 2327 static void 2328 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, 2329 int before_rf, int digphy) 2330 { 2331 uint32_t anaparm; 2332 2333 anaparm = RTW_READ(regs, RTW_ANAPARM); 2334 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF); 2335 2336 switch (power) { 2337 case RTW_OFF: 2338 if (before_rf) 2339 return; 2340 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF; 2341 anaparm |= RTW_ANAPARM_TXDACOFF; 2342 break; 2343 case RTW_SLEEP: 2344 if (!before_rf) 2345 return; 2346 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP; 2347 anaparm |= RTW_ANAPARM_TXDACOFF; 2348 break; 2349 case RTW_ON: 2350 if (!before_rf) 2351 return; 2352 if (digphy) { 2353 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON; 2354 /* XXX guess */ 2355 anaparm |= RTW_ANAPARM_TXDACOFF; 2356 } else 2357 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON; 2358 break; 2359 } 2360 RTW_DPRINTF(RTW_DEBUG_PWR, 2361 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n", 2362 __func__, rtw_pwrstate_string(power), 2363 (before_rf) ? "before" : "after", anaparm)); 2364 2365 RTW_WRITE(regs, RTW_ANAPARM, anaparm); 2366 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM); 2367 } 2368 2369 static void 2370 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf, 2371 int digphy) 2372 { 2373 struct rtw_regs *regs = &sc->sc_regs; 2374 2375 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2376 2377 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy); 2378 2379 rtw_set_access(regs, RTW_ACCESS_NONE); 2380 2381 return; 2382 } 2383 2384 static int 2385 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power) 2386 { 2387 int rc; 2388 2389 RTW_DPRINTF(RTW_DEBUG_PWR, 2390 ("%s: %s->%s\n", __func__, 2391 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power))); 2392 2393 if (sc->sc_pwrstate == power) 2394 return 0; 2395 2396 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY); 2397 rc = rtw_rf_pwrstate(sc->sc_rf, power); 2398 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY); 2399 2400 switch (power) { 2401 case RTW_ON: 2402 /* TBD set LEDs */ 2403 break; 2404 case RTW_SLEEP: 2405 /* TBD */ 2406 break; 2407 case RTW_OFF: 2408 /* TBD */ 2409 break; 2410 } 2411 if (rc == 0) 2412 sc->sc_pwrstate = power; 2413 else 2414 sc->sc_pwrstate = RTW_OFF; 2415 return rc; 2416 } 2417 2418 static int 2419 rtw_tune(struct rtw_softc *sc) 2420 { 2421 struct ieee80211com *ic = &sc->sc_ic; 2422 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 2423 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap; 2424 u_int chan; 2425 int rc; 2426 int antdiv = sc->sc_flags & RTW_F_ANTDIV, 2427 dflantb = sc->sc_flags & RTW_F_DFLANTB; 2428 2429 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2430 KASSERT(chan != IEEE80211_CHAN_ANY); 2431 2432 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2433 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2434 2435 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2436 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2437 2438 if (chan == sc->sc_cur_chan) { 2439 RTW_DPRINTF(RTW_DEBUG_TUNE, 2440 ("%s: already tuned chan #%d\n", __func__, chan)); 2441 return 0; 2442 } 2443 2444 rtw_suspend_ticks(sc); 2445 2446 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0); 2447 2448 /* TBD wait for Tx to complete */ 2449 2450 KASSERT((sc->sc_flags & RTW_F_ENABLED) != 0); 2451 2452 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf, 2453 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr, 2454 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) { 2455 /* XXX condition on powersaving */ 2456 aprint_error_dev(sc->sc_dev, "phy init failed\n"); 2457 } 2458 2459 sc->sc_cur_chan = chan; 2460 2461 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2462 2463 rtw_resume_ticks(sc); 2464 2465 return rc; 2466 } 2467 2468 void 2469 rtw_disable(struct rtw_softc *sc) 2470 { 2471 int rc; 2472 2473 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 2474 return; 2475 2476 /* turn off PHY */ 2477 if ((sc->sc_flags & RTW_F_INVALID) == 0 && 2478 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0) { 2479 aprint_error_dev(sc->sc_dev, 2480 "failed to turn off PHY (%d)\n", rc); 2481 } 2482 2483 if (sc->sc_disable != NULL) 2484 (*sc->sc_disable)(sc); 2485 2486 sc->sc_flags &= ~RTW_F_ENABLED; 2487 } 2488 2489 int 2490 rtw_enable(struct rtw_softc *sc) 2491 { 2492 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 2493 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2494 aprint_error_dev(sc->sc_dev, 2495 "device enable failed\n"); 2496 return (EIO); 2497 } 2498 sc->sc_flags |= RTW_F_ENABLED; 2499 /* Power may have been removed, and WEP keys thus 2500 * reset. 2501 */ 2502 sc->sc_flags &= ~RTW_F_DK_VALID; 2503 } 2504 return (0); 2505 } 2506 2507 static void 2508 rtw_transmit_config(struct rtw_regs *regs) 2509 { 2510 uint32_t tcr; 2511 2512 tcr = RTW_READ(regs, RTW_TCR); 2513 2514 tcr |= RTW_TCR_CWMIN; 2515 tcr &= ~RTW_TCR_MXDMA_MASK; 2516 tcr |= RTW_TCR_MXDMA_256; 2517 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */ 2518 tcr &= ~RTW_TCR_LBK_MASK; 2519 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */ 2520 2521 /* set short/long retry limits */ 2522 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); 2523 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK); 2524 2525 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ 2526 2527 RTW_WRITE(regs, RTW_TCR, tcr); 2528 RTW_SYNC(regs, RTW_TCR, RTW_TCR); 2529 } 2530 2531 static inline void 2532 rtw_enable_interrupts(struct rtw_softc *sc) 2533 { 2534 struct rtw_regs *regs = &sc->sc_regs; 2535 2536 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT; 2537 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT; 2538 2539 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten); 2540 RTW_WBW(regs, RTW_IMR, RTW_ISR); 2541 RTW_WRITE16(regs, RTW_ISR, 0xffff); 2542 RTW_SYNC(regs, RTW_IMR, RTW_ISR); 2543 2544 /* XXX necessary? */ 2545 if (sc->sc_intr_ack != NULL) 2546 (*sc->sc_intr_ack)(regs); 2547 } 2548 2549 static void 2550 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode) 2551 { 2552 uint8_t msr; 2553 2554 /* I'm guessing that MSR is protected as CONFIG[0123] are. */ 2555 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG); 2556 2557 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; 2558 2559 switch (opmode) { 2560 case IEEE80211_M_AHDEMO: 2561 case IEEE80211_M_IBSS: 2562 msr |= RTW_MSR_NETYPE_ADHOC_OK; 2563 break; 2564 case IEEE80211_M_HOSTAP: 2565 msr |= RTW_MSR_NETYPE_AP_OK; 2566 break; 2567 case IEEE80211_M_MONITOR: 2568 /* XXX */ 2569 msr |= RTW_MSR_NETYPE_NOLINK; 2570 break; 2571 case IEEE80211_M_STA: 2572 msr |= RTW_MSR_NETYPE_INFRA_OK; 2573 break; 2574 } 2575 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr); 2576 2577 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE); 2578 } 2579 2580 #define rtw_calchash(addr) \ 2581 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26) 2582 2583 static void 2584 rtw_pktfilt_load(struct rtw_softc *sc) 2585 { 2586 struct rtw_regs *regs = &sc->sc_regs; 2587 struct ieee80211com *ic = &sc->sc_ic; 2588 struct ethercom *ec = &sc->sc_ec; 2589 struct ifnet *ifp = &sc->sc_if; 2590 int hash; 2591 uint32_t hashes[2] = { 0, 0 }; 2592 struct ether_multi *enm; 2593 struct ether_multistep step; 2594 2595 /* XXX might be necessary to stop Rx/Tx engines while setting filters */ 2596 2597 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK; 2598 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK); 2599 2600 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT; 2601 /* MAC auto-reset PHY (huh?) */ 2602 sc->sc_rcr |= RTW_RCR_ENMARP; 2603 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */ 2604 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE; 2605 2606 switch (ic->ic_opmode) { 2607 case IEEE80211_M_MONITOR: 2608 sc->sc_rcr |= RTW_RCR_MONITOR; 2609 break; 2610 case IEEE80211_M_AHDEMO: 2611 case IEEE80211_M_IBSS: 2612 /* receive broadcasts in our BSS */ 2613 sc->sc_rcr |= RTW_RCR_ADD3; 2614 break; 2615 default: 2616 break; 2617 } 2618 2619 ifp->if_flags &= ~IFF_ALLMULTI; 2620 2621 /* 2622 * Program the 64-bit multicast hash filter. 2623 */ 2624 ETHER_FIRST_MULTI(step, ec, enm); 2625 while (enm != NULL) { 2626 /* XXX */ 2627 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2628 ETHER_ADDR_LEN) != 0) { 2629 ifp->if_flags |= IFF_ALLMULTI; 2630 break; 2631 } 2632 2633 hash = rtw_calchash(enm->enm_addrlo); 2634 hashes[hash >> 5] |= (1 << (hash & 0x1f)); 2635 ETHER_NEXT_MULTI(step, enm); 2636 } 2637 2638 /* XXX accept all broadcast if scanning */ 2639 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2640 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2641 2642 if (ifp->if_flags & IFF_PROMISC) { 2643 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */ 2644 sc->sc_rcr |= RTW_RCR_ACRC32; /* accept frames failing CRC */ 2645 sc->sc_rcr |= RTW_RCR_AICV; /* accept frames failing ICV */ 2646 ifp->if_flags |= IFF_ALLMULTI; 2647 } 2648 2649 if (ifp->if_flags & IFF_ALLMULTI) 2650 hashes[0] = hashes[1] = 0xffffffff; 2651 2652 if ((hashes[0] | hashes[1]) != 0) 2653 sc->sc_rcr |= RTW_RCR_AM; /* accept multicast */ 2654 2655 RTW_WRITE(regs, RTW_MAR0, hashes[0]); 2656 RTW_WRITE(regs, RTW_MAR1, hashes[1]); 2657 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr); 2658 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */ 2659 2660 DPRINTF(sc, RTW_DEBUG_PKTFILT, 2661 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n", 2662 device_xname(sc->sc_dev), RTW_READ(regs, RTW_MAR0), 2663 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR))); 2664 } 2665 2666 static struct mbuf * 2667 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni) 2668 { 2669 struct ieee80211com *ic = &sc->sc_ic; 2670 struct mbuf *m; 2671 struct ieee80211_beacon_offsets boff; 2672 2673 if ((m = ieee80211_beacon_alloc(ic, ni, &boff)) != NULL) { 2674 RTW_DPRINTF(RTW_DEBUG_BEACON, 2675 ("%s: m %p len %u\n", __func__, m, m->m_len)); 2676 } 2677 return m; 2678 } 2679 2680 /* Must be called at splnet. */ 2681 static int 2682 rtw_init(struct ifnet *ifp) 2683 { 2684 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 2685 struct ieee80211com *ic = &sc->sc_ic; 2686 struct rtw_regs *regs = &sc->sc_regs; 2687 int rc = 0; 2688 2689 if ((rc = rtw_enable(sc)) != 0) 2690 goto out; 2691 2692 /* Cancel pending I/O and reset. */ 2693 rtw_stop(ifp, 0); 2694 2695 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n", 2696 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 2697 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 2698 2699 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) 2700 goto out; 2701 2702 if ((rc = rtw_swring_setup(sc)) != 0) 2703 goto out; 2704 2705 rtw_transmit_config(regs); 2706 2707 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2708 2709 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */ 2710 RTW_WBW(regs, RTW_MSR, RTW_BRSR); 2711 2712 /* long PLCP header, 1Mb/2Mb basic rate */ 2713 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS); 2714 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR); 2715 2716 rtw_set_access(regs, RTW_ACCESS_ANAPARM); 2717 rtw_set_access(regs, RTW_ACCESS_NONE); 2718 2719 /* XXX from reference sources */ 2720 RTW_WRITE(regs, RTW_FEMR, 0xffff); 2721 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR); 2722 2723 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev); 2724 2725 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay); 2726 /* from Linux driver */ 2727 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC); 2728 2729 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT); 2730 2731 rtw_enable_interrupts(sc); 2732 2733 rtw_pktfilt_load(sc); 2734 2735 rtw_hwring_setup(sc); 2736 2737 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey); 2738 2739 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 2740 2741 ifp->if_flags |= IFF_RUNNING; 2742 ic->ic_state = IEEE80211_S_INIT; 2743 2744 RTW_WRITE16(regs, RTW_BSSID16, 0x0); 2745 RTW_WRITE(regs, RTW_BSSID32, 0x0); 2746 2747 rtw_resume_ticks(sc); 2748 2749 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 2750 2751 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2752 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2753 else 2754 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2755 2756 out: 2757 aprint_error_dev(sc->sc_dev, "interface not running\n"); 2758 return rc; 2759 } 2760 2761 static inline void 2762 rtw_led_init(struct rtw_regs *regs) 2763 { 2764 uint8_t cfg0, cfg1; 2765 2766 rtw_set_access(regs, RTW_ACCESS_CONFIG); 2767 2768 cfg0 = RTW_READ8(regs, RTW_CONFIG0); 2769 cfg0 |= RTW_CONFIG0_LEDGPOEN; 2770 RTW_WRITE8(regs, RTW_CONFIG0, cfg0); 2771 2772 cfg1 = RTW_READ8(regs, RTW_CONFIG1); 2773 RTW_DPRINTF(RTW_DEBUG_LED, 2774 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1)); 2775 2776 cfg1 &= ~RTW_CONFIG1_LEDS_MASK; 2777 cfg1 |= RTW_CONFIG1_LEDS_TX_RX; 2778 RTW_WRITE8(regs, RTW_CONFIG1, cfg1); 2779 2780 rtw_set_access(regs, RTW_ACCESS_NONE); 2781 } 2782 2783 /* 2784 * IEEE80211_S_INIT: LED1 off 2785 * 2786 * IEEE80211_S_AUTH, 2787 * IEEE80211_S_ASSOC, 2788 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx 2789 * 2790 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx 2791 */ 2792 static void 2793 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate) 2794 { 2795 struct rtw_led_state *ls; 2796 2797 ls = &sc->sc_led_state; 2798 2799 switch (nstate) { 2800 case IEEE80211_S_INIT: 2801 rtw_led_init(&sc->sc_regs); 2802 callout_stop(&ls->ls_slow_ch); 2803 callout_stop(&ls->ls_fast_ch); 2804 ls->ls_slowblink = 0; 2805 ls->ls_actblink = 0; 2806 ls->ls_default = 0; 2807 break; 2808 case IEEE80211_S_SCAN: 2809 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2810 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2811 /*FALLTHROUGH*/ 2812 case IEEE80211_S_AUTH: 2813 case IEEE80211_S_ASSOC: 2814 ls->ls_default = RTW_LED1; 2815 ls->ls_actblink = RTW_LED1; 2816 ls->ls_slowblink = RTW_LED1; 2817 break; 2818 case IEEE80211_S_RUN: 2819 ls->ls_slowblink = 0; 2820 break; 2821 } 2822 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2823 } 2824 2825 static void 2826 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid) 2827 { 2828 uint8_t led_condition; 2829 bus_size_t ofs; 2830 uint8_t mask, newval, val; 2831 2832 led_condition = ls->ls_default; 2833 2834 if (ls->ls_state & RTW_LED_S_SLOW) 2835 led_condition ^= ls->ls_slowblink; 2836 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX)) 2837 led_condition ^= ls->ls_actblink; 2838 2839 RTW_DPRINTF(RTW_DEBUG_LED, 2840 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition)); 2841 2842 switch (hwverid) { 2843 default: 2844 case 'F': 2845 ofs = RTW_PSR; 2846 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1; 2847 if (led_condition & RTW_LED0) 2848 newval &= ~RTW_PSR_LEDGPO0; 2849 if (led_condition & RTW_LED1) 2850 newval &= ~RTW_PSR_LEDGPO1; 2851 break; 2852 case 'D': 2853 ofs = RTW_9346CR; 2854 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS; 2855 newval = RTW_9346CR_EEM_PROGRAM; 2856 if (led_condition & RTW_LED0) 2857 newval |= RTW_9346CR_EEDI; 2858 if (led_condition & RTW_LED1) 2859 newval |= RTW_9346CR_EECS; 2860 break; 2861 } 2862 val = RTW_READ8(regs, ofs); 2863 RTW_DPRINTF(RTW_DEBUG_LED, 2864 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val, 2865 (uintptr_t)ofs)); 2866 val &= ~mask; 2867 val |= newval; 2868 RTW_WRITE8(regs, ofs, val); 2869 RTW_DPRINTF(RTW_DEBUG_LED, 2870 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val, 2871 (uintptr_t)ofs)); 2872 RTW_SYNC(regs, ofs, ofs); 2873 } 2874 2875 static void 2876 rtw_led_fastblink(void *arg) 2877 { 2878 int ostate, s; 2879 struct rtw_softc *sc = (struct rtw_softc *)arg; 2880 struct rtw_led_state *ls = &sc->sc_led_state; 2881 2882 s = splnet(); 2883 ostate = ls->ls_state; 2884 ls->ls_state ^= ls->ls_event; 2885 2886 if ((ls->ls_event & RTW_LED_S_TX) == 0) 2887 ls->ls_state &= ~RTW_LED_S_TX; 2888 2889 if ((ls->ls_event & RTW_LED_S_RX) == 0) 2890 ls->ls_state &= ~RTW_LED_S_RX; 2891 2892 ls->ls_event = 0; 2893 2894 if (ostate != ls->ls_state) 2895 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2896 splx(s); 2897 2898 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS); 2899 } 2900 2901 static void 2902 rtw_led_slowblink(void *arg) 2903 { 2904 int s; 2905 struct rtw_softc *sc = (struct rtw_softc *)arg; 2906 struct rtw_led_state *ls = &sc->sc_led_state; 2907 2908 s = splnet(); 2909 ls->ls_state ^= RTW_LED_S_SLOW; 2910 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid); 2911 splx(s); 2912 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS); 2913 } 2914 2915 static inline void 2916 rtw_led_attach(struct rtw_led_state *ls, void *arg) 2917 { 2918 callout_init(&ls->ls_fast_ch, 0); 2919 callout_init(&ls->ls_slow_ch, 0); 2920 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg); 2921 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg); 2922 } 2923 2924 static int 2925 rtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2926 { 2927 int rc = 0, s; 2928 struct rtw_softc *sc = ifp->if_softc; 2929 2930 s = splnet(); 2931 if (cmd == SIOCSIFFLAGS) { 2932 if ((ifp->if_flags & IFF_UP) != 0) { 2933 if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2934 rtw_pktfilt_load(sc); 2935 else 2936 rc = rtw_init(ifp); 2937 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2938 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) { 2939 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__); 2940 rtw_stop(ifp, 1); 2941 } 2942 } else if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET) 2943 ; /* nothing to do */ 2944 else if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 2945 /* reload packet filter if running */ 2946 if (ifp->if_flags & IFF_RUNNING) 2947 rtw_pktfilt_load(sc); 2948 rc = 0; 2949 } else if ((sc->sc_flags & RTW_F_ENABLED) != 0) 2950 /* reinitialize h/w if activated */ 2951 rc = rtw_init(ifp); 2952 else 2953 rc = 0; 2954 splx(s); 2955 return rc; 2956 } 2957 2958 /* Select a transmit ring with at least one h/w and s/w descriptor free. 2959 * Return 0 on success, -1 on failure. 2960 */ 2961 static inline int 2962 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp, 2963 struct rtw_txdesc_blk **tdbp, int pri) 2964 { 2965 struct rtw_txsoft_blk *tsb; 2966 struct rtw_txdesc_blk *tdb; 2967 2968 KASSERT(pri >= 0 && pri < RTW_NTXPRI); 2969 2970 tsb = &sc->sc_txsoft_blk[pri]; 2971 tdb = &sc->sc_txdesc_blk[pri]; 2972 2973 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) { 2974 if (tsb->tsb_tx_timer == 0) 2975 tsb->tsb_tx_timer = 5; 2976 *tsbp = NULL; 2977 *tdbp = NULL; 2978 return -1; 2979 } 2980 *tsbp = tsb; 2981 *tdbp = tdb; 2982 return 0; 2983 } 2984 2985 static inline struct mbuf * 2986 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri, 2987 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp, 2988 struct ieee80211_node **nip, short *if_flagsp) 2989 { 2990 struct mbuf *m; 2991 2992 if (IF_IS_EMPTY(ifq)) 2993 return NULL; 2994 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 2995 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 2996 __func__, pri)); 2997 *if_flagsp |= IFF_OACTIVE; 2998 sc->sc_if.if_timer = 1; 2999 return NULL; 3000 } 3001 IF_DEQUEUE(ifq, m); 3002 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3003 m->m_pkthdr.rcvif = NULL; 3004 KASSERT(*nip != NULL); 3005 return m; 3006 } 3007 3008 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp 3009 * at the driver's selection of transmit control block for the packet. 3010 */ 3011 static inline int 3012 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp, 3013 struct rtw_txdesc_blk **tdbp, struct mbuf **mp, 3014 struct ieee80211_node **nip) 3015 { 3016 int pri; 3017 struct ether_header *eh; 3018 struct mbuf *m0; 3019 struct rtw_softc *sc; 3020 short *if_flagsp; 3021 3022 *mp = NULL; 3023 3024 sc = (struct rtw_softc *)ifp->if_softc; 3025 3026 DPRINTF(sc, RTW_DEBUG_XMIT, 3027 ("%s: enter %s\n", device_xname(sc->sc_dev), __func__)); 3028 3029 if_flagsp = &ifp->if_flags; 3030 3031 if (sc->sc_ic.ic_state == IEEE80211_S_RUN && 3032 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp, 3033 tdbp, nip, if_flagsp)) != NULL) { 3034 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n", 3035 __func__)); 3036 return 0; 3037 } 3038 3039 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp, 3040 tdbp, nip, if_flagsp)) != NULL) { 3041 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n", 3042 __func__)); 3043 return 0; 3044 } 3045 3046 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) { 3047 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__)); 3048 return 0; 3049 } 3050 3051 IFQ_POLL(&ifp->if_snd, m0); 3052 if (m0 == NULL) { 3053 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3054 __func__)); 3055 return 0; 3056 } 3057 3058 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD; 3059 3060 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) { 3061 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n", 3062 __func__, pri)); 3063 *if_flagsp |= IFF_OACTIVE; 3064 sc->sc_if.if_timer = 1; 3065 return 0; 3066 } 3067 3068 IFQ_DEQUEUE(&ifp->if_snd, m0); 3069 if (m0 == NULL) { 3070 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n", 3071 __func__)); 3072 return 0; 3073 } 3074 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__)); 3075 ifp->if_opackets++; 3076 #if NBPFILTER > 0 3077 if (ifp->if_bpf) 3078 bpf_mtap(ifp->if_bpf, m0); 3079 #endif 3080 eh = mtod(m0, struct ether_header *); 3081 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost); 3082 if (*nip == NULL) { 3083 /* NB: ieee80211_find_txnode does stat+msg */ 3084 m_freem(m0); 3085 return -1; 3086 } 3087 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) { 3088 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__)); 3089 ifp->if_oerrors++; 3090 return -1; 3091 } 3092 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3093 *mp = m0; 3094 return 0; 3095 } 3096 3097 static int 3098 rtw_seg_too_short(bus_dmamap_t dmamap) 3099 { 3100 int i; 3101 for (i = 0; i < dmamap->dm_nsegs; i++) { 3102 if (dmamap->dm_segs[i].ds_len < 4) 3103 return 1; 3104 } 3105 return 0; 3106 } 3107 3108 /* TBD factor with atw_start */ 3109 static struct mbuf * 3110 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain, 3111 u_int ndescfree, device_t dev) 3112 { 3113 int first, rc; 3114 struct mbuf *m, *m0; 3115 3116 m0 = chain; 3117 3118 /* 3119 * Load the DMA map. Copy and try (once) again if the packet 3120 * didn't fit in the alloted number of segments. 3121 */ 3122 for (first = 1; 3123 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0, 3124 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 3125 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first; 3126 first = 0) { 3127 if (rc == 0) { 3128 #ifdef RTW_DIAGxxx 3129 if (rtw_seg_too_short(dmam)) { 3130 printf("%s: short segment, mbuf lengths:", __func__); 3131 for (m = m0; m; m = m->m_next) 3132 printf(" %d", m->m_len); 3133 printf("\n"); 3134 } 3135 #endif 3136 bus_dmamap_unload(dmat, dmam); 3137 } 3138 MGETHDR(m, M_DONTWAIT, MT_DATA); 3139 if (m == NULL) { 3140 aprint_error_dev(dev, "unable to allocate Tx mbuf\n"); 3141 break; 3142 } 3143 if (m0->m_pkthdr.len > MHLEN) { 3144 MCLGET(m, M_DONTWAIT); 3145 if ((m->m_flags & M_EXT) == 0) { 3146 aprint_error_dev(dev, 3147 "cannot allocate Tx cluster\n"); 3148 m_freem(m); 3149 break; 3150 } 3151 } 3152 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3153 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3154 m_freem(m0); 3155 m0 = m; 3156 m = NULL; 3157 } 3158 if (rc != 0) { 3159 aprint_error_dev(dev, "cannot load Tx buffer, rc = %d\n", rc); 3160 m_freem(m0); 3161 return NULL; 3162 } else if (rtw_seg_too_short(dmam)) { 3163 aprint_error_dev(dev, 3164 "cannot load Tx buffer, segment too short\n"); 3165 bus_dmamap_unload(dmat, dmam); 3166 m_freem(m0); 3167 return NULL; 3168 } else if (dmam->dm_nsegs > ndescfree) { 3169 aprint_error_dev(dev, "too many tx segments\n"); 3170 bus_dmamap_unload(dmat, dmam); 3171 m_freem(m0); 3172 return NULL; 3173 } 3174 return m0; 3175 } 3176 3177 #ifdef RTW_DEBUG 3178 static void 3179 rtw_print_txdesc(struct rtw_softc *sc, const char *action, 3180 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc) 3181 { 3182 struct rtw_txdesc *td = &tdb->tdb_desc[desc]; 3183 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] next %#08x " 3184 "buf %#08x ctl0 %#08x ctl1 %#08x len %#08x\n", 3185 device_xname(sc->sc_dev), ts, action, desc, 3186 le32toh(td->td_buf), le32toh(td->td_next), 3187 le32toh(td->td_ctl0), le32toh(td->td_ctl1), 3188 le32toh(td->td_len))); 3189 } 3190 #endif /* RTW_DEBUG */ 3191 3192 static void 3193 rtw_start(struct ifnet *ifp) 3194 { 3195 uint8_t tppoll; 3196 int desc, i, lastdesc, npkt, rate; 3197 uint32_t proto_ctl0, ctl0, ctl1; 3198 bus_dmamap_t dmamap; 3199 struct ieee80211com *ic; 3200 struct ieee80211_duration *d0; 3201 struct ieee80211_frame_min *wh; 3202 struct ieee80211_node *ni = NULL; /* XXX: GCC */ 3203 struct mbuf *m0; 3204 struct rtw_softc *sc; 3205 struct rtw_txsoft_blk *tsb = NULL; /* XXX: GCC */ 3206 struct rtw_txdesc_blk *tdb = NULL; /* XXX: GCC */ 3207 struct rtw_txsoft *ts; 3208 struct rtw_txdesc *td; 3209 struct ieee80211_key *k; 3210 3211 sc = (struct rtw_softc *)ifp->if_softc; 3212 ic = &sc->sc_ic; 3213 3214 DPRINTF(sc, RTW_DEBUG_XMIT, 3215 ("%s: enter %s\n", device_xname(sc->sc_dev), __func__)); 3216 3217 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3218 goto out; 3219 3220 /* XXX do real rate control */ 3221 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS; 3222 3223 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0) 3224 proto_ctl0 |= RTW_TXCTL0_SPLCP; 3225 3226 for (;;) { 3227 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1) 3228 continue; 3229 if (m0 == NULL) 3230 break; 3231 3232 wh = mtod(m0, struct ieee80211_frame_min *); 3233 3234 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 && 3235 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3236 m_freem(m0); 3237 break; 3238 } else 3239 k = NULL; 3240 3241 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq); 3242 3243 dmamap = ts->ts_dmamap; 3244 3245 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0, 3246 tdb->tdb_nfree, sc->sc_dev); 3247 3248 if (m0 == NULL || dmamap->dm_nsegs == 0) { 3249 DPRINTF(sc, RTW_DEBUG_XMIT, 3250 ("%s: fail dmamap load\n", __func__)); 3251 goto post_dequeue_err; 3252 } 3253 3254 /* Note well: rtw_dmamap_load_txbuf may have created 3255 * a new chain, so we must find the header once 3256 * more. 3257 */ 3258 wh = mtod(m0, struct ieee80211_frame_min *); 3259 3260 /* XXX do real rate control */ 3261 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3262 IEEE80211_FC0_TYPE_MGT) 3263 rate = 2; 3264 else 3265 rate = MAX(2, ieee80211_get_rate(ni)); 3266 3267 #ifdef RTW_DEBUG 3268 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3269 (IFF_DEBUG|IFF_LINK2)) { 3270 ieee80211_dump_pkt(mtod(m0, uint8_t *), 3271 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len 3272 : sizeof(wh), 3273 rate, 0); 3274 } 3275 #endif /* RTW_DEBUG */ 3276 ctl0 = proto_ctl0 | 3277 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); 3278 3279 switch (rate) { 3280 default: 3281 case 2: 3282 ctl0 |= RTW_TXCTL0_RATE_1MBPS; 3283 break; 3284 case 4: 3285 ctl0 |= RTW_TXCTL0_RATE_2MBPS; 3286 break; 3287 case 11: 3288 ctl0 |= RTW_TXCTL0_RATE_5MBPS; 3289 break; 3290 case 22: 3291 ctl0 |= RTW_TXCTL0_RATE_11MBPS; 3292 break; 3293 } 3294 /* XXX >= ? Compare after fragmentation? */ 3295 if (m0->m_pkthdr.len > ic->ic_rtsthreshold) 3296 ctl0 |= RTW_TXCTL0_RTSEN; 3297 3298 /* XXX Sometimes writes a bogus keyid; h/w doesn't 3299 * seem to care, since we don't activate h/w Tx 3300 * encryption. 3301 */ 3302 if (k != NULL) { 3303 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & 3304 RTW_TXCTL0_KEYID_MASK; 3305 } 3306 3307 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3308 IEEE80211_FC0_TYPE_MGT) { 3309 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN); 3310 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 3311 IEEE80211_FC0_SUBTYPE_BEACON) 3312 ctl0 |= RTW_TXCTL0_BEACON; 3313 } 3314 3315 if (ieee80211_compute_duration(wh, k, m0->m_pkthdr.len, 3316 ic->ic_flags, ic->ic_fragthreshold, 3317 rate, &ts->ts_d0, &ts->ts_dn, &npkt, 3318 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == 3319 (IFF_DEBUG|IFF_LINK2)) == -1) { 3320 DPRINTF(sc, RTW_DEBUG_XMIT, 3321 ("%s: fail compute duration\n", __func__)); 3322 goto post_load_err; 3323 } 3324 3325 d0 = &ts->ts_d0; 3326 3327 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); 3328 3329 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | 3330 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); 3331 3332 if (d0->d_residue) 3333 ctl1 |= RTW_TXCTL1_LENGEXT; 3334 3335 /* TBD fragmentation */ 3336 3337 ts->ts_first = tdb->tdb_next; 3338 3339 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3340 BUS_DMASYNC_PREWRITE); 3341 3342 KASSERT(ts->ts_first < tdb->tdb_ndesc); 3343 3344 #if NBPFILTER > 0 3345 if (ic->ic_rawbpf != NULL) 3346 bpf_mtap((void *)ic->ic_rawbpf, m0); 3347 3348 if (sc->sc_radiobpf != NULL) { 3349 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap; 3350 3351 rt->rt_rate = rate; 3352 3353 bpf_mtap2(sc->sc_radiobpf, (void *)rt, 3354 sizeof(sc->sc_txtapu), m0); 3355 } 3356 #endif /* NBPFILTER > 0 */ 3357 3358 for (i = 0, lastdesc = desc = ts->ts_first; 3359 i < dmamap->dm_nsegs; 3360 i++, desc = RTW_NEXT_IDX(tdb, desc)) { 3361 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) { 3362 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, 3363 ("%s: seg too long\n", __func__)); 3364 goto post_load_err; 3365 } 3366 td = &tdb->tdb_desc[desc]; 3367 td->td_ctl0 = htole32(ctl0); 3368 td->td_ctl1 = htole32(ctl1); 3369 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr); 3370 td->td_len = htole32(dmamap->dm_segs[i].ds_len); 3371 td->td_next = htole32(RTW_NEXT_DESC(tdb, desc)); 3372 if (i != 0) 3373 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN); 3374 lastdesc = desc; 3375 #ifdef RTW_DEBUG 3376 rtw_print_txdesc(sc, "load", ts, tdb, desc); 3377 #endif /* RTW_DEBUG */ 3378 } 3379 3380 KASSERT(desc < tdb->tdb_ndesc); 3381 3382 ts->ts_ni = ni; 3383 KASSERT(ni != NULL); 3384 ts->ts_mbuf = m0; 3385 ts->ts_last = lastdesc; 3386 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS); 3387 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3388 htole32(RTW_TXCTL0_FS); 3389 3390 #ifdef RTW_DEBUG 3391 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first); 3392 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last); 3393 #endif /* RTW_DEBUG */ 3394 3395 tdb->tdb_nfree -= dmamap->dm_nsegs; 3396 tdb->tdb_next = desc; 3397 3398 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs, 3399 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3400 3401 tdb->tdb_desc[ts->ts_first].td_ctl0 |= 3402 htole32(RTW_TXCTL0_OWN); 3403 3404 #ifdef RTW_DEBUG 3405 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first); 3406 #endif /* RTW_DEBUG */ 3407 3408 rtw_txdescs_sync(tdb, ts->ts_first, 1, 3409 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3410 3411 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q); 3412 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q); 3413 3414 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN]) 3415 sc->sc_led_state.ls_event |= RTW_LED_S_TX; 3416 tsb->tsb_tx_timer = 5; 3417 ifp->if_timer = 1; 3418 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL); 3419 tppoll &= ~RTW_TPPOLL_SALL; 3420 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL; 3421 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll); 3422 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL); 3423 } 3424 out: 3425 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__)); 3426 return; 3427 post_load_err: 3428 bus_dmamap_unload(sc->sc_dmat, dmamap); 3429 m_freem(m0); 3430 post_dequeue_err: 3431 ieee80211_free_node(ni); 3432 return; 3433 } 3434 3435 static void 3436 rtw_idle(struct rtw_regs *regs) 3437 { 3438 int active; 3439 3440 /* request stop DMA; wait for packets to stop transmitting. */ 3441 3442 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL); 3443 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL); 3444 3445 for (active = 0; active < 300 && 3446 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0; active++) 3447 DELAY(10); 3448 printf("%s: transmit DMA idle in %dus\n", __func__, active * 10); 3449 } 3450 3451 static void 3452 rtw_watchdog(struct ifnet *ifp) 3453 { 3454 int pri, tx_timeouts = 0; 3455 struct rtw_softc *sc; 3456 struct rtw_txsoft_blk *tsb; 3457 3458 sc = ifp->if_softc; 3459 3460 ifp->if_timer = 0; 3461 3462 if ((sc->sc_flags & RTW_F_ENABLED) == 0) 3463 return; 3464 3465 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3466 tsb = &sc->sc_txsoft_blk[pri]; 3467 3468 if (tsb->tsb_tx_timer == 0) 3469 continue; 3470 else if (--tsb->tsb_tx_timer == 0) { 3471 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) 3472 continue; 3473 printf("%s: transmit timeout, priority %d\n", 3474 ifp->if_xname, pri); 3475 ifp->if_oerrors++; 3476 if (pri != RTW_TXPRIBCN) 3477 tx_timeouts++; 3478 } else 3479 ifp->if_timer = 1; 3480 } 3481 3482 if (tx_timeouts > 0) { 3483 /* Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr, 3484 * reset s/w tx-ring pointers, and start transmission. 3485 * 3486 * TBD Stop/restart just the broken rings? 3487 */ 3488 rtw_idle(&sc->sc_regs); 3489 rtw_io_enable(sc, RTW_CR_TE, 0); 3490 rtw_txdescs_reset(sc); 3491 rtw_io_enable(sc, RTW_CR_TE, 1); 3492 rtw_start(ifp); 3493 } 3494 ieee80211_watchdog(&sc->sc_ic); 3495 return; 3496 } 3497 3498 static void 3499 rtw_next_scan(void *arg) 3500 { 3501 struct ieee80211com *ic = arg; 3502 int s; 3503 3504 /* don't call rtw_start w/o network interrupts blocked */ 3505 s = splnet(); 3506 if (ic->ic_state == IEEE80211_S_SCAN) 3507 ieee80211_next_scan(ic); 3508 splx(s); 3509 } 3510 3511 static void 3512 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) 3513 { 3514 uint16_t bcnitv, bintritv, intval; 3515 int i; 3516 struct rtw_regs *regs = &sc->sc_regs; 3517 3518 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3519 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]); 3520 3521 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32); 3522 3523 rtw_set_access(regs, RTW_ACCESS_CONFIG); 3524 3525 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); 3526 3527 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; 3528 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); 3529 RTW_WRITE16(regs, RTW_BCNITV, bcnitv); 3530 /* interrupt host 1ms before the TBTT */ 3531 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV; 3532 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV); 3533 RTW_WRITE16(regs, RTW_BINTRITV, bintritv); 3534 /* magic from Linux */ 3535 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND)); 3536 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); 3537 rtw_set_access(regs, RTW_ACCESS_NONE); 3538 3539 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1); 3540 } 3541 3542 /* Synchronize the hardware state with the software state. */ 3543 static int 3544 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3545 { 3546 struct ifnet *ifp = ic->ic_ifp; 3547 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3548 enum ieee80211_state ostate; 3549 int error; 3550 3551 ostate = ic->ic_state; 3552 3553 rtw_led_newstate(sc, nstate); 3554 3555 if (nstate == IEEE80211_S_INIT) { 3556 callout_stop(&sc->sc_scan_ch); 3557 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 3558 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3559 } 3560 3561 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT) 3562 rtw_pwrstate(sc, RTW_ON); 3563 3564 if ((error = rtw_tune(sc)) != 0) 3565 return error; 3566 3567 switch (nstate) { 3568 case IEEE80211_S_INIT: 3569 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 3570 break; 3571 case IEEE80211_S_SCAN: 3572 if (ostate != IEEE80211_S_SCAN) { 3573 (void)memset(ic->ic_bss->ni_bssid, 0, 3574 IEEE80211_ADDR_LEN); 3575 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3576 } 3577 3578 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000, 3579 rtw_next_scan, ic); 3580 3581 break; 3582 case IEEE80211_S_RUN: 3583 switch (ic->ic_opmode) { 3584 case IEEE80211_M_HOSTAP: 3585 case IEEE80211_M_IBSS: 3586 rtw_set_nettype(sc, IEEE80211_M_MONITOR); 3587 /*FALLTHROUGH*/ 3588 case IEEE80211_M_AHDEMO: 3589 case IEEE80211_M_STA: 3590 rtw_join_bss(sc, ic->ic_bss->ni_bssid, 3591 ic->ic_bss->ni_intval); 3592 break; 3593 case IEEE80211_M_MONITOR: 3594 break; 3595 } 3596 rtw_set_nettype(sc, ic->ic_opmode); 3597 break; 3598 case IEEE80211_S_ASSOC: 3599 case IEEE80211_S_AUTH: 3600 break; 3601 } 3602 3603 if (nstate != IEEE80211_S_SCAN) 3604 callout_stop(&sc->sc_scan_ch); 3605 3606 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg); 3607 } 3608 3609 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */ 3610 static uint64_t 3611 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp) 3612 { 3613 uint32_t tsftl, tsfth; 3614 3615 tsfth = RTW_READ(regs, RTW_TSFTRH); 3616 tsftl = RTW_READ(regs, RTW_TSFTRL); 3617 if (tsftl < rstamp) /* Compensate for rollover. */ 3618 tsfth--; 3619 return ((uint64_t)tsfth << 32) | rstamp; 3620 } 3621 3622 static void 3623 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3624 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 3625 { 3626 struct ifnet *ifp = ic->ic_ifp; 3627 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3628 3629 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3630 3631 switch (subtype) { 3632 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3633 case IEEE80211_FC0_SUBTYPE_BEACON: 3634 if (ic->ic_opmode == IEEE80211_M_IBSS && 3635 ic->ic_state == IEEE80211_S_RUN) { 3636 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp); 3637 if (le64toh(ni->ni_tstamp.tsf) >= tsf) 3638 (void)ieee80211_ibss_merge(ni); 3639 } 3640 break; 3641 default: 3642 break; 3643 } 3644 return; 3645 } 3646 3647 static struct ieee80211_node * 3648 rtw_node_alloc(struct ieee80211_node_table *nt) 3649 { 3650 struct ifnet *ifp = nt->nt_ic->ic_ifp; 3651 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3652 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt); 3653 3654 DPRINTF(sc, RTW_DEBUG_NODE, 3655 ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 3656 return ni; 3657 } 3658 3659 static void 3660 rtw_node_free(struct ieee80211_node *ni) 3661 { 3662 struct ieee80211com *ic = ni->ni_ic; 3663 struct ifnet *ifp = ic->ic_ifp; 3664 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc; 3665 3666 DPRINTF(sc, RTW_DEBUG_NODE, 3667 ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 3668 ether_sprintf(ni->ni_bssid))); 3669 (*sc->sc_mtbl.mt_node_free)(ni); 3670 } 3671 3672 static int 3673 rtw_media_change(struct ifnet *ifp) 3674 { 3675 int error; 3676 3677 error = ieee80211_media_change(ifp); 3678 if (error == ENETRESET) { 3679 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3680 (IFF_RUNNING|IFF_UP)) 3681 rtw_init(ifp); /* XXX lose error */ 3682 error = 0; 3683 } 3684 return error; 3685 } 3686 3687 static void 3688 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3689 { 3690 struct rtw_softc *sc = ifp->if_softc; 3691 3692 if ((sc->sc_flags & RTW_F_ENABLED) == 0) { 3693 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3694 imr->ifm_status = 0; 3695 return; 3696 } 3697 ieee80211_media_status(ifp, imr); 3698 } 3699 3700 static inline void 3701 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc) 3702 { 3703 (void)strlcpy(ifp->if_xname, dvname, IFNAMSIZ); 3704 ifp->if_softc = softc; 3705 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 3706 IFF_NOTRAILERS; 3707 ifp->if_ioctl = rtw_ioctl; 3708 ifp->if_start = rtw_start; 3709 ifp->if_watchdog = rtw_watchdog; 3710 ifp->if_init = rtw_init; 3711 ifp->if_stop = rtw_stop; 3712 } 3713 3714 static inline void 3715 rtw_set80211props(struct ieee80211com *ic) 3716 { 3717 int nrate; 3718 ic->ic_phytype = IEEE80211_T_DS; 3719 ic->ic_opmode = IEEE80211_M_STA; 3720 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 3721 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 3722 3723 nrate = 0; 3724 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3725 IEEE80211_RATE_BASIC | 2; 3726 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 3727 IEEE80211_RATE_BASIC | 4; 3728 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 3729 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 3730 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 3731 } 3732 3733 static inline void 3734 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic) 3735 { 3736 mtbl->mt_newstate = ic->ic_newstate; 3737 ic->ic_newstate = rtw_newstate; 3738 3739 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt; 3740 ic->ic_recv_mgmt = rtw_recv_mgmt; 3741 3742 mtbl->mt_node_free = ic->ic_node_free; 3743 ic->ic_node_free = rtw_node_free; 3744 3745 mtbl->mt_node_alloc = ic->ic_node_alloc; 3746 ic->ic_node_alloc = rtw_node_alloc; 3747 3748 ic->ic_crypto.cs_key_delete = rtw_key_delete; 3749 ic->ic_crypto.cs_key_set = rtw_key_set; 3750 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin; 3751 ic->ic_crypto.cs_key_update_end = rtw_key_update_end; 3752 } 3753 3754 static inline void 3755 rtw_init_radiotap(struct rtw_softc *sc) 3756 { 3757 uint32_t present; 3758 3759 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 3760 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 3761 3762 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) 3763 present = htole32(RTW_PHILIPS_RX_RADIOTAP_PRESENT); 3764 else 3765 present = htole32(RTW_RX_RADIOTAP_PRESENT); 3766 sc->sc_rxtap.rr_ihdr.it_present = present; 3767 3768 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 3769 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 3770 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT); 3771 } 3772 3773 static int 3774 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen) 3775 { 3776 SIMPLEQ_INIT(&tsb->tsb_dirtyq); 3777 SIMPLEQ_INIT(&tsb->tsb_freeq); 3778 tsb->tsb_ndesc = qlen; 3779 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF, 3780 M_NOWAIT); 3781 if (tsb->tsb_desc == NULL) 3782 return ENOMEM; 3783 return 0; 3784 } 3785 3786 static void 3787 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc) 3788 { 3789 int pri; 3790 struct rtw_txsoft_blk *tsb; 3791 3792 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3793 tsb = &sc->sc_txsoft_blk[pri]; 3794 free(tsb->tsb_desc, M_DEVBUF); 3795 tsb->tsb_desc = NULL; 3796 } 3797 } 3798 3799 static int 3800 rtw_txsoft_blk_setup_all(struct rtw_softc *sc) 3801 { 3802 int pri, rc = 0; 3803 int qlen[RTW_NTXPRI] = 3804 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN}; 3805 struct rtw_txsoft_blk *tsbs; 3806 3807 tsbs = sc->sc_txsoft_blk; 3808 3809 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3810 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]); 3811 if (rc != 0) 3812 break; 3813 } 3814 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ; 3815 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ; 3816 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ; 3817 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ; 3818 return rc; 3819 } 3820 3821 static void 3822 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc, 3823 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase) 3824 { 3825 tdb->tdb_ndesc = ndesc; 3826 tdb->tdb_desc = desc; 3827 tdb->tdb_physbase = physbase; 3828 tdb->tdb_ofs = ofs; 3829 3830 (void)memset(tdb->tdb_desc, 0, 3831 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc); 3832 3833 rtw_txdesc_blk_init(tdb); 3834 tdb->tdb_next = 0; 3835 } 3836 3837 static void 3838 rtw_txdesc_blk_setup_all(struct rtw_softc *sc) 3839 { 3840 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO], 3841 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO, 3842 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo)); 3843 3844 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD], 3845 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD, 3846 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd)); 3847 3848 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI], 3849 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI, 3850 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi)); 3851 3852 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN], 3853 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN, 3854 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn)); 3855 } 3856 3857 static struct rtw_rf * 3858 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy) 3859 { 3860 rtw_rf_write_t rf_write; 3861 struct rtw_rf *rf; 3862 3863 switch (rfchipid) { 3864 default: 3865 rf_write = rtw_rf_hostwrite; 3866 break; 3867 case RTW_RFCHIPID_INTERSIL: 3868 case RTW_RFCHIPID_PHILIPS: 3869 case RTW_RFCHIPID_GCT: /* XXX a guess */ 3870 case RTW_RFCHIPID_RFMD: 3871 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite; 3872 break; 3873 } 3874 3875 switch (rfchipid) { 3876 case RTW_RFCHIPID_GCT: 3877 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0); 3878 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3879 break; 3880 case RTW_RFCHIPID_MAXIM: 3881 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0); 3882 sc->sc_pwrstate_cb = rtw_maxim_pwrstate; 3883 break; 3884 case RTW_RFCHIPID_PHILIPS: 3885 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy); 3886 sc->sc_pwrstate_cb = rtw_philips_pwrstate; 3887 break; 3888 case RTW_RFCHIPID_RFMD: 3889 /* XXX RFMD has no RF constructor */ 3890 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate; 3891 /*FALLTHROUGH*/ 3892 default: 3893 return NULL; 3894 } 3895 rf->rf_continuous_tx_cb = 3896 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable; 3897 rf->rf_continuous_tx_arg = (void *)sc; 3898 return rf; 3899 } 3900 3901 /* Revision C and later use a different PHY delay setting than 3902 * revisions A and B. 3903 */ 3904 static uint8_t 3905 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) 3906 { 3907 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) 3908 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) 3909 3910 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); 3911 3912 RTW_WRITE(regs, RTW_RCR, REVAB); 3913 RTW_WBW(regs, RTW_RCR, RTW_RCR); 3914 RTW_WRITE(regs, RTW_RCR, REVC); 3915 3916 RTW_WBR(regs, RTW_RCR, RTW_RCR); 3917 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC) 3918 phydelay |= RTW_PHYDELAY_REVC_MAGIC; 3919 3920 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */ 3921 RTW_SYNC(regs, RTW_RCR, RTW_RCR); 3922 3923 return phydelay; 3924 #undef REVC 3925 } 3926 3927 void 3928 rtw_attach(struct rtw_softc *sc) 3929 { 3930 struct ifnet *ifp = &sc->sc_if; 3931 struct ieee80211com *ic = &sc->sc_ic; 3932 struct rtw_txsoft_blk *tsb; 3933 int pri, rc; 3934 3935 rtw_cipher_wep = ieee80211_cipher_wep; 3936 rtw_cipher_wep.ic_decap = rtw_wep_decap; 3937 3938 NEXT_ATTACH_STATE(sc, DETACHED); 3939 3940 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) { 3941 case RTW_TCR_HWVERID_F: 3942 sc->sc_hwverid = 'F'; 3943 break; 3944 case RTW_TCR_HWVERID_D: 3945 sc->sc_hwverid = 'D'; 3946 break; 3947 default: 3948 sc->sc_hwverid = '?'; 3949 break; 3950 } 3951 aprint_verbose_dev(sc->sc_dev, "hardware version %c\n", 3952 sc->sc_hwverid); 3953 3954 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs), 3955 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs, 3956 0); 3957 3958 if (rc != 0) { 3959 aprint_error_dev(sc->sc_dev, 3960 "could not allocate hw descriptors, error %d\n", rc); 3961 goto err; 3962 } 3963 3964 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC); 3965 3966 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs, 3967 sc->sc_desc_nsegs, sizeof(struct rtw_descs), 3968 (void **)&sc->sc_descs, BUS_DMA_COHERENT); 3969 3970 if (rc != 0) { 3971 aprint_error_dev(sc->sc_dev, 3972 "could not map hw descriptors, error %d\n", rc); 3973 goto err; 3974 } 3975 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP); 3976 3977 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1, 3978 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap); 3979 3980 if (rc != 0) { 3981 aprint_error_dev(sc->sc_dev, 3982 "could not create DMA map for hw descriptors, error %d\n", 3983 rc); 3984 goto err; 3985 } 3986 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE); 3987 3988 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat; 3989 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap; 3990 3991 for (pri = 0; pri < RTW_NTXPRI; pri++) { 3992 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat; 3993 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap; 3994 } 3995 3996 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs, 3997 sizeof(struct rtw_descs), NULL, 0); 3998 3999 if (rc != 0) { 4000 aprint_error_dev(sc->sc_dev, 4001 "could not load DMA map for hw descriptors, error %d\n", 4002 rc); 4003 goto err; 4004 } 4005 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD); 4006 4007 if (rtw_txsoft_blk_setup_all(sc) != 0) 4008 goto err; 4009 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP); 4010 4011 rtw_txdesc_blk_setup_all(sc); 4012 4013 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP); 4014 4015 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0]; 4016 4017 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4018 tsb = &sc->sc_txsoft_blk[pri]; 4019 4020 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat, 4021 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) { 4022 aprint_error_dev(sc->sc_dev, 4023 "could not load DMA map for hw tx descriptors, " 4024 "error %d\n", rc); 4025 goto err; 4026 } 4027 } 4028 4029 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE); 4030 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0], 4031 RTW_RXQLEN)) != 0) { 4032 aprint_error_dev(sc->sc_dev, 4033 "could not load DMA map for hw rx descriptors, error %d\n", 4034 rc); 4035 goto err; 4036 } 4037 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE); 4038 4039 /* Reset the chip to a known state. */ 4040 if (rtw_reset(sc) != 0) 4041 goto err; 4042 NEXT_ATTACH_STATE(sc, FINISH_RESET); 4043 4044 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR); 4045 4046 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0) 4047 sc->sc_flags |= RTW_F_9356SROM; 4048 4049 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom, 4050 sc->sc_dev) != 0) 4051 goto err; 4052 4053 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM); 4054 4055 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr, 4056 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale, 4057 sc->sc_dev) != 0) { 4058 aprint_error_dev(sc->sc_dev, 4059 "attach failed, malformed serial ROM\n"); 4060 goto err; 4061 } 4062 4063 aprint_verbose_dev(sc->sc_dev, "%s PHY\n", 4064 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog"); 4065 4066 aprint_verbose_dev(sc->sc_dev, "carrier-sense threshold %u\n", 4067 sc->sc_csthr); 4068 4069 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM); 4070 4071 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid, 4072 sc->sc_flags & RTW_F_DIGPHY); 4073 4074 if (sc->sc_rf == NULL) { 4075 aprint_verbose_dev(sc->sc_dev, 4076 "attach failed, could not attach RF\n"); 4077 goto err; 4078 } 4079 4080 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH); 4081 4082 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr); 4083 4084 RTW_DPRINTF(RTW_DEBUG_ATTACH, 4085 ("%s: PHY delay %d\n", device_xname(sc->sc_dev), sc->sc_phydelay)); 4086 4087 if (sc->sc_locale == RTW_LOCALE_UNKNOWN) 4088 rtw_identify_country(&sc->sc_regs, &sc->sc_locale); 4089 4090 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, sc->sc_dev); 4091 4092 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr, 4093 sc->sc_dev) != 0) 4094 goto err; 4095 NEXT_ATTACH_STATE(sc, FINISH_ID_STA); 4096 4097 rtw_setifprops(ifp, device_xname(sc->sc_dev), (void*)sc); 4098 4099 IFQ_SET_READY(&ifp->if_snd); 4100 4101 sc->sc_ic.ic_ifp = ifp; 4102 rtw_set80211props(&sc->sc_ic); 4103 4104 rtw_led_attach(&sc->sc_led_state, (void *)sc); 4105 4106 /* 4107 * Call MI attach routines. 4108 */ 4109 if_attach(ifp); 4110 ieee80211_ifattach(&sc->sc_ic); 4111 4112 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic); 4113 4114 /* possibly we should fill in our own sc_send_prresp, since 4115 * the RTL8180 is probably sending probe responses in ad hoc 4116 * mode. 4117 */ 4118 4119 /* complete initialization */ 4120 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status); 4121 callout_init(&sc->sc_scan_ch, 0); 4122 4123 rtw_init_radiotap(sc); 4124 4125 #if NBPFILTER > 0 4126 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4127 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 4128 #endif 4129 4130 if (!pmf_device_register(sc->sc_dev, NULL, NULL)) { 4131 aprint_error_dev(sc->sc_dev, 4132 "couldn't establish power handler\n"); 4133 } else 4134 pmf_class_network_register(sc->sc_dev, &sc->sc_if); 4135 4136 NEXT_ATTACH_STATE(sc, FINISHED); 4137 4138 ieee80211_announce(ic); 4139 return; 4140 err: 4141 rtw_detach(sc); 4142 return; 4143 } 4144 4145 int 4146 rtw_detach(struct rtw_softc *sc) 4147 { 4148 struct ifnet *ifp = &sc->sc_if; 4149 int pri, s; 4150 4151 s = splnet(); 4152 sc->sc_flags |= RTW_F_INVALID; 4153 4154 switch (sc->sc_attach_state) { 4155 case FINISHED: 4156 rtw_stop(ifp, 1); 4157 4158 pmf_device_deregister(sc->sc_dev); 4159 callout_stop(&sc->sc_scan_ch); 4160 ieee80211_ifdetach(&sc->sc_ic); 4161 if_detach(ifp); 4162 /*FALLTHROUGH*/ 4163 case FINISH_ID_STA: 4164 case FINISH_RF_ATTACH: 4165 rtw_rf_destroy(sc->sc_rf); 4166 sc->sc_rf = NULL; 4167 /*FALLTHROUGH*/ 4168 case FINISH_PARSE_SROM: 4169 case FINISH_READ_SROM: 4170 rtw_srom_free(&sc->sc_srom); 4171 /*FALLTHROUGH*/ 4172 case FINISH_RESET: 4173 case FINISH_RXMAPS_CREATE: 4174 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0], 4175 RTW_RXQLEN); 4176 /*FALLTHROUGH*/ 4177 case FINISH_TXMAPS_CREATE: 4178 for (pri = 0; pri < RTW_NTXPRI; pri++) { 4179 rtw_txdesc_dmamaps_destroy(sc->sc_dmat, 4180 sc->sc_txsoft_blk[pri].tsb_desc, 4181 sc->sc_txsoft_blk[pri].tsb_ndesc); 4182 } 4183 /*FALLTHROUGH*/ 4184 case FINISH_TXDESCBLK_SETUP: 4185 case FINISH_TXCTLBLK_SETUP: 4186 rtw_txsoft_blk_cleanup_all(sc); 4187 /*FALLTHROUGH*/ 4188 case FINISH_DESCMAP_LOAD: 4189 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap); 4190 /*FALLTHROUGH*/ 4191 case FINISH_DESCMAP_CREATE: 4192 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap); 4193 /*FALLTHROUGH*/ 4194 case FINISH_DESC_MAP: 4195 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 4196 sizeof(struct rtw_descs)); 4197 /*FALLTHROUGH*/ 4198 case FINISH_DESC_ALLOC: 4199 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs, 4200 sc->sc_desc_nsegs); 4201 /*FALLTHROUGH*/ 4202 case DETACHED: 4203 NEXT_ATTACH_STATE(sc, DETACHED); 4204 break; 4205 } 4206 splx(s); 4207 return 0; 4208 } 4209 4210 int 4211 rtw_activate(device_t self, enum devact act) 4212 { 4213 struct rtw_softc *sc = device_private(self); 4214 int rc = 0, s; 4215 4216 s = splnet(); 4217 switch (act) { 4218 case DVACT_ACTIVATE: 4219 rc = EOPNOTSUPP; 4220 break; 4221 4222 case DVACT_DEACTIVATE: 4223 if_deactivate(&sc->sc_if); 4224 break; 4225 } 4226 splx(s); 4227 return rc; 4228 } 4229
Indexes created Tue Sep 30 07:10:03 GMT 2025