rtwphy.c revision 1.1.2.3
1 1.1.2.3 skrll /* $NetBSD: rtwphy.c,v 1.1.2.3 2004/12/18 09:31:57 skrll Exp $ */ 2 1.1.2.2 skrll /*- 3 1.1.2.2 skrll * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 1.1.2.2 skrll * 5 1.1.2.2 skrll * Programmed for NetBSD by David Young. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 3. The name of David Young may not be used to endorse or promote 16 1.1.2.2 skrll * products derived from this software without specific prior 17 1.1.2.2 skrll * written permission. 18 1.1.2.2 skrll * 19 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 1.1.2.2 skrll * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 1.1.2.2 skrll * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 1.1.2.2 skrll * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 1.1.2.2 skrll * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 1.1.2.2 skrll * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 1.1.2.2 skrll * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 1.1.2.2 skrll * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 1.1.2.2 skrll * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 1.1.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 1.1.2.2 skrll * OF SUCH DAMAGE. 31 1.1.2.2 skrll */ 32 1.1.2.2 skrll /* 33 1.1.2.2 skrll * Control the Philips SA2400 RF front-end and the baseband processor 34 1.1.2.2 skrll * built into the Realtek RTL8180. 35 1.1.2.2 skrll */ 36 1.1.2.2 skrll 37 1.1.2.2 skrll #include <sys/cdefs.h> 38 1.1.2.3 skrll __KERNEL_RCSID(0, "$NetBSD: rtwphy.c,v 1.1.2.3 2004/12/18 09:31:57 skrll Exp $"); 39 1.1.2.2 skrll 40 1.1.2.2 skrll #include <sys/param.h> 41 1.1.2.2 skrll #include <sys/systm.h> 42 1.1.2.2 skrll #include <sys/types.h> 43 1.1.2.2 skrll 44 1.1.2.2 skrll #include <machine/bus.h> 45 1.1.2.2 skrll 46 1.1.2.2 skrll #include <net/if.h> 47 1.1.2.2 skrll #include <net/if_media.h> 48 1.1.2.2 skrll #include <net/if_ether.h> 49 1.1.2.2 skrll 50 1.1.2.2 skrll #include <net80211/ieee80211_var.h> 51 1.1.2.2 skrll #include <net80211/ieee80211_compat.h> 52 1.1.2.2 skrll #include <net80211/ieee80211_radiotap.h> 53 1.1.2.2 skrll 54 1.1.2.2 skrll #include <dev/ic/rtwreg.h> 55 1.1.2.2 skrll #include <dev/ic/max2820reg.h> 56 1.1.2.2 skrll #include <dev/ic/sa2400reg.h> 57 1.1.2.2 skrll #include <dev/ic/rtwvar.h> 58 1.1.2.2 skrll #include <dev/ic/rtwphyio.h> 59 1.1.2.2 skrll #include <dev/ic/rtwphy.h> 60 1.1.2.2 skrll 61 1.1.2.2 skrll static int rtw_max2820_pwrstate(struct rtw_rf *, enum rtw_pwrstate); 62 1.1.2.2 skrll static int rtw_sa2400_pwrstate(struct rtw_rf *, enum rtw_pwrstate); 63 1.1.2.2 skrll 64 1.1.2.2 skrll static int 65 1.1.2.2 skrll rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb, 66 1.1.2.2 skrll u_int freq) 67 1.1.2.2 skrll { 68 1.1.2.2 skrll u_int antatten = antatten0; 69 1.1.2.2 skrll if (dflantb) 70 1.1.2.2 skrll antatten |= RTW_BBP_ANTATTEN_DFLANTB; 71 1.1.2.2 skrll if (freq == 2484) /* channel 14 */ 72 1.1.2.2 skrll antatten |= RTW_BBP_ANTATTEN_CHAN14; 73 1.1.2.2 skrll return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten); 74 1.1.2.2 skrll } 75 1.1.2.2 skrll 76 1.1.2.2 skrll static int 77 1.1.2.2 skrll rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv, 78 1.1.2.2 skrll int dflantb, u_int8_t cs_threshold, u_int freq) 79 1.1.2.2 skrll { 80 1.1.2.2 skrll int rc; 81 1.1.2.2 skrll u_int32_t sys2, sys3; 82 1.1.2.2 skrll 83 1.1.2.2 skrll sys2 = bb->bb_sys2; 84 1.1.2.2 skrll if (antdiv) 85 1.1.2.2 skrll sys2 |= RTW_BBP_SYS2_ANTDIV; 86 1.1.2.2 skrll sys3 = bb->bb_sys3 | 87 1.1.2.2 skrll LSHIFT(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK); 88 1.1.2.2 skrll 89 1.1.2.2 skrll #define RTW_BBP_WRITE_OR_RETURN(reg, val) \ 90 1.1.2.2 skrll if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \ 91 1.1.2.2 skrll return rc; 92 1.1.2.2 skrll 93 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1, bb->bb_sys1); 94 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC, bb->bb_txagc); 95 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET, bb->bb_lnadet); 96 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI, bb->bb_ifagcini); 97 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT, bb->bb_ifagclimit); 98 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET, bb->bb_ifagcdet); 99 1.1.2.2 skrll 100 1.1.2.2 skrll if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0) 101 1.1.2.2 skrll return rc; 102 1.1.2.2 skrll 103 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL, bb->bb_trl); 104 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2, sys2); 105 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3, sys3); 106 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM, bb->bb_chestlim); 107 1.1.2.2 skrll RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM, bb->bb_chsqlim); 108 1.1.2.2 skrll return 0; 109 1.1.2.2 skrll } 110 1.1.2.2 skrll 111 1.1.2.2 skrll static int 112 1.1.2.2 skrll rtw_sa2400_txpower(struct rtw_rf *rf, u_int8_t opaque_txpower) 113 1.1.2.2 skrll { 114 1.1.2.2 skrll struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 115 1.1.2.2 skrll struct rtw_rfbus *bus = &sa->sa_bus; 116 1.1.2.2 skrll 117 1.1.2.2 skrll return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_TX, 118 1.1.2.2 skrll opaque_txpower); 119 1.1.2.2 skrll } 120 1.1.2.2 skrll 121 1.1.2.2 skrll /* make sure we're using the same settings as the reference driver */ 122 1.1.2.2 skrll static void 123 1.1.2.2 skrll verify_syna(u_int freq, u_int32_t val) 124 1.1.2.2 skrll { 125 1.1.2.2 skrll u_int32_t expected_val = ~val; 126 1.1.2.2 skrll 127 1.1.2.2 skrll switch (freq) { 128 1.1.2.2 skrll case 2412: 129 1.1.2.2 skrll expected_val = 0x0000096c; /* ch 1 */ 130 1.1.2.2 skrll break; 131 1.1.2.2 skrll case 2417: 132 1.1.2.2 skrll expected_val = 0x00080970; /* ch 2 */ 133 1.1.2.2 skrll break; 134 1.1.2.2 skrll case 2422: 135 1.1.2.2 skrll expected_val = 0x00100974; /* ch 3 */ 136 1.1.2.2 skrll break; 137 1.1.2.2 skrll case 2427: 138 1.1.2.2 skrll expected_val = 0x00180978; /* ch 4 */ 139 1.1.2.2 skrll break; 140 1.1.2.2 skrll case 2432: 141 1.1.2.2 skrll expected_val = 0x00000980; /* ch 5 */ 142 1.1.2.2 skrll break; 143 1.1.2.2 skrll case 2437: 144 1.1.2.2 skrll expected_val = 0x00080984; /* ch 6 */ 145 1.1.2.2 skrll break; 146 1.1.2.2 skrll case 2442: 147 1.1.2.2 skrll expected_val = 0x00100988; /* ch 7 */ 148 1.1.2.2 skrll break; 149 1.1.2.2 skrll case 2447: 150 1.1.2.2 skrll expected_val = 0x0018098c; /* ch 8 */ 151 1.1.2.2 skrll break; 152 1.1.2.2 skrll case 2452: 153 1.1.2.2 skrll expected_val = 0x00000994; /* ch 9 */ 154 1.1.2.2 skrll break; 155 1.1.2.2 skrll case 2457: 156 1.1.2.2 skrll expected_val = 0x00080998; /* ch 10 */ 157 1.1.2.2 skrll break; 158 1.1.2.2 skrll case 2462: 159 1.1.2.2 skrll expected_val = 0x0010099c; /* ch 11 */ 160 1.1.2.2 skrll break; 161 1.1.2.2 skrll case 2467: 162 1.1.2.2 skrll expected_val = 0x001809a0; /* ch 12 */ 163 1.1.2.2 skrll break; 164 1.1.2.2 skrll case 2472: 165 1.1.2.2 skrll expected_val = 0x000009a8; /* ch 13 */ 166 1.1.2.2 skrll break; 167 1.1.2.2 skrll case 2484: 168 1.1.2.2 skrll expected_val = 0x000009b4; /* ch 14 */ 169 1.1.2.2 skrll break; 170 1.1.2.2 skrll } 171 1.1.2.2 skrll KASSERT(val == expected_val); 172 1.1.2.2 skrll } 173 1.1.2.2 skrll 174 1.1.2.2 skrll /* freq is in MHz */ 175 1.1.2.2 skrll static int 176 1.1.2.2 skrll rtw_sa2400_tune(struct rtw_rf *rf, u_int freq) 177 1.1.2.2 skrll { 178 1.1.2.2 skrll struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 179 1.1.2.2 skrll struct rtw_rfbus *bus = &sa->sa_bus; 180 1.1.2.2 skrll int rc; 181 1.1.2.2 skrll u_int32_t syna, synb, sync; 182 1.1.2.2 skrll 183 1.1.2.2 skrll /* XO = 44MHz, R = 11, hence N is in units of XO / R = 4MHz. 184 1.1.2.2 skrll * 185 1.1.2.2 skrll * The channel spacing (5MHz) is not divisible by 4MHz, so 186 1.1.2.2 skrll * we set the fractional part of N to compensate. 187 1.1.2.2 skrll */ 188 1.1.2.2 skrll int n = freq / 4, nf = (freq % 4) * 2; 189 1.1.2.2 skrll 190 1.1.2.2 skrll syna = LSHIFT(nf, SA2400_SYNA_NF_MASK) | LSHIFT(n, SA2400_SYNA_N_MASK); 191 1.1.2.2 skrll verify_syna(freq, syna); 192 1.1.2.2 skrll 193 1.1.2.2 skrll /* Divide the 44MHz crystal down to 4MHz. Set the fractional 194 1.1.2.2 skrll * compensation charge pump value to agree with the fractional 195 1.1.2.2 skrll * modulus. 196 1.1.2.2 skrll */ 197 1.1.2.2 skrll synb = LSHIFT(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL | 198 1.1.2.2 skrll SA2400_SYNB_ON | SA2400_SYNB_ONE | 199 1.1.2.2 skrll LSHIFT(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */ 200 1.1.2.2 skrll 201 1.1.2.2 skrll sync = SA2400_SYNC_CP_NORMAL; 202 1.1.2.2 skrll 203 1.1.2.2 skrll if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNA, 204 1.1.2.2 skrll syna)) != 0) 205 1.1.2.2 skrll return rc; 206 1.1.2.2 skrll if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNB, 207 1.1.2.2 skrll synb)) != 0) 208 1.1.2.2 skrll return rc; 209 1.1.2.2 skrll if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNC, 210 1.1.2.2 skrll sync)) != 0) 211 1.1.2.2 skrll return rc; 212 1.1.2.2 skrll return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYND, 0x0); 213 1.1.2.2 skrll } 214 1.1.2.2 skrll 215 1.1.2.2 skrll static int 216 1.1.2.2 skrll rtw_sa2400_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 217 1.1.2.2 skrll { 218 1.1.2.2 skrll struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 219 1.1.2.2 skrll struct rtw_rfbus *bus = &sa->sa_bus; 220 1.1.2.2 skrll u_int32_t opmode; 221 1.1.2.3 skrll opmode = SA2400_OPMODE_DEFAULTS; 222 1.1.2.2 skrll switch (power) { 223 1.1.2.2 skrll case RTW_ON: 224 1.1.2.2 skrll opmode |= SA2400_OPMODE_MODE_TXRX; 225 1.1.2.2 skrll break; 226 1.1.2.2 skrll case RTW_SLEEP: 227 1.1.2.2 skrll opmode |= SA2400_OPMODE_MODE_WAIT; 228 1.1.2.2 skrll break; 229 1.1.2.2 skrll case RTW_OFF: 230 1.1.2.2 skrll opmode |= SA2400_OPMODE_MODE_SLEEP; 231 1.1.2.2 skrll break; 232 1.1.2.2 skrll } 233 1.1.2.2 skrll 234 1.1.2.2 skrll if (sa->sa_digphy) 235 1.1.2.2 skrll opmode |= SA2400_OPMODE_DIGIN; 236 1.1.2.2 skrll 237 1.1.2.2 skrll return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 238 1.1.2.2 skrll opmode); 239 1.1.2.2 skrll } 240 1.1.2.2 skrll 241 1.1.2.2 skrll static int 242 1.1.2.2 skrll rtw_sa2400_manrx_init(struct rtw_sa2400 *sa) 243 1.1.2.2 skrll { 244 1.1.2.2 skrll u_int32_t manrx; 245 1.1.2.2 skrll 246 1.1.2.2 skrll /* XXX we are not supposed to be in RXMGC mode when we do 247 1.1.2.2 skrll * this? 248 1.1.2.2 skrll */ 249 1.1.2.2 skrll manrx = SA2400_MANRX_AHSN; 250 1.1.2.2 skrll manrx |= SA2400_MANRX_TEN; 251 1.1.2.2 skrll manrx |= LSHIFT(1023, SA2400_MANRX_RXGAIN_MASK); 252 1.1.2.2 skrll 253 1.1.2.2 skrll return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX, 254 1.1.2.2 skrll manrx); 255 1.1.2.2 skrll } 256 1.1.2.2 skrll 257 1.1.2.2 skrll static int 258 1.1.2.2 skrll rtw_sa2400_vcocal_start(struct rtw_sa2400 *sa, int start) 259 1.1.2.2 skrll { 260 1.1.2.2 skrll u_int32_t opmode; 261 1.1.2.2 skrll 262 1.1.2.3 skrll opmode = SA2400_OPMODE_DEFAULTS; 263 1.1.2.2 skrll if (start) 264 1.1.2.2 skrll opmode |= SA2400_OPMODE_MODE_VCOCALIB; 265 1.1.2.2 skrll else 266 1.1.2.2 skrll opmode |= SA2400_OPMODE_MODE_SLEEP; 267 1.1.2.2 skrll 268 1.1.2.2 skrll if (sa->sa_digphy) 269 1.1.2.2 skrll opmode |= SA2400_OPMODE_DIGIN; 270 1.1.2.2 skrll 271 1.1.2.2 skrll return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 272 1.1.2.2 skrll opmode); 273 1.1.2.2 skrll } 274 1.1.2.2 skrll 275 1.1.2.2 skrll static int 276 1.1.2.2 skrll rtw_sa2400_vco_calibration(struct rtw_sa2400 *sa) 277 1.1.2.2 skrll { 278 1.1.2.2 skrll int rc; 279 1.1.2.2 skrll /* calibrate VCO */ 280 1.1.2.2 skrll if ((rc = rtw_sa2400_vcocal_start(sa, 1)) != 0) 281 1.1.2.2 skrll return rc; 282 1.1.2.2 skrll DELAY(2200); /* 2.2 milliseconds */ 283 1.1.2.2 skrll /* XXX superfluous: SA2400 automatically entered SLEEP mode. */ 284 1.1.2.2 skrll return rtw_sa2400_vcocal_start(sa, 0); 285 1.1.2.2 skrll } 286 1.1.2.2 skrll 287 1.1.2.2 skrll static int 288 1.1.2.2 skrll rtw_sa2400_filter_calibration(struct rtw_sa2400 *sa) 289 1.1.2.2 skrll { 290 1.1.2.2 skrll u_int32_t opmode; 291 1.1.2.2 skrll 292 1.1.2.3 skrll opmode = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_FCALIB; 293 1.1.2.2 skrll if (sa->sa_digphy) 294 1.1.2.2 skrll opmode |= SA2400_OPMODE_DIGIN; 295 1.1.2.2 skrll 296 1.1.2.2 skrll return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 297 1.1.2.2 skrll opmode); 298 1.1.2.2 skrll } 299 1.1.2.2 skrll 300 1.1.2.2 skrll static int 301 1.1.2.2 skrll rtw_sa2400_dc_calibration(struct rtw_sa2400 *sa) 302 1.1.2.2 skrll { 303 1.1.2.2 skrll struct rtw_rf *rf = &sa->sa_rf; 304 1.1.2.2 skrll int rc; 305 1.1.2.2 skrll u_int32_t dccal; 306 1.1.2.2 skrll 307 1.1.2.2 skrll (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 1); 308 1.1.2.2 skrll 309 1.1.2.3 skrll dccal = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_TXRX; 310 1.1.2.2 skrll 311 1.1.2.2 skrll rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 312 1.1.2.2 skrll dccal); 313 1.1.2.2 skrll if (rc != 0) 314 1.1.2.2 skrll return rc; 315 1.1.2.2 skrll 316 1.1.2.2 skrll DELAY(5); /* DCALIB after being in Tx mode for 5 317 1.1.2.2 skrll * microseconds 318 1.1.2.2 skrll */ 319 1.1.2.2 skrll 320 1.1.2.2 skrll dccal &= ~SA2400_OPMODE_MODE_MASK; 321 1.1.2.2 skrll dccal |= SA2400_OPMODE_MODE_DCALIB; 322 1.1.2.2 skrll 323 1.1.2.2 skrll rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 324 1.1.2.2 skrll dccal); 325 1.1.2.2 skrll if (rc != 0) 326 1.1.2.2 skrll return rc; 327 1.1.2.2 skrll 328 1.1.2.2 skrll DELAY(20); /* calibration takes at most 20 microseconds */ 329 1.1.2.2 skrll 330 1.1.2.2 skrll (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 0); 331 1.1.2.2 skrll 332 1.1.2.2 skrll return 0; 333 1.1.2.2 skrll } 334 1.1.2.2 skrll 335 1.1.2.2 skrll static int 336 1.1.2.2 skrll rtw_sa2400_agc_init(struct rtw_sa2400 *sa) 337 1.1.2.2 skrll { 338 1.1.2.2 skrll u_int32_t agc; 339 1.1.2.2 skrll 340 1.1.2.2 skrll agc = LSHIFT(25, SA2400_AGC_MAXGAIN_MASK); 341 1.1.2.2 skrll agc |= LSHIFT(7, SA2400_AGC_BBPDELAY_MASK); 342 1.1.2.2 skrll agc |= LSHIFT(15, SA2400_AGC_LNADELAY_MASK); 343 1.1.2.2 skrll agc |= LSHIFT(27, SA2400_AGC_RXONDELAY_MASK); 344 1.1.2.2 skrll 345 1.1.2.2 skrll return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC, 346 1.1.2.2 skrll agc); 347 1.1.2.2 skrll } 348 1.1.2.2 skrll 349 1.1.2.2 skrll static void 350 1.1.2.2 skrll rtw_sa2400_destroy(struct rtw_rf *rf) 351 1.1.2.2 skrll { 352 1.1.2.2 skrll struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 353 1.1.2.2 skrll memset(sa, 0, sizeof(*sa)); 354 1.1.2.2 skrll free(sa, M_DEVBUF); 355 1.1.2.2 skrll } 356 1.1.2.2 skrll 357 1.1.2.2 skrll static int 358 1.1.2.3 skrll rtw_sa2400_calibrate(struct rtw_rf *rf, u_int freq) 359 1.1.2.3 skrll { 360 1.1.2.3 skrll struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 361 1.1.2.3 skrll int i, rc; 362 1.1.2.3 skrll 363 1.1.2.3 skrll /* XXX reference driver calibrates VCO twice. Is it a bug? */ 364 1.1.2.3 skrll for (i = 0; i < 2; i++) { 365 1.1.2.3 skrll if ((rc = rtw_sa2400_vco_calibration(sa)) != 0) 366 1.1.2.3 skrll return rc; 367 1.1.2.3 skrll } 368 1.1.2.3 skrll /* VCO calibration erases synthesizer registers, so re-tune */ 369 1.1.2.3 skrll if ((rc = rtw_sa2400_tune(rf, freq)) != 0) 370 1.1.2.3 skrll return rc; 371 1.1.2.3 skrll if ((rc = rtw_sa2400_filter_calibration(sa)) != 0) 372 1.1.2.3 skrll return rc; 373 1.1.2.3 skrll /* analog PHY needs DC calibration */ 374 1.1.2.3 skrll if (!sa->sa_digphy) 375 1.1.2.3 skrll return rtw_sa2400_dc_calibration(sa); 376 1.1.2.3 skrll return 0; 377 1.1.2.3 skrll } 378 1.1.2.3 skrll 379 1.1.2.3 skrll static int 380 1.1.2.2 skrll rtw_sa2400_init(struct rtw_rf *rf, u_int freq, u_int8_t opaque_txpower, 381 1.1.2.2 skrll enum rtw_pwrstate power) 382 1.1.2.2 skrll { 383 1.1.2.2 skrll struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 384 1.1.2.2 skrll int rc; 385 1.1.2.2 skrll 386 1.1.2.2 skrll if ((rc = rtw_sa2400_txpower(rf, opaque_txpower)) != 0) 387 1.1.2.2 skrll return rc; 388 1.1.2.2 skrll 389 1.1.2.2 skrll /* skip configuration if it's time to sleep or to power-down. */ 390 1.1.2.2 skrll if (power == RTW_SLEEP || power == RTW_OFF) 391 1.1.2.2 skrll return rtw_sa2400_pwrstate(rf, power); 392 1.1.2.2 skrll 393 1.1.2.2 skrll /* go to sleep for configuration */ 394 1.1.2.2 skrll if ((rc = rtw_sa2400_pwrstate(rf, RTW_SLEEP)) != 0) 395 1.1.2.2 skrll return rc; 396 1.1.2.2 skrll 397 1.1.2.3 skrll if ((rc = rtw_sa2400_tune(rf, freq)) != 0) 398 1.1.2.3 skrll return rc; 399 1.1.2.2 skrll if ((rc = rtw_sa2400_agc_init(sa)) != 0) 400 1.1.2.2 skrll return rc; 401 1.1.2.2 skrll if ((rc = rtw_sa2400_manrx_init(sa)) != 0) 402 1.1.2.2 skrll return rc; 403 1.1.2.3 skrll if ((rc = rtw_sa2400_calibrate(rf, freq)) != 0) 404 1.1.2.2 skrll return rc; 405 1.1.2.3 skrll 406 1.1.2.2 skrll /* enter Tx/Rx mode */ 407 1.1.2.2 skrll return rtw_sa2400_pwrstate(rf, power); 408 1.1.2.2 skrll } 409 1.1.2.2 skrll 410 1.1.2.2 skrll struct rtw_rf * 411 1.1.2.2 skrll rtw_sa2400_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy) 412 1.1.2.2 skrll { 413 1.1.2.2 skrll struct rtw_sa2400 *sa; 414 1.1.2.2 skrll struct rtw_rfbus *bus; 415 1.1.2.2 skrll struct rtw_rf *rf; 416 1.1.2.2 skrll struct rtw_bbpset *bb; 417 1.1.2.2 skrll 418 1.1.2.2 skrll sa = malloc(sizeof(*sa), M_DEVBUF, M_NOWAIT | M_ZERO); 419 1.1.2.2 skrll if (sa == NULL) 420 1.1.2.2 skrll return NULL; 421 1.1.2.2 skrll 422 1.1.2.2 skrll sa->sa_digphy = digphy; 423 1.1.2.2 skrll 424 1.1.2.2 skrll rf = &sa->sa_rf; 425 1.1.2.2 skrll bus = &sa->sa_bus; 426 1.1.2.2 skrll 427 1.1.2.2 skrll rf->rf_init = rtw_sa2400_init; 428 1.1.2.2 skrll rf->rf_destroy = rtw_sa2400_destroy; 429 1.1.2.2 skrll rf->rf_txpower = rtw_sa2400_txpower; 430 1.1.2.2 skrll rf->rf_tune = rtw_sa2400_tune; 431 1.1.2.2 skrll rf->rf_pwrstate = rtw_sa2400_pwrstate; 432 1.1.2.2 skrll bb = &rf->rf_bbpset; 433 1.1.2.2 skrll 434 1.1.2.2 skrll /* XXX magic */ 435 1.1.2.2 skrll bb->bb_antatten = RTW_BBP_ANTATTEN_PHILIPS_MAGIC; 436 1.1.2.2 skrll bb->bb_chestlim = 0x00; 437 1.1.2.2 skrll bb->bb_chsqlim = 0xa0; 438 1.1.2.2 skrll bb->bb_ifagcdet = 0x64; 439 1.1.2.2 skrll bb->bb_ifagcini = 0x90; 440 1.1.2.2 skrll bb->bb_ifagclimit = 0x1a; 441 1.1.2.2 skrll bb->bb_lnadet = 0xe0; 442 1.1.2.2 skrll bb->bb_sys1 = 0x98; 443 1.1.2.2 skrll bb->bb_sys2 = 0x47; 444 1.1.2.2 skrll bb->bb_sys3 = 0x90; 445 1.1.2.2 skrll bb->bb_trl = 0x88; 446 1.1.2.2 skrll bb->bb_txagc = 0x38; 447 1.1.2.2 skrll 448 1.1.2.2 skrll bus->b_regs = regs; 449 1.1.2.2 skrll bus->b_write = rf_write; 450 1.1.2.2 skrll 451 1.1.2.2 skrll return &sa->sa_rf; 452 1.1.2.2 skrll } 453 1.1.2.2 skrll 454 1.1.2.2 skrll /* freq is in MHz */ 455 1.1.2.2 skrll static int 456 1.1.2.2 skrll rtw_max2820_tune(struct rtw_rf *rf, u_int freq) 457 1.1.2.2 skrll { 458 1.1.2.2 skrll struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 459 1.1.2.2 skrll struct rtw_rfbus *bus = &mx->mx_bus; 460 1.1.2.2 skrll 461 1.1.2.2 skrll if (freq < 2400 || freq > 2499) 462 1.1.2.2 skrll return -1; 463 1.1.2.2 skrll 464 1.1.2.2 skrll return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL, 465 1.1.2.2 skrll LSHIFT(freq - 2400, MAX2820_CHANNEL_CF_MASK)); 466 1.1.2.2 skrll } 467 1.1.2.2 skrll 468 1.1.2.2 skrll static void 469 1.1.2.2 skrll rtw_max2820_destroy(struct rtw_rf *rf) 470 1.1.2.2 skrll { 471 1.1.2.2 skrll struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 472 1.1.2.2 skrll memset(mx, 0, sizeof(*mx)); 473 1.1.2.2 skrll free(mx, M_DEVBUF); 474 1.1.2.2 skrll } 475 1.1.2.2 skrll 476 1.1.2.2 skrll static int 477 1.1.2.2 skrll rtw_max2820_init(struct rtw_rf *rf, u_int freq, u_int8_t opaque_txpower, 478 1.1.2.2 skrll enum rtw_pwrstate power) 479 1.1.2.2 skrll { 480 1.1.2.2 skrll struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 481 1.1.2.2 skrll struct rtw_rfbus *bus = &mx->mx_bus; 482 1.1.2.2 skrll int rc; 483 1.1.2.2 skrll 484 1.1.2.2 skrll if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST, 485 1.1.2.2 skrll MAX2820_TEST_DEFAULT)) != 0) 486 1.1.2.2 skrll return rc; 487 1.1.2.2 skrll 488 1.1.2.2 skrll if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, 489 1.1.2.2 skrll MAX2820_ENABLE_DEFAULT)) != 0) 490 1.1.2.2 skrll return rc; 491 1.1.2.2 skrll 492 1.1.2.2 skrll /* skip configuration if it's time to sleep or to power-down. */ 493 1.1.2.2 skrll if ((rc = rtw_max2820_pwrstate(rf, power)) != 0) 494 1.1.2.2 skrll return rc; 495 1.1.2.2 skrll else if (power == RTW_OFF || power == RTW_SLEEP) 496 1.1.2.2 skrll return 0; 497 1.1.2.2 skrll 498 1.1.2.2 skrll if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH, 499 1.1.2.2 skrll MAX2820_SYNTH_R_44MHZ)) != 0) 500 1.1.2.2 skrll return rc; 501 1.1.2.2 skrll 502 1.1.2.2 skrll if ((rc = rtw_max2820_tune(rf, freq)) != 0) 503 1.1.2.2 skrll return rc; 504 1.1.2.2 skrll 505 1.1.2.2 skrll /* XXX The MAX2820 datasheet indicates that 1C and 2C should not 506 1.1.2.2 skrll * be changed from 7, however, the reference driver sets them 507 1.1.2.2 skrll * to 4 and 1, respectively. 508 1.1.2.2 skrll */ 509 1.1.2.2 skrll if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE, 510 1.1.2.2 skrll MAX2820_RECEIVE_DL_DEFAULT | 511 1.1.2.2 skrll LSHIFT(4, MAX2820A_RECEIVE_1C_MASK) | 512 1.1.2.2 skrll LSHIFT(1, MAX2820A_RECEIVE_2C_MASK))) != 0) 513 1.1.2.2 skrll return rc; 514 1.1.2.2 skrll 515 1.1.2.2 skrll return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT, 516 1.1.2.2 skrll MAX2820_TRANSMIT_PA_DEFAULT); 517 1.1.2.2 skrll } 518 1.1.2.2 skrll 519 1.1.2.2 skrll static int 520 1.1.2.2 skrll rtw_max2820_txpower(struct rtw_rf *rf, u_int8_t opaque_txpower) 521 1.1.2.2 skrll { 522 1.1.2.2 skrll /* TBD */ 523 1.1.2.2 skrll return 0; 524 1.1.2.2 skrll } 525 1.1.2.2 skrll 526 1.1.2.2 skrll static int 527 1.1.2.2 skrll rtw_max2820_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 528 1.1.2.2 skrll { 529 1.1.2.2 skrll uint32_t enable; 530 1.1.2.2 skrll struct rtw_max2820 *mx; 531 1.1.2.2 skrll struct rtw_rfbus *bus; 532 1.1.2.2 skrll 533 1.1.2.2 skrll mx = (struct rtw_max2820 *)rf; 534 1.1.2.2 skrll bus = &mx->mx_bus; 535 1.1.2.2 skrll 536 1.1.2.2 skrll switch (power) { 537 1.1.2.2 skrll case RTW_OFF: 538 1.1.2.2 skrll case RTW_SLEEP: 539 1.1.2.2 skrll default: 540 1.1.2.2 skrll enable = 0x0; 541 1.1.2.2 skrll break; 542 1.1.2.2 skrll case RTW_ON: 543 1.1.2.2 skrll enable = MAX2820_ENABLE_DEFAULT; 544 1.1.2.2 skrll break; 545 1.1.2.2 skrll } 546 1.1.2.2 skrll return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, enable); 547 1.1.2.2 skrll } 548 1.1.2.2 skrll 549 1.1.2.2 skrll struct rtw_rf * 550 1.1.2.2 skrll rtw_max2820_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int is_a) 551 1.1.2.2 skrll { 552 1.1.2.2 skrll struct rtw_max2820 *mx; 553 1.1.2.2 skrll struct rtw_rfbus *bus; 554 1.1.2.2 skrll struct rtw_rf *rf; 555 1.1.2.2 skrll struct rtw_bbpset *bb; 556 1.1.2.2 skrll 557 1.1.2.2 skrll mx = malloc(sizeof(*mx), M_DEVBUF, M_NOWAIT | M_ZERO); 558 1.1.2.2 skrll if (mx == NULL) 559 1.1.2.2 skrll return NULL; 560 1.1.2.2 skrll 561 1.1.2.2 skrll mx->mx_is_a = is_a; 562 1.1.2.2 skrll 563 1.1.2.2 skrll rf = &mx->mx_rf; 564 1.1.2.2 skrll bus = &mx->mx_bus; 565 1.1.2.2 skrll 566 1.1.2.2 skrll rf->rf_init = rtw_max2820_init; 567 1.1.2.2 skrll rf->rf_destroy = rtw_max2820_destroy; 568 1.1.2.2 skrll rf->rf_txpower = rtw_max2820_txpower; 569 1.1.2.2 skrll rf->rf_tune = rtw_max2820_tune; 570 1.1.2.2 skrll rf->rf_pwrstate = rtw_max2820_pwrstate; 571 1.1.2.2 skrll bb = &rf->rf_bbpset; 572 1.1.2.2 skrll 573 1.1.2.2 skrll /* XXX magic */ 574 1.1.2.2 skrll bb->bb_antatten = RTW_BBP_ANTATTEN_MAXIM_MAGIC; 575 1.1.2.2 skrll bb->bb_chestlim = 0; 576 1.1.2.2 skrll bb->bb_chsqlim = 159; 577 1.1.2.2 skrll bb->bb_ifagcdet = 100; 578 1.1.2.2 skrll bb->bb_ifagcini = 144; 579 1.1.2.2 skrll bb->bb_ifagclimit = 26; 580 1.1.2.2 skrll bb->bb_lnadet = 248; 581 1.1.2.2 skrll bb->bb_sys1 = 136; 582 1.1.2.2 skrll bb->bb_sys2 = 71; 583 1.1.2.2 skrll bb->bb_sys3 = 155; 584 1.1.2.2 skrll bb->bb_trl = 136; 585 1.1.2.2 skrll bb->bb_txagc = 8; 586 1.1.2.2 skrll 587 1.1.2.2 skrll bus->b_regs = regs; 588 1.1.2.2 skrll bus->b_write = rf_write; 589 1.1.2.2 skrll 590 1.1.2.2 skrll return &mx->mx_rf; 591 1.1.2.2 skrll } 592 1.1.2.2 skrll 593 1.1.2.2 skrll /* freq is in MHz */ 594 1.1.2.2 skrll int 595 1.1.2.2 skrll rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, u_int8_t opaque_txpower, 596 1.1.2.2 skrll u_int8_t cs_threshold, u_int freq, int antdiv, int dflantb, 597 1.1.2.2 skrll enum rtw_pwrstate power) 598 1.1.2.2 skrll { 599 1.1.2.2 skrll int rc; 600 1.1.2.2 skrll RTW_DPRINTF(("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u " 601 1.1.2.2 skrll "pwrstate %s\n", __func__, opaque_txpower, cs_threshold, 602 1.1.2.2 skrll freq, antdiv, dflantb, rtw_pwrstate_string(power))); 603 1.1.2.2 skrll 604 1.1.2.2 skrll /* XXX is this really necessary? */ 605 1.1.2.2 skrll if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) 606 1.1.2.2 skrll return rc; 607 1.1.2.2 skrll if ((rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb, 608 1.1.2.2 skrll freq)) != 0) 609 1.1.2.2 skrll return rc; 610 1.1.2.2 skrll if ((rc = rtw_rf_tune(rf, freq)) != 0) 611 1.1.2.2 skrll return rc; 612 1.1.2.2 skrll /* initialize RF */ 613 1.1.2.2 skrll if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0) 614 1.1.2.2 skrll return rc; 615 1.1.2.2 skrll #if 0 /* what is this redundant tx power setting here for? */ 616 1.1.2.2 skrll if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) 617 1.1.2.2 skrll return rc; 618 1.1.2.2 skrll #endif 619 1.1.2.2 skrll return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb, 620 1.1.2.2 skrll cs_threshold, freq); 621 1.1.2.2 skrll } 622
Indexes created Tue Oct 14 15:09:51 GMT 2025