rtwphy.c revision 1.1.2.2
1 /* $NetBSD: rtwphy.c,v 1.1.2.2 2004/10/19 15:56:56 skrll Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Control the Philips SA2400 RF front-end and the baseband processor 34 * built into the Realtek RTL8180. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: rtwphy.c,v 1.1.2.2 2004/10/19 15:56:56 skrll Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/types.h> 43 44 #include <machine/bus.h> 45 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_ether.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_compat.h> 52 #include <net80211/ieee80211_radiotap.h> 53 54 #include <dev/ic/rtwreg.h> 55 #include <dev/ic/max2820reg.h> 56 #include <dev/ic/sa2400reg.h> 57 #include <dev/ic/rtwvar.h> 58 #include <dev/ic/rtwphyio.h> 59 #include <dev/ic/rtwphy.h> 60 61 static int rtw_max2820_pwrstate(struct rtw_rf *, enum rtw_pwrstate); 62 static int rtw_sa2400_pwrstate(struct rtw_rf *, enum rtw_pwrstate); 63 64 static int 65 rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb, 66 u_int freq) 67 { 68 u_int antatten = antatten0; 69 if (dflantb) 70 antatten |= RTW_BBP_ANTATTEN_DFLANTB; 71 if (freq == 2484) /* channel 14 */ 72 antatten |= RTW_BBP_ANTATTEN_CHAN14; 73 return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten); 74 } 75 76 static int 77 rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv, 78 int dflantb, u_int8_t cs_threshold, u_int freq) 79 { 80 int rc; 81 u_int32_t sys2, sys3; 82 83 sys2 = bb->bb_sys2; 84 if (antdiv) 85 sys2 |= RTW_BBP_SYS2_ANTDIV; 86 sys3 = bb->bb_sys3 | 87 LSHIFT(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK); 88 89 #define RTW_BBP_WRITE_OR_RETURN(reg, val) \ 90 if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \ 91 return rc; 92 93 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1, bb->bb_sys1); 94 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC, bb->bb_txagc); 95 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET, bb->bb_lnadet); 96 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI, bb->bb_ifagcini); 97 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT, bb->bb_ifagclimit); 98 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET, bb->bb_ifagcdet); 99 100 if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0) 101 return rc; 102 103 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL, bb->bb_trl); 104 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2, sys2); 105 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3, sys3); 106 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM, bb->bb_chestlim); 107 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM, bb->bb_chsqlim); 108 return 0; 109 } 110 111 static int 112 rtw_sa2400_txpower(struct rtw_rf *rf, u_int8_t opaque_txpower) 113 { 114 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 115 struct rtw_rfbus *bus = &sa->sa_bus; 116 117 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_TX, 118 opaque_txpower); 119 } 120 121 /* make sure we're using the same settings as the reference driver */ 122 static void 123 verify_syna(u_int freq, u_int32_t val) 124 { 125 u_int32_t expected_val = ~val; 126 127 switch (freq) { 128 case 2412: 129 expected_val = 0x0000096c; /* ch 1 */ 130 break; 131 case 2417: 132 expected_val = 0x00080970; /* ch 2 */ 133 break; 134 case 2422: 135 expected_val = 0x00100974; /* ch 3 */ 136 break; 137 case 2427: 138 expected_val = 0x00180978; /* ch 4 */ 139 break; 140 case 2432: 141 expected_val = 0x00000980; /* ch 5 */ 142 break; 143 case 2437: 144 expected_val = 0x00080984; /* ch 6 */ 145 break; 146 case 2442: 147 expected_val = 0x00100988; /* ch 7 */ 148 break; 149 case 2447: 150 expected_val = 0x0018098c; /* ch 8 */ 151 break; 152 case 2452: 153 expected_val = 0x00000994; /* ch 9 */ 154 break; 155 case 2457: 156 expected_val = 0x00080998; /* ch 10 */ 157 break; 158 case 2462: 159 expected_val = 0x0010099c; /* ch 11 */ 160 break; 161 case 2467: 162 expected_val = 0x001809a0; /* ch 12 */ 163 break; 164 case 2472: 165 expected_val = 0x000009a8; /* ch 13 */ 166 break; 167 case 2484: 168 expected_val = 0x000009b4; /* ch 14 */ 169 break; 170 } 171 KASSERT(val == expected_val); 172 } 173 174 /* freq is in MHz */ 175 static int 176 rtw_sa2400_tune(struct rtw_rf *rf, u_int freq) 177 { 178 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 179 struct rtw_rfbus *bus = &sa->sa_bus; 180 int rc; 181 u_int32_t syna, synb, sync; 182 183 /* XO = 44MHz, R = 11, hence N is in units of XO / R = 4MHz. 184 * 185 * The channel spacing (5MHz) is not divisible by 4MHz, so 186 * we set the fractional part of N to compensate. 187 */ 188 int n = freq / 4, nf = (freq % 4) * 2; 189 190 syna = LSHIFT(nf, SA2400_SYNA_NF_MASK) | LSHIFT(n, SA2400_SYNA_N_MASK); 191 verify_syna(freq, syna); 192 193 /* Divide the 44MHz crystal down to 4MHz. Set the fractional 194 * compensation charge pump value to agree with the fractional 195 * modulus. 196 */ 197 synb = LSHIFT(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL | 198 SA2400_SYNB_ON | SA2400_SYNB_ONE | 199 LSHIFT(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */ 200 201 sync = SA2400_SYNC_CP_NORMAL; 202 203 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNA, 204 syna)) != 0) 205 return rc; 206 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNB, 207 synb)) != 0) 208 return rc; 209 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNC, 210 sync)) != 0) 211 return rc; 212 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYND, 0x0); 213 } 214 215 static int 216 rtw_sa2400_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 217 { 218 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 219 struct rtw_rfbus *bus = &sa->sa_bus; 220 u_int32_t opmode; 221 opmode = SA2400_OPMODE_XO; 222 opmode |= SA2400_OPMODE_RXLV; 223 opmode |= SA2400_OPMODE_CLK; 224 opmode |= SA2400_OPMODE_I0P3; 225 opmode |= LSHIFT(3, SA2400_OPMODE_FILTTUNE_MASK); 226 switch (power) { 227 case RTW_ON: 228 opmode |= SA2400_OPMODE_MODE_TXRX; 229 break; 230 case RTW_SLEEP: 231 opmode |= SA2400_OPMODE_MODE_WAIT; 232 break; 233 case RTW_OFF: 234 opmode |= SA2400_OPMODE_MODE_SLEEP; 235 break; 236 } 237 238 if (sa->sa_digphy) 239 opmode |= SA2400_OPMODE_DIGIN; 240 241 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 242 opmode); 243 } 244 245 static int 246 rtw_sa2400_manrx_init(struct rtw_sa2400 *sa) 247 { 248 u_int32_t manrx; 249 250 /* XXX we are not supposed to be in RXMGC mode when we do 251 * this? 252 */ 253 manrx = SA2400_MANRX_AHSN; 254 manrx |= SA2400_MANRX_TEN; 255 manrx |= LSHIFT(1023, SA2400_MANRX_RXGAIN_MASK); 256 257 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX, 258 manrx); 259 } 260 261 static int 262 rtw_sa2400_vcocal_start(struct rtw_sa2400 *sa, int start) 263 { 264 u_int32_t opmode; 265 266 opmode = SA2400_OPMODE_XO; 267 opmode |= SA2400_OPMODE_RXLV; 268 opmode |= SA2400_OPMODE_CLK; 269 opmode |= SA2400_OPMODE_I0P3; 270 opmode |= LSHIFT(3, SA2400_OPMODE_FILTTUNE_MASK); 271 if (start) 272 opmode |= SA2400_OPMODE_MODE_VCOCALIB; 273 else 274 opmode |= SA2400_OPMODE_MODE_SLEEP; 275 276 if (sa->sa_digphy) 277 opmode |= SA2400_OPMODE_DIGIN; 278 279 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 280 opmode); 281 } 282 283 static int 284 rtw_sa2400_vco_calibration(struct rtw_sa2400 *sa) 285 { 286 int rc; 287 /* calibrate VCO */ 288 if ((rc = rtw_sa2400_vcocal_start(sa, 1)) != 0) 289 return rc; 290 DELAY(2200); /* 2.2 milliseconds */ 291 /* XXX superfluous: SA2400 automatically entered SLEEP mode. */ 292 return rtw_sa2400_vcocal_start(sa, 0); 293 } 294 295 static int 296 rtw_sa2400_filter_calibration(struct rtw_sa2400 *sa) 297 { 298 u_int32_t opmode; 299 300 opmode = SA2400_OPMODE_XO; 301 opmode |= SA2400_OPMODE_RXLV; 302 opmode |= SA2400_OPMODE_CLK; 303 opmode |= SA2400_OPMODE_I0P3; 304 opmode |= LSHIFT(3, SA2400_OPMODE_FILTTUNE_MASK); 305 opmode |= SA2400_OPMODE_MODE_FCALIB; 306 if (sa->sa_digphy) 307 opmode |= SA2400_OPMODE_DIGIN; 308 309 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 310 opmode); 311 } 312 313 static int 314 rtw_sa2400_dc_calibration(struct rtw_sa2400 *sa) 315 { 316 struct rtw_rf *rf = &sa->sa_rf; 317 int rc; 318 u_int32_t dccal; 319 320 (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 1); 321 322 dccal = SA2400_OPMODE_XO; 323 dccal |= SA2400_OPMODE_RXLV; 324 dccal |= SA2400_OPMODE_CLK; 325 dccal |= SA2400_OPMODE_I0P3; 326 dccal |= LSHIFT(3, SA2400_OPMODE_FILTTUNE_MASK); 327 dccal |= SA2400_OPMODE_MODE_TXRX; 328 329 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 330 dccal); 331 if (rc != 0) 332 return rc; 333 334 DELAY(5); /* DCALIB after being in Tx mode for 5 335 * microseconds 336 */ 337 338 dccal &= ~SA2400_OPMODE_MODE_MASK; 339 dccal |= SA2400_OPMODE_MODE_DCALIB; 340 341 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 342 dccal); 343 if (rc != 0) 344 return rc; 345 346 DELAY(20); /* calibration takes at most 20 microseconds */ 347 348 (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 0); 349 350 return 0; 351 } 352 353 static int 354 rtw_sa2400_agc_init(struct rtw_sa2400 *sa) 355 { 356 u_int32_t agc; 357 358 agc = LSHIFT(25, SA2400_AGC_MAXGAIN_MASK); 359 agc |= LSHIFT(7, SA2400_AGC_BBPDELAY_MASK); 360 agc |= LSHIFT(15, SA2400_AGC_LNADELAY_MASK); 361 agc |= LSHIFT(27, SA2400_AGC_RXONDELAY_MASK); 362 363 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC, 364 agc); 365 } 366 367 static void 368 rtw_sa2400_destroy(struct rtw_rf *rf) 369 { 370 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 371 memset(sa, 0, sizeof(*sa)); 372 free(sa, M_DEVBUF); 373 } 374 375 static int 376 rtw_sa2400_init(struct rtw_rf *rf, u_int freq, u_int8_t opaque_txpower, 377 enum rtw_pwrstate power) 378 { 379 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 380 int rc; 381 382 if ((rc = rtw_sa2400_txpower(rf, opaque_txpower)) != 0) 383 return rc; 384 385 /* skip configuration if it's time to sleep or to power-down. */ 386 if (power == RTW_SLEEP || power == RTW_OFF) 387 return rtw_sa2400_pwrstate(rf, power); 388 389 /* go to sleep for configuration */ 390 if ((rc = rtw_sa2400_pwrstate(rf, RTW_SLEEP)) != 0) 391 return rc; 392 393 if ((rc = rtw_sa2400_agc_init(sa)) != 0) 394 return rc; 395 if ((rc = rtw_sa2400_manrx_init(sa)) != 0) 396 return rc; 397 398 /* XXX reference driver calibrates VCO twice. Is it a bug? */ 399 if ((rc = rtw_sa2400_vco_calibration(sa)) != 0) 400 return rc; 401 /* VCO calibration erases synthesizer registers */ 402 if ((rc = rtw_sa2400_tune(rf, freq)) != 0) 403 return rc; 404 if ((rc = rtw_sa2400_filter_calibration(sa)) != 0) 405 return rc; 406 /* analog PHY needs DC calibration */ 407 if (!sa->sa_digphy && (rc = rtw_sa2400_dc_calibration(sa)) != 0) 408 return rc; 409 /* enter Tx/Rx mode */ 410 return rtw_sa2400_pwrstate(rf, power); 411 } 412 413 struct rtw_rf * 414 rtw_sa2400_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy) 415 { 416 struct rtw_sa2400 *sa; 417 struct rtw_rfbus *bus; 418 struct rtw_rf *rf; 419 struct rtw_bbpset *bb; 420 421 sa = malloc(sizeof(*sa), M_DEVBUF, M_NOWAIT | M_ZERO); 422 if (sa == NULL) 423 return NULL; 424 425 sa->sa_digphy = digphy; 426 427 rf = &sa->sa_rf; 428 bus = &sa->sa_bus; 429 430 rf->rf_init = rtw_sa2400_init; 431 rf->rf_destroy = rtw_sa2400_destroy; 432 rf->rf_txpower = rtw_sa2400_txpower; 433 rf->rf_tune = rtw_sa2400_tune; 434 rf->rf_pwrstate = rtw_sa2400_pwrstate; 435 bb = &rf->rf_bbpset; 436 437 /* XXX magic */ 438 bb->bb_antatten = RTW_BBP_ANTATTEN_PHILIPS_MAGIC; 439 bb->bb_chestlim = 0x00; 440 bb->bb_chsqlim = 0xa0; 441 bb->bb_ifagcdet = 0x64; 442 bb->bb_ifagcini = 0x90; 443 bb->bb_ifagclimit = 0x1a; 444 bb->bb_lnadet = 0xe0; 445 bb->bb_sys1 = 0x98; 446 bb->bb_sys2 = 0x47; 447 bb->bb_sys3 = 0x90; 448 bb->bb_trl = 0x88; 449 bb->bb_txagc = 0x38; 450 451 bus->b_regs = regs; 452 bus->b_write = rf_write; 453 454 return &sa->sa_rf; 455 } 456 457 /* freq is in MHz */ 458 static int 459 rtw_max2820_tune(struct rtw_rf *rf, u_int freq) 460 { 461 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 462 struct rtw_rfbus *bus = &mx->mx_bus; 463 464 if (freq < 2400 || freq > 2499) 465 return -1; 466 467 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL, 468 LSHIFT(freq - 2400, MAX2820_CHANNEL_CF_MASK)); 469 } 470 471 static void 472 rtw_max2820_destroy(struct rtw_rf *rf) 473 { 474 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 475 memset(mx, 0, sizeof(*mx)); 476 free(mx, M_DEVBUF); 477 } 478 479 static int 480 rtw_max2820_init(struct rtw_rf *rf, u_int freq, u_int8_t opaque_txpower, 481 enum rtw_pwrstate power) 482 { 483 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 484 struct rtw_rfbus *bus = &mx->mx_bus; 485 int rc; 486 487 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST, 488 MAX2820_TEST_DEFAULT)) != 0) 489 return rc; 490 491 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, 492 MAX2820_ENABLE_DEFAULT)) != 0) 493 return rc; 494 495 /* skip configuration if it's time to sleep or to power-down. */ 496 if ((rc = rtw_max2820_pwrstate(rf, power)) != 0) 497 return rc; 498 else if (power == RTW_OFF || power == RTW_SLEEP) 499 return 0; 500 501 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH, 502 MAX2820_SYNTH_R_44MHZ)) != 0) 503 return rc; 504 505 if ((rc = rtw_max2820_tune(rf, freq)) != 0) 506 return rc; 507 508 /* XXX The MAX2820 datasheet indicates that 1C and 2C should not 509 * be changed from 7, however, the reference driver sets them 510 * to 4 and 1, respectively. 511 */ 512 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE, 513 MAX2820_RECEIVE_DL_DEFAULT | 514 LSHIFT(4, MAX2820A_RECEIVE_1C_MASK) | 515 LSHIFT(1, MAX2820A_RECEIVE_2C_MASK))) != 0) 516 return rc; 517 518 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT, 519 MAX2820_TRANSMIT_PA_DEFAULT); 520 } 521 522 static int 523 rtw_max2820_txpower(struct rtw_rf *rf, u_int8_t opaque_txpower) 524 { 525 /* TBD */ 526 return 0; 527 } 528 529 static int 530 rtw_max2820_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 531 { 532 uint32_t enable; 533 struct rtw_max2820 *mx; 534 struct rtw_rfbus *bus; 535 536 mx = (struct rtw_max2820 *)rf; 537 bus = &mx->mx_bus; 538 539 switch (power) { 540 case RTW_OFF: 541 case RTW_SLEEP: 542 default: 543 enable = 0x0; 544 break; 545 case RTW_ON: 546 enable = MAX2820_ENABLE_DEFAULT; 547 break; 548 } 549 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, enable); 550 } 551 552 struct rtw_rf * 553 rtw_max2820_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int is_a) 554 { 555 struct rtw_max2820 *mx; 556 struct rtw_rfbus *bus; 557 struct rtw_rf *rf; 558 struct rtw_bbpset *bb; 559 560 mx = malloc(sizeof(*mx), M_DEVBUF, M_NOWAIT | M_ZERO); 561 if (mx == NULL) 562 return NULL; 563 564 mx->mx_is_a = is_a; 565 566 rf = &mx->mx_rf; 567 bus = &mx->mx_bus; 568 569 rf->rf_init = rtw_max2820_init; 570 rf->rf_destroy = rtw_max2820_destroy; 571 rf->rf_txpower = rtw_max2820_txpower; 572 rf->rf_tune = rtw_max2820_tune; 573 rf->rf_pwrstate = rtw_max2820_pwrstate; 574 bb = &rf->rf_bbpset; 575 576 /* XXX magic */ 577 bb->bb_antatten = RTW_BBP_ANTATTEN_MAXIM_MAGIC; 578 bb->bb_chestlim = 0; 579 bb->bb_chsqlim = 159; 580 bb->bb_ifagcdet = 100; 581 bb->bb_ifagcini = 144; 582 bb->bb_ifagclimit = 26; 583 bb->bb_lnadet = 248; 584 bb->bb_sys1 = 136; 585 bb->bb_sys2 = 71; 586 bb->bb_sys3 = 155; 587 bb->bb_trl = 136; 588 bb->bb_txagc = 8; 589 590 bus->b_regs = regs; 591 bus->b_write = rf_write; 592 593 return &mx->mx_rf; 594 } 595 596 /* freq is in MHz */ 597 int 598 rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, u_int8_t opaque_txpower, 599 u_int8_t cs_threshold, u_int freq, int antdiv, int dflantb, 600 enum rtw_pwrstate power) 601 { 602 int rc; 603 RTW_DPRINTF(("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u " 604 "pwrstate %s\n", __func__, opaque_txpower, cs_threshold, 605 freq, antdiv, dflantb, rtw_pwrstate_string(power))); 606 607 /* XXX is this really necessary? */ 608 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) 609 return rc; 610 if ((rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb, 611 freq)) != 0) 612 return rc; 613 if ((rc = rtw_rf_tune(rf, freq)) != 0) 614 return rc; 615 /* initialize RF */ 616 if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0) 617 return rc; 618 #if 0 /* what is this redundant tx power setting here for? */ 619 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) 620 return rc; 621 #endif 622 return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb, 623 cs_threshold, freq); 624 } 625
Indexes created Wed Oct 15 07:09:58 GMT 2025