rtwphy.c revision 1.15
1 /* $NetBSD: rtwphy.c,v 1.15 2009/10/19 23:19:39 rmind Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 17 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 19 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 20 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 27 * OF SUCH DAMAGE. 28 */ 29 /* 30 * Control the Philips SA2400 RF front-end and the baseband processor 31 * built into the Realtek RTL8180. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: rtwphy.c,v 1.15 2009/10/19 23:19:39 rmind Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/device.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 #include <net/if_ether.h> 47 48 #include <net80211/ieee80211_netbsd.h> 49 #include <net80211/ieee80211_radiotap.h> 50 #include <net80211/ieee80211_var.h> 51 52 #include <dev/ic/rtwreg.h> 53 #include <dev/ic/max2820reg.h> 54 #include <dev/ic/sa2400reg.h> 55 #include <dev/ic/rtwvar.h> 56 #include <dev/ic/rtwphyio.h> 57 #include <dev/ic/rtwphy.h> 58 59 static int rtw_max2820_pwrstate(struct rtw_rf *, enum rtw_pwrstate); 60 static int rtw_sa2400_pwrstate(struct rtw_rf *, enum rtw_pwrstate); 61 62 #define GCT_WRITE(__gr, __addr, __val, __label) \ 63 do { \ 64 if (rtw_rfbus_write(&(__gr)->gr_bus, RTW_RFCHIPID_GCT, \ 65 (__addr), (__val)) == -1) \ 66 goto __label; \ 67 } while(0) 68 69 static int 70 rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb, 71 u_int freq) 72 { 73 u_int antatten = antatten0; 74 if (dflantb) 75 antatten |= RTW_BBP_ANTATTEN_DFLANTB; 76 if (freq == 2484) /* channel 14 */ 77 antatten |= RTW_BBP_ANTATTEN_CHAN14; 78 return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten); 79 } 80 81 static int 82 rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv, 83 int dflantb, uint8_t cs_threshold, u_int freq) 84 { 85 int rc; 86 uint32_t sys2, sys3; 87 88 sys2 = bb->bb_sys2; 89 if (antdiv) 90 sys2 |= RTW_BBP_SYS2_ANTDIV; 91 sys3 = bb->bb_sys3 | 92 __SHIFTIN(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK); 93 94 #define RTW_BBP_WRITE_OR_RETURN(reg, val) \ 95 if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \ 96 return rc; 97 98 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1, bb->bb_sys1); 99 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC, bb->bb_txagc); 100 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET, bb->bb_lnadet); 101 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI, bb->bb_ifagcini); 102 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT, bb->bb_ifagclimit); 103 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET, bb->bb_ifagcdet); 104 105 if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0) 106 return rc; 107 108 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL, bb->bb_trl); 109 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2, sys2); 110 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3, sys3); 111 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM, bb->bb_chestlim); 112 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM, bb->bb_chsqlim); 113 return 0; 114 } 115 116 static int 117 rtw_sa2400_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) 118 { 119 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 120 struct rtw_rfbus *bus = &sa->sa_bus; 121 122 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_TX, 123 opaque_txpower); 124 } 125 126 /* make sure we're using the same settings as the reference driver */ 127 static void 128 verify_syna(u_int freq, uint32_t val) 129 { 130 uint32_t expected_val = ~val; 131 132 switch (freq) { 133 case 2412: 134 expected_val = 0x0000096c; /* ch 1 */ 135 break; 136 case 2417: 137 expected_val = 0x00080970; /* ch 2 */ 138 break; 139 case 2422: 140 expected_val = 0x00100974; /* ch 3 */ 141 break; 142 case 2427: 143 expected_val = 0x00180978; /* ch 4 */ 144 break; 145 case 2432: 146 expected_val = 0x00000980; /* ch 5 */ 147 break; 148 case 2437: 149 expected_val = 0x00080984; /* ch 6 */ 150 break; 151 case 2442: 152 expected_val = 0x00100988; /* ch 7 */ 153 break; 154 case 2447: 155 expected_val = 0x0018098c; /* ch 8 */ 156 break; 157 case 2452: 158 expected_val = 0x00000994; /* ch 9 */ 159 break; 160 case 2457: 161 expected_val = 0x00080998; /* ch 10 */ 162 break; 163 case 2462: 164 expected_val = 0x0010099c; /* ch 11 */ 165 break; 166 case 2467: 167 expected_val = 0x001809a0; /* ch 12 */ 168 break; 169 case 2472: 170 expected_val = 0x000009a8; /* ch 13 */ 171 break; 172 case 2484: 173 expected_val = 0x000009b4; /* ch 14 */ 174 break; 175 } 176 KASSERT(val == expected_val); 177 } 178 179 /* freq is in MHz */ 180 static int 181 rtw_sa2400_tune(struct rtw_rf *rf, u_int freq) 182 { 183 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 184 struct rtw_rfbus *bus = &sa->sa_bus; 185 int rc; 186 uint32_t syna, synb, sync; 187 188 /* XO = 44MHz, R = 11, hence N is in units of XO / R = 4MHz. 189 * 190 * The channel spacing (5MHz) is not divisible by 4MHz, so 191 * we set the fractional part of N to compensate. 192 */ 193 int n = freq / 4, nf = (freq % 4) * 2; 194 195 syna = __SHIFTIN(nf, SA2400_SYNA_NF_MASK) | __SHIFTIN(n, SA2400_SYNA_N_MASK); 196 verify_syna(freq, syna); 197 198 /* Divide the 44MHz crystal down to 4MHz. Set the fractional 199 * compensation charge pump value to agree with the fractional 200 * modulus. 201 */ 202 synb = __SHIFTIN(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL | 203 SA2400_SYNB_ON | SA2400_SYNB_ONE | 204 __SHIFTIN(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */ 205 206 sync = SA2400_SYNC_CP_NORMAL; 207 208 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNA, 209 syna)) != 0) 210 return rc; 211 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNB, 212 synb)) != 0) 213 return rc; 214 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNC, 215 sync)) != 0) 216 return rc; 217 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYND, 0x0); 218 } 219 220 static int 221 rtw_sa2400_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 222 { 223 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 224 struct rtw_rfbus *bus = &sa->sa_bus; 225 uint32_t opmode; 226 opmode = SA2400_OPMODE_DEFAULTS; 227 switch (power) { 228 case RTW_ON: 229 opmode |= SA2400_OPMODE_MODE_TXRX; 230 break; 231 case RTW_SLEEP: 232 opmode |= SA2400_OPMODE_MODE_WAIT; 233 break; 234 case RTW_OFF: 235 opmode |= SA2400_OPMODE_MODE_SLEEP; 236 break; 237 } 238 239 if (sa->sa_digphy) 240 opmode |= SA2400_OPMODE_DIGIN; 241 242 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 243 opmode); 244 } 245 246 static int 247 rtw_sa2400_manrx_init(struct rtw_sa2400 *sa) 248 { 249 uint32_t manrx; 250 251 /* XXX we are not supposed to be in RXMGC mode when we do 252 * this? 253 */ 254 manrx = SA2400_MANRX_AHSN; 255 manrx |= SA2400_MANRX_TEN; 256 manrx |= __SHIFTIN(1023, SA2400_MANRX_RXGAIN_MASK); 257 258 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX, 259 manrx); 260 } 261 262 static int 263 rtw_sa2400_vcocal_start(struct rtw_sa2400 *sa, int start) 264 { 265 uint32_t opmode; 266 267 opmode = SA2400_OPMODE_DEFAULTS; 268 if (start) 269 opmode |= SA2400_OPMODE_MODE_VCOCALIB; 270 else 271 opmode |= SA2400_OPMODE_MODE_SLEEP; 272 273 if (sa->sa_digphy) 274 opmode |= SA2400_OPMODE_DIGIN; 275 276 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 277 opmode); 278 } 279 280 static int 281 rtw_sa2400_vco_calibration(struct rtw_sa2400 *sa) 282 { 283 int rc; 284 /* calibrate VCO */ 285 if ((rc = rtw_sa2400_vcocal_start(sa, 1)) != 0) 286 return rc; 287 DELAY(2200); /* 2.2 milliseconds */ 288 /* XXX superfluous: SA2400 automatically entered SLEEP mode. */ 289 return rtw_sa2400_vcocal_start(sa, 0); 290 } 291 292 static int 293 rtw_sa2400_filter_calibration(struct rtw_sa2400 *sa) 294 { 295 uint32_t opmode; 296 297 opmode = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_FCALIB; 298 if (sa->sa_digphy) 299 opmode |= SA2400_OPMODE_DIGIN; 300 301 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 302 opmode); 303 } 304 305 static int 306 rtw_sa2400_dc_calibration(struct rtw_sa2400 *sa) 307 { 308 struct rtw_rf *rf = &sa->sa_rf; 309 int rc; 310 uint32_t dccal; 311 312 (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 1); 313 314 dccal = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_TXRX; 315 316 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 317 dccal); 318 if (rc != 0) 319 return rc; 320 321 DELAY(5); /* DCALIB after being in Tx mode for 5 322 * microseconds 323 */ 324 325 dccal &= ~SA2400_OPMODE_MODE_MASK; 326 dccal |= SA2400_OPMODE_MODE_DCALIB; 327 328 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 329 dccal); 330 if (rc != 0) 331 return rc; 332 333 DELAY(20); /* calibration takes at most 20 microseconds */ 334 335 (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 0); 336 337 return 0; 338 } 339 340 static int 341 rtw_sa2400_agc_init(struct rtw_sa2400 *sa) 342 { 343 uint32_t agc; 344 345 agc = __SHIFTIN(25, SA2400_AGC_MAXGAIN_MASK); 346 agc |= __SHIFTIN(7, SA2400_AGC_BBPDELAY_MASK); 347 agc |= __SHIFTIN(15, SA2400_AGC_LNADELAY_MASK); 348 agc |= __SHIFTIN(27, SA2400_AGC_RXONDELAY_MASK); 349 350 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC, 351 agc); 352 } 353 354 static void 355 rtw_sa2400_destroy(struct rtw_rf *rf) 356 { 357 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 358 memset(sa, 0, sizeof(*sa)); 359 free(sa, M_DEVBUF); 360 } 361 362 static int 363 rtw_sa2400_calibrate(struct rtw_rf *rf, u_int freq) 364 { 365 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 366 int i, rc; 367 368 /* XXX reference driver calibrates VCO twice. Is it a bug? */ 369 for (i = 0; i < 2; i++) { 370 if ((rc = rtw_sa2400_vco_calibration(sa)) != 0) 371 return rc; 372 } 373 /* VCO calibration erases synthesizer registers, so re-tune */ 374 if ((rc = rtw_sa2400_tune(rf, freq)) != 0) 375 return rc; 376 if ((rc = rtw_sa2400_filter_calibration(sa)) != 0) 377 return rc; 378 /* analog PHY needs DC calibration */ 379 if (!sa->sa_digphy) 380 return rtw_sa2400_dc_calibration(sa); 381 return 0; 382 } 383 384 static int 385 rtw_sa2400_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, 386 enum rtw_pwrstate power) 387 { 388 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 389 int rc; 390 391 if ((rc = rtw_sa2400_txpower(rf, opaque_txpower)) != 0) 392 return rc; 393 394 /* skip configuration if it's time to sleep or to power-down. */ 395 if (power == RTW_SLEEP || power == RTW_OFF) 396 return rtw_sa2400_pwrstate(rf, power); 397 398 /* go to sleep for configuration */ 399 if ((rc = rtw_sa2400_pwrstate(rf, RTW_SLEEP)) != 0) 400 return rc; 401 402 if ((rc = rtw_sa2400_tune(rf, freq)) != 0) 403 return rc; 404 if ((rc = rtw_sa2400_agc_init(sa)) != 0) 405 return rc; 406 if ((rc = rtw_sa2400_manrx_init(sa)) != 0) 407 return rc; 408 if ((rc = rtw_sa2400_calibrate(rf, freq)) != 0) 409 return rc; 410 411 /* enter Tx/Rx mode */ 412 return rtw_sa2400_pwrstate(rf, power); 413 } 414 415 struct rtw_rf * 416 rtw_sa2400_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy) 417 { 418 struct rtw_sa2400 *sa; 419 struct rtw_rfbus *bus; 420 struct rtw_rf *rf; 421 struct rtw_bbpset *bb; 422 423 sa = malloc(sizeof(*sa), M_DEVBUF, M_NOWAIT | M_ZERO); 424 if (sa == NULL) 425 return NULL; 426 427 sa->sa_digphy = digphy; 428 429 rf = &sa->sa_rf; 430 bus = &sa->sa_bus; 431 432 rf->rf_init = rtw_sa2400_init; 433 rf->rf_destroy = rtw_sa2400_destroy; 434 rf->rf_txpower = rtw_sa2400_txpower; 435 rf->rf_tune = rtw_sa2400_tune; 436 rf->rf_pwrstate = rtw_sa2400_pwrstate; 437 bb = &rf->rf_bbpset; 438 439 /* XXX magic */ 440 bb->bb_antatten = RTW_BBP_ANTATTEN_PHILIPS_MAGIC; 441 bb->bb_chestlim = 0x00; 442 bb->bb_chsqlim = 0xa0; 443 bb->bb_ifagcdet = 0x64; 444 bb->bb_ifagcini = 0x90; 445 bb->bb_ifagclimit = 0x1a; 446 bb->bb_lnadet = 0xe0; 447 bb->bb_sys1 = 0x98; 448 bb->bb_sys2 = 0x47; 449 bb->bb_sys3 = 0x90; 450 bb->bb_trl = 0x88; 451 bb->bb_txagc = 0x38; 452 453 bus->b_regs = regs; 454 bus->b_write = rf_write; 455 456 return &sa->sa_rf; 457 } 458 459 static int 460 rtw_grf5101_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) 461 { 462 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; 463 464 GCT_WRITE(gr, 0x15, 0, err); 465 GCT_WRITE(gr, 0x06, opaque_txpower, err); 466 GCT_WRITE(gr, 0x15, 0x10, err); 467 GCT_WRITE(gr, 0x15, 0x00, err); 468 return 0; 469 err: 470 return -1; 471 } 472 473 static int 474 rtw_grf5101_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 475 { 476 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; 477 switch (power) { 478 case RTW_OFF: 479 case RTW_SLEEP: 480 GCT_WRITE(gr, 0x07, 0x0000, err); 481 GCT_WRITE(gr, 0x1f, 0x0045, err); 482 GCT_WRITE(gr, 0x1f, 0x0005, err); 483 GCT_WRITE(gr, 0x00, 0x08e4, err); 484 default: 485 break; 486 case RTW_ON: 487 GCT_WRITE(gr, 0x1f, 0x0001, err); 488 DELAY(10); 489 GCT_WRITE(gr, 0x1f, 0x0001, err); 490 DELAY(10); 491 GCT_WRITE(gr, 0x1f, 0x0041, err); 492 DELAY(10); 493 GCT_WRITE(gr, 0x1f, 0x0061, err); 494 DELAY(10); 495 GCT_WRITE(gr, 0x00, 0x0ae4, err); 496 DELAY(10); 497 GCT_WRITE(gr, 0x07, 0x1000, err); 498 DELAY(100); 499 break; 500 } 501 502 return 0; 503 err: 504 return -1; 505 } 506 507 static int 508 rtw_grf5101_tune(struct rtw_rf *rf, u_int freq) 509 { 510 int channel; 511 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; 512 513 if (freq == 2484) 514 channel = 14; 515 else if ((channel = (freq - 2412) / 5 + 1) < 1 || channel > 13) { 516 RTW_DPRINTF(RTW_DEBUG_PHY, 517 ("%s: invalid channel %d (freq %d)\n", __func__, channel, 518 freq)); 519 return -1; 520 } 521 522 GCT_WRITE(gr, 0x07, 0, err); 523 GCT_WRITE(gr, 0x0b, channel - 1, err); 524 GCT_WRITE(gr, 0x07, 0x1000, err); 525 return 0; 526 err: 527 return -1; 528 } 529 530 static int 531 rtw_grf5101_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, 532 enum rtw_pwrstate power) 533 { 534 int rc; 535 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; 536 537 /* 538 * These values have been derived from the rtl8180-sa2400 539 * Linux driver. It is unknown what they all do, GCT refuse 540 * to release any documentation so these are more than 541 * likely sub optimal settings 542 */ 543 544 GCT_WRITE(gr, 0x01, 0x1a23, err); 545 GCT_WRITE(gr, 0x02, 0x4971, err); 546 GCT_WRITE(gr, 0x03, 0x41de, err); 547 GCT_WRITE(gr, 0x04, 0x2d80, err); 548 549 GCT_WRITE(gr, 0x05, 0x61ff, err); 550 551 GCT_WRITE(gr, 0x06, 0x0, err); 552 553 GCT_WRITE(gr, 0x08, 0x7533, err); 554 GCT_WRITE(gr, 0x09, 0xc401, err); 555 GCT_WRITE(gr, 0x0a, 0x0, err); 556 GCT_WRITE(gr, 0x0c, 0x1c7, err); 557 GCT_WRITE(gr, 0x0d, 0x29d3, err); 558 GCT_WRITE(gr, 0x0e, 0x2e8, err); 559 GCT_WRITE(gr, 0x10, 0x192, err); 560 GCT_WRITE(gr, 0x11, 0x248, err); 561 GCT_WRITE(gr, 0x12, 0x0, err); 562 GCT_WRITE(gr, 0x13, 0x20c4, err); 563 GCT_WRITE(gr, 0x14, 0xf4fc, err); 564 GCT_WRITE(gr, 0x15, 0x0, err); 565 GCT_WRITE(gr, 0x16, 0x1500, err); 566 567 if ((rc = rtw_grf5101_txpower(rf, opaque_txpower)) != 0) 568 return rc; 569 570 if ((rc = rtw_grf5101_tune(rf, freq)) != 0) 571 return rc; 572 573 return 0; 574 err: 575 return -1; 576 } 577 578 static void 579 rtw_grf5101_destroy(struct rtw_rf *rf) 580 { 581 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; 582 memset(gr, 0, sizeof(*gr)); 583 free(gr, M_DEVBUF); 584 } 585 586 struct rtw_rf * 587 rtw_grf5101_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, 588 int digphy) 589 { 590 struct rtw_grf5101 *gr; 591 struct rtw_rfbus *bus; 592 struct rtw_rf *rf; 593 struct rtw_bbpset *bb; 594 595 gr = malloc(sizeof(*gr), M_DEVBUF, M_NOWAIT | M_ZERO); 596 if (gr == NULL) 597 return NULL; 598 599 rf = &gr->gr_rf; 600 bus = &gr->gr_bus; 601 602 rf->rf_init = rtw_grf5101_init; 603 rf->rf_destroy = rtw_grf5101_destroy; 604 rf->rf_txpower = rtw_grf5101_txpower; 605 rf->rf_tune = rtw_grf5101_tune; 606 rf->rf_pwrstate = rtw_grf5101_pwrstate; 607 bb = &rf->rf_bbpset; 608 609 /* XXX magic */ 610 bb->bb_antatten = RTW_BBP_ANTATTEN_GCT_MAGIC; 611 bb->bb_chestlim = 0x00; 612 bb->bb_chsqlim = 0xa0; 613 bb->bb_ifagcdet = 0x64; 614 bb->bb_ifagcini = 0x90; 615 bb->bb_ifagclimit = 0x1e; 616 bb->bb_lnadet = 0xc0; 617 bb->bb_sys1 = 0xa8; 618 bb->bb_sys2 = 0x47; 619 bb->bb_sys3 = 0x9b; 620 bb->bb_trl = 0x88; 621 bb->bb_txagc = 0x08; 622 623 bus->b_regs = regs; 624 bus->b_write = rf_write; 625 626 return &gr->gr_rf; 627 } 628 629 /* freq is in MHz */ 630 static int 631 rtw_max2820_tune(struct rtw_rf *rf, u_int freq) 632 { 633 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 634 struct rtw_rfbus *bus = &mx->mx_bus; 635 636 if (freq < 2400 || freq > 2499) 637 return -1; 638 639 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL, 640 __SHIFTIN(freq - 2400, MAX2820_CHANNEL_CF_MASK)); 641 } 642 643 static void 644 rtw_max2820_destroy(struct rtw_rf *rf) 645 { 646 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 647 memset(mx, 0, sizeof(*mx)); 648 free(mx, M_DEVBUF); 649 } 650 651 static int 652 rtw_max2820_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, 653 enum rtw_pwrstate power) 654 { 655 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 656 struct rtw_rfbus *bus = &mx->mx_bus; 657 int rc; 658 659 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST, 660 MAX2820_TEST_DEFAULT)) != 0) 661 return rc; 662 663 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, 664 MAX2820_ENABLE_DEFAULT)) != 0) 665 return rc; 666 667 /* skip configuration if it's time to sleep or to power-down. */ 668 if ((rc = rtw_max2820_pwrstate(rf, power)) != 0) 669 return rc; 670 else if (power == RTW_OFF || power == RTW_SLEEP) 671 return 0; 672 673 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH, 674 MAX2820_SYNTH_R_44MHZ)) != 0) 675 return rc; 676 677 if ((rc = rtw_max2820_tune(rf, freq)) != 0) 678 return rc; 679 680 /* XXX The MAX2820 datasheet indicates that 1C and 2C should not 681 * be changed from 7, however, the reference driver sets them 682 * to 4 and 1, respectively. 683 */ 684 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE, 685 MAX2820_RECEIVE_DL_DEFAULT | 686 __SHIFTIN(4, MAX2820A_RECEIVE_1C_MASK) | 687 __SHIFTIN(1, MAX2820A_RECEIVE_2C_MASK))) != 0) 688 return rc; 689 690 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT, 691 MAX2820_TRANSMIT_PA_DEFAULT); 692 } 693 694 static int 695 rtw_max2820_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) 696 { 697 /* TBD */ 698 return 0; 699 } 700 701 static int 702 rtw_max2820_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 703 { 704 uint32_t enable; 705 struct rtw_max2820 *mx; 706 struct rtw_rfbus *bus; 707 708 mx = (struct rtw_max2820 *)rf; 709 bus = &mx->mx_bus; 710 711 switch (power) { 712 case RTW_OFF: 713 case RTW_SLEEP: 714 default: 715 enable = 0x0; 716 break; 717 case RTW_ON: 718 enable = MAX2820_ENABLE_DEFAULT; 719 break; 720 } 721 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, enable); 722 } 723 724 struct rtw_rf * 725 rtw_max2820_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int is_a) 726 { 727 struct rtw_max2820 *mx; 728 struct rtw_rfbus *bus; 729 struct rtw_rf *rf; 730 struct rtw_bbpset *bb; 731 732 mx = malloc(sizeof(*mx), M_DEVBUF, M_NOWAIT | M_ZERO); 733 if (mx == NULL) 734 return NULL; 735 736 mx->mx_is_a = is_a; 737 738 rf = &mx->mx_rf; 739 bus = &mx->mx_bus; 740 741 rf->rf_init = rtw_max2820_init; 742 rf->rf_destroy = rtw_max2820_destroy; 743 rf->rf_txpower = rtw_max2820_txpower; 744 rf->rf_tune = rtw_max2820_tune; 745 rf->rf_pwrstate = rtw_max2820_pwrstate; 746 bb = &rf->rf_bbpset; 747 748 /* XXX magic */ 749 bb->bb_antatten = RTW_BBP_ANTATTEN_MAXIM_MAGIC; 750 bb->bb_chestlim = 0; 751 bb->bb_chsqlim = 159; 752 bb->bb_ifagcdet = 100; 753 bb->bb_ifagcini = 144; 754 bb->bb_ifagclimit = 26; 755 bb->bb_lnadet = 248; 756 bb->bb_sys1 = 136; 757 bb->bb_sys2 = 71; 758 bb->bb_sys3 = 155; 759 bb->bb_trl = 136; 760 bb->bb_txagc = 8; 761 762 bus->b_regs = regs; 763 bus->b_write = rf_write; 764 765 return &mx->mx_rf; 766 } 767 768 /* freq is in MHz */ 769 int 770 rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, uint8_t opaque_txpower, 771 uint8_t cs_threshold, u_int freq, int antdiv, int dflantb, 772 enum rtw_pwrstate power) 773 { 774 int rc; 775 RTW_DPRINTF(RTW_DEBUG_PHY, 776 ("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u " 777 "pwrstate %s\n", __func__, opaque_txpower, cs_threshold, freq, 778 antdiv, dflantb, rtw_pwrstate_string(power))); 779 780 /* XXX is this really necessary? */ 781 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) 782 return rc; 783 if ((rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb, 784 freq)) != 0) 785 return rc; 786 if ((rc = rtw_rf_tune(rf, freq)) != 0) 787 return rc; 788 /* initialize RF */ 789 if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0) 790 return rc; 791 #if 0 /* what is this redundant tx power setting here for? */ 792 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) 793 return rc; 794 #endif 795 return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb, 796 cs_threshold, freq); 797 } 798
Indexes created Mon Oct 13 14:09:54 GMT 2025