rtwreg.h revision 1.1
1 /* $NetBSD: rtwreg.h,v 1.1 2004/09/26 02:29:15 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* Macros for bit twiddling. */ 35 /* TBD factor w/ dev/ic/atwreg.h. */ 36 37 #ifndef _BIT_TWIDDLE 38 #define _BIT_TWIDDLE 39 /* nth bit, BIT(0) == 0x1. */ 40 #define BIT(n) (((n) == 32) ? 0 : ((u_int32_t)1 << (n))) 41 42 /* bits m through n, m < n. */ 43 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 44 45 /* find least significant bit that is set */ 46 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 47 48 /* for x a power of two and p a non-negative integer, is x a greater 49 * power than 2**p? 50 */ 51 #define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 52 53 #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 54 55 #define MASK_TO_SHIFT4(m) \ 56 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 57 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 58 : MASK_TO_SHIFT2((m))) 59 60 #define MASK_TO_SHIFT8(m) \ 61 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 62 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 63 : MASK_TO_SHIFT4((m))) 64 65 #define MASK_TO_SHIFT16(m) \ 66 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 67 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 68 : MASK_TO_SHIFT8((m))) 69 70 #define MASK_TO_SHIFT(m) \ 71 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 72 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 73 : MASK_TO_SHIFT16((m))) 74 75 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 76 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 77 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 78 #define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 79 80 #endif /* _BIT_TWIDDLE */ 81 82 /* RTL8180L Host Control and Status Registers */ 83 84 #define RTW_IDR0 0x00 /* ID Register: MAC addr, 6 bytes. 85 * Auto-loaded from EEPROM. Read by byte, 86 * by word, or by double word, but write 87 * only by double word. 88 */ 89 #define RTW_IDR1 0x04 90 91 #define RTW_MAR0 0x08 /* Multicast filter, 64b. */ 92 #define RTW_MAR1 0x0c 93 94 #define RTW_TSFTRL 0x18 /* Timing Synchronization Function Timer 95 * Register, low word, 32b, read-only. 96 */ 97 #define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */ 98 #define RTW_TLPDA 0x20 /* Transmit Low Priority Descriptors Start 99 * Address, 32b, 256-byte alignment. 100 */ 101 #define RTW_TNPDA 0x24 /* Transmit Normal Priority Descriptors Start 102 * Address, 32b, 256-byte alignment. 103 */ 104 #define RTW_THPDA 0x28 /* Transmit High Priority Descriptors Start 105 * Address, 32b, 256-byte alignment. 106 */ 107 108 #define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */ 109 #define RTW_BRSR_BPLCP BIT(8) /* 1: use short PLCP header for CTS/ACK packet, 110 * 0: use long PLCP header 111 */ 112 #define RTW_BRSR_MBR8180_MASK BITS(1,0) /* Maximum Basic Service Rate */ 113 #define RTW_BRSR_MBR8180_1MBPS LSHIFT(0, RTW_BRSR_MBR_MASK) 114 #define RTW_BRSR_MBR8180_2MBPS LSHIFT(1, RTW_BRSR_MBR_MASK) 115 #define RTW_BRSR_MBR8180_5MBPS LSHIFT(2, RTW_BRSR_MBR_MASK) 116 #define RTW_BRSR_MBR8180_11MBPS LSHIFT(3, RTW_BRSR_MBR_MASK) 117 118 /* 8181 and 8180 docs conflict! */ 119 #define RTW_BRSR_MBR8181_1MBPS BIT(0) 120 #define RTW_BRSR_MBR8181_2MBPS BIT(1) 121 #define RTW_BRSR_MBR8181_5MBPS BIT(2) 122 #define RTW_BRSR_MBR8181_11MBPS BIT(3) 123 124 /* BSSID, 6 bytes */ 125 #define RTW_BSSID16 0x2e /* first two bytes */ 126 #define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */ 127 #define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */ 128 #define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */ 129 #define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */ 130 #define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */ 131 #define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */ 132 #define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */ 133 134 #define RTW_CR 0x37 /* Command Register, 8b */ 135 #define RTW_CR_RST BIT(4) /* Reset: host sets to 1 to disable 136 * transmitter & receiver, reinitialize FIFO. 137 * RTL8180L sets to 0 to signal completion. 138 */ 139 #define RTW_CR_RE BIT(3) /* Receiver Enable: host enables receiver 140 * by writing 1. RTL8180L indicates receiver 141 * is active with 1. After power-up, host 142 * must wait for reset before writing. 143 */ 144 #define RTW_CR_TE BIT(2) /* Transmitter Enable: host enables transmitter 145 * by writing 1. RTL8180L indicates transmitter 146 * is active with 1. After power-up, host 147 * must wait for reset before writing. 148 */ 149 #define RTW_CR_MULRW BIT(0) /* PCI Multiple Read/Write enable: 1 enables, 150 * 0 disables. XXX RTL8180, only? 151 */ 152 153 #define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */ 154 #define RTW_ISR 0x3e /* Interrupt status register, 16b */ 155 156 #define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO Overflow */ 157 #define RTW_INTR_TIMEOUT BIT(14) /* Time Out: 1 indicates 158 * RTW_TSFTR[0:31] = RTW_TINT 159 */ 160 #define RTW_INTR_BCNINT BIT(13) /* Beacon Time Out: time for host to 161 * prepare beacon: 162 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 163 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV) 164 */ 165 #define RTW_INTR_ATIMINT BIT(12) 166 /* ATIM Time Out: ATIM interval will pass, 167 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 168 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV) 169 */ 170 #define RTW_INTR_TBDER BIT(11) /* Tx Beacon Descriptor Error: 171 * beacon transmission aborted because 172 * frame Rx'd 173 */ 174 #define RTW_INTR_TBDOK BIT(10) /* Tx Beacon Descriptor OK */ 175 #define RTW_INTR_THPDER BIT(9) /* Tx High Priority Descriptor Error: 176 * reached short/long retry limit 177 */ 178 #define RTW_INTR_THPDOK BIT(8) /* Tx High Priority Descriptor OK */ 179 #define RTW_INTR_TNPDER BIT(7) /* Tx Normal Priority Descriptor Error: 180 * reached short/long retry limit 181 */ 182 #define RTW_INTR_TNPDOK BIT(6) /* Tx Normal Priority Descriptor OK */ 183 #define RTW_INTR_RXFOVW BIT(5) /* Rx FIFO Overflow: either RDU (see below) 184 * or PCI bus too slow/busy 185 */ 186 #define RTW_INTR_RDU BIT(4) /* Rx Descriptor Unavailable */ 187 #define RTW_INTR_TLPDER BIT(3) /* Tx Normal Priority Descriptor Error 188 * reached short/long retry limit 189 */ 190 #define RTW_INTR_TLPDOK BIT(2) /* Tx Normal Priority Descriptor OK */ 191 #define RTW_INTR_RER BIT(1) /* Rx Error: CRC32 or ICV error */ 192 #define RTW_INTR_ROK BIT(0) /* Rx OK */ 193 194 /* Convenient interrupt conjunctions. */ 195 #define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK) 196 #define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\ 197 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK) 198 #define RTW_INTR_BEACON (RTW_INTR_TBDER|RTW_INTR_TBDOK|RTW_INTR_BCNINT) 199 #define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU) 200 201 #define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */ 202 #define RTW_TCR_CWMIN BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */ 203 #define RTW_TCR_SWSEQ BIT(30) /* 1: host assigns 802.11 sequence number, 204 * 0: hardware assigns sequence number 205 */ 206 /* Hardware version ID, read-only */ 207 #define RTW_TCR_HWVERID_MASK BITS(29, 25) 208 #define RTW_TCR_HWVERID_D LSHIFT(26, RTW_TCR_HWVERID_MASK) 209 #define RTW_TCR_HWVERID_F LSHIFT(27, RTW_TCR_HWVERID_MASK) 210 #define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F 211 212 /* Set ACK/CTS Timeout (EIFS). 213 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?) 214 * 0: ACK rate = 1Mbps 215 */ 216 #define RTW_TCR_SAT BIT(24) 217 /* Max DMA Burst Size per Tx DMA Burst */ 218 #define RTW_TCR_MXDMA_MASK BITS(23,21) 219 #define RTW_TCR_MXDMA_16 LSHIFT(0, RTW_TCR_MXDMA_MASK) 220 #define RTW_TCR_MXDMA_32 LSHIFT(1, RTW_TCR_MXDMA_MASK) 221 #define RTW_TCR_MXDMA_64 LSHIFT(2, RTW_TCR_MXDMA_MASK) 222 #define RTW_TCR_MXDMA_128 LSHIFT(3, RTW_TCR_MXDMA_MASK) 223 #define RTW_TCR_MXDMA_256 LSHIFT(4, RTW_TCR_MXDMA_MASK) 224 #define RTW_TCR_MXDMA_512 LSHIFT(5, RTW_TCR_MXDMA_MASK) 225 #define RTW_TCR_MXDMA_1024 LSHIFT(6, RTW_TCR_MXDMA_MASK) 226 #define RTW_TCR_MXDMA_2048 LSHIFT(7, RTW_TCR_MXDMA_MASK) 227 228 #define RTW_TCR_DISCW BIT(20) /* disable 802.11 random backoff */ 229 230 #define RTW_TCR_ICV BIT(19) /* host lets RTL8180 append ICV to 231 * WEP packets 232 */ 233 234 /* Loopback Test: disables TXI/TXQ outputs. */ 235 #define RTW_TCR_LBK_MASK BITS(18,17) 236 #define RTW_TCR_LBK_NORMAL LSHIFT(0, RTW_TCR_LBK_MASK) /* normal ops */ 237 #define RTW_TCR_LBK_MAC LSHIFT(1, RTW_TCR_LBK_MASK) /* MAC loopback */ 238 #define RTW_TCR_LBK_BBP LSHIFT(2, RTW_TCR_LBK_MASK) /* baseband loop. */ 239 #define RTW_TCR_LBK_CONT LSHIFT(3, RTW_TCR_LBK_MASK) /* continuous Tx */ 240 241 #define RTW_TCR_CRC BIT(16) /* host lets RTL8180 append CRC32 */ 242 #define RTW_TCR_SRL_MASK BITS(15,8) /* Short Retry Limit */ 243 #define RTW_TCR_LRL_MASK BITS(7,0) /* Long Retry Limit */ 244 245 #define RTW_RCR 0x44 /* Receive Configuration Register, 32b */ 246 #define RTW_RCR_ONLYERLPKT BIT(31) /* only do Early Rx on packets 247 * longer than 1536 bytes 248 */ 249 #define RTW_RCR_ENCS2 BIT(30) /* enable carrier sense method 2 */ 250 #define RTW_RCR_ENCS1 BIT(29) /* enable carrier sense method 1 */ 251 #define RTW_RCR_ENMARP BIT(28) /* enable MAC auto-reset PHY */ 252 #define RTW_RCR_CBSSID BIT(23) /* Check BSSID/ToDS/FromDS: set 253 * "Link On" when received BSSID 254 * matches RTW_BSSID and received 255 * ToDS/FromDS are appropriate 256 * according to RTW_MSR_NETYPE. 257 */ 258 #define RTW_RCR_APWRMGT BIT(22) /* accept packets w/ PWRMGMT bit set */ 259 #define RTW_RCR_ADD3 BIT(21) /* when RTW_MSR_NETYPE == 260 * RTW_MSR_NETYPE_INFRA_OK, accept 261 * broadcast/multicast packets whose 262 * 3rd address matches RTL8180's MAC. 263 */ 264 #define RTW_RCR_AMF BIT(20) /* accept management frames */ 265 #define RTW_RCR_ACF BIT(19) /* accept control frames */ 266 #define RTW_RCR_ADF BIT(18) /* accept data frames */ 267 /* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data 268 * bytes are received 269 */ 270 #define RTW_RCR_RXFTH_MASK BITS(15,13) 271 #define RTW_RCR_RXFTH_64 LSHIFT(2, RTW_RCR_RXFTH_MASK) 272 #define RTW_RCR_RXFTH_128 LSHIFT(3, RTW_RCR_RXFTH_MASK) 273 #define RTW_RCR_RXFTH_256 LSHIFT(4, RTW_RCR_RXFTH_MASK) 274 #define RTW_RCR_RXFTH_512 LSHIFT(5, RTW_RCR_RXFTH_MASK) 275 #define RTW_RCR_RXFTH_1024 LSHIFT(6, RTW_RCR_RXFTH_MASK) 276 #define RTW_RCR_RXFTH_WHOLE LSHIFT(7, RTW_RCR_RXFTH_MASK) 277 278 #define RTW_RCR_AICV BIT(12) /* accept frames w/ ICV errors */ 279 280 /* Max DMA Burst Size per Rx DMA Burst */ 281 #define RTW_RCR_MXDMA_MASK BITS(10,8) 282 #define RTW_RCR_MXDMA_16 LSHIFT(0, RTW_RCR_MXDMA_MASK) 283 #define RTW_RCR_MXDMA_32 LSHIFT(1, RTW_RCR_MXDMA_MASK) 284 #define RTW_RCR_MXDMA_64 LSHIFT(2, RTW_RCR_MXDMA_MASK) 285 #define RTW_RCR_MXDMA_128 LSHIFT(3, RTW_RCR_MXDMA_MASK) 286 #define RTW_RCR_MXDMA_256 LSHIFT(4, RTW_RCR_MXDMA_MASK) 287 #define RTW_RCR_MXDMA_512 LSHIFT(5, RTW_RCR_MXDMA_MASK) 288 #define RTW_RCR_MXDMA_1024 LSHIFT(6, RTW_RCR_MXDMA_MASK) 289 #define RTW_RCR_MXDMA_UNLIMITED LSHIFT(7, RTW_RCR_MXDMA_MASK) 290 291 /* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */ 292 #define RTW_RCR_9356SEL BIT(6) 293 294 #define RTW_RCR_ACRC32 BIT(5) /* accept frames w/ CRC32 errors */ 295 #define RTW_RCR_AB BIT(3) /* accept broadcast frames */ 296 #define RTW_RCR_AM BIT(2) /* accept multicast frames */ 297 /* accept physical match frames. XXX means PLCP header ok? */ 298 #define RTW_RCR_APM BIT(1) 299 #define RTW_RCR_AAP BIT(0) /* accept frames w/ destination */ 300 301 #define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */ 302 #define RTW_TBDA 0x4c /* Transmit Beacon Descriptor Start Address, 303 * 32b, 256-byte alignment 304 */ 305 #define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */ 306 #define RTW_9346CR_EEM_MASK BITS(7,6) /* Operating Mode */ 307 #define RTW_9346CR_EEM_NORMAL LSHIFT(0, RTW_9346CR_EEM_MASK) 308 /* Load the EEPROM. Reset registers to defaults. 309 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL. 310 * XXX RTL8180 only? 311 */ 312 #define RTW_9346CR_EEM_AUTOLOAD LSHIFT(1, RTW_9346CR_EEM_MASK) 313 /* Disable network & bus-master operations and enable 314 * _EECS, _EESK, _EEDI, _EEDO. 315 * XXX RTL8180 only? 316 */ 317 #define RTW_9346CR_EEM_PROGRAM LSHIFT(2, RTW_9346CR_EEM_MASK) 318 /* Enable RTW_CONFIG[0123] registers. */ 319 #define RTW_9346CR_EEM_CONFIG LSHIFT(3, RTW_9346CR_EEM_MASK) 320 /* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes. 321 * XXX RTL8180 only? 322 */ 323 #define RTW_9346CR_EECS BIT(3) 324 #define RTW_9346CR_EESK BIT(2) 325 #define RTW_9346CR_EEDI BIT(1) 326 #define RTW_9346CR_EEDO BIT(0) /* read-only */ 327 328 #define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */ 329 #define RTW_CONFIG0_WEP40 BIT(7) /* implements 40-bit WEP, 330 * XXX RTL8180 only? 331 */ 332 #define RTW_CONFIG0_WEP104 BIT(6) /* implements 104-bit WEP, 333 * from EEPROM, read-only 334 * XXX RTL8180 only? 335 */ 336 #define RTW_CONFIG0_LEDGPOEN BIT(4) /* 1: RTW_PSR_LEDGPO[01] control 337 * LED[01] pins. 338 * 0: LED behavior defined by 339 * RTW_CONFIG1_LEDS10_MASK 340 * XXX RTL8180 only? 341 */ 342 /* auxiliary power is present, read-only */ 343 #define RTW_CONFIG0_AUXPWR BIT(3) 344 /* Geographic Location, read-only */ 345 #define RTW_CONFIG0_GL_MASK BITS(1,0) 346 /* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_* 347 * work. 348 */ 349 #define _RTW_CONFIG0_GL_USA LSHIFT(3, RTW_CONFIG0_GL_MASK) 350 #define RTW_CONFIG0_GL_EUROPE LSHIFT(2, RTW_CONFIG0_GL_MASK) 351 #define RTW_CONFIG0_GL_JAPAN LSHIFT(1, RTW_CONFIG0_GL_MASK) 352 #define RTW_CONFIG0_GL_USA LSHIFT(0, RTW_CONFIG0_GL_MASK) 353 /* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */ 354 355 #define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */ 356 357 /* LED configuration. From EEPROM. Read/write. 358 * 359 * Setting LED0 LED1 360 * ------- ---- ---- 361 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure 362 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link 363 * RTW_CONFIG1_LEDS_TX_RX Tx Rx 364 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure 365 */ 366 #define RTW_CONFIG1_LEDS_MASK BITS(7,6) 367 #define RTW_CONFIG1_LEDS_ACT_INFRA LSHIFT(0, RTW_CONFIG1_LEDS_MASK) 368 #define RTW_CONFIG1_LEDS_ACT_LINK LSHIFT(1, RTW_CONFIG1_LEDS_MASK) 369 #define RTW_CONFIG1_LEDS_TX_RX LSHIFT(2, RTW_CONFIG1_LEDS_MASK) 370 #define RTW_CONFIG1_LEDS_LINKACT_INFRA LSHIFT(3, RTW_CONFIG1_LEDS_MASK) 371 372 /* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms. 373 * 374 * RTW_CONFIG1_LWACT 375 * 0 1 376 * RTW_CONFIG4_LWPTN 0 active high active low 377 * 1 positive pulse negative pulse 378 */ 379 #define RTW_CONFIG1_LWACT BIT(4) 380 381 #define RTW_CONFIG1_MEMMAP BIT(3) /* using PCI memory space, read-only */ 382 #define RTW_CONFIG1_IOMAP BIT(2) /* using PCI I/O space, read-only */ 383 #define RTW_CONFIG1_VPD BIT(1) /* if set, VPD from offsets 384 * 0x40-0x7f in EEPROM are at 385 * registers 0x60-0x67 of PCI 386 * Configuration Space (XXX huh?) 387 */ 388 #define RTW_CONFIG1_PMEN BIT(0) /* Power Management Enable: TBD */ 389 390 #define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */ 391 #define RTW_CONFIG2_LCK BIT(7) /* clocks are locked, read-only: 392 * Tx frequency & symbol clocks 393 * are derived from the same OSC 394 */ 395 #define RTW_CONFIG2_ANT BIT(6) /* diversity enabled, read-only */ 396 #define RTW_CONFIG2_DPS BIT(3) /* Descriptor Polling State: enable 397 * test mode. 398 */ 399 #define RTW_CONFIG2_PAPESIGN BIT(2) /* TBD, from EEPROM */ 400 #define RTW_CONFIG2_PAPETIME_MASK BITS(1,0) /* TBD, from EEPROM */ 401 402 #define RTW_ANAPARM 0x54 /* Analog parameter, 32b */ 403 #define RTW_ANAPARM_RFPOW0_MASK BITS(30,28) /* undocumented bits 404 * which appear to 405 * control the power 406 * state of the RF 407 * components 408 */ 409 #define RTW_ANAPARM_RFPOW0_RFMD_ON LSHIFT(0x4, RTW_ANAPARM_RFPOW0_MASK) 410 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 411 #define RTW_ANAPARM_RFPOW0_RFMD_SLEEP LSHIFT(0x3, RTW_ANAPARM_RFPOW0_MASK) 412 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 413 #define RTW_ANAPARM_RFPOW0_RFMD_OFF LSHIFT(0x3, RTW_ANAPARM_RFPOW0_MASK) 414 415 #define RTW_ANAPARM_RFPOW0_PHILIPS_ON LSHIFT(0x3, RTW_ANAPARM_RFPOW0_MASK) 416 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 417 #define RTW_ANAPARM_RFPOW0_PHILIPS_SLEEP\ 418 LSHIFT(0x3, RTW_ANAPARM_RFPOW0_MASK) 419 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 420 #define RTW_ANAPARM_RFPOW0_PHILIPS_OFF\ 421 LSHIFT(0x3, RTW_ANAPARM_RFPOW0_MASK) 422 423 #define RTW_ANAPARM_TXDACOFF BIT(27) /* 1: disable Tx DAC, 424 * 0: enable 425 */ 426 #define RTW_ANAPARM_RFPOW1_MASK BITS(26,20) /* undocumented bits 427 * which appear to 428 * control the power 429 * state of the RF 430 * components 431 */ 432 #define RTW_ANAPARM_RFPOW1_RFMD_ON LSHIFT(0x8, RTW_ANAPARM_RFPOW1_MASK) 433 #define RTW_ANAPARM_RFPOW1_RFMD_SLEEP LSHIFT(0x78, RTW_ANAPARM_RFPOW1_MASK) 434 #define RTW_ANAPARM_RFPOW1_RFMD_OFF LSHIFT(0x79, RTW_ANAPARM_RFPOW1_MASK) 435 436 #define RTW_ANAPARM_RFPOW1_PHILIPS_ON LSHIFT(0x28, RTW_ANAPARM_RFPOW1_MASK) 437 #define RTW_ANAPARM_RFPOW1_PHILIPS_SLEEP\ 438 LSHIFT(0x78, RTW_ANAPARM_RFPOW1_MASK) 439 #define RTW_ANAPARM_RFPOW1_PHILIPS_OFF\ 440 LSHIFT(0x79, RTW_ANAPARM_RFPOW1_MASK) 441 442 #define RTW_ANAPARM_CARDSP_MASK BITS(19,0) /* undocumented 443 * card-specific 444 * bits from the 445 * EEPROM. 446 */ 447 448 #define RTW_MSR 0x58 /* Media Status Register, 8b */ 449 /* Network Type and Link Status */ 450 #define RTW_MSR_NETYPE_MASK BITS(3,2) 451 /* AP, XXX RTL8181 only? */ 452 #define RTW_MSR_NETYPE_AP_OK LSHIFT(3, RTW_MSR_NETYPE_MASK) 453 /* infrastructure link ok */ 454 #define RTW_MSR_NETYPE_INFRA_OK LSHIFT(2, RTW_MSR_NETYPE_MASK) 455 /* ad-hoc link ok */ 456 #define RTW_MSR_NETYPE_ADHOC_OK LSHIFT(1, RTW_MSR_NETYPE_MASK) 457 /* no link */ 458 #define RTW_MSR_NETYPE_NOLINK LSHIFT(0, RTW_MSR_NETYPE_MASK) 459 460 #define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */ 461 #define RTW_CONFIG3_GNTSEL BIT(7) /* Grant Select, read-only */ 462 #define RTW_CONFIG3_PARMEN BIT(6) /* Set RTW_CONFIG3_PARMEN and 463 * RTW_9346CR_EEM_CONFIG to 464 * allow RTW_ANAPARM writes. 465 */ 466 #define RTW_CONFIG3_MAGIC BIT(5) /* Valid when RTW_CONFIG1_PMEN is 467 * set. If set, RTL8180 wakes up 468 * OS when Magic Packet is Rx'd. 469 */ 470 #define RTW_CONFIG3_CARDBEN BIT(3) /* Cardbus-related registers 471 * and functions are enabled, 472 * read-only. XXX RTL8180 only. 473 */ 474 #define RTW_CONFIG3_CLKRUNEN BIT(2) /* CLKRUN enabled, read-only. 475 * XXX RTL8180 only. 476 */ 477 #define RTW_CONFIG3_FUNCREGEN BIT(1) /* Function Registers Enabled, 478 * read-only. XXX RTL8180 only. 479 */ 480 #define RTW_CONFIG3_FBTBEN BIT(0) /* Fast back-to-back enabled, 481 * read-only. 482 */ 483 #define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */ 484 #define RTW_CONFIG4_VCOPDN BIT(7) /* VCO Power Down 485 * 0: normal operation 486 * (power-on default) 487 * 1: power-down VCO, RF front-end, 488 * and most RTL8180 components. 489 */ 490 #define RTW_CONFIG4_PWROFF BIT(6) /* Power Off 491 * 0: normal operation 492 * (power-on default) 493 * 1: power-down RF front-end, 494 * and most RTL8180 components, 495 * but leave VCO on. 496 * 497 * XXX RFMD front-end only? 498 */ 499 #define RTW_CONFIG4_PWRMGT BIT(5) /* Power Management 500 * 0: normal operation 501 * (power-on default) 502 * 1: set Tx packet's PWRMGMT bit. 503 */ 504 #define RTW_CONFIG4_LWPME BIT(4) /* LANWAKE vs. PMEB: Cardbus-only 505 * 0: LWAKE & PMEB asserted 506 * simultaneously 507 * 1: LWAKE asserted only if 508 * both PMEB is asserted and 509 * ISOLATEB is low. 510 * XXX RTL8180 only. 511 */ 512 #define RTW_CONFIG4_LWPTN BIT(2) /* see RTW_CONFIG1_LWACT 513 * XXX RTL8180 only. 514 */ 515 /* Radio Front-End Programming Method */ 516 #define RTW_CONFIG4_RFTYPE_MASK BITS(1,0) 517 #define RTW_CONFIG4_RFTYPE_INTERSIL LSHIFT(1, RTW_CONFIG4_RFTYPE_MASK) 518 #define RTW_CONFIG4_RFTYPE_RFMD LSHIFT(2, RTW_CONFIG4_RFTYPE_MASK) 519 #define RTW_CONFIG4_RFTYPE_PHILIPS LSHIFT(3, RTW_CONFIG4_RFTYPE_MASK) 520 521 #define RTW_TESTR 0x5B /* TEST mode register, 8b */ 522 523 #define RTW_PSR 0x5e /* Page Select Register, 8b */ 524 #define RTW_PSR_GPO BIT(7) /* Control/status of pin 52. */ 525 #define RTW_PSR_GPI BIT(6) /* Status of pin 64. */ 526 #define RTW_PSR_LEDGPO1 BIT(5) /* Status/control of LED1 pin if 527 * RTW_CONFIG0_LEDGPOEN is set. 528 */ 529 #define RTW_PSR_LEDGPO0 BIT(4) /* Status/control of LED0 pin if 530 * RTW_CONFIG0_LEDGPOEN is set. 531 */ 532 #define RTW_PSR_UWF BIT(1) /* Enable Unicast Wakeup Frame */ 533 #define RTW_PSR_PSEN BIT(0) /* 1: page 1, 0: page 0 */ 534 535 #define RTW_SCR 0x5f /* Security Configuration Register, 8b */ 536 #define RTW_SCR_KM_MASK BITS(5,4) /* Key Mode */ 537 #define RTW_SCR_KM_WEP104 LSHIFT(1, RTW_SCR_KM_MASK) 538 #define RTW_SCR_KM_WEP40 LSHIFT(0, RTW_SCR_KM_MASK) 539 #define RTW_SCR_TXSECON BIT(1) /* Enable Tx WEP. Invalid if 540 * neither RTW_CONFIG0_WEP40 nor 541 * RTW_CONFIG0_WEP104 is set. 542 */ 543 #define RTW_SCR_RXSECON BIT(0) /* Enable Rx WEP. Invalid if 544 * neither RTW_CONFIG0_WEP40 nor 545 * RTW_CONFIG0_WEP104 is set. 546 */ 547 548 #define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */ 549 #define RTW_BCNITV_BCNITV BITS(9,0) /* TU between TBTT, written 550 * by host. 551 */ 552 #define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */ 553 #define RTW_ATIMWND_ATIMWND BITS(9,0) /* ATIM Window length in TU, 554 * written by host. 555 */ 556 557 #define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */ 558 #define RTW_BINTRITV_BINTRITV BITS(9,0) /* RTL8180 wakes host with 559 * RTW_INTR_BCNINT at BINTRITV 560 * microseconds before TBTT 561 */ 562 #define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */ 563 #define RTW_ATIMTRITV_ATIMTRITV BITS(9,0) /* RTL8180 wakes host with 564 * RTW_INTR_ATIMINT at ATIMTRITV 565 * microseconds before end of 566 * ATIM Window 567 */ 568 569 #define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */ 570 #define RTW_PHYDELAY_REVC_MAGIC BIT(3) /* Rev. C magic from reference 571 * driver 572 */ 573 #define RTW_PHYDELAY_PHYDELAY BITS(2,0) /* microsecond Tx delay between 574 * MAC and RF front-end 575 */ 576 #define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */ 577 #define RTW_CRCOUNT_MAGIC 0x4c 578 579 #define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */ 580 581 #define RTW_BB 0x7c /* Baseband interface, 32b */ 582 /* used for writing RTL8180's integrated baseband processor */ 583 #define RTW_BB_RD_MASK BITS(23,16) /* data to read */ 584 #define RTW_BB_WR_MASK BITS(15,8) /* data to write */ 585 #define RTW_BB_WREN BIT(7) /* write enable */ 586 #define RTW_BB_ADDR_MASK BITS(6,0) /* address */ 587 588 #define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */ 589 #define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */ 590 #define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */ 591 592 #define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */ 593 #define RTW_PHYCFG_MAC_POLL BIT(31) /* if !RTW_PHYCFG_HST, 594 * host sets. MAC clears 595 * after banging bits. 596 */ 597 #define RTW_PHYCFG_HST BIT(30) /* 1: host bangs bits 598 * 0: MAC bangs bits 599 */ 600 #define RTW_PHYCFG_MAC_RFTYPE_MASK BITS(29,28) 601 #define RTW_PHYCFG_MAC_RFTYPE_INTERSIL LSHIFT(0, RTW_PHYCFG_MAC_RFTYPE_MASK) 602 #define RTW_PHYCFG_MAC_RFTYPE_RFMD LSHIFT(1, RTW_PHYCFG_MAC_RFTYPE_MASK) 603 #define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD 604 #define RTW_PHYCFG_MAC_RFTYPE_PHILIPS LSHIFT(3, RTW_PHYCFG_MAC_RFTYPE_MASK) 605 #define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK BITS(27,24) 606 #define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK BITS(23,0) 607 #define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK BITS(27,24) 608 #define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK BITS(11,8) 609 #define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK BITS(7,0) 610 #define RTW_PHYCFG_HST_EN BIT(2) 611 #define RTW_PHYCFG_HST_CLK BIT(1) 612 #define RTW_PHYCFG_HST_DATA BIT(0) 613 614 #define RTW_MAXIM_HIDATA_MASK BITS(11,4) 615 #define RTW_MAXIM_LODATA_MASK BITS(3,0) 616 617 /** 618 ** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1. 619 **/ 620 621 #define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */ 622 #define RTW_WAKEUP0H 0x88 /* 32b */ 623 624 #define RTW_WAKEUP1L 0x8c 625 #define RTW_WAKEUP1H 0x90 626 627 #define RTW_WAKEUP2LL 0x94 628 #define RTW_WAKEUP2LH 0x98 629 630 #define RTW_WAKEUP2HL 0x9c 631 #define RTW_WAKEUP2HH 0xa0 632 633 #define RTW_WAKEUP3LL 0xa4 634 #define RTW_WAKEUP3LH 0xa8 635 636 #define RTW_WAKEUP3HL 0xac 637 #define RTW_WAKEUP3HH 0xb0 638 639 #define RTW_WAKEUP4LL 0xb4 640 #define RTW_WAKEUP4LH 0xb8 641 642 #define RTW_WAKEUP4HL 0xbc 643 #define RTW_WAKEUP4HH 0xc0 644 645 #define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */ 646 #define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */ 647 #define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */ 648 #define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */ 649 #define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */ 650 651 /** 652 ** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0. 653 **/ 654 655 /* Default Key Registers, each 128b 656 * 657 * If RTW_SCR_KM_WEP104, 104 lsb are the key. 658 * If RTW_SCR_KM_WEP40, 40 lsb are the key. 659 */ 660 #define RTW_DK0 0x90 /* Default Key 0 Register, 128b */ 661 #define RTW_DK1 0xa0 /* Default Key 1 Register, 128b */ 662 #define RTW_DK2 0xb0 /* Default Key 2 Register, 128b */ 663 #define RTW_DK3 0xc0 /* Default Key 3 Register, 128b */ 664 665 #define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */ 666 #define RTW_CONFIG5_TXFIFOOK BIT(7) /* Tx FIFO self-test pass, read-only */ 667 #define RTW_CONFIG5_RXFIFOOK BIT(6) /* Rx FIFO self-test pass, read-only */ 668 #define RTW_CONFIG5_CALON BIT(5) /* 1: start calibration cycle 669 * and raise AGCRESET pin. 670 * 0: lower AGCRESET pin 671 */ 672 #define RTW_CONFIG5_EACPI BIT(2) /* Enable ACPI Wake up, default 0 */ 673 #define RTW_CONFIG5_LANWAKE BIT(1) /* Enable LAN Wake signal, 674 * from EEPROM 675 */ 676 #define RTW_CONFIG5_PMESTS BIT(0) /* 1: both software & PCI Reset 677 * reset PME_Status 678 * 0: only software resets PME_Status 679 * 680 * From EEPROM. 681 */ 682 683 #define RTW_TPPOLL 0xd9 /* Transmit Priority Polling Register, 8b, 684 * write-only. 685 */ 686 #define RTW_TPPOLL_BQ BIT(7) /* RTL8180 clears to notify host of a beacon 687 * Tx. Host writes have no effect. 688 */ 689 #define RTW_TPPOLL_HPQ BIT(6) /* Host writes 1 to notify RTL8180 of 690 * high-priority Tx packets, RTL8180 clears 691 * to after high-priority Tx is complete. 692 */ 693 #define RTW_TPPOLL_NPQ BIT(5) /* If RTW_CONFIG2_DPS is set, 694 * host writes 1 to notify RTL8180 of 695 * normal-priority Tx packets, RTL8180 clears 696 * after normal-priority Tx is complete. 697 * 698 * If RTW_CONFIG2_DPS is clear, host writes 699 * have no effect. RTL8180 clears after 700 * normal-priority Tx is complete. 701 */ 702 #define RTW_TPPOLL_LPQ BIT(4) /* Host writes 1 to notify RTL8180 of 703 * low-priority Tx packets, RTL8180 clears 704 * after low-priority Tx is complete. 705 */ 706 #define RTW_TPPOLL_SBQ BIT(3) /* Host writes 1 to tell RTL8180 to 707 * stop beacon DMA. This bit is invalid 708 * when RTW_CONFIG2_DPS is set. 709 */ 710 #define RTW_TPPOLL_SHPQ BIT(2) /* Host writes 1 to tell RTL8180 to 711 * stop high-priority DMA. 712 */ 713 #define RTW_TPPOLL_SNPQ BIT(2) /* Host writes 1 to tell RTL8180 to 714 * stop normal-priority DMA. This bit is invalid 715 * when RTW_CONFIG2_DPS is set. 716 */ 717 #define RTW_TPPOLL_SLPQ BIT(2) /* Host writes 1 to tell RTL8180 to 718 * stop low-priority DMA. 719 */ 720 #define RTW_TPPOLL_FSWINT BIT(0) /* Force software interrupt. From 721 * reference driver. 722 */ 723 724 725 #define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */ 726 /* Contention Window: indicates number of contention windows before Tx 727 */ 728 #define RTW_CWR_CW BITS(9,0) 729 730 /* Retry Count Register, 16b, read-only */ 731 #define RTW_RETRYCTR 0xde 732 /* Retry Count: indicates number of retries after Tx */ 733 #define RTW_RETRYCTR_RETRYCT BITS(7,0) 734 735 #define RTW_RDSAR 0xe4 /* Receive descriptor Start Address Register, 736 * 32b, 256-byte alignment. 737 */ 738 /* Function Event Register, 32b, Cardbus only. Only valid when 739 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 740 */ 741 #define RTW_FER 0xf0 742 #define RTW_FER_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 743 #define RTW_FER_GWAKE BIT(4) /* General Wakeup */ 744 /* Function Event Mask Register, 32b, Cardbus only. Only valid when 745 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 746 */ 747 #define RTW_FEMR 0xf4 748 #define RTW_FEMR_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 749 #define RTW_FEMR_WKUP BIT(14) /* Wakeup Mask */ 750 #define RTW_FEMR_GWAKE BIT(4) /* General Wakeup */ 751 /* Function Present State Register, 32b, read-only, Cardbus only. 752 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 753 * are set. 754 */ 755 #define RTW_FPSR 0xf8 756 #define RTW_FPSR_INTR BIT(15) /* TBD */ 757 #define RTW_FPSR_GWAKE BIT(4) /* General Wakeup: TBD */ 758 /* Function Force Event Register, 32b, write-only, Cardbus only. 759 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 760 * are set. 761 */ 762 #define RTW_FFER 0xfc 763 #define RTW_FFER_INTR BIT(15) /* TBD */ 764 #define RTW_FFER_GWAKE BIT(4) /* General Wakeup: TBD */ 765 766 /* Serial EEPROM offsets */ 767 #define RTW_SR_ID 0x00 /* 16b */ 768 #define RTW_SR_VID 0x02 /* 16b */ 769 #define RTW_SR_DID 0x04 /* 16b */ 770 #define RTW_SR_SVID 0x06 /* 16b */ 771 #define RTW_SR_SMID 0x08 /* 16b */ 772 #define RTW_SR_MNGNT 0x0a 773 #define RTW_SR_MXLAT 0x0b 774 #define RTW_SR_RFCHIPID 0x0c 775 #define RTW_SR_CONFIG3 0x0d 776 #define RTW_SR_MAC 0x0e /* 6 bytes */ 777 #define RTW_SR_CONFIG0 0x14 778 #define RTW_SR_CONFIG1 0x15 779 #define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */ 780 #define RTW_SR_CONFIG2 0x18 781 #define RTW_SR_CONFIG4 0x19 782 #define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */ 783 #define RTW_SR_TESTR 0x1e 784 #define RTW_SR_CONFIG5 0x1f 785 #define RTW_SR_TXPOWER1 0x20 786 #define RTW_SR_TXPOWER2 0x21 787 #define RTW_SR_TXPOWER3 0x22 788 #define RTW_SR_TXPOWER4 0x23 789 #define RTW_SR_TXPOWER5 0x24 790 #define RTW_SR_TXPOWER6 0x25 791 #define RTW_SR_TXPOWER7 0x26 792 #define RTW_SR_TXPOWER8 0x27 793 #define RTW_SR_TXPOWER9 0x28 794 #define RTW_SR_TXPOWER10 0x29 795 #define RTW_SR_TXPOWER11 0x2a 796 #define RTW_SR_TXPOWER12 0x2b 797 #define RTW_SR_TXPOWER13 0x2c 798 #define RTW_SR_TXPOWER14 0x2d 799 #define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */ 800 #define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */ 801 #define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */ 802 #define RTW_SR_CISPOINTER 0x30 /* 16b */ 803 #define RTW_SR_RFPARM 0x32 /* RF-specific parameter */ 804 #define RTW_SR_RFPARM_DIGPHY BIT(0) /* 1: digital PHY */ 805 #define RTW_SR_RFPARM_DFLANTB BIT(1) /* 1: antenna B is default */ 806 #define RTW_SR_RFPARM_CS_MASK BITS(2,3) /* carrier-sense type */ 807 #define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */ 808 #define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */ 809 #define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */ 810 #define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes*/ 811 812 /* 813 * RTL8180 Transmit/Receive Descriptors 814 */ 815 816 /* the first descriptor in each ring must be on a 256-byte boundary */ 817 #define RTW_DESC_ALIGNMENT 256 818 819 /* Tx descriptor */ 820 struct rtw_txdesc { 821 u_int32_t htx_ctl0; 822 u_int32_t htx_ctl1; 823 u_int32_t htx_buf; 824 u_int32_t htx_len; 825 u_int32_t htx_next; 826 u_int32_t htx_rsvd[3]; 827 }; 828 829 #define htx_stat htx_ctl0 830 831 #define RTW_TXCTL0_OWN BIT(31) /* 1: ready to Tx */ 832 #define RTW_TXCTL0_RSVD0 BIT(30) /* reserved */ 833 #define RTW_TXCTL0_FS BIT(29) /* first segment */ 834 #define RTW_TXCTL0_LS BIT(28) /* last segment */ 835 836 #define RTW_TXCTL0_RATE_MASK BITS(27,24) /* Tx rate */ 837 #define RTW_TXCTL0_RATE_1MBPS LSHIFT(0, RTW_TXCTL_RATE_MASK) 838 #define RTW_TXCTL0_RATE_2MBPS LSHIFT(1, RTW_TXCTL_RATE_MASK) 839 #define RTW_TXCTL0_RATE_5MBPS LSHIFT(2, RTW_TXCTL_RATE_MASK) 840 #define RTW_TXCTL0_RATE_11MBPS LSHIFT(3, RTW_TXCTL_RATE_MASK) 841 842 #define RTW_TXCTL0_RTSEN BIT(23) /* RTS Enable */ 843 844 #define RTW_TXCTL0_RTSRATE_MASK BITS(22,19) /* Tx rate */ 845 #define RTW_TXCTL0_RTSRATE_1MBPS LSHIFT(0, RTW_TXCTL_RTSRATE_MASK) 846 #define RTW_TXCTL0_RTSRATE_2MBPS LSHIFT(1, RTW_TXCTL_RTSRATE_MASK) 847 #define RTW_TXCTL0_RTSRATE_5MBPS LSHIFT(2, RTW_TXCTL_RTSRATE_MASK) 848 #define RTW_TXCTL0_RTSRATE_11MBPS LSHIFT(3, RTW_TXCTL_RTSRATE_MASK) 849 850 #define RTW_TXCTL0_BEACON BIT(18) /* packet is a beacon */ 851 #define RTW_TXCTL0_MOREFRAG BIT(17) /* another fragment follows */ 852 #define RTW_TXCTL0_SPLCP BIT(16) /* add short PLCP preamble 853 * and header 854 */ 855 #define RTW_TXCTL0_KEYID_MASK BITS(15,14) /* default key id */ 856 #define RTW_TXCTL0_RSVD1_MASK BITS(13,12) /* reserved */ 857 #define RTW_TXCTL0_TPKTSIZE_MASK BITS(11,0) /* Tx packet size 858 * in bytes 859 */ 860 861 #define RTW_TXSTAT_OWN RTW_TXCTL_OWN 862 #define RTW_TXSTAT_RSVD0 RTW_TXCTL_RSVD0 863 #define RTW_TXSTAT_FS RTW_TXCTL_FS 864 #define RTW_TXSTAT_LS RTW_TXCTL_LS 865 #define RTW_TXSTAT_RSVD0 RTW_TXCTL_RSVD0 866 #define RTW_TXSTAT_RSVD1_MASK BITS(27,16) 867 #define RTW_TXSTAT_TOK BIT(15) 868 #define RTW_TXSTAT_RTSRETRY_MASK BITS(14,8) /* RTS retry count */ 869 #define RTW_TXSTAT_DRC_MASK BITS(7,0) /* Data retry count */ 870 871 #define RTW_TXCTL1_LENGEXT BIT(31) /* supplements _LENGTH 872 * in packets sent 5.5Mb/s or 873 * faster 874 */ 875 #define RTW_TXCTL1_LENGTH_MASK BITS(30,16) /* PLCP length (microseconds) */ 876 #define RTW_TXCTL1_RTSDUR_MASK BITS(15,0) /* RTS Duration 877 * (microseconds) 878 */ 879 880 #define RTW_TXLEN_LENGTH_MASK BITS(11,0) /* Tx buffer length in bytes */ 881 882 /* Rx descriptor */ 883 struct rtw_rxdesc { 884 u_int32_t hrx_ctl; 885 u_int32_t hrx_rsvd0; 886 u_int32_t hrx_buf; 887 u_int32_t hrx_rsvd1; 888 }; 889 890 #define hrx_stat hrx_ctl 891 #define hrx_rssi hrx_rsvd0 892 #define hrx_tsftl hrx_buf /* valid only when RTW_RXSTAT_LS is set */ 893 #define hrx_tsfth hrx_rsvd1 /* valid only when RTW_RXSTAT_LS is set */ 894 895 #define RTW_RXCTL_OWN BIT(31) /* 1: owned by NIC */ 896 #define RTW_RXCTL_EOR BIT(30) /* end of ring */ 897 #define RTW_RXCTL_FS BIT(29) /* first segment */ 898 #define RTW_RXCTL_LS BIT(28) /* last segment */ 899 #define RTW_RXCTL_RSVD0_MASK BITS(29,12) /* reserved */ 900 #define RTW_RXCTL_LENGTH_MASK BITS(11,0) /* Rx buffer length */ 901 902 #define RTW_RXSTAT_OWN RTW_RXCTL_OWN 903 #define RTW_RXSTAT_EOR RTW_RXCTL_EOR 904 #define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */ 905 #define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */ 906 #define RTW_RXSTAT_DMAFAIL BIT(27) /* DMA failure on this pkt */ 907 #define RTW_RXSTAT_BOVF BIT(26) /* buffer overflow XXX means 908 * FIFO exhausted? 909 */ 910 #define RTW_RXSTAT_SPLCP BIT(25) /* Rx'd with short preamble 911 * and PLCP header 912 */ 913 #define RTW_RXSTAT_RSVD1 BIT(24) /* reserved */ 914 #define RTW_RXSTAT_RATE_MASK BITS(23,20) /* Rx rate */ 915 #define RTW_RXSTAT_RATE_1MBPS LSHIFT(0, RTW_RXSTAT_RATE_MASK) 916 #define RTW_RXSTAT_RATE_2MBPS LSHIFT(1, RTW_RXSTAT_RATE_MASK) 917 #define RTW_RXSTAT_RATE_5MBPS LSHIFT(2, RTW_RXSTAT_RATE_MASK) 918 #define RTW_RXSTAT_RATE_11MBPS LSHIFT(3, RTW_RXSTAT_RATE_MASK) 919 #define RTW_RXSTAT_MIC BIT(19) /* XXX from reference driver */ 920 #define RTW_RXSTAT_MAR BIT(18) /* is multicast */ 921 #define RTW_RXSTAT_PAR BIT(17) /* matches RTL8180's MAC */ 922 #define RTW_RXSTAT_BAR BIT(16) /* is broadcast */ 923 #define RTW_RXSTAT_RES BIT(15) /* error summary. valid when 924 * RTW_RXSTAT_LS set. indicates 925 * that either RTW_RXSTAT_CRC32 926 * or RTW_RXSTAT_ICV is set. 927 */ 928 #define RTW_RXSTAT_PWRMGT BIT(14) /* 802.11 PWRMGMT bit is set */ 929 #define RTW_RXSTAT_CRC16 BIT(14) /* XXX CRC16 error, from 930 * reference driver 931 */ 932 #define RTW_RXSTAT_CRC32 BIT(13) /* CRC32 error */ 933 #define RTW_RXSTAT_ICV BIT(12) /* ICV error */ 934 #define RTW_RXSTAT_LENGTH_MASK BITS(11,0) /* frame length, including 935 * CRC32 936 */ 937 938 /* Convenient status conjunction. */ 939 #define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS) 940 /* Convenient status disjunctions. */ 941 #define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF) 942 #define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\ 943 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\ 944 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\ 945 RTW_RXSTAT_ICV) 946 947 948 #define RTW_RXRSSI_VLAN BITS(32,16) /* XXX from reference driver */ 949 /* for Philips RF front-ends */ 950 #define RTW_RXRSSI_RSSI BITS(15,8) /* RF energy at the PHY */ 951 /* for RF front-ends by Intersil, Maxim, RFMD */ 952 #define RTW_RXRSSI_IMR_RSSI BITS(15,9) /* RF energy at the PHY */ 953 #define RTW_RXRSSI_IMR_LNA BIT(8) /* 1: LNA activated */ 954 #define RTW_RXRSSI_SQ BITS(7,0) /* Barker code-lock quality */ 955 956 #define RTW_READ8(regs, ofs) \ 957 bus_space_read_1((regs)->r_bt, (regs)->r_bh, (ofs)) 958 959 #define RTW_READ16(regs, ofs) \ 960 bus_space_read_2((regs)->r_bt, (regs)->r_bh, (ofs)) 961 962 #define RTW_READ(regs, ofs) \ 963 bus_space_read_4((regs)->r_bt, (regs)->r_bh, (ofs)) 964 965 #define RTW_WRITE8(regs, ofs, val) \ 966 bus_space_write_1((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 967 968 #define RTW_WRITE16(regs, ofs, val) \ 969 bus_space_write_2((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 970 971 #define RTW_WRITE(regs, ofs, val) \ 972 bus_space_write_4((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 973 974 #define RTW_ISSET(regs, reg, mask) \ 975 (RTW_READ((regs), (reg)) & (mask)) 976 977 #define RTW_CLR(regs, reg, mask) \ 978 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask)) 979 980 /* bus_space(9) lied? */ 981 #ifndef BUS_SPACE_BARRIER_SYNC 982 #define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 983 #endif 984 985 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ 986 #define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ 987 #endif 988 989 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE 990 #define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ 991 #endif 992 993 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ 994 #define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE 995 #endif 996 997 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE 998 #define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE 999 #endif 1000 1001 /* 1002 * Bus barrier 1003 * 1004 * Complete outstanding read and/or write ops on [reg0, reg1] 1005 * ([reg1, reg0]) before starting new ops on the same region. See 1006 * acceptable bus_space_barrier(9) for the flag definitions. 1007 */ 1008 #define RTW_BARRIER(regs, reg0, reg1, flags) \ 1009 bus_space_barrier((regs)->r_bh, (regs)->r_bt, \ 1010 MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags) 1011 1012 /* 1013 * Barrier convenience macros. 1014 */ 1015 /* sync */ 1016 #define RTW_SYNC(regs, reg0, reg1) \ 1017 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC) 1018 1019 /* write-before-write */ 1020 #define RTW_WBW(regs, reg0, reg1) \ 1021 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1022 1023 /* write-before-read */ 1024 #define RTW_WBR(regs, reg0, reg1) \ 1025 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 1026 1027 /* read-before-read */ 1028 #define RTW_RBR(regs, reg0, reg1) \ 1029 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ) 1030 1031 /* read-before-read */ 1032 #define RTW_RBW(regs, reg0, reg1) \ 1033 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 1034 1035 #define RTW_WBRW(regs, reg0, reg1) \ 1036 RTW_BARRIER(regs, reg0, reg1, \ 1037 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 1038 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1039 1040 /* 1041 * Registers for RTL8180L's built-in baseband modem. 1042 */ 1043 #define RTW_BBP_SYS1 0x00 1044 #define RTW_BBP_TXAGC 0x03 1045 #define RTW_BBP_LNADET 0x04 1046 #define RTW_BBP_IFAGCINI 0x05 1047 #define RTW_BBP_IFAGCLIMIT 0x06 1048 #define RTW_BBP_IFAGCDET 0x07 1049 1050 #define RTW_BBP_ANTATTEN 0x10 1051 #define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91 1052 #define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92 1053 #define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93 1054 #define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3 1055 #define RTW_BBP_ANTATTEN_DFLANTB 0x40 1056 #define RTW_BBP_ANTATTEN_CHAN14 0x0c 1057 1058 #define RTW_BBP_TRL 0x11 1059 #define RTW_BBP_SYS2 0x12 1060 #define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */ 1061 #define RTW_BBP_SYS2_RATE_MASK BITS(5,4) /* loopback rate? 1062 * 0: 1Mbps 1063 * 1: 2Mbps 1064 * 2: 5.5Mbps 1065 * 3: 11Mbps 1066 */ 1067 #define RTW_BBP_SYS3 0x13 1068 /* carrier-sense threshold */ 1069 #define RTW_BBP_SYS3_CSTHRESH_MASK BITS(0,3) 1070 #define RTW_BBP_CHESTLIM 0x19 1071 #define RTW_BBP_CHSQLIM 0x1a 1072 1073
Indexes created Sun Sep 28 16:09:52 GMT 2025