rtwreg.h revision 1.17
1 /* $NetBSD: rtwreg.h,v 1.17 2006/03/08 00:24:06 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 33 #include <lib/libkern/libkern.h> 34 35 /* RTL8180L Host Control and Status Registers */ 36 37 #define RTW_IDR0 0x00 /* ID Register: MAC addr, 6 bytes. 38 * Auto-loaded from EEPROM. Read by byte, 39 * by word, or by double word, but write 40 * only by double word. 41 */ 42 #define RTW_IDR1 0x04 43 44 #define RTW_MAR0 0x08 /* Multicast filter, 64b. */ 45 #define RTW_MAR1 0x0c 46 47 #define RTW_TSFTRL 0x18 /* Timing Synchronization Function Timer 48 * Register, low word, 32b, read-only. 49 */ 50 #define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */ 51 #define RTW_TLPDA 0x20 /* Transmit Low Priority Descriptors Start 52 * Address, 32b, 256-byte alignment. 53 */ 54 #define RTW_TNPDA 0x24 /* Transmit Normal Priority Descriptors Start 55 * Address, 32b, 256-byte alignment. 56 */ 57 #define RTW_THPDA 0x28 /* Transmit High Priority Descriptors Start 58 * Address, 32b, 256-byte alignment. 59 */ 60 61 #define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */ 62 #define RTW_BRSR_BPLCP BIT(8) /* 1: use short PLCP header for CTS/ACK packet, 63 * 0: use long PLCP header 64 */ 65 #define RTW_BRSR_MBR8180_MASK BITS(1,0) /* Maximum Basic Service Rate */ 66 #define RTW_BRSR_MBR8180_1MBPS SHIFTIN(0, RTW_BRSR_MBR8180_MASK) 67 #define RTW_BRSR_MBR8180_2MBPS SHIFTIN(1, RTW_BRSR_MBR8180_MASK) 68 #define RTW_BRSR_MBR8180_5MBPS SHIFTIN(2, RTW_BRSR_MBR8180_MASK) 69 #define RTW_BRSR_MBR8180_11MBPS SHIFTIN(3, RTW_BRSR_MBR8180_MASK) 70 71 /* 8181 and 8180 docs conflict! */ 72 #define RTW_BRSR_MBR8181_1MBPS BIT(0) 73 #define RTW_BRSR_MBR8181_2MBPS BIT(1) 74 #define RTW_BRSR_MBR8181_5MBPS BIT(2) 75 #define RTW_BRSR_MBR8181_11MBPS BIT(3) 76 77 #define RTW_BSSID 0x2e 78 /* BSSID, 6 bytes */ 79 #define RTW_BSSID16 0x2e /* first two bytes */ 80 #define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */ 81 #define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */ 82 #define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */ 83 #define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */ 84 #define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */ 85 #define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */ 86 #define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */ 87 88 #define RTW_CR 0x37 /* Command Register, 8b */ 89 #define RTW_CR_RST BIT(4) /* Reset: host sets to 1 to disable 90 * transmitter & receiver, reinitialize FIFO. 91 * RTL8180L sets to 0 to signal completion. 92 */ 93 #define RTW_CR_RE BIT(3) /* Receiver Enable: host enables receiver 94 * by writing 1. RTL8180L indicates receiver 95 * is active with 1. After power-up, host 96 * must wait for reset before writing. 97 */ 98 #define RTW_CR_TE BIT(2) /* Transmitter Enable: host enables transmitter 99 * by writing 1. RTL8180L indicates transmitter 100 * is active with 1. After power-up, host 101 * must wait for reset before writing. 102 */ 103 #define RTW_CR_MULRW BIT(0) /* PCI Multiple Read/Write enable: 1 enables, 104 * 0 disables. XXX RTL8180, only? 105 */ 106 107 #define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */ 108 #define RTW_ISR 0x3e /* Interrupt status register, 16b */ 109 110 #define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO underflow */ 111 #define RTW_INTR_TIMEOUT BIT(14) /* Time Out: 1 indicates 112 * RTW_TSFTR[0:31] = RTW_TINT 113 */ 114 #define RTW_INTR_BCNINT BIT(13) /* Beacon Time Out: time for host to 115 * prepare beacon: 116 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 117 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV) 118 */ 119 #define RTW_INTR_ATIMINT BIT(12) 120 /* ATIM Time Out: ATIM interval will pass, 121 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 122 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV) 123 */ 124 #define RTW_INTR_TBDER BIT(11) /* Tx Beacon Descriptor Error: 125 * beacon transmission aborted because 126 * frame Rx'd 127 */ 128 #define RTW_INTR_TBDOK BIT(10) /* Tx Beacon Descriptor OK */ 129 #define RTW_INTR_THPDER BIT(9) /* Tx High Priority Descriptor Error: 130 * reached short/long retry limit 131 */ 132 #define RTW_INTR_THPDOK BIT(8) /* Tx High Priority Descriptor OK */ 133 #define RTW_INTR_TNPDER BIT(7) /* Tx Normal Priority Descriptor Error: 134 * reached short/long retry limit 135 */ 136 #define RTW_INTR_TNPDOK BIT(6) /* Tx Normal Priority Descriptor OK */ 137 #define RTW_INTR_RXFOVW BIT(5) /* Rx FIFO Overflow: either RDU (see below) 138 * or PCI bus too slow/busy 139 */ 140 #define RTW_INTR_RDU BIT(4) /* Rx Descriptor Unavailable */ 141 #define RTW_INTR_TLPDER BIT(3) /* Tx Normal Priority Descriptor Error 142 * reached short/long retry limit 143 */ 144 #define RTW_INTR_TLPDOK BIT(2) /* Tx Normal Priority Descriptor OK */ 145 #define RTW_INTR_RER BIT(1) /* Rx Error: CRC32 or ICV error */ 146 #define RTW_INTR_ROK BIT(0) /* Rx OK */ 147 148 /* Convenient interrupt conjunctions. */ 149 #define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK) 150 #define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\ 151 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK|\ 152 RTW_INTR_TBDER|RTW_INTR_TBDOK) 153 #define RTW_INTR_BEACON (RTW_INTR_BCNINT|RTW_INTR_TBDER|RTW_INTR_TBDOK) 154 #define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU) 155 156 #define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */ 157 #define RTW_TCR_CWMIN BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */ 158 #define RTW_TCR_SWSEQ BIT(30) /* 1: host assigns 802.11 sequence number, 159 * 0: hardware assigns sequence number 160 */ 161 /* Hardware version ID, read-only */ 162 #define RTW_TCR_HWVERID_MASK BITS(29, 25) 163 #define RTW_TCR_HWVERID_D SHIFTIN(26, RTW_TCR_HWVERID_MASK) 164 #define RTW_TCR_HWVERID_F SHIFTIN(27, RTW_TCR_HWVERID_MASK) 165 #define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F 166 167 /* Set ACK/CTS Timeout (EIFS). 168 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?) 169 * 0: ACK rate = 1Mbps 170 */ 171 #define RTW_TCR_SAT BIT(24) 172 /* Max DMA Burst Size per Tx DMA Burst */ 173 #define RTW_TCR_MXDMA_MASK BITS(23,21) 174 #define RTW_TCR_MXDMA_16 SHIFTIN(0, RTW_TCR_MXDMA_MASK) 175 #define RTW_TCR_MXDMA_32 SHIFTIN(1, RTW_TCR_MXDMA_MASK) 176 #define RTW_TCR_MXDMA_64 SHIFTIN(2, RTW_TCR_MXDMA_MASK) 177 #define RTW_TCR_MXDMA_128 SHIFTIN(3, RTW_TCR_MXDMA_MASK) 178 #define RTW_TCR_MXDMA_256 SHIFTIN(4, RTW_TCR_MXDMA_MASK) 179 #define RTW_TCR_MXDMA_512 SHIFTIN(5, RTW_TCR_MXDMA_MASK) 180 #define RTW_TCR_MXDMA_1024 SHIFTIN(6, RTW_TCR_MXDMA_MASK) 181 #define RTW_TCR_MXDMA_2048 SHIFTIN(7, RTW_TCR_MXDMA_MASK) 182 183 #define RTW_TCR_DISCW BIT(20) /* disable 802.11 random backoff */ 184 185 #define RTW_TCR_ICV BIT(19) /* host lets RTL8180 append ICV to 186 * WEP packets 187 */ 188 189 /* Loopback Test: disables TXI/TXQ outputs. */ 190 #define RTW_TCR_LBK_MASK BITS(18,17) 191 #define RTW_TCR_LBK_NORMAL SHIFTIN(0, RTW_TCR_LBK_MASK) /* normal ops */ 192 #define RTW_TCR_LBK_MAC SHIFTIN(1, RTW_TCR_LBK_MASK) /* MAC loopback */ 193 #define RTW_TCR_LBK_BBP SHIFTIN(2, RTW_TCR_LBK_MASK) /* baseband loop. */ 194 #define RTW_TCR_LBK_CONT SHIFTIN(3, RTW_TCR_LBK_MASK) /* continuous Tx */ 195 196 #define RTW_TCR_CRC BIT(16) /* 0: RTL8180 appends CRC32 197 * 1: host appends CRC32 198 * 199 * (I *think* this is right. 200 * The docs have a mysterious 201 * description in the 202 * passive voice.) 203 */ 204 #define RTW_TCR_SRL_MASK BITS(15,8) /* Short Retry Limit */ 205 #define RTW_TCR_LRL_MASK BITS(7,0) /* Long Retry Limit */ 206 207 #define RTW_RCR 0x44 /* Receive Configuration Register, 32b */ 208 #define RTW_RCR_ONLYERLPKT BIT(31) /* only do Early Rx on packets 209 * longer than 1536 bytes 210 */ 211 #define RTW_RCR_ENCS2 BIT(30) /* enable carrier sense method 2 */ 212 #define RTW_RCR_ENCS1 BIT(29) /* enable carrier sense method 1 */ 213 #define RTW_RCR_ENMARP BIT(28) /* enable MAC auto-reset PHY */ 214 #define RTW_RCR_CBSSID BIT(23) /* Check BSSID/ToDS/FromDS: set 215 * "Link On" when received BSSID 216 * matches RTW_BSSID and received 217 * ToDS/FromDS are appropriate 218 * according to RTW_MSR_NETYPE. 219 */ 220 #define RTW_RCR_APWRMGT BIT(22) /* accept packets w/ PWRMGMT bit set */ 221 #define RTW_RCR_ADD3 BIT(21) /* when RTW_MSR_NETYPE == 222 * RTW_MSR_NETYPE_INFRA_OK, accept 223 * broadcast/multicast packets whose 224 * 3rd address matches RTL8180's MAC. 225 */ 226 #define RTW_RCR_AMF BIT(20) /* accept management frames */ 227 #define RTW_RCR_ACF BIT(19) /* accept control frames */ 228 #define RTW_RCR_ADF BIT(18) /* accept data frames */ 229 /* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data 230 * bytes are received 231 */ 232 #define RTW_RCR_RXFTH_MASK BITS(15,13) 233 #define RTW_RCR_RXFTH_64 SHIFTIN(2, RTW_RCR_RXFTH_MASK) 234 #define RTW_RCR_RXFTH_128 SHIFTIN(3, RTW_RCR_RXFTH_MASK) 235 #define RTW_RCR_RXFTH_256 SHIFTIN(4, RTW_RCR_RXFTH_MASK) 236 #define RTW_RCR_RXFTH_512 SHIFTIN(5, RTW_RCR_RXFTH_MASK) 237 #define RTW_RCR_RXFTH_1024 SHIFTIN(6, RTW_RCR_RXFTH_MASK) 238 #define RTW_RCR_RXFTH_WHOLE SHIFTIN(7, RTW_RCR_RXFTH_MASK) 239 240 #define RTW_RCR_AICV BIT(12) /* accept frames w/ ICV errors */ 241 242 /* Max DMA Burst Size per Rx DMA Burst */ 243 #define RTW_RCR_MXDMA_MASK BITS(10,8) 244 #define RTW_RCR_MXDMA_16 SHIFTIN(0, RTW_RCR_MXDMA_MASK) 245 #define RTW_RCR_MXDMA_32 SHIFTIN(1, RTW_RCR_MXDMA_MASK) 246 #define RTW_RCR_MXDMA_64 SHIFTIN(2, RTW_RCR_MXDMA_MASK) 247 #define RTW_RCR_MXDMA_128 SHIFTIN(3, RTW_RCR_MXDMA_MASK) 248 #define RTW_RCR_MXDMA_256 SHIFTIN(4, RTW_RCR_MXDMA_MASK) 249 #define RTW_RCR_MXDMA_512 SHIFTIN(5, RTW_RCR_MXDMA_MASK) 250 #define RTW_RCR_MXDMA_1024 SHIFTIN(6, RTW_RCR_MXDMA_MASK) 251 #define RTW_RCR_MXDMA_UNLIMITED SHIFTIN(7, RTW_RCR_MXDMA_MASK) 252 253 /* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */ 254 #define RTW_RCR_9356SEL BIT(6) 255 256 #define RTW_RCR_ACRC32 BIT(5) /* accept frames w/ CRC32 errors */ 257 #define RTW_RCR_AB BIT(3) /* accept broadcast frames */ 258 #define RTW_RCR_AM BIT(2) /* accept multicast frames */ 259 /* accept physical match frames. XXX means PLCP header ok? */ 260 #define RTW_RCR_APM BIT(1) 261 #define RTW_RCR_AAP BIT(0) /* accept frames w/ destination */ 262 263 /* Additional bits to set in monitor mode. */ 264 #define RTW_RCR_MONITOR ( \ 265 RTW_RCR_AAP | \ 266 RTW_RCR_ACF | \ 267 RTW_RCR_ACRC32 | \ 268 RTW_RCR_AICV | \ 269 0) 270 271 /* The packet filter bits. */ 272 #define RTW_RCR_PKTFILTER_MASK (\ 273 RTW_RCR_AAP | \ 274 RTW_RCR_AB | \ 275 RTW_RCR_ACF | \ 276 RTW_RCR_ACRC32 | \ 277 RTW_RCR_ADD3 | \ 278 RTW_RCR_ADF | \ 279 RTW_RCR_AICV | \ 280 RTW_RCR_AM | \ 281 RTW_RCR_AMF | \ 282 RTW_RCR_APM | \ 283 RTW_RCR_APWRMGT | \ 284 0) 285 286 /* Receive power-management frames and mgmt/ctrl/data frames. */ 287 #define RTW_RCR_PKTFILTER_DEFAULT ( \ 288 RTW_RCR_ADF | \ 289 RTW_RCR_AMF | \ 290 RTW_RCR_APM | \ 291 RTW_RCR_APWRMGT | \ 292 0) 293 294 #define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */ 295 #define RTW_TBDA 0x4c /* Transmit Beacon Descriptor Start Address, 296 * 32b, 256-byte alignment 297 */ 298 #define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */ 299 #define RTW_9346CR_EEM_MASK BITS(7,6) /* Operating Mode */ 300 #define RTW_9346CR_EEM_NORMAL SHIFTIN(0, RTW_9346CR_EEM_MASK) 301 /* Load the EEPROM. Reset registers to defaults. 302 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL. 303 * XXX RTL8180 only? 304 */ 305 #define RTW_9346CR_EEM_AUTOLOAD SHIFTIN(1, RTW_9346CR_EEM_MASK) 306 /* Disable network & bus-master operations and enable 307 * _EECS, _EESK, _EEDI, _EEDO. 308 * XXX RTL8180 only? 309 */ 310 #define RTW_9346CR_EEM_PROGRAM SHIFTIN(2, RTW_9346CR_EEM_MASK) 311 /* Enable RTW_CONFIG[0123] registers. */ 312 #define RTW_9346CR_EEM_CONFIG SHIFTIN(3, RTW_9346CR_EEM_MASK) 313 /* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes. 314 * XXX RTL8180 only? 315 */ 316 #define RTW_9346CR_EECS BIT(3) 317 #define RTW_9346CR_EESK BIT(2) 318 #define RTW_9346CR_EEDI BIT(1) 319 #define RTW_9346CR_EEDO BIT(0) /* read-only */ 320 321 #define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */ 322 #define RTW_CONFIG0_WEP40 BIT(7) /* implements 40-bit WEP, 323 * XXX RTL8180 only? 324 */ 325 #define RTW_CONFIG0_WEP104 BIT(6) /* implements 104-bit WEP, 326 * from EEPROM, read-only 327 * XXX RTL8180 only? 328 */ 329 #define RTW_CONFIG0_LEDGPOEN BIT(4) /* 1: RTW_PSR_LEDGPO[01] control 330 * LED[01] pins. 331 * 0: LED behavior defined by 332 * RTW_CONFIG1_LEDS10_MASK 333 * XXX RTL8180 only? 334 */ 335 /* auxiliary power is present, read-only */ 336 #define RTW_CONFIG0_AUXPWR BIT(3) 337 /* Geographic Location, read-only */ 338 #define RTW_CONFIG0_GL_MASK BITS(1,0) 339 /* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_* 340 * work. 341 */ 342 #define _RTW_CONFIG0_GL_USA SHIFTIN(3, RTW_CONFIG0_GL_MASK) 343 #define RTW_CONFIG0_GL_EUROPE SHIFTIN(2, RTW_CONFIG0_GL_MASK) 344 #define RTW_CONFIG0_GL_JAPAN SHIFTIN(1, RTW_CONFIG0_GL_MASK) 345 #define RTW_CONFIG0_GL_USA SHIFTIN(0, RTW_CONFIG0_GL_MASK) 346 /* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */ 347 348 #define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */ 349 350 /* LED configuration. From EEPROM. Read/write. 351 * 352 * Setting LED0 LED1 353 * ------- ---- ---- 354 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure 355 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link 356 * RTW_CONFIG1_LEDS_TX_RX Tx Rx 357 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure 358 */ 359 #define RTW_CONFIG1_LEDS_MASK BITS(7,6) 360 #define RTW_CONFIG1_LEDS_ACT_INFRA SHIFTIN(0, RTW_CONFIG1_LEDS_MASK) 361 #define RTW_CONFIG1_LEDS_ACT_LINK SHIFTIN(1, RTW_CONFIG1_LEDS_MASK) 362 #define RTW_CONFIG1_LEDS_TX_RX SHIFTIN(2, RTW_CONFIG1_LEDS_MASK) 363 #define RTW_CONFIG1_LEDS_LINKACT_INFRA SHIFTIN(3, RTW_CONFIG1_LEDS_MASK) 364 365 /* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms. 366 * 367 * RTW_CONFIG1_LWACT 368 * 0 1 369 * RTW_CONFIG4_LWPTN 0 active high active low 370 * 1 positive pulse negative pulse 371 */ 372 #define RTW_CONFIG1_LWACT BIT(4) 373 374 #define RTW_CONFIG1_MEMMAP BIT(3) /* using PCI memory space, read-only */ 375 #define RTW_CONFIG1_IOMAP BIT(2) /* using PCI I/O space, read-only */ 376 #define RTW_CONFIG1_VPD BIT(1) /* if set, VPD from offsets 377 * 0x40-0x7f in EEPROM are at 378 * registers 0x60-0x67 of PCI 379 * Configuration Space (XXX huh?) 380 */ 381 #define RTW_CONFIG1_PMEN BIT(0) /* Power Management Enable: TBD */ 382 383 #define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */ 384 #define RTW_CONFIG2_LCK BIT(7) /* clocks are locked, read-only: 385 * Tx frequency & symbol clocks 386 * are derived from the same OSC 387 */ 388 #define RTW_CONFIG2_ANT BIT(6) /* diversity enabled, read-only */ 389 #define RTW_CONFIG2_DPS BIT(3) /* Descriptor Polling State: enable 390 * test mode. 391 */ 392 #define RTW_CONFIG2_PAPESIGN BIT(2) /* TBD, from EEPROM */ 393 #define RTW_CONFIG2_PAPETIME_MASK BITS(1,0) /* TBD, from EEPROM */ 394 395 #define RTW_ANAPARM 0x54 /* Analog parameter, 32b */ 396 #define RTW_ANAPARM_RFPOW0_MASK BITS(30,28) /* undocumented bits 397 * which appear to 398 * control the power 399 * state of the RF 400 * components 401 */ 402 #define RTW_ANAPARM_RFPOW_MASK \ 403 (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK) 404 405 #define RTW_ANAPARM_TXDACOFF BIT(27) /* 1: disable Tx DAC, 406 * 0: enable 407 */ 408 #define RTW_ANAPARM_RFPOW1_MASK BITS(26,20) /* undocumented bits 409 * which appear to 410 * control the power 411 * state of the RF 412 * components 413 */ 414 415 /* 416 * Maxim On/Sleep/Off control 417 */ 418 #define RTW_ANAPARM_RFPOW_MAXIM_ON SHIFTIN(0x8, RTW_ANAPARM_RFPOW1_MASK) 419 420 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 421 #define RTW_ANAPARM_RFPOW_MAXIM_SLEEP SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) 422 423 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 424 #define RTW_ANAPARM_RFPOW_MAXIM_OFF SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) 425 426 /* 427 * RFMD On/Sleep/Off control 428 */ 429 #define RTW_ANAPARM_RFPOW_RFMD_ON SHIFTIN(0x408, RTW_ANAPARM_RFPOW1_MASK) 430 431 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 432 #define RTW_ANAPARM_RFPOW_RFMD_SLEEP SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) 433 434 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 435 #define RTW_ANAPARM_RFPOW_RFMD_OFF SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) 436 437 /* 438 * Philips On/Sleep/Off control 439 */ 440 #define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \ 441 SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK) 442 #define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \ 443 SHIFTIN(0x008, RTW_ANAPARM_RFPOW1_MASK) 444 445 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 446 #define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\ 447 SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) 448 449 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 450 #define RTW_ANAPARM_RFPOW_PHILIPS_OFF\ 451 SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) 452 453 #define RTW_ANAPARM_RFPOW_PHILIPS_ON SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK) 454 455 #define RTW_ANAPARM_CARDSP_MASK BITS(19,0) /* undocumented 456 * card-specific 457 * bits from the 458 * EEPROM. 459 */ 460 461 #define RTW_MSR 0x58 /* Media Status Register, 8b */ 462 /* Network Type and Link Status */ 463 #define RTW_MSR_NETYPE_MASK BITS(3,2) 464 /* AP, XXX RTL8181 only? */ 465 #define RTW_MSR_NETYPE_AP_OK SHIFTIN(3, RTW_MSR_NETYPE_MASK) 466 /* infrastructure link ok */ 467 #define RTW_MSR_NETYPE_INFRA_OK SHIFTIN(2, RTW_MSR_NETYPE_MASK) 468 /* ad-hoc link ok */ 469 #define RTW_MSR_NETYPE_ADHOC_OK SHIFTIN(1, RTW_MSR_NETYPE_MASK) 470 /* no link */ 471 #define RTW_MSR_NETYPE_NOLINK SHIFTIN(0, RTW_MSR_NETYPE_MASK) 472 473 #define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */ 474 #define RTW_CONFIG3_GNTSEL BIT(7) /* Grant Select, read-only */ 475 #define RTW_CONFIG3_PARMEN BIT(6) /* Set RTW_CONFIG3_PARMEN and 476 * RTW_9346CR_EEM_CONFIG to 477 * allow RTW_ANAPARM writes. 478 */ 479 #define RTW_CONFIG3_MAGIC BIT(5) /* Valid when RTW_CONFIG1_PMEN is 480 * set. If set, RTL8180 wakes up 481 * OS when Magic Packet is Rx'd. 482 */ 483 #define RTW_CONFIG3_CARDBEN BIT(3) /* Cardbus-related registers 484 * and functions are enabled, 485 * read-only. XXX RTL8180 only. 486 */ 487 #define RTW_CONFIG3_CLKRUNEN BIT(2) /* CLKRUN enabled, read-only. 488 * XXX RTL8180 only. 489 */ 490 #define RTW_CONFIG3_FUNCREGEN BIT(1) /* Function Registers Enabled, 491 * read-only. XXX RTL8180 only. 492 */ 493 #define RTW_CONFIG3_FBTBEN BIT(0) /* Fast back-to-back enabled, 494 * read-only. 495 */ 496 #define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */ 497 #define RTW_CONFIG4_VCOPDN BIT(7) /* VCO Power Down 498 * 0: normal operation 499 * (power-on default) 500 * 1: power-down VCO, RF front-end, 501 * and most RTL8180 components. 502 */ 503 #define RTW_CONFIG4_PWROFF BIT(6) /* Power Off 504 * 0: normal operation 505 * (power-on default) 506 * 1: power-down RF front-end, 507 * and most RTL8180 components, 508 * but leave VCO on. 509 * 510 * XXX RFMD front-end only? 511 */ 512 #define RTW_CONFIG4_PWRMGT BIT(5) /* Power Management 513 * 0: normal operation 514 * (power-on default) 515 * 1: set Tx packet's PWRMGMT bit. 516 */ 517 #define RTW_CONFIG4_LWPME BIT(4) /* LANWAKE vs. PMEB: Cardbus-only 518 * 0: LWAKE & PMEB asserted 519 * simultaneously 520 * 1: LWAKE asserted only if 521 * both PMEB is asserted and 522 * ISOLATEB is low. 523 * XXX RTL8180 only. 524 */ 525 #define RTW_CONFIG4_LWPTN BIT(2) /* see RTW_CONFIG1_LWACT 526 * XXX RTL8180 only. 527 */ 528 /* Radio Front-End Programming Method */ 529 #define RTW_CONFIG4_RFTYPE_MASK BITS(1,0) 530 #define RTW_CONFIG4_RFTYPE_INTERSIL SHIFTIN(1, RTW_CONFIG4_RFTYPE_MASK) 531 #define RTW_CONFIG4_RFTYPE_RFMD SHIFTIN(2, RTW_CONFIG4_RFTYPE_MASK) 532 #define RTW_CONFIG4_RFTYPE_PHILIPS SHIFTIN(3, RTW_CONFIG4_RFTYPE_MASK) 533 534 #define RTW_TESTR 0x5B /* TEST mode register, 8b */ 535 536 #define RTW_PSR 0x5e /* Page Select Register, 8b */ 537 #define RTW_PSR_GPO BIT(7) /* Control/status of pin 52. */ 538 #define RTW_PSR_GPI BIT(6) /* Status of pin 64. */ 539 #define RTW_PSR_LEDGPO1 BIT(5) /* Status/control of LED1 pin if 540 * RTW_CONFIG0_LEDGPOEN is set. 541 */ 542 #define RTW_PSR_LEDGPO0 BIT(4) /* Status/control of LED0 pin if 543 * RTW_CONFIG0_LEDGPOEN is set. 544 */ 545 #define RTW_PSR_UWF BIT(1) /* Enable Unicast Wakeup Frame */ 546 #define RTW_PSR_PSEN BIT(0) /* 1: page 1, 0: page 0 */ 547 548 #define RTW_SCR 0x5f /* Security Configuration Register, 8b */ 549 #define RTW_SCR_KM_MASK BITS(5,4) /* Key Mode */ 550 #define RTW_SCR_KM_WEP104 SHIFTIN(1, RTW_SCR_KM_MASK) 551 #define RTW_SCR_KM_WEP40 SHIFTIN(0, RTW_SCR_KM_MASK) 552 #define RTW_SCR_TXSECON BIT(1) /* Enable Tx WEP. Invalid if 553 * neither RTW_CONFIG0_WEP40 nor 554 * RTW_CONFIG0_WEP104 is set. 555 */ 556 #define RTW_SCR_RXSECON BIT(0) /* Enable Rx WEP. Invalid if 557 * neither RTW_CONFIG0_WEP40 nor 558 * RTW_CONFIG0_WEP104 is set. 559 */ 560 561 #define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */ 562 #define RTW_BCNITV_BCNITV_MASK BITS(9,0) /* TU between TBTT, written 563 * by host. 564 */ 565 #define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */ 566 #define RTW_ATIMWND_ATIMWND BITS(9,0) /* ATIM Window length in TU, 567 * written by host. 568 */ 569 570 #define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */ 571 #define RTW_BINTRITV_BINTRITV BITS(9,0) /* RTL8180 wakes host with 572 * RTW_INTR_BCNINT at BINTRITV 573 * microseconds before TBTT 574 */ 575 #define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */ 576 #define RTW_ATIMTRITV_ATIMTRITV BITS(9,0) /* RTL8180 wakes host with 577 * RTW_INTR_ATIMINT at ATIMTRITV 578 * microseconds before end of 579 * ATIM Window 580 */ 581 582 #define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */ 583 #define RTW_PHYDELAY_REVC_MAGIC BIT(3) /* Rev. C magic from reference 584 * driver 585 */ 586 #define RTW_PHYDELAY_PHYDELAY BITS(2,0) /* microsecond Tx delay between 587 * MAC and RF front-end 588 */ 589 #define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */ 590 #define RTW_CRCOUNT_MAGIC 0x4c 591 592 #define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */ 593 594 #define RTW_BB 0x7c /* Baseband interface, 32b */ 595 /* used for writing RTL8180's integrated baseband processor */ 596 #define RTW_BB_RD_MASK BITS(23,16) /* data to read */ 597 #define RTW_BB_WR_MASK BITS(15,8) /* data to write */ 598 #define RTW_BB_WREN BIT(7) /* write enable */ 599 #define RTW_BB_ADDR_MASK BITS(6,0) /* address */ 600 601 #define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */ 602 #define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */ 603 #define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */ 604 605 #define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */ 606 #define RTW_PHYCFG_MAC_POLL BIT(31) /* if !RTW_PHYCFG_HST, 607 * host sets. MAC clears 608 * after banging bits. 609 */ 610 #define RTW_PHYCFG_HST BIT(30) /* 1: host bangs bits 611 * 0: MAC bangs bits 612 */ 613 #define RTW_PHYCFG_MAC_RFTYPE_MASK BITS(29,28) 614 #define RTW_PHYCFG_MAC_RFTYPE_INTERSIL SHIFTIN(0, RTW_PHYCFG_MAC_RFTYPE_MASK) 615 #define RTW_PHYCFG_MAC_RFTYPE_RFMD SHIFTIN(1, RTW_PHYCFG_MAC_RFTYPE_MASK) 616 #define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD 617 #define RTW_PHYCFG_MAC_RFTYPE_PHILIPS SHIFTIN(3, RTW_PHYCFG_MAC_RFTYPE_MASK) 618 #define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK BITS(27,24) 619 #define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK BITS(23,0) 620 #define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK BITS(27,24) 621 #define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK BITS(11,8) 622 #define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK BITS(7,0) 623 #define RTW_PHYCFG_HST_EN BIT(2) 624 #define RTW_PHYCFG_HST_CLK BIT(1) 625 #define RTW_PHYCFG_HST_DATA BIT(0) 626 627 #define RTW_MAXIM_HIDATA_MASK BITS(11,4) 628 #define RTW_MAXIM_LODATA_MASK BITS(3,0) 629 630 /** 631 ** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1. 632 **/ 633 634 #define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */ 635 #define RTW_WAKEUP0H 0x88 /* 32b */ 636 637 #define RTW_WAKEUP1L 0x8c 638 #define RTW_WAKEUP1H 0x90 639 640 #define RTW_WAKEUP2LL 0x94 641 #define RTW_WAKEUP2LH 0x98 642 643 #define RTW_WAKEUP2HL 0x9c 644 #define RTW_WAKEUP2HH 0xa0 645 646 #define RTW_WAKEUP3LL 0xa4 647 #define RTW_WAKEUP3LH 0xa8 648 649 #define RTW_WAKEUP3HL 0xac 650 #define RTW_WAKEUP3HH 0xb0 651 652 #define RTW_WAKEUP4LL 0xb4 653 #define RTW_WAKEUP4LH 0xb8 654 655 #define RTW_WAKEUP4HL 0xbc 656 #define RTW_WAKEUP4HH 0xc0 657 658 #define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */ 659 #define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */ 660 #define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */ 661 #define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */ 662 #define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */ 663 664 /** 665 ** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0. 666 **/ 667 668 /* Default Key Registers, each 128b 669 * 670 * If RTW_SCR_KM_WEP104, 104 lsb are the key. 671 * If RTW_SCR_KM_WEP40, 40 lsb are the key. 672 */ 673 #define RTW_DK0 0x90 /* Default Key 0 Register, 128b */ 674 #define RTW_DK1 0xa0 /* Default Key 1 Register, 128b */ 675 #define RTW_DK2 0xb0 /* Default Key 2 Register, 128b */ 676 #define RTW_DK3 0xc0 /* Default Key 3 Register, 128b */ 677 678 #define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */ 679 #define RTW_CONFIG5_TXFIFOOK BIT(7) /* Tx FIFO self-test pass, read-only */ 680 #define RTW_CONFIG5_RXFIFOOK BIT(6) /* Rx FIFO self-test pass, read-only */ 681 #define RTW_CONFIG5_CALON BIT(5) /* 1: start calibration cycle 682 * and raise AGCRESET pin. 683 * 0: lower AGCRESET pin 684 */ 685 #define RTW_CONFIG5_EACPI BIT(2) /* Enable ACPI Wake up, default 0 */ 686 #define RTW_CONFIG5_LANWAKE BIT(1) /* Enable LAN Wake signal, 687 * from EEPROM 688 */ 689 #define RTW_CONFIG5_PMESTS BIT(0) /* 1: both software & PCI Reset 690 * reset PME_Status 691 * 0: only software resets PME_Status 692 * 693 * From EEPROM. 694 */ 695 696 #define RTW_TPPOLL 0xd9 /* Transmit Priority Polling Register, 8b, 697 * write-only. 698 */ 699 #define RTW_TPPOLL_BQ BIT(7) /* RTL8180 clears to notify host of a beacon 700 * Tx. Host writes have no effect. 701 */ 702 #define RTW_TPPOLL_HPQ BIT(6) /* Host writes 1 to notify RTL8180 of 703 * high-priority Tx packets, RTL8180 clears 704 * to after high-priority Tx is complete. 705 */ 706 #define RTW_TPPOLL_NPQ BIT(5) /* If RTW_CONFIG2_DPS is set, 707 * host writes 1 to notify RTL8180 of 708 * normal-priority Tx packets, RTL8180 clears 709 * after normal-priority Tx is complete. 710 * 711 * If RTW_CONFIG2_DPS is clear, host writes 712 * have no effect. RTL8180 clears after 713 * normal-priority Tx is complete. 714 */ 715 #define RTW_TPPOLL_LPQ BIT(4) /* Host writes 1 to notify RTL8180 of 716 * low-priority Tx packets, RTL8180 clears 717 * after low-priority Tx is complete. 718 */ 719 #define RTW_TPPOLL_SBQ BIT(3) /* Host writes 1 to tell RTL8180 to 720 * stop beacon DMA. This bit is invalid 721 * when RTW_CONFIG2_DPS is set. 722 */ 723 #define RTW_TPPOLL_SHPQ BIT(2) /* Host writes 1 to tell RTL8180 to 724 * stop high-priority DMA. 725 */ 726 #define RTW_TPPOLL_SNPQ BIT(1) /* Host writes 1 to tell RTL8180 to 727 * stop normal-priority DMA. This bit is invalid 728 * when RTW_CONFIG2_DPS is set. 729 */ 730 #define RTW_TPPOLL_SLPQ BIT(0) /* Host writes 1 to tell RTL8180 to 731 * stop low-priority DMA. 732 */ 733 734 /* Start all queues. */ 735 #define RTW_TPPOLL_ALL (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \ 736 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ) 737 /* Check all queues' activity. */ 738 #define RTW_TPPOLL_ACTIVE RTW_TPPOLL_ALL 739 /* Stop all queues. */ 740 #define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \ 741 RTW_TPPOLL_SNPQ | RTW_TPPOLL_SLPQ) 742 743 #define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */ 744 /* Contention Window: indicates number of contention windows before Tx 745 */ 746 #define RTW_CWR_CW BITS(9,0) 747 748 /* Retry Count Register, 16b, read-only */ 749 #define RTW_RETRYCTR 0xde 750 /* Retry Count: indicates number of retries after Tx */ 751 #define RTW_RETRYCTR_RETRYCT BITS(7,0) 752 753 #define RTW_RDSAR 0xe4 /* Receive descriptor Start Address Register, 754 * 32b, 256-byte alignment. 755 */ 756 /* Function Event Register, 32b, Cardbus only. Only valid when 757 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 758 */ 759 #define RTW_FER 0xf0 760 #define RTW_FER_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 761 #define RTW_FER_GWAKE BIT(4) /* General Wakeup */ 762 /* Function Event Mask Register, 32b, Cardbus only. Only valid when 763 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 764 */ 765 #define RTW_FEMR 0xf4 766 #define RTW_FEMR_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 767 #define RTW_FEMR_WKUP BIT(14) /* Wakeup Mask */ 768 #define RTW_FEMR_GWAKE BIT(4) /* General Wakeup */ 769 /* Function Present State Register, 32b, read-only, Cardbus only. 770 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 771 * are set. 772 */ 773 #define RTW_FPSR 0xf8 774 #define RTW_FPSR_INTR BIT(15) /* TBD */ 775 #define RTW_FPSR_GWAKE BIT(4) /* General Wakeup: TBD */ 776 /* Function Force Event Register, 32b, write-only, Cardbus only. 777 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 778 * are set. 779 */ 780 #define RTW_FFER 0xfc 781 #define RTW_FFER_INTR BIT(15) /* TBD */ 782 #define RTW_FFER_GWAKE BIT(4) /* General Wakeup: TBD */ 783 784 /* Serial EEPROM offsets */ 785 #define RTW_SR_ID 0x00 /* 16b */ 786 #define RTW_SR_VID 0x02 /* 16b */ 787 #define RTW_SR_DID 0x04 /* 16b */ 788 #define RTW_SR_SVID 0x06 /* 16b */ 789 #define RTW_SR_SMID 0x08 /* 16b */ 790 #define RTW_SR_MNGNT 0x0a 791 #define RTW_SR_MXLAT 0x0b 792 #define RTW_SR_RFCHIPID 0x0c 793 #define RTW_SR_CONFIG3 0x0d 794 #define RTW_SR_MAC 0x0e /* 6 bytes */ 795 #define RTW_SR_CONFIG0 0x14 796 #define RTW_SR_CONFIG1 0x15 797 #define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */ 798 #define RTW_SR_CONFIG2 0x18 799 #define RTW_SR_CONFIG4 0x19 800 #define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */ 801 #define RTW_SR_TESTR 0x1e 802 #define RTW_SR_CONFIG5 0x1f 803 #define RTW_SR_TXPOWER1 0x20 804 #define RTW_SR_TXPOWER2 0x21 805 #define RTW_SR_TXPOWER3 0x22 806 #define RTW_SR_TXPOWER4 0x23 807 #define RTW_SR_TXPOWER5 0x24 808 #define RTW_SR_TXPOWER6 0x25 809 #define RTW_SR_TXPOWER7 0x26 810 #define RTW_SR_TXPOWER8 0x27 811 #define RTW_SR_TXPOWER9 0x28 812 #define RTW_SR_TXPOWER10 0x29 813 #define RTW_SR_TXPOWER11 0x2a 814 #define RTW_SR_TXPOWER12 0x2b 815 #define RTW_SR_TXPOWER13 0x2c 816 #define RTW_SR_TXPOWER14 0x2d 817 #define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */ 818 #define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */ 819 #define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */ 820 #define RTW_SR_CISPOINTER 0x30 /* 16b */ 821 #define RTW_SR_RFPARM 0x32 /* RF-specific parameter */ 822 #define RTW_SR_RFPARM_DIGPHY BIT(0) /* 1: digital PHY */ 823 #define RTW_SR_RFPARM_DFLANTB BIT(1) /* 1: antenna B is default */ 824 #define RTW_SR_RFPARM_CS_MASK BITS(2,3) /* carrier-sense type */ 825 #define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */ 826 #define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */ 827 #define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */ 828 #define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes*/ 829 830 /* 831 * RTL8180 Transmit/Receive Descriptors 832 */ 833 834 /* the first descriptor in each ring must be on a 256-byte boundary */ 835 #define RTW_DESC_ALIGNMENT 256 836 837 /* Tx descriptor */ 838 struct rtw_txdesc { 839 uint32_t td_ctl0; 840 uint32_t td_ctl1; 841 uint32_t td_buf; 842 uint32_t td_len; 843 uint32_t td_next; 844 uint32_t td_rsvd[3]; 845 }; 846 847 #define td_stat td_ctl0 848 849 #define RTW_TXCTL0_OWN BIT(31) /* 1: ready to Tx */ 850 #define RTW_TXCTL0_RSVD0 BIT(30) /* reserved */ 851 #define RTW_TXCTL0_FS BIT(29) /* first segment */ 852 #define RTW_TXCTL0_LS BIT(28) /* last segment */ 853 854 #define RTW_TXCTL0_RATE_MASK BITS(27,24) /* Tx rate */ 855 #define RTW_TXCTL0_RATE_1MBPS SHIFTIN(0, RTW_TXCTL0_RATE_MASK) 856 #define RTW_TXCTL0_RATE_2MBPS SHIFTIN(1, RTW_TXCTL0_RATE_MASK) 857 #define RTW_TXCTL0_RATE_5MBPS SHIFTIN(2, RTW_TXCTL0_RATE_MASK) 858 #define RTW_TXCTL0_RATE_11MBPS SHIFTIN(3, RTW_TXCTL0_RATE_MASK) 859 860 #define RTW_TXCTL0_RTSEN BIT(23) /* RTS Enable */ 861 862 #define RTW_TXCTL0_RTSRATE_MASK BITS(22,19) /* Tx rate */ 863 #define RTW_TXCTL0_RTSRATE_1MBPS SHIFTIN(0, RTW_TXCTL0_RTSRATE_MASK) 864 #define RTW_TXCTL0_RTSRATE_2MBPS SHIFTIN(1, RTW_TXCTL0_RTSRATE_MASK) 865 #define RTW_TXCTL0_RTSRATE_5MBPS SHIFTIN(2, RTW_TXCTL0_RTSRATE_MASK) 866 #define RTW_TXCTL0_RTSRATE_11MBPS SHIFTIN(3, RTW_TXCTL0_RTSRATE_MASK) 867 868 #define RTW_TXCTL0_BEACON BIT(18) /* packet is a beacon */ 869 #define RTW_TXCTL0_MOREFRAG BIT(17) /* another fragment follows */ 870 #define RTW_TXCTL0_SPLCP BIT(16) /* add short PLCP preamble 871 * and header 872 */ 873 #define RTW_TXCTL0_KEYID_MASK BITS(15,14) /* default key id */ 874 #define RTW_TXCTL0_RSVD1_MASK BITS(13,12) /* reserved */ 875 #define RTW_TXCTL0_TPKTSIZE_MASK BITS(11,0) /* Tx packet size 876 * in bytes 877 */ 878 879 #define RTW_TXSTAT_OWN RTW_TXCTL0_OWN 880 #define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0 881 #define RTW_TXSTAT_FS RTW_TXCTL0_FS 882 #define RTW_TXSTAT_LS RTW_TXCTL0_LS 883 #define RTW_TXSTAT_RSVD1_MASK BITS(27,16) 884 #define RTW_TXSTAT_TOK BIT(15) 885 #define RTW_TXSTAT_RTSRETRY_MASK BITS(14,8) /* RTS retry count */ 886 #define RTW_TXSTAT_DRC_MASK BITS(7,0) /* Data retry count */ 887 888 #define RTW_TXCTL1_LENGEXT BIT(31) /* supplements _LENGTH 889 * in packets sent 5.5Mb/s or 890 * faster 891 */ 892 #define RTW_TXCTL1_LENGTH_MASK BITS(30,16) /* PLCP length (microseconds) */ 893 #define RTW_TXCTL1_RTSDUR_MASK BITS(15,0) /* RTS Duration 894 * (microseconds) 895 */ 896 897 #define RTW_TXLEN_LENGTH_MASK BITS(11,0) /* Tx buffer length in bytes */ 898 899 /* Rx descriptor */ 900 struct rtw_rxdesc { 901 uint32_t rd_ctl; 902 uint32_t rd_rsvd0; 903 uint32_t rd_buf; 904 uint32_t rd_rsvd1; 905 }; 906 907 #define rd_stat rd_ctl 908 #define rd_rssi rd_rsvd0 909 #define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */ 910 #define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */ 911 912 #define RTW_RXCTL_OWN BIT(31) /* 1: owned by NIC */ 913 #define RTW_RXCTL_EOR BIT(30) /* end of ring */ 914 #define RTW_RXCTL_FS BIT(29) /* first segment */ 915 #define RTW_RXCTL_LS BIT(28) /* last segment */ 916 #define RTW_RXCTL_RSVD0_MASK BITS(29,12) /* reserved */ 917 #define RTW_RXCTL_LENGTH_MASK BITS(11,0) /* Rx buffer length */ 918 919 #define RTW_RXSTAT_OWN RTW_RXCTL_OWN 920 #define RTW_RXSTAT_EOR RTW_RXCTL_EOR 921 #define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */ 922 #define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */ 923 #define RTW_RXSTAT_DMAFAIL BIT(27) /* DMA failure on this pkt */ 924 #define RTW_RXSTAT_BOVF BIT(26) /* buffer overflow XXX means 925 * FIFO exhausted? 926 */ 927 #define RTW_RXSTAT_SPLCP BIT(25) /* Rx'd with short preamble 928 * and PLCP header 929 */ 930 #define RTW_RXSTAT_RSVD1 BIT(24) /* reserved */ 931 #define RTW_RXSTAT_RATE_MASK BITS(23,20) /* Rx rate */ 932 #define RTW_RXSTAT_RATE_1MBPS SHIFTIN(0, RTW_RXSTAT_RATE_MASK) 933 #define RTW_RXSTAT_RATE_2MBPS SHIFTIN(1, RTW_RXSTAT_RATE_MASK) 934 #define RTW_RXSTAT_RATE_5MBPS SHIFTIN(2, RTW_RXSTAT_RATE_MASK) 935 #define RTW_RXSTAT_RATE_11MBPS SHIFTIN(3, RTW_RXSTAT_RATE_MASK) 936 #define RTW_RXSTAT_MIC BIT(19) /* XXX from reference driver */ 937 #define RTW_RXSTAT_MAR BIT(18) /* is multicast */ 938 #define RTW_RXSTAT_PAR BIT(17) /* matches RTL8180's MAC */ 939 #define RTW_RXSTAT_BAR BIT(16) /* is broadcast */ 940 #define RTW_RXSTAT_RES BIT(15) /* error summary. valid when 941 * RTW_RXSTAT_LS set. indicates 942 * that either RTW_RXSTAT_CRC32 943 * or RTW_RXSTAT_ICV is set. 944 */ 945 #define RTW_RXSTAT_PWRMGT BIT(14) /* 802.11 PWRMGMT bit is set */ 946 #define RTW_RXSTAT_CRC16 BIT(14) /* XXX CRC16 error, from 947 * reference driver 948 */ 949 #define RTW_RXSTAT_CRC32 BIT(13) /* CRC32 error */ 950 #define RTW_RXSTAT_ICV BIT(12) /* ICV error */ 951 #define RTW_RXSTAT_LENGTH_MASK BITS(11,0) /* frame length, including 952 * CRC32 953 */ 954 955 /* Convenient status conjunction. */ 956 #define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS) 957 /* Convenient status disjunctions. */ 958 #define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF) 959 #define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\ 960 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\ 961 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\ 962 RTW_RXSTAT_ICV) 963 964 965 #define RTW_RXRSSI_VLAN BITS(32,16) /* XXX from reference driver */ 966 /* for Philips RF front-ends */ 967 #define RTW_RXRSSI_RSSI BITS(15,8) /* RF energy at the PHY */ 968 /* for RF front-ends by Intersil, Maxim, RFMD */ 969 #define RTW_RXRSSI_IMR_RSSI BITS(15,9) /* RF energy at the PHY */ 970 #define RTW_RXRSSI_IMR_LNA BIT(8) /* 1: LNA activated */ 971 #define RTW_RXRSSI_SQ BITS(7,0) /* Barker code-lock quality */ 972 973 #define RTW_READ8(regs, ofs) \ 974 bus_space_read_1((regs)->r_bt, (regs)->r_bh, (ofs)) 975 976 #define RTW_READ16(regs, ofs) \ 977 bus_space_read_2((regs)->r_bt, (regs)->r_bh, (ofs)) 978 979 #define RTW_READ(regs, ofs) \ 980 bus_space_read_4((regs)->r_bt, (regs)->r_bh, (ofs)) 981 982 #define RTW_WRITE8(regs, ofs, val) \ 983 bus_space_write_1((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 984 985 #define RTW_WRITE16(regs, ofs, val) \ 986 bus_space_write_2((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 987 988 #define RTW_WRITE(regs, ofs, val) \ 989 bus_space_write_4((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 990 991 #define RTW_ISSET(regs, reg, mask) \ 992 (RTW_READ((regs), (reg)) & (mask)) 993 994 #define RTW_CLR(regs, reg, mask) \ 995 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask)) 996 997 /* bus_space(9) lied? */ 998 #ifndef BUS_SPACE_BARRIER_SYNC 999 #define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 1000 #endif 1001 1002 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ 1003 #define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ 1004 #endif 1005 1006 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE 1007 #define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ 1008 #endif 1009 1010 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ 1011 #define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE 1012 #endif 1013 1014 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE 1015 #define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE 1016 #endif 1017 1018 /* 1019 * Bus barrier 1020 * 1021 * Complete outstanding read and/or write ops on [reg0, reg1] 1022 * ([reg1, reg0]) before starting new ops on the same region. See 1023 * acceptable bus_space_barrier(9) for the flag definitions. 1024 */ 1025 #define RTW_BARRIER(regs, reg0, reg1, flags) \ 1026 bus_space_barrier((regs)->r_bh, (regs)->r_bt, \ 1027 MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags) 1028 1029 /* 1030 * Barrier convenience macros. 1031 */ 1032 /* sync */ 1033 #define RTW_SYNC(regs, reg0, reg1) \ 1034 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC) 1035 1036 /* write-before-write */ 1037 #define RTW_WBW(regs, reg0, reg1) \ 1038 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1039 1040 /* write-before-read */ 1041 #define RTW_WBR(regs, reg0, reg1) \ 1042 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 1043 1044 /* read-before-read */ 1045 #define RTW_RBR(regs, reg0, reg1) \ 1046 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ) 1047 1048 /* read-before-read */ 1049 #define RTW_RBW(regs, reg0, reg1) \ 1050 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 1051 1052 #define RTW_WBRW(regs, reg0, reg1) \ 1053 RTW_BARRIER(regs, reg0, reg1, \ 1054 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 1055 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1056 1057 /* 1058 * Registers for RTL8180L's built-in baseband modem. 1059 */ 1060 #define RTW_BBP_SYS1 0x00 1061 #define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */ 1062 #define RTW_BBP_LNADET 0x04 /* guess: low-noise amplifier activation 1063 * threshold 1064 */ 1065 #define RTW_BBP_IFAGCINI 0x05 /* guess: intermediate frequency (IF) 1066 * auto-gain control (AGC) initial value 1067 */ 1068 #define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */ 1069 #define RTW_BBP_IFAGCDET 0x07 /* guess: activation threshold for 1070 * IF AGC loop 1071 */ 1072 1073 #define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */ 1074 #define RTW_BBP_ANTATTEN_GCT_MAGIC 0xa3 1075 #define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91 1076 #define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92 1077 #define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93 1078 #define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3 1079 #define RTW_BBP_ANTATTEN_DFLANTB 0x40 1080 #define RTW_BBP_ANTATTEN_CHAN14 0x0c 1081 1082 #define RTW_BBP_TRL 0x11 /* guess: transmit/receive 1083 * switch latency 1084 */ 1085 #define RTW_BBP_SYS2 0x12 1086 #define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */ 1087 #define RTW_BBP_SYS2_RATE_MASK BITS(5,4) /* loopback rate? 1088 * 0: 1Mbps 1089 * 1: 2Mbps 1090 * 2: 5.5Mbps 1091 * 3: 11Mbps 1092 */ 1093 #define RTW_BBP_SYS3 0x13 1094 /* carrier-sense threshold */ 1095 #define RTW_BBP_SYS3_CSTHRESH_MASK BITS(0,3) 1096 #define RTW_BBP_CHESTLIM 0x19 /* guess: channel energy-detect 1097 * threshold 1098 */ 1099 #define RTW_BBP_CHSQLIM 0x1a /* guess: channel signal-quality 1100 * threshold 1101 */ 1102
Indexes created Tue Sep 30 10:09:55 GMT 2025