rtwreg.h revision 1.3
1 /* $NetBSD: rtwreg.h,v 1.3 2004/12/20 23:05:41 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* Macros for bit twiddling. */ 35 /* TBD factor w/ dev/ic/atwreg.h. */ 36 37 #ifndef _BIT_TWIDDLE 38 #define _BIT_TWIDDLE 39 /* nth bit, BIT(0) == 0x1. */ 40 #define BIT(n) (((n) == 32) ? 0 : ((u_int32_t)1 << (n))) 41 42 /* bits m through n, m < n. */ 43 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 44 45 /* find least significant bit that is set */ 46 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 47 48 /* for x a power of two and p a non-negative integer, is x a greater 49 * power than 2**p? 50 */ 51 #define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 52 53 #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 54 55 #define MASK_TO_SHIFT4(m) \ 56 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 57 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 58 : MASK_TO_SHIFT2((m))) 59 60 #define MASK_TO_SHIFT8(m) \ 61 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 62 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 63 : MASK_TO_SHIFT4((m))) 64 65 #define MASK_TO_SHIFT16(m) \ 66 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 67 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 68 : MASK_TO_SHIFT8((m))) 69 70 #define MASK_TO_SHIFT(m) \ 71 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 72 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 73 : MASK_TO_SHIFT16((m))) 74 75 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 76 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 77 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 78 #define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 79 80 #endif /* _BIT_TWIDDLE */ 81 82 /* RTL8180L Host Control and Status Registers */ 83 84 #define RTW_IDR0 0x00 /* ID Register: MAC addr, 6 bytes. 85 * Auto-loaded from EEPROM. Read by byte, 86 * by word, or by double word, but write 87 * only by double word. 88 */ 89 #define RTW_IDR1 0x04 90 91 #define RTW_MAR0 0x08 /* Multicast filter, 64b. */ 92 #define RTW_MAR1 0x0c 93 94 #define RTW_TSFTRL 0x18 /* Timing Synchronization Function Timer 95 * Register, low word, 32b, read-only. 96 */ 97 #define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */ 98 #define RTW_TLPDA 0x20 /* Transmit Low Priority Descriptors Start 99 * Address, 32b, 256-byte alignment. 100 */ 101 #define RTW_TNPDA 0x24 /* Transmit Normal Priority Descriptors Start 102 * Address, 32b, 256-byte alignment. 103 */ 104 #define RTW_THPDA 0x28 /* Transmit High Priority Descriptors Start 105 * Address, 32b, 256-byte alignment. 106 */ 107 108 #define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */ 109 #define RTW_BRSR_BPLCP BIT(8) /* 1: use short PLCP header for CTS/ACK packet, 110 * 0: use long PLCP header 111 */ 112 #define RTW_BRSR_MBR8180_MASK BITS(1,0) /* Maximum Basic Service Rate */ 113 #define RTW_BRSR_MBR8180_1MBPS LSHIFT(0, RTW_BRSR_MBR_MASK) 114 #define RTW_BRSR_MBR8180_2MBPS LSHIFT(1, RTW_BRSR_MBR_MASK) 115 #define RTW_BRSR_MBR8180_5MBPS LSHIFT(2, RTW_BRSR_MBR_MASK) 116 #define RTW_BRSR_MBR8180_11MBPS LSHIFT(3, RTW_BRSR_MBR_MASK) 117 118 /* 8181 and 8180 docs conflict! */ 119 #define RTW_BRSR_MBR8181_1MBPS BIT(0) 120 #define RTW_BRSR_MBR8181_2MBPS BIT(1) 121 #define RTW_BRSR_MBR8181_5MBPS BIT(2) 122 #define RTW_BRSR_MBR8181_11MBPS BIT(3) 123 124 #define RTW_BSSID 0x2e 125 /* BSSID, 6 bytes */ 126 #define RTW_BSSID16 0x2e /* first two bytes */ 127 #define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */ 128 #define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */ 129 #define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */ 130 #define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */ 131 #define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */ 132 #define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */ 133 #define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */ 134 135 #define RTW_CR 0x37 /* Command Register, 8b */ 136 #define RTW_CR_RST BIT(4) /* Reset: host sets to 1 to disable 137 * transmitter & receiver, reinitialize FIFO. 138 * RTL8180L sets to 0 to signal completion. 139 */ 140 #define RTW_CR_RE BIT(3) /* Receiver Enable: host enables receiver 141 * by writing 1. RTL8180L indicates receiver 142 * is active with 1. After power-up, host 143 * must wait for reset before writing. 144 */ 145 #define RTW_CR_TE BIT(2) /* Transmitter Enable: host enables transmitter 146 * by writing 1. RTL8180L indicates transmitter 147 * is active with 1. After power-up, host 148 * must wait for reset before writing. 149 */ 150 #define RTW_CR_MULRW BIT(0) /* PCI Multiple Read/Write enable: 1 enables, 151 * 0 disables. XXX RTL8180, only? 152 */ 153 154 #define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */ 155 #define RTW_ISR 0x3e /* Interrupt status register, 16b */ 156 157 #define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO Overflow */ 158 #define RTW_INTR_TIMEOUT BIT(14) /* Time Out: 1 indicates 159 * RTW_TSFTR[0:31] = RTW_TINT 160 */ 161 #define RTW_INTR_BCNINT BIT(13) /* Beacon Time Out: time for host to 162 * prepare beacon: 163 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 164 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV) 165 */ 166 #define RTW_INTR_ATIMINT BIT(12) 167 /* ATIM Time Out: ATIM interval will pass, 168 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 169 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV) 170 */ 171 #define RTW_INTR_TBDER BIT(11) /* Tx Beacon Descriptor Error: 172 * beacon transmission aborted because 173 * frame Rx'd 174 */ 175 #define RTW_INTR_TBDOK BIT(10) /* Tx Beacon Descriptor OK */ 176 #define RTW_INTR_THPDER BIT(9) /* Tx High Priority Descriptor Error: 177 * reached short/long retry limit 178 */ 179 #define RTW_INTR_THPDOK BIT(8) /* Tx High Priority Descriptor OK */ 180 #define RTW_INTR_TNPDER BIT(7) /* Tx Normal Priority Descriptor Error: 181 * reached short/long retry limit 182 */ 183 #define RTW_INTR_TNPDOK BIT(6) /* Tx Normal Priority Descriptor OK */ 184 #define RTW_INTR_RXFOVW BIT(5) /* Rx FIFO Overflow: either RDU (see below) 185 * or PCI bus too slow/busy 186 */ 187 #define RTW_INTR_RDU BIT(4) /* Rx Descriptor Unavailable */ 188 #define RTW_INTR_TLPDER BIT(3) /* Tx Normal Priority Descriptor Error 189 * reached short/long retry limit 190 */ 191 #define RTW_INTR_TLPDOK BIT(2) /* Tx Normal Priority Descriptor OK */ 192 #define RTW_INTR_RER BIT(1) /* Rx Error: CRC32 or ICV error */ 193 #define RTW_INTR_ROK BIT(0) /* Rx OK */ 194 195 /* Convenient interrupt conjunctions. */ 196 #define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK) 197 #define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\ 198 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK) 199 #define RTW_INTR_BEACON (RTW_INTR_TBDER|RTW_INTR_TBDOK|RTW_INTR_BCNINT) 200 #define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU) 201 202 #define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */ 203 #define RTW_TCR_CWMIN BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */ 204 #define RTW_TCR_SWSEQ BIT(30) /* 1: host assigns 802.11 sequence number, 205 * 0: hardware assigns sequence number 206 */ 207 /* Hardware version ID, read-only */ 208 #define RTW_TCR_HWVERID_MASK BITS(29, 25) 209 #define RTW_TCR_HWVERID_D LSHIFT(26, RTW_TCR_HWVERID_MASK) 210 #define RTW_TCR_HWVERID_F LSHIFT(27, RTW_TCR_HWVERID_MASK) 211 #define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F 212 213 /* Set ACK/CTS Timeout (EIFS). 214 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?) 215 * 0: ACK rate = 1Mbps 216 */ 217 #define RTW_TCR_SAT BIT(24) 218 /* Max DMA Burst Size per Tx DMA Burst */ 219 #define RTW_TCR_MXDMA_MASK BITS(23,21) 220 #define RTW_TCR_MXDMA_16 LSHIFT(0, RTW_TCR_MXDMA_MASK) 221 #define RTW_TCR_MXDMA_32 LSHIFT(1, RTW_TCR_MXDMA_MASK) 222 #define RTW_TCR_MXDMA_64 LSHIFT(2, RTW_TCR_MXDMA_MASK) 223 #define RTW_TCR_MXDMA_128 LSHIFT(3, RTW_TCR_MXDMA_MASK) 224 #define RTW_TCR_MXDMA_256 LSHIFT(4, RTW_TCR_MXDMA_MASK) 225 #define RTW_TCR_MXDMA_512 LSHIFT(5, RTW_TCR_MXDMA_MASK) 226 #define RTW_TCR_MXDMA_1024 LSHIFT(6, RTW_TCR_MXDMA_MASK) 227 #define RTW_TCR_MXDMA_2048 LSHIFT(7, RTW_TCR_MXDMA_MASK) 228 229 #define RTW_TCR_DISCW BIT(20) /* disable 802.11 random backoff */ 230 231 #define RTW_TCR_ICV BIT(19) /* host lets RTL8180 append ICV to 232 * WEP packets 233 */ 234 235 /* Loopback Test: disables TXI/TXQ outputs. */ 236 #define RTW_TCR_LBK_MASK BITS(18,17) 237 #define RTW_TCR_LBK_NORMAL LSHIFT(0, RTW_TCR_LBK_MASK) /* normal ops */ 238 #define RTW_TCR_LBK_MAC LSHIFT(1, RTW_TCR_LBK_MASK) /* MAC loopback */ 239 #define RTW_TCR_LBK_BBP LSHIFT(2, RTW_TCR_LBK_MASK) /* baseband loop. */ 240 #define RTW_TCR_LBK_CONT LSHIFT(3, RTW_TCR_LBK_MASK) /* continuous Tx */ 241 242 #define RTW_TCR_CRC BIT(16) /* host lets RTL8180 append CRC32 */ 243 #define RTW_TCR_SRL_MASK BITS(15,8) /* Short Retry Limit */ 244 #define RTW_TCR_LRL_MASK BITS(7,0) /* Long Retry Limit */ 245 246 #define RTW_RCR 0x44 /* Receive Configuration Register, 32b */ 247 #define RTW_RCR_ONLYERLPKT BIT(31) /* only do Early Rx on packets 248 * longer than 1536 bytes 249 */ 250 #define RTW_RCR_ENCS2 BIT(30) /* enable carrier sense method 2 */ 251 #define RTW_RCR_ENCS1 BIT(29) /* enable carrier sense method 1 */ 252 #define RTW_RCR_ENMARP BIT(28) /* enable MAC auto-reset PHY */ 253 #define RTW_RCR_CBSSID BIT(23) /* Check BSSID/ToDS/FromDS: set 254 * "Link On" when received BSSID 255 * matches RTW_BSSID and received 256 * ToDS/FromDS are appropriate 257 * according to RTW_MSR_NETYPE. 258 */ 259 #define RTW_RCR_APWRMGT BIT(22) /* accept packets w/ PWRMGMT bit set */ 260 #define RTW_RCR_ADD3 BIT(21) /* when RTW_MSR_NETYPE == 261 * RTW_MSR_NETYPE_INFRA_OK, accept 262 * broadcast/multicast packets whose 263 * 3rd address matches RTL8180's MAC. 264 */ 265 #define RTW_RCR_AMF BIT(20) /* accept management frames */ 266 #define RTW_RCR_ACF BIT(19) /* accept control frames */ 267 #define RTW_RCR_ADF BIT(18) /* accept data frames */ 268 /* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data 269 * bytes are received 270 */ 271 #define RTW_RCR_RXFTH_MASK BITS(15,13) 272 #define RTW_RCR_RXFTH_64 LSHIFT(2, RTW_RCR_RXFTH_MASK) 273 #define RTW_RCR_RXFTH_128 LSHIFT(3, RTW_RCR_RXFTH_MASK) 274 #define RTW_RCR_RXFTH_256 LSHIFT(4, RTW_RCR_RXFTH_MASK) 275 #define RTW_RCR_RXFTH_512 LSHIFT(5, RTW_RCR_RXFTH_MASK) 276 #define RTW_RCR_RXFTH_1024 LSHIFT(6, RTW_RCR_RXFTH_MASK) 277 #define RTW_RCR_RXFTH_WHOLE LSHIFT(7, RTW_RCR_RXFTH_MASK) 278 279 #define RTW_RCR_AICV BIT(12) /* accept frames w/ ICV errors */ 280 281 /* Max DMA Burst Size per Rx DMA Burst */ 282 #define RTW_RCR_MXDMA_MASK BITS(10,8) 283 #define RTW_RCR_MXDMA_16 LSHIFT(0, RTW_RCR_MXDMA_MASK) 284 #define RTW_RCR_MXDMA_32 LSHIFT(1, RTW_RCR_MXDMA_MASK) 285 #define RTW_RCR_MXDMA_64 LSHIFT(2, RTW_RCR_MXDMA_MASK) 286 #define RTW_RCR_MXDMA_128 LSHIFT(3, RTW_RCR_MXDMA_MASK) 287 #define RTW_RCR_MXDMA_256 LSHIFT(4, RTW_RCR_MXDMA_MASK) 288 #define RTW_RCR_MXDMA_512 LSHIFT(5, RTW_RCR_MXDMA_MASK) 289 #define RTW_RCR_MXDMA_1024 LSHIFT(6, RTW_RCR_MXDMA_MASK) 290 #define RTW_RCR_MXDMA_UNLIMITED LSHIFT(7, RTW_RCR_MXDMA_MASK) 291 292 /* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */ 293 #define RTW_RCR_9356SEL BIT(6) 294 295 #define RTW_RCR_ACRC32 BIT(5) /* accept frames w/ CRC32 errors */ 296 #define RTW_RCR_AB BIT(3) /* accept broadcast frames */ 297 #define RTW_RCR_AM BIT(2) /* accept multicast frames */ 298 /* accept physical match frames. XXX means PLCP header ok? */ 299 #define RTW_RCR_APM BIT(1) 300 #define RTW_RCR_AAP BIT(0) /* accept frames w/ destination */ 301 302 #define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */ 303 #define RTW_TBDA 0x4c /* Transmit Beacon Descriptor Start Address, 304 * 32b, 256-byte alignment 305 */ 306 #define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */ 307 #define RTW_9346CR_EEM_MASK BITS(7,6) /* Operating Mode */ 308 #define RTW_9346CR_EEM_NORMAL LSHIFT(0, RTW_9346CR_EEM_MASK) 309 /* Load the EEPROM. Reset registers to defaults. 310 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL. 311 * XXX RTL8180 only? 312 */ 313 #define RTW_9346CR_EEM_AUTOLOAD LSHIFT(1, RTW_9346CR_EEM_MASK) 314 /* Disable network & bus-master operations and enable 315 * _EECS, _EESK, _EEDI, _EEDO. 316 * XXX RTL8180 only? 317 */ 318 #define RTW_9346CR_EEM_PROGRAM LSHIFT(2, RTW_9346CR_EEM_MASK) 319 /* Enable RTW_CONFIG[0123] registers. */ 320 #define RTW_9346CR_EEM_CONFIG LSHIFT(3, RTW_9346CR_EEM_MASK) 321 /* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes. 322 * XXX RTL8180 only? 323 */ 324 #define RTW_9346CR_EECS BIT(3) 325 #define RTW_9346CR_EESK BIT(2) 326 #define RTW_9346CR_EEDI BIT(1) 327 #define RTW_9346CR_EEDO BIT(0) /* read-only */ 328 329 #define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */ 330 #define RTW_CONFIG0_WEP40 BIT(7) /* implements 40-bit WEP, 331 * XXX RTL8180 only? 332 */ 333 #define RTW_CONFIG0_WEP104 BIT(6) /* implements 104-bit WEP, 334 * from EEPROM, read-only 335 * XXX RTL8180 only? 336 */ 337 #define RTW_CONFIG0_LEDGPOEN BIT(4) /* 1: RTW_PSR_LEDGPO[01] control 338 * LED[01] pins. 339 * 0: LED behavior defined by 340 * RTW_CONFIG1_LEDS10_MASK 341 * XXX RTL8180 only? 342 */ 343 /* auxiliary power is present, read-only */ 344 #define RTW_CONFIG0_AUXPWR BIT(3) 345 /* Geographic Location, read-only */ 346 #define RTW_CONFIG0_GL_MASK BITS(1,0) 347 /* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_* 348 * work. 349 */ 350 #define _RTW_CONFIG0_GL_USA LSHIFT(3, RTW_CONFIG0_GL_MASK) 351 #define RTW_CONFIG0_GL_EUROPE LSHIFT(2, RTW_CONFIG0_GL_MASK) 352 #define RTW_CONFIG0_GL_JAPAN LSHIFT(1, RTW_CONFIG0_GL_MASK) 353 #define RTW_CONFIG0_GL_USA LSHIFT(0, RTW_CONFIG0_GL_MASK) 354 /* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */ 355 356 #define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */ 357 358 /* LED configuration. From EEPROM. Read/write. 359 * 360 * Setting LED0 LED1 361 * ------- ---- ---- 362 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure 363 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link 364 * RTW_CONFIG1_LEDS_TX_RX Tx Rx 365 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure 366 */ 367 #define RTW_CONFIG1_LEDS_MASK BITS(7,6) 368 #define RTW_CONFIG1_LEDS_ACT_INFRA LSHIFT(0, RTW_CONFIG1_LEDS_MASK) 369 #define RTW_CONFIG1_LEDS_ACT_LINK LSHIFT(1, RTW_CONFIG1_LEDS_MASK) 370 #define RTW_CONFIG1_LEDS_TX_RX LSHIFT(2, RTW_CONFIG1_LEDS_MASK) 371 #define RTW_CONFIG1_LEDS_LINKACT_INFRA LSHIFT(3, RTW_CONFIG1_LEDS_MASK) 372 373 /* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms. 374 * 375 * RTW_CONFIG1_LWACT 376 * 0 1 377 * RTW_CONFIG4_LWPTN 0 active high active low 378 * 1 positive pulse negative pulse 379 */ 380 #define RTW_CONFIG1_LWACT BIT(4) 381 382 #define RTW_CONFIG1_MEMMAP BIT(3) /* using PCI memory space, read-only */ 383 #define RTW_CONFIG1_IOMAP BIT(2) /* using PCI I/O space, read-only */ 384 #define RTW_CONFIG1_VPD BIT(1) /* if set, VPD from offsets 385 * 0x40-0x7f in EEPROM are at 386 * registers 0x60-0x67 of PCI 387 * Configuration Space (XXX huh?) 388 */ 389 #define RTW_CONFIG1_PMEN BIT(0) /* Power Management Enable: TBD */ 390 391 #define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */ 392 #define RTW_CONFIG2_LCK BIT(7) /* clocks are locked, read-only: 393 * Tx frequency & symbol clocks 394 * are derived from the same OSC 395 */ 396 #define RTW_CONFIG2_ANT BIT(6) /* diversity enabled, read-only */ 397 #define RTW_CONFIG2_DPS BIT(3) /* Descriptor Polling State: enable 398 * test mode. 399 */ 400 #define RTW_CONFIG2_PAPESIGN BIT(2) /* TBD, from EEPROM */ 401 #define RTW_CONFIG2_PAPETIME_MASK BITS(1,0) /* TBD, from EEPROM */ 402 403 #define RTW_ANAPARM 0x54 /* Analog parameter, 32b */ 404 #define RTW_ANAPARM_RFPOW0_MASK BITS(30,28) /* undocumented bits 405 * which appear to 406 * control the power 407 * state of the RF 408 * components 409 */ 410 #define RTW_ANAPARM_RFPOW_MASK \ 411 (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK) 412 413 #define RTW_ANAPARM_TXDACOFF BIT(27) /* 1: disable Tx DAC, 414 * 0: enable 415 */ 416 #define RTW_ANAPARM_RFPOW1_MASK BITS(26,20) /* undocumented bits 417 * which appear to 418 * control the power 419 * state of the RF 420 * components 421 */ 422 423 /* 424 * Maxim On/Sleep/Off control 425 */ 426 #define RTW_ANAPARM_RFPOW_MAXIM_ON LSHIFT(0x8, RTW_ANAPARM_RFPOW1_MASK) 427 428 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 429 #define RTW_ANAPARM_RFPOW_MAXIM_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 430 431 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 432 #define RTW_ANAPARM_RFPOW_MAXIM_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 433 434 /* 435 * RFMD On/Sleep/Off control 436 */ 437 #define RTW_ANAPARM_RFPOW_RFMD_ON LSHIFT(0x408, RTW_ANAPARM_RFPOW1_MASK) 438 439 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 440 #define RTW_ANAPARM_RFPOW_RFMD_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 441 442 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 443 #define RTW_ANAPARM_RFPOW_RFMD_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 444 445 /* 446 * Philips On/Sleep/Off control 447 */ 448 #define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \ 449 LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK) 450 #define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \ 451 LSHIFT(0x008, RTW_ANAPARM_RFPOW1_MASK) 452 453 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 454 #define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\ 455 LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 456 457 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 458 #define RTW_ANAPARM_RFPOW_PHILIPS_OFF\ 459 LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 460 461 #define RTW_ANAPARM_RFPOW_PHILIPS_ON LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK) 462 463 #define RTW_ANAPARM_CARDSP_MASK BITS(19,0) /* undocumented 464 * card-specific 465 * bits from the 466 * EEPROM. 467 */ 468 469 #define RTW_MSR 0x58 /* Media Status Register, 8b */ 470 /* Network Type and Link Status */ 471 #define RTW_MSR_NETYPE_MASK BITS(3,2) 472 /* AP, XXX RTL8181 only? */ 473 #define RTW_MSR_NETYPE_AP_OK LSHIFT(3, RTW_MSR_NETYPE_MASK) 474 /* infrastructure link ok */ 475 #define RTW_MSR_NETYPE_INFRA_OK LSHIFT(2, RTW_MSR_NETYPE_MASK) 476 /* ad-hoc link ok */ 477 #define RTW_MSR_NETYPE_ADHOC_OK LSHIFT(1, RTW_MSR_NETYPE_MASK) 478 /* no link */ 479 #define RTW_MSR_NETYPE_NOLINK LSHIFT(0, RTW_MSR_NETYPE_MASK) 480 481 #define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */ 482 #define RTW_CONFIG3_GNTSEL BIT(7) /* Grant Select, read-only */ 483 #define RTW_CONFIG3_PARMEN BIT(6) /* Set RTW_CONFIG3_PARMEN and 484 * RTW_9346CR_EEM_CONFIG to 485 * allow RTW_ANAPARM writes. 486 */ 487 #define RTW_CONFIG3_MAGIC BIT(5) /* Valid when RTW_CONFIG1_PMEN is 488 * set. If set, RTL8180 wakes up 489 * OS when Magic Packet is Rx'd. 490 */ 491 #define RTW_CONFIG3_CARDBEN BIT(3) /* Cardbus-related registers 492 * and functions are enabled, 493 * read-only. XXX RTL8180 only. 494 */ 495 #define RTW_CONFIG3_CLKRUNEN BIT(2) /* CLKRUN enabled, read-only. 496 * XXX RTL8180 only. 497 */ 498 #define RTW_CONFIG3_FUNCREGEN BIT(1) /* Function Registers Enabled, 499 * read-only. XXX RTL8180 only. 500 */ 501 #define RTW_CONFIG3_FBTBEN BIT(0) /* Fast back-to-back enabled, 502 * read-only. 503 */ 504 #define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */ 505 #define RTW_CONFIG4_VCOPDN BIT(7) /* VCO Power Down 506 * 0: normal operation 507 * (power-on default) 508 * 1: power-down VCO, RF front-end, 509 * and most RTL8180 components. 510 */ 511 #define RTW_CONFIG4_PWROFF BIT(6) /* Power Off 512 * 0: normal operation 513 * (power-on default) 514 * 1: power-down RF front-end, 515 * and most RTL8180 components, 516 * but leave VCO on. 517 * 518 * XXX RFMD front-end only? 519 */ 520 #define RTW_CONFIG4_PWRMGT BIT(5) /* Power Management 521 * 0: normal operation 522 * (power-on default) 523 * 1: set Tx packet's PWRMGMT bit. 524 */ 525 #define RTW_CONFIG4_LWPME BIT(4) /* LANWAKE vs. PMEB: Cardbus-only 526 * 0: LWAKE & PMEB asserted 527 * simultaneously 528 * 1: LWAKE asserted only if 529 * both PMEB is asserted and 530 * ISOLATEB is low. 531 * XXX RTL8180 only. 532 */ 533 #define RTW_CONFIG4_LWPTN BIT(2) /* see RTW_CONFIG1_LWACT 534 * XXX RTL8180 only. 535 */ 536 /* Radio Front-End Programming Method */ 537 #define RTW_CONFIG4_RFTYPE_MASK BITS(1,0) 538 #define RTW_CONFIG4_RFTYPE_INTERSIL LSHIFT(1, RTW_CONFIG4_RFTYPE_MASK) 539 #define RTW_CONFIG4_RFTYPE_RFMD LSHIFT(2, RTW_CONFIG4_RFTYPE_MASK) 540 #define RTW_CONFIG4_RFTYPE_PHILIPS LSHIFT(3, RTW_CONFIG4_RFTYPE_MASK) 541 542 #define RTW_TESTR 0x5B /* TEST mode register, 8b */ 543 544 #define RTW_PSR 0x5e /* Page Select Register, 8b */ 545 #define RTW_PSR_GPO BIT(7) /* Control/status of pin 52. */ 546 #define RTW_PSR_GPI BIT(6) /* Status of pin 64. */ 547 #define RTW_PSR_LEDGPO1 BIT(5) /* Status/control of LED1 pin if 548 * RTW_CONFIG0_LEDGPOEN is set. 549 */ 550 #define RTW_PSR_LEDGPO0 BIT(4) /* Status/control of LED0 pin if 551 * RTW_CONFIG0_LEDGPOEN is set. 552 */ 553 #define RTW_PSR_UWF BIT(1) /* Enable Unicast Wakeup Frame */ 554 #define RTW_PSR_PSEN BIT(0) /* 1: page 1, 0: page 0 */ 555 556 #define RTW_SCR 0x5f /* Security Configuration Register, 8b */ 557 #define RTW_SCR_KM_MASK BITS(5,4) /* Key Mode */ 558 #define RTW_SCR_KM_WEP104 LSHIFT(1, RTW_SCR_KM_MASK) 559 #define RTW_SCR_KM_WEP40 LSHIFT(0, RTW_SCR_KM_MASK) 560 #define RTW_SCR_TXSECON BIT(1) /* Enable Tx WEP. Invalid if 561 * neither RTW_CONFIG0_WEP40 nor 562 * RTW_CONFIG0_WEP104 is set. 563 */ 564 #define RTW_SCR_RXSECON BIT(0) /* Enable Rx WEP. Invalid if 565 * neither RTW_CONFIG0_WEP40 nor 566 * RTW_CONFIG0_WEP104 is set. 567 */ 568 569 #define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */ 570 #define RTW_BCNITV_BCNITV_MASK BITS(9,0) /* TU between TBTT, written 571 * by host. 572 */ 573 #define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */ 574 #define RTW_ATIMWND_ATIMWND BITS(9,0) /* ATIM Window length in TU, 575 * written by host. 576 */ 577 578 #define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */ 579 #define RTW_BINTRITV_BINTRITV BITS(9,0) /* RTL8180 wakes host with 580 * RTW_INTR_BCNINT at BINTRITV 581 * microseconds before TBTT 582 */ 583 #define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */ 584 #define RTW_ATIMTRITV_ATIMTRITV BITS(9,0) /* RTL8180 wakes host with 585 * RTW_INTR_ATIMINT at ATIMTRITV 586 * microseconds before end of 587 * ATIM Window 588 */ 589 590 #define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */ 591 #define RTW_PHYDELAY_REVC_MAGIC BIT(3) /* Rev. C magic from reference 592 * driver 593 */ 594 #define RTW_PHYDELAY_PHYDELAY BITS(2,0) /* microsecond Tx delay between 595 * MAC and RF front-end 596 */ 597 #define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */ 598 #define RTW_CRCOUNT_MAGIC 0x4c 599 600 #define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */ 601 602 #define RTW_BB 0x7c /* Baseband interface, 32b */ 603 /* used for writing RTL8180's integrated baseband processor */ 604 #define RTW_BB_RD_MASK BITS(23,16) /* data to read */ 605 #define RTW_BB_WR_MASK BITS(15,8) /* data to write */ 606 #define RTW_BB_WREN BIT(7) /* write enable */ 607 #define RTW_BB_ADDR_MASK BITS(6,0) /* address */ 608 609 #define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */ 610 #define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */ 611 #define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */ 612 613 #define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */ 614 #define RTW_PHYCFG_MAC_POLL BIT(31) /* if !RTW_PHYCFG_HST, 615 * host sets. MAC clears 616 * after banging bits. 617 */ 618 #define RTW_PHYCFG_HST BIT(30) /* 1: host bangs bits 619 * 0: MAC bangs bits 620 */ 621 #define RTW_PHYCFG_MAC_RFTYPE_MASK BITS(29,28) 622 #define RTW_PHYCFG_MAC_RFTYPE_INTERSIL LSHIFT(0, RTW_PHYCFG_MAC_RFTYPE_MASK) 623 #define RTW_PHYCFG_MAC_RFTYPE_RFMD LSHIFT(1, RTW_PHYCFG_MAC_RFTYPE_MASK) 624 #define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD 625 #define RTW_PHYCFG_MAC_RFTYPE_PHILIPS LSHIFT(3, RTW_PHYCFG_MAC_RFTYPE_MASK) 626 #define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK BITS(27,24) 627 #define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK BITS(23,0) 628 #define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK BITS(27,24) 629 #define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK BITS(11,8) 630 #define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK BITS(7,0) 631 #define RTW_PHYCFG_HST_EN BIT(2) 632 #define RTW_PHYCFG_HST_CLK BIT(1) 633 #define RTW_PHYCFG_HST_DATA BIT(0) 634 635 #define RTW_MAXIM_HIDATA_MASK BITS(11,4) 636 #define RTW_MAXIM_LODATA_MASK BITS(3,0) 637 638 /** 639 ** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1. 640 **/ 641 642 #define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */ 643 #define RTW_WAKEUP0H 0x88 /* 32b */ 644 645 #define RTW_WAKEUP1L 0x8c 646 #define RTW_WAKEUP1H 0x90 647 648 #define RTW_WAKEUP2LL 0x94 649 #define RTW_WAKEUP2LH 0x98 650 651 #define RTW_WAKEUP2HL 0x9c 652 #define RTW_WAKEUP2HH 0xa0 653 654 #define RTW_WAKEUP3LL 0xa4 655 #define RTW_WAKEUP3LH 0xa8 656 657 #define RTW_WAKEUP3HL 0xac 658 #define RTW_WAKEUP3HH 0xb0 659 660 #define RTW_WAKEUP4LL 0xb4 661 #define RTW_WAKEUP4LH 0xb8 662 663 #define RTW_WAKEUP4HL 0xbc 664 #define RTW_WAKEUP4HH 0xc0 665 666 #define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */ 667 #define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */ 668 #define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */ 669 #define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */ 670 #define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */ 671 672 /** 673 ** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0. 674 **/ 675 676 /* Default Key Registers, each 128b 677 * 678 * If RTW_SCR_KM_WEP104, 104 lsb are the key. 679 * If RTW_SCR_KM_WEP40, 40 lsb are the key. 680 */ 681 #define RTW_DK0 0x90 /* Default Key 0 Register, 128b */ 682 #define RTW_DK1 0xa0 /* Default Key 1 Register, 128b */ 683 #define RTW_DK2 0xb0 /* Default Key 2 Register, 128b */ 684 #define RTW_DK3 0xc0 /* Default Key 3 Register, 128b */ 685 686 #define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */ 687 #define RTW_CONFIG5_TXFIFOOK BIT(7) /* Tx FIFO self-test pass, read-only */ 688 #define RTW_CONFIG5_RXFIFOOK BIT(6) /* Rx FIFO self-test pass, read-only */ 689 #define RTW_CONFIG5_CALON BIT(5) /* 1: start calibration cycle 690 * and raise AGCRESET pin. 691 * 0: lower AGCRESET pin 692 */ 693 #define RTW_CONFIG5_EACPI BIT(2) /* Enable ACPI Wake up, default 0 */ 694 #define RTW_CONFIG5_LANWAKE BIT(1) /* Enable LAN Wake signal, 695 * from EEPROM 696 */ 697 #define RTW_CONFIG5_PMESTS BIT(0) /* 1: both software & PCI Reset 698 * reset PME_Status 699 * 0: only software resets PME_Status 700 * 701 * From EEPROM. 702 */ 703 704 #define RTW_TPPOLL 0xd9 /* Transmit Priority Polling Register, 8b, 705 * write-only. 706 */ 707 #define RTW_TPPOLL_BQ BIT(7) /* RTL8180 clears to notify host of a beacon 708 * Tx. Host writes have no effect. 709 */ 710 #define RTW_TPPOLL_HPQ BIT(6) /* Host writes 1 to notify RTL8180 of 711 * high-priority Tx packets, RTL8180 clears 712 * to after high-priority Tx is complete. 713 */ 714 #define RTW_TPPOLL_NPQ BIT(5) /* If RTW_CONFIG2_DPS is set, 715 * host writes 1 to notify RTL8180 of 716 * normal-priority Tx packets, RTL8180 clears 717 * after normal-priority Tx is complete. 718 * 719 * If RTW_CONFIG2_DPS is clear, host writes 720 * have no effect. RTL8180 clears after 721 * normal-priority Tx is complete. 722 */ 723 #define RTW_TPPOLL_LPQ BIT(4) /* Host writes 1 to notify RTL8180 of 724 * low-priority Tx packets, RTL8180 clears 725 * after low-priority Tx is complete. 726 */ 727 #define RTW_TPPOLL_SBQ BIT(3) /* Host writes 1 to tell RTL8180 to 728 * stop beacon DMA. This bit is invalid 729 * when RTW_CONFIG2_DPS is set. 730 */ 731 #define RTW_TPPOLL_SHPQ BIT(2) /* Host writes 1 to tell RTL8180 to 732 * stop high-priority DMA. 733 */ 734 #define RTW_TPPOLL_SNPQ BIT(2) /* Host writes 1 to tell RTL8180 to 735 * stop normal-priority DMA. This bit is invalid 736 * when RTW_CONFIG2_DPS is set. 737 */ 738 #define RTW_TPPOLL_SLPQ BIT(2) /* Host writes 1 to tell RTL8180 to 739 * stop low-priority DMA. 740 */ 741 #define RTW_TPPOLL_FSWINT BIT(0) /* Force software interrupt. From 742 * reference driver. 743 */ 744 745 746 #define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */ 747 /* Contention Window: indicates number of contention windows before Tx 748 */ 749 #define RTW_CWR_CW BITS(9,0) 750 751 /* Retry Count Register, 16b, read-only */ 752 #define RTW_RETRYCTR 0xde 753 /* Retry Count: indicates number of retries after Tx */ 754 #define RTW_RETRYCTR_RETRYCT BITS(7,0) 755 756 #define RTW_RDSAR 0xe4 /* Receive descriptor Start Address Register, 757 * 32b, 256-byte alignment. 758 */ 759 /* Function Event Register, 32b, Cardbus only. Only valid when 760 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 761 */ 762 #define RTW_FER 0xf0 763 #define RTW_FER_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 764 #define RTW_FER_GWAKE BIT(4) /* General Wakeup */ 765 /* Function Event Mask Register, 32b, Cardbus only. Only valid when 766 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 767 */ 768 #define RTW_FEMR 0xf4 769 #define RTW_FEMR_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 770 #define RTW_FEMR_WKUP BIT(14) /* Wakeup Mask */ 771 #define RTW_FEMR_GWAKE BIT(4) /* General Wakeup */ 772 /* Function Present State Register, 32b, read-only, Cardbus only. 773 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 774 * are set. 775 */ 776 #define RTW_FPSR 0xf8 777 #define RTW_FPSR_INTR BIT(15) /* TBD */ 778 #define RTW_FPSR_GWAKE BIT(4) /* General Wakeup: TBD */ 779 /* Function Force Event Register, 32b, write-only, Cardbus only. 780 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 781 * are set. 782 */ 783 #define RTW_FFER 0xfc 784 #define RTW_FFER_INTR BIT(15) /* TBD */ 785 #define RTW_FFER_GWAKE BIT(4) /* General Wakeup: TBD */ 786 787 /* Serial EEPROM offsets */ 788 #define RTW_SR_ID 0x00 /* 16b */ 789 #define RTW_SR_VID 0x02 /* 16b */ 790 #define RTW_SR_DID 0x04 /* 16b */ 791 #define RTW_SR_SVID 0x06 /* 16b */ 792 #define RTW_SR_SMID 0x08 /* 16b */ 793 #define RTW_SR_MNGNT 0x0a 794 #define RTW_SR_MXLAT 0x0b 795 #define RTW_SR_RFCHIPID 0x0c 796 #define RTW_SR_CONFIG3 0x0d 797 #define RTW_SR_MAC 0x0e /* 6 bytes */ 798 #define RTW_SR_CONFIG0 0x14 799 #define RTW_SR_CONFIG1 0x15 800 #define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */ 801 #define RTW_SR_CONFIG2 0x18 802 #define RTW_SR_CONFIG4 0x19 803 #define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */ 804 #define RTW_SR_TESTR 0x1e 805 #define RTW_SR_CONFIG5 0x1f 806 #define RTW_SR_TXPOWER1 0x20 807 #define RTW_SR_TXPOWER2 0x21 808 #define RTW_SR_TXPOWER3 0x22 809 #define RTW_SR_TXPOWER4 0x23 810 #define RTW_SR_TXPOWER5 0x24 811 #define RTW_SR_TXPOWER6 0x25 812 #define RTW_SR_TXPOWER7 0x26 813 #define RTW_SR_TXPOWER8 0x27 814 #define RTW_SR_TXPOWER9 0x28 815 #define RTW_SR_TXPOWER10 0x29 816 #define RTW_SR_TXPOWER11 0x2a 817 #define RTW_SR_TXPOWER12 0x2b 818 #define RTW_SR_TXPOWER13 0x2c 819 #define RTW_SR_TXPOWER14 0x2d 820 #define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */ 821 #define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */ 822 #define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */ 823 #define RTW_SR_CISPOINTER 0x30 /* 16b */ 824 #define RTW_SR_RFPARM 0x32 /* RF-specific parameter */ 825 #define RTW_SR_RFPARM_DIGPHY BIT(0) /* 1: digital PHY */ 826 #define RTW_SR_RFPARM_DFLANTB BIT(1) /* 1: antenna B is default */ 827 #define RTW_SR_RFPARM_CS_MASK BITS(2,3) /* carrier-sense type */ 828 #define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */ 829 #define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */ 830 #define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */ 831 #define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes*/ 832 833 /* 834 * RTL8180 Transmit/Receive Descriptors 835 */ 836 837 /* the first descriptor in each ring must be on a 256-byte boundary */ 838 #define RTW_DESC_ALIGNMENT 256 839 840 /* Tx descriptor */ 841 struct rtw_txdesc { 842 u_int32_t htx_ctl0; 843 u_int32_t htx_ctl1; 844 u_int32_t htx_buf; 845 u_int32_t htx_len; 846 u_int32_t htx_next; 847 u_int32_t htx_rsvd[3]; 848 }; 849 850 #define htx_stat htx_ctl0 851 852 #define RTW_TXCTL0_OWN BIT(31) /* 1: ready to Tx */ 853 #define RTW_TXCTL0_RSVD0 BIT(30) /* reserved */ 854 #define RTW_TXCTL0_FS BIT(29) /* first segment */ 855 #define RTW_TXCTL0_LS BIT(28) /* last segment */ 856 857 #define RTW_TXCTL0_RATE_MASK BITS(27,24) /* Tx rate */ 858 #define RTW_TXCTL0_RATE_1MBPS LSHIFT(0, RTW_TXCTL0_RATE_MASK) 859 #define RTW_TXCTL0_RATE_2MBPS LSHIFT(1, RTW_TXCTL0_RATE_MASK) 860 #define RTW_TXCTL0_RATE_5MBPS LSHIFT(2, RTW_TXCTL0_RATE_MASK) 861 #define RTW_TXCTL0_RATE_11MBPS LSHIFT(3, RTW_TXCTL0_RATE_MASK) 862 863 #define RTW_TXCTL0_RTSEN BIT(23) /* RTS Enable */ 864 865 #define RTW_TXCTL0_RTSRATE_MASK BITS(22,19) /* Tx rate */ 866 #define RTW_TXCTL0_RTSRATE_1MBPS LSHIFT(0, RTW_TXCTL0_RTSRATE_MASK) 867 #define RTW_TXCTL0_RTSRATE_2MBPS LSHIFT(1, RTW_TXCTL0_RTSRATE_MASK) 868 #define RTW_TXCTL0_RTSRATE_5MBPS LSHIFT(2, RTW_TXCTL0_RTSRATE_MASK) 869 #define RTW_TXCTL0_RTSRATE_11MBPS LSHIFT(3, RTW_TXCTL0_RTSRATE_MASK) 870 871 #define RTW_TXCTL0_BEACON BIT(18) /* packet is a beacon */ 872 #define RTW_TXCTL0_MOREFRAG BIT(17) /* another fragment follows */ 873 #define RTW_TXCTL0_SPLCP BIT(16) /* add short PLCP preamble 874 * and header 875 */ 876 #define RTW_TXCTL0_KEYID_MASK BITS(15,14) /* default key id */ 877 #define RTW_TXCTL0_RSVD1_MASK BITS(13,12) /* reserved */ 878 #define RTW_TXCTL0_TPKTSIZE_MASK BITS(11,0) /* Tx packet size 879 * in bytes 880 */ 881 882 #define RTW_TXSTAT_OWN RTW_TXCTL0_OWN 883 #define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0 884 #define RTW_TXSTAT_FS RTW_TXCTL0_FS 885 #define RTW_TXSTAT_LS RTW_TXCTL0_LS 886 #define RTW_TXSTAT_RSVD1_MASK BITS(27,16) 887 #define RTW_TXSTAT_TOK BIT(15) 888 #define RTW_TXSTAT_RTSRETRY_MASK BITS(14,8) /* RTS retry count */ 889 #define RTW_TXSTAT_DRC_MASK BITS(7,0) /* Data retry count */ 890 891 #define RTW_TXCTL1_LENGEXT BIT(31) /* supplements _LENGTH 892 * in packets sent 5.5Mb/s or 893 * faster 894 */ 895 #define RTW_TXCTL1_LENGTH_MASK BITS(30,16) /* PLCP length (microseconds) */ 896 #define RTW_TXCTL1_RTSDUR_MASK BITS(15,0) /* RTS Duration 897 * (microseconds) 898 */ 899 900 #define RTW_TXLEN_LENGTH_MASK BITS(11,0) /* Tx buffer length in bytes */ 901 902 /* Rx descriptor */ 903 struct rtw_rxdesc { 904 u_int32_t hrx_ctl; 905 u_int32_t hrx_rsvd0; 906 u_int32_t hrx_buf; 907 u_int32_t hrx_rsvd1; 908 }; 909 910 #define hrx_stat hrx_ctl 911 #define hrx_rssi hrx_rsvd0 912 #define hrx_tsftl hrx_buf /* valid only when RTW_RXSTAT_LS is set */ 913 #define hrx_tsfth hrx_rsvd1 /* valid only when RTW_RXSTAT_LS is set */ 914 915 #define RTW_RXCTL_OWN BIT(31) /* 1: owned by NIC */ 916 #define RTW_RXCTL_EOR BIT(30) /* end of ring */ 917 #define RTW_RXCTL_FS BIT(29) /* first segment */ 918 #define RTW_RXCTL_LS BIT(28) /* last segment */ 919 #define RTW_RXCTL_RSVD0_MASK BITS(29,12) /* reserved */ 920 #define RTW_RXCTL_LENGTH_MASK BITS(11,0) /* Rx buffer length */ 921 922 #define RTW_RXSTAT_OWN RTW_RXCTL_OWN 923 #define RTW_RXSTAT_EOR RTW_RXCTL_EOR 924 #define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */ 925 #define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */ 926 #define RTW_RXSTAT_DMAFAIL BIT(27) /* DMA failure on this pkt */ 927 #define RTW_RXSTAT_BOVF BIT(26) /* buffer overflow XXX means 928 * FIFO exhausted? 929 */ 930 #define RTW_RXSTAT_SPLCP BIT(25) /* Rx'd with short preamble 931 * and PLCP header 932 */ 933 #define RTW_RXSTAT_RSVD1 BIT(24) /* reserved */ 934 #define RTW_RXSTAT_RATE_MASK BITS(23,20) /* Rx rate */ 935 #define RTW_RXSTAT_RATE_1MBPS LSHIFT(0, RTW_RXSTAT_RATE_MASK) 936 #define RTW_RXSTAT_RATE_2MBPS LSHIFT(1, RTW_RXSTAT_RATE_MASK) 937 #define RTW_RXSTAT_RATE_5MBPS LSHIFT(2, RTW_RXSTAT_RATE_MASK) 938 #define RTW_RXSTAT_RATE_11MBPS LSHIFT(3, RTW_RXSTAT_RATE_MASK) 939 #define RTW_RXSTAT_MIC BIT(19) /* XXX from reference driver */ 940 #define RTW_RXSTAT_MAR BIT(18) /* is multicast */ 941 #define RTW_RXSTAT_PAR BIT(17) /* matches RTL8180's MAC */ 942 #define RTW_RXSTAT_BAR BIT(16) /* is broadcast */ 943 #define RTW_RXSTAT_RES BIT(15) /* error summary. valid when 944 * RTW_RXSTAT_LS set. indicates 945 * that either RTW_RXSTAT_CRC32 946 * or RTW_RXSTAT_ICV is set. 947 */ 948 #define RTW_RXSTAT_PWRMGT BIT(14) /* 802.11 PWRMGMT bit is set */ 949 #define RTW_RXSTAT_CRC16 BIT(14) /* XXX CRC16 error, from 950 * reference driver 951 */ 952 #define RTW_RXSTAT_CRC32 BIT(13) /* CRC32 error */ 953 #define RTW_RXSTAT_ICV BIT(12) /* ICV error */ 954 #define RTW_RXSTAT_LENGTH_MASK BITS(11,0) /* frame length, including 955 * CRC32 956 */ 957 958 /* Convenient status conjunction. */ 959 #define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS) 960 /* Convenient status disjunctions. */ 961 #define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF) 962 #define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\ 963 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\ 964 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\ 965 RTW_RXSTAT_ICV) 966 967 968 #define RTW_RXRSSI_VLAN BITS(32,16) /* XXX from reference driver */ 969 /* for Philips RF front-ends */ 970 #define RTW_RXRSSI_RSSI BITS(15,8) /* RF energy at the PHY */ 971 /* for RF front-ends by Intersil, Maxim, RFMD */ 972 #define RTW_RXRSSI_IMR_RSSI BITS(15,9) /* RF energy at the PHY */ 973 #define RTW_RXRSSI_IMR_LNA BIT(8) /* 1: LNA activated */ 974 #define RTW_RXRSSI_SQ BITS(7,0) /* Barker code-lock quality */ 975 976 #define RTW_READ8(regs, ofs) \ 977 bus_space_read_1((regs)->r_bt, (regs)->r_bh, (ofs)) 978 979 #define RTW_READ16(regs, ofs) \ 980 bus_space_read_2((regs)->r_bt, (regs)->r_bh, (ofs)) 981 982 #define RTW_READ(regs, ofs) \ 983 bus_space_read_4((regs)->r_bt, (regs)->r_bh, (ofs)) 984 985 #define RTW_WRITE8(regs, ofs, val) \ 986 bus_space_write_1((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 987 988 #define RTW_WRITE16(regs, ofs, val) \ 989 bus_space_write_2((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 990 991 #define RTW_WRITE(regs, ofs, val) \ 992 bus_space_write_4((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 993 994 #define RTW_ISSET(regs, reg, mask) \ 995 (RTW_READ((regs), (reg)) & (mask)) 996 997 #define RTW_CLR(regs, reg, mask) \ 998 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask)) 999 1000 /* bus_space(9) lied? */ 1001 #ifndef BUS_SPACE_BARRIER_SYNC 1002 #define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 1003 #endif 1004 1005 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ 1006 #define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ 1007 #endif 1008 1009 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE 1010 #define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ 1011 #endif 1012 1013 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ 1014 #define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE 1015 #endif 1016 1017 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE 1018 #define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE 1019 #endif 1020 1021 /* 1022 * Bus barrier 1023 * 1024 * Complete outstanding read and/or write ops on [reg0, reg1] 1025 * ([reg1, reg0]) before starting new ops on the same region. See 1026 * acceptable bus_space_barrier(9) for the flag definitions. 1027 */ 1028 #define RTW_BARRIER(regs, reg0, reg1, flags) \ 1029 bus_space_barrier((regs)->r_bh, (regs)->r_bt, \ 1030 MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags) 1031 1032 /* 1033 * Barrier convenience macros. 1034 */ 1035 /* sync */ 1036 #define RTW_SYNC(regs, reg0, reg1) \ 1037 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC) 1038 1039 /* write-before-write */ 1040 #define RTW_WBW(regs, reg0, reg1) \ 1041 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1042 1043 /* write-before-read */ 1044 #define RTW_WBR(regs, reg0, reg1) \ 1045 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 1046 1047 /* read-before-read */ 1048 #define RTW_RBR(regs, reg0, reg1) \ 1049 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ) 1050 1051 /* read-before-read */ 1052 #define RTW_RBW(regs, reg0, reg1) \ 1053 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 1054 1055 #define RTW_WBRW(regs, reg0, reg1) \ 1056 RTW_BARRIER(regs, reg0, reg1, \ 1057 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 1058 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1059 1060 /* 1061 * Registers for RTL8180L's built-in baseband modem. 1062 */ 1063 #define RTW_BBP_SYS1 0x00 1064 #define RTW_BBP_TXAGC 0x03 1065 #define RTW_BBP_LNADET 0x04 1066 #define RTW_BBP_IFAGCINI 0x05 1067 #define RTW_BBP_IFAGCLIMIT 0x06 1068 #define RTW_BBP_IFAGCDET 0x07 1069 1070 #define RTW_BBP_ANTATTEN 0x10 1071 #define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91 1072 #define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92 1073 #define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93 1074 #define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3 1075 #define RTW_BBP_ANTATTEN_DFLANTB 0x40 1076 #define RTW_BBP_ANTATTEN_CHAN14 0x0c 1077 1078 #define RTW_BBP_TRL 0x11 1079 #define RTW_BBP_SYS2 0x12 1080 #define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */ 1081 #define RTW_BBP_SYS2_RATE_MASK BITS(5,4) /* loopback rate? 1082 * 0: 1Mbps 1083 * 1: 2Mbps 1084 * 2: 5.5Mbps 1085 * 3: 11Mbps 1086 */ 1087 #define RTW_BBP_SYS3 0x13 1088 /* carrier-sense threshold */ 1089 #define RTW_BBP_SYS3_CSTHRESH_MASK BITS(0,3) 1090 #define RTW_BBP_CHESTLIM 0x19 1091 #define RTW_BBP_CHSQLIM 0x1a 1092 1093
Indexes created Mon Sep 29 21:09:56 GMT 2025