rtwvar.h revision 1.13
1 /* $NetBSD: rtwvar.h,v 1.13 2004/12/28 22:30:07 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Driver for the Realtek RTL8180 802.11 MAC/BBP by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_IC_RTWVAR_H_ 34 #define _DEV_IC_RTWVAR_H_ 35 36 #include <sys/queue.h> 37 #include <sys/callout.h> 38 39 #ifdef RTW_DEBUG 40 #define RTW_DEBUG_TUNE 0x000001 41 #define RTW_DEBUG_PKTFILT 0x000002 42 #define RTW_DEBUG_XMIT 0x000004 43 #define RTW_DEBUG_XMIT_DESC 0x000008 44 #define RTW_DEBUG_NODE 0x000010 45 #define RTW_DEBUG_PWR 0x000020 46 #define RTW_DEBUG_ATTACH 0x000040 47 #define RTW_DEBUG_REGDUMP 0x000080 48 #define RTW_DEBUG_ACCESS 0x000100 49 #define RTW_DEBUG_RESET 0x000200 50 #define RTW_DEBUG_INIT 0x000400 51 #define RTW_DEBUG_IOSTATE 0x000800 52 #define RTW_DEBUG_RECV 0x001000 53 #define RTW_DEBUG_RECV_DESC 0x002000 54 #define RTW_DEBUG_IO_KICK 0x004000 55 #define RTW_DEBUG_INTR 0x008000 56 #define RTW_DEBUG_PHY 0x010000 57 #define RTW_DEBUG_PHYIO 0x020000 58 #define RTW_DEBUG_PHYBITIO 0x040000 59 #define RTW_DEBUG_TIMEOUT 0x080000 60 #define RTW_DEBUG_BUGS 0x100000 61 #define RTW_DEBUG_MAX 0x1fffff 62 63 extern int rtw_debug; 64 #define RTW_DPRINTF(__flags, __x) \ 65 if ((rtw_debug & (__flags)) != 0) printf __x 66 #define DPRINTF(__sc, __flags, __x) \ 67 if (((__sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) != 0) \ 68 RTW_DPRINTF(__flags, __x) 69 #else /* RTW_DEBUG */ 70 #define RTW_DPRINTF(__flags, __x) 71 #define DPRINTF(__sc, __flags, __x) 72 #endif /* RTW_DEBUG */ 73 74 #if 0 75 enum rtw_rftype { 76 RTW_RFTYPE_INTERSIL = 0, 77 RTW_RFTYPE_RFMD, 78 RTW_RFTYPE_PHILIPS, 79 RTW_RFTYPE_MAXIM 80 }; 81 #endif 82 83 enum rtw_locale { 84 RTW_LOCALE_USA = 0, 85 RTW_LOCALE_EUROPE, 86 RTW_LOCALE_JAPAN, 87 RTW_LOCALE_UNKNOWN 88 }; 89 90 enum rtw_rfchipid { 91 RTW_RFCHIPID_RESERVED = 0, 92 RTW_RFCHIPID_INTERSIL = 1, 93 RTW_RFCHIPID_RFMD = 2, 94 RTW_RFCHIPID_PHILIPS = 3, 95 RTW_RFCHIPID_MAXIM = 4, 96 RTW_RFCHIPID_GCT = 5 97 }; 98 99 /* sc_flags */ 100 #define RTW_F_ENABLED 0x00000001 /* chip is enabled */ 101 #define RTW_F_DIGPHY 0x00000002 /* digital PHY */ 102 #define RTW_F_DFLANTB 0x00000004 /* B antenna is default */ 103 #define RTW_F_ANTDIV 0x00000010 /* h/w antenna diversity */ 104 #define RTW_F_9356SROM 0x00000020 /* 93c56 SROM */ 105 #define RTW_F_SLEEP 0x00000040 /* chip is asleep */ 106 #define RTW_F_INVALID 0x00000080 /* chip is absent */ 107 /* all PHY flags */ 108 #define RTW_F_ALLPHY (RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV) 109 110 struct rtw_regs { 111 bus_space_tag_t r_bt; 112 bus_space_handle_t r_bh; 113 }; 114 115 #define RTW_SR_GET(sr, ofs) \ 116 (((sr)->sr_content[(ofs)/2] >> (((ofs) % 2 == 0) ? 0 : 8)) & 0xff) 117 118 #define RTW_SR_GET16(sr, ofs) \ 119 (RTW_SR_GET((sr), (ofs)) | (RTW_SR_GET((sr), (ofs) + 1) << 8)) 120 121 struct rtw_srom { 122 u_int16_t *sr_content; 123 u_int16_t sr_size; 124 }; 125 126 struct rtw_rxctl { 127 struct mbuf *srx_mbuf; 128 bus_dmamap_t srx_dmamap; 129 }; 130 131 struct rtw_txctl { 132 SIMPLEQ_ENTRY(rtw_txctl) stx_q; 133 struct mbuf *stx_mbuf; 134 bus_dmamap_t stx_dmamap; 135 struct ieee80211_node *stx_ni; /* destination node */ 136 u_int stx_first; /* 1st hw descriptor */ 137 u_int stx_last; /* last hw descriptor */ 138 struct ieee80211_duration stx_d0; 139 struct ieee80211_duration stx_dn; 140 }; 141 142 #define RTW_NTXPRI 4 /* number of Tx priorities */ 143 #define RTW_TXPRILO 0 144 #define RTW_TXPRIMD 1 145 #define RTW_TXPRIHI 2 146 #define RTW_TXPRIBCN 3 /* beacon priority */ 147 148 #define RTW_MAXPKTSEGS 64 /* Max 64 segments per Tx packet */ 149 150 #define CASSERT(cond, complaint) complaint[(cond) ? 0 : -1] = complaint[(cond) ? 0 : -1] 151 152 /* Note well: the descriptor rings must begin on RTW_DESC_ALIGNMENT 153 * boundaries. I allocate them consecutively from one buffer, so 154 * just round up. 155 */ 156 #define RTW_TXQLENLO 64 /* low-priority queue length */ 157 #define RTW_TXQLENMD 64 /* medium-priority */ 158 #define RTW_TXQLENHI 64 /* high-priority */ 159 #define RTW_TXQLENBCN 1 /* beacon */ 160 161 #define RTW_NTXDESCLO RTW_TXQLENLO 162 #define RTW_NTXDESCMD RTW_TXQLENMD 163 #define RTW_NTXDESCHI RTW_TXQLENHI 164 #define RTW_NTXDESCBCN RTW_TXQLENBCN 165 166 #define RTW_NTXDESCTOTAL (RTW_NTXDESCLO + RTW_NTXDESCMD + \ 167 RTW_NTXDESCHI + RTW_NTXDESCBCN) 168 169 #define RTW_RXQLEN 64 170 171 struct rtw_txdesc_blk { 172 u_int htc_ndesc; 173 u_int htc_next; 174 u_int htc_nfree; 175 bus_addr_t htc_physbase; 176 bus_addr_t htc_ofs; 177 struct rtw_txdesc *htc_desc; 178 }; 179 180 #define RTW_NEXT_IDX(__htc, __idx) (((__idx) + 1) % (__htc)->htc_ndesc) 181 182 #define RTW_NEXT_DESC(__htc, __idx) \ 183 ((__htc)->htc_physbase + \ 184 sizeof(struct rtw_txdesc) * RTW_NEXT_IDX((__htc), (__idx))) 185 186 SIMPLEQ_HEAD(rtw_txq, rtw_txctl); 187 188 struct rtw_txctl_blk { 189 /* dirty/free s/w descriptors */ 190 struct rtw_txq stc_dirtyq; 191 struct rtw_txq stc_freeq; 192 u_int stc_ndesc; 193 int stc_tx_timer; 194 struct rtw_txctl *stc_desc; 195 }; 196 197 struct rtw_descs { 198 struct rtw_txdesc hd_txlo[RTW_NTXDESCLO]; 199 struct rtw_txdesc hd_txmd[RTW_NTXDESCMD]; 200 struct rtw_txdesc hd_txhi[RTW_NTXDESCMD]; 201 struct rtw_rxdesc hd_rx[RTW_RXQLEN]; 202 struct rtw_txdesc hd_bcn[RTW_NTXDESCBCN]; 203 }; 204 #define RTW_DESC_OFFSET(ring, i) offsetof(struct rtw_descs, ring[i]) 205 #define RTW_RING_OFFSET(ring) RTW_DESC_OFFSET(ring, 0) 206 #define RTW_RING_BASE(sc, ring) ((sc)->sc_desc_physaddr + \ 207 RTW_RING_OFFSET(ring)) 208 209 /* Radio capture format for RTL8180. */ 210 211 #define RTW_RX_RADIOTAP_PRESENT \ 212 ((1 << IEEE80211_RADIOTAP_TSFT) | \ 213 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 214 (1 << IEEE80211_RADIOTAP_RATE) | \ 215 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 216 (1 << IEEE80211_RADIOTAP_LOCK_QUALITY) | \ 217 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ 218 0) 219 220 struct rtw_rx_radiotap_header { 221 struct ieee80211_radiotap_header rr_ihdr; 222 uint64_t rr_tsft; 223 u_int8_t rr_flags; 224 u_int8_t rr_rate; 225 u_int16_t rr_chan_freq; 226 u_int16_t rr_chan_flags; 227 uint16_t rr_barker_lock; 228 u_int8_t rr_antsignal; 229 } __attribute__((__packed__)); 230 231 #define RTW_TX_RADIOTAP_PRESENT \ 232 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 233 (1 << IEEE80211_RADIOTAP_RATE) | \ 234 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 235 0) 236 237 struct rtw_tx_radiotap_header { 238 struct ieee80211_radiotap_header rt_ihdr; 239 u_int8_t rt_flags; 240 u_int8_t rt_rate; 241 u_int16_t rt_chan_freq; 242 u_int16_t rt_chan_flags; 243 } __attribute__((__packed__)); 244 245 enum rtw_attach_state {FINISHED, FINISH_DESCMAP_LOAD, FINISH_DESCMAP_CREATE, 246 FINISH_DESC_MAP, FINISH_DESC_ALLOC, FINISH_RXMAPS_CREATE, 247 FINISH_TXMAPS_CREATE, FINISH_RESET, FINISH_READ_SROM, FINISH_PARSE_SROM, 248 FINISH_RF_ATTACH, FINISH_ID_STA, FINISH_TXDESCBLK_SETUP, 249 FINISH_TXCTLBLK_SETUP, DETACHED}; 250 251 struct rtw_hooks { 252 void *rh_shutdown; /* shutdown hook */ 253 void *rh_power; /* power management hook */ 254 }; 255 256 struct rtw_mtbl { 257 int (*mt_newstate)(struct ieee80211com *, 258 enum ieee80211_state, int); 259 void (*mt_recv_mgmt)(struct ieee80211com *, 260 struct mbuf *, struct ieee80211_node *, 261 int, int, u_int32_t); 262 struct ieee80211_node *(*mt_node_alloc)(struct ieee80211com *); 263 void (*mt_node_free)(struct ieee80211com *, 264 struct ieee80211_node *); 265 }; 266 267 enum rtw_pwrstate { RTW_OFF = 0, RTW_SLEEP, RTW_ON }; 268 269 typedef void (*rtw_continuous_tx_cb_t)(void *arg, int); 270 271 struct rtw_phy { 272 struct rtw_rf *p_rf; 273 struct rtw_regs *p_regs; 274 }; 275 276 struct rtw_bbpset { 277 u_int bb_antatten; 278 u_int bb_chestlim; 279 u_int bb_chsqlim; 280 u_int bb_ifagcdet; 281 u_int bb_ifagcini; 282 u_int bb_ifagclimit; 283 u_int bb_lnadet; 284 u_int bb_sys1; 285 u_int bb_sys2; 286 u_int bb_sys3; 287 u_int bb_trl; 288 u_int bb_txagc; 289 }; 290 291 struct rtw_rf { 292 void (*rf_destroy)(struct rtw_rf *); 293 /* args: frequency, txpower, power state */ 294 int (*rf_init)(struct rtw_rf *, u_int, u_int8_t, 295 enum rtw_pwrstate); 296 /* arg: power state */ 297 int (*rf_pwrstate)(struct rtw_rf *, enum rtw_pwrstate); 298 /* arg: frequency */ 299 int (*rf_tune)(struct rtw_rf *, u_int); 300 /* arg: txpower */ 301 int (*rf_txpower)(struct rtw_rf *, u_int8_t); 302 rtw_continuous_tx_cb_t rf_continuous_tx_cb; 303 void *rf_continuous_tx_arg; 304 struct rtw_bbpset rf_bbpset; 305 }; 306 307 static __inline void 308 rtw_rf_destroy(struct rtw_rf *rf) 309 { 310 (*rf->rf_destroy)(rf); 311 } 312 313 static __inline int 314 rtw_rf_init(struct rtw_rf *rf, u_int freq, u_int8_t opaque_txpower, 315 enum rtw_pwrstate power) 316 { 317 return (*rf->rf_init)(rf, freq, opaque_txpower, power); 318 } 319 320 static __inline int 321 rtw_rf_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 322 { 323 return (*rf->rf_pwrstate)(rf, power); 324 } 325 326 static __inline int 327 rtw_rf_tune(struct rtw_rf *rf, u_int freq) 328 { 329 return (*rf->rf_tune)(rf, freq); 330 } 331 332 static __inline int 333 rtw_rf_txpower(struct rtw_rf *rf, u_int8_t opaque_txpower) 334 { 335 return (*rf->rf_txpower)(rf, opaque_txpower); 336 } 337 338 typedef int (*rtw_rf_write_t)(struct rtw_regs *, enum rtw_rfchipid, u_int, 339 u_int32_t); 340 341 struct rtw_rfbus { 342 struct rtw_regs *b_regs; 343 rtw_rf_write_t b_write; 344 }; 345 346 static __inline int 347 rtw_rfbus_write(struct rtw_rfbus *bus, enum rtw_rfchipid rfchipid, u_int addr, 348 u_int32_t val) 349 { 350 return (*bus->b_write)(bus->b_regs, rfchipid, addr, val); 351 } 352 353 struct rtw_max2820 { 354 struct rtw_rf mx_rf; 355 struct rtw_rfbus mx_bus; 356 int mx_is_a; /* 1: MAX2820A/MAX2821A */ 357 }; 358 359 struct rtw_sa2400 { 360 struct rtw_rf sa_rf; 361 struct rtw_rfbus sa_bus; 362 int sa_digphy; /* 1: digital PHY */ 363 }; 364 365 typedef void (*rtw_pwrstate_t)(struct rtw_regs *, enum rtw_pwrstate, int, int); 366 367 enum rtw_access {RTW_ACCESS_NONE = 0, 368 RTW_ACCESS_CONFIG = 1, 369 RTW_ACCESS_ANAPARM = 2}; 370 371 struct rtw_softc { 372 struct device sc_dev; 373 struct ieee80211com sc_ic; 374 struct rtw_regs sc_regs; 375 bus_dma_tag_t sc_dmat; 376 u_int32_t sc_flags; 377 378 #if 0 379 enum rtw_rftype sc_rftype; 380 #endif 381 enum rtw_attach_state sc_attach_state; 382 enum rtw_rfchipid sc_rfchipid; 383 enum rtw_locale sc_locale; 384 u_int8_t sc_phydelay; 385 386 /* s/w Tx/Rx descriptors */ 387 struct rtw_txctl_blk sc_txctl_blk[RTW_NTXPRI]; 388 u_int sc_txq; 389 u_int sc_txnext; 390 391 struct rtw_txdesc_blk sc_txdesc_blk[RTW_NTXPRI]; 392 struct rtw_rxdesc *sc_rxdesc; 393 struct rtw_rxctl sc_rxctl[RTW_RXQLEN]; 394 u_int sc_rxnext; 395 u_int sc_nrxdesc; 396 397 struct rtw_descs *sc_descs; 398 399 bus_dma_segment_t sc_desc_segs; 400 int sc_desc_nsegs; 401 bus_dmamap_t sc_desc_dmamap; 402 #define sc_desc_physaddr sc_desc_dmamap->dm_segs[0].ds_addr 403 404 struct rtw_srom sc_srom; 405 406 enum rtw_pwrstate sc_pwrstate; 407 408 rtw_pwrstate_t sc_pwrstate_cb; 409 410 struct rtw_rf *sc_rf; 411 412 u_int16_t sc_inten; 413 414 /* interrupt acknowledge hook */ 415 void (*sc_intr_ack) __P((struct rtw_regs *)); 416 417 int (*sc_enable)(struct rtw_softc *); 418 void (*sc_disable)(struct rtw_softc *); 419 void (*sc_power)(struct rtw_softc *, int); 420 struct rtw_mtbl sc_mtbl; 421 struct rtw_hooks sc_hooks; 422 423 caddr_t sc_radiobpf; 424 425 struct callout sc_scan_ch; 426 u_int sc_cur_chan; 427 428 u_int32_t sc_tsfth; /* most significant TSFT bits */ 429 u_int32_t sc_rcr; /* RTW_RCR */ 430 u_int8_t sc_csthr; /* carrier-sense threshold */ 431 432 int sc_do_tick; /* indicate 1s ticks */ 433 struct timeval sc_tick0; /* first tick */ 434 435 uint8_t sc_rev; /* PCI/Cardbus revision */ 436 437 uint32_t sc_anaparm; /* register RTW_ANAPARM */ 438 439 union { 440 struct rtw_rx_radiotap_header tap; 441 u_int8_t pad[64]; 442 } sc_rxtapu; 443 union { 444 struct rtw_tx_radiotap_header tap; 445 u_int8_t pad[64]; 446 } sc_txtapu; 447 enum rtw_access sc_access; 448 }; 449 450 #define sc_if sc_ic.ic_if 451 #define sc_rxtap sc_rxtapu.tap 452 #define sc_txtap sc_txtapu.tap 453 454 extern int rtw_host_rfio; 455 456 void rtw_txdac_enable(struct rtw_softc *, int); 457 void rtw_anaparm_enable(struct rtw_regs *, int); 458 void rtw_config0123_enable(struct rtw_regs *, int); 459 void rtw_continuous_tx_enable(struct rtw_softc *, int); 460 void rtw_set_access(struct rtw_softc *, enum rtw_access); 461 462 void rtw_attach(struct rtw_softc *); 463 int rtw_detach(struct rtw_softc *); 464 int rtw_intr(void *); 465 466 void rtw_disable(struct rtw_softc *); 467 int rtw_enable(struct rtw_softc *); 468 469 int rtw_activate(struct device *, enum devact); 470 void rtw_power(int, void *); 471 void rtw_shutdown(void *); 472 473 const char *rtw_pwrstate_string(enum rtw_pwrstate); 474 475 #endif /* _DEV_IC_RTWVAR_H_ */ 476
Indexes created Thu Sep 25 14:09:45 GMT 2025