seeq8005.c revision 1.11
1 /* $NetBSD: seeq8005.c,v 1.11 2001/03/24 20:38:41 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chip: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 */ 43 /* 44 * More information on the 8004 and 8005 AEDLC controllers can be found in 45 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 46 * 47 * This data book may no longer be available as these are rather old chips 48 * (1991 - 1993) 49 */ 50 /* 51 * This driver is based on the arm32 ea(4) driver, hence the names of many 52 * of the functions. 53 */ 54 /* 55 * Bugs/possible improvements: 56 * - Does not currently support DMA 57 * - Does not transmit multiple packets in one go 58 * - Does not support 8-bit busses 59 */ 60 61 #include "opt_inet.h" 62 #include "opt_ns.h" 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 67 __RCSID("$NetBSD: seeq8005.c,v 1.11 2001/03/24 20:38:41 bjh21 Exp $"); 68 69 #include <sys/systm.h> 70 #include <sys/endian.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_types.h> 81 #include <net/if_ether.h> 82 #include <net/if_media.h> 83 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/in_systm.h> 87 #include <netinet/in_var.h> 88 #include <netinet/ip.h> 89 #include <netinet/if_inarp.h> 90 #endif 91 92 #ifdef NS 93 #include <netns/ns.h> 94 #include <netns/ns_if.h> 95 #endif 96 97 #include "bpfilter.h" 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <machine/bus.h> 104 #include <machine/intr.h> 105 106 #include <dev/ic/seeq8005reg.h> 107 #include <dev/ic/seeq8005var.h> 108 109 /*#define SEEQ_DEBUG*/ 110 111 /* for debugging convenience */ 112 #ifdef SEEQ_DEBUG 113 #define SEEQ_DEBUG_MISC 1 114 #define SEEQ_DEBUG_TX 2 115 #define SEEQ_DEBUG_RX 4 116 #define SEEQ_DEBUG_PKT 8 117 #define SEEQ_DEBUG_TXINT 16 118 #define SEEQ_DEBUG_RXINT 32 119 int seeq_debug = 0; 120 #define DPRINTF(f, x) { if (seeq_debug & (f)) printf x; } 121 #else 122 #define DPRINTF(f, x) 123 #endif 124 #define dprintf(x) DPRINTF(SEEQ_DEBUG_MISC, x) 125 126 #define SEEQ_TX_BUFFER_SIZE 0x600 /* (> MAX_ETHER_LEN) */ 127 128 /* 129 * prototypes 130 */ 131 132 static int ea_init(struct ifnet *); 133 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 134 static void ea_start(struct ifnet *); 135 static void ea_watchdog(struct ifnet *); 136 static void ea_chipreset(struct seeq8005_softc *); 137 static void ea_ramtest(struct seeq8005_softc *); 138 static int ea_stoptx(struct seeq8005_softc *); 139 static int ea_stoprx(struct seeq8005_softc *); 140 static void ea_stop(struct ifnet *, int); 141 static void ea_await_fifo_empty(struct seeq8005_softc *); 142 static void ea_await_fifo_full(struct seeq8005_softc *); 143 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 145 static void ea_select_buffer(struct seeq8005_softc *, int); 146 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 147 static void ea_read(struct seeq8005_softc *, int, int); 148 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 149 static void ea_getpackets(struct seeq8005_softc *); 150 static void eatxpacket(struct seeq8005_softc *); 151 static void ea_mc_reset(struct seeq8005_softc *); 152 static void ea_mc_reset_8004(struct seeq8005_softc *); 153 static void ea_mc_reset_8005(struct seeq8005_softc *); 154 static int ea_mediachange(struct ifnet *); 155 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 156 157 158 /* 159 * Attach chip. 160 */ 161 162 void 163 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 164 int nmedia, int defmedia) 165 { 166 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 167 u_int id; 168 169 KASSERT(myaddr != NULL); 170 printf(" address %s", ether_sprintf(myaddr)); 171 172 /* Stop the board. */ 173 174 ea_chipreset(sc); 175 176 /* Get the product ID */ 177 178 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 179 id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 180 181 switch (id & SEEQ_PRODUCTID_MASK) { 182 case SEEQ_PRODUCTID_8004: 183 sc->sc_variant = SEEQ_8004; 184 break; 185 default: /* XXX */ 186 sc->sc_variant = SEEQ_8005; 187 break; 188 } 189 190 switch (sc->sc_variant) { 191 case SEEQ_8004: 192 printf(", SEEQ80C04 rev %x\n", 193 id & SEEQ_PRODUCTID_REV_MASK); 194 break; 195 case SEEQ_8005: 196 if (id != 0xff) 197 printf(", SEEQ8005 rev %x\n", id); 198 else 199 printf(", SEEQ8005\n"); 200 break; 201 default: 202 printf(", Unknown ethernet controller\n"); 203 return; 204 } 205 206 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 207 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 208 209 /* 210 * Set up tx and rx buffers. 211 * 212 * We use approximately a third of the packet memory for TX 213 * buffers and the rest for RX buffers 214 */ 215 sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 3; 216 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 217 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 218 sc->sc_enabled = 0; 219 220 /* Test the RAM */ 221 ea_ramtest(sc); 222 223 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 224 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 225 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 226 227 /* Initialise ifnet structure. */ 228 229 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 230 ifp->if_softc = sc; 231 ifp->if_start = ea_start; 232 ifp->if_ioctl = ea_ioctl; 233 ifp->if_init = ea_init; 234 ifp->if_stop = ea_stop; 235 ifp->if_watchdog = ea_watchdog; 236 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 237 if (sc->sc_variant == SEEQ_8004) 238 ifp->if_flags |= IFF_SIMPLEX; 239 IFQ_SET_READY(&ifp->if_snd); 240 241 /* Initialize media goo. */ 242 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 243 if (media != NULL) { 244 int i; 245 246 for (i = 0; i < nmedia; i++) 247 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 248 ifmedia_set(&sc->sc_media, defmedia); 249 } else { 250 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 251 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 252 } 253 254 /* Now we can attach the interface. */ 255 256 if_attach(ifp); 257 ether_ifattach(ifp, myaddr); 258 259 printf("\n"); 260 } 261 262 /* 263 * Media change callback. 264 */ 265 static int 266 ea_mediachange(struct ifnet *ifp) 267 { 268 struct seeq8005_softc *sc = ifp->if_softc; 269 270 if (sc->sc_mediachange) 271 return ((*sc->sc_mediachange)(sc)); 272 return (EINVAL); 273 } 274 275 /* 276 * Media status callback. 277 */ 278 static void 279 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 280 { 281 struct seeq8005_softc *sc = ifp->if_softc; 282 283 if (sc->sc_enabled == 0) { 284 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 285 ifmr->ifm_status = 0; 286 return; 287 } 288 289 if (sc->sc_mediastatus) 290 (*sc->sc_mediastatus)(sc, ifmr); 291 } 292 293 /* 294 * Test the RAM on the ethernet card. 295 */ 296 297 void 298 ea_ramtest(struct seeq8005_softc *sc) 299 { 300 bus_space_tag_t iot = sc->sc_iot; 301 bus_space_handle_t ioh = sc->sc_ioh; 302 int loop; 303 u_int sum = 0; 304 305 /* dprintf(("ea_ramtest()\n"));*/ 306 307 /* 308 * Test the buffer memory on the board. 309 * Write simple pattens to it and read them back. 310 */ 311 312 /* Set up the whole buffer RAM for writing */ 313 314 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 315 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 316 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 317 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 318 319 #define SEEQ_RAMTEST_LOOP(value) \ 320 do { \ 321 /* Set the write start address and write a pattern */ \ 322 ea_writebuf(sc, NULL, 0x0000, 0); \ 323 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 324 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (value)); \ 325 \ 326 /* Set the read start address and verify the pattern */ \ 327 ea_readbuf(sc, NULL, 0x0000, 0); \ 328 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 329 if (bus_space_read_2(iot, ioh, SEEQ_BUFWIN) != (value)) \ 330 ++sum; \ 331 if (sum != 0) \ 332 dprintf(("sum=%d\n", sum)); \ 333 } while (/*CONSTCOND*/0) 334 335 SEEQ_RAMTEST_LOOP(loop); 336 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 337 SEEQ_RAMTEST_LOOP(0xaa55); 338 SEEQ_RAMTEST_LOOP(0x55aa); 339 340 /* Report */ 341 342 if (sum > 0) 343 printf("%s: buffer RAM failed self test, %d faults\n", 344 sc->sc_dev.dv_xname, sum); 345 } 346 347 348 /* 349 * Stop the tx interface. 350 * 351 * Returns 0 if the tx was already stopped or 1 if it was active 352 */ 353 354 static int 355 ea_stoptx(struct seeq8005_softc *sc) 356 { 357 bus_space_tag_t iot = sc->sc_iot; 358 bus_space_handle_t ioh = sc->sc_ioh; 359 int timeout; 360 int status; 361 362 DPRINTF(SEEQ_DEBUG_TX, ("seeq_stoptx()\n")); 363 364 sc->sc_enabled = 0; 365 366 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 367 if (!(status & SEEQ_STATUS_TX_ON)) 368 return 0; 369 370 /* Stop any tx and wait for confirmation */ 371 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 372 sc->sc_command | SEEQ_CMD_TX_OFF); 373 374 timeout = 20000; 375 do { 376 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 377 delay(1); 378 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 379 if (timeout == 0) 380 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 381 sc->sc_dev.dv_xname); 382 383 /* Clear any pending tx interrupt */ 384 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 385 sc->sc_command | SEEQ_CMD_TX_INTACK); 386 return 1; 387 } 388 389 390 /* 391 * Stop the rx interface. 392 * 393 * Returns 0 if the tx was already stopped or 1 if it was active 394 */ 395 396 static int 397 ea_stoprx(struct seeq8005_softc *sc) 398 { 399 bus_space_tag_t iot = sc->sc_iot; 400 bus_space_handle_t ioh = sc->sc_ioh; 401 int timeout; 402 int status; 403 404 DPRINTF(SEEQ_DEBUG_RX, ("seeq_stoprx()\n")); 405 406 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 407 if (!(status & SEEQ_STATUS_RX_ON)) 408 return 0; 409 410 /* Stop any rx and wait for confirmation */ 411 412 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 413 sc->sc_command | SEEQ_CMD_RX_OFF); 414 415 timeout = 20000; 416 do { 417 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 418 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 419 if (timeout == 0) 420 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 421 sc->sc_dev.dv_xname); 422 423 /* Clear any pending rx interrupt */ 424 425 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 426 sc->sc_command | SEEQ_CMD_RX_INTACK); 427 return 1; 428 } 429 430 431 /* 432 * Stop interface. 433 * Stop all IO and shut the interface down 434 */ 435 436 static void 437 ea_stop(struct ifnet *ifp, int disable) 438 { 439 struct seeq8005_softc *sc = ifp->if_softc; 440 bus_space_tag_t iot = sc->sc_iot; 441 bus_space_handle_t ioh = sc->sc_ioh; 442 443 DPRINTF(SEEQ_DEBUG_MISC, ("seeq_stop()\n")); 444 445 /* Stop all IO */ 446 ea_stoptx(sc); 447 ea_stoprx(sc); 448 449 /* Disable rx and tx interrupts */ 450 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 451 452 /* Clear any pending interrupts */ 453 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 454 sc->sc_command | SEEQ_CMD_RX_INTACK | 455 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 456 SEEQ_CMD_BW_INTACK); 457 458 if (sc->sc_variant == SEEQ_8004) { 459 /* Put the chip to sleep */ 460 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 461 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 462 sc->sc_config3 | SEEQ_CFG3_SLEEP); 463 } 464 465 /* Cancel any watchdog timer */ 466 sc->sc_ethercom.ec_if.if_timer = 0; 467 } 468 469 470 /* 471 * Reset the chip 472 * Following this the software registers are reset 473 */ 474 475 static void 476 ea_chipreset(struct seeq8005_softc *sc) 477 { 478 bus_space_tag_t iot = sc->sc_iot; 479 bus_space_handle_t ioh = sc->sc_ioh; 480 481 DPRINTF(SEEQ_DEBUG_MISC, ("seeq_chipreset()\n")); 482 483 /* Reset the controller. Min of 4us delay here */ 484 485 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 486 delay(4); 487 488 sc->sc_command = 0; 489 sc->sc_config1 = 0; 490 sc->sc_config2 = 0; 491 sc->sc_config3 = 0; 492 } 493 494 495 /* 496 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 497 * switching the FIFO from write to read. We also use it when changing 498 * the address for writes. 499 */ 500 static void 501 ea_await_fifo_empty(struct seeq8005_softc *sc) 502 { 503 bus_space_tag_t iot = sc->sc_iot; 504 bus_space_handle_t ioh = sc->sc_ioh; 505 int timeout; 506 507 timeout = 20000; 508 if ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 509 SEEQ_STATUS_FIFO_DIR) != 0) 510 return; /* FIFO is reading anyway. */ 511 while ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 512 SEEQ_STATUS_FIFO_EMPTY) == 0 && 513 --timeout > 0) 514 continue; 515 } 516 517 /* 518 * Wait for the DMA FIFO to fill before reading from it. 519 */ 520 static void 521 ea_await_fifo_full(struct seeq8005_softc *sc) 522 { 523 bus_space_tag_t iot = sc->sc_iot; 524 bus_space_handle_t ioh = sc->sc_ioh; 525 int timeout; 526 527 timeout = 20000; 528 while ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 529 SEEQ_STATUS_FIFO_FULL) == 0 && 530 --timeout > 0) 531 continue; 532 } 533 534 /* 535 * write to the buffer memory on the interface 536 * 537 * The buffer address is set to ADDR. 538 * If len != 0 then data is copied from the address starting at buf 539 * to the interface buffer. 540 * BUF must be usable as a u_int16_t *. 541 * If LEN is odd, it must be safe to overwrite one extra byte. 542 */ 543 544 static void 545 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 546 { 547 bus_space_tag_t iot = sc->sc_iot; 548 bus_space_handle_t ioh = sc->sc_ioh; 549 550 dprintf(("writebuf: st=%04x\n", 551 bus_space_read_2(iot, ioh, SEEQ_STATUS))); 552 553 #ifdef DIAGNOSTIC 554 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 555 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 556 #endif 557 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 558 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 559 560 /* Assume that copying too much is safe. */ 561 if (len % 2 != 0) 562 len++; 563 564 if (addr != -1) { 565 ea_await_fifo_empty(sc); 566 567 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 568 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 569 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 570 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 571 } 572 573 if (len > 0) 574 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 575 (u_int16_t *)buf, len / 2); 576 /* Leave FIFO to empty in the background */ 577 } 578 579 580 /* 581 * read from the buffer memory on the interface 582 * 583 * The buffer address is set to ADDR. 584 * If len != 0 then data is copied from the interface buffer to the 585 * address starting at buf. 586 * BUF must be usable as a u_int16_t *. 587 * If LEN is odd, it must be safe to overwrite one extra byte. 588 */ 589 590 static void 591 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 592 { 593 594 bus_space_tag_t iot = sc->sc_iot; 595 bus_space_handle_t ioh = sc->sc_ioh; 596 597 dprintf(("readbuf: st=%04x addr=%04x len=%d\n", 598 bus_space_read_2(iot, ioh, SEEQ_STATUS), addr, len)); 599 600 #ifdef DIAGNOSTIC 601 if (!ALIGNED_POINTER(buf, u_int16_t)) 602 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 603 #endif 604 if (addr >= SEEQ_MAX_BUFFER_SIZE) 605 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 606 607 /* Assume that copying too much is safe. */ 608 if (len % 2 != 0) 609 len++; 610 611 if (addr != -1) { 612 ea_await_fifo_empty(sc); 613 614 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 615 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 616 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 617 sc->sc_command | SEEQ_CMD_FIFO_READ); 618 619 ea_await_fifo_full(sc); 620 } 621 622 if (len > 0) 623 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 624 (u_int16_t *)buf, len / 2); 625 } 626 627 static void 628 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 629 { 630 631 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 632 sc->sc_config1 | bufcode); 633 } 634 635 /* Must be called at splnet */ 636 static void 637 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 638 { 639 int i; 640 641 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 642 for (i = 0; i < ETHER_ADDR_LEN; ++i) 643 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 644 ea[i]); 645 } 646 647 /* 648 * Initialize interface. 649 * 650 * This should leave the interface in a state for packet reception and 651 * transmission. 652 */ 653 654 static int 655 ea_init(struct ifnet *ifp) 656 { 657 struct seeq8005_softc *sc = ifp->if_softc; 658 bus_space_tag_t iot = sc->sc_iot; 659 bus_space_handle_t ioh = sc->sc_ioh; 660 int s; 661 662 dprintf(("ea_init()\n")); 663 664 s = splnet(); 665 666 /* First, reset the board. */ 667 668 ea_chipreset(sc); 669 670 /* Set up defaults for the registers */ 671 672 sc->sc_command = 0; 673 sc->sc_config1 = 0; 674 #if BYTE_ORDER == BIG_ENDIAN 675 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 676 #else 677 sc->sc_config2 = 0; 678 #endif 679 sc->sc_config3 = 0; 680 681 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 682 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 683 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 684 if (sc->sc_variant == SEEQ_8004) { 685 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 686 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 687 } 688 689 /* Write the station address - the receiver must be off */ 690 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 691 692 /* Split board memory into Rx and Tx. */ 693 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 694 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 695 696 if (sc->sc_variant == SEEQ_8004) 697 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 698 699 /* Configure rx. */ 700 if (ifp->if_flags & IFF_PROMISC) 701 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 702 else if (ifp->if_flags & IFF_ALLMULTI) 703 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 704 else 705 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 706 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 707 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 708 709 /* Setup the Rx pointers */ 710 sc->sc_rx_ptr = sc->sc_tx_bufsize; 711 712 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 713 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 714 715 716 /* Place a NULL header at the beginning of the receive area */ 717 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 718 719 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 720 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 721 722 723 /* Configure TX. */ 724 dprintf(("Configuring tx...\n")); 725 726 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 727 728 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 729 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 730 731 /* Reset tx buffer pointers */ 732 sc->sc_tx_cur = 0; 733 sc->sc_tx_used = 0; 734 sc->sc_tx_next = 0; 735 736 /* Place a NULL header at the beginning of the transmit area */ 737 ea_writebuf(sc, NULL, 0x0000, 0); 738 739 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 740 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 741 742 sc->sc_command |= SEEQ_CMD_TX_INTEN; 743 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 744 745 /* Turn on Rx */ 746 sc->sc_command |= SEEQ_CMD_RX_INTEN; 747 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 748 sc->sc_command | SEEQ_CMD_RX_ON); 749 750 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 751 752 753 /* Set flags appropriately. */ 754 ifp->if_flags |= IFF_RUNNING; 755 ifp->if_flags &= ~IFF_OACTIVE; 756 sc->sc_enabled = 1; 757 758 /* And start output. */ 759 ea_start(ifp); 760 761 splx(s); 762 return 0; 763 } 764 765 /* 766 * Start output on interface. Get datagrams from the queue and output them, 767 * giving the receiver a chance between datagrams. Call only from splnet or 768 * interrupt level! 769 */ 770 771 static void 772 ea_start(struct ifnet *ifp) 773 { 774 struct seeq8005_softc *sc = ifp->if_softc; 775 int s; 776 777 s = splnet(); 778 #ifdef SEEQ_TX_DEBUG 779 dprintf(("ea_start()...\n")); 780 #endif 781 782 /* Don't do anything if output is active. */ 783 784 if (ifp->if_flags & IFF_OACTIVE) 785 return; 786 787 /* Mark interface as output active */ 788 789 ifp->if_flags |= IFF_OACTIVE; 790 791 /* tx packets */ 792 793 eatxpacket(sc); 794 splx(s); 795 } 796 797 798 /* 799 * Transfer a packet to the interface buffer and start transmission 800 * 801 * Called at splnet() 802 */ 803 804 void 805 eatxpacket(struct seeq8005_softc *sc) 806 { 807 bus_space_tag_t iot = sc->sc_iot; 808 bus_space_handle_t ioh = sc->sc_ioh; 809 struct mbuf *m, *m0; 810 struct ifnet *ifp; 811 int len, nextpacket; 812 u_int8_t hdr[4]; 813 814 ifp = &sc->sc_ethercom.ec_if; 815 816 /* Dequeue the next packet. */ 817 IFQ_DEQUEUE(&ifp->if_snd, m0); 818 819 /* If there's nothing to send, return. */ 820 if (!m0) { 821 ifp->if_flags &= ~IFF_OACTIVE; 822 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 823 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 824 #ifdef SEEQ_TX_DEBUG 825 dprintf(("tx finished\n")); 826 #endif 827 return; 828 } 829 830 #if NBPFILTER > 0 831 /* Give the packet to the bpf, if any. */ 832 if (ifp->if_bpf) 833 bpf_mtap(ifp->if_bpf, m0); 834 #endif 835 836 #ifdef SEEQ_TX_DEBUG 837 dprintf(("Tx new packet\n")); 838 #endif 839 840 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 841 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 842 843 /* 844 * Copy the frame to the start of the transmit area on the card, 845 * leaving four bytes for the transmit header. 846 */ 847 len = 0; 848 for (m = m0; m; m = m->m_next) { 849 if (m->m_len == 0) 850 continue; 851 ea_writebuf(sc, mtod(m, caddr_t), 4 + len, m->m_len); 852 len += m->m_len; 853 } 854 m_freem(m0); 855 856 857 /* If packet size is odd round up to the next 16 bit boundry */ 858 if (len % 2) 859 ++len; 860 861 len = max(len, ETHER_MIN_LEN); 862 863 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN)) 864 log(LOG_WARNING, "%s: oversize packet = %d bytes\n", 865 sc->sc_dev.dv_xname, len); 866 867 #if 0 /*def SEEQ_TX_DEBUG*/ 868 dprintf(("ea: xfr pkt length=%d...\n", len)); 869 870 dprintf(("%s-->", ether_sprintf(sc->sc_pktbuf+6))); 871 dprintf(("%s\n", ether_sprintf(sc->sc_pktbuf))); 872 #endif 873 874 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS)));*/ 875 876 /* Follow it with a NULL packet header */ 877 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 878 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 879 880 881 /* Write the packet header */ 882 883 nextpacket = len + 4; 884 hdr[0] = (nextpacket >> 8) & 0xff; 885 hdr[1] = nextpacket & 0xff; 886 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 887 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 888 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 889 ea_writebuf(sc, hdr, 0x0000, 4); 890 891 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 892 893 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS)));*/ 894 895 #ifdef SEEQ_PACKET_DEBUG 896 ea_dump_buffer(sc, 0); 897 #endif 898 899 900 /* Now transmit the datagram. */ 901 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS)));*/ 902 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 903 sc->sc_command | SEEQ_CMD_TX_ON); 904 #ifdef SEEQ_TX_DEBUG 905 dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS))); 906 dprintf(("tx: queued\n")); 907 #endif 908 } 909 910 911 /* 912 * Ethernet controller interrupt. 913 */ 914 915 int 916 seeq8005intr(void *arg) 917 { 918 struct seeq8005_softc *sc = arg; 919 bus_space_tag_t iot = sc->sc_iot; 920 bus_space_handle_t ioh = sc->sc_ioh; 921 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 922 int status, handled; 923 u_int8_t txhdr[4]; 924 u_int txstatus; 925 926 handled = 0; 927 dprintf(("eaintr: ")); 928 929 930 /* Get the controller status */ 931 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 932 dprintf(("st=%04x ", status)); 933 934 935 /* Tx interrupt ? */ 936 if (status & SEEQ_STATUS_TX_INT) { 937 dprintf(("txint ")); 938 handled = 1; 939 940 /* Acknowledge the interrupt */ 941 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 942 sc->sc_command | SEEQ_CMD_TX_INTACK); 943 944 ea_readbuf(sc, txhdr, 0x0000, 4); 945 946 #ifdef SEEQ_TX_DEBUG 947 dprintf(("txstatus=%02x %02x %02x %02x\n", 948 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 949 #endif 950 txstatus = txhdr[3]; 951 952 /* 953 * If SEEQ_TXSTAT_COLLISION is set then we received at least 954 * one collision. On the 8004 we can find out exactly how many 955 * collisions occurred. 956 * 957 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 958 * completed. 959 * 960 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 961 * occurred and the packet transmission was aborted. 962 * This situation is untested as present. 963 * 964 * The SEEQ_TXSTAT_BABBLE should never be set and is untested 965 * as we should never xmit oversized packets. 966 */ 967 if (txstatus & SEEQ_TXSTAT_COLLISION) { 968 switch (sc->sc_variant) { 969 case SEEQ_8004: { 970 int colls; 971 972 /* 973 * The 8004 contains a 4 bit collision count 974 * in the status register. 975 */ 976 977 /* This appears to be broken on 80C04.AE */ 978 /* ifp->if_collisions += 979 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 980 & SEEQ_TXSTAT_COLLISION_MASK;*/ 981 982 /* Use the TX Collision register */ 983 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 984 colls = bus_space_read_1(iot, ioh, 985 SEEQ_BUFWIN); 986 ifp->if_collisions += colls; 987 break; 988 } 989 case SEEQ_8005: 990 /* We known there was at least 1 collision */ 991 ifp->if_collisions++; 992 break; 993 } 994 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 995 printf("seeq_intr: col16 %x\n", txstatus); 996 ifp->if_collisions += 16; 997 ifp->if_oerrors++; 998 } else if (txstatus & SEEQ_TXSTAT_BABBLE) { 999 ifp->if_oerrors++; 1000 } 1001 1002 /* Have we completed transmission on the packet ? */ 1003 if (txstatus & SEEQ_PKTSTAT_DONE) { 1004 /* Clear watchdog timer. */ 1005 ifp->if_timer = 0; 1006 ifp->if_flags &= ~IFF_OACTIVE; 1007 1008 /* Update stats */ 1009 ifp->if_opackets++; 1010 1011 /* Tx next packet */ 1012 1013 eatxpacket(sc); 1014 } 1015 1016 } 1017 1018 1019 /* Rx interrupt ? */ 1020 if (status & SEEQ_STATUS_RX_INT) { 1021 dprintf(("rxint ")); 1022 handled = 1; 1023 1024 /* Acknowledge the interrupt */ 1025 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1026 sc->sc_command | SEEQ_CMD_RX_INTACK); 1027 1028 /* Processes the received packets */ 1029 ea_getpackets(sc); 1030 1031 1032 #if 0 1033 /* Make sure the receiver is on */ 1034 if ((status & SEEQ_STATUS_RX_ON) == 0) { 1035 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1036 sc->sc_command | SEEQ_CMD_RX_ON); 1037 printf("rxintr: rx is off st=%04x\n",status); 1038 } 1039 #endif 1040 } 1041 1042 #ifdef SEEQ_DEBUG 1043 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 1044 dprintf(("st=%04x\n", status)); 1045 #endif 1046 1047 return handled; 1048 } 1049 1050 1051 void 1052 ea_getpackets(struct seeq8005_softc *sc) 1053 { 1054 bus_space_tag_t iot = sc->sc_iot; 1055 bus_space_handle_t ioh = sc->sc_ioh; 1056 u_int addr; 1057 int len; 1058 int ctrl; 1059 int ptr; 1060 int pack; 1061 int status; 1062 u_int8_t rxhdr[4]; 1063 struct ifnet *ifp; 1064 1065 ifp = &sc->sc_ethercom.ec_if; 1066 1067 1068 /* We start from the last rx pointer position */ 1069 addr = sc->sc_rx_ptr; 1070 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1071 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1072 1073 do { 1074 /* Read rx header */ 1075 ea_readbuf(sc, rxhdr, addr, 4); 1076 1077 /* Split the packet header */ 1078 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1079 ctrl = rxhdr[2]; 1080 status = rxhdr[3]; 1081 1082 #ifdef SEEQ_RX_DEBUG 1083 dprintf(("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1084 addr, ptr, ctrl, status)); 1085 #endif 1086 1087 1088 /* Zero packet ptr ? then must be null header so exit */ 1089 if (ptr == 0) break; 1090 1091 1092 /* Get packet length */ 1093 len = (ptr - addr) - 4; 1094 1095 if (len < 0) 1096 len += sc->sc_rx_bufsize; 1097 1098 #ifdef SEEQ_RX_DEBUG 1099 dprintf(("len=%04x\n", len)); 1100 #endif 1101 1102 1103 /* Has the packet rx completed ? if not then exit */ 1104 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1105 break; 1106 1107 /* 1108 * Did we have any errors? then note error and go to 1109 * next packet 1110 */ 1111 if (__predict_false(status & SEEQ_RXSTAT_ERROR_MASK)) { 1112 ++ifp->if_ierrors; 1113 log(LOG_WARNING, 1114 "%s: rx packet error (%02x) - dropping packet\n", 1115 sc->sc_dev.dv_xname, status & 0x0f); 1116 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1117 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, 1118 sc->sc_config2); 1119 ea_init(ifp); 1120 return; 1121 } 1122 1123 /* 1124 * Is the packet too big ? - this will probably be trapped 1125 * above as a receive error 1126 */ 1127 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1128 ++ifp->if_ierrors; 1129 log(LOG_WARNING, "%s: rx packet size error len=%d\n", 1130 sc->sc_dev.dv_xname, len); 1131 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1132 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, 1133 sc->sc_config2); 1134 ea_init(ifp); 1135 return; 1136 } 1137 1138 ifp->if_ipackets++; 1139 /* Pass data up to upper levels. */ 1140 ea_read(sc, addr + 4, len); 1141 1142 addr = ptr; 1143 ++pack; 1144 } while (len != 0); 1145 1146 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1147 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1148 1149 #ifdef SEEQ_RX_DEBUG 1150 dprintf(("new rx ptr=%04x\n", addr)); 1151 #endif 1152 1153 1154 /* Store new rx pointer */ 1155 sc->sc_rx_ptr = addr; 1156 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1157 1158 /* Make sure the receiver is on */ 1159 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1160 sc->sc_command | SEEQ_CMD_RX_ON); 1161 1162 } 1163 1164 1165 /* 1166 * Pass a packet up to the higher levels. 1167 */ 1168 1169 static void 1170 ea_read(struct seeq8005_softc *sc, int addr, int len) 1171 { 1172 struct mbuf *m; 1173 struct ifnet *ifp; 1174 1175 ifp = &sc->sc_ethercom.ec_if; 1176 1177 /* Pull packet off interface. */ 1178 m = ea_get(sc, addr, len, ifp); 1179 if (m == 0) 1180 return; 1181 1182 #ifdef SEEQ_RX_DEBUG 1183 dprintf(("%s-->", ether_sprintf(eh->ether_shost))); 1184 dprintf(("%s\n", ether_sprintf(eh->ether_dhost))); 1185 #endif 1186 1187 #if NBPFILTER > 0 1188 /* 1189 * Check if there's a BPF listener on this interface. 1190 * If so, hand off the raw packet to bpf. 1191 */ 1192 if (ifp->if_bpf) 1193 bpf_mtap(ifp->if_bpf, m); 1194 #endif 1195 1196 (*ifp->if_input)(ifp, m); 1197 } 1198 1199 /* 1200 * Pull read data off a interface. Len is length of data, with local net 1201 * header stripped. We copy the data into mbufs. When full cluster sized 1202 * units are present we copy into clusters. 1203 */ 1204 1205 struct mbuf * 1206 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1207 { 1208 struct mbuf *top, **mp, *m; 1209 int len; 1210 u_int cp, epkt; 1211 1212 cp = addr; 1213 epkt = cp + totlen; 1214 1215 MGETHDR(m, M_DONTWAIT, MT_DATA); 1216 if (m == 0) 1217 return 0; 1218 m->m_pkthdr.rcvif = ifp; 1219 m->m_pkthdr.len = totlen; 1220 m->m_len = MHLEN; 1221 top = 0; 1222 mp = ⊤ 1223 1224 while (totlen > 0) { 1225 if (top) { 1226 MGET(m, M_DONTWAIT, MT_DATA); 1227 if (m == 0) { 1228 m_freem(top); 1229 return 0; 1230 } 1231 m->m_len = MLEN; 1232 } 1233 len = min(totlen, epkt - cp); 1234 if (len >= MINCLSIZE) { 1235 MCLGET(m, M_DONTWAIT); 1236 if (m->m_flags & M_EXT) 1237 m->m_len = len = min(len, MCLBYTES); 1238 else 1239 len = m->m_len; 1240 } else { 1241 /* 1242 * Place initial small packet/header at end of mbuf. 1243 */ 1244 if (len < m->m_len) { 1245 if (top == 0 && len + max_linkhdr <= m->m_len) 1246 m->m_data += max_linkhdr; 1247 m->m_len = len; 1248 } else 1249 len = m->m_len; 1250 } 1251 if (top == 0) { 1252 /* Make sure the payload is aligned */ 1253 caddr_t newdata = (caddr_t) 1254 ALIGN(m->m_data + sizeof(struct ether_header)) - 1255 sizeof(struct ether_header); 1256 len -= newdata - m->m_data; 1257 m->m_len = len; 1258 m->m_data = newdata; 1259 } 1260 ea_readbuf(sc, mtod(m, u_char *), 1261 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1262 len); 1263 cp += len; 1264 *mp = m; 1265 mp = &m->m_next; 1266 totlen -= len; 1267 if (cp == epkt) 1268 cp = addr; 1269 } 1270 1271 return top; 1272 } 1273 1274 /* 1275 * Process an ioctl request. Mostly boilerplate. 1276 */ 1277 static int 1278 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1279 { 1280 struct seeq8005_softc *sc = ifp->if_softc; 1281 int s, error = 0; 1282 1283 s = splnet(); 1284 switch (cmd) { 1285 1286 default: 1287 error = ether_ioctl(ifp, cmd, data); 1288 if (error == ENETRESET) { 1289 /* 1290 * Multicast list has changed; set the hardware filter 1291 * accordingly. 1292 */ 1293 ea_mc_reset(sc); 1294 error = 0; 1295 } 1296 break; 1297 } 1298 1299 splx(s); 1300 return error; 1301 } 1302 1303 /* Must be called at splnet() */ 1304 1305 static void 1306 ea_mc_reset(struct seeq8005_softc *sc) 1307 { 1308 1309 switch (sc->sc_variant) { 1310 case SEEQ_8004: 1311 ea_mc_reset_8004(sc); 1312 return; 1313 case SEEQ_8005: 1314 ea_mc_reset_8005(sc); 1315 return; 1316 } 1317 } 1318 1319 static void 1320 ea_mc_reset_8004(struct seeq8005_softc *sc) 1321 { 1322 struct ethercom *ec = &sc->sc_ethercom; 1323 struct ifnet *ifp = &ec->ec_if; 1324 struct ether_multi *enm; 1325 u_int8_t *cp, c; 1326 u_int32_t crc; 1327 int i, len; 1328 struct ether_multistep step; 1329 u_int8_t af[8]; 1330 1331 /* 1332 * Set up multicast address filter by passing all multicast addresses 1333 * through a crc generator, and then using bits 2 - 7 as an index 1334 * into the 64 bit logical address filter. The high order bits 1335 * selects the word, while the rest of the bits select the bit within 1336 * the word. 1337 */ 1338 1339 if (ifp->if_flags & IFF_PROMISC) { 1340 ifp->if_flags |= IFF_ALLMULTI; 1341 for (i = 0; i < 8; i++) 1342 af[i] = 0xff; 1343 return; 1344 } 1345 for (i = 0; i < 8; i++) 1346 af[i] = 0; 1347 ETHER_FIRST_MULTI(step, ec, enm); 1348 while (enm != NULL) { 1349 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1350 sizeof(enm->enm_addrlo)) != 0) { 1351 /* 1352 * We must listen to a range of multicast addresses. 1353 * For now, just accept all multicasts, rather than 1354 * trying to set only those filter bits needed to match 1355 * the range. (At this time, the only use of address 1356 * ranges is for IP multicast routing, for which the 1357 * range is big enough to require all bits set.) 1358 */ 1359 ifp->if_flags |= IFF_ALLMULTI; 1360 for (i = 0; i < 8; i++) 1361 af[i] = 0xff; 1362 return; 1363 } 1364 cp = enm->enm_addrlo; 1365 crc = 0xffffffff; 1366 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1367 c = *cp++; 1368 for (i = 8; --i >= 0;) { 1369 if (((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01)) { 1370 crc <<= 1; 1371 crc ^= 0x04c11db6 | 1; 1372 } else 1373 crc <<= 1; 1374 c >>= 1; 1375 } 1376 } 1377 /* Just want the 6 most significant bits. */ 1378 crc = (crc >> 2) & 0x3f; 1379 1380 /* Turn on the corresponding bit in the filter. */ 1381 af[crc >> 3] |= 1 << (crc & 0x7); 1382 1383 ETHER_NEXT_MULTI(step, enm); 1384 } 1385 ifp->if_flags &= ~IFF_ALLMULTI; 1386 1387 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1388 for (i = 0; i < 8; ++i) 1389 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1390 SEEQ_BUFWIN, af[i]); 1391 } 1392 1393 static void 1394 ea_mc_reset_8005(struct seeq8005_softc *sc) 1395 { 1396 struct ether_multi *enm; 1397 struct ether_multistep step; 1398 int naddr, maxaddrs; 1399 1400 naddr = 0; 1401 maxaddrs = 5; 1402 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1403 while (enm != NULL) { 1404 /* Have we got space? */ 1405 if (naddr >= maxaddrs || 1406 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1407 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1408 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1409 return; 1410 } 1411 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1412 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1413 naddr++; 1414 ETHER_NEXT_MULTI(step, enm); 1415 } 1416 for (; naddr < maxaddrs; naddr++) 1417 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1418 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1419 sc->sc_config1); 1420 } 1421 1422 /* 1423 * Device timeout routine. 1424 * 1425 * Ok I am not sure exactly how the device timeout should work.... 1426 * Currently what will happens is that that the device timeout is only 1427 * set when a packet it received. This indicates we are on an active 1428 * network and thus we should expect more packets. If non arrive in 1429 * in the timeout period then we reinitialise as we may have jammed. 1430 * We zero the timeout at this point so that we don't end up with 1431 * an endless stream of timeouts if the network goes down. 1432 */ 1433 1434 static void 1435 ea_watchdog(struct ifnet *ifp) 1436 { 1437 struct seeq8005_softc *sc = ifp->if_softc; 1438 1439 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1440 ifp->if_oerrors++; 1441 dprintf(("ea_watchdog: ")); 1442 dprintf(("st=%04x\n", 1443 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_STATUS))); 1444 1445 /* Kick the interface */ 1446 1447 ea_init(ifp); 1448 1449 /* ifp->if_timer = SEEQ_TIMEOUT;*/ 1450 ifp->if_timer = 0; 1451 } 1452 1453 /* End of if_ea.c */ 1454
Indexes created Mon Sep 29 21:09:56 GMT 2025