seeq8005.c revision 1.13
1 /* $NetBSD: seeq8005.c,v 1.13 2001/03/25 01:06:59 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chip: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 */ 43 /* 44 * More information on the 8004 and 8005 AEDLC controllers can be found in 45 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 46 * 47 * This data book may no longer be available as these are rather old chips 48 * (1991 - 1993) 49 */ 50 /* 51 * This driver is based on the arm32 ea(4) driver, hence the names of many 52 * of the functions. 53 */ 54 /* 55 * Bugs/possible improvements: 56 * - Does not currently support DMA 57 * - Does not transmit multiple packets in one go 58 * - Does not support 8-bit busses 59 */ 60 61 #include "opt_inet.h" 62 #include "opt_ns.h" 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 67 __RCSID("$NetBSD: seeq8005.c,v 1.13 2001/03/25 01:06:59 bjh21 Exp $"); 68 69 #include <sys/systm.h> 70 #include <sys/endian.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_types.h> 81 #include <net/if_ether.h> 82 #include <net/if_media.h> 83 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/in_systm.h> 87 #include <netinet/in_var.h> 88 #include <netinet/ip.h> 89 #include <netinet/if_inarp.h> 90 #endif 91 92 #ifdef NS 93 #include <netns/ns.h> 94 #include <netns/ns_if.h> 95 #endif 96 97 #include "bpfilter.h" 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <machine/bus.h> 104 #include <machine/intr.h> 105 106 #include <dev/ic/seeq8005reg.h> 107 #include <dev/ic/seeq8005var.h> 108 109 /*#define SEEQ_DEBUG*/ 110 111 /* for debugging convenience */ 112 #ifdef SEEQ_DEBUG 113 #define SEEQ_DEBUG_MISC 1 114 #define SEEQ_DEBUG_TX 2 115 #define SEEQ_DEBUG_RX 4 116 #define SEEQ_DEBUG_PKT 8 117 #define SEEQ_DEBUG_TXINT 16 118 #define SEEQ_DEBUG_RXINT 32 119 int seeq_debug = 0; 120 #define DPRINTF(f, x) { if (seeq_debug & (f)) printf x; } 121 #else 122 #define DPRINTF(f, x) 123 #endif 124 #define dprintf(x) DPRINTF(SEEQ_DEBUG_MISC, x) 125 126 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> MAX_ETHER_LEN) */ 127 128 /* 129 * prototypes 130 */ 131 132 static int ea_init(struct ifnet *); 133 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 134 static void ea_start(struct ifnet *); 135 static void ea_watchdog(struct ifnet *); 136 static void ea_chipreset(struct seeq8005_softc *); 137 static void ea_ramtest(struct seeq8005_softc *); 138 static int ea_stoptx(struct seeq8005_softc *); 139 static int ea_stoprx(struct seeq8005_softc *); 140 static void ea_stop(struct ifnet *, int); 141 static void ea_await_fifo_empty(struct seeq8005_softc *); 142 static void ea_await_fifo_full(struct seeq8005_softc *); 143 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 145 static void ea_select_buffer(struct seeq8005_softc *, int); 146 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 147 static void ea_read(struct seeq8005_softc *, int, int); 148 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 149 static void ea_getpackets(struct seeq8005_softc *); 150 static void eatxpacket(struct seeq8005_softc *); 151 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 152 static void ea_mc_reset(struct seeq8005_softc *); 153 static void ea_mc_reset_8004(struct seeq8005_softc *); 154 static void ea_mc_reset_8005(struct seeq8005_softc *); 155 static int ea_mediachange(struct ifnet *); 156 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 157 158 159 /* 160 * Attach chip. 161 */ 162 163 void 164 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 165 int nmedia, int defmedia) 166 { 167 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 168 u_int id; 169 170 KASSERT(myaddr != NULL); 171 printf(" address %s", ether_sprintf(myaddr)); 172 173 /* Stop the board. */ 174 175 ea_chipreset(sc); 176 177 /* Get the product ID */ 178 179 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 180 id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 181 182 switch (id & SEEQ_PRODUCTID_MASK) { 183 case SEEQ_PRODUCTID_8004: 184 sc->sc_variant = SEEQ_8004; 185 break; 186 default: /* XXX */ 187 sc->sc_variant = SEEQ_8005; 188 break; 189 } 190 191 switch (sc->sc_variant) { 192 case SEEQ_8004: 193 printf(", SEEQ80C04 rev %x\n", 194 id & SEEQ_PRODUCTID_REV_MASK); 195 break; 196 case SEEQ_8005: 197 if (id != 0xff) 198 printf(", SEEQ8005 rev %x\n", id); 199 else 200 printf(", SEEQ8005\n"); 201 break; 202 default: 203 printf(", Unknown ethernet controller\n"); 204 return; 205 } 206 207 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 208 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 209 210 /* 211 * Set up tx and rx buffers. 212 * 213 * We use approximately a quarter of the packet memory for TX 214 * buffers and the rest for RX buffers 215 */ 216 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 217 sc->sc_tx_bufs = 1; 218 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 219 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 220 sc->sc_enabled = 0; 221 222 /* Test the RAM */ 223 ea_ramtest(sc); 224 225 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 226 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 227 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 228 229 /* Initialise ifnet structure. */ 230 231 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 232 ifp->if_softc = sc; 233 ifp->if_start = ea_start; 234 ifp->if_ioctl = ea_ioctl; 235 ifp->if_init = ea_init; 236 ifp->if_stop = ea_stop; 237 ifp->if_watchdog = ea_watchdog; 238 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 239 if (sc->sc_variant == SEEQ_8004) 240 ifp->if_flags |= IFF_SIMPLEX; 241 IFQ_SET_READY(&ifp->if_snd); 242 243 /* Initialize media goo. */ 244 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 245 if (media != NULL) { 246 int i; 247 248 for (i = 0; i < nmedia; i++) 249 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 250 ifmedia_set(&sc->sc_media, defmedia); 251 } else { 252 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 253 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 254 } 255 256 /* Now we can attach the interface. */ 257 258 if_attach(ifp); 259 ether_ifattach(ifp, myaddr); 260 261 printf("\n"); 262 } 263 264 /* 265 * Media change callback. 266 */ 267 static int 268 ea_mediachange(struct ifnet *ifp) 269 { 270 struct seeq8005_softc *sc = ifp->if_softc; 271 272 if (sc->sc_mediachange) 273 return ((*sc->sc_mediachange)(sc)); 274 return (EINVAL); 275 } 276 277 /* 278 * Media status callback. 279 */ 280 static void 281 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 282 { 283 struct seeq8005_softc *sc = ifp->if_softc; 284 285 if (sc->sc_enabled == 0) { 286 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 287 ifmr->ifm_status = 0; 288 return; 289 } 290 291 if (sc->sc_mediastatus) 292 (*sc->sc_mediastatus)(sc, ifmr); 293 } 294 295 /* 296 * Test the RAM on the ethernet card. 297 */ 298 299 void 300 ea_ramtest(struct seeq8005_softc *sc) 301 { 302 bus_space_tag_t iot = sc->sc_iot; 303 bus_space_handle_t ioh = sc->sc_ioh; 304 int loop; 305 u_int sum = 0; 306 307 /* dprintf(("ea_ramtest()\n"));*/ 308 309 /* 310 * Test the buffer memory on the board. 311 * Write simple pattens to it and read them back. 312 */ 313 314 /* Set up the whole buffer RAM for writing */ 315 316 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 317 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 318 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 319 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 320 321 #define SEEQ_RAMTEST_LOOP(value) \ 322 do { \ 323 /* Set the write start address and write a pattern */ \ 324 ea_writebuf(sc, NULL, 0x0000, 0); \ 325 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 326 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (value)); \ 327 \ 328 /* Set the read start address and verify the pattern */ \ 329 ea_readbuf(sc, NULL, 0x0000, 0); \ 330 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 331 if (bus_space_read_2(iot, ioh, SEEQ_BUFWIN) != (value)) \ 332 ++sum; \ 333 if (sum != 0) \ 334 dprintf(("sum=%d\n", sum)); \ 335 } while (/*CONSTCOND*/0) 336 337 SEEQ_RAMTEST_LOOP(loop); 338 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 339 SEEQ_RAMTEST_LOOP(0xaa55); 340 SEEQ_RAMTEST_LOOP(0x55aa); 341 342 /* Report */ 343 344 if (sum > 0) 345 printf("%s: buffer RAM failed self test, %d faults\n", 346 sc->sc_dev.dv_xname, sum); 347 } 348 349 350 /* 351 * Stop the tx interface. 352 * 353 * Returns 0 if the tx was already stopped or 1 if it was active 354 */ 355 356 static int 357 ea_stoptx(struct seeq8005_softc *sc) 358 { 359 bus_space_tag_t iot = sc->sc_iot; 360 bus_space_handle_t ioh = sc->sc_ioh; 361 int timeout; 362 int status; 363 364 DPRINTF(SEEQ_DEBUG_TX, ("seeq_stoptx()\n")); 365 366 sc->sc_enabled = 0; 367 368 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 369 if (!(status & SEEQ_STATUS_TX_ON)) 370 return 0; 371 372 /* Stop any tx and wait for confirmation */ 373 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 374 sc->sc_command | SEEQ_CMD_TX_OFF); 375 376 timeout = 20000; 377 do { 378 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 379 delay(1); 380 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 381 if (timeout == 0) 382 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 383 sc->sc_dev.dv_xname); 384 385 /* Clear any pending tx interrupt */ 386 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 387 sc->sc_command | SEEQ_CMD_TX_INTACK); 388 return 1; 389 } 390 391 392 /* 393 * Stop the rx interface. 394 * 395 * Returns 0 if the tx was already stopped or 1 if it was active 396 */ 397 398 static int 399 ea_stoprx(struct seeq8005_softc *sc) 400 { 401 bus_space_tag_t iot = sc->sc_iot; 402 bus_space_handle_t ioh = sc->sc_ioh; 403 int timeout; 404 int status; 405 406 DPRINTF(SEEQ_DEBUG_RX, ("seeq_stoprx()\n")); 407 408 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 409 if (!(status & SEEQ_STATUS_RX_ON)) 410 return 0; 411 412 /* Stop any rx and wait for confirmation */ 413 414 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 415 sc->sc_command | SEEQ_CMD_RX_OFF); 416 417 timeout = 20000; 418 do { 419 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 420 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 421 if (timeout == 0) 422 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 423 sc->sc_dev.dv_xname); 424 425 /* Clear any pending rx interrupt */ 426 427 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 428 sc->sc_command | SEEQ_CMD_RX_INTACK); 429 return 1; 430 } 431 432 433 /* 434 * Stop interface. 435 * Stop all IO and shut the interface down 436 */ 437 438 static void 439 ea_stop(struct ifnet *ifp, int disable) 440 { 441 struct seeq8005_softc *sc = ifp->if_softc; 442 bus_space_tag_t iot = sc->sc_iot; 443 bus_space_handle_t ioh = sc->sc_ioh; 444 445 DPRINTF(SEEQ_DEBUG_MISC, ("seeq_stop()\n")); 446 447 /* Stop all IO */ 448 ea_stoptx(sc); 449 ea_stoprx(sc); 450 451 /* Disable rx and tx interrupts */ 452 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 453 454 /* Clear any pending interrupts */ 455 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 456 sc->sc_command | SEEQ_CMD_RX_INTACK | 457 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 458 SEEQ_CMD_BW_INTACK); 459 460 if (sc->sc_variant == SEEQ_8004) { 461 /* Put the chip to sleep */ 462 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 463 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 464 sc->sc_config3 | SEEQ_CFG3_SLEEP); 465 } 466 467 /* Cancel any watchdog timer */ 468 sc->sc_ethercom.ec_if.if_timer = 0; 469 } 470 471 472 /* 473 * Reset the chip 474 * Following this the software registers are reset 475 */ 476 477 static void 478 ea_chipreset(struct seeq8005_softc *sc) 479 { 480 bus_space_tag_t iot = sc->sc_iot; 481 bus_space_handle_t ioh = sc->sc_ioh; 482 483 DPRINTF(SEEQ_DEBUG_MISC, ("seeq_chipreset()\n")); 484 485 /* Reset the controller. Min of 4us delay here */ 486 487 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 488 delay(4); 489 490 sc->sc_command = 0; 491 sc->sc_config1 = 0; 492 sc->sc_config2 = 0; 493 sc->sc_config3 = 0; 494 } 495 496 497 /* 498 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 499 * switching the FIFO from write to read. We also use it when changing 500 * the address for writes. 501 */ 502 static void 503 ea_await_fifo_empty(struct seeq8005_softc *sc) 504 { 505 bus_space_tag_t iot = sc->sc_iot; 506 bus_space_handle_t ioh = sc->sc_ioh; 507 int timeout; 508 509 timeout = 20000; 510 if ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 511 SEEQ_STATUS_FIFO_DIR) != 0) 512 return; /* FIFO is reading anyway. */ 513 while ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 514 SEEQ_STATUS_FIFO_EMPTY) == 0 && 515 --timeout > 0) 516 continue; 517 } 518 519 /* 520 * Wait for the DMA FIFO to fill before reading from it. 521 */ 522 static void 523 ea_await_fifo_full(struct seeq8005_softc *sc) 524 { 525 bus_space_tag_t iot = sc->sc_iot; 526 bus_space_handle_t ioh = sc->sc_ioh; 527 int timeout; 528 529 timeout = 20000; 530 while ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 531 SEEQ_STATUS_FIFO_FULL) == 0 && 532 --timeout > 0) 533 continue; 534 } 535 536 /* 537 * write to the buffer memory on the interface 538 * 539 * The buffer address is set to ADDR. 540 * If len != 0 then data is copied from the address starting at buf 541 * to the interface buffer. 542 * BUF must be usable as a u_int16_t *. 543 * If LEN is odd, it must be safe to overwrite one extra byte. 544 */ 545 546 static void 547 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 548 { 549 bus_space_tag_t iot = sc->sc_iot; 550 bus_space_handle_t ioh = sc->sc_ioh; 551 552 dprintf(("writebuf: st=%04x\n", 553 bus_space_read_2(iot, ioh, SEEQ_STATUS))); 554 555 #ifdef DIAGNOSTIC 556 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 557 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 558 #endif 559 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 560 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 561 562 /* Assume that copying too much is safe. */ 563 if (len % 2 != 0) 564 len++; 565 566 if (addr != -1) { 567 ea_await_fifo_empty(sc); 568 569 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 570 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 571 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 572 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 573 } 574 575 if (len > 0) 576 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 577 (u_int16_t *)buf, len / 2); 578 /* Leave FIFO to empty in the background */ 579 } 580 581 582 /* 583 * read from the buffer memory on the interface 584 * 585 * The buffer address is set to ADDR. 586 * If len != 0 then data is copied from the interface buffer to the 587 * address starting at buf. 588 * BUF must be usable as a u_int16_t *. 589 * If LEN is odd, it must be safe to overwrite one extra byte. 590 */ 591 592 static void 593 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 594 { 595 596 bus_space_tag_t iot = sc->sc_iot; 597 bus_space_handle_t ioh = sc->sc_ioh; 598 599 dprintf(("readbuf: st=%04x addr=%04x len=%d\n", 600 bus_space_read_2(iot, ioh, SEEQ_STATUS), addr, len)); 601 602 #ifdef DIAGNOSTIC 603 if (!ALIGNED_POINTER(buf, u_int16_t)) 604 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 605 #endif 606 if (addr >= SEEQ_MAX_BUFFER_SIZE) 607 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 608 609 /* Assume that copying too much is safe. */ 610 if (len % 2 != 0) 611 len++; 612 613 if (addr != -1) { 614 ea_await_fifo_empty(sc); 615 616 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 617 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 618 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 619 sc->sc_command | SEEQ_CMD_FIFO_READ); 620 621 ea_await_fifo_full(sc); 622 } 623 624 if (len > 0) 625 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 626 (u_int16_t *)buf, len / 2); 627 } 628 629 static void 630 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 631 { 632 633 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 634 sc->sc_config1 | bufcode); 635 } 636 637 /* Must be called at splnet */ 638 static void 639 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 640 { 641 int i; 642 643 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 644 for (i = 0; i < ETHER_ADDR_LEN; ++i) 645 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 646 ea[i]); 647 } 648 649 /* 650 * Initialize interface. 651 * 652 * This should leave the interface in a state for packet reception and 653 * transmission. 654 */ 655 656 static int 657 ea_init(struct ifnet *ifp) 658 { 659 struct seeq8005_softc *sc = ifp->if_softc; 660 bus_space_tag_t iot = sc->sc_iot; 661 bus_space_handle_t ioh = sc->sc_ioh; 662 int s; 663 664 dprintf(("ea_init()\n")); 665 666 s = splnet(); 667 668 /* First, reset the board. */ 669 670 ea_chipreset(sc); 671 672 /* Set up defaults for the registers */ 673 674 sc->sc_command = 0; 675 sc->sc_config1 = 0; 676 #if BYTE_ORDER == BIG_ENDIAN 677 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 678 #else 679 sc->sc_config2 = 0; 680 #endif 681 sc->sc_config3 = 0; 682 683 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 684 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 685 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 686 if (sc->sc_variant == SEEQ_8004) { 687 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 688 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 689 } 690 691 /* Write the station address - the receiver must be off */ 692 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 693 694 /* Split board memory into Rx and Tx. */ 695 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 696 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 697 698 if (sc->sc_variant == SEEQ_8004) 699 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 700 701 /* Configure rx. */ 702 ea_mc_reset(sc); 703 if (ifp->if_flags & IFF_PROMISC) 704 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 705 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 706 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 707 else 708 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 709 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 710 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 711 712 /* Setup the Rx pointers */ 713 sc->sc_rx_ptr = sc->sc_tx_bufsize; 714 715 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 716 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 717 718 719 /* Place a NULL header at the beginning of the receive area */ 720 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 721 722 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 723 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 724 725 726 /* Configure TX. */ 727 dprintf(("Configuring tx...\n")); 728 729 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 730 731 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 732 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 733 734 /* Reset tx buffer pointers */ 735 sc->sc_tx_cur = 0; 736 sc->sc_tx_used = 0; 737 sc->sc_tx_next = 0; 738 739 /* Place a NULL header at the beginning of the transmit area */ 740 ea_writebuf(sc, NULL, 0x0000, 0); 741 742 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 743 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 744 745 sc->sc_command |= SEEQ_CMD_TX_INTEN; 746 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 747 748 /* Turn on Rx */ 749 sc->sc_command |= SEEQ_CMD_RX_INTEN; 750 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 751 sc->sc_command | SEEQ_CMD_RX_ON); 752 753 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 754 755 756 /* Set flags appropriately. */ 757 ifp->if_flags |= IFF_RUNNING; 758 ifp->if_flags &= ~IFF_OACTIVE; 759 sc->sc_enabled = 1; 760 761 /* And start output. */ 762 ea_start(ifp); 763 764 splx(s); 765 return 0; 766 } 767 768 /* 769 * Start output on interface. Get datagrams from the queue and output them, 770 * giving the receiver a chance between datagrams. Call only from splnet or 771 * interrupt level! 772 */ 773 774 static void 775 ea_start(struct ifnet *ifp) 776 { 777 struct seeq8005_softc *sc = ifp->if_softc; 778 int s; 779 780 s = splnet(); 781 #ifdef SEEQ_TX_DEBUG 782 dprintf(("ea_start()...\n")); 783 #endif 784 785 /* Don't do anything if output is active. */ 786 787 if (ifp->if_flags & IFF_OACTIVE) 788 return; 789 790 /* Mark interface as output active */ 791 792 ifp->if_flags |= IFF_OACTIVE; 793 794 /* tx packets */ 795 796 eatxpacket(sc); 797 splx(s); 798 } 799 800 801 /* 802 * Transfer a packet to the interface buffer and start transmission 803 * 804 * Called at splnet() 805 */ 806 807 void 808 eatxpacket(struct seeq8005_softc *sc) 809 { 810 bus_space_tag_t iot = sc->sc_iot; 811 bus_space_handle_t ioh = sc->sc_ioh; 812 struct mbuf *m0; 813 struct ifnet *ifp; 814 815 ifp = &sc->sc_ethercom.ec_if; 816 817 /* Dequeue the next packet. */ 818 IFQ_DEQUEUE(&ifp->if_snd, m0); 819 820 /* If there's nothing to send, return. */ 821 if (!m0) { 822 ifp->if_flags &= ~IFF_OACTIVE; 823 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 824 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 825 #ifdef SEEQ_TX_DEBUG 826 dprintf(("tx finished\n")); 827 #endif 828 return; 829 } 830 831 #if NBPFILTER > 0 832 /* Give the packet to the bpf, if any. */ 833 if (ifp->if_bpf) 834 bpf_mtap(ifp->if_bpf, m0); 835 #endif 836 837 #ifdef SEEQ_TX_DEBUG 838 dprintf(("Tx new packet\n")); 839 #endif 840 841 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 842 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 843 844 ea_writembuf(sc, m0, 0x0000); 845 m_freem(m0); 846 847 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 848 849 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS)));*/ 850 851 #ifdef SEEQ_PACKET_DEBUG 852 ea_dump_buffer(sc, 0); 853 #endif 854 855 856 /* Now transmit the datagram. */ 857 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS)));*/ 858 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 859 sc->sc_command | SEEQ_CMD_TX_ON); 860 #ifdef SEEQ_TX_DEBUG 861 dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS))); 862 dprintf(("tx: queued\n")); 863 #endif 864 } 865 866 /* 867 * Copy a packet from an mbuf to the transmit buffer on the card. 868 * 869 * Puts a valid Tx header at the start of the packet, and a null header at 870 * the end. 871 */ 872 static int 873 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 874 { 875 struct mbuf *m; 876 int len, nextpacket; 877 u_int8_t hdr[4]; 878 879 /* 880 * Copy the datagram to the packet buffer. 881 */ 882 ea_writebuf(sc, NULL, bufstart + 4, 0); 883 884 len = 0; 885 for (m = m0; m; m = m->m_next) { 886 if (m->m_len == 0) 887 continue; 888 ea_writebuf(sc, mtod(m, caddr_t), -1, m->m_len); 889 len += m->m_len; 890 } 891 892 /* If packet size is odd round up to the next 16 bit boundry */ 893 if (len % 2) 894 ++len; 895 896 len = max(len, ETHER_MIN_LEN); 897 898 ea_writebuf(sc, NULL, bufstart + 4 + len, 0); 899 /* Follow it with a NULL packet header */ 900 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 901 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 902 903 /* Ok we now have a packet len bytes long in our packet buffer */ 904 DPRINTF(SEEQ_DEBUG_TX, ("seeq_writembuf: length=%d\n", len)); 905 906 /* Write the packet header */ 907 nextpacket = len + 4; 908 hdr[0] = (nextpacket >> 8) & 0xff; 909 hdr[1] = nextpacket & 0xff; 910 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 911 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 912 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 913 ea_writebuf(sc, hdr, 0x0000, 4); 914 915 return len; 916 } 917 918 /* 919 * Ethernet controller interrupt. 920 */ 921 922 int 923 seeq8005intr(void *arg) 924 { 925 struct seeq8005_softc *sc = arg; 926 bus_space_tag_t iot = sc->sc_iot; 927 bus_space_handle_t ioh = sc->sc_ioh; 928 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 929 int status, handled; 930 u_int8_t txhdr[4]; 931 u_int txstatus; 932 933 handled = 0; 934 dprintf(("eaintr: ")); 935 936 937 /* Get the controller status */ 938 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 939 dprintf(("st=%04x ", status)); 940 941 942 /* Tx interrupt ? */ 943 if (status & SEEQ_STATUS_TX_INT) { 944 dprintf(("txint ")); 945 handled = 1; 946 947 /* Acknowledge the interrupt */ 948 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 949 sc->sc_command | SEEQ_CMD_TX_INTACK); 950 951 ea_readbuf(sc, txhdr, 0x0000, 4); 952 953 #ifdef SEEQ_TX_DEBUG 954 dprintf(("txstatus=%02x %02x %02x %02x\n", 955 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 956 #endif 957 txstatus = txhdr[3]; 958 959 /* 960 * If SEEQ_TXSTAT_COLLISION is set then we received at least 961 * one collision. On the 8004 we can find out exactly how many 962 * collisions occurred. 963 * 964 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 965 * completed. 966 * 967 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 968 * occurred and the packet transmission was aborted. 969 * This situation is untested as present. 970 * 971 * The SEEQ_TXSTAT_BABBLE should never be set and is untested 972 * as we should never xmit oversized packets. 973 */ 974 if (txstatus & SEEQ_TXSTAT_COLLISION) { 975 switch (sc->sc_variant) { 976 case SEEQ_8004: { 977 int colls; 978 979 /* 980 * The 8004 contains a 4 bit collision count 981 * in the status register. 982 */ 983 984 /* This appears to be broken on 80C04.AE */ 985 /* ifp->if_collisions += 986 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 987 & SEEQ_TXSTAT_COLLISION_MASK;*/ 988 989 /* Use the TX Collision register */ 990 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 991 colls = bus_space_read_1(iot, ioh, 992 SEEQ_BUFWIN); 993 ifp->if_collisions += colls; 994 break; 995 } 996 case SEEQ_8005: 997 /* We known there was at least 1 collision */ 998 ifp->if_collisions++; 999 break; 1000 } 1001 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1002 printf("seeq_intr: col16 %x\n", txstatus); 1003 ifp->if_collisions += 16; 1004 ifp->if_oerrors++; 1005 } else if (txstatus & SEEQ_TXSTAT_BABBLE) { 1006 ifp->if_oerrors++; 1007 } 1008 1009 /* Have we completed transmission on the packet ? */ 1010 if (txstatus & SEEQ_PKTSTAT_DONE) { 1011 /* Clear watchdog timer. */ 1012 ifp->if_timer = 0; 1013 ifp->if_flags &= ~IFF_OACTIVE; 1014 1015 /* Update stats */ 1016 ifp->if_opackets++; 1017 1018 /* Tx next packet */ 1019 1020 eatxpacket(sc); 1021 } 1022 1023 } 1024 1025 1026 /* Rx interrupt ? */ 1027 if (status & SEEQ_STATUS_RX_INT) { 1028 dprintf(("rxint ")); 1029 handled = 1; 1030 1031 /* Acknowledge the interrupt */ 1032 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1033 sc->sc_command | SEEQ_CMD_RX_INTACK); 1034 1035 /* Processes the received packets */ 1036 ea_getpackets(sc); 1037 1038 1039 #if 0 1040 /* Make sure the receiver is on */ 1041 if ((status & SEEQ_STATUS_RX_ON) == 0) { 1042 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1043 sc->sc_command | SEEQ_CMD_RX_ON); 1044 printf("rxintr: rx is off st=%04x\n",status); 1045 } 1046 #endif 1047 } 1048 1049 #ifdef SEEQ_DEBUG 1050 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 1051 dprintf(("st=%04x\n", status)); 1052 #endif 1053 1054 return handled; 1055 } 1056 1057 1058 void 1059 ea_getpackets(struct seeq8005_softc *sc) 1060 { 1061 bus_space_tag_t iot = sc->sc_iot; 1062 bus_space_handle_t ioh = sc->sc_ioh; 1063 u_int addr; 1064 int len; 1065 int ctrl; 1066 int ptr; 1067 int pack; 1068 int status; 1069 u_int8_t rxhdr[4]; 1070 struct ifnet *ifp; 1071 1072 ifp = &sc->sc_ethercom.ec_if; 1073 1074 1075 /* We start from the last rx pointer position */ 1076 addr = sc->sc_rx_ptr; 1077 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1078 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1079 1080 do { 1081 /* Read rx header */ 1082 ea_readbuf(sc, rxhdr, addr, 4); 1083 1084 /* Split the packet header */ 1085 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1086 ctrl = rxhdr[2]; 1087 status = rxhdr[3]; 1088 1089 #ifdef SEEQ_RX_DEBUG 1090 dprintf(("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1091 addr, ptr, ctrl, status)); 1092 #endif 1093 1094 1095 /* Zero packet ptr ? then must be null header so exit */ 1096 if (ptr == 0) break; 1097 1098 1099 /* Get packet length */ 1100 len = (ptr - addr) - 4; 1101 1102 if (len < 0) 1103 len += sc->sc_rx_bufsize; 1104 1105 #ifdef SEEQ_RX_DEBUG 1106 dprintf(("len=%04x\n", len)); 1107 #endif 1108 1109 1110 /* Has the packet rx completed ? if not then exit */ 1111 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1112 break; 1113 1114 /* 1115 * Did we have any errors? then note error and go to 1116 * next packet 1117 */ 1118 if (__predict_false(status & SEEQ_RXSTAT_ERROR_MASK)) { 1119 ++ifp->if_ierrors; 1120 log(LOG_WARNING, 1121 "%s: rx packet error (%02x) - dropping packet\n", 1122 sc->sc_dev.dv_xname, status & 0x0f); 1123 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1124 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, 1125 sc->sc_config2); 1126 ea_init(ifp); 1127 return; 1128 } 1129 1130 /* 1131 * Is the packet too big ? - this will probably be trapped 1132 * above as a receive error 1133 */ 1134 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1135 ++ifp->if_ierrors; 1136 log(LOG_WARNING, "%s: rx packet size error len=%d\n", 1137 sc->sc_dev.dv_xname, len); 1138 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1139 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, 1140 sc->sc_config2); 1141 ea_init(ifp); 1142 return; 1143 } 1144 1145 ifp->if_ipackets++; 1146 /* Pass data up to upper levels. */ 1147 ea_read(sc, addr + 4, len); 1148 1149 addr = ptr; 1150 ++pack; 1151 } while (len != 0); 1152 1153 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1154 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1155 1156 #ifdef SEEQ_RX_DEBUG 1157 dprintf(("new rx ptr=%04x\n", addr)); 1158 #endif 1159 1160 1161 /* Store new rx pointer */ 1162 sc->sc_rx_ptr = addr; 1163 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1164 1165 /* Make sure the receiver is on */ 1166 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1167 sc->sc_command | SEEQ_CMD_RX_ON); 1168 1169 } 1170 1171 1172 /* 1173 * Pass a packet up to the higher levels. 1174 */ 1175 1176 static void 1177 ea_read(struct seeq8005_softc *sc, int addr, int len) 1178 { 1179 struct mbuf *m; 1180 struct ifnet *ifp; 1181 1182 ifp = &sc->sc_ethercom.ec_if; 1183 1184 /* Pull packet off interface. */ 1185 m = ea_get(sc, addr, len, ifp); 1186 if (m == 0) 1187 return; 1188 1189 #ifdef SEEQ_RX_DEBUG 1190 dprintf(("%s-->", ether_sprintf(eh->ether_shost))); 1191 dprintf(("%s\n", ether_sprintf(eh->ether_dhost))); 1192 #endif 1193 1194 #if NBPFILTER > 0 1195 /* 1196 * Check if there's a BPF listener on this interface. 1197 * If so, hand off the raw packet to bpf. 1198 */ 1199 if (ifp->if_bpf) 1200 bpf_mtap(ifp->if_bpf, m); 1201 #endif 1202 1203 (*ifp->if_input)(ifp, m); 1204 } 1205 1206 /* 1207 * Pull read data off a interface. Len is length of data, with local net 1208 * header stripped. We copy the data into mbufs. When full cluster sized 1209 * units are present we copy into clusters. 1210 */ 1211 1212 struct mbuf * 1213 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1214 { 1215 struct mbuf *top, **mp, *m; 1216 int len; 1217 u_int cp, epkt; 1218 1219 cp = addr; 1220 epkt = cp + totlen; 1221 1222 MGETHDR(m, M_DONTWAIT, MT_DATA); 1223 if (m == 0) 1224 return 0; 1225 m->m_pkthdr.rcvif = ifp; 1226 m->m_pkthdr.len = totlen; 1227 m->m_len = MHLEN; 1228 top = 0; 1229 mp = ⊤ 1230 1231 while (totlen > 0) { 1232 if (top) { 1233 MGET(m, M_DONTWAIT, MT_DATA); 1234 if (m == 0) { 1235 m_freem(top); 1236 return 0; 1237 } 1238 m->m_len = MLEN; 1239 } 1240 len = min(totlen, epkt - cp); 1241 if (len >= MINCLSIZE) { 1242 MCLGET(m, M_DONTWAIT); 1243 if (m->m_flags & M_EXT) 1244 m->m_len = len = min(len, MCLBYTES); 1245 else 1246 len = m->m_len; 1247 } else { 1248 /* 1249 * Place initial small packet/header at end of mbuf. 1250 */ 1251 if (len < m->m_len) { 1252 if (top == 0 && len + max_linkhdr <= m->m_len) 1253 m->m_data += max_linkhdr; 1254 m->m_len = len; 1255 } else 1256 len = m->m_len; 1257 } 1258 if (top == 0) { 1259 /* Make sure the payload is aligned */ 1260 caddr_t newdata = (caddr_t) 1261 ALIGN(m->m_data + sizeof(struct ether_header)) - 1262 sizeof(struct ether_header); 1263 len -= newdata - m->m_data; 1264 m->m_len = len; 1265 m->m_data = newdata; 1266 } 1267 ea_readbuf(sc, mtod(m, u_char *), 1268 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1269 len); 1270 cp += len; 1271 *mp = m; 1272 mp = &m->m_next; 1273 totlen -= len; 1274 if (cp == epkt) 1275 cp = addr; 1276 } 1277 1278 return top; 1279 } 1280 1281 /* 1282 * Process an ioctl request. Mostly boilerplate. 1283 */ 1284 static int 1285 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1286 { 1287 struct seeq8005_softc *sc = ifp->if_softc; 1288 int s, error = 0; 1289 1290 s = splnet(); 1291 switch (cmd) { 1292 1293 default: 1294 error = ether_ioctl(ifp, cmd, data); 1295 if (error == ENETRESET) { 1296 /* 1297 * Multicast list has changed; set the hardware filter 1298 * accordingly. 1299 */ 1300 ea_mc_reset(sc); 1301 error = 0; 1302 } 1303 break; 1304 } 1305 1306 splx(s); 1307 return error; 1308 } 1309 1310 /* Must be called at splnet() */ 1311 1312 static void 1313 ea_mc_reset(struct seeq8005_softc *sc) 1314 { 1315 1316 switch (sc->sc_variant) { 1317 case SEEQ_8004: 1318 ea_mc_reset_8004(sc); 1319 return; 1320 case SEEQ_8005: 1321 ea_mc_reset_8005(sc); 1322 return; 1323 } 1324 } 1325 1326 static void 1327 ea_mc_reset_8004(struct seeq8005_softc *sc) 1328 { 1329 struct ethercom *ec = &sc->sc_ethercom; 1330 struct ifnet *ifp = &ec->ec_if; 1331 struct ether_multi *enm; 1332 u_int8_t *cp, c; 1333 u_int32_t crc; 1334 int i, len; 1335 struct ether_multistep step; 1336 u_int8_t af[8]; 1337 1338 /* 1339 * Set up multicast address filter by passing all multicast addresses 1340 * through a crc generator, and then using bits 2 - 7 as an index 1341 * into the 64 bit logical address filter. The high order bits 1342 * selects the word, while the rest of the bits select the bit within 1343 * the word. 1344 */ 1345 1346 if (ifp->if_flags & IFF_PROMISC) { 1347 ifp->if_flags |= IFF_ALLMULTI; 1348 for (i = 0; i < 8; i++) 1349 af[i] = 0xff; 1350 return; 1351 } 1352 for (i = 0; i < 8; i++) 1353 af[i] = 0; 1354 ETHER_FIRST_MULTI(step, ec, enm); 1355 while (enm != NULL) { 1356 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1357 sizeof(enm->enm_addrlo)) != 0) { 1358 /* 1359 * We must listen to a range of multicast addresses. 1360 * For now, just accept all multicasts, rather than 1361 * trying to set only those filter bits needed to match 1362 * the range. (At this time, the only use of address 1363 * ranges is for IP multicast routing, for which the 1364 * range is big enough to require all bits set.) 1365 */ 1366 ifp->if_flags |= IFF_ALLMULTI; 1367 for (i = 0; i < 8; i++) 1368 af[i] = 0xff; 1369 break; 1370 } 1371 cp = enm->enm_addrlo; 1372 crc = 0xffffffff; 1373 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1374 c = *cp++; 1375 for (i = 8; --i >= 0;) { 1376 if (((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01)) { 1377 crc <<= 1; 1378 crc ^= 0x04c11db6 | 1; 1379 } else 1380 crc <<= 1; 1381 c >>= 1; 1382 } 1383 } 1384 /* Just want the 6 most significant bits. */ 1385 crc = (crc >> 2) & 0x3f; 1386 1387 /* Turn on the corresponding bit in the filter. */ 1388 af[crc >> 3] |= 1 << (crc & 0x7); 1389 1390 ETHER_NEXT_MULTI(step, enm); 1391 } 1392 ifp->if_flags &= ~IFF_ALLMULTI; 1393 1394 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1395 for (i = 0; i < 8; ++i) 1396 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1397 SEEQ_BUFWIN, af[i]); 1398 } 1399 1400 static void 1401 ea_mc_reset_8005(struct seeq8005_softc *sc) 1402 { 1403 struct ether_multi *enm; 1404 struct ether_multistep step; 1405 int naddr, maxaddrs; 1406 1407 naddr = 0; 1408 maxaddrs = 5; 1409 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1410 while (enm != NULL) { 1411 /* Have we got space? */ 1412 if (naddr >= maxaddrs || 1413 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1414 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1415 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1416 return; 1417 } 1418 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1419 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1420 naddr++; 1421 ETHER_NEXT_MULTI(step, enm); 1422 } 1423 for (; naddr < maxaddrs; naddr++) 1424 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1425 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1426 sc->sc_config1); 1427 } 1428 1429 /* 1430 * Device timeout routine. 1431 * 1432 * Ok I am not sure exactly how the device timeout should work.... 1433 * Currently what will happens is that that the device timeout is only 1434 * set when a packet it received. This indicates we are on an active 1435 * network and thus we should expect more packets. If non arrive in 1436 * in the timeout period then we reinitialise as we may have jammed. 1437 * We zero the timeout at this point so that we don't end up with 1438 * an endless stream of timeouts if the network goes down. 1439 */ 1440 1441 static void 1442 ea_watchdog(struct ifnet *ifp) 1443 { 1444 struct seeq8005_softc *sc = ifp->if_softc; 1445 1446 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1447 ifp->if_oerrors++; 1448 dprintf(("ea_watchdog: ")); 1449 dprintf(("st=%04x\n", 1450 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_STATUS))); 1451 1452 /* Kick the interface */ 1453 1454 ea_init(ifp); 1455 1456 /* ifp->if_timer = SEEQ_TIMEOUT;*/ 1457 ifp->if_timer = 0; 1458 } 1459 1460 /* End of if_ea.c */ 1461
Indexes created Tue Sep 30 07:10:03 GMT 2025