seeq8005.c revision 1.14
1 /* $NetBSD: seeq8005.c,v 1.14 2001/03/27 18:03:04 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chip: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 */ 43 /* 44 * More information on the 8004 and 8005 AEDLC controllers can be found in 45 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 46 * 47 * This data book may no longer be available as these are rather old chips 48 * (1991 - 1993) 49 */ 50 /* 51 * This driver is based on the arm32 ea(4) driver, hence the names of many 52 * of the functions. 53 */ 54 /* 55 * Bugs/possible improvements: 56 * - Does not currently support DMA 57 * - Does not transmit multiple packets in one go 58 * - Does not support 8-bit busses 59 */ 60 61 #include "opt_inet.h" 62 #include "opt_ns.h" 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 67 __RCSID("$NetBSD: seeq8005.c,v 1.14 2001/03/27 18:03:04 bjh21 Exp $"); 68 69 #include <sys/systm.h> 70 #include <sys/endian.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_types.h> 81 #include <net/if_ether.h> 82 #include <net/if_media.h> 83 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/in_systm.h> 87 #include <netinet/in_var.h> 88 #include <netinet/ip.h> 89 #include <netinet/if_inarp.h> 90 #endif 91 92 #ifdef NS 93 #include <netns/ns.h> 94 #include <netns/ns_if.h> 95 #endif 96 97 #include "bpfilter.h" 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <machine/bus.h> 104 #include <machine/intr.h> 105 106 #include <dev/ic/seeq8005reg.h> 107 #include <dev/ic/seeq8005var.h> 108 109 /*#define SEEQ_DEBUG*/ 110 111 /* for debugging convenience */ 112 #ifdef SEEQ_DEBUG 113 #define SEEQ_DEBUG_MISC 1 114 #define SEEQ_DEBUG_TX 2 115 #define SEEQ_DEBUG_RX 4 116 #define SEEQ_DEBUG_PKT 8 117 #define SEEQ_DEBUG_TXINT 16 118 #define SEEQ_DEBUG_RXINT 32 119 int seeq_debug = 0; 120 #define DPRINTF(f, x) { if (seeq_debug & (f)) printf x; } 121 #else 122 #define DPRINTF(f, x) 123 #endif 124 #define dprintf(x) DPRINTF(SEEQ_DEBUG_MISC, x) 125 126 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> MAX_ETHER_LEN) */ 127 128 /* 129 * prototypes 130 */ 131 132 static int ea_init(struct ifnet *); 133 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 134 static void ea_start(struct ifnet *); 135 static void ea_watchdog(struct ifnet *); 136 static void ea_chipreset(struct seeq8005_softc *); 137 static void ea_ramtest(struct seeq8005_softc *); 138 static int ea_stoptx(struct seeq8005_softc *); 139 static int ea_stoprx(struct seeq8005_softc *); 140 static void ea_stop(struct ifnet *, int); 141 static void ea_await_fifo_empty(struct seeq8005_softc *); 142 static void ea_await_fifo_full(struct seeq8005_softc *); 143 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 145 static void ea_select_buffer(struct seeq8005_softc *, int); 146 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 147 static void ea_read(struct seeq8005_softc *, int, int); 148 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 149 static void ea_getpackets(struct seeq8005_softc *); 150 static void eatxpacket(struct seeq8005_softc *); 151 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 152 static void ea_mc_reset(struct seeq8005_softc *); 153 static void ea_mc_reset_8004(struct seeq8005_softc *); 154 static void ea_mc_reset_8005(struct seeq8005_softc *); 155 static int ea_mediachange(struct ifnet *); 156 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 157 158 159 /* 160 * Attach chip. 161 */ 162 163 void 164 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 165 int nmedia, int defmedia) 166 { 167 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 168 u_int id; 169 170 KASSERT(myaddr != NULL); 171 printf(" address %s", ether_sprintf(myaddr)); 172 173 /* Stop the board. */ 174 175 ea_chipreset(sc); 176 177 /* Get the product ID */ 178 179 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 180 id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 181 182 switch (id & SEEQ_PRODUCTID_MASK) { 183 case SEEQ_PRODUCTID_8004: 184 sc->sc_variant = SEEQ_8004; 185 break; 186 default: /* XXX */ 187 sc->sc_variant = SEEQ_8005; 188 break; 189 } 190 191 switch (sc->sc_variant) { 192 case SEEQ_8004: 193 printf(", SEEQ80C04 rev %x\n", 194 id & SEEQ_PRODUCTID_REV_MASK); 195 break; 196 case SEEQ_8005: 197 if (id != 0xff) 198 printf(", SEEQ8005 rev %x\n", id); 199 else 200 printf(", SEEQ8005\n"); 201 break; 202 default: 203 printf(", Unknown ethernet controller\n"); 204 return; 205 } 206 207 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 208 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 209 210 /* 211 * Set up tx and rx buffers. 212 * 213 * We use approximately a quarter of the packet memory for TX 214 * buffers and the rest for RX buffers 215 */ 216 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 217 sc->sc_tx_bufs = 1; 218 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 219 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 220 sc->sc_enabled = 0; 221 222 /* Test the RAM */ 223 ea_ramtest(sc); 224 225 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 226 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 227 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 228 229 /* Initialise ifnet structure. */ 230 231 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 232 ifp->if_softc = sc; 233 ifp->if_start = ea_start; 234 ifp->if_ioctl = ea_ioctl; 235 ifp->if_init = ea_init; 236 ifp->if_stop = ea_stop; 237 ifp->if_watchdog = ea_watchdog; 238 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 239 if (sc->sc_variant == SEEQ_8004) 240 ifp->if_flags |= IFF_SIMPLEX; 241 IFQ_SET_READY(&ifp->if_snd); 242 243 /* Initialize media goo. */ 244 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 245 if (media != NULL) { 246 int i; 247 248 for (i = 0; i < nmedia; i++) 249 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 250 ifmedia_set(&sc->sc_media, defmedia); 251 } else { 252 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 253 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 254 } 255 256 /* Now we can attach the interface. */ 257 258 if_attach(ifp); 259 ether_ifattach(ifp, myaddr); 260 261 printf("\n"); 262 } 263 264 /* 265 * Media change callback. 266 */ 267 static int 268 ea_mediachange(struct ifnet *ifp) 269 { 270 struct seeq8005_softc *sc = ifp->if_softc; 271 272 if (sc->sc_mediachange) 273 return ((*sc->sc_mediachange)(sc)); 274 return (EINVAL); 275 } 276 277 /* 278 * Media status callback. 279 */ 280 static void 281 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 282 { 283 struct seeq8005_softc *sc = ifp->if_softc; 284 285 if (sc->sc_enabled == 0) { 286 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 287 ifmr->ifm_status = 0; 288 return; 289 } 290 291 if (sc->sc_mediastatus) 292 (*sc->sc_mediastatus)(sc, ifmr); 293 } 294 295 /* 296 * Test the RAM on the ethernet card. 297 */ 298 299 void 300 ea_ramtest(struct seeq8005_softc *sc) 301 { 302 bus_space_tag_t iot = sc->sc_iot; 303 bus_space_handle_t ioh = sc->sc_ioh; 304 int loop; 305 u_int sum = 0; 306 307 /* dprintf(("ea_ramtest()\n"));*/ 308 309 /* 310 * Test the buffer memory on the board. 311 * Write simple pattens to it and read them back. 312 */ 313 314 /* Set up the whole buffer RAM for writing */ 315 316 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 317 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 318 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 319 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 320 321 #define SEEQ_RAMTEST_LOOP(value) \ 322 do { \ 323 /* Set the write start address and write a pattern */ \ 324 ea_writebuf(sc, NULL, 0x0000, 0); \ 325 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 326 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (value)); \ 327 \ 328 /* Set the read start address and verify the pattern */ \ 329 ea_readbuf(sc, NULL, 0x0000, 0); \ 330 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 331 if (bus_space_read_2(iot, ioh, SEEQ_BUFWIN) != (value)) \ 332 ++sum; \ 333 if (sum != 0) \ 334 dprintf(("sum=%d\n", sum)); \ 335 } while (/*CONSTCOND*/0) 336 337 SEEQ_RAMTEST_LOOP(loop); 338 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 339 SEEQ_RAMTEST_LOOP(0xaa55); 340 SEEQ_RAMTEST_LOOP(0x55aa); 341 342 /* Report */ 343 344 if (sum > 0) 345 printf("%s: buffer RAM failed self test, %d faults\n", 346 sc->sc_dev.dv_xname, sum); 347 } 348 349 350 /* 351 * Stop the tx interface. 352 * 353 * Returns 0 if the tx was already stopped or 1 if it was active 354 */ 355 356 static int 357 ea_stoptx(struct seeq8005_softc *sc) 358 { 359 bus_space_tag_t iot = sc->sc_iot; 360 bus_space_handle_t ioh = sc->sc_ioh; 361 int timeout; 362 int status; 363 364 DPRINTF(SEEQ_DEBUG_TX, ("seeq_stoptx()\n")); 365 366 sc->sc_enabled = 0; 367 368 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 369 if (!(status & SEEQ_STATUS_TX_ON)) 370 return 0; 371 372 /* Stop any tx and wait for confirmation */ 373 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 374 sc->sc_command | SEEQ_CMD_TX_OFF); 375 376 timeout = 20000; 377 do { 378 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 379 delay(1); 380 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 381 if (timeout == 0) 382 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 383 sc->sc_dev.dv_xname); 384 385 /* Clear any pending tx interrupt */ 386 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 387 sc->sc_command | SEEQ_CMD_TX_INTACK); 388 return 1; 389 } 390 391 392 /* 393 * Stop the rx interface. 394 * 395 * Returns 0 if the tx was already stopped or 1 if it was active 396 */ 397 398 static int 399 ea_stoprx(struct seeq8005_softc *sc) 400 { 401 bus_space_tag_t iot = sc->sc_iot; 402 bus_space_handle_t ioh = sc->sc_ioh; 403 int timeout; 404 int status; 405 406 DPRINTF(SEEQ_DEBUG_RX, ("seeq_stoprx()\n")); 407 408 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 409 if (!(status & SEEQ_STATUS_RX_ON)) 410 return 0; 411 412 /* Stop any rx and wait for confirmation */ 413 414 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 415 sc->sc_command | SEEQ_CMD_RX_OFF); 416 417 timeout = 20000; 418 do { 419 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 420 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 421 if (timeout == 0) 422 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 423 sc->sc_dev.dv_xname); 424 425 /* Clear any pending rx interrupt */ 426 427 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 428 sc->sc_command | SEEQ_CMD_RX_INTACK); 429 return 1; 430 } 431 432 433 /* 434 * Stop interface. 435 * Stop all IO and shut the interface down 436 */ 437 438 static void 439 ea_stop(struct ifnet *ifp, int disable) 440 { 441 struct seeq8005_softc *sc = ifp->if_softc; 442 bus_space_tag_t iot = sc->sc_iot; 443 bus_space_handle_t ioh = sc->sc_ioh; 444 445 DPRINTF(SEEQ_DEBUG_MISC, ("seeq_stop()\n")); 446 447 /* Stop all IO */ 448 ea_stoptx(sc); 449 ea_stoprx(sc); 450 451 /* Disable rx and tx interrupts */ 452 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 453 454 /* Clear any pending interrupts */ 455 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 456 sc->sc_command | SEEQ_CMD_RX_INTACK | 457 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 458 SEEQ_CMD_BW_INTACK); 459 460 if (sc->sc_variant == SEEQ_8004) { 461 /* Put the chip to sleep */ 462 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 463 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 464 sc->sc_config3 | SEEQ_CFG3_SLEEP); 465 } 466 467 /* Cancel any watchdog timer */ 468 sc->sc_ethercom.ec_if.if_timer = 0; 469 } 470 471 472 /* 473 * Reset the chip 474 * Following this the software registers are reset 475 */ 476 477 static void 478 ea_chipreset(struct seeq8005_softc *sc) 479 { 480 bus_space_tag_t iot = sc->sc_iot; 481 bus_space_handle_t ioh = sc->sc_ioh; 482 483 DPRINTF(SEEQ_DEBUG_MISC, ("seeq_chipreset()\n")); 484 485 /* Reset the controller. Min of 4us delay here */ 486 487 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 488 delay(4); 489 490 sc->sc_command = 0; 491 sc->sc_config1 = 0; 492 sc->sc_config2 = 0; 493 sc->sc_config3 = 0; 494 } 495 496 497 /* 498 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 499 * switching the FIFO from write to read. We also use it when changing 500 * the address for writes. 501 */ 502 static void 503 ea_await_fifo_empty(struct seeq8005_softc *sc) 504 { 505 bus_space_tag_t iot = sc->sc_iot; 506 bus_space_handle_t ioh = sc->sc_ioh; 507 int timeout; 508 509 timeout = 20000; 510 if ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 511 SEEQ_STATUS_FIFO_DIR) != 0) 512 return; /* FIFO is reading anyway. */ 513 while ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 514 SEEQ_STATUS_FIFO_EMPTY) == 0 && 515 --timeout > 0) 516 continue; 517 } 518 519 /* 520 * Wait for the DMA FIFO to fill before reading from it. 521 */ 522 static void 523 ea_await_fifo_full(struct seeq8005_softc *sc) 524 { 525 bus_space_tag_t iot = sc->sc_iot; 526 bus_space_handle_t ioh = sc->sc_ioh; 527 int timeout; 528 529 timeout = 20000; 530 while ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 531 SEEQ_STATUS_FIFO_FULL) == 0 && 532 --timeout > 0) 533 continue; 534 } 535 536 /* 537 * write to the buffer memory on the interface 538 * 539 * The buffer address is set to ADDR. 540 * If len != 0 then data is copied from the address starting at buf 541 * to the interface buffer. 542 * BUF must be usable as a u_int16_t *. 543 * If LEN is odd, it must be safe to overwrite one extra byte. 544 */ 545 546 static void 547 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 548 { 549 bus_space_tag_t iot = sc->sc_iot; 550 bus_space_handle_t ioh = sc->sc_ioh; 551 552 dprintf(("writebuf: st=%04x\n", 553 bus_space_read_2(iot, ioh, SEEQ_STATUS))); 554 555 #ifdef DIAGNOSTIC 556 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 557 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 558 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 559 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 560 #endif 561 562 /* Assume that copying too much is safe. */ 563 if (len % 2 != 0) 564 len++; 565 566 if (addr != -1) { 567 ea_await_fifo_empty(sc); 568 569 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 570 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 571 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 572 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 573 } 574 575 if (len > 0) 576 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 577 (u_int16_t *)buf, len / 2); 578 /* Leave FIFO to empty in the background */ 579 } 580 581 582 /* 583 * read from the buffer memory on the interface 584 * 585 * The buffer address is set to ADDR. 586 * If len != 0 then data is copied from the interface buffer to the 587 * address starting at buf. 588 * BUF must be usable as a u_int16_t *. 589 * If LEN is odd, it must be safe to overwrite one extra byte. 590 */ 591 592 static void 593 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 594 { 595 596 bus_space_tag_t iot = sc->sc_iot; 597 bus_space_handle_t ioh = sc->sc_ioh; 598 599 dprintf(("readbuf: st=%04x addr=%04x len=%d\n", 600 bus_space_read_2(iot, ioh, SEEQ_STATUS), addr, len)); 601 602 #ifdef DIAGNOSTIC 603 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 604 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 605 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 606 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 607 #endif 608 609 /* Assume that copying too much is safe. */ 610 if (len % 2 != 0) 611 len++; 612 613 if (addr != -1) { 614 ea_await_fifo_empty(sc); 615 616 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 617 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 618 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 619 sc->sc_command | SEEQ_CMD_FIFO_READ); 620 621 ea_await_fifo_full(sc); 622 } 623 624 if (len > 0) 625 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 626 (u_int16_t *)buf, len / 2); 627 } 628 629 static void 630 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 631 { 632 633 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 634 sc->sc_config1 | bufcode); 635 } 636 637 /* Must be called at splnet */ 638 static void 639 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 640 { 641 int i; 642 643 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 644 for (i = 0; i < ETHER_ADDR_LEN; ++i) 645 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 646 ea[i]); 647 } 648 649 /* 650 * Initialize interface. 651 * 652 * This should leave the interface in a state for packet reception and 653 * transmission. 654 */ 655 656 static int 657 ea_init(struct ifnet *ifp) 658 { 659 struct seeq8005_softc *sc = ifp->if_softc; 660 bus_space_tag_t iot = sc->sc_iot; 661 bus_space_handle_t ioh = sc->sc_ioh; 662 int s; 663 664 dprintf(("ea_init()\n")); 665 666 s = splnet(); 667 668 /* First, reset the board. */ 669 670 ea_chipreset(sc); 671 672 /* Set up defaults for the registers */ 673 674 sc->sc_command = 0; 675 sc->sc_config1 = 0; 676 #if BYTE_ORDER == BIG_ENDIAN 677 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 678 #else 679 sc->sc_config2 = 0; 680 #endif 681 sc->sc_config3 = 0; 682 683 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 684 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 685 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 686 if (sc->sc_variant == SEEQ_8004) { 687 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 688 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 689 } 690 691 /* Write the station address - the receiver must be off */ 692 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 693 694 /* Split board memory into Rx and Tx. */ 695 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 696 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 697 698 if (sc->sc_variant == SEEQ_8004) 699 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 700 701 /* Configure rx. */ 702 ea_mc_reset(sc); 703 if (ifp->if_flags & IFF_PROMISC) 704 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 705 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 706 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 707 else 708 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 709 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 710 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 711 712 /* Setup the Rx pointers */ 713 sc->sc_rx_ptr = sc->sc_tx_bufsize; 714 715 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 716 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 717 718 719 /* Place a NULL header at the beginning of the receive area */ 720 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 721 722 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 723 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 724 725 726 /* Configure TX. */ 727 dprintf(("Configuring tx...\n")); 728 729 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 730 731 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 732 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 733 734 /* Reset tx buffer pointers */ 735 sc->sc_tx_cur = 0; 736 sc->sc_tx_used = 0; 737 sc->sc_tx_next = 0; 738 739 /* Place a NULL header at the beginning of the transmit area */ 740 ea_writebuf(sc, NULL, 0x0000, 0); 741 742 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 743 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 744 745 sc->sc_command |= SEEQ_CMD_TX_INTEN; 746 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 747 748 /* Turn on Rx */ 749 sc->sc_command |= SEEQ_CMD_RX_INTEN; 750 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 751 sc->sc_command | SEEQ_CMD_RX_ON); 752 753 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 754 755 756 /* Set flags appropriately. */ 757 ifp->if_flags |= IFF_RUNNING; 758 ifp->if_flags &= ~IFF_OACTIVE; 759 sc->sc_enabled = 1; 760 761 /* And start output. */ 762 ea_start(ifp); 763 764 splx(s); 765 return 0; 766 } 767 768 /* 769 * Start output on interface. Get datagrams from the queue and output them, 770 * giving the receiver a chance between datagrams. Call only from splnet or 771 * interrupt level! 772 */ 773 774 static void 775 ea_start(struct ifnet *ifp) 776 { 777 struct seeq8005_softc *sc = ifp->if_softc; 778 int s; 779 780 s = splnet(); 781 #ifdef SEEQ_TX_DEBUG 782 dprintf(("ea_start()...\n")); 783 #endif 784 785 /* 786 * Don't do anything if output is active. seeq8005intr() will call 787 * us (actually eatxpacket()) back when the card's ready for more 788 * frames. 789 */ 790 if (ifp->if_flags & IFF_OACTIVE) 791 return; 792 793 /* Mark interface as output active */ 794 795 ifp->if_flags |= IFF_OACTIVE; 796 797 /* tx packets */ 798 799 eatxpacket(sc); 800 splx(s); 801 } 802 803 804 /* 805 * Transfer a packet to the interface buffer and start transmission 806 * 807 * Called at splnet() 808 */ 809 810 void 811 eatxpacket(struct seeq8005_softc *sc) 812 { 813 bus_space_tag_t iot = sc->sc_iot; 814 bus_space_handle_t ioh = sc->sc_ioh; 815 struct mbuf *m0; 816 struct ifnet *ifp; 817 818 ifp = &sc->sc_ethercom.ec_if; 819 820 /* Dequeue the next packet. */ 821 IFQ_DEQUEUE(&ifp->if_snd, m0); 822 823 /* If there's nothing to send, return. */ 824 if (!m0) { 825 ifp->if_flags &= ~IFF_OACTIVE; 826 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 827 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 828 #ifdef SEEQ_TX_DEBUG 829 dprintf(("tx finished\n")); 830 #endif 831 return; 832 } 833 834 #if NBPFILTER > 0 835 /* Give the packet to the bpf, if any. */ 836 if (ifp->if_bpf) 837 bpf_mtap(ifp->if_bpf, m0); 838 #endif 839 840 #ifdef SEEQ_TX_DEBUG 841 dprintf(("Tx new packet\n")); 842 #endif 843 844 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 845 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 846 847 ea_writembuf(sc, m0, 0x0000); 848 m_freem(m0); 849 850 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 851 852 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS)));*/ 853 854 #ifdef SEEQ_PACKET_DEBUG 855 ea_dump_buffer(sc, 0); 856 #endif 857 858 859 /* Now transmit the datagram. */ 860 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS)));*/ 861 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 862 sc->sc_command | SEEQ_CMD_TX_ON); 863 #ifdef SEEQ_TX_DEBUG 864 dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS))); 865 dprintf(("tx: queued\n")); 866 #endif 867 } 868 869 /* 870 * Copy a packet from an mbuf to the transmit buffer on the card. 871 * 872 * Puts a valid Tx header at the start of the packet, and a null header at 873 * the end. 874 */ 875 static int 876 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 877 { 878 struct mbuf *m; 879 int len, nextpacket; 880 u_int8_t hdr[4]; 881 882 /* 883 * Copy the datagram to the packet buffer. 884 */ 885 ea_writebuf(sc, NULL, bufstart + 4, 0); 886 887 len = 0; 888 for (m = m0; m; m = m->m_next) { 889 if (m->m_len == 0) 890 continue; 891 ea_writebuf(sc, mtod(m, caddr_t), -1, m->m_len); 892 len += m->m_len; 893 } 894 895 /* If packet size is odd round up to the next 16 bit boundry */ 896 if (len % 2) 897 ++len; 898 899 len = max(len, ETHER_MIN_LEN); 900 901 ea_writebuf(sc, NULL, bufstart + 4 + len, 0); 902 /* Follow it with a NULL packet header */ 903 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 904 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 905 906 /* Ok we now have a packet len bytes long in our packet buffer */ 907 DPRINTF(SEEQ_DEBUG_TX, ("seeq_writembuf: length=%d\n", len)); 908 909 /* Write the packet header */ 910 nextpacket = len + 4; 911 hdr[0] = (nextpacket >> 8) & 0xff; 912 hdr[1] = nextpacket & 0xff; 913 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 914 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 915 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 916 ea_writebuf(sc, hdr, 0x0000, 4); 917 918 return len; 919 } 920 921 /* 922 * Ethernet controller interrupt. 923 */ 924 925 int 926 seeq8005intr(void *arg) 927 { 928 struct seeq8005_softc *sc = arg; 929 bus_space_tag_t iot = sc->sc_iot; 930 bus_space_handle_t ioh = sc->sc_ioh; 931 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 932 int status, handled; 933 u_int8_t txhdr[4]; 934 u_int txstatus; 935 936 handled = 0; 937 dprintf(("eaintr: ")); 938 939 940 /* Get the controller status */ 941 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 942 dprintf(("st=%04x ", status)); 943 944 945 /* Tx interrupt ? */ 946 if (status & SEEQ_STATUS_TX_INT) { 947 dprintf(("txint ")); 948 handled = 1; 949 950 /* Acknowledge the interrupt */ 951 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 952 sc->sc_command | SEEQ_CMD_TX_INTACK); 953 954 ea_readbuf(sc, txhdr, 0x0000, 4); 955 956 #ifdef SEEQ_TX_DEBUG 957 dprintf(("txstatus=%02x %02x %02x %02x\n", 958 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 959 #endif 960 txstatus = txhdr[3]; 961 962 /* 963 * If SEEQ_TXSTAT_COLLISION is set then we received at least 964 * one collision. On the 8004 we can find out exactly how many 965 * collisions occurred. 966 * 967 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 968 * completed. 969 * 970 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 971 * occurred and the packet transmission was aborted. 972 * This situation is untested as present. 973 * 974 * The SEEQ_TXSTAT_BABBLE should never be set and is untested 975 * as we should never xmit oversized packets. 976 */ 977 if (txstatus & SEEQ_TXSTAT_COLLISION) { 978 switch (sc->sc_variant) { 979 case SEEQ_8004: { 980 int colls; 981 982 /* 983 * The 8004 contains a 4 bit collision count 984 * in the status register. 985 */ 986 987 /* This appears to be broken on 80C04.AE */ 988 /* ifp->if_collisions += 989 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 990 & SEEQ_TXSTAT_COLLISION_MASK;*/ 991 992 /* Use the TX Collision register */ 993 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 994 colls = bus_space_read_1(iot, ioh, 995 SEEQ_BUFWIN); 996 ifp->if_collisions += colls; 997 break; 998 } 999 case SEEQ_8005: 1000 /* We known there was at least 1 collision */ 1001 ifp->if_collisions++; 1002 break; 1003 } 1004 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1005 printf("seeq_intr: col16 %x\n", txstatus); 1006 ifp->if_collisions += 16; 1007 ifp->if_oerrors++; 1008 } else if (txstatus & SEEQ_TXSTAT_BABBLE) { 1009 ifp->if_oerrors++; 1010 } 1011 1012 /* Have we completed transmission on the packet ? */ 1013 if (txstatus & SEEQ_PKTSTAT_DONE) { 1014 /* Clear watchdog timer. */ 1015 ifp->if_timer = 0; 1016 ifp->if_flags &= ~IFF_OACTIVE; 1017 1018 /* Update stats */ 1019 ifp->if_opackets++; 1020 1021 /* Tx next packet */ 1022 1023 eatxpacket(sc); 1024 } 1025 1026 } 1027 1028 1029 /* Rx interrupt ? */ 1030 if (status & SEEQ_STATUS_RX_INT) { 1031 dprintf(("rxint ")); 1032 handled = 1; 1033 1034 /* Acknowledge the interrupt */ 1035 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1036 sc->sc_command | SEEQ_CMD_RX_INTACK); 1037 1038 /* Processes the received packets */ 1039 ea_getpackets(sc); 1040 1041 1042 #if 0 1043 /* Make sure the receiver is on */ 1044 if ((status & SEEQ_STATUS_RX_ON) == 0) { 1045 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1046 sc->sc_command | SEEQ_CMD_RX_ON); 1047 printf("rxintr: rx is off st=%04x\n",status); 1048 } 1049 #endif 1050 } 1051 1052 #ifdef SEEQ_DEBUG 1053 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 1054 dprintf(("st=%04x\n", status)); 1055 #endif 1056 1057 return handled; 1058 } 1059 1060 1061 void 1062 ea_getpackets(struct seeq8005_softc *sc) 1063 { 1064 bus_space_tag_t iot = sc->sc_iot; 1065 bus_space_handle_t ioh = sc->sc_ioh; 1066 u_int addr; 1067 int len; 1068 int ctrl; 1069 int ptr; 1070 int pack; 1071 int status; 1072 u_int8_t rxhdr[4]; 1073 struct ifnet *ifp; 1074 1075 ifp = &sc->sc_ethercom.ec_if; 1076 1077 1078 /* We start from the last rx pointer position */ 1079 addr = sc->sc_rx_ptr; 1080 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1081 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1082 1083 do { 1084 /* Read rx header */ 1085 ea_readbuf(sc, rxhdr, addr, 4); 1086 1087 /* Split the packet header */ 1088 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1089 ctrl = rxhdr[2]; 1090 status = rxhdr[3]; 1091 1092 #ifdef SEEQ_RX_DEBUG 1093 dprintf(("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1094 addr, ptr, ctrl, status)); 1095 #endif 1096 1097 1098 /* Zero packet ptr ? then must be null header so exit */ 1099 if (ptr == 0) break; 1100 1101 1102 /* Get packet length */ 1103 len = (ptr - addr) - 4; 1104 1105 if (len < 0) 1106 len += sc->sc_rx_bufsize; 1107 1108 #ifdef SEEQ_RX_DEBUG 1109 dprintf(("len=%04x\n", len)); 1110 #endif 1111 1112 1113 /* Has the packet rx completed ? if not then exit */ 1114 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1115 break; 1116 1117 /* 1118 * Did we have any errors? then note error and go to 1119 * next packet 1120 */ 1121 if (__predict_false(status & SEEQ_RXSTAT_ERROR_MASK)) { 1122 ++ifp->if_ierrors; 1123 log(LOG_WARNING, 1124 "%s: rx packet error (%02x) - dropping packet\n", 1125 sc->sc_dev.dv_xname, status & 0x0f); 1126 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1127 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, 1128 sc->sc_config2); 1129 ea_init(ifp); 1130 return; 1131 } 1132 1133 /* 1134 * Is the packet too big ? - this will probably be trapped 1135 * above as a receive error 1136 */ 1137 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1138 ++ifp->if_ierrors; 1139 log(LOG_WARNING, "%s: rx packet size error len=%d\n", 1140 sc->sc_dev.dv_xname, len); 1141 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1142 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, 1143 sc->sc_config2); 1144 ea_init(ifp); 1145 return; 1146 } 1147 1148 ifp->if_ipackets++; 1149 /* Pass data up to upper levels. */ 1150 ea_read(sc, addr + 4, len); 1151 1152 addr = ptr; 1153 ++pack; 1154 } while (len != 0); 1155 1156 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1157 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1158 1159 #ifdef SEEQ_RX_DEBUG 1160 dprintf(("new rx ptr=%04x\n", addr)); 1161 #endif 1162 1163 1164 /* Store new rx pointer */ 1165 sc->sc_rx_ptr = addr; 1166 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1167 1168 /* Make sure the receiver is on */ 1169 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1170 sc->sc_command | SEEQ_CMD_RX_ON); 1171 1172 } 1173 1174 1175 /* 1176 * Pass a packet up to the higher levels. 1177 */ 1178 1179 static void 1180 ea_read(struct seeq8005_softc *sc, int addr, int len) 1181 { 1182 struct mbuf *m; 1183 struct ifnet *ifp; 1184 1185 ifp = &sc->sc_ethercom.ec_if; 1186 1187 /* Pull packet off interface. */ 1188 m = ea_get(sc, addr, len, ifp); 1189 if (m == 0) 1190 return; 1191 1192 #ifdef SEEQ_RX_DEBUG 1193 dprintf(("%s-->", ether_sprintf(eh->ether_shost))); 1194 dprintf(("%s\n", ether_sprintf(eh->ether_dhost))); 1195 #endif 1196 1197 #if NBPFILTER > 0 1198 /* 1199 * Check if there's a BPF listener on this interface. 1200 * If so, hand off the raw packet to bpf. 1201 */ 1202 if (ifp->if_bpf) 1203 bpf_mtap(ifp->if_bpf, m); 1204 #endif 1205 1206 (*ifp->if_input)(ifp, m); 1207 } 1208 1209 /* 1210 * Pull read data off a interface. Len is length of data, with local net 1211 * header stripped. We copy the data into mbufs. When full cluster sized 1212 * units are present we copy into clusters. 1213 */ 1214 1215 struct mbuf * 1216 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1217 { 1218 struct mbuf *top, **mp, *m; 1219 int len; 1220 u_int cp, epkt; 1221 1222 cp = addr; 1223 epkt = cp + totlen; 1224 1225 MGETHDR(m, M_DONTWAIT, MT_DATA); 1226 if (m == 0) 1227 return 0; 1228 m->m_pkthdr.rcvif = ifp; 1229 m->m_pkthdr.len = totlen; 1230 m->m_len = MHLEN; 1231 top = 0; 1232 mp = ⊤ 1233 1234 while (totlen > 0) { 1235 if (top) { 1236 MGET(m, M_DONTWAIT, MT_DATA); 1237 if (m == 0) { 1238 m_freem(top); 1239 return 0; 1240 } 1241 m->m_len = MLEN; 1242 } 1243 len = min(totlen, epkt - cp); 1244 if (len >= MINCLSIZE) { 1245 MCLGET(m, M_DONTWAIT); 1246 if (m->m_flags & M_EXT) 1247 m->m_len = len = min(len, MCLBYTES); 1248 else 1249 len = m->m_len; 1250 } else { 1251 /* 1252 * Place initial small packet/header at end of mbuf. 1253 */ 1254 if (len < m->m_len) { 1255 if (top == 0 && len + max_linkhdr <= m->m_len) 1256 m->m_data += max_linkhdr; 1257 m->m_len = len; 1258 } else 1259 len = m->m_len; 1260 } 1261 if (top == 0) { 1262 /* Make sure the payload is aligned */ 1263 caddr_t newdata = (caddr_t) 1264 ALIGN(m->m_data + sizeof(struct ether_header)) - 1265 sizeof(struct ether_header); 1266 len -= newdata - m->m_data; 1267 m->m_len = len; 1268 m->m_data = newdata; 1269 } 1270 ea_readbuf(sc, mtod(m, u_char *), 1271 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1272 len); 1273 cp += len; 1274 *mp = m; 1275 mp = &m->m_next; 1276 totlen -= len; 1277 if (cp == epkt) 1278 cp = addr; 1279 } 1280 1281 return top; 1282 } 1283 1284 /* 1285 * Process an ioctl request. Mostly boilerplate. 1286 */ 1287 static int 1288 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1289 { 1290 struct seeq8005_softc *sc = ifp->if_softc; 1291 int s, error = 0; 1292 1293 s = splnet(); 1294 switch (cmd) { 1295 1296 default: 1297 error = ether_ioctl(ifp, cmd, data); 1298 if (error == ENETRESET) { 1299 /* 1300 * Multicast list has changed; set the hardware filter 1301 * accordingly. 1302 */ 1303 ea_mc_reset(sc); 1304 error = 0; 1305 } 1306 break; 1307 } 1308 1309 splx(s); 1310 return error; 1311 } 1312 1313 /* Must be called at splnet() */ 1314 1315 static void 1316 ea_mc_reset(struct seeq8005_softc *sc) 1317 { 1318 1319 switch (sc->sc_variant) { 1320 case SEEQ_8004: 1321 ea_mc_reset_8004(sc); 1322 return; 1323 case SEEQ_8005: 1324 ea_mc_reset_8005(sc); 1325 return; 1326 } 1327 } 1328 1329 static void 1330 ea_mc_reset_8004(struct seeq8005_softc *sc) 1331 { 1332 struct ethercom *ec = &sc->sc_ethercom; 1333 struct ifnet *ifp = &ec->ec_if; 1334 struct ether_multi *enm; 1335 u_int8_t *cp, c; 1336 u_int32_t crc; 1337 int i, len; 1338 struct ether_multistep step; 1339 u_int8_t af[8]; 1340 1341 /* 1342 * Set up multicast address filter by passing all multicast addresses 1343 * through a crc generator, and then using bits 2 - 7 as an index 1344 * into the 64 bit logical address filter. The high order bits 1345 * selects the word, while the rest of the bits select the bit within 1346 * the word. 1347 */ 1348 1349 if (ifp->if_flags & IFF_PROMISC) { 1350 ifp->if_flags |= IFF_ALLMULTI; 1351 for (i = 0; i < 8; i++) 1352 af[i] = 0xff; 1353 return; 1354 } 1355 for (i = 0; i < 8; i++) 1356 af[i] = 0; 1357 ETHER_FIRST_MULTI(step, ec, enm); 1358 while (enm != NULL) { 1359 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1360 sizeof(enm->enm_addrlo)) != 0) { 1361 /* 1362 * We must listen to a range of multicast addresses. 1363 * For now, just accept all multicasts, rather than 1364 * trying to set only those filter bits needed to match 1365 * the range. (At this time, the only use of address 1366 * ranges is for IP multicast routing, for which the 1367 * range is big enough to require all bits set.) 1368 */ 1369 ifp->if_flags |= IFF_ALLMULTI; 1370 for (i = 0; i < 8; i++) 1371 af[i] = 0xff; 1372 break; 1373 } 1374 cp = enm->enm_addrlo; 1375 crc = 0xffffffff; 1376 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1377 c = *cp++; 1378 for (i = 8; --i >= 0;) { 1379 if (((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01)) { 1380 crc <<= 1; 1381 crc ^= 0x04c11db6 | 1; 1382 } else 1383 crc <<= 1; 1384 c >>= 1; 1385 } 1386 } 1387 /* Just want the 6 most significant bits. */ 1388 crc = (crc >> 2) & 0x3f; 1389 1390 /* Turn on the corresponding bit in the filter. */ 1391 af[crc >> 3] |= 1 << (crc & 0x7); 1392 1393 ETHER_NEXT_MULTI(step, enm); 1394 } 1395 ifp->if_flags &= ~IFF_ALLMULTI; 1396 1397 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1398 for (i = 0; i < 8; ++i) 1399 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1400 SEEQ_BUFWIN, af[i]); 1401 } 1402 1403 static void 1404 ea_mc_reset_8005(struct seeq8005_softc *sc) 1405 { 1406 struct ether_multi *enm; 1407 struct ether_multistep step; 1408 int naddr, maxaddrs; 1409 1410 naddr = 0; 1411 maxaddrs = 5; 1412 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1413 while (enm != NULL) { 1414 /* Have we got space? */ 1415 if (naddr >= maxaddrs || 1416 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1417 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1418 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1419 return; 1420 } 1421 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1422 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1423 naddr++; 1424 ETHER_NEXT_MULTI(step, enm); 1425 } 1426 for (; naddr < maxaddrs; naddr++) 1427 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1428 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1429 sc->sc_config1); 1430 } 1431 1432 /* 1433 * Device timeout routine. 1434 * 1435 * Ok I am not sure exactly how the device timeout should work.... 1436 * Currently what will happens is that that the device timeout is only 1437 * set when a packet it received. This indicates we are on an active 1438 * network and thus we should expect more packets. If non arrive in 1439 * in the timeout period then we reinitialise as we may have jammed. 1440 * We zero the timeout at this point so that we don't end up with 1441 * an endless stream of timeouts if the network goes down. 1442 */ 1443 1444 static void 1445 ea_watchdog(struct ifnet *ifp) 1446 { 1447 struct seeq8005_softc *sc = ifp->if_softc; 1448 1449 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1450 ifp->if_oerrors++; 1451 dprintf(("ea_watchdog: ")); 1452 dprintf(("st=%04x\n", 1453 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_STATUS))); 1454 1455 /* Kick the interface */ 1456 1457 ea_init(ifp); 1458 1459 /* ifp->if_timer = SEEQ_TIMEOUT;*/ 1460 ifp->if_timer = 0; 1461 } 1462 1463 /* End of if_ea.c */ 1464
Indexes created Tue Sep 30 07:10:03 GMT 2025