seeq8005.c revision 1.17
1 /* $NetBSD: seeq8005.c,v 1.17 2001/03/27 22:17:51 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chip: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 */ 43 /* 44 * More information on the 8004 and 8005 AEDLC controllers can be found in 45 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 46 * 47 * This data book may no longer be available as these are rather old chips 48 * (1991 - 1993) 49 */ 50 /* 51 * This driver is based on the arm32 ea(4) driver, hence the names of many 52 * of the functions. 53 */ 54 /* 55 * Bugs/possible improvements: 56 * - Does not currently support DMA 57 * - Does not transmit multiple packets in one go 58 * - Does not support 8-bit busses 59 */ 60 61 #include "opt_inet.h" 62 #include "opt_ns.h" 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 67 __RCSID("$NetBSD: seeq8005.c,v 1.17 2001/03/27 22:17:51 bjh21 Exp $"); 68 69 #include <sys/systm.h> 70 #include <sys/endian.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_types.h> 81 #include <net/if_ether.h> 82 #include <net/if_media.h> 83 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/in_systm.h> 87 #include <netinet/in_var.h> 88 #include <netinet/ip.h> 89 #include <netinet/if_inarp.h> 90 #endif 91 92 #ifdef NS 93 #include <netns/ns.h> 94 #include <netns/ns_if.h> 95 #endif 96 97 #include "bpfilter.h" 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <machine/bus.h> 104 #include <machine/intr.h> 105 106 #include <dev/ic/seeq8005reg.h> 107 #include <dev/ic/seeq8005var.h> 108 109 /*#define SEEQ_DEBUG*/ 110 111 /* for debugging convenience */ 112 #ifdef SEEQ8005_DEBUG 113 #define SEEQ_DEBUG_MISC 1 114 #define SEEQ_DEBUG_TX 2 115 #define SEEQ_DEBUG_RX 4 116 #define SEEQ_DEBUG_PKT 8 117 #define SEEQ_DEBUG_TXINT 16 118 #define SEEQ_DEBUG_RXINT 32 119 int seeq8005_debug = 0; 120 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 121 #else 122 #define DPRINTF(f, x) 123 #endif 124 125 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> MAX_ETHER_LEN) */ 126 127 /* 128 * prototypes 129 */ 130 131 static int ea_init(struct ifnet *); 132 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 133 static void ea_start(struct ifnet *); 134 static void ea_watchdog(struct ifnet *); 135 static void ea_chipreset(struct seeq8005_softc *); 136 static void ea_ramtest(struct seeq8005_softc *); 137 static int ea_stoptx(struct seeq8005_softc *); 138 static int ea_stoprx(struct seeq8005_softc *); 139 static void ea_stop(struct ifnet *, int); 140 static void ea_await_fifo_empty(struct seeq8005_softc *); 141 static void ea_await_fifo_full(struct seeq8005_softc *); 142 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 143 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_select_buffer(struct seeq8005_softc *, int); 145 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 146 static void ea_read(struct seeq8005_softc *, int, int); 147 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 148 static void ea_getpackets(struct seeq8005_softc *); 149 static void eatxpacket(struct seeq8005_softc *); 150 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 151 static void ea_mc_reset(struct seeq8005_softc *); 152 static void ea_mc_reset_8004(struct seeq8005_softc *); 153 static void ea_mc_reset_8005(struct seeq8005_softc *); 154 static int ea_mediachange(struct ifnet *); 155 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 156 157 158 /* 159 * Attach chip. 160 */ 161 162 void 163 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 164 int nmedia, int defmedia) 165 { 166 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 167 u_int id; 168 169 KASSERT(myaddr != NULL); 170 printf(" address %s", ether_sprintf(myaddr)); 171 172 /* Stop the board. */ 173 174 ea_chipreset(sc); 175 176 /* Get the product ID */ 177 178 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 179 id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 180 181 switch (id & SEEQ_PRODUCTID_MASK) { 182 case SEEQ_PRODUCTID_8004: 183 sc->sc_variant = SEEQ_8004; 184 break; 185 default: /* XXX */ 186 sc->sc_variant = SEEQ_8005; 187 break; 188 } 189 190 switch (sc->sc_variant) { 191 case SEEQ_8004: 192 printf(", SEEQ80C04 rev %x\n", 193 id & SEEQ_PRODUCTID_REV_MASK); 194 break; 195 case SEEQ_8005: 196 if (id != 0xff) 197 printf(", SEEQ8005 rev %x\n", id); 198 else 199 printf(", SEEQ8005\n"); 200 break; 201 default: 202 printf(", Unknown ethernet controller\n"); 203 return; 204 } 205 206 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 207 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 208 209 /* 210 * Set up tx and rx buffers. 211 * 212 * We use approximately a quarter of the packet memory for TX 213 * buffers and the rest for RX buffers 214 */ 215 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 216 sc->sc_tx_bufs = 1; 217 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 218 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 219 sc->sc_enabled = 0; 220 221 /* Test the RAM */ 222 ea_ramtest(sc); 223 224 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 225 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 226 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 227 228 /* Initialise ifnet structure. */ 229 230 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 231 ifp->if_softc = sc; 232 ifp->if_start = ea_start; 233 ifp->if_ioctl = ea_ioctl; 234 ifp->if_init = ea_init; 235 ifp->if_stop = ea_stop; 236 ifp->if_watchdog = ea_watchdog; 237 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 238 if (sc->sc_variant == SEEQ_8004) 239 ifp->if_flags |= IFF_SIMPLEX; 240 IFQ_SET_READY(&ifp->if_snd); 241 242 /* Initialize media goo. */ 243 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 244 if (media != NULL) { 245 int i; 246 247 for (i = 0; i < nmedia; i++) 248 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 249 ifmedia_set(&sc->sc_media, defmedia); 250 } else { 251 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 252 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 253 } 254 255 /* Now we can attach the interface. */ 256 257 if_attach(ifp); 258 ether_ifattach(ifp, myaddr); 259 260 printf("\n"); 261 } 262 263 /* 264 * Media change callback. 265 */ 266 static int 267 ea_mediachange(struct ifnet *ifp) 268 { 269 struct seeq8005_softc *sc = ifp->if_softc; 270 271 if (sc->sc_mediachange) 272 return ((*sc->sc_mediachange)(sc)); 273 return (EINVAL); 274 } 275 276 /* 277 * Media status callback. 278 */ 279 static void 280 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 281 { 282 struct seeq8005_softc *sc = ifp->if_softc; 283 284 if (sc->sc_enabled == 0) { 285 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 286 ifmr->ifm_status = 0; 287 return; 288 } 289 290 if (sc->sc_mediastatus) 291 (*sc->sc_mediastatus)(sc, ifmr); 292 } 293 294 /* 295 * Test the RAM on the ethernet card. 296 */ 297 298 void 299 ea_ramtest(struct seeq8005_softc *sc) 300 { 301 bus_space_tag_t iot = sc->sc_iot; 302 bus_space_handle_t ioh = sc->sc_ioh; 303 int loop; 304 u_int sum = 0; 305 306 /* 307 * Test the buffer memory on the board. 308 * Write simple pattens to it and read them back. 309 */ 310 311 /* Set up the whole buffer RAM for writing */ 312 313 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 314 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 315 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 316 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 317 318 #define SEEQ_RAMTEST_LOOP(value) \ 319 do { \ 320 /* Set the write start address and write a pattern */ \ 321 ea_writebuf(sc, NULL, 0x0000, 0); \ 322 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 323 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (value)); \ 324 \ 325 /* Set the read start address and verify the pattern */ \ 326 ea_readbuf(sc, NULL, 0x0000, 0); \ 327 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 328 if (bus_space_read_2(iot, ioh, SEEQ_BUFWIN) != (value)) \ 329 ++sum; \ 330 } while (/*CONSTCOND*/0) 331 332 SEEQ_RAMTEST_LOOP(loop); 333 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 334 SEEQ_RAMTEST_LOOP(0xaa55); 335 SEEQ_RAMTEST_LOOP(0x55aa); 336 337 /* Report */ 338 339 if (sum > 0) 340 printf("%s: buffer RAM failed self test, %d faults\n", 341 sc->sc_dev.dv_xname, sum); 342 } 343 344 345 /* 346 * Stop the tx interface. 347 * 348 * Returns 0 if the tx was already stopped or 1 if it was active 349 */ 350 351 static int 352 ea_stoptx(struct seeq8005_softc *sc) 353 { 354 bus_space_tag_t iot = sc->sc_iot; 355 bus_space_handle_t ioh = sc->sc_ioh; 356 int timeout; 357 int status; 358 359 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 360 361 sc->sc_enabled = 0; 362 363 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 364 if (!(status & SEEQ_STATUS_TX_ON)) 365 return 0; 366 367 /* Stop any tx and wait for confirmation */ 368 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 369 sc->sc_command | SEEQ_CMD_TX_OFF); 370 371 timeout = 20000; 372 do { 373 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 374 delay(1); 375 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 376 if (timeout == 0) 377 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 378 sc->sc_dev.dv_xname); 379 380 /* Clear any pending tx interrupt */ 381 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 382 sc->sc_command | SEEQ_CMD_TX_INTACK); 383 return 1; 384 } 385 386 387 /* 388 * Stop the rx interface. 389 * 390 * Returns 0 if the tx was already stopped or 1 if it was active 391 */ 392 393 static int 394 ea_stoprx(struct seeq8005_softc *sc) 395 { 396 bus_space_tag_t iot = sc->sc_iot; 397 bus_space_handle_t ioh = sc->sc_ioh; 398 int timeout; 399 int status; 400 401 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 402 403 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 404 if (!(status & SEEQ_STATUS_RX_ON)) 405 return 0; 406 407 /* Stop any rx and wait for confirmation */ 408 409 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 410 sc->sc_command | SEEQ_CMD_RX_OFF); 411 412 timeout = 20000; 413 do { 414 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 415 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 416 if (timeout == 0) 417 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 418 sc->sc_dev.dv_xname); 419 420 /* Clear any pending rx interrupt */ 421 422 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 423 sc->sc_command | SEEQ_CMD_RX_INTACK); 424 return 1; 425 } 426 427 428 /* 429 * Stop interface. 430 * Stop all IO and shut the interface down 431 */ 432 433 static void 434 ea_stop(struct ifnet *ifp, int disable) 435 { 436 struct seeq8005_softc *sc = ifp->if_softc; 437 bus_space_tag_t iot = sc->sc_iot; 438 bus_space_handle_t ioh = sc->sc_ioh; 439 440 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 441 442 /* Stop all IO */ 443 ea_stoptx(sc); 444 ea_stoprx(sc); 445 446 /* Disable rx and tx interrupts */ 447 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 448 449 /* Clear any pending interrupts */ 450 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 451 sc->sc_command | SEEQ_CMD_RX_INTACK | 452 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 453 SEEQ_CMD_BW_INTACK); 454 455 if (sc->sc_variant == SEEQ_8004) { 456 /* Put the chip to sleep */ 457 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 458 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 459 sc->sc_config3 | SEEQ_CFG3_SLEEP); 460 } 461 462 /* Cancel any watchdog timer */ 463 sc->sc_ethercom.ec_if.if_timer = 0; 464 } 465 466 467 /* 468 * Reset the chip 469 * Following this the software registers are reset 470 */ 471 472 static void 473 ea_chipreset(struct seeq8005_softc *sc) 474 { 475 bus_space_tag_t iot = sc->sc_iot; 476 bus_space_handle_t ioh = sc->sc_ioh; 477 478 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 479 480 /* Reset the controller. Min of 4us delay here */ 481 482 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 483 delay(4); 484 485 sc->sc_command = 0; 486 sc->sc_config1 = 0; 487 sc->sc_config2 = 0; 488 sc->sc_config3 = 0; 489 } 490 491 492 /* 493 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 494 * switching the FIFO from write to read. We also use it when changing 495 * the address for writes. 496 */ 497 static void 498 ea_await_fifo_empty(struct seeq8005_softc *sc) 499 { 500 bus_space_tag_t iot = sc->sc_iot; 501 bus_space_handle_t ioh = sc->sc_ioh; 502 int timeout; 503 504 timeout = 20000; 505 if ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 506 SEEQ_STATUS_FIFO_DIR) != 0) 507 return; /* FIFO is reading anyway. */ 508 while ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 509 SEEQ_STATUS_FIFO_EMPTY) == 0 && 510 --timeout > 0) 511 continue; 512 } 513 514 /* 515 * Wait for the DMA FIFO to fill before reading from it. 516 */ 517 static void 518 ea_await_fifo_full(struct seeq8005_softc *sc) 519 { 520 bus_space_tag_t iot = sc->sc_iot; 521 bus_space_handle_t ioh = sc->sc_ioh; 522 int timeout; 523 524 timeout = 20000; 525 while ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 526 SEEQ_STATUS_FIFO_FULL) == 0 && 527 --timeout > 0) 528 continue; 529 } 530 531 /* 532 * write to the buffer memory on the interface 533 * 534 * The buffer address is set to ADDR. 535 * If len != 0 then data is copied from the address starting at buf 536 * to the interface buffer. 537 * BUF must be usable as a u_int16_t *. 538 * If LEN is odd, it must be safe to overwrite one extra byte. 539 */ 540 541 static void 542 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 543 { 544 bus_space_tag_t iot = sc->sc_iot; 545 bus_space_handle_t ioh = sc->sc_ioh; 546 547 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 548 bus_space_read_2(iot, ioh, SEEQ_STATUS))); 549 550 #ifdef DIAGNOSTIC 551 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 552 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 553 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 554 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 555 #endif 556 557 /* Assume that copying too much is safe. */ 558 if (len % 2 != 0) 559 len++; 560 561 if (addr != -1) { 562 ea_await_fifo_empty(sc); 563 564 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 565 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 566 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 567 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 568 } 569 570 if (len > 0) 571 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 572 (u_int16_t *)buf, len / 2); 573 /* Leave FIFO to empty in the background */ 574 } 575 576 577 /* 578 * read from the buffer memory on the interface 579 * 580 * The buffer address is set to ADDR. 581 * If len != 0 then data is copied from the interface buffer to the 582 * address starting at buf. 583 * BUF must be usable as a u_int16_t *. 584 * If LEN is odd, it must be safe to overwrite one extra byte. 585 */ 586 587 static void 588 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 589 { 590 591 bus_space_tag_t iot = sc->sc_iot; 592 bus_space_handle_t ioh = sc->sc_ioh; 593 594 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 595 bus_space_read_2(iot, ioh, SEEQ_STATUS), addr, len)); 596 597 #ifdef DIAGNOSTIC 598 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 599 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 600 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 601 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 602 #endif 603 604 /* Assume that copying too much is safe. */ 605 if (len % 2 != 0) 606 len++; 607 608 if (addr != -1) { 609 ea_await_fifo_empty(sc); 610 611 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 612 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 613 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 614 sc->sc_command | SEEQ_CMD_FIFO_READ); 615 616 ea_await_fifo_full(sc); 617 } 618 619 if (len > 0) 620 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 621 (u_int16_t *)buf, len / 2); 622 } 623 624 static void 625 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 626 { 627 628 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 629 sc->sc_config1 | bufcode); 630 } 631 632 /* Must be called at splnet */ 633 static void 634 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 635 { 636 int i; 637 638 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 639 for (i = 0; i < ETHER_ADDR_LEN; ++i) 640 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 641 ea[i]); 642 } 643 644 /* 645 * Initialize interface. 646 * 647 * This should leave the interface in a state for packet reception and 648 * transmission. 649 */ 650 651 static int 652 ea_init(struct ifnet *ifp) 653 { 654 struct seeq8005_softc *sc = ifp->if_softc; 655 bus_space_tag_t iot = sc->sc_iot; 656 bus_space_handle_t ioh = sc->sc_ioh; 657 int s; 658 659 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 660 661 s = splnet(); 662 663 /* First, reset the board. */ 664 665 ea_chipreset(sc); 666 667 /* Set up defaults for the registers */ 668 669 sc->sc_command = 0; 670 sc->sc_config1 = 0; 671 #if BYTE_ORDER == BIG_ENDIAN 672 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 673 #else 674 sc->sc_config2 = 0; 675 #endif 676 sc->sc_config3 = 0; 677 678 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 679 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 680 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 681 if (sc->sc_variant == SEEQ_8004) { 682 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 683 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 684 } 685 686 /* Write the station address - the receiver must be off */ 687 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 688 689 /* Split board memory into Rx and Tx. */ 690 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 691 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 692 693 if (sc->sc_variant == SEEQ_8004) 694 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 695 696 /* Configure rx. */ 697 ea_mc_reset(sc); 698 if (ifp->if_flags & IFF_PROMISC) 699 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 700 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 701 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 702 else 703 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 704 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 705 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 706 707 /* Setup the Rx pointers */ 708 sc->sc_rx_ptr = sc->sc_tx_bufsize; 709 710 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 711 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 712 713 714 /* Place a NULL header at the beginning of the receive area */ 715 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 716 717 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 718 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 719 720 721 /* Configure TX. */ 722 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 723 724 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 725 726 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 727 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 728 729 /* Reset tx buffer pointers */ 730 sc->sc_tx_cur = 0; 731 sc->sc_tx_used = 0; 732 sc->sc_tx_next = 0; 733 734 /* Place a NULL header at the beginning of the transmit area */ 735 ea_writebuf(sc, NULL, 0x0000, 0); 736 737 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 738 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 739 740 sc->sc_command |= SEEQ_CMD_TX_INTEN; 741 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 742 743 /* Turn on Rx */ 744 sc->sc_command |= SEEQ_CMD_RX_INTEN; 745 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 746 sc->sc_command | SEEQ_CMD_RX_ON); 747 748 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 749 750 751 /* Set flags appropriately. */ 752 ifp->if_flags |= IFF_RUNNING; 753 ifp->if_flags &= ~IFF_OACTIVE; 754 sc->sc_enabled = 1; 755 756 /* And start output. */ 757 ea_start(ifp); 758 759 splx(s); 760 return 0; 761 } 762 763 /* 764 * Start output on interface. Get datagrams from the queue and output them, 765 * giving the receiver a chance between datagrams. Call only from splnet or 766 * interrupt level! 767 */ 768 769 static void 770 ea_start(struct ifnet *ifp) 771 { 772 struct seeq8005_softc *sc = ifp->if_softc; 773 int s; 774 775 s = splnet(); 776 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 777 778 /* 779 * Don't do anything if output is active. seeq8005intr() will call 780 * us (actually eatxpacket()) back when the card's ready for more 781 * frames. 782 */ 783 if (ifp->if_flags & IFF_OACTIVE) 784 return; 785 786 /* Mark interface as output active */ 787 788 ifp->if_flags |= IFF_OACTIVE; 789 790 /* tx packets */ 791 792 eatxpacket(sc); 793 splx(s); 794 } 795 796 797 /* 798 * Transfer a packet to the interface buffer and start transmission 799 * 800 * Called at splnet() 801 */ 802 803 void 804 eatxpacket(struct seeq8005_softc *sc) 805 { 806 bus_space_tag_t iot = sc->sc_iot; 807 bus_space_handle_t ioh = sc->sc_ioh; 808 struct mbuf *m0; 809 struct ifnet *ifp; 810 811 ifp = &sc->sc_ethercom.ec_if; 812 813 /* Dequeue the next packet. */ 814 IFQ_DEQUEUE(&ifp->if_snd, m0); 815 816 /* If there's nothing to send, return. */ 817 if (!m0) { 818 ifp->if_flags &= ~IFF_OACTIVE; 819 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 820 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 821 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 822 return; 823 } 824 825 #if NBPFILTER > 0 826 /* Give the packet to the bpf, if any. */ 827 if (ifp->if_bpf) 828 bpf_mtap(ifp->if_bpf, m0); 829 #endif 830 831 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 832 833 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 834 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 835 836 ea_writembuf(sc, m0, 0x0000); 837 m_freem(m0); 838 839 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 840 841 /* Now transmit the datagram. */ 842 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 843 sc->sc_command | SEEQ_CMD_TX_ON); 844 845 /* Make sure we notice if the chip goes silent on us. */ 846 ifp->if_timer = 5; 847 848 DPRINTF(SEEQ_DEBUG_TX, 849 ("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS))); 850 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 851 } 852 853 /* 854 * Copy a packet from an mbuf to the transmit buffer on the card. 855 * 856 * Puts a valid Tx header at the start of the packet, and a null header at 857 * the end. 858 */ 859 static int 860 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 861 { 862 struct mbuf *m; 863 int len, nextpacket; 864 u_int8_t hdr[4]; 865 866 /* 867 * Copy the datagram to the packet buffer. 868 */ 869 ea_writebuf(sc, NULL, bufstart + 4, 0); 870 871 len = 0; 872 for (m = m0; m; m = m->m_next) { 873 if (m->m_len == 0) 874 continue; 875 ea_writebuf(sc, mtod(m, caddr_t), -1, m->m_len); 876 len += m->m_len; 877 } 878 879 /* If packet size is odd round up to the next 16 bit boundry */ 880 if (len % 2) 881 ++len; 882 883 len = max(len, ETHER_MIN_LEN); 884 885 ea_writebuf(sc, NULL, bufstart + 4 + len, 0); 886 /* Follow it with a NULL packet header */ 887 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 888 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 889 890 /* Ok we now have a packet len bytes long in our packet buffer */ 891 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 892 893 /* Write the packet header */ 894 nextpacket = len + 4; 895 hdr[0] = (nextpacket >> 8) & 0xff; 896 hdr[1] = nextpacket & 0xff; 897 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 898 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 899 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 900 ea_writebuf(sc, hdr, 0x0000, 4); 901 902 return len; 903 } 904 905 /* 906 * Ethernet controller interrupt. 907 */ 908 909 int 910 seeq8005intr(void *arg) 911 { 912 struct seeq8005_softc *sc = arg; 913 bus_space_tag_t iot = sc->sc_iot; 914 bus_space_handle_t ioh = sc->sc_ioh; 915 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 916 int status, handled; 917 u_int8_t txhdr[4]; 918 u_int txstatus; 919 920 handled = 0; 921 922 /* Get the controller status */ 923 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 924 925 /* Tx interrupt ? */ 926 if (status & SEEQ_STATUS_TX_INT) { 927 handled = 1; 928 929 /* Acknowledge the interrupt */ 930 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 931 sc->sc_command | SEEQ_CMD_TX_INTACK); 932 933 ea_readbuf(sc, txhdr, 0x0000, 4); 934 935 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 936 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 937 txstatus = txhdr[3]; 938 939 /* 940 * If SEEQ_TXSTAT_COLLISION is set then we received at least 941 * one collision. On the 8004 we can find out exactly how many 942 * collisions occurred. 943 * 944 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 945 * completed. 946 * 947 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 948 * occurred and the packet transmission was aborted. 949 * This situation is untested as present. 950 * 951 * The SEEQ_TXSTAT_BABBLE should never be set and is untested 952 * as we should never xmit oversized packets. 953 */ 954 if (txstatus & SEEQ_TXSTAT_COLLISION) { 955 switch (sc->sc_variant) { 956 case SEEQ_8004: { 957 int colls; 958 959 /* 960 * The 8004 contains a 4 bit collision count 961 * in the status register. 962 */ 963 964 /* This appears to be broken on 80C04.AE */ 965 /* ifp->if_collisions += 966 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 967 & SEEQ_TXSTAT_COLLISION_MASK;*/ 968 969 /* Use the TX Collision register */ 970 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 971 colls = bus_space_read_1(iot, ioh, 972 SEEQ_BUFWIN); 973 ifp->if_collisions += colls; 974 break; 975 } 976 case SEEQ_8005: 977 /* We known there was at least 1 collision */ 978 ifp->if_collisions++; 979 break; 980 } 981 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 982 printf("seeq_intr: col16 %x\n", txstatus); 983 ifp->if_collisions += 16; 984 ifp->if_oerrors++; 985 } else if (txstatus & SEEQ_TXSTAT_BABBLE) { 986 ifp->if_oerrors++; 987 } 988 989 /* Have we completed transmission on the packet ? */ 990 if (txstatus & SEEQ_PKTSTAT_DONE) { 991 /* Clear watchdog timer. */ 992 ifp->if_timer = 0; 993 ifp->if_flags &= ~IFF_OACTIVE; 994 995 /* Update stats */ 996 ifp->if_opackets++; 997 998 /* Tx next packet */ 999 1000 eatxpacket(sc); 1001 } 1002 1003 } 1004 1005 1006 /* Rx interrupt ? */ 1007 if (status & SEEQ_STATUS_RX_INT) { 1008 handled = 1; 1009 1010 /* Acknowledge the interrupt */ 1011 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1012 sc->sc_command | SEEQ_CMD_RX_INTACK); 1013 1014 /* Processes the received packets */ 1015 ea_getpackets(sc); 1016 1017 1018 #if 0 1019 /* Make sure the receiver is on */ 1020 if ((status & SEEQ_STATUS_RX_ON) == 0) { 1021 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1022 sc->sc_command | SEEQ_CMD_RX_ON); 1023 printf("rxintr: rx is off st=%04x\n",status); 1024 } 1025 #endif 1026 } 1027 1028 return handled; 1029 } 1030 1031 1032 void 1033 ea_getpackets(struct seeq8005_softc *sc) 1034 { 1035 bus_space_tag_t iot = sc->sc_iot; 1036 bus_space_handle_t ioh = sc->sc_ioh; 1037 u_int addr; 1038 int len; 1039 int ctrl; 1040 int ptr; 1041 int pack; 1042 int status; 1043 u_int8_t rxhdr[4]; 1044 struct ifnet *ifp; 1045 1046 ifp = &sc->sc_ethercom.ec_if; 1047 1048 1049 /* We start from the last rx pointer position */ 1050 addr = sc->sc_rx_ptr; 1051 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1052 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1053 1054 do { 1055 /* Read rx header */ 1056 ea_readbuf(sc, rxhdr, addr, 4); 1057 1058 /* Split the packet header */ 1059 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1060 ctrl = rxhdr[2]; 1061 status = rxhdr[3]; 1062 1063 DPRINTF(SEEQ_DEBUG_RX, 1064 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1065 addr, ptr, ctrl, status)); 1066 1067 /* Zero packet ptr ? then must be null header so exit */ 1068 if (ptr == 0) break; 1069 1070 /* Sanity-check the next-packet pointer and flags. */ 1071 if (__predict_false(ptr < sc->sc_tx_bufsize || 1072 (ctrl & SEEQ_PKTCMD_TX))) { 1073 ++ifp->if_ierrors; 1074 log(LOG_ERR, 1075 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1076 sc->sc_dev.dv_xname, addr, ptr); 1077 ea_init(ifp); 1078 return; 1079 } 1080 1081 /* Get packet length */ 1082 len = (ptr - addr) - 4; 1083 1084 if (len < 0) 1085 len += sc->sc_rx_bufsize; 1086 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1087 1088 /* Has the packet rx completed ? if not then exit */ 1089 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1090 break; 1091 1092 /* 1093 * Did we have any errors? then note error and go to 1094 * next packet 1095 */ 1096 if (__predict_false(status & SEEQ_RXSTAT_ERROR_MASK)) { 1097 ++ifp->if_ierrors; 1098 /* XXX oversize packets may be OK */ 1099 log(LOG_WARNING, 1100 "%s: rx packet error at %04x (err=%02x)\n", 1101 sc->sc_dev.dv_xname, addr, status & 0x0f); 1102 goto pktdone; 1103 } 1104 /* 1105 * Is the packet too big ? - this will probably be trapped 1106 * above as a receive error. If it's not, this is indicative 1107 * of buffer corruption. 1108 */ 1109 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1110 ++ifp->if_ierrors; 1111 log(LOG_ERR, 1112 "%s: rx packet size error at %04x (len=%d)\n", 1113 sc->sc_dev.dv_xname, addr, len); 1114 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1115 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, 1116 sc->sc_config2); 1117 ea_init(ifp); 1118 return; 1119 } 1120 1121 ifp->if_ipackets++; 1122 /* Pass data up to upper levels. */ 1123 ea_read(sc, addr + 4, len); 1124 1125 pktdone: 1126 addr = ptr; 1127 ++pack; 1128 } while (len != 0); 1129 1130 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1131 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1132 1133 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1134 1135 /* Store new rx pointer */ 1136 sc->sc_rx_ptr = addr; 1137 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1138 1139 /* Make sure the receiver is on */ 1140 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1141 sc->sc_command | SEEQ_CMD_RX_ON); 1142 } 1143 1144 1145 /* 1146 * Pass a packet up to the higher levels. 1147 */ 1148 1149 static void 1150 ea_read(struct seeq8005_softc *sc, int addr, int len) 1151 { 1152 struct mbuf *m; 1153 struct ifnet *ifp; 1154 1155 ifp = &sc->sc_ethercom.ec_if; 1156 1157 /* Pull packet off interface. */ 1158 m = ea_get(sc, addr, len, ifp); 1159 if (m == 0) 1160 return; 1161 1162 #if NBPFILTER > 0 1163 /* 1164 * Check if there's a BPF listener on this interface. 1165 * If so, hand off the raw packet to bpf. 1166 */ 1167 if (ifp->if_bpf) 1168 bpf_mtap(ifp->if_bpf, m); 1169 #endif 1170 1171 (*ifp->if_input)(ifp, m); 1172 } 1173 1174 /* 1175 * Pull read data off a interface. Len is length of data, with local net 1176 * header stripped. We copy the data into mbufs. When full cluster sized 1177 * units are present we copy into clusters. 1178 */ 1179 1180 struct mbuf * 1181 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1182 { 1183 struct mbuf *top, **mp, *m; 1184 int len; 1185 u_int cp, epkt; 1186 1187 cp = addr; 1188 epkt = cp + totlen; 1189 1190 MGETHDR(m, M_DONTWAIT, MT_DATA); 1191 if (m == 0) 1192 return 0; 1193 m->m_pkthdr.rcvif = ifp; 1194 m->m_pkthdr.len = totlen; 1195 m->m_len = MHLEN; 1196 top = 0; 1197 mp = ⊤ 1198 1199 while (totlen > 0) { 1200 if (top) { 1201 MGET(m, M_DONTWAIT, MT_DATA); 1202 if (m == 0) { 1203 m_freem(top); 1204 return 0; 1205 } 1206 m->m_len = MLEN; 1207 } 1208 len = min(totlen, epkt - cp); 1209 if (len >= MINCLSIZE) { 1210 MCLGET(m, M_DONTWAIT); 1211 if (m->m_flags & M_EXT) 1212 m->m_len = len = min(len, MCLBYTES); 1213 else 1214 len = m->m_len; 1215 } else { 1216 /* 1217 * Place initial small packet/header at end of mbuf. 1218 */ 1219 if (len < m->m_len) { 1220 if (top == 0 && len + max_linkhdr <= m->m_len) 1221 m->m_data += max_linkhdr; 1222 m->m_len = len; 1223 } else 1224 len = m->m_len; 1225 } 1226 if (top == 0) { 1227 /* Make sure the payload is aligned */ 1228 caddr_t newdata = (caddr_t) 1229 ALIGN(m->m_data + sizeof(struct ether_header)) - 1230 sizeof(struct ether_header); 1231 len -= newdata - m->m_data; 1232 m->m_len = len; 1233 m->m_data = newdata; 1234 } 1235 ea_readbuf(sc, mtod(m, u_char *), 1236 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1237 len); 1238 cp += len; 1239 *mp = m; 1240 mp = &m->m_next; 1241 totlen -= len; 1242 if (cp == epkt) 1243 cp = addr; 1244 } 1245 1246 return top; 1247 } 1248 1249 /* 1250 * Process an ioctl request. Mostly boilerplate. 1251 */ 1252 static int 1253 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1254 { 1255 struct seeq8005_softc *sc = ifp->if_softc; 1256 int s, error = 0; 1257 1258 s = splnet(); 1259 switch (cmd) { 1260 1261 default: 1262 error = ether_ioctl(ifp, cmd, data); 1263 if (error == ENETRESET) { 1264 /* 1265 * Multicast list has changed; set the hardware filter 1266 * accordingly. 1267 */ 1268 ea_mc_reset(sc); 1269 error = 0; 1270 } 1271 break; 1272 } 1273 1274 splx(s); 1275 return error; 1276 } 1277 1278 /* Must be called at splnet() */ 1279 1280 static void 1281 ea_mc_reset(struct seeq8005_softc *sc) 1282 { 1283 1284 switch (sc->sc_variant) { 1285 case SEEQ_8004: 1286 ea_mc_reset_8004(sc); 1287 return; 1288 case SEEQ_8005: 1289 ea_mc_reset_8005(sc); 1290 return; 1291 } 1292 } 1293 1294 static void 1295 ea_mc_reset_8004(struct seeq8005_softc *sc) 1296 { 1297 struct ethercom *ec = &sc->sc_ethercom; 1298 struct ifnet *ifp = &ec->ec_if; 1299 struct ether_multi *enm; 1300 u_int8_t *cp, c; 1301 u_int32_t crc; 1302 int i, len; 1303 struct ether_multistep step; 1304 u_int8_t af[8]; 1305 1306 /* 1307 * Set up multicast address filter by passing all multicast addresses 1308 * through a crc generator, and then using bits 2 - 7 as an index 1309 * into the 64 bit logical address filter. The high order bits 1310 * selects the word, while the rest of the bits select the bit within 1311 * the word. 1312 */ 1313 1314 if (ifp->if_flags & IFF_PROMISC) { 1315 ifp->if_flags |= IFF_ALLMULTI; 1316 for (i = 0; i < 8; i++) 1317 af[i] = 0xff; 1318 return; 1319 } 1320 for (i = 0; i < 8; i++) 1321 af[i] = 0; 1322 ETHER_FIRST_MULTI(step, ec, enm); 1323 while (enm != NULL) { 1324 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1325 sizeof(enm->enm_addrlo)) != 0) { 1326 /* 1327 * We must listen to a range of multicast addresses. 1328 * For now, just accept all multicasts, rather than 1329 * trying to set only those filter bits needed to match 1330 * the range. (At this time, the only use of address 1331 * ranges is for IP multicast routing, for which the 1332 * range is big enough to require all bits set.) 1333 */ 1334 ifp->if_flags |= IFF_ALLMULTI; 1335 for (i = 0; i < 8; i++) 1336 af[i] = 0xff; 1337 break; 1338 } 1339 cp = enm->enm_addrlo; 1340 crc = 0xffffffff; 1341 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1342 c = *cp++; 1343 for (i = 8; --i >= 0;) { 1344 if (((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01)) { 1345 crc <<= 1; 1346 crc ^= 0x04c11db6 | 1; 1347 } else 1348 crc <<= 1; 1349 c >>= 1; 1350 } 1351 } 1352 /* Just want the 6 most significant bits. */ 1353 crc = (crc >> 2) & 0x3f; 1354 1355 /* Turn on the corresponding bit in the filter. */ 1356 af[crc >> 3] |= 1 << (crc & 0x7); 1357 1358 ETHER_NEXT_MULTI(step, enm); 1359 } 1360 ifp->if_flags &= ~IFF_ALLMULTI; 1361 1362 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1363 for (i = 0; i < 8; ++i) 1364 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1365 SEEQ_BUFWIN, af[i]); 1366 } 1367 1368 static void 1369 ea_mc_reset_8005(struct seeq8005_softc *sc) 1370 { 1371 struct ether_multi *enm; 1372 struct ether_multistep step; 1373 int naddr, maxaddrs; 1374 1375 naddr = 0; 1376 maxaddrs = 5; 1377 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1378 while (enm != NULL) { 1379 /* Have we got space? */ 1380 if (naddr >= maxaddrs || 1381 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1382 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1383 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1384 return; 1385 } 1386 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1387 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1388 naddr++; 1389 ETHER_NEXT_MULTI(step, enm); 1390 } 1391 for (; naddr < maxaddrs; naddr++) 1392 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1393 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1394 sc->sc_config1); 1395 } 1396 1397 /* 1398 * Device timeout routine. 1399 */ 1400 1401 static void 1402 ea_watchdog(struct ifnet *ifp) 1403 { 1404 struct seeq8005_softc *sc = ifp->if_softc; 1405 1406 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1407 sc->sc_dev.dv_xname, 1408 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1409 ifp->if_oerrors++; 1410 1411 /* Kick the interface */ 1412 1413 ea_init(ifp); 1414 1415 ifp->if_timer = 0; 1416 } 1417 1418 /* End of if_ea.c */ 1419
Indexes created Mon Sep 29 21:09:56 GMT 2025