seeq8005.c revision 1.18
1 /* $NetBSD: seeq8005.c,v 1.18 2001/03/29 17:46:39 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chip: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 */ 43 /* 44 * More information on the 8004 and 8005 AEDLC controllers can be found in 45 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 46 * 47 * This data book may no longer be available as these are rather old chips 48 * (1991 - 1993) 49 */ 50 /* 51 * This driver is based on the arm32 ea(4) driver, hence the names of many 52 * of the functions. 53 */ 54 /* 55 * Bugs/possible improvements: 56 * - Does not currently support DMA 57 * - Does not transmit multiple packets in one go 58 * - Does not support 8-bit busses 59 */ 60 61 #include "opt_inet.h" 62 #include "opt_ns.h" 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 67 __RCSID("$NetBSD: seeq8005.c,v 1.18 2001/03/29 17:46:39 bjh21 Exp $"); 68 69 #include <sys/systm.h> 70 #include <sys/endian.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_types.h> 81 #include <net/if_ether.h> 82 #include <net/if_media.h> 83 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/in_systm.h> 87 #include <netinet/in_var.h> 88 #include <netinet/ip.h> 89 #include <netinet/if_inarp.h> 90 #endif 91 92 #ifdef NS 93 #include <netns/ns.h> 94 #include <netns/ns_if.h> 95 #endif 96 97 #include "bpfilter.h" 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <machine/bus.h> 104 #include <machine/intr.h> 105 106 #include <dev/ic/seeq8005reg.h> 107 #include <dev/ic/seeq8005var.h> 108 109 /*#define SEEQ_DEBUG*/ 110 111 /* for debugging convenience */ 112 #ifdef SEEQ8005_DEBUG 113 #define SEEQ_DEBUG_MISC 1 114 #define SEEQ_DEBUG_TX 2 115 #define SEEQ_DEBUG_RX 4 116 #define SEEQ_DEBUG_PKT 8 117 #define SEEQ_DEBUG_TXINT 16 118 #define SEEQ_DEBUG_RXINT 32 119 int seeq8005_debug = 0; 120 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 121 #else 122 #define DPRINTF(f, x) 123 #endif 124 125 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> MAX_ETHER_LEN) */ 126 127 /* 128 * prototypes 129 */ 130 131 static int ea_init(struct ifnet *); 132 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 133 static void ea_start(struct ifnet *); 134 static void ea_watchdog(struct ifnet *); 135 static void ea_chipreset(struct seeq8005_softc *); 136 static void ea_ramtest(struct seeq8005_softc *); 137 static int ea_stoptx(struct seeq8005_softc *); 138 static int ea_stoprx(struct seeq8005_softc *); 139 static void ea_stop(struct ifnet *, int); 140 static void ea_await_fifo_empty(struct seeq8005_softc *); 141 static void ea_await_fifo_full(struct seeq8005_softc *); 142 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 143 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_select_buffer(struct seeq8005_softc *, int); 145 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 146 static void ea_read(struct seeq8005_softc *, int, int); 147 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 148 static void ea_getpackets(struct seeq8005_softc *); 149 static void eatxpacket(struct seeq8005_softc *); 150 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 151 static void ea_mc_reset(struct seeq8005_softc *); 152 static void ea_mc_reset_8004(struct seeq8005_softc *); 153 static void ea_mc_reset_8005(struct seeq8005_softc *); 154 static int ea_mediachange(struct ifnet *); 155 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 156 157 158 /* 159 * Attach chip. 160 */ 161 162 void 163 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 164 int nmedia, int defmedia) 165 { 166 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 167 u_int id; 168 169 KASSERT(myaddr != NULL); 170 printf(" address %s", ether_sprintf(myaddr)); 171 172 /* Stop the board. */ 173 174 ea_chipreset(sc); 175 176 /* Get the product ID */ 177 178 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 179 id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 180 181 switch (id & SEEQ_PRODUCTID_MASK) { 182 case SEEQ_PRODUCTID_8004: 183 sc->sc_variant = SEEQ_8004; 184 break; 185 default: /* XXX */ 186 sc->sc_variant = SEEQ_8005; 187 break; 188 } 189 190 switch (sc->sc_variant) { 191 case SEEQ_8004: 192 printf(", SEEQ80C04 rev %x\n", 193 id & SEEQ_PRODUCTID_REV_MASK); 194 break; 195 case SEEQ_8005: 196 if (id != 0xff) 197 printf(", SEEQ8005 rev %x\n", id); 198 else 199 printf(", SEEQ8005\n"); 200 break; 201 default: 202 printf(", Unknown ethernet controller\n"); 203 return; 204 } 205 206 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 207 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 208 209 /* 210 * Set up tx and rx buffers. 211 * 212 * We use approximately a quarter of the packet memory for TX 213 * buffers and the rest for RX buffers 214 */ 215 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 216 sc->sc_tx_bufs = 1; 217 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 218 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 219 sc->sc_enabled = 0; 220 221 /* Test the RAM */ 222 ea_ramtest(sc); 223 224 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 225 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 226 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 227 228 /* Initialise ifnet structure. */ 229 230 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 231 ifp->if_softc = sc; 232 ifp->if_start = ea_start; 233 ifp->if_ioctl = ea_ioctl; 234 ifp->if_init = ea_init; 235 ifp->if_stop = ea_stop; 236 ifp->if_watchdog = ea_watchdog; 237 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 238 if (sc->sc_variant == SEEQ_8004) 239 ifp->if_flags |= IFF_SIMPLEX; 240 IFQ_SET_READY(&ifp->if_snd); 241 242 /* Initialize media goo. */ 243 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 244 if (media != NULL) { 245 int i; 246 247 for (i = 0; i < nmedia; i++) 248 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 249 ifmedia_set(&sc->sc_media, defmedia); 250 } else { 251 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 252 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 253 } 254 255 /* Now we can attach the interface. */ 256 257 if_attach(ifp); 258 ether_ifattach(ifp, myaddr); 259 260 printf("\n"); 261 } 262 263 /* 264 * Media change callback. 265 */ 266 static int 267 ea_mediachange(struct ifnet *ifp) 268 { 269 struct seeq8005_softc *sc = ifp->if_softc; 270 271 if (sc->sc_mediachange) 272 return ((*sc->sc_mediachange)(sc)); 273 return (EINVAL); 274 } 275 276 /* 277 * Media status callback. 278 */ 279 static void 280 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 281 { 282 struct seeq8005_softc *sc = ifp->if_softc; 283 284 if (sc->sc_enabled == 0) { 285 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 286 ifmr->ifm_status = 0; 287 return; 288 } 289 290 if (sc->sc_mediastatus) 291 (*sc->sc_mediastatus)(sc, ifmr); 292 } 293 294 /* 295 * Test the RAM on the ethernet card. 296 */ 297 298 void 299 ea_ramtest(struct seeq8005_softc *sc) 300 { 301 bus_space_tag_t iot = sc->sc_iot; 302 bus_space_handle_t ioh = sc->sc_ioh; 303 int loop; 304 u_int sum = 0; 305 306 /* 307 * Test the buffer memory on the board. 308 * Write simple pattens to it and read them back. 309 */ 310 311 /* Set up the whole buffer RAM for writing */ 312 313 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 314 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 315 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 316 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 317 318 #define SEEQ_RAMTEST_LOOP(value) \ 319 do { \ 320 /* Set the write start address and write a pattern */ \ 321 ea_writebuf(sc, NULL, 0x0000, 0); \ 322 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 323 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (value)); \ 324 \ 325 /* Set the read start address and verify the pattern */ \ 326 ea_readbuf(sc, NULL, 0x0000, 0); \ 327 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 328 if (bus_space_read_2(iot, ioh, SEEQ_BUFWIN) != (value)) \ 329 ++sum; \ 330 } while (/*CONSTCOND*/0) 331 332 SEEQ_RAMTEST_LOOP(loop); 333 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 334 SEEQ_RAMTEST_LOOP(0xaa55); 335 SEEQ_RAMTEST_LOOP(0x55aa); 336 337 /* Report */ 338 339 if (sum > 0) 340 printf("%s: buffer RAM failed self test, %d faults\n", 341 sc->sc_dev.dv_xname, sum); 342 } 343 344 345 /* 346 * Stop the tx interface. 347 * 348 * Returns 0 if the tx was already stopped or 1 if it was active 349 */ 350 351 static int 352 ea_stoptx(struct seeq8005_softc *sc) 353 { 354 bus_space_tag_t iot = sc->sc_iot; 355 bus_space_handle_t ioh = sc->sc_ioh; 356 int timeout; 357 int status; 358 359 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 360 361 sc->sc_enabled = 0; 362 363 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 364 if (!(status & SEEQ_STATUS_TX_ON)) 365 return 0; 366 367 /* Stop any tx and wait for confirmation */ 368 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 369 sc->sc_command | SEEQ_CMD_TX_OFF); 370 371 timeout = 20000; 372 do { 373 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 374 delay(1); 375 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 376 if (timeout == 0) 377 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 378 sc->sc_dev.dv_xname); 379 380 /* Clear any pending tx interrupt */ 381 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 382 sc->sc_command | SEEQ_CMD_TX_INTACK); 383 return 1; 384 } 385 386 387 /* 388 * Stop the rx interface. 389 * 390 * Returns 0 if the tx was already stopped or 1 if it was active 391 */ 392 393 static int 394 ea_stoprx(struct seeq8005_softc *sc) 395 { 396 bus_space_tag_t iot = sc->sc_iot; 397 bus_space_handle_t ioh = sc->sc_ioh; 398 int timeout; 399 int status; 400 401 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 402 403 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 404 if (!(status & SEEQ_STATUS_RX_ON)) 405 return 0; 406 407 /* Stop any rx and wait for confirmation */ 408 409 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 410 sc->sc_command | SEEQ_CMD_RX_OFF); 411 412 timeout = 20000; 413 do { 414 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 415 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 416 if (timeout == 0) 417 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 418 sc->sc_dev.dv_xname); 419 420 /* Clear any pending rx interrupt */ 421 422 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 423 sc->sc_command | SEEQ_CMD_RX_INTACK); 424 return 1; 425 } 426 427 428 /* 429 * Stop interface. 430 * Stop all IO and shut the interface down 431 */ 432 433 static void 434 ea_stop(struct ifnet *ifp, int disable) 435 { 436 struct seeq8005_softc *sc = ifp->if_softc; 437 bus_space_tag_t iot = sc->sc_iot; 438 bus_space_handle_t ioh = sc->sc_ioh; 439 440 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 441 442 /* Stop all IO */ 443 ea_stoptx(sc); 444 ea_stoprx(sc); 445 446 /* Disable rx and tx interrupts */ 447 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 448 449 /* Clear any pending interrupts */ 450 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 451 sc->sc_command | SEEQ_CMD_RX_INTACK | 452 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 453 SEEQ_CMD_BW_INTACK); 454 455 if (sc->sc_variant == SEEQ_8004) { 456 /* Put the chip to sleep */ 457 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 458 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 459 sc->sc_config3 | SEEQ_CFG3_SLEEP); 460 } 461 462 /* Cancel any watchdog timer */ 463 sc->sc_ethercom.ec_if.if_timer = 0; 464 } 465 466 467 /* 468 * Reset the chip 469 * Following this the software registers are reset 470 */ 471 472 static void 473 ea_chipreset(struct seeq8005_softc *sc) 474 { 475 bus_space_tag_t iot = sc->sc_iot; 476 bus_space_handle_t ioh = sc->sc_ioh; 477 478 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 479 480 /* Reset the controller. Min of 4us delay here */ 481 482 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 483 delay(4); 484 485 sc->sc_command = 0; 486 sc->sc_config1 = 0; 487 sc->sc_config2 = 0; 488 sc->sc_config3 = 0; 489 } 490 491 492 /* 493 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 494 * switching the FIFO from write to read. We also use it when changing 495 * the address for writes. 496 */ 497 static void 498 ea_await_fifo_empty(struct seeq8005_softc *sc) 499 { 500 bus_space_tag_t iot = sc->sc_iot; 501 bus_space_handle_t ioh = sc->sc_ioh; 502 int timeout; 503 504 timeout = 20000; 505 if ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 506 SEEQ_STATUS_FIFO_DIR) != 0) 507 return; /* FIFO is reading anyway. */ 508 while (--timeout > 0) 509 if (bus_space_read_2(iot, ioh, SEEQ_STATUS) & 510 SEEQ_STATUS_FIFO_EMPTY) 511 return; 512 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", sc->sc_dev.dv_xname); 513 } 514 515 /* 516 * Wait for the DMA FIFO to fill before reading from it. 517 */ 518 static void 519 ea_await_fifo_full(struct seeq8005_softc *sc) 520 { 521 bus_space_tag_t iot = sc->sc_iot; 522 bus_space_handle_t ioh = sc->sc_ioh; 523 int timeout; 524 525 timeout = 20000; 526 while (--timeout > 0) 527 if (bus_space_read_2(iot, ioh, SEEQ_STATUS) & 528 SEEQ_STATUS_FIFO_FULL) 529 return; 530 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", sc->sc_dev.dv_xname); 531 } 532 533 /* 534 * write to the buffer memory on the interface 535 * 536 * The buffer address is set to ADDR. 537 * If len != 0 then data is copied from the address starting at buf 538 * to the interface buffer. 539 * BUF must be usable as a u_int16_t *. 540 * If LEN is odd, it must be safe to overwrite one extra byte. 541 */ 542 543 static void 544 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 545 { 546 bus_space_tag_t iot = sc->sc_iot; 547 bus_space_handle_t ioh = sc->sc_ioh; 548 549 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 550 bus_space_read_2(iot, ioh, SEEQ_STATUS))); 551 552 #ifdef DIAGNOSTIC 553 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 554 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 555 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 556 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 557 #endif 558 559 /* Assume that copying too much is safe. */ 560 if (len % 2 != 0) 561 len++; 562 563 if (addr != -1) { 564 ea_await_fifo_empty(sc); 565 566 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 567 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 568 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 569 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 570 } 571 572 if (len > 0) 573 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 574 (u_int16_t *)buf, len / 2); 575 /* Leave FIFO to empty in the background */ 576 } 577 578 579 /* 580 * read from the buffer memory on the interface 581 * 582 * The buffer address is set to ADDR. 583 * If len != 0 then data is copied from the interface buffer to the 584 * address starting at buf. 585 * BUF must be usable as a u_int16_t *. 586 * If LEN is odd, it must be safe to overwrite one extra byte. 587 */ 588 589 static void 590 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 591 { 592 593 bus_space_tag_t iot = sc->sc_iot; 594 bus_space_handle_t ioh = sc->sc_ioh; 595 596 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 597 bus_space_read_2(iot, ioh, SEEQ_STATUS), addr, len)); 598 599 #ifdef DIAGNOSTIC 600 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 601 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 602 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 603 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 604 #endif 605 606 /* Assume that copying too much is safe. */ 607 if (len % 2 != 0) 608 len++; 609 610 if (addr != -1) { 611 ea_await_fifo_empty(sc); 612 613 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 614 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 615 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 616 sc->sc_command | SEEQ_CMD_FIFO_READ); 617 618 ea_await_fifo_full(sc); 619 } 620 621 if (len > 0) 622 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 623 (u_int16_t *)buf, len / 2); 624 } 625 626 static void 627 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 628 { 629 630 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 631 sc->sc_config1 | bufcode); 632 } 633 634 /* Must be called at splnet */ 635 static void 636 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 637 { 638 int i; 639 640 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 641 for (i = 0; i < ETHER_ADDR_LEN; ++i) 642 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 643 ea[i]); 644 } 645 646 /* 647 * Initialize interface. 648 * 649 * This should leave the interface in a state for packet reception and 650 * transmission. 651 */ 652 653 static int 654 ea_init(struct ifnet *ifp) 655 { 656 struct seeq8005_softc *sc = ifp->if_softc; 657 bus_space_tag_t iot = sc->sc_iot; 658 bus_space_handle_t ioh = sc->sc_ioh; 659 int s; 660 661 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 662 663 s = splnet(); 664 665 /* First, reset the board. */ 666 667 ea_chipreset(sc); 668 669 /* Set up defaults for the registers */ 670 671 sc->sc_command = 0; 672 sc->sc_config1 = 0; 673 #if BYTE_ORDER == BIG_ENDIAN 674 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 675 #else 676 sc->sc_config2 = 0; 677 #endif 678 sc->sc_config3 = 0; 679 680 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 681 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 682 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 683 if (sc->sc_variant == SEEQ_8004) { 684 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 685 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 686 } 687 688 /* Write the station address - the receiver must be off */ 689 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 690 691 /* Split board memory into Rx and Tx. */ 692 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 693 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 694 695 if (sc->sc_variant == SEEQ_8004) 696 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 697 698 /* Configure rx. */ 699 ea_mc_reset(sc); 700 if (ifp->if_flags & IFF_PROMISC) 701 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 702 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 703 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 704 else 705 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 706 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 707 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 708 709 /* Setup the Rx pointers */ 710 sc->sc_rx_ptr = sc->sc_tx_bufsize; 711 712 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 713 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 714 715 716 /* Place a NULL header at the beginning of the receive area */ 717 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 718 719 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 720 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 721 722 723 /* Configure TX. */ 724 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 725 726 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 727 728 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 729 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 730 731 /* Reset tx buffer pointers */ 732 sc->sc_tx_cur = 0; 733 sc->sc_tx_used = 0; 734 sc->sc_tx_next = 0; 735 736 /* Place a NULL header at the beginning of the transmit area */ 737 ea_writebuf(sc, NULL, 0x0000, 0); 738 739 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 740 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 741 742 sc->sc_command |= SEEQ_CMD_TX_INTEN; 743 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 744 745 /* Turn on Rx */ 746 sc->sc_command |= SEEQ_CMD_RX_INTEN; 747 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 748 sc->sc_command | SEEQ_CMD_RX_ON); 749 750 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 751 752 753 /* Set flags appropriately. */ 754 ifp->if_flags |= IFF_RUNNING; 755 ifp->if_flags &= ~IFF_OACTIVE; 756 sc->sc_enabled = 1; 757 758 /* And start output. */ 759 ea_start(ifp); 760 761 splx(s); 762 return 0; 763 } 764 765 /* 766 * Start output on interface. Get datagrams from the queue and output them, 767 * giving the receiver a chance between datagrams. Call only from splnet or 768 * interrupt level! 769 */ 770 771 static void 772 ea_start(struct ifnet *ifp) 773 { 774 struct seeq8005_softc *sc = ifp->if_softc; 775 int s; 776 777 s = splnet(); 778 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 779 780 /* 781 * Don't do anything if output is active. seeq8005intr() will call 782 * us (actually eatxpacket()) back when the card's ready for more 783 * frames. 784 */ 785 if (ifp->if_flags & IFF_OACTIVE) 786 return; 787 788 /* Mark interface as output active */ 789 790 ifp->if_flags |= IFF_OACTIVE; 791 792 /* tx packets */ 793 794 eatxpacket(sc); 795 splx(s); 796 } 797 798 799 /* 800 * Transfer a packet to the interface buffer and start transmission 801 * 802 * Called at splnet() 803 */ 804 805 void 806 eatxpacket(struct seeq8005_softc *sc) 807 { 808 bus_space_tag_t iot = sc->sc_iot; 809 bus_space_handle_t ioh = sc->sc_ioh; 810 struct mbuf *m0; 811 struct ifnet *ifp; 812 813 ifp = &sc->sc_ethercom.ec_if; 814 815 /* Dequeue the next packet. */ 816 IFQ_DEQUEUE(&ifp->if_snd, m0); 817 818 /* If there's nothing to send, return. */ 819 if (!m0) { 820 ifp->if_flags &= ~IFF_OACTIVE; 821 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 822 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 823 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 824 return; 825 } 826 827 #if NBPFILTER > 0 828 /* Give the packet to the bpf, if any. */ 829 if (ifp->if_bpf) 830 bpf_mtap(ifp->if_bpf, m0); 831 #endif 832 833 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 834 835 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 836 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 837 838 ea_writembuf(sc, m0, 0x0000); 839 m_freem(m0); 840 841 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 842 843 /* Now transmit the datagram. */ 844 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 845 sc->sc_command | SEEQ_CMD_TX_ON); 846 847 /* Make sure we notice if the chip goes silent on us. */ 848 ifp->if_timer = 5; 849 850 DPRINTF(SEEQ_DEBUG_TX, 851 ("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS))); 852 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 853 } 854 855 /* 856 * Copy a packet from an mbuf to the transmit buffer on the card. 857 * 858 * Puts a valid Tx header at the start of the packet, and a null header at 859 * the end. 860 */ 861 static int 862 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 863 { 864 struct mbuf *m; 865 int len, nextpacket; 866 u_int8_t hdr[4]; 867 868 /* 869 * Copy the datagram to the packet buffer. 870 */ 871 ea_writebuf(sc, NULL, bufstart + 4, 0); 872 873 len = 0; 874 for (m = m0; m; m = m->m_next) { 875 if (m->m_len == 0) 876 continue; 877 ea_writebuf(sc, mtod(m, caddr_t), -1, m->m_len); 878 len += m->m_len; 879 } 880 881 /* If packet size is odd round up to the next 16 bit boundry */ 882 if (len % 2) 883 ++len; 884 885 len = max(len, ETHER_MIN_LEN); 886 887 ea_writebuf(sc, NULL, bufstart + 4 + len, 0); 888 /* Follow it with a NULL packet header */ 889 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 890 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 891 892 /* Ok we now have a packet len bytes long in our packet buffer */ 893 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 894 895 /* Write the packet header */ 896 nextpacket = len + 4; 897 hdr[0] = (nextpacket >> 8) & 0xff; 898 hdr[1] = nextpacket & 0xff; 899 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 900 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 901 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 902 ea_writebuf(sc, hdr, 0x0000, 4); 903 904 return len; 905 } 906 907 /* 908 * Ethernet controller interrupt. 909 */ 910 911 int 912 seeq8005intr(void *arg) 913 { 914 struct seeq8005_softc *sc = arg; 915 bus_space_tag_t iot = sc->sc_iot; 916 bus_space_handle_t ioh = sc->sc_ioh; 917 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 918 int status, handled; 919 u_int8_t txhdr[4]; 920 u_int txstatus; 921 922 handled = 0; 923 924 /* Get the controller status */ 925 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 926 927 /* Tx interrupt ? */ 928 if (status & SEEQ_STATUS_TX_INT) { 929 handled = 1; 930 931 /* Acknowledge the interrupt */ 932 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 933 sc->sc_command | SEEQ_CMD_TX_INTACK); 934 935 ea_readbuf(sc, txhdr, 0x0000, 4); 936 937 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 938 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 939 txstatus = txhdr[3]; 940 941 /* 942 * If SEEQ_TXSTAT_COLLISION is set then we received at least 943 * one collision. On the 8004 we can find out exactly how many 944 * collisions occurred. 945 * 946 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 947 * completed. 948 * 949 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 950 * occurred and the packet transmission was aborted. 951 * This situation is untested as present. 952 * 953 * The SEEQ_TXSTAT_BABBLE should never be set and is untested 954 * as we should never xmit oversized packets. 955 */ 956 if (txstatus & SEEQ_TXSTAT_COLLISION) { 957 switch (sc->sc_variant) { 958 case SEEQ_8004: { 959 int colls; 960 961 /* 962 * The 8004 contains a 4 bit collision count 963 * in the status register. 964 */ 965 966 /* This appears to be broken on 80C04.AE */ 967 /* ifp->if_collisions += 968 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 969 & SEEQ_TXSTAT_COLLISION_MASK;*/ 970 971 /* Use the TX Collision register */ 972 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 973 colls = bus_space_read_1(iot, ioh, 974 SEEQ_BUFWIN); 975 ifp->if_collisions += colls; 976 break; 977 } 978 case SEEQ_8005: 979 /* We known there was at least 1 collision */ 980 ifp->if_collisions++; 981 break; 982 } 983 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 984 printf("seeq_intr: col16 %x\n", txstatus); 985 ifp->if_collisions += 16; 986 ifp->if_oerrors++; 987 } else if (txstatus & SEEQ_TXSTAT_BABBLE) { 988 ifp->if_oerrors++; 989 } 990 991 /* Have we completed transmission on the packet ? */ 992 if (txstatus & SEEQ_PKTSTAT_DONE) { 993 /* Clear watchdog timer. */ 994 ifp->if_timer = 0; 995 ifp->if_flags &= ~IFF_OACTIVE; 996 997 /* Update stats */ 998 ifp->if_opackets++; 999 1000 /* Tx next packet */ 1001 1002 eatxpacket(sc); 1003 } 1004 1005 } 1006 1007 1008 /* Rx interrupt ? */ 1009 if (status & SEEQ_STATUS_RX_INT) { 1010 handled = 1; 1011 1012 /* Acknowledge the interrupt */ 1013 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1014 sc->sc_command | SEEQ_CMD_RX_INTACK); 1015 1016 /* Processes the received packets */ 1017 ea_getpackets(sc); 1018 1019 1020 #if 0 1021 /* Make sure the receiver is on */ 1022 if ((status & SEEQ_STATUS_RX_ON) == 0) { 1023 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1024 sc->sc_command | SEEQ_CMD_RX_ON); 1025 printf("rxintr: rx is off st=%04x\n",status); 1026 } 1027 #endif 1028 } 1029 1030 return handled; 1031 } 1032 1033 1034 void 1035 ea_getpackets(struct seeq8005_softc *sc) 1036 { 1037 bus_space_tag_t iot = sc->sc_iot; 1038 bus_space_handle_t ioh = sc->sc_ioh; 1039 u_int addr; 1040 int len; 1041 int ctrl; 1042 int ptr; 1043 int pack; 1044 int status; 1045 u_int8_t rxhdr[4]; 1046 struct ifnet *ifp; 1047 1048 ifp = &sc->sc_ethercom.ec_if; 1049 1050 1051 /* We start from the last rx pointer position */ 1052 addr = sc->sc_rx_ptr; 1053 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1054 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1055 1056 do { 1057 /* Read rx header */ 1058 ea_readbuf(sc, rxhdr, addr, 4); 1059 1060 /* Split the packet header */ 1061 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1062 ctrl = rxhdr[2]; 1063 status = rxhdr[3]; 1064 1065 DPRINTF(SEEQ_DEBUG_RX, 1066 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1067 addr, ptr, ctrl, status)); 1068 1069 /* Zero packet ptr ? then must be null header so exit */ 1070 if (ptr == 0) break; 1071 1072 /* Sanity-check the next-packet pointer and flags. */ 1073 if (__predict_false(ptr < sc->sc_tx_bufsize || 1074 (ctrl & SEEQ_PKTCMD_TX))) { 1075 ++ifp->if_ierrors; 1076 log(LOG_ERR, 1077 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1078 sc->sc_dev.dv_xname, addr, ptr); 1079 ea_init(ifp); 1080 return; 1081 } 1082 1083 /* Get packet length */ 1084 len = (ptr - addr) - 4; 1085 1086 if (len < 0) 1087 len += sc->sc_rx_bufsize; 1088 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1089 1090 /* Has the packet rx completed ? if not then exit */ 1091 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1092 break; 1093 1094 /* 1095 * Did we have any errors? then note error and go to 1096 * next packet 1097 */ 1098 if (__predict_false(status & SEEQ_RXSTAT_ERROR_MASK)) { 1099 ++ifp->if_ierrors; 1100 /* XXX oversize packets may be OK */ 1101 log(LOG_WARNING, 1102 "%s: rx packet error at %04x (err=%02x)\n", 1103 sc->sc_dev.dv_xname, addr, status & 0x0f); 1104 goto pktdone; 1105 } 1106 /* 1107 * Is the packet too big ? - this will probably be trapped 1108 * above as a receive error. If it's not, this is indicative 1109 * of buffer corruption. 1110 */ 1111 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1112 ++ifp->if_ierrors; 1113 log(LOG_ERR, 1114 "%s: rx packet size error at %04x (len=%d)\n", 1115 sc->sc_dev.dv_xname, addr, len); 1116 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1117 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, 1118 sc->sc_config2); 1119 ea_init(ifp); 1120 return; 1121 } 1122 1123 ifp->if_ipackets++; 1124 /* Pass data up to upper levels. */ 1125 ea_read(sc, addr + 4, len); 1126 1127 pktdone: 1128 addr = ptr; 1129 ++pack; 1130 } while (len != 0); 1131 1132 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1133 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1134 1135 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1136 1137 /* Store new rx pointer */ 1138 sc->sc_rx_ptr = addr; 1139 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1140 1141 /* Make sure the receiver is on */ 1142 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1143 sc->sc_command | SEEQ_CMD_RX_ON); 1144 } 1145 1146 1147 /* 1148 * Pass a packet up to the higher levels. 1149 */ 1150 1151 static void 1152 ea_read(struct seeq8005_softc *sc, int addr, int len) 1153 { 1154 struct mbuf *m; 1155 struct ifnet *ifp; 1156 1157 ifp = &sc->sc_ethercom.ec_if; 1158 1159 /* Pull packet off interface. */ 1160 m = ea_get(sc, addr, len, ifp); 1161 if (m == 0) 1162 return; 1163 1164 #if NBPFILTER > 0 1165 /* 1166 * Check if there's a BPF listener on this interface. 1167 * If so, hand off the raw packet to bpf. 1168 */ 1169 if (ifp->if_bpf) 1170 bpf_mtap(ifp->if_bpf, m); 1171 #endif 1172 1173 (*ifp->if_input)(ifp, m); 1174 } 1175 1176 /* 1177 * Pull read data off a interface. Len is length of data, with local net 1178 * header stripped. We copy the data into mbufs. When full cluster sized 1179 * units are present we copy into clusters. 1180 */ 1181 1182 struct mbuf * 1183 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1184 { 1185 struct mbuf *top, **mp, *m; 1186 int len; 1187 u_int cp, epkt; 1188 1189 cp = addr; 1190 epkt = cp + totlen; 1191 1192 MGETHDR(m, M_DONTWAIT, MT_DATA); 1193 if (m == 0) 1194 return 0; 1195 m->m_pkthdr.rcvif = ifp; 1196 m->m_pkthdr.len = totlen; 1197 m->m_len = MHLEN; 1198 top = 0; 1199 mp = ⊤ 1200 1201 while (totlen > 0) { 1202 if (top) { 1203 MGET(m, M_DONTWAIT, MT_DATA); 1204 if (m == 0) { 1205 m_freem(top); 1206 return 0; 1207 } 1208 m->m_len = MLEN; 1209 } 1210 len = min(totlen, epkt - cp); 1211 if (len >= MINCLSIZE) { 1212 MCLGET(m, M_DONTWAIT); 1213 if (m->m_flags & M_EXT) 1214 m->m_len = len = min(len, MCLBYTES); 1215 else 1216 len = m->m_len; 1217 } else { 1218 /* 1219 * Place initial small packet/header at end of mbuf. 1220 */ 1221 if (len < m->m_len) { 1222 if (top == 0 && len + max_linkhdr <= m->m_len) 1223 m->m_data += max_linkhdr; 1224 m->m_len = len; 1225 } else 1226 len = m->m_len; 1227 } 1228 if (top == 0) { 1229 /* Make sure the payload is aligned */ 1230 caddr_t newdata = (caddr_t) 1231 ALIGN(m->m_data + sizeof(struct ether_header)) - 1232 sizeof(struct ether_header); 1233 len -= newdata - m->m_data; 1234 m->m_len = len; 1235 m->m_data = newdata; 1236 } 1237 ea_readbuf(sc, mtod(m, u_char *), 1238 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1239 len); 1240 cp += len; 1241 *mp = m; 1242 mp = &m->m_next; 1243 totlen -= len; 1244 if (cp == epkt) 1245 cp = addr; 1246 } 1247 1248 return top; 1249 } 1250 1251 /* 1252 * Process an ioctl request. Mostly boilerplate. 1253 */ 1254 static int 1255 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1256 { 1257 struct seeq8005_softc *sc = ifp->if_softc; 1258 int s, error = 0; 1259 1260 s = splnet(); 1261 switch (cmd) { 1262 1263 default: 1264 error = ether_ioctl(ifp, cmd, data); 1265 if (error == ENETRESET) { 1266 /* 1267 * Multicast list has changed; set the hardware filter 1268 * accordingly. 1269 */ 1270 ea_mc_reset(sc); 1271 error = 0; 1272 } 1273 break; 1274 } 1275 1276 splx(s); 1277 return error; 1278 } 1279 1280 /* Must be called at splnet() */ 1281 1282 static void 1283 ea_mc_reset(struct seeq8005_softc *sc) 1284 { 1285 1286 switch (sc->sc_variant) { 1287 case SEEQ_8004: 1288 ea_mc_reset_8004(sc); 1289 return; 1290 case SEEQ_8005: 1291 ea_mc_reset_8005(sc); 1292 return; 1293 } 1294 } 1295 1296 static void 1297 ea_mc_reset_8004(struct seeq8005_softc *sc) 1298 { 1299 struct ethercom *ec = &sc->sc_ethercom; 1300 struct ifnet *ifp = &ec->ec_if; 1301 struct ether_multi *enm; 1302 u_int8_t *cp, c; 1303 u_int32_t crc; 1304 int i, len; 1305 struct ether_multistep step; 1306 u_int8_t af[8]; 1307 1308 /* 1309 * Set up multicast address filter by passing all multicast addresses 1310 * through a crc generator, and then using bits 2 - 7 as an index 1311 * into the 64 bit logical address filter. The high order bits 1312 * selects the word, while the rest of the bits select the bit within 1313 * the word. 1314 */ 1315 1316 if (ifp->if_flags & IFF_PROMISC) { 1317 ifp->if_flags |= IFF_ALLMULTI; 1318 for (i = 0; i < 8; i++) 1319 af[i] = 0xff; 1320 return; 1321 } 1322 for (i = 0; i < 8; i++) 1323 af[i] = 0; 1324 ETHER_FIRST_MULTI(step, ec, enm); 1325 while (enm != NULL) { 1326 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1327 sizeof(enm->enm_addrlo)) != 0) { 1328 /* 1329 * We must listen to a range of multicast addresses. 1330 * For now, just accept all multicasts, rather than 1331 * trying to set only those filter bits needed to match 1332 * the range. (At this time, the only use of address 1333 * ranges is for IP multicast routing, for which the 1334 * range is big enough to require all bits set.) 1335 */ 1336 ifp->if_flags |= IFF_ALLMULTI; 1337 for (i = 0; i < 8; i++) 1338 af[i] = 0xff; 1339 break; 1340 } 1341 cp = enm->enm_addrlo; 1342 crc = 0xffffffff; 1343 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1344 c = *cp++; 1345 for (i = 8; --i >= 0;) { 1346 if (((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01)) { 1347 crc <<= 1; 1348 crc ^= 0x04c11db6 | 1; 1349 } else 1350 crc <<= 1; 1351 c >>= 1; 1352 } 1353 } 1354 /* Just want the 6 most significant bits. */ 1355 crc = (crc >> 2) & 0x3f; 1356 1357 /* Turn on the corresponding bit in the filter. */ 1358 af[crc >> 3] |= 1 << (crc & 0x7); 1359 1360 ETHER_NEXT_MULTI(step, enm); 1361 } 1362 ifp->if_flags &= ~IFF_ALLMULTI; 1363 1364 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1365 for (i = 0; i < 8; ++i) 1366 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1367 SEEQ_BUFWIN, af[i]); 1368 } 1369 1370 static void 1371 ea_mc_reset_8005(struct seeq8005_softc *sc) 1372 { 1373 struct ether_multi *enm; 1374 struct ether_multistep step; 1375 int naddr, maxaddrs; 1376 1377 naddr = 0; 1378 maxaddrs = 5; 1379 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1380 while (enm != NULL) { 1381 /* Have we got space? */ 1382 if (naddr >= maxaddrs || 1383 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1384 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1385 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1386 return; 1387 } 1388 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1389 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1390 naddr++; 1391 ETHER_NEXT_MULTI(step, enm); 1392 } 1393 for (; naddr < maxaddrs; naddr++) 1394 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1395 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1396 sc->sc_config1); 1397 } 1398 1399 /* 1400 * Device timeout routine. 1401 */ 1402 1403 static void 1404 ea_watchdog(struct ifnet *ifp) 1405 { 1406 struct seeq8005_softc *sc = ifp->if_softc; 1407 1408 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1409 sc->sc_dev.dv_xname, 1410 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1411 ifp->if_oerrors++; 1412 1413 /* Kick the interface */ 1414 1415 ea_init(ifp); 1416 1417 ifp->if_timer = 0; 1418 } 1419 1420 /* End of if_ea.c */ 1421
Indexes created Mon Sep 29 21:09:56 GMT 2025