seeq8005.c revision 1.20
1 /* $NetBSD: seeq8005.c,v 1.20 2001/04/02 22:25:17 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chip: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45 /* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52 /* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56 /* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63 #include "opt_inet.h" 64 #include "opt_ns.h" 65 66 #include <sys/types.h> 67 #include <sys/param.h> 68 69 __RCSID("$NetBSD: seeq8005.c,v 1.20 2001/04/02 22:25:17 bjh21 Exp $"); 70 71 #include <sys/systm.h> 72 #include <sys/endian.h> 73 #include <sys/errno.h> 74 #include <sys/ioctl.h> 75 #include <sys/mbuf.h> 76 #include <sys/socket.h> 77 #include <sys/syslog.h> 78 #include <sys/device.h> 79 80 #include <net/if.h> 81 #include <net/if_dl.h> 82 #include <net/if_types.h> 83 #include <net/if_ether.h> 84 #include <net/if_media.h> 85 86 #ifdef INET 87 #include <netinet/in.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/in_var.h> 90 #include <netinet/ip.h> 91 #include <netinet/if_inarp.h> 92 #endif 93 94 #ifdef NS 95 #include <netns/ns.h> 96 #include <netns/ns_if.h> 97 #endif 98 99 #include "bpfilter.h" 100 #if NBPFILTER > 0 101 #include <net/bpf.h> 102 #include <net/bpfdesc.h> 103 #endif 104 105 #include <machine/bus.h> 106 #include <machine/intr.h> 107 108 #include <dev/ic/seeq8005reg.h> 109 #include <dev/ic/seeq8005var.h> 110 111 /*#define SEEQ_DEBUG*/ 112 113 /* for debugging convenience */ 114 #ifdef SEEQ8005_DEBUG 115 #define SEEQ_DEBUG_MISC 1 116 #define SEEQ_DEBUG_TX 2 117 #define SEEQ_DEBUG_RX 4 118 #define SEEQ_DEBUG_PKT 8 119 #define SEEQ_DEBUG_TXINT 16 120 #define SEEQ_DEBUG_RXINT 32 121 int seeq8005_debug = 0; 122 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 123 #else 124 #define DPRINTF(f, x) 125 #endif 126 127 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> MAX_ETHER_LEN) */ 128 129 /* 130 * prototypes 131 */ 132 133 static int ea_init(struct ifnet *); 134 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 135 static void ea_start(struct ifnet *); 136 static void ea_watchdog(struct ifnet *); 137 static void ea_chipreset(struct seeq8005_softc *); 138 static void ea_ramtest(struct seeq8005_softc *); 139 static int ea_stoptx(struct seeq8005_softc *); 140 static int ea_stoprx(struct seeq8005_softc *); 141 static void ea_stop(struct ifnet *, int); 142 static void ea_await_fifo_empty(struct seeq8005_softc *); 143 static void ea_await_fifo_full(struct seeq8005_softc *); 144 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 145 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 146 static void ea_select_buffer(struct seeq8005_softc *, int); 147 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 148 static void ea_read(struct seeq8005_softc *, int, int); 149 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 150 static void ea_txint(struct seeq8005_softc *); 151 static void ea_rxint(struct seeq8005_softc *); 152 static void eatxpacket(struct seeq8005_softc *); 153 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 154 static void ea_mc_reset(struct seeq8005_softc *); 155 static void ea_mc_reset_8004(struct seeq8005_softc *); 156 static void ea_mc_reset_8005(struct seeq8005_softc *); 157 static int ea_mediachange(struct ifnet *); 158 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 159 160 161 /* 162 * Attach chip. 163 */ 164 165 void 166 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 167 int nmedia, int defmedia) 168 { 169 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 170 u_int id; 171 172 KASSERT(myaddr != NULL); 173 printf(" address %s", ether_sprintf(myaddr)); 174 175 /* Stop the board. */ 176 177 ea_chipreset(sc); 178 179 /* Get the product ID */ 180 181 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 182 id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 183 184 switch (id & SEEQ_PRODUCTID_MASK) { 185 case SEEQ_PRODUCTID_8004: 186 sc->sc_variant = SEEQ_8004; 187 switch (id & SEEQ_PRODUCTID_REV_MASK) { 188 case SEEQ_PRODUCTID_REV_80C04: 189 printf(", SEEQ 80C04\n"); 190 break; 191 case SEEQ_PRODUCTID_REV_80C04A: 192 printf(", SEEQ 80C04A\n"); 193 break; 194 default: 195 /* Unknown SEEQ 8004 variants */ 196 printf(", SEEQ 8004 rev %x\n", 197 id & SEEQ_PRODUCTID_REV_MASK); 198 break; 199 } 200 break; 201 default: /* XXX */ 202 sc->sc_variant = SEEQ_8005; 203 printf(", SEEQ 8005\n"); 204 break; 205 } 206 207 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 208 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 209 210 /* 211 * Set up tx and rx buffers. 212 * 213 * We use approximately a quarter of the packet memory for TX 214 * buffers and the rest for RX buffers 215 */ 216 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 217 sc->sc_tx_bufs = 1; 218 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 219 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 220 sc->sc_enabled = 0; 221 222 /* Test the RAM */ 223 ea_ramtest(sc); 224 225 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 226 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 227 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 228 229 /* Initialise ifnet structure. */ 230 231 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 232 ifp->if_softc = sc; 233 ifp->if_start = ea_start; 234 ifp->if_ioctl = ea_ioctl; 235 ifp->if_init = ea_init; 236 ifp->if_stop = ea_stop; 237 ifp->if_watchdog = ea_watchdog; 238 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 239 if (sc->sc_variant == SEEQ_8004) 240 ifp->if_flags |= IFF_SIMPLEX; 241 IFQ_SET_READY(&ifp->if_snd); 242 243 /* Initialize media goo. */ 244 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 245 if (media != NULL) { 246 int i; 247 248 for (i = 0; i < nmedia; i++) 249 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 250 ifmedia_set(&sc->sc_media, defmedia); 251 } else { 252 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 253 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 254 } 255 256 /* Now we can attach the interface. */ 257 258 if_attach(ifp); 259 ether_ifattach(ifp, myaddr); 260 261 printf("\n"); 262 } 263 264 /* 265 * Media change callback. 266 */ 267 static int 268 ea_mediachange(struct ifnet *ifp) 269 { 270 struct seeq8005_softc *sc = ifp->if_softc; 271 272 if (sc->sc_mediachange) 273 return ((*sc->sc_mediachange)(sc)); 274 return (EINVAL); 275 } 276 277 /* 278 * Media status callback. 279 */ 280 static void 281 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 282 { 283 struct seeq8005_softc *sc = ifp->if_softc; 284 285 if (sc->sc_enabled == 0) { 286 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 287 ifmr->ifm_status = 0; 288 return; 289 } 290 291 if (sc->sc_mediastatus) 292 (*sc->sc_mediastatus)(sc, ifmr); 293 } 294 295 /* 296 * Test the RAM on the ethernet card. 297 */ 298 299 void 300 ea_ramtest(struct seeq8005_softc *sc) 301 { 302 bus_space_tag_t iot = sc->sc_iot; 303 bus_space_handle_t ioh = sc->sc_ioh; 304 int loop; 305 u_int sum = 0; 306 307 /* 308 * Test the buffer memory on the board. 309 * Write simple pattens to it and read them back. 310 */ 311 312 /* Set up the whole buffer RAM for writing */ 313 314 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 315 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 316 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 317 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 318 319 #define SEEQ_RAMTEST_LOOP(value) \ 320 do { \ 321 /* Set the write start address and write a pattern */ \ 322 ea_writebuf(sc, NULL, 0x0000, 0); \ 323 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 324 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (value)); \ 325 \ 326 /* Set the read start address and verify the pattern */ \ 327 ea_readbuf(sc, NULL, 0x0000, 0); \ 328 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 329 if (bus_space_read_2(iot, ioh, SEEQ_BUFWIN) != (value)) \ 330 ++sum; \ 331 } while (/*CONSTCOND*/0) 332 333 SEEQ_RAMTEST_LOOP(loop); 334 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 335 SEEQ_RAMTEST_LOOP(0xaa55); 336 SEEQ_RAMTEST_LOOP(0x55aa); 337 338 /* Report */ 339 340 if (sum > 0) 341 printf("%s: buffer RAM failed self test, %d faults\n", 342 sc->sc_dev.dv_xname, sum); 343 } 344 345 346 /* 347 * Stop the tx interface. 348 * 349 * Returns 0 if the tx was already stopped or 1 if it was active 350 */ 351 352 static int 353 ea_stoptx(struct seeq8005_softc *sc) 354 { 355 bus_space_tag_t iot = sc->sc_iot; 356 bus_space_handle_t ioh = sc->sc_ioh; 357 int timeout; 358 int status; 359 360 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 361 362 sc->sc_enabled = 0; 363 364 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 365 if (!(status & SEEQ_STATUS_TX_ON)) 366 return 0; 367 368 /* Stop any tx and wait for confirmation */ 369 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 370 sc->sc_command | SEEQ_CMD_TX_OFF); 371 372 timeout = 20000; 373 do { 374 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 375 delay(1); 376 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 377 if (timeout == 0) 378 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 379 sc->sc_dev.dv_xname); 380 381 /* Clear any pending tx interrupt */ 382 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 383 sc->sc_command | SEEQ_CMD_TX_INTACK); 384 return 1; 385 } 386 387 388 /* 389 * Stop the rx interface. 390 * 391 * Returns 0 if the tx was already stopped or 1 if it was active 392 */ 393 394 static int 395 ea_stoprx(struct seeq8005_softc *sc) 396 { 397 bus_space_tag_t iot = sc->sc_iot; 398 bus_space_handle_t ioh = sc->sc_ioh; 399 int timeout; 400 int status; 401 402 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 403 404 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 405 if (!(status & SEEQ_STATUS_RX_ON)) 406 return 0; 407 408 /* Stop any rx and wait for confirmation */ 409 410 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 411 sc->sc_command | SEEQ_CMD_RX_OFF); 412 413 timeout = 20000; 414 do { 415 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 416 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 417 if (timeout == 0) 418 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 419 sc->sc_dev.dv_xname); 420 421 /* Clear any pending rx interrupt */ 422 423 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 424 sc->sc_command | SEEQ_CMD_RX_INTACK); 425 return 1; 426 } 427 428 429 /* 430 * Stop interface. 431 * Stop all IO and shut the interface down 432 */ 433 434 static void 435 ea_stop(struct ifnet *ifp, int disable) 436 { 437 struct seeq8005_softc *sc = ifp->if_softc; 438 bus_space_tag_t iot = sc->sc_iot; 439 bus_space_handle_t ioh = sc->sc_ioh; 440 441 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 442 443 /* Stop all IO */ 444 ea_stoptx(sc); 445 ea_stoprx(sc); 446 447 /* Disable rx and tx interrupts */ 448 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 449 450 /* Clear any pending interrupts */ 451 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 452 sc->sc_command | SEEQ_CMD_RX_INTACK | 453 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 454 SEEQ_CMD_BW_INTACK); 455 456 if (sc->sc_variant == SEEQ_8004) { 457 /* Put the chip to sleep */ 458 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 459 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 460 sc->sc_config3 | SEEQ_CFG3_SLEEP); 461 } 462 463 /* Cancel any watchdog timer */ 464 sc->sc_ethercom.ec_if.if_timer = 0; 465 } 466 467 468 /* 469 * Reset the chip 470 * Following this the software registers are reset 471 */ 472 473 static void 474 ea_chipreset(struct seeq8005_softc *sc) 475 { 476 bus_space_tag_t iot = sc->sc_iot; 477 bus_space_handle_t ioh = sc->sc_ioh; 478 479 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 480 481 /* Reset the controller. Min of 4us delay here */ 482 483 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 484 delay(4); 485 486 sc->sc_command = 0; 487 sc->sc_config1 = 0; 488 sc->sc_config2 = 0; 489 sc->sc_config3 = 0; 490 } 491 492 493 /* 494 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 495 * switching the FIFO from write to read. We also use it when changing 496 * the address for writes. 497 */ 498 static void 499 ea_await_fifo_empty(struct seeq8005_softc *sc) 500 { 501 bus_space_tag_t iot = sc->sc_iot; 502 bus_space_handle_t ioh = sc->sc_ioh; 503 int timeout; 504 505 timeout = 20000; 506 if ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 507 SEEQ_STATUS_FIFO_DIR) != 0) 508 return; /* FIFO is reading anyway. */ 509 while (--timeout > 0) 510 if (bus_space_read_2(iot, ioh, SEEQ_STATUS) & 511 SEEQ_STATUS_FIFO_EMPTY) 512 return; 513 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", sc->sc_dev.dv_xname); 514 } 515 516 /* 517 * Wait for the DMA FIFO to fill before reading from it. 518 */ 519 static void 520 ea_await_fifo_full(struct seeq8005_softc *sc) 521 { 522 bus_space_tag_t iot = sc->sc_iot; 523 bus_space_handle_t ioh = sc->sc_ioh; 524 int timeout; 525 526 timeout = 20000; 527 while (--timeout > 0) 528 if (bus_space_read_2(iot, ioh, SEEQ_STATUS) & 529 SEEQ_STATUS_FIFO_FULL) 530 return; 531 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", sc->sc_dev.dv_xname); 532 } 533 534 /* 535 * write to the buffer memory on the interface 536 * 537 * The buffer address is set to ADDR. 538 * If len != 0 then data is copied from the address starting at buf 539 * to the interface buffer. 540 * BUF must be usable as a u_int16_t *. 541 * If LEN is odd, it must be safe to overwrite one extra byte. 542 */ 543 544 static void 545 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 546 { 547 bus_space_tag_t iot = sc->sc_iot; 548 bus_space_handle_t ioh = sc->sc_ioh; 549 550 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 551 bus_space_read_2(iot, ioh, SEEQ_STATUS))); 552 553 #ifdef DIAGNOSTIC 554 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 555 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 556 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 557 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 558 #endif 559 560 /* Assume that copying too much is safe. */ 561 if (len % 2 != 0) 562 len++; 563 564 if (addr != -1) { 565 ea_await_fifo_empty(sc); 566 567 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 568 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 569 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 570 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 571 } 572 573 if (len > 0) 574 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 575 (u_int16_t *)buf, len / 2); 576 /* Leave FIFO to empty in the background */ 577 } 578 579 580 /* 581 * read from the buffer memory on the interface 582 * 583 * The buffer address is set to ADDR. 584 * If len != 0 then data is copied from the interface buffer to the 585 * address starting at buf. 586 * BUF must be usable as a u_int16_t *. 587 * If LEN is odd, it must be safe to overwrite one extra byte. 588 */ 589 590 static void 591 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 592 { 593 bus_space_tag_t iot = sc->sc_iot; 594 bus_space_handle_t ioh = sc->sc_ioh; 595 int runup; 596 597 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 598 bus_space_read_2(iot, ioh, SEEQ_STATUS), addr, len)); 599 600 #ifdef DIAGNOSTIC 601 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 602 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 603 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 604 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 605 #endif 606 607 /* Assume that copying too much is safe. */ 608 if (len % 2 != 0) 609 len++; 610 611 if (addr != -1) { 612 /* 613 * SEEQ 80C04 bug: 614 * Starting reading from certain addresses seems to cause 615 * us to get bogus results, so we avoid them. 616 */ 617 runup = 0; 618 if (sc->sc_variant == SEEQ_8004 && 619 ((addr & 0x00ff) == 0x00ea || 620 (addr & 0x00ff) == 0x00ee || 621 (addr & 0x00ff) == 0x00f0)) 622 runup = (addr & 0x00ff) - 0x00e8; 623 624 ea_await_fifo_empty(sc); 625 626 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 627 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr - runup); 628 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 629 sc->sc_command | SEEQ_CMD_FIFO_READ); 630 631 ea_await_fifo_full(sc); 632 while (runup > 0) { 633 (void)bus_space_read_2(iot, ioh, SEEQ_BUFWIN); 634 runup -= 2; 635 } 636 } 637 638 if (len > 0) 639 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 640 (u_int16_t *)buf, len / 2); 641 } 642 643 static void 644 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 645 { 646 647 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 648 sc->sc_config1 | bufcode); 649 } 650 651 /* Must be called at splnet */ 652 static void 653 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 654 { 655 int i; 656 657 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 658 for (i = 0; i < ETHER_ADDR_LEN; ++i) 659 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 660 ea[i]); 661 } 662 663 /* 664 * Initialize interface. 665 * 666 * This should leave the interface in a state for packet reception and 667 * transmission. 668 */ 669 670 static int 671 ea_init(struct ifnet *ifp) 672 { 673 struct seeq8005_softc *sc = ifp->if_softc; 674 bus_space_tag_t iot = sc->sc_iot; 675 bus_space_handle_t ioh = sc->sc_ioh; 676 int s; 677 678 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 679 680 s = splnet(); 681 682 /* First, reset the board. */ 683 684 ea_chipreset(sc); 685 686 /* Set up defaults for the registers */ 687 688 sc->sc_command = 0; 689 sc->sc_config1 = 0; 690 #if BYTE_ORDER == BIG_ENDIAN 691 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 692 #else 693 sc->sc_config2 = 0; 694 #endif 695 sc->sc_config3 = 0; 696 697 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 698 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 699 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 700 if (sc->sc_variant == SEEQ_8004) { 701 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 702 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 703 } 704 705 /* Write the station address - the receiver must be off */ 706 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 707 708 /* Split board memory into Rx and Tx. */ 709 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 710 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 711 712 if (sc->sc_variant == SEEQ_8004) 713 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 714 715 /* Configure rx. */ 716 ea_mc_reset(sc); 717 if (ifp->if_flags & IFF_PROMISC) 718 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 719 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 720 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 721 else 722 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 723 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 724 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 725 726 /* Setup the Rx pointers */ 727 sc->sc_rx_ptr = sc->sc_tx_bufsize; 728 729 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 730 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 731 732 733 /* Place a NULL header at the beginning of the receive area */ 734 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 735 736 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 737 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 738 739 740 /* Configure TX. */ 741 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 742 743 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 744 745 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 746 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 747 748 /* Reset tx buffer pointers */ 749 sc->sc_tx_cur = 0; 750 sc->sc_tx_used = 0; 751 sc->sc_tx_next = 0; 752 753 /* Place a NULL header at the beginning of the transmit area */ 754 ea_writebuf(sc, NULL, 0x0000, 0); 755 756 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 757 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 758 759 sc->sc_command |= SEEQ_CMD_TX_INTEN; 760 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 761 762 /* Turn on Rx */ 763 sc->sc_command |= SEEQ_CMD_RX_INTEN; 764 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 765 sc->sc_command | SEEQ_CMD_RX_ON); 766 767 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 768 769 770 /* Set flags appropriately. */ 771 ifp->if_flags |= IFF_RUNNING; 772 ifp->if_flags &= ~IFF_OACTIVE; 773 sc->sc_enabled = 1; 774 775 /* And start output. */ 776 ea_start(ifp); 777 778 splx(s); 779 return 0; 780 } 781 782 /* 783 * Start output on interface. Get datagrams from the queue and output them, 784 * giving the receiver a chance between datagrams. Call only from splnet or 785 * interrupt level! 786 */ 787 788 static void 789 ea_start(struct ifnet *ifp) 790 { 791 struct seeq8005_softc *sc = ifp->if_softc; 792 int s; 793 794 s = splnet(); 795 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 796 797 /* 798 * Don't do anything if output is active. seeq8005intr() will call 799 * us (actually eatxpacket()) back when the card's ready for more 800 * frames. 801 */ 802 if (ifp->if_flags & IFF_OACTIVE) 803 return; 804 805 /* Mark interface as output active */ 806 807 ifp->if_flags |= IFF_OACTIVE; 808 809 /* tx packets */ 810 811 eatxpacket(sc); 812 splx(s); 813 } 814 815 816 /* 817 * Transfer a packet to the interface buffer and start transmission 818 * 819 * Called at splnet() 820 */ 821 822 void 823 eatxpacket(struct seeq8005_softc *sc) 824 { 825 bus_space_tag_t iot = sc->sc_iot; 826 bus_space_handle_t ioh = sc->sc_ioh; 827 struct mbuf *m0; 828 struct ifnet *ifp; 829 830 ifp = &sc->sc_ethercom.ec_if; 831 832 /* Dequeue the next packet. */ 833 IFQ_DEQUEUE(&ifp->if_snd, m0); 834 835 /* If there's nothing to send, return. */ 836 if (!m0) { 837 ifp->if_flags &= ~IFF_OACTIVE; 838 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 839 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 840 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 841 return; 842 } 843 844 #if NBPFILTER > 0 845 /* Give the packet to the bpf, if any. */ 846 if (ifp->if_bpf) 847 bpf_mtap(ifp->if_bpf, m0); 848 #endif 849 850 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 851 852 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 853 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 854 855 ea_writembuf(sc, m0, 0x0000); 856 m_freem(m0); 857 858 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 859 860 /* Now transmit the datagram. */ 861 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 862 sc->sc_command | SEEQ_CMD_TX_ON); 863 864 /* Make sure we notice if the chip goes silent on us. */ 865 ifp->if_timer = 5; 866 867 DPRINTF(SEEQ_DEBUG_TX, 868 ("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS))); 869 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 870 } 871 872 /* 873 * Copy a packet from an mbuf to the transmit buffer on the card. 874 * 875 * Puts a valid Tx header at the start of the packet, and a null header at 876 * the end. 877 */ 878 static int 879 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 880 { 881 struct mbuf *m; 882 int len, nextpacket; 883 u_int8_t hdr[4]; 884 885 /* 886 * Copy the datagram to the packet buffer. 887 */ 888 ea_writebuf(sc, NULL, bufstart + 4, 0); 889 890 len = 0; 891 for (m = m0; m; m = m->m_next) { 892 if (m->m_len == 0) 893 continue; 894 ea_writebuf(sc, mtod(m, caddr_t), -1, m->m_len); 895 len += m->m_len; 896 } 897 898 /* If packet size is odd round up to the next 16 bit boundry */ 899 if (len % 2) 900 ++len; 901 902 len = max(len, ETHER_MIN_LEN); 903 904 ea_writebuf(sc, NULL, bufstart + 4 + len, 0); 905 /* Follow it with a NULL packet header */ 906 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 907 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 908 909 /* Ok we now have a packet len bytes long in our packet buffer */ 910 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 911 912 /* Write the packet header */ 913 nextpacket = len + 4; 914 hdr[0] = (nextpacket >> 8) & 0xff; 915 hdr[1] = nextpacket & 0xff; 916 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 917 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 918 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 919 ea_writebuf(sc, hdr, 0x0000, 4); 920 921 return len; 922 } 923 924 /* 925 * Ethernet controller interrupt. 926 */ 927 928 int 929 seeq8005intr(void *arg) 930 { 931 struct seeq8005_softc *sc = arg; 932 bus_space_tag_t iot = sc->sc_iot; 933 bus_space_handle_t ioh = sc->sc_ioh; 934 int status, handled; 935 936 handled = 0; 937 938 /* Get the controller status */ 939 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 940 941 /* Tx interrupt ? */ 942 if (status & SEEQ_STATUS_TX_INT) { 943 handled = 1; 944 945 /* Acknowledge the interrupt */ 946 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 947 sc->sc_command | SEEQ_CMD_TX_INTACK); 948 949 ea_txint(sc); 950 } 951 952 953 /* Rx interrupt ? */ 954 if (status & SEEQ_STATUS_RX_INT) { 955 handled = 1; 956 957 /* Acknowledge the interrupt */ 958 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 959 sc->sc_command | SEEQ_CMD_RX_INTACK); 960 961 /* Processes the received packets */ 962 ea_rxint(sc); 963 } 964 965 return handled; 966 } 967 968 static void 969 ea_txint(struct seeq8005_softc *sc) 970 { 971 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 972 bus_space_tag_t iot = sc->sc_iot; 973 bus_space_handle_t ioh = sc->sc_ioh; 974 u_int8_t txhdr[4]; 975 u_int txstatus; 976 977 ea_readbuf(sc, txhdr, 0x0000, 4); 978 979 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 980 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 981 txstatus = txhdr[3]; 982 983 /* 984 * If SEEQ_TXSTAT_COLLISION is set then we received at least 985 * one collision. On the 8004 we can find out exactly how many 986 * collisions occurred. 987 * 988 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 989 * completed. 990 * 991 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 992 * occurred and the packet transmission was aborted. 993 * This situation is untested as present. 994 * 995 * The SEEQ_TXSTAT_BABBLE should never be set and is untested 996 * as we should never xmit oversized packets. 997 */ 998 if (txstatus & SEEQ_TXSTAT_COLLISION) { 999 switch (sc->sc_variant) { 1000 case SEEQ_8004: { 1001 int colls; 1002 1003 /* 1004 * The 8004 contains a 4 bit collision count 1005 * in the status register. 1006 */ 1007 1008 /* This appears to be broken on 80C04.AE */ 1009 /* ifp->if_collisions += 1010 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1011 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1012 1013 /* Use the TX Collision register */ 1014 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1015 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1016 ifp->if_collisions += colls; 1017 break; 1018 } 1019 case SEEQ_8005: 1020 /* We known there was at least 1 collision */ 1021 ifp->if_collisions++; 1022 break; 1023 } 1024 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1025 printf("seeq_intr: col16 %x\n", txstatus); 1026 ifp->if_collisions += 16; 1027 ifp->if_oerrors++; 1028 } else if (txstatus & SEEQ_TXSTAT_BABBLE) { 1029 ifp->if_oerrors++; 1030 } 1031 1032 /* Have we completed transmission on the packet ? */ 1033 if (txstatus & SEEQ_PKTSTAT_DONE) { 1034 /* Clear watchdog timer. */ 1035 ifp->if_timer = 0; 1036 ifp->if_flags &= ~IFF_OACTIVE; 1037 1038 /* Update stats */ 1039 ifp->if_opackets++; 1040 1041 /* Tx next packet */ 1042 1043 eatxpacket(sc); 1044 } 1045 } 1046 1047 void 1048 ea_rxint(struct seeq8005_softc *sc) 1049 { 1050 bus_space_tag_t iot = sc->sc_iot; 1051 bus_space_handle_t ioh = sc->sc_ioh; 1052 u_int addr; 1053 int len; 1054 int ctrl; 1055 int ptr; 1056 int pack; 1057 int status; 1058 u_int8_t rxhdr[4]; 1059 struct ifnet *ifp; 1060 1061 ifp = &sc->sc_ethercom.ec_if; 1062 1063 1064 /* We start from the last rx pointer position */ 1065 addr = sc->sc_rx_ptr; 1066 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1067 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1068 1069 do { 1070 /* Read rx header */ 1071 ea_readbuf(sc, rxhdr, addr, 4); 1072 1073 /* Split the packet header */ 1074 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1075 ctrl = rxhdr[2]; 1076 status = rxhdr[3]; 1077 1078 DPRINTF(SEEQ_DEBUG_RX, 1079 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1080 addr, ptr, ctrl, status)); 1081 1082 /* Zero packet ptr ? then must be null header so exit */ 1083 if (ptr == 0) break; 1084 1085 /* Sanity-check the next-packet pointer and flags. */ 1086 if (__predict_false(ptr < sc->sc_tx_bufsize || 1087 (ctrl & SEEQ_PKTCMD_TX))) { 1088 ++ifp->if_ierrors; 1089 log(LOG_ERR, 1090 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1091 sc->sc_dev.dv_xname, addr, ptr); 1092 ea_init(ifp); 1093 return; 1094 } 1095 1096 /* Get packet length */ 1097 len = (ptr - addr) - 4; 1098 1099 if (len < 0) 1100 len += sc->sc_rx_bufsize; 1101 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1102 1103 /* Has the packet rx completed ? if not then exit */ 1104 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1105 break; 1106 1107 /* 1108 * Did we have any errors? then note error and go to 1109 * next packet 1110 */ 1111 if (__predict_false(status & SEEQ_RXSTAT_ERROR_MASK)) { 1112 ++ifp->if_ierrors; 1113 /* XXX oversize packets may be OK */ 1114 log(LOG_WARNING, 1115 "%s: rx packet error at %04x (err=%02x)\n", 1116 sc->sc_dev.dv_xname, addr, status & 0x0f); 1117 /* XXX shouldn't need to reset if it's genuine. */ 1118 ea_init(ifp); 1119 return; 1120 } 1121 /* 1122 * Is the packet too big ? - this will probably be trapped 1123 * above as a receive error. If it's not, this is indicative 1124 * of buffer corruption. 1125 */ 1126 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1127 ++ifp->if_ierrors; 1128 log(LOG_ERR, 1129 "%s: rx packet size error at %04x (len=%d)\n", 1130 sc->sc_dev.dv_xname, addr, len); 1131 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1132 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, 1133 sc->sc_config2); 1134 ea_init(ifp); 1135 return; 1136 } 1137 1138 ifp->if_ipackets++; 1139 /* Pass data up to upper levels. */ 1140 ea_read(sc, addr + 4, len); 1141 1142 addr = ptr; 1143 ++pack; 1144 } while (len != 0); 1145 1146 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1147 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1148 1149 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1150 1151 /* Store new rx pointer */ 1152 sc->sc_rx_ptr = addr; 1153 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1154 1155 /* Make sure the receiver is on */ 1156 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1157 sc->sc_command | SEEQ_CMD_RX_ON); 1158 } 1159 1160 1161 /* 1162 * Pass a packet up to the higher levels. 1163 */ 1164 1165 static void 1166 ea_read(struct seeq8005_softc *sc, int addr, int len) 1167 { 1168 struct mbuf *m; 1169 struct ifnet *ifp; 1170 1171 ifp = &sc->sc_ethercom.ec_if; 1172 1173 /* Pull packet off interface. */ 1174 m = ea_get(sc, addr, len, ifp); 1175 if (m == 0) 1176 return; 1177 1178 #if NBPFILTER > 0 1179 /* 1180 * Check if there's a BPF listener on this interface. 1181 * If so, hand off the raw packet to bpf. 1182 */ 1183 if (ifp->if_bpf) 1184 bpf_mtap(ifp->if_bpf, m); 1185 #endif 1186 1187 (*ifp->if_input)(ifp, m); 1188 } 1189 1190 /* 1191 * Pull read data off a interface. Len is length of data, with local net 1192 * header stripped. We copy the data into mbufs. When full cluster sized 1193 * units are present we copy into clusters. 1194 */ 1195 1196 struct mbuf * 1197 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1198 { 1199 struct mbuf *top, **mp, *m; 1200 int len; 1201 u_int cp, epkt; 1202 1203 cp = addr; 1204 epkt = cp + totlen; 1205 1206 MGETHDR(m, M_DONTWAIT, MT_DATA); 1207 if (m == 0) 1208 return 0; 1209 m->m_pkthdr.rcvif = ifp; 1210 m->m_pkthdr.len = totlen; 1211 m->m_len = MHLEN; 1212 top = 0; 1213 mp = ⊤ 1214 1215 while (totlen > 0) { 1216 if (top) { 1217 MGET(m, M_DONTWAIT, MT_DATA); 1218 if (m == 0) { 1219 m_freem(top); 1220 return 0; 1221 } 1222 m->m_len = MLEN; 1223 } 1224 len = min(totlen, epkt - cp); 1225 if (len >= MINCLSIZE) { 1226 MCLGET(m, M_DONTWAIT); 1227 if (m->m_flags & M_EXT) 1228 m->m_len = len = min(len, MCLBYTES); 1229 else 1230 len = m->m_len; 1231 } else { 1232 /* 1233 * Place initial small packet/header at end of mbuf. 1234 */ 1235 if (len < m->m_len) { 1236 if (top == 0 && len + max_linkhdr <= m->m_len) 1237 m->m_data += max_linkhdr; 1238 m->m_len = len; 1239 } else 1240 len = m->m_len; 1241 } 1242 if (top == 0) { 1243 /* Make sure the payload is aligned */ 1244 caddr_t newdata = (caddr_t) 1245 ALIGN(m->m_data + sizeof(struct ether_header)) - 1246 sizeof(struct ether_header); 1247 len -= newdata - m->m_data; 1248 m->m_len = len; 1249 m->m_data = newdata; 1250 } 1251 ea_readbuf(sc, mtod(m, u_char *), 1252 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1253 len); 1254 cp += len; 1255 *mp = m; 1256 mp = &m->m_next; 1257 totlen -= len; 1258 if (cp == epkt) 1259 cp = addr; 1260 } 1261 1262 return top; 1263 } 1264 1265 /* 1266 * Process an ioctl request. Mostly boilerplate. 1267 */ 1268 static int 1269 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1270 { 1271 struct seeq8005_softc *sc = ifp->if_softc; 1272 int s, error = 0; 1273 1274 s = splnet(); 1275 switch (cmd) { 1276 1277 default: 1278 error = ether_ioctl(ifp, cmd, data); 1279 if (error == ENETRESET) { 1280 /* 1281 * Multicast list has changed; set the hardware filter 1282 * accordingly. 1283 */ 1284 ea_mc_reset(sc); 1285 error = 0; 1286 } 1287 break; 1288 } 1289 1290 splx(s); 1291 return error; 1292 } 1293 1294 /* Must be called at splnet() */ 1295 1296 static void 1297 ea_mc_reset(struct seeq8005_softc *sc) 1298 { 1299 1300 switch (sc->sc_variant) { 1301 case SEEQ_8004: 1302 ea_mc_reset_8004(sc); 1303 return; 1304 case SEEQ_8005: 1305 ea_mc_reset_8005(sc); 1306 return; 1307 } 1308 } 1309 1310 static void 1311 ea_mc_reset_8004(struct seeq8005_softc *sc) 1312 { 1313 struct ethercom *ec = &sc->sc_ethercom; 1314 struct ifnet *ifp = &ec->ec_if; 1315 struct ether_multi *enm; 1316 u_int8_t *cp, c; 1317 u_int32_t crc; 1318 int i, len; 1319 struct ether_multistep step; 1320 u_int8_t af[8]; 1321 1322 /* 1323 * Set up multicast address filter by passing all multicast addresses 1324 * through a crc generator, and then using bits 2 - 7 as an index 1325 * into the 64 bit logical address filter. The high order bits 1326 * selects the word, while the rest of the bits select the bit within 1327 * the word. 1328 */ 1329 1330 if (ifp->if_flags & IFF_PROMISC) { 1331 ifp->if_flags |= IFF_ALLMULTI; 1332 for (i = 0; i < 8; i++) 1333 af[i] = 0xff; 1334 return; 1335 } 1336 for (i = 0; i < 8; i++) 1337 af[i] = 0; 1338 ETHER_FIRST_MULTI(step, ec, enm); 1339 while (enm != NULL) { 1340 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1341 sizeof(enm->enm_addrlo)) != 0) { 1342 /* 1343 * We must listen to a range of multicast addresses. 1344 * For now, just accept all multicasts, rather than 1345 * trying to set only those filter bits needed to match 1346 * the range. (At this time, the only use of address 1347 * ranges is for IP multicast routing, for which the 1348 * range is big enough to require all bits set.) 1349 */ 1350 ifp->if_flags |= IFF_ALLMULTI; 1351 for (i = 0; i < 8; i++) 1352 af[i] = 0xff; 1353 break; 1354 } 1355 cp = enm->enm_addrlo; 1356 crc = 0xffffffff; 1357 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1358 c = *cp++; 1359 for (i = 8; --i >= 0;) { 1360 if (((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01)) { 1361 crc <<= 1; 1362 crc ^= 0x04c11db6 | 1; 1363 } else 1364 crc <<= 1; 1365 c >>= 1; 1366 } 1367 } 1368 /* Just want the 6 most significant bits. */ 1369 crc = (crc >> 2) & 0x3f; 1370 1371 /* Turn on the corresponding bit in the filter. */ 1372 af[crc >> 3] |= 1 << (crc & 0x7); 1373 1374 ETHER_NEXT_MULTI(step, enm); 1375 } 1376 ifp->if_flags &= ~IFF_ALLMULTI; 1377 1378 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1379 for (i = 0; i < 8; ++i) 1380 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1381 SEEQ_BUFWIN, af[i]); 1382 } 1383 1384 static void 1385 ea_mc_reset_8005(struct seeq8005_softc *sc) 1386 { 1387 struct ether_multi *enm; 1388 struct ether_multistep step; 1389 int naddr, maxaddrs; 1390 1391 naddr = 0; 1392 maxaddrs = 5; 1393 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1394 while (enm != NULL) { 1395 /* Have we got space? */ 1396 if (naddr >= maxaddrs || 1397 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1398 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1399 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1400 return; 1401 } 1402 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1403 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1404 naddr++; 1405 ETHER_NEXT_MULTI(step, enm); 1406 } 1407 for (; naddr < maxaddrs; naddr++) 1408 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1409 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1410 sc->sc_config1); 1411 } 1412 1413 /* 1414 * Device timeout routine. 1415 */ 1416 1417 static void 1418 ea_watchdog(struct ifnet *ifp) 1419 { 1420 struct seeq8005_softc *sc = ifp->if_softc; 1421 1422 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1423 sc->sc_dev.dv_xname, 1424 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1425 ifp->if_oerrors++; 1426 1427 /* Kick the interface */ 1428 1429 ea_init(ifp); 1430 1431 ifp->if_timer = 0; 1432 } 1433 1434 /* End of if_ea.c */ 1435
Indexes created Mon Sep 29 21:09:56 GMT 2025