seeq8005.c revision 1.24
1 /* $NetBSD: seeq8005.c,v 1.24 2001/06/22 20:31:55 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45 /* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52 /* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56 /* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 66 __RCSID("$NetBSD: seeq8005.c,v 1.24 2001/06/22 20:31:55 bjh21 Exp $"); 67 68 #include <sys/systm.h> 69 #include <sys/endian.h> 70 #include <sys/errno.h> 71 #include <sys/ioctl.h> 72 #include <sys/mbuf.h> 73 #include <sys/socket.h> 74 #include <sys/syslog.h> 75 #include <sys/device.h> 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 #include <net/if_ether.h> 81 #include <net/if_media.h> 82 83 #include "bpfilter.h" 84 #if NBPFILTER > 0 85 #include <net/bpf.h> 86 #include <net/bpfdesc.h> 87 #endif 88 89 #include <machine/bus.h> 90 #include <machine/intr.h> 91 92 #include <dev/ic/seeq8005reg.h> 93 #include <dev/ic/seeq8005var.h> 94 95 /*#define SEEQ_DEBUG*/ 96 97 /* for debugging convenience */ 98 #ifdef SEEQ8005_DEBUG 99 #define SEEQ_DEBUG_MISC 1 100 #define SEEQ_DEBUG_TX 2 101 #define SEEQ_DEBUG_RX 4 102 #define SEEQ_DEBUG_PKT 8 103 #define SEEQ_DEBUG_TXINT 16 104 #define SEEQ_DEBUG_RXINT 32 105 int seeq8005_debug = 0; 106 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 107 #else 108 #define DPRINTF(f, x) 109 #endif 110 111 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> MAX_ETHER_LEN) */ 112 113 #define SEEQ_READ16(sc, iot, ioh, reg) \ 114 ((sc)->sc_flags & SF_8BIT ? \ 115 (bus_space_read_1((iot), (ioh), (reg)) | \ 116 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 117 (bus_space_read_2((iot), (ioh), (reg)))) 118 119 #define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 120 if ((sc)->sc_flags & SF_8BIT) { \ 121 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 122 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 123 } else \ 124 bus_space_write_2((iot), (ioh), (reg), (val)); \ 125 } while (/*CONSTCOND*/0) 126 127 /* 128 * prototypes 129 */ 130 131 static int ea_init(struct ifnet *); 132 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 133 static void ea_start(struct ifnet *); 134 static void ea_watchdog(struct ifnet *); 135 static void ea_chipreset(struct seeq8005_softc *); 136 static void ea_ramtest(struct seeq8005_softc *); 137 static int ea_stoptx(struct seeq8005_softc *); 138 static int ea_stoprx(struct seeq8005_softc *); 139 static void ea_stop(struct ifnet *, int); 140 static void ea_await_fifo_empty(struct seeq8005_softc *); 141 static void ea_await_fifo_full(struct seeq8005_softc *); 142 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 143 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_select_buffer(struct seeq8005_softc *, int); 145 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 146 static void ea_read(struct seeq8005_softc *, int, int); 147 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 148 static void ea_txint(struct seeq8005_softc *); 149 static void ea_rxint(struct seeq8005_softc *); 150 static void eatxpacket(struct seeq8005_softc *); 151 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 152 static void ea_mc_reset(struct seeq8005_softc *); 153 static void ea_mc_reset_8004(struct seeq8005_softc *); 154 static void ea_mc_reset_8005(struct seeq8005_softc *); 155 static int ea_mediachange(struct ifnet *); 156 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 157 158 159 /* 160 * Attach chip. 161 */ 162 163 void 164 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 165 int nmedia, int defmedia) 166 { 167 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 168 bus_space_tag_t iot = sc->sc_iot; 169 bus_space_handle_t ioh = sc->sc_ioh; 170 u_int id; 171 int tmp; 172 173 KASSERT(myaddr != NULL); 174 printf(" address %s", ether_sprintf(myaddr)); 175 176 /* Stop the board. */ 177 178 ea_chipreset(sc); 179 180 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 181 sc->sc_flags |= SF_8BIT; 182 printf("[0x%04x]", SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR)); 183 184 185 /* Work out data bus width. */ 186 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 187 if ((tmp = SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR)) != 0x1234) { 188 printf("[0x%04x]", tmp); 189 /* Try 8-bit mode */ 190 sc->sc_flags |= SF_8BIT; 191 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 192 if ((tmp = SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR)) != 0x1234) { 193 printf("[0x%04x]", tmp); 194 printf("\n%s: Cannot determine data bus width\n", 195 sc->sc_dev.dv_xname); 196 return; 197 } 198 } 199 200 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 201 202 /* Get the product ID */ 203 204 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 205 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 206 207 switch (id & SEEQ_PRODUCTID_MASK) { 208 case SEEQ_PRODUCTID_8004: 209 sc->sc_variant = SEEQ_8004; 210 switch (id & SEEQ_PRODUCTID_REV_MASK) { 211 case SEEQ_PRODUCTID_REV_80C04: 212 printf(", SEEQ 80C04\n"); 213 break; 214 case SEEQ_PRODUCTID_REV_80C04A: 215 printf(", SEEQ 80C04A\n"); 216 break; 217 default: 218 /* Unknown SEEQ 8004 variants */ 219 printf(", SEEQ 8004 rev %x\n", 220 id & SEEQ_PRODUCTID_REV_MASK); 221 break; 222 } 223 break; 224 default: /* XXX */ 225 sc->sc_variant = SEEQ_8005; 226 printf(", SEEQ 8005\n"); 227 break; 228 } 229 230 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 231 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 232 233 /* 234 * Set up tx and rx buffers. 235 * 236 * We use approximately a quarter of the packet memory for TX 237 * buffers and the rest for RX buffers 238 */ 239 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 240 sc->sc_tx_bufs = 1; 241 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 242 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 243 sc->sc_enabled = 0; 244 245 /* Test the RAM */ 246 ea_ramtest(sc); 247 248 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 249 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 250 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 251 252 /* Initialise ifnet structure. */ 253 254 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 255 ifp->if_softc = sc; 256 ifp->if_start = ea_start; 257 ifp->if_ioctl = ea_ioctl; 258 ifp->if_init = ea_init; 259 ifp->if_stop = ea_stop; 260 ifp->if_watchdog = ea_watchdog; 261 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 262 if (sc->sc_variant == SEEQ_8004) 263 ifp->if_flags |= IFF_SIMPLEX; 264 IFQ_SET_READY(&ifp->if_snd); 265 266 /* Initialize media goo. */ 267 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 268 if (media != NULL) { 269 int i; 270 271 for (i = 0; i < nmedia; i++) 272 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 273 ifmedia_set(&sc->sc_media, defmedia); 274 } else { 275 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 276 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 277 } 278 279 /* Now we can attach the interface. */ 280 281 if_attach(ifp); 282 ether_ifattach(ifp, myaddr); 283 284 printf("\n"); 285 } 286 287 /* 288 * Media change callback. 289 */ 290 static int 291 ea_mediachange(struct ifnet *ifp) 292 { 293 struct seeq8005_softc *sc = ifp->if_softc; 294 295 if (sc->sc_mediachange) 296 return ((*sc->sc_mediachange)(sc)); 297 return (EINVAL); 298 } 299 300 /* 301 * Media status callback. 302 */ 303 static void 304 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 305 { 306 struct seeq8005_softc *sc = ifp->if_softc; 307 308 if (sc->sc_enabled == 0) { 309 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 310 ifmr->ifm_status = 0; 311 return; 312 } 313 314 if (sc->sc_mediastatus) 315 (*sc->sc_mediastatus)(sc, ifmr); 316 } 317 318 /* 319 * Test the RAM on the ethernet card. 320 */ 321 322 void 323 ea_ramtest(struct seeq8005_softc *sc) 324 { 325 bus_space_tag_t iot = sc->sc_iot; 326 bus_space_handle_t ioh = sc->sc_ioh; 327 int loop; 328 u_int sum = 0; 329 330 /* 331 * Test the buffer memory on the board. 332 * Write simple pattens to it and read them back. 333 */ 334 335 /* Set up the whole buffer RAM for writing */ 336 337 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 338 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 339 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 340 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 341 342 #define SEEQ_RAMTEST_LOOP(value) \ 343 do { \ 344 /* Set the write start address and write a pattern */ \ 345 ea_writebuf(sc, NULL, 0x0000, 0); \ 346 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 347 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 348 \ 349 /* Set the read start address and verify the pattern */ \ 350 ea_readbuf(sc, NULL, 0x0000, 0); \ 351 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 352 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 353 ++sum; \ 354 } while (/*CONSTCOND*/0) 355 356 SEEQ_RAMTEST_LOOP(loop); 357 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 358 SEEQ_RAMTEST_LOOP(0xaa55); 359 SEEQ_RAMTEST_LOOP(0x55aa); 360 361 /* Report */ 362 363 if (sum > 0) 364 printf("%s: buffer RAM failed self test, %d faults\n", 365 sc->sc_dev.dv_xname, sum); 366 } 367 368 369 /* 370 * Stop the tx interface. 371 * 372 * Returns 0 if the tx was already stopped or 1 if it was active 373 */ 374 375 static int 376 ea_stoptx(struct seeq8005_softc *sc) 377 { 378 bus_space_tag_t iot = sc->sc_iot; 379 bus_space_handle_t ioh = sc->sc_ioh; 380 int timeout; 381 int status; 382 383 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 384 385 sc->sc_enabled = 0; 386 387 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 388 if (!(status & SEEQ_STATUS_TX_ON)) 389 return 0; 390 391 /* Stop any tx and wait for confirmation */ 392 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 393 sc->sc_command | SEEQ_CMD_TX_OFF); 394 395 timeout = 20000; 396 do { 397 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 398 delay(1); 399 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 400 if (timeout == 0) 401 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 402 sc->sc_dev.dv_xname); 403 404 /* Clear any pending tx interrupt */ 405 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 406 sc->sc_command | SEEQ_CMD_TX_INTACK); 407 return 1; 408 } 409 410 411 /* 412 * Stop the rx interface. 413 * 414 * Returns 0 if the tx was already stopped or 1 if it was active 415 */ 416 417 static int 418 ea_stoprx(struct seeq8005_softc *sc) 419 { 420 bus_space_tag_t iot = sc->sc_iot; 421 bus_space_handle_t ioh = sc->sc_ioh; 422 int timeout; 423 int status; 424 425 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 426 427 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 428 if (!(status & SEEQ_STATUS_RX_ON)) 429 return 0; 430 431 /* Stop any rx and wait for confirmation */ 432 433 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 434 sc->sc_command | SEEQ_CMD_RX_OFF); 435 436 timeout = 20000; 437 do { 438 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 439 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 440 if (timeout == 0) 441 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 442 sc->sc_dev.dv_xname); 443 444 /* Clear any pending rx interrupt */ 445 446 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 447 sc->sc_command | SEEQ_CMD_RX_INTACK); 448 return 1; 449 } 450 451 452 /* 453 * Stop interface. 454 * Stop all IO and shut the interface down 455 */ 456 457 static void 458 ea_stop(struct ifnet *ifp, int disable) 459 { 460 struct seeq8005_softc *sc = ifp->if_softc; 461 bus_space_tag_t iot = sc->sc_iot; 462 bus_space_handle_t ioh = sc->sc_ioh; 463 464 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 465 466 /* Stop all IO */ 467 ea_stoptx(sc); 468 ea_stoprx(sc); 469 470 /* Disable rx and tx interrupts */ 471 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 472 473 /* Clear any pending interrupts */ 474 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 475 sc->sc_command | SEEQ_CMD_RX_INTACK | 476 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 477 SEEQ_CMD_BW_INTACK); 478 479 if (sc->sc_variant == SEEQ_8004) { 480 /* Put the chip to sleep */ 481 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 482 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 483 sc->sc_config3 | SEEQ_CFG3_SLEEP); 484 } 485 486 /* Cancel any watchdog timer */ 487 sc->sc_ethercom.ec_if.if_timer = 0; 488 } 489 490 491 /* 492 * Reset the chip 493 * Following this the software registers are reset 494 */ 495 496 static void 497 ea_chipreset(struct seeq8005_softc *sc) 498 { 499 bus_space_tag_t iot = sc->sc_iot; 500 bus_space_handle_t ioh = sc->sc_ioh; 501 502 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 503 504 /* Reset the controller. Min of 4us delay here */ 505 506 /* 507 * This can be called before we know whether the chip is in 8- or 508 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 509 * harmless in 8-bit mode, so we do that second. 510 */ 511 512 /* In 16-bit mode, this will munge the PreamSelect bit. */ 513 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 514 delay(4); 515 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 516 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 517 delay(4); 518 519 sc->sc_command = 0; 520 sc->sc_config1 = 0; 521 sc->sc_config2 = 0; 522 sc->sc_config3 = 0; 523 } 524 525 526 /* 527 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 528 * switching the FIFO from write to read. We also use it when changing 529 * the address for writes. 530 */ 531 static void 532 ea_await_fifo_empty(struct seeq8005_softc *sc) 533 { 534 bus_space_tag_t iot = sc->sc_iot; 535 bus_space_handle_t ioh = sc->sc_ioh; 536 int timeout; 537 538 timeout = 20000; 539 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 540 SEEQ_STATUS_FIFO_DIR) != 0) 541 return; /* FIFO is reading anyway. */ 542 while (--timeout > 0) 543 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 544 SEEQ_STATUS_FIFO_EMPTY) 545 return; 546 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", sc->sc_dev.dv_xname); 547 } 548 549 /* 550 * Wait for the DMA FIFO to fill before reading from it. 551 */ 552 static void 553 ea_await_fifo_full(struct seeq8005_softc *sc) 554 { 555 bus_space_tag_t iot = sc->sc_iot; 556 bus_space_handle_t ioh = sc->sc_ioh; 557 int timeout; 558 559 timeout = 20000; 560 while (--timeout > 0) 561 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 562 SEEQ_STATUS_FIFO_FULL) 563 return; 564 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", sc->sc_dev.dv_xname); 565 } 566 567 /* 568 * write to the buffer memory on the interface 569 * 570 * The buffer address is set to ADDR. 571 * If len != 0 then data is copied from the address starting at buf 572 * to the interface buffer. 573 * BUF must be usable as a u_int16_t *. 574 * If LEN is odd, it must be safe to overwrite one extra byte. 575 */ 576 577 static void 578 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 579 { 580 bus_space_tag_t iot = sc->sc_iot; 581 bus_space_handle_t ioh = sc->sc_ioh; 582 583 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 584 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 585 586 #ifdef DIAGNOSTIC 587 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 588 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 589 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 590 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 591 #endif 592 593 /* Assume that copying too much is safe. */ 594 if (len % 2 != 0) 595 len++; 596 597 if (addr != -1) { 598 ea_await_fifo_empty(sc); 599 600 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 601 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 602 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 603 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 604 } 605 606 if (len > 0) { 607 if (sc->sc_flags & SF_8BIT) 608 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 609 (u_int8_t *)buf, len); 610 else 611 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 612 (u_int16_t *)buf, len / 2); 613 } 614 /* Leave FIFO to empty in the background */ 615 } 616 617 618 /* 619 * read from the buffer memory on the interface 620 * 621 * The buffer address is set to ADDR. 622 * If len != 0 then data is copied from the interface buffer to the 623 * address starting at buf. 624 * BUF must be usable as a u_int16_t *. 625 * If LEN is odd, it must be safe to overwrite one extra byte. 626 */ 627 628 static void 629 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 630 { 631 bus_space_tag_t iot = sc->sc_iot; 632 bus_space_handle_t ioh = sc->sc_ioh; 633 int runup; 634 635 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 636 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 637 638 #ifdef DIAGNOSTIC 639 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 640 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 641 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 642 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 643 #endif 644 645 /* Assume that copying too much is safe. */ 646 if (len % 2 != 0) 647 len++; 648 649 if (addr != -1) { 650 /* 651 * SEEQ 80C04 bug: 652 * Starting reading from certain addresses seems to cause 653 * us to get bogus results, so we avoid them. 654 */ 655 runup = 0; 656 if (sc->sc_variant == SEEQ_8004 && 657 ((addr & 0x00ff) == 0x00ea || 658 (addr & 0x00ff) == 0x00ee || 659 (addr & 0x00ff) == 0x00f0)) 660 runup = (addr & 0x00ff) - 0x00e8; 661 662 ea_await_fifo_empty(sc); 663 664 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 665 666 /* 667 * 80C04 bug workaround. I found this in the old arm32 "eb" 668 * driver. I've no idea what it does, but it seems to stop 669 * the chip mangling data so often. 670 */ 671 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 672 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 673 ea_await_fifo_empty(sc); 674 675 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 676 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 677 sc->sc_command | SEEQ_CMD_FIFO_READ); 678 679 ea_await_fifo_full(sc); 680 while (runup > 0) { 681 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 682 runup -= 2; 683 } 684 } 685 686 if (len > 0) { 687 if (sc->sc_flags & SF_8BIT) 688 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 689 (u_int8_t *)buf, len); 690 else 691 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 692 (u_int16_t *)buf, len / 2); 693 } 694 } 695 696 static void 697 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 698 { 699 700 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 701 sc->sc_config1 | bufcode); 702 } 703 704 /* Must be called at splnet */ 705 static void 706 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 707 { 708 int i; 709 710 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 711 for (i = 0; i < ETHER_ADDR_LEN; ++i) 712 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 713 ea[i]); 714 } 715 716 /* 717 * Initialize interface. 718 * 719 * This should leave the interface in a state for packet reception and 720 * transmission. 721 */ 722 723 static int 724 ea_init(struct ifnet *ifp) 725 { 726 struct seeq8005_softc *sc = ifp->if_softc; 727 bus_space_tag_t iot = sc->sc_iot; 728 bus_space_handle_t ioh = sc->sc_ioh; 729 int s; 730 731 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 732 733 s = splnet(); 734 735 /* First, reset the board. */ 736 737 ea_chipreset(sc); 738 739 /* Set up defaults for the registers */ 740 741 sc->sc_command = 0; 742 sc->sc_config1 = 0; 743 #if BYTE_ORDER == BIG_ENDIAN 744 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 745 #else 746 sc->sc_config2 = 0; 747 #endif 748 sc->sc_config3 = 0; 749 750 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 751 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 752 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 753 if (sc->sc_variant == SEEQ_8004) { 754 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 755 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 756 } 757 758 /* Write the station address - the receiver must be off */ 759 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 760 761 /* Split board memory into Rx and Tx. */ 762 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 763 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 764 765 if (sc->sc_variant == SEEQ_8004) 766 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 767 768 /* Configure rx. */ 769 ea_mc_reset(sc); 770 if (ifp->if_flags & IFF_PROMISC) 771 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 772 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 773 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 774 else 775 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 776 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 777 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 778 779 /* Setup the Rx pointers */ 780 sc->sc_rx_ptr = sc->sc_tx_bufsize; 781 782 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 783 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 784 785 786 /* Place a NULL header at the beginning of the receive area */ 787 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 788 789 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 790 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 791 792 793 /* Configure TX. */ 794 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 795 796 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 797 798 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 799 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 800 801 /* Reset tx buffer pointers */ 802 sc->sc_tx_cur = 0; 803 sc->sc_tx_used = 0; 804 sc->sc_tx_next = 0; 805 806 /* Place a NULL header at the beginning of the transmit area */ 807 ea_writebuf(sc, NULL, 0x0000, 0); 808 809 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 810 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 811 812 sc->sc_command |= SEEQ_CMD_TX_INTEN; 813 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 814 815 /* Turn on Rx */ 816 sc->sc_command |= SEEQ_CMD_RX_INTEN; 817 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 818 sc->sc_command | SEEQ_CMD_RX_ON); 819 820 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 821 822 823 /* Set flags appropriately. */ 824 ifp->if_flags |= IFF_RUNNING; 825 ifp->if_flags &= ~IFF_OACTIVE; 826 sc->sc_enabled = 1; 827 828 /* And start output. */ 829 ea_start(ifp); 830 831 splx(s); 832 return 0; 833 } 834 835 /* 836 * Start output on interface. Get datagrams from the queue and output them, 837 * giving the receiver a chance between datagrams. Call only from splnet or 838 * interrupt level! 839 */ 840 841 static void 842 ea_start(struct ifnet *ifp) 843 { 844 struct seeq8005_softc *sc = ifp->if_softc; 845 int s; 846 847 s = splnet(); 848 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 849 850 /* 851 * Don't do anything if output is active. seeq8005intr() will call 852 * us (actually eatxpacket()) back when the card's ready for more 853 * frames. 854 */ 855 if (ifp->if_flags & IFF_OACTIVE) 856 return; 857 858 /* Mark interface as output active */ 859 860 ifp->if_flags |= IFF_OACTIVE; 861 862 /* tx packets */ 863 864 eatxpacket(sc); 865 splx(s); 866 } 867 868 869 /* 870 * Transfer a packet to the interface buffer and start transmission 871 * 872 * Called at splnet() 873 */ 874 875 void 876 eatxpacket(struct seeq8005_softc *sc) 877 { 878 bus_space_tag_t iot = sc->sc_iot; 879 bus_space_handle_t ioh = sc->sc_ioh; 880 struct mbuf *m0; 881 struct ifnet *ifp; 882 883 ifp = &sc->sc_ethercom.ec_if; 884 885 /* Dequeue the next packet. */ 886 IFQ_DEQUEUE(&ifp->if_snd, m0); 887 888 /* If there's nothing to send, return. */ 889 if (!m0) { 890 ifp->if_flags &= ~IFF_OACTIVE; 891 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 892 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 893 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 894 return; 895 } 896 897 #if NBPFILTER > 0 898 /* Give the packet to the bpf, if any. */ 899 if (ifp->if_bpf) 900 bpf_mtap(ifp->if_bpf, m0); 901 #endif 902 903 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 904 905 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 906 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 907 908 ea_writembuf(sc, m0, 0x0000); 909 m_freem(m0); 910 911 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 912 913 /* Now transmit the datagram. */ 914 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 915 sc->sc_command | SEEQ_CMD_TX_ON); 916 917 /* Make sure we notice if the chip goes silent on us. */ 918 ifp->if_timer = 5; 919 920 DPRINTF(SEEQ_DEBUG_TX, 921 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 922 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 923 } 924 925 /* 926 * Copy a packet from an mbuf to the transmit buffer on the card. 927 * 928 * Puts a valid Tx header at the start of the packet, and a null header at 929 * the end. 930 */ 931 static int 932 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 933 { 934 struct mbuf *m; 935 int len, nextpacket; 936 u_int8_t hdr[4]; 937 938 /* 939 * Copy the datagram to the packet buffer. 940 */ 941 len = 0; 942 for (m = m0; m; m = m->m_next) { 943 if (m->m_len == 0) 944 continue; 945 ea_writebuf(sc, mtod(m, caddr_t), bufstart + 4 + len, 946 m->m_len); 947 len += m->m_len; 948 } 949 950 len = max(len, ETHER_MIN_LEN); 951 952 /* Follow it with a NULL packet header */ 953 memset(hdr, 0, 4); 954 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 955 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 956 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 957 958 /* Ok we now have a packet len bytes long in our packet buffer */ 959 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 960 961 /* Write the packet header */ 962 nextpacket = len + 4; 963 hdr[0] = (nextpacket >> 8) & 0xff; 964 hdr[1] = nextpacket & 0xff; 965 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 966 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 967 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 968 ea_writebuf(sc, hdr, 0x0000, 4); 969 970 return len; 971 } 972 973 /* 974 * Ethernet controller interrupt. 975 */ 976 977 int 978 seeq8005intr(void *arg) 979 { 980 struct seeq8005_softc *sc = arg; 981 bus_space_tag_t iot = sc->sc_iot; 982 bus_space_handle_t ioh = sc->sc_ioh; 983 int status, handled; 984 985 handled = 0; 986 987 /* Get the controller status */ 988 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 989 990 /* Tx interrupt ? */ 991 if (status & SEEQ_STATUS_TX_INT) { 992 handled = 1; 993 994 /* Acknowledge the interrupt */ 995 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 996 sc->sc_command | SEEQ_CMD_TX_INTACK); 997 998 ea_txint(sc); 999 } 1000 1001 1002 /* Rx interrupt ? */ 1003 if (status & SEEQ_STATUS_RX_INT) { 1004 handled = 1; 1005 1006 /* Acknowledge the interrupt */ 1007 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1008 sc->sc_command | SEEQ_CMD_RX_INTACK); 1009 1010 /* Processes the received packets */ 1011 ea_rxint(sc); 1012 } 1013 1014 return handled; 1015 } 1016 1017 static void 1018 ea_txint(struct seeq8005_softc *sc) 1019 { 1020 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1021 bus_space_tag_t iot = sc->sc_iot; 1022 bus_space_handle_t ioh = sc->sc_ioh; 1023 u_int8_t txhdr[4]; 1024 u_int txstatus; 1025 1026 ea_readbuf(sc, txhdr, 0x0000, 4); 1027 1028 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1029 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1030 txstatus = txhdr[3]; 1031 1032 /* 1033 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1034 * one collision. On the 8004 we can find out exactly how many 1035 * collisions occurred. 1036 * 1037 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1038 * completed. 1039 * 1040 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1041 * occurred and the packet transmission was aborted. 1042 * This situation is untested as present. 1043 * 1044 * The SEEQ_TXSTAT_BABBLE should never be set and is untested 1045 * as we should never xmit oversized packets. 1046 */ 1047 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1048 switch (sc->sc_variant) { 1049 case SEEQ_8004: { 1050 int colls; 1051 1052 /* 1053 * The 8004 contains a 4 bit collision count 1054 * in the status register. 1055 */ 1056 1057 /* This appears to be broken on 80C04.AE */ 1058 /* ifp->if_collisions += 1059 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1060 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1061 1062 /* Use the TX Collision register */ 1063 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1064 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1065 ifp->if_collisions += colls; 1066 break; 1067 } 1068 case SEEQ_8005: 1069 /* We known there was at least 1 collision */ 1070 ifp->if_collisions++; 1071 break; 1072 } 1073 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1074 printf("seeq_intr: col16 %x\n", txstatus); 1075 ifp->if_collisions += 16; 1076 ifp->if_oerrors++; 1077 } else if (txstatus & SEEQ_TXSTAT_BABBLE) { 1078 ifp->if_oerrors++; 1079 } 1080 1081 /* Have we completed transmission on the packet ? */ 1082 if (txstatus & SEEQ_PKTSTAT_DONE) { 1083 /* Clear watchdog timer. */ 1084 ifp->if_timer = 0; 1085 ifp->if_flags &= ~IFF_OACTIVE; 1086 1087 /* Update stats */ 1088 ifp->if_opackets++; 1089 1090 /* Tx next packet */ 1091 1092 eatxpacket(sc); 1093 } 1094 } 1095 1096 void 1097 ea_rxint(struct seeq8005_softc *sc) 1098 { 1099 bus_space_tag_t iot = sc->sc_iot; 1100 bus_space_handle_t ioh = sc->sc_ioh; 1101 u_int addr; 1102 int len; 1103 int ctrl; 1104 int ptr; 1105 int pack; 1106 int status; 1107 u_int8_t rxhdr[4]; 1108 struct ifnet *ifp; 1109 1110 ifp = &sc->sc_ethercom.ec_if; 1111 1112 1113 /* We start from the last rx pointer position */ 1114 addr = sc->sc_rx_ptr; 1115 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1116 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1117 1118 do { 1119 /* Read rx header */ 1120 ea_readbuf(sc, rxhdr, addr, 4); 1121 1122 /* Split the packet header */ 1123 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1124 ctrl = rxhdr[2]; 1125 status = rxhdr[3]; 1126 1127 DPRINTF(SEEQ_DEBUG_RX, 1128 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1129 addr, ptr, ctrl, status)); 1130 1131 /* Zero packet ptr ? then must be null header so exit */ 1132 if (ptr == 0) break; 1133 1134 /* Sanity-check the next-packet pointer and flags. */ 1135 if (__predict_false(ptr < sc->sc_tx_bufsize || 1136 (ctrl & SEEQ_PKTCMD_TX))) { 1137 ++ifp->if_ierrors; 1138 log(LOG_ERR, 1139 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1140 sc->sc_dev.dv_xname, addr, ptr); 1141 ea_init(ifp); 1142 return; 1143 } 1144 1145 /* Get packet length */ 1146 len = (ptr - addr) - 4; 1147 1148 if (len < 0) 1149 len += sc->sc_rx_bufsize; 1150 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1151 1152 /* Has the packet rx completed ? if not then exit */ 1153 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1154 break; 1155 1156 /* 1157 * Did we have any errors? then note error and go to 1158 * next packet 1159 */ 1160 if (__predict_false(status & SEEQ_RXSTAT_ERROR_MASK)) { 1161 ++ifp->if_ierrors; 1162 /* XXX oversize packets may be OK */ 1163 log(LOG_WARNING, 1164 "%s: rx packet error at %04x (err=%02x)\n", 1165 sc->sc_dev.dv_xname, addr, status & 0x0f); 1166 /* XXX shouldn't need to reset if it's genuine. */ 1167 ea_init(ifp); 1168 return; 1169 } 1170 /* 1171 * Is the packet too big ? - this will probably be trapped 1172 * above as a receive error. If it's not, this is indicative 1173 * of buffer corruption. 1174 */ 1175 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1176 ++ifp->if_ierrors; 1177 log(LOG_ERR, 1178 "%s: rx packet size error at %04x (len=%d)\n", 1179 sc->sc_dev.dv_xname, addr, len); 1180 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1181 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, 1182 sc->sc_config2); 1183 ea_init(ifp); 1184 return; 1185 } 1186 1187 ifp->if_ipackets++; 1188 /* Pass data up to upper levels. */ 1189 ea_read(sc, addr + 4, len); 1190 1191 addr = ptr; 1192 ++pack; 1193 } while (len != 0); 1194 1195 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1196 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1197 1198 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1199 1200 /* Store new rx pointer */ 1201 sc->sc_rx_ptr = addr; 1202 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1203 1204 /* Make sure the receiver is on */ 1205 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1206 sc->sc_command | SEEQ_CMD_RX_ON); 1207 } 1208 1209 1210 /* 1211 * Pass a packet up to the higher levels. 1212 */ 1213 1214 static void 1215 ea_read(struct seeq8005_softc *sc, int addr, int len) 1216 { 1217 struct mbuf *m; 1218 struct ifnet *ifp; 1219 1220 ifp = &sc->sc_ethercom.ec_if; 1221 1222 /* Pull packet off interface. */ 1223 m = ea_get(sc, addr, len, ifp); 1224 if (m == 0) 1225 return; 1226 1227 #if NBPFILTER > 0 1228 /* 1229 * Check if there's a BPF listener on this interface. 1230 * If so, hand off the raw packet to bpf. 1231 */ 1232 if (ifp->if_bpf) 1233 bpf_mtap(ifp->if_bpf, m); 1234 #endif 1235 1236 (*ifp->if_input)(ifp, m); 1237 } 1238 1239 /* 1240 * Pull read data off a interface. Len is length of data, with local net 1241 * header stripped. We copy the data into mbufs. When full cluster sized 1242 * units are present we copy into clusters. 1243 */ 1244 1245 struct mbuf * 1246 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1247 { 1248 struct mbuf *top, **mp, *m; 1249 int len; 1250 u_int cp, epkt; 1251 1252 cp = addr; 1253 epkt = cp + totlen; 1254 1255 MGETHDR(m, M_DONTWAIT, MT_DATA); 1256 if (m == 0) 1257 return 0; 1258 m->m_pkthdr.rcvif = ifp; 1259 m->m_pkthdr.len = totlen; 1260 m->m_len = MHLEN; 1261 top = 0; 1262 mp = ⊤ 1263 1264 while (totlen > 0) { 1265 if (top) { 1266 MGET(m, M_DONTWAIT, MT_DATA); 1267 if (m == 0) { 1268 m_freem(top); 1269 return 0; 1270 } 1271 m->m_len = MLEN; 1272 } 1273 len = min(totlen, epkt - cp); 1274 if (len >= MINCLSIZE) { 1275 MCLGET(m, M_DONTWAIT); 1276 if (m->m_flags & M_EXT) 1277 m->m_len = len = min(len, MCLBYTES); 1278 else 1279 len = m->m_len; 1280 } else { 1281 /* 1282 * Place initial small packet/header at end of mbuf. 1283 */ 1284 if (len < m->m_len) { 1285 if (top == 0 && len + max_linkhdr <= m->m_len) 1286 m->m_data += max_linkhdr; 1287 m->m_len = len; 1288 } else 1289 len = m->m_len; 1290 } 1291 if (top == 0) { 1292 /* Make sure the payload is aligned */ 1293 caddr_t newdata = (caddr_t) 1294 ALIGN(m->m_data + sizeof(struct ether_header)) - 1295 sizeof(struct ether_header); 1296 len -= newdata - m->m_data; 1297 m->m_len = len; 1298 m->m_data = newdata; 1299 } 1300 ea_readbuf(sc, mtod(m, u_char *), 1301 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1302 len); 1303 cp += len; 1304 *mp = m; 1305 mp = &m->m_next; 1306 totlen -= len; 1307 if (cp == epkt) 1308 cp = addr; 1309 } 1310 1311 return top; 1312 } 1313 1314 /* 1315 * Process an ioctl request. Mostly boilerplate. 1316 */ 1317 static int 1318 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1319 { 1320 struct seeq8005_softc *sc = ifp->if_softc; 1321 int s, error = 0; 1322 1323 s = splnet(); 1324 switch (cmd) { 1325 1326 default: 1327 error = ether_ioctl(ifp, cmd, data); 1328 if (error == ENETRESET) { 1329 /* 1330 * Multicast list has changed; set the hardware filter 1331 * accordingly. 1332 */ 1333 ea_mc_reset(sc); 1334 error = 0; 1335 } 1336 break; 1337 } 1338 1339 splx(s); 1340 return error; 1341 } 1342 1343 /* Must be called at splnet() */ 1344 1345 static void 1346 ea_mc_reset(struct seeq8005_softc *sc) 1347 { 1348 1349 switch (sc->sc_variant) { 1350 case SEEQ_8004: 1351 ea_mc_reset_8004(sc); 1352 return; 1353 case SEEQ_8005: 1354 ea_mc_reset_8005(sc); 1355 return; 1356 } 1357 } 1358 1359 static void 1360 ea_mc_reset_8004(struct seeq8005_softc *sc) 1361 { 1362 struct ethercom *ec = &sc->sc_ethercom; 1363 struct ifnet *ifp = &ec->ec_if; 1364 struct ether_multi *enm; 1365 u_int32_t crc; 1366 int i; 1367 struct ether_multistep step; 1368 u_int8_t af[8]; 1369 1370 /* 1371 * Set up multicast address filter by passing all multicast addresses 1372 * through a crc generator, and then using bits 2 - 7 as an index 1373 * into the 64 bit logical address filter. The high order bits 1374 * selects the word, while the rest of the bits select the bit within 1375 * the word. 1376 */ 1377 1378 if (ifp->if_flags & IFF_PROMISC) { 1379 ifp->if_flags |= IFF_ALLMULTI; 1380 for (i = 0; i < 8; i++) 1381 af[i] = 0xff; 1382 return; 1383 } 1384 for (i = 0; i < 8; i++) 1385 af[i] = 0; 1386 ETHER_FIRST_MULTI(step, ec, enm); 1387 while (enm != NULL) { 1388 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1389 sizeof(enm->enm_addrlo)) != 0) { 1390 /* 1391 * We must listen to a range of multicast addresses. 1392 * For now, just accept all multicasts, rather than 1393 * trying to set only those filter bits needed to match 1394 * the range. (At this time, the only use of address 1395 * ranges is for IP multicast routing, for which the 1396 * range is big enough to require all bits set.) 1397 */ 1398 ifp->if_flags |= IFF_ALLMULTI; 1399 for (i = 0; i < 8; i++) 1400 af[i] = 0xff; 1401 break; 1402 } 1403 cp = enm->enm_addrlo; 1404 crc = 0xffffffff; 1405 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1406 c = *cp++; 1407 for (i = 8; --i >= 0;) { 1408 if (((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01)) { 1409 crc <<= 1; 1410 crc ^= 0x04c11db6 | 1; 1411 } else 1412 crc <<= 1; 1413 c >>= 1; 1414 } 1415 } 1416 /* Just want the 6 most significant bits. */ 1417 crc = (crc >> 2) & 0x3f; 1418 1419 /* Turn on the corresponding bit in the filter. */ 1420 af[crc >> 3] |= 1 << (crc & 0x7); 1421 1422 ETHER_NEXT_MULTI(step, enm); 1423 } 1424 ifp->if_flags &= ~IFF_ALLMULTI; 1425 1426 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1427 for (i = 0; i < 8; ++i) 1428 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1429 SEEQ_BUFWIN, af[i]); 1430 } 1431 1432 static void 1433 ea_mc_reset_8005(struct seeq8005_softc *sc) 1434 { 1435 struct ether_multi *enm; 1436 struct ether_multistep step; 1437 int naddr, maxaddrs; 1438 1439 naddr = 0; 1440 maxaddrs = 5; 1441 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1442 while (enm != NULL) { 1443 /* Have we got space? */ 1444 if (naddr >= maxaddrs || 1445 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1446 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1447 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1448 return; 1449 } 1450 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1451 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1452 naddr++; 1453 ETHER_NEXT_MULTI(step, enm); 1454 } 1455 for (; naddr < maxaddrs; naddr++) 1456 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1457 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1458 sc->sc_config1); 1459 } 1460 1461 /* 1462 * Device timeout routine. 1463 */ 1464 1465 static void 1466 ea_watchdog(struct ifnet *ifp) 1467 { 1468 struct seeq8005_softc *sc = ifp->if_softc; 1469 1470 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1471 sc->sc_dev.dv_xname, 1472 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1473 ifp->if_oerrors++; 1474 1475 /* Kick the interface */ 1476 1477 ea_init(ifp); 1478 1479 ifp->if_timer = 0; 1480 } 1481 1482 /* End of if_ea.c */ 1483
Indexes created Mon Sep 29 21:09:56 GMT 2025