seeq8005.c revision 1.26
1 /* $NetBSD: seeq8005.c,v 1.26 2001/06/23 17:32:21 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45 /* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52 /* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56 /* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 66 __RCSID("$NetBSD: seeq8005.c,v 1.26 2001/06/23 17:32:21 bjh21 Exp $"); 67 68 #include <sys/systm.h> 69 #include <sys/endian.h> 70 #include <sys/errno.h> 71 #include <sys/ioctl.h> 72 #include <sys/mbuf.h> 73 #include <sys/socket.h> 74 #include <sys/syslog.h> 75 #include <sys/device.h> 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 #include <net/if_ether.h> 81 #include <net/if_media.h> 82 83 #include "bpfilter.h" 84 #if NBPFILTER > 0 85 #include <net/bpf.h> 86 #include <net/bpfdesc.h> 87 #endif 88 89 #include <machine/bus.h> 90 #include <machine/intr.h> 91 92 #include <dev/ic/seeq8005reg.h> 93 #include <dev/ic/seeq8005var.h> 94 95 /*#define SEEQ_DEBUG*/ 96 97 /* for debugging convenience */ 98 #ifdef SEEQ8005_DEBUG 99 #define SEEQ_DEBUG_MISC 1 100 #define SEEQ_DEBUG_TX 2 101 #define SEEQ_DEBUG_RX 4 102 #define SEEQ_DEBUG_PKT 8 103 #define SEEQ_DEBUG_TXINT 16 104 #define SEEQ_DEBUG_RXINT 32 105 int seeq8005_debug = 0; 106 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 107 #else 108 #define DPRINTF(f, x) 109 #endif 110 111 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> MAX_ETHER_LEN) */ 112 113 #define SEEQ_READ16(sc, iot, ioh, reg) \ 114 ((sc)->sc_flags & SF_8BIT ? \ 115 (bus_space_read_1((iot), (ioh), (reg)) | \ 116 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 117 (bus_space_read_2((iot), (ioh), (reg)))) 118 119 #define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 120 if ((sc)->sc_flags & SF_8BIT) { \ 121 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 122 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 123 } else \ 124 bus_space_write_2((iot), (ioh), (reg), (val)); \ 125 } while (/*CONSTCOND*/0) 126 127 /* 128 * prototypes 129 */ 130 131 static int ea_init(struct ifnet *); 132 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 133 static void ea_start(struct ifnet *); 134 static void ea_watchdog(struct ifnet *); 135 static void ea_chipreset(struct seeq8005_softc *); 136 static void ea_ramtest(struct seeq8005_softc *); 137 static int ea_stoptx(struct seeq8005_softc *); 138 static int ea_stoprx(struct seeq8005_softc *); 139 static void ea_stop(struct ifnet *, int); 140 static void ea_await_fifo_empty(struct seeq8005_softc *); 141 static void ea_await_fifo_full(struct seeq8005_softc *); 142 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 143 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_select_buffer(struct seeq8005_softc *, int); 145 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 146 static void ea_read(struct seeq8005_softc *, int, int); 147 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 148 static void ea_txint(struct seeq8005_softc *); 149 static void ea_rxint(struct seeq8005_softc *); 150 static void eatxpacket(struct seeq8005_softc *); 151 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 152 static void ea_mc_reset(struct seeq8005_softc *); 153 static void ea_mc_reset_8004(struct seeq8005_softc *); 154 static void ea_mc_reset_8005(struct seeq8005_softc *); 155 static int ea_mediachange(struct ifnet *); 156 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 157 158 159 /* 160 * Attach chip. 161 */ 162 163 void 164 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 165 int nmedia, int defmedia) 166 { 167 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 168 bus_space_tag_t iot = sc->sc_iot; 169 bus_space_handle_t ioh = sc->sc_ioh; 170 u_int id; 171 172 KASSERT(myaddr != NULL); 173 printf(" address %s", ether_sprintf(myaddr)); 174 175 /* Stop the board. */ 176 177 ea_chipreset(sc); 178 179 /* Work out data bus width. */ 180 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 181 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 182 /* Try 8-bit mode */ 183 sc->sc_flags |= SF_8BIT; 184 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 185 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 186 printf("\n%s: Cannot determine data bus width\n", 187 sc->sc_dev.dv_xname); 188 return; 189 } 190 } 191 192 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 193 194 /* Get the product ID */ 195 196 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 197 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 198 199 switch (id & SEEQ_PRODUCTID_MASK) { 200 case SEEQ_PRODUCTID_8004: 201 sc->sc_variant = SEEQ_8004; 202 switch (id & SEEQ_PRODUCTID_REV_MASK) { 203 case SEEQ_PRODUCTID_REV_80C04: 204 printf(", SEEQ 80C04\n"); 205 break; 206 case SEEQ_PRODUCTID_REV_80C04A: 207 printf(", SEEQ 80C04A\n"); 208 break; 209 default: 210 /* Unknown SEEQ 8004 variants */ 211 printf(", SEEQ 8004 rev %x\n", 212 id & SEEQ_PRODUCTID_REV_MASK); 213 break; 214 } 215 break; 216 default: /* XXX */ 217 sc->sc_variant = SEEQ_8005; 218 printf(", SEEQ 8005\n"); 219 break; 220 } 221 222 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 223 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 224 225 /* 226 * Set up tx and rx buffers. 227 * 228 * We use approximately a quarter of the packet memory for TX 229 * buffers and the rest for RX buffers 230 */ 231 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 232 sc->sc_tx_bufs = 1; 233 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 234 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 235 sc->sc_enabled = 0; 236 237 /* Test the RAM */ 238 ea_ramtest(sc); 239 240 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 241 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 242 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 243 244 /* Initialise ifnet structure. */ 245 246 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 247 ifp->if_softc = sc; 248 ifp->if_start = ea_start; 249 ifp->if_ioctl = ea_ioctl; 250 ifp->if_init = ea_init; 251 ifp->if_stop = ea_stop; 252 ifp->if_watchdog = ea_watchdog; 253 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 254 if (sc->sc_variant == SEEQ_8004) 255 ifp->if_flags |= IFF_SIMPLEX; 256 IFQ_SET_READY(&ifp->if_snd); 257 258 /* Initialize media goo. */ 259 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 260 if (media != NULL) { 261 int i; 262 263 for (i = 0; i < nmedia; i++) 264 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 265 ifmedia_set(&sc->sc_media, defmedia); 266 } else { 267 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 268 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 269 } 270 271 /* Now we can attach the interface. */ 272 273 if_attach(ifp); 274 ether_ifattach(ifp, myaddr); 275 276 printf("\n"); 277 } 278 279 /* 280 * Media change callback. 281 */ 282 static int 283 ea_mediachange(struct ifnet *ifp) 284 { 285 struct seeq8005_softc *sc = ifp->if_softc; 286 287 if (sc->sc_mediachange) 288 return ((*sc->sc_mediachange)(sc)); 289 return (EINVAL); 290 } 291 292 /* 293 * Media status callback. 294 */ 295 static void 296 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 297 { 298 struct seeq8005_softc *sc = ifp->if_softc; 299 300 if (sc->sc_enabled == 0) { 301 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 302 ifmr->ifm_status = 0; 303 return; 304 } 305 306 if (sc->sc_mediastatus) 307 (*sc->sc_mediastatus)(sc, ifmr); 308 } 309 310 /* 311 * Test the RAM on the ethernet card. 312 */ 313 314 void 315 ea_ramtest(struct seeq8005_softc *sc) 316 { 317 bus_space_tag_t iot = sc->sc_iot; 318 bus_space_handle_t ioh = sc->sc_ioh; 319 int loop; 320 u_int sum = 0; 321 322 /* 323 * Test the buffer memory on the board. 324 * Write simple pattens to it and read them back. 325 */ 326 327 /* Set up the whole buffer RAM for writing */ 328 329 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 330 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 331 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 332 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 333 334 #define SEEQ_RAMTEST_LOOP(value) \ 335 do { \ 336 /* Set the write start address and write a pattern */ \ 337 ea_writebuf(sc, NULL, 0x0000, 0); \ 338 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 339 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 340 \ 341 /* Set the read start address and verify the pattern */ \ 342 ea_readbuf(sc, NULL, 0x0000, 0); \ 343 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 344 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 345 ++sum; \ 346 } while (/*CONSTCOND*/0) 347 348 SEEQ_RAMTEST_LOOP(loop); 349 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 350 SEEQ_RAMTEST_LOOP(0xaa55); 351 SEEQ_RAMTEST_LOOP(0x55aa); 352 353 /* Report */ 354 355 if (sum > 0) 356 printf("%s: buffer RAM failed self test, %d faults\n", 357 sc->sc_dev.dv_xname, sum); 358 } 359 360 361 /* 362 * Stop the tx interface. 363 * 364 * Returns 0 if the tx was already stopped or 1 if it was active 365 */ 366 367 static int 368 ea_stoptx(struct seeq8005_softc *sc) 369 { 370 bus_space_tag_t iot = sc->sc_iot; 371 bus_space_handle_t ioh = sc->sc_ioh; 372 int timeout; 373 int status; 374 375 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 376 377 sc->sc_enabled = 0; 378 379 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 380 if (!(status & SEEQ_STATUS_TX_ON)) 381 return 0; 382 383 /* Stop any tx and wait for confirmation */ 384 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 385 sc->sc_command | SEEQ_CMD_TX_OFF); 386 387 timeout = 20000; 388 do { 389 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 390 delay(1); 391 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 392 if (timeout == 0) 393 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 394 sc->sc_dev.dv_xname); 395 396 /* Clear any pending tx interrupt */ 397 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 398 sc->sc_command | SEEQ_CMD_TX_INTACK); 399 return 1; 400 } 401 402 403 /* 404 * Stop the rx interface. 405 * 406 * Returns 0 if the tx was already stopped or 1 if it was active 407 */ 408 409 static int 410 ea_stoprx(struct seeq8005_softc *sc) 411 { 412 bus_space_tag_t iot = sc->sc_iot; 413 bus_space_handle_t ioh = sc->sc_ioh; 414 int timeout; 415 int status; 416 417 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 418 419 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 420 if (!(status & SEEQ_STATUS_RX_ON)) 421 return 0; 422 423 /* Stop any rx and wait for confirmation */ 424 425 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 426 sc->sc_command | SEEQ_CMD_RX_OFF); 427 428 timeout = 20000; 429 do { 430 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 431 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 432 if (timeout == 0) 433 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 434 sc->sc_dev.dv_xname); 435 436 /* Clear any pending rx interrupt */ 437 438 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 439 sc->sc_command | SEEQ_CMD_RX_INTACK); 440 return 1; 441 } 442 443 444 /* 445 * Stop interface. 446 * Stop all IO and shut the interface down 447 */ 448 449 static void 450 ea_stop(struct ifnet *ifp, int disable) 451 { 452 struct seeq8005_softc *sc = ifp->if_softc; 453 bus_space_tag_t iot = sc->sc_iot; 454 bus_space_handle_t ioh = sc->sc_ioh; 455 456 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 457 458 /* Stop all IO */ 459 ea_stoptx(sc); 460 ea_stoprx(sc); 461 462 /* Disable rx and tx interrupts */ 463 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 464 465 /* Clear any pending interrupts */ 466 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 467 sc->sc_command | SEEQ_CMD_RX_INTACK | 468 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 469 SEEQ_CMD_BW_INTACK); 470 471 if (sc->sc_variant == SEEQ_8004) { 472 /* Put the chip to sleep */ 473 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 474 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 475 sc->sc_config3 | SEEQ_CFG3_SLEEP); 476 } 477 478 /* Cancel any watchdog timer */ 479 sc->sc_ethercom.ec_if.if_timer = 0; 480 } 481 482 483 /* 484 * Reset the chip 485 * Following this the software registers are reset 486 */ 487 488 static void 489 ea_chipreset(struct seeq8005_softc *sc) 490 { 491 bus_space_tag_t iot = sc->sc_iot; 492 bus_space_handle_t ioh = sc->sc_ioh; 493 494 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 495 496 /* Reset the controller. Min of 4us delay here */ 497 498 /* 499 * This can be called before we know whether the chip is in 8- or 500 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 501 * harmless in 8-bit mode, so we do that second. 502 */ 503 504 /* In 16-bit mode, this will munge the PreamSelect bit. */ 505 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 506 delay(4); 507 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 508 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 509 delay(4); 510 511 sc->sc_command = 0; 512 sc->sc_config1 = 0; 513 sc->sc_config2 = 0; 514 sc->sc_config3 = 0; 515 } 516 517 518 /* 519 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 520 * switching the FIFO from write to read. We also use it when changing 521 * the address for writes. 522 */ 523 static void 524 ea_await_fifo_empty(struct seeq8005_softc *sc) 525 { 526 bus_space_tag_t iot = sc->sc_iot; 527 bus_space_handle_t ioh = sc->sc_ioh; 528 int timeout; 529 530 timeout = 20000; 531 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 532 SEEQ_STATUS_FIFO_DIR) != 0) 533 return; /* FIFO is reading anyway. */ 534 while (--timeout > 0) 535 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 536 SEEQ_STATUS_FIFO_EMPTY) 537 return; 538 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", sc->sc_dev.dv_xname); 539 } 540 541 /* 542 * Wait for the DMA FIFO to fill before reading from it. 543 */ 544 static void 545 ea_await_fifo_full(struct seeq8005_softc *sc) 546 { 547 bus_space_tag_t iot = sc->sc_iot; 548 bus_space_handle_t ioh = sc->sc_ioh; 549 int timeout; 550 551 timeout = 20000; 552 while (--timeout > 0) 553 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 554 SEEQ_STATUS_FIFO_FULL) 555 return; 556 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", sc->sc_dev.dv_xname); 557 } 558 559 /* 560 * write to the buffer memory on the interface 561 * 562 * The buffer address is set to ADDR. 563 * If len != 0 then data is copied from the address starting at buf 564 * to the interface buffer. 565 * BUF must be usable as a u_int16_t *. 566 * If LEN is odd, it must be safe to overwrite one extra byte. 567 */ 568 569 static void 570 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 571 { 572 bus_space_tag_t iot = sc->sc_iot; 573 bus_space_handle_t ioh = sc->sc_ioh; 574 575 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 576 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 577 578 #ifdef DIAGNOSTIC 579 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 580 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 581 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 582 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 583 #endif 584 585 /* Assume that copying too much is safe. */ 586 if (len % 2 != 0) 587 len++; 588 589 if (addr != -1) { 590 ea_await_fifo_empty(sc); 591 592 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 593 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 594 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 595 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 596 } 597 598 if (len > 0) { 599 if (sc->sc_flags & SF_8BIT) 600 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 601 (u_int8_t *)buf, len); 602 else 603 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 604 (u_int16_t *)buf, len / 2); 605 } 606 /* Leave FIFO to empty in the background */ 607 } 608 609 610 /* 611 * read from the buffer memory on the interface 612 * 613 * The buffer address is set to ADDR. 614 * If len != 0 then data is copied from the interface buffer to the 615 * address starting at buf. 616 * BUF must be usable as a u_int16_t *. 617 * If LEN is odd, it must be safe to overwrite one extra byte. 618 */ 619 620 static void 621 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 622 { 623 bus_space_tag_t iot = sc->sc_iot; 624 bus_space_handle_t ioh = sc->sc_ioh; 625 int runup; 626 627 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 628 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 629 630 #ifdef DIAGNOSTIC 631 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 632 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 633 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 634 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 635 #endif 636 637 /* Assume that copying too much is safe. */ 638 if (len % 2 != 0) 639 len++; 640 641 if (addr != -1) { 642 /* 643 * SEEQ 80C04 bug: 644 * Starting reading from certain addresses seems to cause 645 * us to get bogus results, so we avoid them. 646 */ 647 runup = 0; 648 if (sc->sc_variant == SEEQ_8004 && 649 ((addr & 0x00ff) == 0x00ea || 650 (addr & 0x00ff) == 0x00ee || 651 (addr & 0x00ff) == 0x00f0)) 652 runup = (addr & 0x00ff) - 0x00e8; 653 654 ea_await_fifo_empty(sc); 655 656 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 657 658 /* 659 * 80C04 bug workaround. I found this in the old arm32 "eb" 660 * driver. I've no idea what it does, but it seems to stop 661 * the chip mangling data so often. 662 */ 663 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 664 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 665 ea_await_fifo_empty(sc); 666 667 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 668 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 669 sc->sc_command | SEEQ_CMD_FIFO_READ); 670 671 ea_await_fifo_full(sc); 672 while (runup > 0) { 673 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 674 runup -= 2; 675 } 676 } 677 678 if (len > 0) { 679 if (sc->sc_flags & SF_8BIT) 680 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 681 (u_int8_t *)buf, len); 682 else 683 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 684 (u_int16_t *)buf, len / 2); 685 } 686 } 687 688 static void 689 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 690 { 691 692 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 693 sc->sc_config1 | bufcode); 694 } 695 696 /* Must be called at splnet */ 697 static void 698 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 699 { 700 int i; 701 702 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 703 for (i = 0; i < ETHER_ADDR_LEN; ++i) 704 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 705 ea[i]); 706 } 707 708 /* 709 * Initialize interface. 710 * 711 * This should leave the interface in a state for packet reception and 712 * transmission. 713 */ 714 715 static int 716 ea_init(struct ifnet *ifp) 717 { 718 struct seeq8005_softc *sc = ifp->if_softc; 719 bus_space_tag_t iot = sc->sc_iot; 720 bus_space_handle_t ioh = sc->sc_ioh; 721 int s; 722 723 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 724 725 s = splnet(); 726 727 /* First, reset the board. */ 728 729 ea_chipreset(sc); 730 731 /* Set up defaults for the registers */ 732 733 sc->sc_command = 0; 734 sc->sc_config1 = 0; 735 #if BYTE_ORDER == BIG_ENDIAN 736 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 737 #else 738 sc->sc_config2 = 0; 739 #endif 740 sc->sc_config3 = 0; 741 742 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 743 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 744 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 745 if (sc->sc_variant == SEEQ_8004) { 746 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 747 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 748 } 749 750 /* Write the station address - the receiver must be off */ 751 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 752 753 /* Split board memory into Rx and Tx. */ 754 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 755 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 756 757 if (sc->sc_variant == SEEQ_8004) 758 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 759 760 /* Configure rx. */ 761 ea_mc_reset(sc); 762 if (ifp->if_flags & IFF_PROMISC) 763 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 764 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 765 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 766 else 767 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 768 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 769 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 770 771 /* Setup the Rx pointers */ 772 sc->sc_rx_ptr = sc->sc_tx_bufsize; 773 774 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 775 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 776 777 778 /* Place a NULL header at the beginning of the receive area */ 779 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 780 781 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 782 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 783 784 785 /* Configure TX. */ 786 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 787 788 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 789 790 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 791 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 792 793 /* Reset tx buffer pointers */ 794 sc->sc_tx_cur = 0; 795 sc->sc_tx_used = 0; 796 sc->sc_tx_next = 0; 797 798 /* Place a NULL header at the beginning of the transmit area */ 799 ea_writebuf(sc, NULL, 0x0000, 0); 800 801 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 802 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 803 804 sc->sc_command |= SEEQ_CMD_TX_INTEN; 805 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 806 807 /* Turn on Rx */ 808 sc->sc_command |= SEEQ_CMD_RX_INTEN; 809 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 810 sc->sc_command | SEEQ_CMD_RX_ON); 811 812 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 813 814 815 /* Set flags appropriately. */ 816 ifp->if_flags |= IFF_RUNNING; 817 ifp->if_flags &= ~IFF_OACTIVE; 818 sc->sc_enabled = 1; 819 820 /* And start output. */ 821 ea_start(ifp); 822 823 splx(s); 824 return 0; 825 } 826 827 /* 828 * Start output on interface. Get datagrams from the queue and output them, 829 * giving the receiver a chance between datagrams. Call only from splnet or 830 * interrupt level! 831 */ 832 833 static void 834 ea_start(struct ifnet *ifp) 835 { 836 struct seeq8005_softc *sc = ifp->if_softc; 837 int s; 838 839 s = splnet(); 840 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 841 842 /* 843 * Don't do anything if output is active. seeq8005intr() will call 844 * us (actually eatxpacket()) back when the card's ready for more 845 * frames. 846 */ 847 if (ifp->if_flags & IFF_OACTIVE) 848 return; 849 850 /* Mark interface as output active */ 851 852 ifp->if_flags |= IFF_OACTIVE; 853 854 /* tx packets */ 855 856 eatxpacket(sc); 857 splx(s); 858 } 859 860 861 /* 862 * Transfer a packet to the interface buffer and start transmission 863 * 864 * Called at splnet() 865 */ 866 867 void 868 eatxpacket(struct seeq8005_softc *sc) 869 { 870 bus_space_tag_t iot = sc->sc_iot; 871 bus_space_handle_t ioh = sc->sc_ioh; 872 struct mbuf *m0; 873 struct ifnet *ifp; 874 875 ifp = &sc->sc_ethercom.ec_if; 876 877 /* Dequeue the next packet. */ 878 IFQ_DEQUEUE(&ifp->if_snd, m0); 879 880 /* If there's nothing to send, return. */ 881 if (!m0) { 882 ifp->if_flags &= ~IFF_OACTIVE; 883 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 884 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 885 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 886 return; 887 } 888 889 #if NBPFILTER > 0 890 /* Give the packet to the bpf, if any. */ 891 if (ifp->if_bpf) 892 bpf_mtap(ifp->if_bpf, m0); 893 #endif 894 895 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 896 897 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 898 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 899 900 ea_writembuf(sc, m0, 0x0000); 901 m_freem(m0); 902 903 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 904 905 /* Now transmit the datagram. */ 906 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 907 sc->sc_command | SEEQ_CMD_TX_ON); 908 909 /* Make sure we notice if the chip goes silent on us. */ 910 ifp->if_timer = 5; 911 912 DPRINTF(SEEQ_DEBUG_TX, 913 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 914 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 915 } 916 917 /* 918 * Copy a packet from an mbuf to the transmit buffer on the card. 919 * 920 * Puts a valid Tx header at the start of the packet, and a null header at 921 * the end. 922 */ 923 static int 924 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 925 { 926 struct mbuf *m; 927 int len, nextpacket; 928 u_int8_t hdr[4]; 929 930 /* 931 * Copy the datagram to the packet buffer. 932 */ 933 len = 0; 934 for (m = m0; m; m = m->m_next) { 935 if (m->m_len == 0) 936 continue; 937 ea_writebuf(sc, mtod(m, caddr_t), bufstart + 4 + len, 938 m->m_len); 939 len += m->m_len; 940 } 941 942 len = max(len, ETHER_MIN_LEN); 943 944 /* Follow it with a NULL packet header */ 945 memset(hdr, 0, 4); 946 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 947 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 948 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 949 950 /* Ok we now have a packet len bytes long in our packet buffer */ 951 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 952 953 /* Write the packet header */ 954 nextpacket = len + 4; 955 hdr[0] = (nextpacket >> 8) & 0xff; 956 hdr[1] = nextpacket & 0xff; 957 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 958 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 959 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 960 ea_writebuf(sc, hdr, 0x0000, 4); 961 962 return len; 963 } 964 965 /* 966 * Ethernet controller interrupt. 967 */ 968 969 int 970 seeq8005intr(void *arg) 971 { 972 struct seeq8005_softc *sc = arg; 973 bus_space_tag_t iot = sc->sc_iot; 974 bus_space_handle_t ioh = sc->sc_ioh; 975 int status, handled; 976 977 handled = 0; 978 979 /* Get the controller status */ 980 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 981 982 /* Tx interrupt ? */ 983 if (status & SEEQ_STATUS_TX_INT) { 984 handled = 1; 985 986 /* Acknowledge the interrupt */ 987 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 988 sc->sc_command | SEEQ_CMD_TX_INTACK); 989 990 ea_txint(sc); 991 } 992 993 994 /* Rx interrupt ? */ 995 if (status & SEEQ_STATUS_RX_INT) { 996 handled = 1; 997 998 /* Acknowledge the interrupt */ 999 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1000 sc->sc_command | SEEQ_CMD_RX_INTACK); 1001 1002 /* Processes the received packets */ 1003 ea_rxint(sc); 1004 } 1005 1006 return handled; 1007 } 1008 1009 static void 1010 ea_txint(struct seeq8005_softc *sc) 1011 { 1012 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1013 bus_space_tag_t iot = sc->sc_iot; 1014 bus_space_handle_t ioh = sc->sc_ioh; 1015 u_int8_t txhdr[4]; 1016 u_int txstatus; 1017 1018 ea_readbuf(sc, txhdr, 0x0000, 4); 1019 1020 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1021 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1022 txstatus = txhdr[3]; 1023 1024 /* 1025 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1026 * one collision. On the 8004 we can find out exactly how many 1027 * collisions occurred. 1028 * 1029 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1030 * completed. 1031 * 1032 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1033 * occurred and the packet transmission was aborted. 1034 * This situation is untested as present. 1035 * 1036 * The SEEQ_TXSTAT_BABBLE should never be set and is untested 1037 * as we should never xmit oversized packets. 1038 */ 1039 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1040 switch (sc->sc_variant) { 1041 case SEEQ_8004: { 1042 int colls; 1043 1044 /* 1045 * The 8004 contains a 4 bit collision count 1046 * in the status register. 1047 */ 1048 1049 /* This appears to be broken on 80C04.AE */ 1050 /* ifp->if_collisions += 1051 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1052 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1053 1054 /* Use the TX Collision register */ 1055 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1056 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1057 ifp->if_collisions += colls; 1058 break; 1059 } 1060 case SEEQ_8005: 1061 /* We known there was at least 1 collision */ 1062 ifp->if_collisions++; 1063 break; 1064 } 1065 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1066 printf("seeq_intr: col16 %x\n", txstatus); 1067 ifp->if_collisions += 16; 1068 ifp->if_oerrors++; 1069 } else if (txstatus & SEEQ_TXSTAT_BABBLE) { 1070 ifp->if_oerrors++; 1071 } 1072 1073 /* Have we completed transmission on the packet ? */ 1074 if (txstatus & SEEQ_PKTSTAT_DONE) { 1075 /* Clear watchdog timer. */ 1076 ifp->if_timer = 0; 1077 ifp->if_flags &= ~IFF_OACTIVE; 1078 1079 /* Update stats */ 1080 ifp->if_opackets++; 1081 1082 /* Tx next packet */ 1083 1084 eatxpacket(sc); 1085 } 1086 } 1087 1088 void 1089 ea_rxint(struct seeq8005_softc *sc) 1090 { 1091 bus_space_tag_t iot = sc->sc_iot; 1092 bus_space_handle_t ioh = sc->sc_ioh; 1093 u_int addr; 1094 int len; 1095 int ctrl; 1096 int ptr; 1097 int pack; 1098 int status; 1099 u_int8_t rxhdr[4]; 1100 struct ifnet *ifp; 1101 1102 ifp = &sc->sc_ethercom.ec_if; 1103 1104 1105 /* We start from the last rx pointer position */ 1106 addr = sc->sc_rx_ptr; 1107 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1108 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1109 1110 do { 1111 /* Read rx header */ 1112 ea_readbuf(sc, rxhdr, addr, 4); 1113 1114 /* Split the packet header */ 1115 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1116 ctrl = rxhdr[2]; 1117 status = rxhdr[3]; 1118 1119 DPRINTF(SEEQ_DEBUG_RX, 1120 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1121 addr, ptr, ctrl, status)); 1122 1123 /* Zero packet ptr ? then must be null header so exit */ 1124 if (ptr == 0) break; 1125 1126 /* Sanity-check the next-packet pointer and flags. */ 1127 if (__predict_false(ptr < sc->sc_tx_bufsize || 1128 (ctrl & SEEQ_PKTCMD_TX))) { 1129 ++ifp->if_ierrors; 1130 log(LOG_ERR, 1131 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1132 sc->sc_dev.dv_xname, addr, ptr); 1133 ea_init(ifp); 1134 return; 1135 } 1136 1137 /* Get packet length */ 1138 len = (ptr - addr) - 4; 1139 1140 if (len < 0) 1141 len += sc->sc_rx_bufsize; 1142 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1143 1144 /* Has the packet rx completed ? if not then exit */ 1145 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1146 break; 1147 1148 /* 1149 * Did we have any errors? then note error and go to 1150 * next packet 1151 */ 1152 if (__predict_false(status & SEEQ_RXSTAT_ERROR_MASK)) { 1153 ++ifp->if_ierrors; 1154 /* XXX oversize packets may be OK */ 1155 log(LOG_WARNING, 1156 "%s: rx packet error at %04x (err=%02x)\n", 1157 sc->sc_dev.dv_xname, addr, status & 0x0f); 1158 /* XXX shouldn't need to reset if it's genuine. */ 1159 ea_init(ifp); 1160 return; 1161 } 1162 /* 1163 * Is the packet too big ? - this will probably be trapped 1164 * above as a receive error. If it's not, this is indicative 1165 * of buffer corruption. 1166 */ 1167 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1168 ++ifp->if_ierrors; 1169 log(LOG_ERR, 1170 "%s: rx packet size error at %04x (len=%d)\n", 1171 sc->sc_dev.dv_xname, addr, len); 1172 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1173 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, 1174 sc->sc_config2); 1175 ea_init(ifp); 1176 return; 1177 } 1178 1179 ifp->if_ipackets++; 1180 /* Pass data up to upper levels. */ 1181 ea_read(sc, addr + 4, len); 1182 1183 addr = ptr; 1184 ++pack; 1185 } while (len != 0); 1186 1187 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1188 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1189 1190 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1191 1192 /* Store new rx pointer */ 1193 sc->sc_rx_ptr = addr; 1194 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1195 1196 /* Make sure the receiver is on */ 1197 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1198 sc->sc_command | SEEQ_CMD_RX_ON); 1199 } 1200 1201 1202 /* 1203 * Pass a packet up to the higher levels. 1204 */ 1205 1206 static void 1207 ea_read(struct seeq8005_softc *sc, int addr, int len) 1208 { 1209 struct mbuf *m; 1210 struct ifnet *ifp; 1211 1212 ifp = &sc->sc_ethercom.ec_if; 1213 1214 /* Pull packet off interface. */ 1215 m = ea_get(sc, addr, len, ifp); 1216 if (m == 0) 1217 return; 1218 1219 #if NBPFILTER > 0 1220 /* 1221 * Check if there's a BPF listener on this interface. 1222 * If so, hand off the raw packet to bpf. 1223 */ 1224 if (ifp->if_bpf) 1225 bpf_mtap(ifp->if_bpf, m); 1226 #endif 1227 1228 (*ifp->if_input)(ifp, m); 1229 } 1230 1231 /* 1232 * Pull read data off a interface. Len is length of data, with local net 1233 * header stripped. We copy the data into mbufs. When full cluster sized 1234 * units are present we copy into clusters. 1235 */ 1236 1237 struct mbuf * 1238 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1239 { 1240 struct mbuf *top, **mp, *m; 1241 int len; 1242 u_int cp, epkt; 1243 1244 cp = addr; 1245 epkt = cp + totlen; 1246 1247 MGETHDR(m, M_DONTWAIT, MT_DATA); 1248 if (m == 0) 1249 return 0; 1250 m->m_pkthdr.rcvif = ifp; 1251 m->m_pkthdr.len = totlen; 1252 m->m_len = MHLEN; 1253 top = 0; 1254 mp = ⊤ 1255 1256 while (totlen > 0) { 1257 if (top) { 1258 MGET(m, M_DONTWAIT, MT_DATA); 1259 if (m == 0) { 1260 m_freem(top); 1261 return 0; 1262 } 1263 m->m_len = MLEN; 1264 } 1265 len = min(totlen, epkt - cp); 1266 if (len >= MINCLSIZE) { 1267 MCLGET(m, M_DONTWAIT); 1268 if (m->m_flags & M_EXT) 1269 m->m_len = len = min(len, MCLBYTES); 1270 else 1271 len = m->m_len; 1272 } else { 1273 /* 1274 * Place initial small packet/header at end of mbuf. 1275 */ 1276 if (len < m->m_len) { 1277 if (top == 0 && len + max_linkhdr <= m->m_len) 1278 m->m_data += max_linkhdr; 1279 m->m_len = len; 1280 } else 1281 len = m->m_len; 1282 } 1283 if (top == 0) { 1284 /* Make sure the payload is aligned */ 1285 caddr_t newdata = (caddr_t) 1286 ALIGN(m->m_data + sizeof(struct ether_header)) - 1287 sizeof(struct ether_header); 1288 len -= newdata - m->m_data; 1289 m->m_len = len; 1290 m->m_data = newdata; 1291 } 1292 ea_readbuf(sc, mtod(m, u_char *), 1293 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1294 len); 1295 cp += len; 1296 *mp = m; 1297 mp = &m->m_next; 1298 totlen -= len; 1299 if (cp == epkt) 1300 cp = addr; 1301 } 1302 1303 return top; 1304 } 1305 1306 /* 1307 * Process an ioctl request. Mostly boilerplate. 1308 */ 1309 static int 1310 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1311 { 1312 struct seeq8005_softc *sc = ifp->if_softc; 1313 int s, error = 0; 1314 1315 s = splnet(); 1316 switch (cmd) { 1317 1318 default: 1319 error = ether_ioctl(ifp, cmd, data); 1320 if (error == ENETRESET) { 1321 /* 1322 * Multicast list has changed; set the hardware filter 1323 * accordingly. 1324 */ 1325 ea_mc_reset(sc); 1326 error = 0; 1327 } 1328 break; 1329 } 1330 1331 splx(s); 1332 return error; 1333 } 1334 1335 /* Must be called at splnet() */ 1336 1337 static void 1338 ea_mc_reset(struct seeq8005_softc *sc) 1339 { 1340 1341 switch (sc->sc_variant) { 1342 case SEEQ_8004: 1343 ea_mc_reset_8004(sc); 1344 return; 1345 case SEEQ_8005: 1346 ea_mc_reset_8005(sc); 1347 return; 1348 } 1349 } 1350 1351 static void 1352 ea_mc_reset_8004(struct seeq8005_softc *sc) 1353 { 1354 struct ethercom *ec = &sc->sc_ethercom; 1355 struct ifnet *ifp = &ec->ec_if; 1356 struct ether_multi *enm; 1357 u_int32_t crc; 1358 int i; 1359 struct ether_multistep step; 1360 u_int8_t af[8]; 1361 1362 /* 1363 * Set up multicast address filter by passing all multicast addresses 1364 * through a crc generator, and then using bits 2 - 7 as an index 1365 * into the 64 bit logical address filter. The high order bits 1366 * selects the word, while the rest of the bits select the bit within 1367 * the word. 1368 */ 1369 1370 if (ifp->if_flags & IFF_PROMISC) { 1371 ifp->if_flags |= IFF_ALLMULTI; 1372 for (i = 0; i < 8; i++) 1373 af[i] = 0xff; 1374 return; 1375 } 1376 for (i = 0; i < 8; i++) 1377 af[i] = 0; 1378 ETHER_FIRST_MULTI(step, ec, enm); 1379 while (enm != NULL) { 1380 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1381 sizeof(enm->enm_addrlo)) != 0) { 1382 /* 1383 * We must listen to a range of multicast addresses. 1384 * For now, just accept all multicasts, rather than 1385 * trying to set only those filter bits needed to match 1386 * the range. (At this time, the only use of address 1387 * ranges is for IP multicast routing, for which the 1388 * range is big enough to require all bits set.) 1389 */ 1390 ifp->if_flags |= IFF_ALLMULTI; 1391 for (i = 0; i < 8; i++) 1392 af[i] = 0xff; 1393 break; 1394 } 1395 1396 crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1397 1398 /* Just want the 6 most significant bits. */ 1399 crc = (crc >> 2) & 0x3f; 1400 1401 /* Turn on the corresponding bit in the filter. */ 1402 af[crc >> 3] |= 1 << (crc & 0x7); 1403 1404 ETHER_NEXT_MULTI(step, enm); 1405 } 1406 ifp->if_flags &= ~IFF_ALLMULTI; 1407 1408 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1409 for (i = 0; i < 8; ++i) 1410 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1411 SEEQ_BUFWIN, af[i]); 1412 } 1413 1414 static void 1415 ea_mc_reset_8005(struct seeq8005_softc *sc) 1416 { 1417 struct ether_multi *enm; 1418 struct ether_multistep step; 1419 int naddr, maxaddrs; 1420 1421 naddr = 0; 1422 maxaddrs = 5; 1423 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1424 while (enm != NULL) { 1425 /* Have we got space? */ 1426 if (naddr >= maxaddrs || 1427 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1428 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1429 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1430 return; 1431 } 1432 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1433 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1434 naddr++; 1435 ETHER_NEXT_MULTI(step, enm); 1436 } 1437 for (; naddr < maxaddrs; naddr++) 1438 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1439 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1440 sc->sc_config1); 1441 } 1442 1443 /* 1444 * Device timeout routine. 1445 */ 1446 1447 static void 1448 ea_watchdog(struct ifnet *ifp) 1449 { 1450 struct seeq8005_softc *sc = ifp->if_softc; 1451 1452 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1453 sc->sc_dev.dv_xname, 1454 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1455 ifp->if_oerrors++; 1456 1457 /* Kick the interface */ 1458 1459 ea_init(ifp); 1460 1461 ifp->if_timer = 0; 1462 } 1463 1464 /* End of if_ea.c */ 1465
Indexes created Tue Sep 30 11:09:46 GMT 2025