seeq8005.c revision 1.27
1 /* $NetBSD: seeq8005.c,v 1.27 2001/06/26 22:00:44 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45 /* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52 /* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56 /* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 66 __RCSID("$NetBSD: seeq8005.c,v 1.27 2001/06/26 22:00:44 bjh21 Exp $"); 67 68 #include <sys/systm.h> 69 #include <sys/endian.h> 70 #include <sys/errno.h> 71 #include <sys/ioctl.h> 72 #include <sys/mbuf.h> 73 #include <sys/socket.h> 74 #include <sys/syslog.h> 75 #include <sys/device.h> 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 #include <net/if_ether.h> 81 #include <net/if_media.h> 82 83 #include "bpfilter.h" 84 #if NBPFILTER > 0 85 #include <net/bpf.h> 86 #include <net/bpfdesc.h> 87 #endif 88 89 #include <machine/bus.h> 90 #include <machine/intr.h> 91 92 #include <dev/ic/seeq8005reg.h> 93 #include <dev/ic/seeq8005var.h> 94 95 /*#define SEEQ_DEBUG*/ 96 97 /* for debugging convenience */ 98 #ifdef SEEQ8005_DEBUG 99 #define SEEQ_DEBUG_MISC 1 100 #define SEEQ_DEBUG_TX 2 101 #define SEEQ_DEBUG_RX 4 102 #define SEEQ_DEBUG_PKT 8 103 #define SEEQ_DEBUG_TXINT 16 104 #define SEEQ_DEBUG_RXINT 32 105 int seeq8005_debug = 0; 106 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 107 #else 108 #define DPRINTF(f, x) 109 #endif 110 111 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> ETHER_MAX_LEN) */ 112 113 #define SEEQ_READ16(sc, iot, ioh, reg) \ 114 ((sc)->sc_flags & SF_8BIT ? \ 115 (bus_space_read_1((iot), (ioh), (reg)) | \ 116 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 117 (bus_space_read_2((iot), (ioh), (reg)))) 118 119 #define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 120 if ((sc)->sc_flags & SF_8BIT) { \ 121 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 122 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 123 } else \ 124 bus_space_write_2((iot), (ioh), (reg), (val)); \ 125 } while (/*CONSTCOND*/0) 126 127 /* 128 * prototypes 129 */ 130 131 static int ea_init(struct ifnet *); 132 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 133 static void ea_start(struct ifnet *); 134 static void ea_watchdog(struct ifnet *); 135 static void ea_chipreset(struct seeq8005_softc *); 136 static void ea_ramtest(struct seeq8005_softc *); 137 static int ea_stoptx(struct seeq8005_softc *); 138 static int ea_stoprx(struct seeq8005_softc *); 139 static void ea_stop(struct ifnet *, int); 140 static void ea_await_fifo_empty(struct seeq8005_softc *); 141 static void ea_await_fifo_full(struct seeq8005_softc *); 142 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 143 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_select_buffer(struct seeq8005_softc *, int); 145 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 146 static void ea_read(struct seeq8005_softc *, int, int); 147 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 148 static void ea_txint(struct seeq8005_softc *); 149 static void ea_rxint(struct seeq8005_softc *); 150 static void eatxpacket(struct seeq8005_softc *); 151 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 152 static void ea_mc_reset(struct seeq8005_softc *); 153 static void ea_mc_reset_8004(struct seeq8005_softc *); 154 static void ea_mc_reset_8005(struct seeq8005_softc *); 155 static int ea_mediachange(struct ifnet *); 156 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 157 158 159 /* 160 * Attach chip. 161 */ 162 163 void 164 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 165 int nmedia, int defmedia) 166 { 167 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 168 bus_space_tag_t iot = sc->sc_iot; 169 bus_space_handle_t ioh = sc->sc_ioh; 170 u_int id; 171 172 KASSERT(myaddr != NULL); 173 printf(" address %s", ether_sprintf(myaddr)); 174 175 /* Stop the board. */ 176 177 ea_chipreset(sc); 178 179 /* Work out data bus width. */ 180 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 181 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 182 /* Try 8-bit mode */ 183 sc->sc_flags |= SF_8BIT; 184 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 185 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 186 printf("\n%s: Cannot determine data bus width\n", 187 sc->sc_dev.dv_xname); 188 return; 189 } 190 } 191 192 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 193 194 /* Get the product ID */ 195 196 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 197 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 198 199 switch (id & SEEQ_PRODUCTID_MASK) { 200 case SEEQ_PRODUCTID_8004: 201 sc->sc_variant = SEEQ_8004; 202 switch (id & SEEQ_PRODUCTID_REV_MASK) { 203 case SEEQ_PRODUCTID_REV_80C04: 204 printf(", SEEQ 80C04\n"); 205 break; 206 case SEEQ_PRODUCTID_REV_80C04A: 207 printf(", SEEQ 80C04A\n"); 208 break; 209 default: 210 /* Unknown SEEQ 8004 variants */ 211 printf(", SEEQ 8004 rev %x\n", 212 id & SEEQ_PRODUCTID_REV_MASK); 213 break; 214 } 215 break; 216 default: /* XXX */ 217 sc->sc_variant = SEEQ_8005; 218 printf(", SEEQ 8005\n"); 219 break; 220 } 221 222 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 223 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 224 225 /* 226 * Set up tx and rx buffers. 227 * 228 * We use approximately a quarter of the packet memory for TX 229 * buffers and the rest for RX buffers 230 */ 231 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 232 sc->sc_tx_bufs = 1; 233 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 234 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 235 sc->sc_enabled = 0; 236 237 /* Test the RAM */ 238 ea_ramtest(sc); 239 240 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 241 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 242 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 243 244 /* Initialise ifnet structure. */ 245 246 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 247 ifp->if_softc = sc; 248 ifp->if_start = ea_start; 249 ifp->if_ioctl = ea_ioctl; 250 ifp->if_init = ea_init; 251 ifp->if_stop = ea_stop; 252 ifp->if_watchdog = ea_watchdog; 253 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 254 if (sc->sc_variant == SEEQ_8004) 255 ifp->if_flags |= IFF_SIMPLEX; 256 IFQ_SET_READY(&ifp->if_snd); 257 258 /* Initialize media goo. */ 259 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 260 if (media != NULL) { 261 int i; 262 263 for (i = 0; i < nmedia; i++) 264 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 265 ifmedia_set(&sc->sc_media, defmedia); 266 } else { 267 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 268 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 269 } 270 271 /* We can support 802.1Q VLAN-sized frames. */ 272 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 273 274 /* Now we can attach the interface. */ 275 276 if_attach(ifp); 277 ether_ifattach(ifp, myaddr); 278 279 printf("\n"); 280 } 281 282 /* 283 * Media change callback. 284 */ 285 static int 286 ea_mediachange(struct ifnet *ifp) 287 { 288 struct seeq8005_softc *sc = ifp->if_softc; 289 290 if (sc->sc_mediachange) 291 return ((*sc->sc_mediachange)(sc)); 292 return (EINVAL); 293 } 294 295 /* 296 * Media status callback. 297 */ 298 static void 299 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 300 { 301 struct seeq8005_softc *sc = ifp->if_softc; 302 303 if (sc->sc_enabled == 0) { 304 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 305 ifmr->ifm_status = 0; 306 return; 307 } 308 309 if (sc->sc_mediastatus) 310 (*sc->sc_mediastatus)(sc, ifmr); 311 } 312 313 /* 314 * Test the RAM on the ethernet card. 315 */ 316 317 void 318 ea_ramtest(struct seeq8005_softc *sc) 319 { 320 bus_space_tag_t iot = sc->sc_iot; 321 bus_space_handle_t ioh = sc->sc_ioh; 322 int loop; 323 u_int sum = 0; 324 325 /* 326 * Test the buffer memory on the board. 327 * Write simple pattens to it and read them back. 328 */ 329 330 /* Set up the whole buffer RAM for writing */ 331 332 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 333 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 334 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 335 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 336 337 #define SEEQ_RAMTEST_LOOP(value) \ 338 do { \ 339 /* Set the write start address and write a pattern */ \ 340 ea_writebuf(sc, NULL, 0x0000, 0); \ 341 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 342 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 343 \ 344 /* Set the read start address and verify the pattern */ \ 345 ea_readbuf(sc, NULL, 0x0000, 0); \ 346 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 347 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 348 ++sum; \ 349 } while (/*CONSTCOND*/0) 350 351 SEEQ_RAMTEST_LOOP(loop); 352 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 353 SEEQ_RAMTEST_LOOP(0xaa55); 354 SEEQ_RAMTEST_LOOP(0x55aa); 355 356 /* Report */ 357 358 if (sum > 0) 359 printf("%s: buffer RAM failed self test, %d faults\n", 360 sc->sc_dev.dv_xname, sum); 361 } 362 363 364 /* 365 * Stop the tx interface. 366 * 367 * Returns 0 if the tx was already stopped or 1 if it was active 368 */ 369 370 static int 371 ea_stoptx(struct seeq8005_softc *sc) 372 { 373 bus_space_tag_t iot = sc->sc_iot; 374 bus_space_handle_t ioh = sc->sc_ioh; 375 int timeout; 376 int status; 377 378 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 379 380 sc->sc_enabled = 0; 381 382 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 383 if (!(status & SEEQ_STATUS_TX_ON)) 384 return 0; 385 386 /* Stop any tx and wait for confirmation */ 387 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 388 sc->sc_command | SEEQ_CMD_TX_OFF); 389 390 timeout = 20000; 391 do { 392 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 393 delay(1); 394 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 395 if (timeout == 0) 396 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 397 sc->sc_dev.dv_xname); 398 399 /* Clear any pending tx interrupt */ 400 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 401 sc->sc_command | SEEQ_CMD_TX_INTACK); 402 return 1; 403 } 404 405 406 /* 407 * Stop the rx interface. 408 * 409 * Returns 0 if the tx was already stopped or 1 if it was active 410 */ 411 412 static int 413 ea_stoprx(struct seeq8005_softc *sc) 414 { 415 bus_space_tag_t iot = sc->sc_iot; 416 bus_space_handle_t ioh = sc->sc_ioh; 417 int timeout; 418 int status; 419 420 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 421 422 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 423 if (!(status & SEEQ_STATUS_RX_ON)) 424 return 0; 425 426 /* Stop any rx and wait for confirmation */ 427 428 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 429 sc->sc_command | SEEQ_CMD_RX_OFF); 430 431 timeout = 20000; 432 do { 433 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 434 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 435 if (timeout == 0) 436 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 437 sc->sc_dev.dv_xname); 438 439 /* Clear any pending rx interrupt */ 440 441 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 442 sc->sc_command | SEEQ_CMD_RX_INTACK); 443 return 1; 444 } 445 446 447 /* 448 * Stop interface. 449 * Stop all IO and shut the interface down 450 */ 451 452 static void 453 ea_stop(struct ifnet *ifp, int disable) 454 { 455 struct seeq8005_softc *sc = ifp->if_softc; 456 bus_space_tag_t iot = sc->sc_iot; 457 bus_space_handle_t ioh = sc->sc_ioh; 458 459 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 460 461 /* Stop all IO */ 462 ea_stoptx(sc); 463 ea_stoprx(sc); 464 465 /* Disable rx and tx interrupts */ 466 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 467 468 /* Clear any pending interrupts */ 469 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 470 sc->sc_command | SEEQ_CMD_RX_INTACK | 471 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 472 SEEQ_CMD_BW_INTACK); 473 474 if (sc->sc_variant == SEEQ_8004) { 475 /* Put the chip to sleep */ 476 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 477 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 478 sc->sc_config3 | SEEQ_CFG3_SLEEP); 479 } 480 481 /* Cancel any watchdog timer */ 482 sc->sc_ethercom.ec_if.if_timer = 0; 483 } 484 485 486 /* 487 * Reset the chip 488 * Following this the software registers are reset 489 */ 490 491 static void 492 ea_chipreset(struct seeq8005_softc *sc) 493 { 494 bus_space_tag_t iot = sc->sc_iot; 495 bus_space_handle_t ioh = sc->sc_ioh; 496 497 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 498 499 /* Reset the controller. Min of 4us delay here */ 500 501 /* 502 * This can be called before we know whether the chip is in 8- or 503 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 504 * harmless in 8-bit mode, so we do that second. 505 */ 506 507 /* In 16-bit mode, this will munge the PreamSelect bit. */ 508 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 509 delay(4); 510 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 511 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 512 delay(4); 513 514 sc->sc_command = 0; 515 sc->sc_config1 = 0; 516 sc->sc_config2 = 0; 517 sc->sc_config3 = 0; 518 } 519 520 521 /* 522 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 523 * switching the FIFO from write to read. We also use it when changing 524 * the address for writes. 525 */ 526 static void 527 ea_await_fifo_empty(struct seeq8005_softc *sc) 528 { 529 bus_space_tag_t iot = sc->sc_iot; 530 bus_space_handle_t ioh = sc->sc_ioh; 531 int timeout; 532 533 timeout = 20000; 534 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 535 SEEQ_STATUS_FIFO_DIR) != 0) 536 return; /* FIFO is reading anyway. */ 537 while (--timeout > 0) 538 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 539 SEEQ_STATUS_FIFO_EMPTY) 540 return; 541 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", sc->sc_dev.dv_xname); 542 } 543 544 /* 545 * Wait for the DMA FIFO to fill before reading from it. 546 */ 547 static void 548 ea_await_fifo_full(struct seeq8005_softc *sc) 549 { 550 bus_space_tag_t iot = sc->sc_iot; 551 bus_space_handle_t ioh = sc->sc_ioh; 552 int timeout; 553 554 timeout = 20000; 555 while (--timeout > 0) 556 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 557 SEEQ_STATUS_FIFO_FULL) 558 return; 559 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", sc->sc_dev.dv_xname); 560 } 561 562 /* 563 * write to the buffer memory on the interface 564 * 565 * The buffer address is set to ADDR. 566 * If len != 0 then data is copied from the address starting at buf 567 * to the interface buffer. 568 * BUF must be usable as a u_int16_t *. 569 * If LEN is odd, it must be safe to overwrite one extra byte. 570 */ 571 572 static void 573 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 574 { 575 bus_space_tag_t iot = sc->sc_iot; 576 bus_space_handle_t ioh = sc->sc_ioh; 577 578 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 579 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 580 581 #ifdef DIAGNOSTIC 582 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 583 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 584 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 585 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 586 #endif 587 588 /* Assume that copying too much is safe. */ 589 if (len % 2 != 0) 590 len++; 591 592 if (addr != -1) { 593 ea_await_fifo_empty(sc); 594 595 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 596 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 597 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 598 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 599 } 600 601 if (len > 0) { 602 if (sc->sc_flags & SF_8BIT) 603 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 604 (u_int8_t *)buf, len); 605 else 606 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 607 (u_int16_t *)buf, len / 2); 608 } 609 /* Leave FIFO to empty in the background */ 610 } 611 612 613 /* 614 * read from the buffer memory on the interface 615 * 616 * The buffer address is set to ADDR. 617 * If len != 0 then data is copied from the interface buffer to the 618 * address starting at buf. 619 * BUF must be usable as a u_int16_t *. 620 * If LEN is odd, it must be safe to overwrite one extra byte. 621 */ 622 623 static void 624 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 625 { 626 bus_space_tag_t iot = sc->sc_iot; 627 bus_space_handle_t ioh = sc->sc_ioh; 628 int runup; 629 630 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 631 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 632 633 #ifdef DIAGNOSTIC 634 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 635 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 636 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 637 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 638 #endif 639 640 /* Assume that copying too much is safe. */ 641 if (len % 2 != 0) 642 len++; 643 644 if (addr != -1) { 645 /* 646 * SEEQ 80C04 bug: 647 * Starting reading from certain addresses seems to cause 648 * us to get bogus results, so we avoid them. 649 */ 650 runup = 0; 651 if (sc->sc_variant == SEEQ_8004 && 652 ((addr & 0x00ff) == 0x00ea || 653 (addr & 0x00ff) == 0x00ee || 654 (addr & 0x00ff) == 0x00f0)) 655 runup = (addr & 0x00ff) - 0x00e8; 656 657 ea_await_fifo_empty(sc); 658 659 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 660 661 /* 662 * 80C04 bug workaround. I found this in the old arm32 "eb" 663 * driver. I've no idea what it does, but it seems to stop 664 * the chip mangling data so often. 665 */ 666 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 667 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 668 ea_await_fifo_empty(sc); 669 670 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 671 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 672 sc->sc_command | SEEQ_CMD_FIFO_READ); 673 674 ea_await_fifo_full(sc); 675 while (runup > 0) { 676 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 677 runup -= 2; 678 } 679 } 680 681 if (len > 0) { 682 if (sc->sc_flags & SF_8BIT) 683 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 684 (u_int8_t *)buf, len); 685 else 686 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 687 (u_int16_t *)buf, len / 2); 688 } 689 } 690 691 static void 692 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 693 { 694 695 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 696 sc->sc_config1 | bufcode); 697 } 698 699 /* Must be called at splnet */ 700 static void 701 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 702 { 703 int i; 704 705 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 706 for (i = 0; i < ETHER_ADDR_LEN; ++i) 707 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 708 ea[i]); 709 } 710 711 /* 712 * Initialize interface. 713 * 714 * This should leave the interface in a state for packet reception and 715 * transmission. 716 */ 717 718 static int 719 ea_init(struct ifnet *ifp) 720 { 721 struct seeq8005_softc *sc = ifp->if_softc; 722 bus_space_tag_t iot = sc->sc_iot; 723 bus_space_handle_t ioh = sc->sc_ioh; 724 int s; 725 726 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 727 728 s = splnet(); 729 730 /* First, reset the board. */ 731 732 ea_chipreset(sc); 733 734 /* Set up defaults for the registers */ 735 736 sc->sc_command = 0; 737 sc->sc_config1 = 0; 738 #if BYTE_ORDER == BIG_ENDIAN 739 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 740 #else 741 sc->sc_config2 = 0; 742 #endif 743 sc->sc_config3 = 0; 744 745 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 746 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 747 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 748 if (sc->sc_variant == SEEQ_8004) { 749 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 750 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 751 } 752 753 /* Write the station address - the receiver must be off */ 754 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 755 756 /* Split board memory into Rx and Tx. */ 757 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 758 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 759 760 if (sc->sc_variant == SEEQ_8004) { 761 /* Make the interface IFF_SIMPLEX. */ 762 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 763 /* Enable reception of long packets (for vlan(4)). */ 764 sc->sc_config2 |= SEEQ_CFG2_PASS_LONGSHORT; 765 } 766 767 /* Configure rx. */ 768 ea_mc_reset(sc); 769 if (ifp->if_flags & IFF_PROMISC) 770 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 771 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 772 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 773 else 774 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 775 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 776 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 777 778 /* Setup the Rx pointers */ 779 sc->sc_rx_ptr = sc->sc_tx_bufsize; 780 781 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 782 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 783 784 785 /* Place a NULL header at the beginning of the receive area */ 786 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 787 788 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 789 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 790 791 792 /* Configure TX. */ 793 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 794 795 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 796 797 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 798 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 799 800 /* Reset tx buffer pointers */ 801 sc->sc_tx_cur = 0; 802 sc->sc_tx_used = 0; 803 sc->sc_tx_next = 0; 804 805 /* Place a NULL header at the beginning of the transmit area */ 806 ea_writebuf(sc, NULL, 0x0000, 0); 807 808 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 809 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 810 811 sc->sc_command |= SEEQ_CMD_TX_INTEN; 812 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 813 814 /* Turn on Rx */ 815 sc->sc_command |= SEEQ_CMD_RX_INTEN; 816 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 817 sc->sc_command | SEEQ_CMD_RX_ON); 818 819 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 820 821 822 /* Set flags appropriately. */ 823 ifp->if_flags |= IFF_RUNNING; 824 ifp->if_flags &= ~IFF_OACTIVE; 825 sc->sc_enabled = 1; 826 827 /* And start output. */ 828 ea_start(ifp); 829 830 splx(s); 831 return 0; 832 } 833 834 /* 835 * Start output on interface. Get datagrams from the queue and output them, 836 * giving the receiver a chance between datagrams. Call only from splnet or 837 * interrupt level! 838 */ 839 840 static void 841 ea_start(struct ifnet *ifp) 842 { 843 struct seeq8005_softc *sc = ifp->if_softc; 844 int s; 845 846 s = splnet(); 847 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 848 849 /* 850 * Don't do anything if output is active. seeq8005intr() will call 851 * us (actually eatxpacket()) back when the card's ready for more 852 * frames. 853 */ 854 if (ifp->if_flags & IFF_OACTIVE) 855 return; 856 857 /* Mark interface as output active */ 858 859 ifp->if_flags |= IFF_OACTIVE; 860 861 /* tx packets */ 862 863 eatxpacket(sc); 864 splx(s); 865 } 866 867 868 /* 869 * Transfer a packet to the interface buffer and start transmission 870 * 871 * Called at splnet() 872 */ 873 874 void 875 eatxpacket(struct seeq8005_softc *sc) 876 { 877 bus_space_tag_t iot = sc->sc_iot; 878 bus_space_handle_t ioh = sc->sc_ioh; 879 struct mbuf *m0; 880 struct ifnet *ifp; 881 882 ifp = &sc->sc_ethercom.ec_if; 883 884 /* Dequeue the next packet. */ 885 IFQ_DEQUEUE(&ifp->if_snd, m0); 886 887 /* If there's nothing to send, return. */ 888 if (!m0) { 889 ifp->if_flags &= ~IFF_OACTIVE; 890 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 891 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 892 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 893 return; 894 } 895 896 #if NBPFILTER > 0 897 /* Give the packet to the bpf, if any. */ 898 if (ifp->if_bpf) 899 bpf_mtap(ifp->if_bpf, m0); 900 #endif 901 902 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 903 904 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 905 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 906 907 ea_writembuf(sc, m0, 0x0000); 908 m_freem(m0); 909 910 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 911 912 /* Now transmit the datagram. */ 913 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 914 sc->sc_command | SEEQ_CMD_TX_ON); 915 916 /* Make sure we notice if the chip goes silent on us. */ 917 ifp->if_timer = 5; 918 919 DPRINTF(SEEQ_DEBUG_TX, 920 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 921 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 922 } 923 924 /* 925 * Copy a packet from an mbuf to the transmit buffer on the card. 926 * 927 * Puts a valid Tx header at the start of the packet, and a null header at 928 * the end. 929 */ 930 static int 931 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 932 { 933 struct mbuf *m; 934 int len, nextpacket; 935 u_int8_t hdr[4]; 936 937 /* 938 * Copy the datagram to the packet buffer. 939 */ 940 len = 0; 941 for (m = m0; m; m = m->m_next) { 942 if (m->m_len == 0) 943 continue; 944 ea_writebuf(sc, mtod(m, caddr_t), bufstart + 4 + len, 945 m->m_len); 946 len += m->m_len; 947 } 948 949 len = max(len, ETHER_MIN_LEN); 950 951 /* Follow it with a NULL packet header */ 952 memset(hdr, 0, 4); 953 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 954 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 955 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 956 957 /* Ok we now have a packet len bytes long in our packet buffer */ 958 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 959 960 /* Write the packet header */ 961 nextpacket = len + 4; 962 hdr[0] = (nextpacket >> 8) & 0xff; 963 hdr[1] = nextpacket & 0xff; 964 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 965 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 966 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 967 ea_writebuf(sc, hdr, 0x0000, 4); 968 969 return len; 970 } 971 972 /* 973 * Ethernet controller interrupt. 974 */ 975 976 int 977 seeq8005intr(void *arg) 978 { 979 struct seeq8005_softc *sc = arg; 980 bus_space_tag_t iot = sc->sc_iot; 981 bus_space_handle_t ioh = sc->sc_ioh; 982 int status, handled; 983 984 handled = 0; 985 986 /* Get the controller status */ 987 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 988 989 /* Tx interrupt ? */ 990 if (status & SEEQ_STATUS_TX_INT) { 991 handled = 1; 992 993 /* Acknowledge the interrupt */ 994 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 995 sc->sc_command | SEEQ_CMD_TX_INTACK); 996 997 ea_txint(sc); 998 } 999 1000 1001 /* Rx interrupt ? */ 1002 if (status & SEEQ_STATUS_RX_INT) { 1003 handled = 1; 1004 1005 /* Acknowledge the interrupt */ 1006 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1007 sc->sc_command | SEEQ_CMD_RX_INTACK); 1008 1009 /* Processes the received packets */ 1010 ea_rxint(sc); 1011 } 1012 1013 return handled; 1014 } 1015 1016 static void 1017 ea_txint(struct seeq8005_softc *sc) 1018 { 1019 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1020 bus_space_tag_t iot = sc->sc_iot; 1021 bus_space_handle_t ioh = sc->sc_ioh; 1022 u_int8_t txhdr[4]; 1023 u_int txstatus; 1024 1025 ea_readbuf(sc, txhdr, 0x0000, 4); 1026 1027 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1028 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1029 txstatus = txhdr[3]; 1030 1031 /* 1032 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1033 * one collision. On the 8004 we can find out exactly how many 1034 * collisions occurred. 1035 * 1036 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1037 * completed. 1038 * 1039 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1040 * occurred and the packet transmission was aborted. 1041 * This situation is untested as present. 1042 * 1043 * The SEEQ_TXSTAT_BABBLE is untested as it should only be set 1044 * when we deliberately transmit oversized packets (e.g. for 1045 * 802.1Q). 1046 */ 1047 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1048 switch (sc->sc_variant) { 1049 case SEEQ_8004: { 1050 int colls; 1051 1052 /* 1053 * The 8004 contains a 4 bit collision count 1054 * in the status register. 1055 */ 1056 1057 /* This appears to be broken on 80C04.AE */ 1058 /* ifp->if_collisions += 1059 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1060 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1061 1062 /* Use the TX Collision register */ 1063 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1064 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1065 ifp->if_collisions += colls; 1066 break; 1067 } 1068 case SEEQ_8005: 1069 /* We known there was at least 1 collision */ 1070 ifp->if_collisions++; 1071 break; 1072 } 1073 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1074 printf("seeq_intr: col16 %x\n", txstatus); 1075 ifp->if_collisions += 16; 1076 ifp->if_oerrors++; 1077 } 1078 1079 /* Have we completed transmission on the packet ? */ 1080 if (txstatus & SEEQ_PKTSTAT_DONE) { 1081 /* Clear watchdog timer. */ 1082 ifp->if_timer = 0; 1083 ifp->if_flags &= ~IFF_OACTIVE; 1084 1085 /* Update stats */ 1086 ifp->if_opackets++; 1087 1088 /* Tx next packet */ 1089 1090 eatxpacket(sc); 1091 } 1092 } 1093 1094 void 1095 ea_rxint(struct seeq8005_softc *sc) 1096 { 1097 bus_space_tag_t iot = sc->sc_iot; 1098 bus_space_handle_t ioh = sc->sc_ioh; 1099 u_int addr; 1100 int len; 1101 int ctrl; 1102 int ptr; 1103 int pack; 1104 int status; 1105 u_int8_t rxhdr[4]; 1106 struct ifnet *ifp; 1107 1108 ifp = &sc->sc_ethercom.ec_if; 1109 1110 1111 /* We start from the last rx pointer position */ 1112 addr = sc->sc_rx_ptr; 1113 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1114 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1115 1116 do { 1117 /* Read rx header */ 1118 ea_readbuf(sc, rxhdr, addr, 4); 1119 1120 /* Split the packet header */ 1121 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1122 ctrl = rxhdr[2]; 1123 status = rxhdr[3]; 1124 1125 DPRINTF(SEEQ_DEBUG_RX, 1126 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1127 addr, ptr, ctrl, status)); 1128 1129 /* Zero packet ptr ? then must be null header so exit */ 1130 if (ptr == 0) break; 1131 1132 /* Sanity-check the next-packet pointer and flags. */ 1133 if (__predict_false(ptr < sc->sc_tx_bufsize || 1134 (ctrl & SEEQ_PKTCMD_TX))) { 1135 ++ifp->if_ierrors; 1136 log(LOG_ERR, 1137 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1138 sc->sc_dev.dv_xname, addr, ptr); 1139 ea_init(ifp); 1140 return; 1141 } 1142 1143 /* Get packet length */ 1144 len = (ptr - addr) - 4; 1145 1146 if (len < 0) 1147 len += sc->sc_rx_bufsize; 1148 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1149 1150 /* Has the packet rx completed ? if not then exit */ 1151 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1152 break; 1153 1154 /* 1155 * Did we have any errors? then note error and go to 1156 * next packet 1157 */ 1158 if (__predict_false(status & 1159 (SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR | 1160 SEEQ_RXSTAT_SHORT_FRAME))) { 1161 ++ifp->if_ierrors; 1162 log(LOG_WARNING, 1163 "%s: rx packet error at %04x (err=%02x)\n", 1164 sc->sc_dev.dv_xname, addr, status & 0x0f); 1165 /* XXX shouldn't need to reset if it's genuine. */ 1166 ea_init(ifp); 1167 return; 1168 } 1169 /* 1170 * Is the packet too big? We allow slightly oversize packets 1171 * for vlan(4) and tcpdump purposes, but the rest of the world 1172 * wants incoming packets in a single mbuf cluster. 1173 */ 1174 if (__predict_false(len > MCLBYTES)) { 1175 ++ifp->if_ierrors; 1176 log(LOG_ERR, 1177 "%s: rx packet size error at %04x (len=%d)\n", 1178 sc->sc_dev.dv_xname, addr, len); 1179 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1180 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, 1181 sc->sc_config2); 1182 ea_init(ifp); 1183 return; 1184 } 1185 1186 ifp->if_ipackets++; 1187 /* Pass data up to upper levels. */ 1188 ea_read(sc, addr + 4, len); 1189 1190 addr = ptr; 1191 ++pack; 1192 } while (len != 0); 1193 1194 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1195 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1196 1197 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1198 1199 /* Store new rx pointer */ 1200 sc->sc_rx_ptr = addr; 1201 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1202 1203 /* Make sure the receiver is on */ 1204 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1205 sc->sc_command | SEEQ_CMD_RX_ON); 1206 } 1207 1208 1209 /* 1210 * Pass a packet up to the higher levels. 1211 */ 1212 1213 static void 1214 ea_read(struct seeq8005_softc *sc, int addr, int len) 1215 { 1216 struct mbuf *m; 1217 struct ifnet *ifp; 1218 1219 ifp = &sc->sc_ethercom.ec_if; 1220 1221 /* Pull packet off interface. */ 1222 m = ea_get(sc, addr, len, ifp); 1223 if (m == 0) 1224 return; 1225 1226 #if NBPFILTER > 0 1227 /* 1228 * Check if there's a BPF listener on this interface. 1229 * If so, hand off the raw packet to bpf. 1230 */ 1231 if (ifp->if_bpf) 1232 bpf_mtap(ifp->if_bpf, m); 1233 #endif 1234 1235 (*ifp->if_input)(ifp, m); 1236 } 1237 1238 /* 1239 * Pull read data off a interface. Len is length of data, with local net 1240 * header stripped. We copy the data into mbufs. When full cluster sized 1241 * units are present we copy into clusters. 1242 */ 1243 1244 struct mbuf * 1245 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1246 { 1247 struct mbuf *top, **mp, *m; 1248 int len; 1249 u_int cp, epkt; 1250 1251 cp = addr; 1252 epkt = cp + totlen; 1253 1254 MGETHDR(m, M_DONTWAIT, MT_DATA); 1255 if (m == 0) 1256 return 0; 1257 m->m_pkthdr.rcvif = ifp; 1258 m->m_pkthdr.len = totlen; 1259 m->m_len = MHLEN; 1260 top = 0; 1261 mp = ⊤ 1262 1263 while (totlen > 0) { 1264 if (top) { 1265 MGET(m, M_DONTWAIT, MT_DATA); 1266 if (m == 0) { 1267 m_freem(top); 1268 return 0; 1269 } 1270 m->m_len = MLEN; 1271 } 1272 len = min(totlen, epkt - cp); 1273 if (len >= MINCLSIZE) { 1274 MCLGET(m, M_DONTWAIT); 1275 if (m->m_flags & M_EXT) 1276 m->m_len = len = min(len, MCLBYTES); 1277 else 1278 len = m->m_len; 1279 } else { 1280 /* 1281 * Place initial small packet/header at end of mbuf. 1282 */ 1283 if (len < m->m_len) { 1284 if (top == 0 && len + max_linkhdr <= m->m_len) 1285 m->m_data += max_linkhdr; 1286 m->m_len = len; 1287 } else 1288 len = m->m_len; 1289 } 1290 if (top == 0) { 1291 /* Make sure the payload is aligned */ 1292 caddr_t newdata = (caddr_t) 1293 ALIGN(m->m_data + sizeof(struct ether_header)) - 1294 sizeof(struct ether_header); 1295 len -= newdata - m->m_data; 1296 m->m_len = len; 1297 m->m_data = newdata; 1298 } 1299 ea_readbuf(sc, mtod(m, u_char *), 1300 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1301 len); 1302 cp += len; 1303 *mp = m; 1304 mp = &m->m_next; 1305 totlen -= len; 1306 if (cp == epkt) 1307 cp = addr; 1308 } 1309 1310 return top; 1311 } 1312 1313 /* 1314 * Process an ioctl request. Mostly boilerplate. 1315 */ 1316 static int 1317 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1318 { 1319 struct seeq8005_softc *sc = ifp->if_softc; 1320 int s, error = 0; 1321 1322 s = splnet(); 1323 switch (cmd) { 1324 1325 default: 1326 error = ether_ioctl(ifp, cmd, data); 1327 if (error == ENETRESET) { 1328 /* 1329 * Multicast list has changed; set the hardware filter 1330 * accordingly. 1331 */ 1332 ea_mc_reset(sc); 1333 error = 0; 1334 } 1335 break; 1336 } 1337 1338 splx(s); 1339 return error; 1340 } 1341 1342 /* Must be called at splnet() */ 1343 1344 static void 1345 ea_mc_reset(struct seeq8005_softc *sc) 1346 { 1347 1348 switch (sc->sc_variant) { 1349 case SEEQ_8004: 1350 ea_mc_reset_8004(sc); 1351 return; 1352 case SEEQ_8005: 1353 ea_mc_reset_8005(sc); 1354 return; 1355 } 1356 } 1357 1358 static void 1359 ea_mc_reset_8004(struct seeq8005_softc *sc) 1360 { 1361 struct ethercom *ec = &sc->sc_ethercom; 1362 struct ifnet *ifp = &ec->ec_if; 1363 struct ether_multi *enm; 1364 u_int32_t crc; 1365 int i; 1366 struct ether_multistep step; 1367 u_int8_t af[8]; 1368 1369 /* 1370 * Set up multicast address filter by passing all multicast addresses 1371 * through a crc generator, and then using bits 2 - 7 as an index 1372 * into the 64 bit logical address filter. The high order bits 1373 * selects the word, while the rest of the bits select the bit within 1374 * the word. 1375 */ 1376 1377 if (ifp->if_flags & IFF_PROMISC) { 1378 ifp->if_flags |= IFF_ALLMULTI; 1379 for (i = 0; i < 8; i++) 1380 af[i] = 0xff; 1381 return; 1382 } 1383 for (i = 0; i < 8; i++) 1384 af[i] = 0; 1385 ETHER_FIRST_MULTI(step, ec, enm); 1386 while (enm != NULL) { 1387 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1388 sizeof(enm->enm_addrlo)) != 0) { 1389 /* 1390 * We must listen to a range of multicast addresses. 1391 * For now, just accept all multicasts, rather than 1392 * trying to set only those filter bits needed to match 1393 * the range. (At this time, the only use of address 1394 * ranges is for IP multicast routing, for which the 1395 * range is big enough to require all bits set.) 1396 */ 1397 ifp->if_flags |= IFF_ALLMULTI; 1398 for (i = 0; i < 8; i++) 1399 af[i] = 0xff; 1400 break; 1401 } 1402 1403 crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1404 1405 /* Just want the 6 most significant bits. */ 1406 crc = (crc >> 2) & 0x3f; 1407 1408 /* Turn on the corresponding bit in the filter. */ 1409 af[crc >> 3] |= 1 << (crc & 0x7); 1410 1411 ETHER_NEXT_MULTI(step, enm); 1412 } 1413 ifp->if_flags &= ~IFF_ALLMULTI; 1414 1415 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1416 for (i = 0; i < 8; ++i) 1417 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1418 SEEQ_BUFWIN, af[i]); 1419 } 1420 1421 static void 1422 ea_mc_reset_8005(struct seeq8005_softc *sc) 1423 { 1424 struct ether_multi *enm; 1425 struct ether_multistep step; 1426 int naddr, maxaddrs; 1427 1428 naddr = 0; 1429 maxaddrs = 5; 1430 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1431 while (enm != NULL) { 1432 /* Have we got space? */ 1433 if (naddr >= maxaddrs || 1434 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1435 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1436 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1437 return; 1438 } 1439 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1440 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1441 naddr++; 1442 ETHER_NEXT_MULTI(step, enm); 1443 } 1444 for (; naddr < maxaddrs; naddr++) 1445 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1446 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1447 sc->sc_config1); 1448 } 1449 1450 /* 1451 * Device timeout routine. 1452 */ 1453 1454 static void 1455 ea_watchdog(struct ifnet *ifp) 1456 { 1457 struct seeq8005_softc *sc = ifp->if_softc; 1458 1459 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1460 sc->sc_dev.dv_xname, 1461 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1462 ifp->if_oerrors++; 1463 1464 /* Kick the interface */ 1465 1466 ea_init(ifp); 1467 1468 ifp->if_timer = 0; 1469 } 1470 1471 /* End of if_ea.c */ 1472
Indexes created Mon Sep 29 21:09:56 GMT 2025