seeq8005.c revision 1.33
1 /* $NetBSD: seeq8005.c,v 1.33 2002/06/07 00:01:19 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45 /* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52 /* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56 /* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: seeq8005.c,v 1.33 2002/06/07 00:01:19 bjh21 Exp $"); 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/endian.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 76 #include <net/if.h> 77 #include <net/if_dl.h> 78 #include <net/if_types.h> 79 #include <net/if_ether.h> 80 #include <net/if_media.h> 81 82 #include "bpfilter.h" 83 #if NBPFILTER > 0 84 #include <net/bpf.h> 85 #include <net/bpfdesc.h> 86 #endif 87 88 #include "rnd.h" 89 #if NRND > 0 90 #include <sys/rnd.h> 91 #endif 92 93 #include <machine/bus.h> 94 #include <machine/intr.h> 95 96 #include <dev/ic/seeq8005reg.h> 97 #include <dev/ic/seeq8005var.h> 98 99 /*#define SEEQ_DEBUG*/ 100 101 /* for debugging convenience */ 102 #ifdef SEEQ8005_DEBUG 103 #define SEEQ_DEBUG_MISC 1 104 #define SEEQ_DEBUG_TX 2 105 #define SEEQ_DEBUG_RX 4 106 #define SEEQ_DEBUG_PKT 8 107 #define SEEQ_DEBUG_TXINT 16 108 #define SEEQ_DEBUG_RXINT 32 109 int seeq8005_debug = 0; 110 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 111 #else 112 #define DPRINTF(f, x) 113 #endif 114 115 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> ETHER_MAX_LEN) */ 116 117 #define SEEQ_READ16(sc, iot, ioh, reg) \ 118 ((sc)->sc_flags & SF_8BIT ? \ 119 (bus_space_read_1((iot), (ioh), (reg)) | \ 120 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 121 (bus_space_read_2((iot), (ioh), (reg)))) 122 123 #define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 124 if ((sc)->sc_flags & SF_8BIT) { \ 125 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 126 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 127 } else \ 128 bus_space_write_2((iot), (ioh), (reg), (val)); \ 129 } while (/*CONSTCOND*/0) 130 131 /* 132 * prototypes 133 */ 134 135 static int ea_init(struct ifnet *); 136 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 137 static void ea_start(struct ifnet *); 138 static void ea_watchdog(struct ifnet *); 139 static void ea_chipreset(struct seeq8005_softc *); 140 static void ea_ramtest(struct seeq8005_softc *); 141 static int ea_stoptx(struct seeq8005_softc *); 142 static int ea_stoprx(struct seeq8005_softc *); 143 static void ea_stop(struct ifnet *, int); 144 static void ea_await_fifo_empty(struct seeq8005_softc *); 145 static void ea_await_fifo_full(struct seeq8005_softc *); 146 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 147 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 148 static void ea_select_buffer(struct seeq8005_softc *, int); 149 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 150 static void ea_read(struct seeq8005_softc *, int, int); 151 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 152 static void ea_txint(struct seeq8005_softc *); 153 static void ea_rxint(struct seeq8005_softc *); 154 static void eatxpacket(struct seeq8005_softc *); 155 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 156 static void ea_mc_reset(struct seeq8005_softc *); 157 static void ea_mc_reset_8004(struct seeq8005_softc *); 158 static void ea_mc_reset_8005(struct seeq8005_softc *); 159 static int ea_mediachange(struct ifnet *); 160 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 161 162 163 /* 164 * Attach chip. 165 */ 166 167 void 168 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 169 int nmedia, int defmedia) 170 { 171 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 172 bus_space_tag_t iot = sc->sc_iot; 173 bus_space_handle_t ioh = sc->sc_ioh; 174 u_int id; 175 176 KASSERT(myaddr != NULL); 177 printf(" address %s", ether_sprintf(myaddr)); 178 179 /* Stop the board. */ 180 181 ea_chipreset(sc); 182 183 /* Work out data bus width. */ 184 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 185 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 186 /* Try 8-bit mode */ 187 sc->sc_flags |= SF_8BIT; 188 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 189 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 190 printf("\n%s: Cannot determine data bus width\n", 191 sc->sc_dev.dv_xname); 192 return; 193 } 194 } 195 196 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 197 198 /* Get the product ID */ 199 200 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 201 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 202 203 switch (id & SEEQ_PRODUCTID_MASK) { 204 case SEEQ_PRODUCTID_8004: 205 sc->sc_variant = SEEQ_8004; 206 switch (id & SEEQ_PRODUCTID_REV_MASK) { 207 case SEEQ_PRODUCTID_REV_80C04: 208 printf(", SEEQ 80C04\n"); 209 break; 210 case SEEQ_PRODUCTID_REV_80C04A: 211 printf(", SEEQ 80C04A\n"); 212 break; 213 default: 214 /* Unknown SEEQ 8004 variants */ 215 printf(", SEEQ 8004 rev %x\n", 216 id & SEEQ_PRODUCTID_REV_MASK); 217 break; 218 } 219 break; 220 default: /* XXX */ 221 sc->sc_variant = SEEQ_8005; 222 printf(", SEEQ 8005\n"); 223 break; 224 } 225 226 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 227 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 228 229 /* 230 * Set up tx and rx buffers. 231 * 232 * We use approximately a quarter of the packet memory for TX 233 * buffers and the rest for RX buffers 234 */ 235 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 236 sc->sc_tx_bufs = 1; 237 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 238 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 239 sc->sc_enabled = 0; 240 241 /* Test the RAM */ 242 ea_ramtest(sc); 243 244 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 245 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 246 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 247 248 /* Initialise ifnet structure. */ 249 250 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 251 ifp->if_softc = sc; 252 ifp->if_start = ea_start; 253 ifp->if_ioctl = ea_ioctl; 254 ifp->if_init = ea_init; 255 ifp->if_stop = ea_stop; 256 ifp->if_watchdog = ea_watchdog; 257 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 258 if (sc->sc_variant == SEEQ_8004) 259 ifp->if_flags |= IFF_SIMPLEX; 260 IFQ_SET_READY(&ifp->if_snd); 261 262 /* Initialize media goo. */ 263 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 264 if (media != NULL) { 265 int i; 266 267 for (i = 0; i < nmedia; i++) 268 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 269 ifmedia_set(&sc->sc_media, defmedia); 270 } else { 271 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 272 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 273 } 274 275 /* We can support 802.1Q VLAN-sized frames. */ 276 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 277 278 /* Now we can attach the interface. */ 279 280 if_attach(ifp); 281 ether_ifattach(ifp, myaddr); 282 283 printf("\n"); 284 285 #if NRND > 0 286 /* After \n because it can print a line of its own. */ 287 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 288 RND_TYPE_NET, 0); 289 #endif 290 } 291 292 /* 293 * Media change callback. 294 */ 295 static int 296 ea_mediachange(struct ifnet *ifp) 297 { 298 struct seeq8005_softc *sc = ifp->if_softc; 299 300 if (sc->sc_mediachange) 301 return ((*sc->sc_mediachange)(sc)); 302 return (EINVAL); 303 } 304 305 /* 306 * Media status callback. 307 */ 308 static void 309 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 310 { 311 struct seeq8005_softc *sc = ifp->if_softc; 312 313 if (sc->sc_enabled == 0) { 314 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 315 ifmr->ifm_status = 0; 316 return; 317 } 318 319 if (sc->sc_mediastatus) 320 (*sc->sc_mediastatus)(sc, ifmr); 321 } 322 323 /* 324 * Test the RAM on the ethernet card. 325 */ 326 327 void 328 ea_ramtest(struct seeq8005_softc *sc) 329 { 330 bus_space_tag_t iot = sc->sc_iot; 331 bus_space_handle_t ioh = sc->sc_ioh; 332 int loop; 333 u_int sum = 0; 334 335 /* 336 * Test the buffer memory on the board. 337 * Write simple pattens to it and read them back. 338 */ 339 340 /* Set up the whole buffer RAM for writing */ 341 342 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 343 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 344 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 345 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 346 347 #define SEEQ_RAMTEST_LOOP(value) \ 348 do { \ 349 /* Set the write start address and write a pattern */ \ 350 ea_writebuf(sc, NULL, 0x0000, 0); \ 351 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 352 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 353 \ 354 /* Set the read start address and verify the pattern */ \ 355 ea_readbuf(sc, NULL, 0x0000, 0); \ 356 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 357 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 358 ++sum; \ 359 } while (/*CONSTCOND*/0) 360 361 SEEQ_RAMTEST_LOOP(loop); 362 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 363 SEEQ_RAMTEST_LOOP(0xaa55); 364 SEEQ_RAMTEST_LOOP(0x55aa); 365 366 /* Report */ 367 368 if (sum > 0) 369 printf("%s: buffer RAM failed self test, %d faults\n", 370 sc->sc_dev.dv_xname, sum); 371 } 372 373 374 /* 375 * Stop the tx interface. 376 * 377 * Returns 0 if the tx was already stopped or 1 if it was active 378 */ 379 380 static int 381 ea_stoptx(struct seeq8005_softc *sc) 382 { 383 bus_space_tag_t iot = sc->sc_iot; 384 bus_space_handle_t ioh = sc->sc_ioh; 385 int timeout; 386 int status; 387 388 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 389 390 sc->sc_enabled = 0; 391 392 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 393 if (!(status & SEEQ_STATUS_TX_ON)) 394 return 0; 395 396 /* Stop any tx and wait for confirmation */ 397 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 398 sc->sc_command | SEEQ_CMD_TX_OFF); 399 400 timeout = 20000; 401 do { 402 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 403 delay(1); 404 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 405 if (timeout == 0) 406 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 407 sc->sc_dev.dv_xname); 408 409 /* Clear any pending tx interrupt */ 410 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 411 sc->sc_command | SEEQ_CMD_TX_INTACK); 412 return 1; 413 } 414 415 416 /* 417 * Stop the rx interface. 418 * 419 * Returns 0 if the tx was already stopped or 1 if it was active 420 */ 421 422 static int 423 ea_stoprx(struct seeq8005_softc *sc) 424 { 425 bus_space_tag_t iot = sc->sc_iot; 426 bus_space_handle_t ioh = sc->sc_ioh; 427 int timeout; 428 int status; 429 430 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 431 432 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 433 if (!(status & SEEQ_STATUS_RX_ON)) 434 return 0; 435 436 /* Stop any rx and wait for confirmation */ 437 438 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 439 sc->sc_command | SEEQ_CMD_RX_OFF); 440 441 timeout = 20000; 442 do { 443 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 444 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 445 if (timeout == 0) 446 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 447 sc->sc_dev.dv_xname); 448 449 /* Clear any pending rx interrupt */ 450 451 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 452 sc->sc_command | SEEQ_CMD_RX_INTACK); 453 return 1; 454 } 455 456 457 /* 458 * Stop interface. 459 * Stop all IO and shut the interface down 460 */ 461 462 static void 463 ea_stop(struct ifnet *ifp, int disable) 464 { 465 struct seeq8005_softc *sc = ifp->if_softc; 466 bus_space_tag_t iot = sc->sc_iot; 467 bus_space_handle_t ioh = sc->sc_ioh; 468 469 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 470 471 /* Stop all IO */ 472 ea_stoptx(sc); 473 ea_stoprx(sc); 474 475 /* Disable rx and tx interrupts */ 476 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 477 478 /* Clear any pending interrupts */ 479 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 480 sc->sc_command | SEEQ_CMD_RX_INTACK | 481 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 482 SEEQ_CMD_BW_INTACK); 483 484 if (sc->sc_variant == SEEQ_8004) { 485 /* Put the chip to sleep */ 486 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 487 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 488 sc->sc_config3 | SEEQ_CFG3_SLEEP); 489 } 490 491 /* Cancel any watchdog timer */ 492 sc->sc_ethercom.ec_if.if_timer = 0; 493 } 494 495 496 /* 497 * Reset the chip 498 * Following this the software registers are reset 499 */ 500 501 static void 502 ea_chipreset(struct seeq8005_softc *sc) 503 { 504 bus_space_tag_t iot = sc->sc_iot; 505 bus_space_handle_t ioh = sc->sc_ioh; 506 507 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 508 509 /* Reset the controller. Min of 4us delay here */ 510 511 /* 512 * This can be called before we know whether the chip is in 8- or 513 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 514 * harmless in 8-bit mode, so we do that second. 515 */ 516 517 /* In 16-bit mode, this will munge the PreamSelect bit. */ 518 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 519 delay(4); 520 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 521 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 522 delay(4); 523 524 sc->sc_command = 0; 525 sc->sc_config1 = 0; 526 sc->sc_config2 = 0; 527 sc->sc_config3 = 0; 528 } 529 530 531 /* 532 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 533 * switching the FIFO from write to read. We also use it when changing 534 * the address for writes. 535 */ 536 static void 537 ea_await_fifo_empty(struct seeq8005_softc *sc) 538 { 539 bus_space_tag_t iot = sc->sc_iot; 540 bus_space_handle_t ioh = sc->sc_ioh; 541 int timeout; 542 543 timeout = 20000; 544 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 545 SEEQ_STATUS_FIFO_DIR) != 0) 546 return; /* FIFO is reading anyway. */ 547 while (--timeout > 0) 548 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 549 SEEQ_STATUS_FIFO_EMPTY) 550 return; 551 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", sc->sc_dev.dv_xname); 552 } 553 554 /* 555 * Wait for the DMA FIFO to fill before reading from it. 556 */ 557 static void 558 ea_await_fifo_full(struct seeq8005_softc *sc) 559 { 560 bus_space_tag_t iot = sc->sc_iot; 561 bus_space_handle_t ioh = sc->sc_ioh; 562 int timeout; 563 564 timeout = 20000; 565 while (--timeout > 0) 566 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 567 SEEQ_STATUS_FIFO_FULL) 568 return; 569 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", sc->sc_dev.dv_xname); 570 } 571 572 /* 573 * write to the buffer memory on the interface 574 * 575 * The buffer address is set to ADDR. 576 * If len != 0 then data is copied from the address starting at buf 577 * to the interface buffer. 578 * BUF must be usable as a u_int16_t *. 579 * If LEN is odd, it must be safe to overwrite one extra byte. 580 */ 581 582 static void 583 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 584 { 585 bus_space_tag_t iot = sc->sc_iot; 586 bus_space_handle_t ioh = sc->sc_ioh; 587 588 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 589 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 590 591 #ifdef DIAGNOSTIC 592 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 593 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 594 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 595 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 596 #endif 597 598 if (addr != -1) { 599 ea_await_fifo_empty(sc); 600 601 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 602 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 603 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 604 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 605 } 606 607 if (len > 0) { 608 if (sc->sc_flags & SF_8BIT) 609 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 610 (u_int8_t *)buf, len); 611 else 612 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 613 (u_int16_t *)buf, len / 2); 614 } 615 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 616 /* Write the last byte */ 617 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, buf[len - 1]); 618 } 619 /* Leave FIFO to empty in the background */ 620 } 621 622 623 /* 624 * read from the buffer memory on the interface 625 * 626 * The buffer address is set to ADDR. 627 * If len != 0 then data is copied from the interface buffer to the 628 * address starting at buf. 629 * BUF must be usable as a u_int16_t *. 630 * If LEN is odd, it must be safe to overwrite one extra byte. 631 */ 632 633 static void 634 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 635 { 636 bus_space_tag_t iot = sc->sc_iot; 637 bus_space_handle_t ioh = sc->sc_ioh; 638 int runup; 639 640 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 641 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 642 643 #ifdef DIAGNOSTIC 644 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 645 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 646 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 647 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 648 #endif 649 650 if (addr != -1) { 651 /* 652 * SEEQ 80C04 bug: 653 * Starting reading from certain addresses seems to cause 654 * us to get bogus results, so we avoid them. 655 */ 656 runup = 0; 657 if (sc->sc_variant == SEEQ_8004 && 658 ((addr & 0x00ff) == 0x00ea || 659 (addr & 0x00ff) == 0x00ee || 660 (addr & 0x00ff) == 0x00f0)) 661 runup = (addr & 0x00ff) - 0x00e8; 662 663 ea_await_fifo_empty(sc); 664 665 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 666 667 /* 668 * 80C04 bug workaround. I found this in the old arm32 "eb" 669 * driver. I've no idea what it does, but it seems to stop 670 * the chip mangling data so often. 671 */ 672 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 673 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 674 ea_await_fifo_empty(sc); 675 676 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 677 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 678 sc->sc_command | SEEQ_CMD_FIFO_READ); 679 680 ea_await_fifo_full(sc); 681 while (runup > 0) { 682 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 683 runup -= 2; 684 } 685 } 686 687 if (len > 0) { 688 if (sc->sc_flags & SF_8BIT) 689 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 690 (u_int8_t *)buf, len); 691 else 692 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 693 (u_int16_t *)buf, len / 2); 694 } 695 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 696 /* Read the last byte */ 697 buf[len - 1] = bus_space_read_2(iot, ioh, SEEQ_BUFWIN); 698 } 699 } 700 701 static void 702 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 703 { 704 705 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 706 sc->sc_config1 | bufcode); 707 } 708 709 /* Must be called at splnet */ 710 static void 711 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 712 { 713 int i; 714 715 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 716 for (i = 0; i < ETHER_ADDR_LEN; ++i) 717 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 718 ea[i]); 719 } 720 721 /* 722 * Initialize interface. 723 * 724 * This should leave the interface in a state for packet reception and 725 * transmission. 726 */ 727 728 static int 729 ea_init(struct ifnet *ifp) 730 { 731 struct seeq8005_softc *sc = ifp->if_softc; 732 bus_space_tag_t iot = sc->sc_iot; 733 bus_space_handle_t ioh = sc->sc_ioh; 734 int s; 735 736 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 737 738 s = splnet(); 739 740 /* First, reset the board. */ 741 742 ea_chipreset(sc); 743 744 /* Set up defaults for the registers */ 745 746 sc->sc_command = 0; 747 sc->sc_config1 = 0; 748 #if BYTE_ORDER == BIG_ENDIAN 749 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 750 #else 751 sc->sc_config2 = 0; 752 #endif 753 sc->sc_config3 = 0; 754 755 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 756 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 757 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 758 if (sc->sc_variant == SEEQ_8004) { 759 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 760 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 761 } 762 763 /* Write the station address - the receiver must be off */ 764 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 765 766 /* Split board memory into Rx and Tx. */ 767 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 768 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 769 770 if (sc->sc_variant == SEEQ_8004) { 771 /* Make the interface IFF_SIMPLEX. */ 772 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 773 /* Enable reception of long packets (for vlan(4)). */ 774 sc->sc_config2 |= SEEQ_CFG2_PASS_LONGSHORT; 775 } 776 777 /* Configure rx. */ 778 ea_mc_reset(sc); 779 if (ifp->if_flags & IFF_PROMISC) 780 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 781 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 782 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 783 else 784 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 785 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 786 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 787 788 /* Setup the Rx pointers */ 789 sc->sc_rx_ptr = sc->sc_tx_bufsize; 790 791 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 792 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 793 794 795 /* Place a NULL header at the beginning of the receive area */ 796 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 797 798 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 799 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 800 801 802 /* Configure TX. */ 803 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 804 805 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 806 807 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 808 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 809 810 /* Reset tx buffer pointers */ 811 sc->sc_tx_cur = 0; 812 sc->sc_tx_used = 0; 813 sc->sc_tx_next = 0; 814 815 /* Place a NULL header at the beginning of the transmit area */ 816 ea_writebuf(sc, NULL, 0x0000, 0); 817 818 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 819 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 820 821 sc->sc_command |= SEEQ_CMD_TX_INTEN; 822 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 823 824 /* Turn on Rx */ 825 sc->sc_command |= SEEQ_CMD_RX_INTEN; 826 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 827 sc->sc_command | SEEQ_CMD_RX_ON); 828 829 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 830 831 832 /* Set flags appropriately. */ 833 ifp->if_flags |= IFF_RUNNING; 834 ifp->if_flags &= ~IFF_OACTIVE; 835 sc->sc_enabled = 1; 836 837 /* And start output. */ 838 ea_start(ifp); 839 840 splx(s); 841 return 0; 842 } 843 844 /* 845 * Start output on interface. Get datagrams from the queue and output them, 846 * giving the receiver a chance between datagrams. Call only from splnet or 847 * interrupt level! 848 */ 849 850 static void 851 ea_start(struct ifnet *ifp) 852 { 853 struct seeq8005_softc *sc = ifp->if_softc; 854 int s; 855 856 s = splnet(); 857 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 858 859 /* 860 * Don't do anything if output is active. seeq8005intr() will call 861 * us (actually eatxpacket()) back when the card's ready for more 862 * frames. 863 */ 864 if (ifp->if_flags & IFF_OACTIVE) 865 return; 866 867 /* Mark interface as output active */ 868 869 ifp->if_flags |= IFF_OACTIVE; 870 871 /* tx packets */ 872 873 eatxpacket(sc); 874 splx(s); 875 } 876 877 878 /* 879 * Transfer a packet to the interface buffer and start transmission 880 * 881 * Called at splnet() 882 */ 883 884 void 885 eatxpacket(struct seeq8005_softc *sc) 886 { 887 bus_space_tag_t iot = sc->sc_iot; 888 bus_space_handle_t ioh = sc->sc_ioh; 889 struct mbuf *m0; 890 struct ifnet *ifp; 891 892 ifp = &sc->sc_ethercom.ec_if; 893 894 /* Dequeue the next packet. */ 895 IFQ_DEQUEUE(&ifp->if_snd, m0); 896 897 /* If there's nothing to send, return. */ 898 if (!m0) { 899 ifp->if_flags &= ~IFF_OACTIVE; 900 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 901 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 902 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 903 return; 904 } 905 906 #if NBPFILTER > 0 907 /* Give the packet to the bpf, if any. */ 908 if (ifp->if_bpf) 909 bpf_mtap(ifp->if_bpf, m0); 910 #endif 911 912 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 913 914 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 915 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 916 917 ea_writembuf(sc, m0, 0x0000); 918 m_freem(m0); 919 920 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 921 922 /* Now transmit the datagram. */ 923 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 924 sc->sc_command | SEEQ_CMD_TX_ON); 925 926 /* Make sure we notice if the chip goes silent on us. */ 927 ifp->if_timer = 5; 928 929 DPRINTF(SEEQ_DEBUG_TX, 930 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 931 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 932 } 933 934 /* 935 * Copy a packet from an mbuf to the transmit buffer on the card. 936 * 937 * Puts a valid Tx header at the start of the packet, and a null header at 938 * the end. 939 */ 940 static int 941 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 942 { 943 struct mbuf *m; 944 int len, nextpacket; 945 u_int8_t hdr[4]; 946 947 /* 948 * Copy the datagram to the packet buffer. 949 */ 950 len = 0; 951 for (m = m0; m; m = m->m_next) { 952 if (m->m_len == 0) 953 continue; 954 ea_writebuf(sc, mtod(m, caddr_t), bufstart + 4 + len, 955 m->m_len); 956 len += m->m_len; 957 } 958 959 len = max(len, ETHER_MIN_LEN); 960 961 /* Follow it with a NULL packet header */ 962 memset(hdr, 0, 4); 963 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 964 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 965 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 966 967 /* Ok we now have a packet len bytes long in our packet buffer */ 968 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 969 970 /* Write the packet header */ 971 nextpacket = len + 4; 972 hdr[0] = (nextpacket >> 8) & 0xff; 973 hdr[1] = nextpacket & 0xff; 974 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 975 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 976 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 977 ea_writebuf(sc, hdr, 0x0000, 4); 978 979 return len; 980 } 981 982 /* 983 * Ethernet controller interrupt. 984 */ 985 986 int 987 seeq8005intr(void *arg) 988 { 989 struct seeq8005_softc *sc = arg; 990 bus_space_tag_t iot = sc->sc_iot; 991 bus_space_handle_t ioh = sc->sc_ioh; 992 int status, handled; 993 994 handled = 0; 995 996 /* Get the controller status */ 997 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 998 999 /* Tx interrupt ? */ 1000 if (status & SEEQ_STATUS_TX_INT) { 1001 handled = 1; 1002 1003 /* Acknowledge the interrupt */ 1004 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1005 sc->sc_command | SEEQ_CMD_TX_INTACK); 1006 1007 ea_txint(sc); 1008 } 1009 1010 1011 /* Rx interrupt ? */ 1012 if (status & SEEQ_STATUS_RX_INT) { 1013 handled = 1; 1014 1015 /* Acknowledge the interrupt */ 1016 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1017 sc->sc_command | SEEQ_CMD_RX_INTACK); 1018 1019 /* Processes the received packets */ 1020 ea_rxint(sc); 1021 } 1022 1023 #if NRND > 0 1024 if (handled) 1025 rnd_add_uint32(&sc->rnd_source, status); 1026 #endif 1027 return handled; 1028 } 1029 1030 static void 1031 ea_txint(struct seeq8005_softc *sc) 1032 { 1033 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1034 bus_space_tag_t iot = sc->sc_iot; 1035 bus_space_handle_t ioh = sc->sc_ioh; 1036 u_int8_t txhdr[4]; 1037 u_int txstatus; 1038 1039 ea_readbuf(sc, txhdr, 0x0000, 4); 1040 1041 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1042 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1043 txstatus = txhdr[3]; 1044 1045 /* 1046 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1047 * one collision. On the 8004 we can find out exactly how many 1048 * collisions occurred. 1049 * 1050 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1051 * completed. 1052 * 1053 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1054 * occurred and the packet transmission was aborted. 1055 * This situation is untested as present. 1056 * 1057 * The SEEQ_TXSTAT_BABBLE is untested as it should only be set 1058 * when we deliberately transmit oversized packets (e.g. for 1059 * 802.1Q). 1060 */ 1061 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1062 switch (sc->sc_variant) { 1063 case SEEQ_8004: { 1064 int colls; 1065 1066 /* 1067 * The 8004 contains a 4 bit collision count 1068 * in the status register. 1069 */ 1070 1071 /* This appears to be broken on 80C04.AE */ 1072 /* ifp->if_collisions += 1073 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1074 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1075 1076 /* Use the TX Collision register */ 1077 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1078 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1079 ifp->if_collisions += colls; 1080 break; 1081 } 1082 case SEEQ_8005: 1083 /* We known there was at least 1 collision */ 1084 ifp->if_collisions++; 1085 break; 1086 } 1087 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1088 printf("seeq_intr: col16 %x\n", txstatus); 1089 ifp->if_collisions += 16; 1090 ifp->if_oerrors++; 1091 } 1092 1093 /* Have we completed transmission on the packet ? */ 1094 if (txstatus & SEEQ_PKTSTAT_DONE) { 1095 /* Clear watchdog timer. */ 1096 ifp->if_timer = 0; 1097 ifp->if_flags &= ~IFF_OACTIVE; 1098 1099 /* Update stats */ 1100 ifp->if_opackets++; 1101 1102 /* Tx next packet */ 1103 1104 eatxpacket(sc); 1105 } 1106 } 1107 1108 void 1109 ea_rxint(struct seeq8005_softc *sc) 1110 { 1111 bus_space_tag_t iot = sc->sc_iot; 1112 bus_space_handle_t ioh = sc->sc_ioh; 1113 u_int addr; 1114 int len; 1115 int ctrl; 1116 int ptr; 1117 int pack; 1118 int status; 1119 u_int8_t rxhdr[4]; 1120 struct ifnet *ifp; 1121 1122 ifp = &sc->sc_ethercom.ec_if; 1123 1124 1125 /* We start from the last rx pointer position */ 1126 addr = sc->sc_rx_ptr; 1127 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1128 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1129 1130 do { 1131 /* Read rx header */ 1132 ea_readbuf(sc, rxhdr, addr, 4); 1133 1134 /* Split the packet header */ 1135 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1136 ctrl = rxhdr[2]; 1137 status = rxhdr[3]; 1138 1139 DPRINTF(SEEQ_DEBUG_RX, 1140 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1141 addr, ptr, ctrl, status)); 1142 1143 /* Zero packet ptr ? then must be null header so exit */ 1144 if (ptr == 0) break; 1145 1146 /* Sanity-check the next-packet pointer and flags. */ 1147 if (__predict_false(ptr < sc->sc_tx_bufsize || 1148 (ctrl & SEEQ_PKTCMD_TX))) { 1149 ++ifp->if_ierrors; 1150 log(LOG_ERR, 1151 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1152 sc->sc_dev.dv_xname, addr, ptr); 1153 ea_init(ifp); 1154 return; 1155 } 1156 1157 /* Get packet length */ 1158 len = (ptr - addr) - 4; 1159 1160 if (len < 0) 1161 len += sc->sc_rx_bufsize; 1162 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1163 1164 /* Has the packet rx completed ? if not then exit */ 1165 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1166 break; 1167 1168 /* 1169 * Did we have any errors? then note error and go to 1170 * next packet 1171 */ 1172 if (__predict_false(status & 1173 (SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR | 1174 SEEQ_RXSTAT_SHORT_FRAME))) { 1175 ++ifp->if_ierrors; 1176 log(LOG_WARNING, 1177 "%s: rx packet error at %04x (err=%02x)\n", 1178 sc->sc_dev.dv_xname, addr, status & 0x0f); 1179 /* XXX shouldn't need to reset if it's genuine. */ 1180 ea_init(ifp); 1181 return; 1182 } 1183 /* 1184 * Is the packet too big? We allow slightly oversize packets 1185 * for vlan(4) and tcpdump purposes, but the rest of the world 1186 * wants incoming packets in a single mbuf cluster. 1187 */ 1188 if (__predict_false(len > MCLBYTES)) { 1189 ++ifp->if_ierrors; 1190 log(LOG_ERR, 1191 "%s: rx packet size error at %04x (len=%d)\n", 1192 sc->sc_dev.dv_xname, addr, len); 1193 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1194 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, 1195 sc->sc_config2); 1196 ea_init(ifp); 1197 return; 1198 } 1199 1200 ifp->if_ipackets++; 1201 /* Pass data up to upper levels. */ 1202 ea_read(sc, addr + 4, len); 1203 1204 addr = ptr; 1205 ++pack; 1206 } while (len != 0); 1207 1208 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1209 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1210 1211 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1212 1213 /* Store new rx pointer */ 1214 sc->sc_rx_ptr = addr; 1215 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1216 1217 /* Make sure the receiver is on */ 1218 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1219 sc->sc_command | SEEQ_CMD_RX_ON); 1220 } 1221 1222 1223 /* 1224 * Pass a packet up to the higher levels. 1225 */ 1226 1227 static void 1228 ea_read(struct seeq8005_softc *sc, int addr, int len) 1229 { 1230 struct mbuf *m; 1231 struct ifnet *ifp; 1232 1233 ifp = &sc->sc_ethercom.ec_if; 1234 1235 /* Pull packet off interface. */ 1236 m = ea_get(sc, addr, len, ifp); 1237 if (m == 0) 1238 return; 1239 1240 #if NBPFILTER > 0 1241 /* 1242 * Check if there's a BPF listener on this interface. 1243 * If so, hand off the raw packet to bpf. 1244 */ 1245 if (ifp->if_bpf) 1246 bpf_mtap(ifp->if_bpf, m); 1247 #endif 1248 1249 (*ifp->if_input)(ifp, m); 1250 } 1251 1252 /* 1253 * Pull read data off a interface. Len is length of data, with local net 1254 * header stripped. We copy the data into mbufs. When full cluster sized 1255 * units are present we copy into clusters. 1256 */ 1257 1258 struct mbuf * 1259 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1260 { 1261 struct mbuf *top, **mp, *m; 1262 int len; 1263 u_int cp, epkt; 1264 1265 cp = addr; 1266 epkt = cp + totlen; 1267 1268 MGETHDR(m, M_DONTWAIT, MT_DATA); 1269 if (m == 0) 1270 return 0; 1271 m->m_pkthdr.rcvif = ifp; 1272 m->m_pkthdr.len = totlen; 1273 m->m_len = MHLEN; 1274 top = 0; 1275 mp = ⊤ 1276 1277 while (totlen > 0) { 1278 if (top) { 1279 MGET(m, M_DONTWAIT, MT_DATA); 1280 if (m == 0) { 1281 m_freem(top); 1282 return 0; 1283 } 1284 m->m_len = MLEN; 1285 } 1286 len = min(totlen, epkt - cp); 1287 if (len >= MINCLSIZE) { 1288 MCLGET(m, M_DONTWAIT); 1289 if (m->m_flags & M_EXT) 1290 m->m_len = len = min(len, MCLBYTES); 1291 else 1292 len = m->m_len; 1293 } else { 1294 /* 1295 * Place initial small packet/header at end of mbuf. 1296 */ 1297 if (len < m->m_len) { 1298 if (top == 0 && len + max_linkhdr <= m->m_len) 1299 m->m_data += max_linkhdr; 1300 m->m_len = len; 1301 } else 1302 len = m->m_len; 1303 } 1304 if (top == 0) { 1305 /* Make sure the payload is aligned */ 1306 caddr_t newdata = (caddr_t) 1307 ALIGN(m->m_data + sizeof(struct ether_header)) - 1308 sizeof(struct ether_header); 1309 len -= newdata - m->m_data; 1310 m->m_len = len; 1311 m->m_data = newdata; 1312 } 1313 ea_readbuf(sc, mtod(m, u_char *), 1314 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1315 len); 1316 cp += len; 1317 *mp = m; 1318 mp = &m->m_next; 1319 totlen -= len; 1320 if (cp == epkt) 1321 cp = addr; 1322 } 1323 1324 return top; 1325 } 1326 1327 /* 1328 * Process an ioctl request. Mostly boilerplate. 1329 */ 1330 static int 1331 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1332 { 1333 struct seeq8005_softc *sc = ifp->if_softc; 1334 int s, error = 0; 1335 1336 s = splnet(); 1337 switch (cmd) { 1338 1339 default: 1340 error = ether_ioctl(ifp, cmd, data); 1341 if (error == ENETRESET) { 1342 /* 1343 * Multicast list has changed; set the hardware filter 1344 * accordingly. 1345 */ 1346 ea_mc_reset(sc); 1347 error = 0; 1348 } 1349 break; 1350 } 1351 1352 splx(s); 1353 return error; 1354 } 1355 1356 /* Must be called at splnet() */ 1357 1358 static void 1359 ea_mc_reset(struct seeq8005_softc *sc) 1360 { 1361 1362 switch (sc->sc_variant) { 1363 case SEEQ_8004: 1364 ea_mc_reset_8004(sc); 1365 return; 1366 case SEEQ_8005: 1367 ea_mc_reset_8005(sc); 1368 return; 1369 } 1370 } 1371 1372 static void 1373 ea_mc_reset_8004(struct seeq8005_softc *sc) 1374 { 1375 struct ethercom *ec = &sc->sc_ethercom; 1376 struct ifnet *ifp = &ec->ec_if; 1377 struct ether_multi *enm; 1378 u_int32_t crc; 1379 int i; 1380 struct ether_multistep step; 1381 u_int8_t af[8]; 1382 1383 /* 1384 * Set up multicast address filter by passing all multicast addresses 1385 * through a crc generator, and then using bits 2 - 7 as an index 1386 * into the 64 bit logical address filter. The high order bits 1387 * selects the word, while the rest of the bits select the bit within 1388 * the word. 1389 */ 1390 1391 if (ifp->if_flags & IFF_PROMISC) { 1392 ifp->if_flags |= IFF_ALLMULTI; 1393 for (i = 0; i < 8; i++) 1394 af[i] = 0xff; 1395 return; 1396 } 1397 for (i = 0; i < 8; i++) 1398 af[i] = 0; 1399 ETHER_FIRST_MULTI(step, ec, enm); 1400 while (enm != NULL) { 1401 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1402 sizeof(enm->enm_addrlo)) != 0) { 1403 /* 1404 * We must listen to a range of multicast addresses. 1405 * For now, just accept all multicasts, rather than 1406 * trying to set only those filter bits needed to match 1407 * the range. (At this time, the only use of address 1408 * ranges is for IP multicast routing, for which the 1409 * range is big enough to require all bits set.) 1410 */ 1411 ifp->if_flags |= IFF_ALLMULTI; 1412 for (i = 0; i < 8; i++) 1413 af[i] = 0xff; 1414 break; 1415 } 1416 1417 crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1418 1419 /* Just want the 6 most significant bits. */ 1420 crc = (crc >> 2) & 0x3f; 1421 1422 /* Turn on the corresponding bit in the filter. */ 1423 af[crc >> 3] |= 1 << (crc & 0x7); 1424 1425 ETHER_NEXT_MULTI(step, enm); 1426 } 1427 ifp->if_flags &= ~IFF_ALLMULTI; 1428 1429 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1430 for (i = 0; i < 8; ++i) 1431 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1432 SEEQ_BUFWIN, af[i]); 1433 } 1434 1435 static void 1436 ea_mc_reset_8005(struct seeq8005_softc *sc) 1437 { 1438 struct ether_multi *enm; 1439 struct ether_multistep step; 1440 int naddr, maxaddrs; 1441 1442 naddr = 0; 1443 maxaddrs = 5; 1444 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1445 while (enm != NULL) { 1446 /* Have we got space? */ 1447 if (naddr >= maxaddrs || 1448 memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1449 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1450 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1451 return; 1452 } 1453 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1454 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1455 naddr++; 1456 ETHER_NEXT_MULTI(step, enm); 1457 } 1458 for (; naddr < maxaddrs; naddr++) 1459 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1460 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1461 sc->sc_config1); 1462 } 1463 1464 /* 1465 * Device timeout routine. 1466 */ 1467 1468 static void 1469 ea_watchdog(struct ifnet *ifp) 1470 { 1471 struct seeq8005_softc *sc = ifp->if_softc; 1472 1473 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1474 sc->sc_dev.dv_xname, 1475 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1476 ifp->if_oerrors++; 1477 1478 /* Kick the interface */ 1479 1480 ea_init(ifp); 1481 1482 ifp->if_timer = 0; 1483 } 1484 1485 /* End of if_ea.c */ 1486
Indexes created Tue Sep 30 07:10:03 GMT 2025