seeq8005.c revision 1.34
1 /* $NetBSD: seeq8005.c,v 1.34 2002/11/03 14:59:06 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45 /* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52 /* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56 /* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: seeq8005.c,v 1.34 2002/11/03 14:59:06 bjh21 Exp $"); 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/endian.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 76 #include <net/if.h> 77 #include <net/if_dl.h> 78 #include <net/if_types.h> 79 #include <net/if_ether.h> 80 #include <net/if_media.h> 81 82 #include "bpfilter.h" 83 #if NBPFILTER > 0 84 #include <net/bpf.h> 85 #include <net/bpfdesc.h> 86 #endif 87 88 #include "rnd.h" 89 #if NRND > 0 90 #include <sys/rnd.h> 91 #endif 92 93 #include <machine/bus.h> 94 #include <machine/intr.h> 95 96 #include <dev/ic/seeq8005reg.h> 97 #include <dev/ic/seeq8005var.h> 98 99 /*#define SEEQ_DEBUG*/ 100 101 /* for debugging convenience */ 102 #ifdef SEEQ8005_DEBUG 103 #define SEEQ_DEBUG_MISC 1 104 #define SEEQ_DEBUG_TX 2 105 #define SEEQ_DEBUG_RX 4 106 #define SEEQ_DEBUG_PKT 8 107 #define SEEQ_DEBUG_TXINT 16 108 #define SEEQ_DEBUG_RXINT 32 109 int seeq8005_debug = 0; 110 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 111 #else 112 #define DPRINTF(f, x) 113 #endif 114 115 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> ETHER_MAX_LEN) */ 116 117 #define SEEQ_READ16(sc, iot, ioh, reg) \ 118 ((sc)->sc_flags & SF_8BIT ? \ 119 (bus_space_read_1((iot), (ioh), (reg)) | \ 120 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 121 (bus_space_read_2((iot), (ioh), (reg)))) 122 123 #define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 124 if ((sc)->sc_flags & SF_8BIT) { \ 125 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 126 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 127 } else \ 128 bus_space_write_2((iot), (ioh), (reg), (val)); \ 129 } while (/*CONSTCOND*/0) 130 131 /* 132 * prototypes 133 */ 134 135 static int ea_init(struct ifnet *); 136 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 137 static void ea_start(struct ifnet *); 138 static void ea_watchdog(struct ifnet *); 139 static void ea_chipreset(struct seeq8005_softc *); 140 static void ea_ramtest(struct seeq8005_softc *); 141 static int ea_stoptx(struct seeq8005_softc *); 142 static int ea_stoprx(struct seeq8005_softc *); 143 static void ea_stop(struct ifnet *, int); 144 static void ea_await_fifo_empty(struct seeq8005_softc *); 145 static void ea_await_fifo_full(struct seeq8005_softc *); 146 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 147 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 148 static void ea_select_buffer(struct seeq8005_softc *, int); 149 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 150 static void ea_read(struct seeq8005_softc *, int, int); 151 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 152 static void ea_txint(struct seeq8005_softc *); 153 static void ea_rxint(struct seeq8005_softc *); 154 static void eatxpacket(struct seeq8005_softc *); 155 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 156 static void ea_mc_reset(struct seeq8005_softc *); 157 static void ea_mc_reset_8004(struct seeq8005_softc *); 158 static void ea_mc_reset_8005(struct seeq8005_softc *); 159 static int ea_mediachange(struct ifnet *); 160 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 161 162 163 /* 164 * Attach chip. 165 */ 166 167 void 168 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 169 int nmedia, int defmedia) 170 { 171 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 172 bus_space_tag_t iot = sc->sc_iot; 173 bus_space_handle_t ioh = sc->sc_ioh; 174 u_int id; 175 176 KASSERT(myaddr != NULL); 177 printf(" address %s", ether_sprintf(myaddr)); 178 179 /* Stop the board. */ 180 181 ea_chipreset(sc); 182 183 /* Work out data bus width. */ 184 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 185 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 186 /* Try 8-bit mode */ 187 sc->sc_flags |= SF_8BIT; 188 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 189 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 190 printf("\n%s: Cannot determine data bus width\n", 191 sc->sc_dev.dv_xname); 192 return; 193 } 194 } 195 196 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 197 198 /* Get the product ID */ 199 200 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 201 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 202 203 switch (id & SEEQ_PRODUCTID_MASK) { 204 case SEEQ_PRODUCTID_8004: 205 sc->sc_variant = SEEQ_8004; 206 switch (id & SEEQ_PRODUCTID_REV_MASK) { 207 case SEEQ_PRODUCTID_REV_80C04: 208 printf(", SEEQ 80C04\n"); 209 break; 210 case SEEQ_PRODUCTID_REV_80C04A: 211 printf(", SEEQ 80C04A\n"); 212 break; 213 default: 214 /* Unknown SEEQ 8004 variants */ 215 printf(", SEEQ 8004 rev %x\n", 216 id & SEEQ_PRODUCTID_REV_MASK); 217 break; 218 } 219 break; 220 default: /* XXX */ 221 sc->sc_variant = SEEQ_8005; 222 printf(", SEEQ 8005\n"); 223 break; 224 } 225 226 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 227 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 228 229 /* 230 * Set up tx and rx buffers. 231 * 232 * We use approximately a quarter of the packet memory for TX 233 * buffers and the rest for RX buffers 234 */ 235 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 236 sc->sc_tx_bufs = 1; 237 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 238 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 239 sc->sc_enabled = 0; 240 241 /* Test the RAM */ 242 ea_ramtest(sc); 243 244 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 245 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 246 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 247 248 /* Initialise ifnet structure. */ 249 250 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 251 ifp->if_softc = sc; 252 ifp->if_start = ea_start; 253 ifp->if_ioctl = ea_ioctl; 254 ifp->if_init = ea_init; 255 ifp->if_stop = ea_stop; 256 ifp->if_watchdog = ea_watchdog; 257 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 258 if (sc->sc_variant == SEEQ_8004) 259 ifp->if_flags |= IFF_SIMPLEX; 260 IFQ_SET_READY(&ifp->if_snd); 261 262 /* Initialize media goo. */ 263 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 264 if (media != NULL) { 265 int i; 266 267 for (i = 0; i < nmedia; i++) 268 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 269 ifmedia_set(&sc->sc_media, defmedia); 270 } else { 271 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 272 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 273 } 274 275 /* We can support 802.1Q VLAN-sized frames. */ 276 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 277 278 /* Now we can attach the interface. */ 279 280 if_attach(ifp); 281 ether_ifattach(ifp, myaddr); 282 283 printf("\n"); 284 285 #if NRND > 0 286 /* After \n because it can print a line of its own. */ 287 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 288 RND_TYPE_NET, 0); 289 #endif 290 } 291 292 /* 293 * Media change callback. 294 */ 295 static int 296 ea_mediachange(struct ifnet *ifp) 297 { 298 struct seeq8005_softc *sc = ifp->if_softc; 299 300 if (sc->sc_mediachange) 301 return ((*sc->sc_mediachange)(sc)); 302 return (EINVAL); 303 } 304 305 /* 306 * Media status callback. 307 */ 308 static void 309 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 310 { 311 struct seeq8005_softc *sc = ifp->if_softc; 312 313 if (sc->sc_enabled == 0) { 314 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 315 ifmr->ifm_status = 0; 316 return; 317 } 318 319 if (sc->sc_mediastatus) 320 (*sc->sc_mediastatus)(sc, ifmr); 321 } 322 323 /* 324 * Test the RAM on the ethernet card. 325 */ 326 327 void 328 ea_ramtest(struct seeq8005_softc *sc) 329 { 330 bus_space_tag_t iot = sc->sc_iot; 331 bus_space_handle_t ioh = sc->sc_ioh; 332 int loop; 333 u_int sum = 0; 334 335 /* 336 * Test the buffer memory on the board. 337 * Write simple pattens to it and read them back. 338 */ 339 340 /* Set up the whole buffer RAM for writing */ 341 342 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 343 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 344 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 345 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 346 347 #define SEEQ_RAMTEST_LOOP(value) \ 348 do { \ 349 /* Set the write start address and write a pattern */ \ 350 ea_writebuf(sc, NULL, 0x0000, 0); \ 351 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 352 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 353 \ 354 /* Set the read start address and verify the pattern */ \ 355 ea_readbuf(sc, NULL, 0x0000, 0); \ 356 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 357 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 358 ++sum; \ 359 } while (/*CONSTCOND*/0) 360 361 SEEQ_RAMTEST_LOOP(loop); 362 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 363 SEEQ_RAMTEST_LOOP(0xaa55); 364 SEEQ_RAMTEST_LOOP(0x55aa); 365 366 /* Report */ 367 368 if (sum > 0) 369 printf("%s: buffer RAM failed self test, %d faults\n", 370 sc->sc_dev.dv_xname, sum); 371 } 372 373 374 /* 375 * Stop the tx interface. 376 * 377 * Returns 0 if the tx was already stopped or 1 if it was active 378 */ 379 380 static int 381 ea_stoptx(struct seeq8005_softc *sc) 382 { 383 bus_space_tag_t iot = sc->sc_iot; 384 bus_space_handle_t ioh = sc->sc_ioh; 385 int timeout; 386 int status; 387 388 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 389 390 sc->sc_enabled = 0; 391 392 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 393 if (!(status & SEEQ_STATUS_TX_ON)) 394 return 0; 395 396 /* Stop any tx and wait for confirmation */ 397 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 398 sc->sc_command | SEEQ_CMD_TX_OFF); 399 400 timeout = 20000; 401 do { 402 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 403 delay(1); 404 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 405 if (timeout == 0) 406 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 407 sc->sc_dev.dv_xname); 408 409 /* Clear any pending tx interrupt */ 410 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 411 sc->sc_command | SEEQ_CMD_TX_INTACK); 412 return 1; 413 } 414 415 416 /* 417 * Stop the rx interface. 418 * 419 * Returns 0 if the tx was already stopped or 1 if it was active 420 */ 421 422 static int 423 ea_stoprx(struct seeq8005_softc *sc) 424 { 425 bus_space_tag_t iot = sc->sc_iot; 426 bus_space_handle_t ioh = sc->sc_ioh; 427 int timeout; 428 int status; 429 430 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 431 432 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 433 if (!(status & SEEQ_STATUS_RX_ON)) 434 return 0; 435 436 /* Stop any rx and wait for confirmation */ 437 438 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 439 sc->sc_command | SEEQ_CMD_RX_OFF); 440 441 timeout = 20000; 442 do { 443 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 444 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 445 if (timeout == 0) 446 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 447 sc->sc_dev.dv_xname); 448 449 /* Clear any pending rx interrupt */ 450 451 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 452 sc->sc_command | SEEQ_CMD_RX_INTACK); 453 return 1; 454 } 455 456 457 /* 458 * Stop interface. 459 * Stop all IO and shut the interface down 460 */ 461 462 /* ARGSUSED */ 463 static void 464 ea_stop(struct ifnet *ifp, int disable) 465 { 466 struct seeq8005_softc *sc = ifp->if_softc; 467 bus_space_tag_t iot = sc->sc_iot; 468 bus_space_handle_t ioh = sc->sc_ioh; 469 470 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 471 472 /* Stop all IO */ 473 ea_stoptx(sc); 474 ea_stoprx(sc); 475 476 /* Disable rx and tx interrupts */ 477 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 478 479 /* Clear any pending interrupts */ 480 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 481 sc->sc_command | SEEQ_CMD_RX_INTACK | 482 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 483 SEEQ_CMD_BW_INTACK); 484 485 if (sc->sc_variant == SEEQ_8004) { 486 /* Put the chip to sleep */ 487 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 488 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 489 sc->sc_config3 | SEEQ_CFG3_SLEEP); 490 } 491 492 /* Cancel any watchdog timer */ 493 sc->sc_ethercom.ec_if.if_timer = 0; 494 } 495 496 497 /* 498 * Reset the chip 499 * Following this the software registers are reset 500 */ 501 502 static void 503 ea_chipreset(struct seeq8005_softc *sc) 504 { 505 bus_space_tag_t iot = sc->sc_iot; 506 bus_space_handle_t ioh = sc->sc_ioh; 507 508 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 509 510 /* Reset the controller. Min of 4us delay here */ 511 512 /* 513 * This can be called before we know whether the chip is in 8- or 514 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 515 * harmless in 8-bit mode, so we do that second. 516 */ 517 518 /* In 16-bit mode, this will munge the PreamSelect bit. */ 519 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 520 delay(4); 521 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 522 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 523 delay(4); 524 525 sc->sc_command = 0; 526 sc->sc_config1 = 0; 527 sc->sc_config2 = 0; 528 sc->sc_config3 = 0; 529 } 530 531 532 /* 533 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 534 * switching the FIFO from write to read. We also use it when changing 535 * the address for writes. 536 */ 537 static void 538 ea_await_fifo_empty(struct seeq8005_softc *sc) 539 { 540 bus_space_tag_t iot = sc->sc_iot; 541 bus_space_handle_t ioh = sc->sc_ioh; 542 int timeout; 543 544 timeout = 20000; 545 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 546 SEEQ_STATUS_FIFO_DIR) != 0) 547 return; /* FIFO is reading anyway. */ 548 while (--timeout > 0) 549 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 550 SEEQ_STATUS_FIFO_EMPTY) 551 return; 552 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", sc->sc_dev.dv_xname); 553 } 554 555 /* 556 * Wait for the DMA FIFO to fill before reading from it. 557 */ 558 static void 559 ea_await_fifo_full(struct seeq8005_softc *sc) 560 { 561 bus_space_tag_t iot = sc->sc_iot; 562 bus_space_handle_t ioh = sc->sc_ioh; 563 int timeout; 564 565 timeout = 20000; 566 while (--timeout > 0) 567 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 568 SEEQ_STATUS_FIFO_FULL) 569 return; 570 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", sc->sc_dev.dv_xname); 571 } 572 573 /* 574 * write to the buffer memory on the interface 575 * 576 * The buffer address is set to ADDR. 577 * If len != 0 then data is copied from the address starting at buf 578 * to the interface buffer. 579 * BUF must be usable as a u_int16_t *. 580 * If LEN is odd, it must be safe to overwrite one extra byte. 581 */ 582 583 static void 584 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 585 { 586 bus_space_tag_t iot = sc->sc_iot; 587 bus_space_handle_t ioh = sc->sc_ioh; 588 589 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 590 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 591 592 #ifdef DIAGNOSTIC 593 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 594 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 595 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 596 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 597 #endif 598 599 if (addr != -1) { 600 ea_await_fifo_empty(sc); 601 602 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 603 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 604 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 605 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 606 } 607 608 if (len > 0) { 609 if (sc->sc_flags & SF_8BIT) 610 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 611 (u_int8_t *)buf, len); 612 else 613 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 614 /* LINTED: alignment checked above */ 615 (u_int16_t *)buf, len / 2); 616 } 617 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 618 /* Write the last byte */ 619 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, buf[len - 1]); 620 } 621 /* Leave FIFO to empty in the background */ 622 } 623 624 625 /* 626 * read from the buffer memory on the interface 627 * 628 * The buffer address is set to ADDR. 629 * If len != 0 then data is copied from the interface buffer to the 630 * address starting at buf. 631 * BUF must be usable as a u_int16_t *. 632 * If LEN is odd, it must be safe to overwrite one extra byte. 633 */ 634 635 static void 636 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 637 { 638 bus_space_tag_t iot = sc->sc_iot; 639 bus_space_handle_t ioh = sc->sc_ioh; 640 int runup; 641 642 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 643 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 644 645 #ifdef DIAGNOSTIC 646 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 647 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 648 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 649 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 650 #endif 651 652 if (addr != -1) { 653 /* 654 * SEEQ 80C04 bug: 655 * Starting reading from certain addresses seems to cause 656 * us to get bogus results, so we avoid them. 657 */ 658 runup = 0; 659 if (sc->sc_variant == SEEQ_8004 && 660 ((addr & 0x00ff) == 0x00ea || 661 (addr & 0x00ff) == 0x00ee || 662 (addr & 0x00ff) == 0x00f0)) 663 runup = (addr & 0x00ff) - 0x00e8; 664 665 ea_await_fifo_empty(sc); 666 667 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 668 669 /* 670 * 80C04 bug workaround. I found this in the old arm32 "eb" 671 * driver. I've no idea what it does, but it seems to stop 672 * the chip mangling data so often. 673 */ 674 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 675 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 676 ea_await_fifo_empty(sc); 677 678 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 679 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 680 sc->sc_command | SEEQ_CMD_FIFO_READ); 681 682 ea_await_fifo_full(sc); 683 while (runup > 0) { 684 /* LINTED: Reading a volatile _does_ have an effect */ 685 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 686 runup -= 2; 687 } 688 } 689 690 if (len > 0) { 691 if (sc->sc_flags & SF_8BIT) 692 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 693 (u_int8_t *)buf, len); 694 else 695 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 696 /* LINTED: pointer alignment checked above */ 697 (u_int16_t *)buf, len / 2); 698 } 699 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 700 /* Read the last byte */ 701 buf[len - 1] = bus_space_read_2(iot, ioh, SEEQ_BUFWIN); 702 } 703 } 704 705 static void 706 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 707 { 708 709 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 710 sc->sc_config1 | bufcode); 711 } 712 713 /* Must be called at splnet */ 714 static void 715 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 716 { 717 int i; 718 719 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 720 for (i = 0; i < ETHER_ADDR_LEN; ++i) 721 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 722 ea[i]); 723 } 724 725 /* 726 * Initialize interface. 727 * 728 * This should leave the interface in a state for packet reception and 729 * transmission. 730 */ 731 732 static int 733 ea_init(struct ifnet *ifp) 734 { 735 struct seeq8005_softc *sc = ifp->if_softc; 736 bus_space_tag_t iot = sc->sc_iot; 737 bus_space_handle_t ioh = sc->sc_ioh; 738 int s; 739 740 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 741 742 s = splnet(); 743 744 /* First, reset the board. */ 745 746 ea_chipreset(sc); 747 748 /* Set up defaults for the registers */ 749 750 sc->sc_command = 0; 751 sc->sc_config1 = 0; 752 #if BYTE_ORDER == BIG_ENDIAN 753 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 754 #else 755 sc->sc_config2 = 0; 756 #endif 757 sc->sc_config3 = 0; 758 759 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 760 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 761 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 762 if (sc->sc_variant == SEEQ_8004) { 763 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 764 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 765 } 766 767 /* Write the station address - the receiver must be off */ 768 ea_set_address(sc, 0, (u_int8_t *)LLADDR(ifp->if_sadl)); 769 770 /* Split board memory into Rx and Tx. */ 771 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 772 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 773 774 if (sc->sc_variant == SEEQ_8004) { 775 /* Make the interface IFF_SIMPLEX. */ 776 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 777 /* Enable reception of long packets (for vlan(4)). */ 778 sc->sc_config2 |= SEEQ_CFG2_PASS_LONGSHORT; 779 } 780 781 /* Configure rx. */ 782 ea_mc_reset(sc); 783 if (ifp->if_flags & IFF_PROMISC) 784 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 785 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 786 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 787 else 788 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 789 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 790 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 791 792 /* Setup the Rx pointers */ 793 sc->sc_rx_ptr = sc->sc_tx_bufsize; 794 795 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 796 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 797 798 799 /* Place a NULL header at the beginning of the receive area */ 800 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 801 802 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 803 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 804 805 806 /* Configure TX. */ 807 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 808 809 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 810 811 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 812 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 813 814 /* Reset tx buffer pointers */ 815 sc->sc_tx_cur = 0; 816 sc->sc_tx_used = 0; 817 sc->sc_tx_next = 0; 818 819 /* Place a NULL header at the beginning of the transmit area */ 820 ea_writebuf(sc, NULL, 0x0000, 0); 821 822 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 823 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 824 825 sc->sc_command |= SEEQ_CMD_TX_INTEN; 826 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 827 828 /* Turn on Rx */ 829 sc->sc_command |= SEEQ_CMD_RX_INTEN; 830 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 831 sc->sc_command | SEEQ_CMD_RX_ON); 832 833 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 834 835 836 /* Set flags appropriately. */ 837 ifp->if_flags |= IFF_RUNNING; 838 ifp->if_flags &= ~IFF_OACTIVE; 839 sc->sc_enabled = 1; 840 841 /* And start output. */ 842 ea_start(ifp); 843 844 splx(s); 845 return 0; 846 } 847 848 /* 849 * Start output on interface. Get datagrams from the queue and output them, 850 * giving the receiver a chance between datagrams. Call only from splnet or 851 * interrupt level! 852 */ 853 854 static void 855 ea_start(struct ifnet *ifp) 856 { 857 struct seeq8005_softc *sc = ifp->if_softc; 858 int s; 859 860 s = splnet(); 861 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 862 863 /* 864 * Don't do anything if output is active. seeq8005intr() will call 865 * us (actually eatxpacket()) back when the card's ready for more 866 * frames. 867 */ 868 if (ifp->if_flags & IFF_OACTIVE) 869 return; 870 871 /* Mark interface as output active */ 872 873 ifp->if_flags |= IFF_OACTIVE; 874 875 /* tx packets */ 876 877 eatxpacket(sc); 878 splx(s); 879 } 880 881 882 /* 883 * Transfer a packet to the interface buffer and start transmission 884 * 885 * Called at splnet() 886 */ 887 888 void 889 eatxpacket(struct seeq8005_softc *sc) 890 { 891 bus_space_tag_t iot = sc->sc_iot; 892 bus_space_handle_t ioh = sc->sc_ioh; 893 struct mbuf *m0; 894 struct ifnet *ifp; 895 896 ifp = &sc->sc_ethercom.ec_if; 897 898 /* Dequeue the next packet. */ 899 IFQ_DEQUEUE(&ifp->if_snd, m0); 900 901 /* If there's nothing to send, return. */ 902 if (!m0) { 903 ifp->if_flags &= ~IFF_OACTIVE; 904 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 905 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 906 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 907 return; 908 } 909 910 #if NBPFILTER > 0 911 /* Give the packet to the bpf, if any. */ 912 if (ifp->if_bpf) 913 bpf_mtap(ifp->if_bpf, m0); 914 #endif 915 916 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 917 918 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 919 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 920 921 ea_writembuf(sc, m0, 0x0000); 922 m_freem(m0); 923 924 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 925 926 /* Now transmit the datagram. */ 927 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 928 sc->sc_command | SEEQ_CMD_TX_ON); 929 930 /* Make sure we notice if the chip goes silent on us. */ 931 ifp->if_timer = 5; 932 933 DPRINTF(SEEQ_DEBUG_TX, 934 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 935 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 936 } 937 938 /* 939 * Copy a packet from an mbuf to the transmit buffer on the card. 940 * 941 * Puts a valid Tx header at the start of the packet, and a null header at 942 * the end. 943 */ 944 static int 945 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 946 { 947 struct mbuf *m; 948 int len, nextpacket; 949 u_int8_t hdr[4]; 950 951 /* 952 * Copy the datagram to the packet buffer. 953 */ 954 len = 0; 955 for (m = m0; m; m = m->m_next) { 956 if (m->m_len == 0) 957 continue; 958 ea_writebuf(sc, mtod(m, u_char *), bufstart + 4 + len, 959 m->m_len); 960 len += m->m_len; 961 } 962 963 len = max(len, ETHER_MIN_LEN); 964 965 /* Follow it with a NULL packet header */ 966 memset(hdr, 0, 4); 967 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 968 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 969 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 970 971 /* Ok we now have a packet len bytes long in our packet buffer */ 972 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 973 974 /* Write the packet header */ 975 nextpacket = len + 4; 976 hdr[0] = (nextpacket >> 8) & 0xff; 977 hdr[1] = nextpacket & 0xff; 978 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 979 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 980 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 981 ea_writebuf(sc, hdr, 0x0000, 4); 982 983 return len; 984 } 985 986 /* 987 * Ethernet controller interrupt. 988 */ 989 990 int 991 seeq8005intr(void *arg) 992 { 993 struct seeq8005_softc *sc = arg; 994 bus_space_tag_t iot = sc->sc_iot; 995 bus_space_handle_t ioh = sc->sc_ioh; 996 int status, handled; 997 998 handled = 0; 999 1000 /* Get the controller status */ 1001 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 1002 1003 /* Tx interrupt ? */ 1004 if (status & SEEQ_STATUS_TX_INT) { 1005 handled = 1; 1006 1007 /* Acknowledge the interrupt */ 1008 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1009 sc->sc_command | SEEQ_CMD_TX_INTACK); 1010 1011 ea_txint(sc); 1012 } 1013 1014 1015 /* Rx interrupt ? */ 1016 if (status & SEEQ_STATUS_RX_INT) { 1017 handled = 1; 1018 1019 /* Acknowledge the interrupt */ 1020 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1021 sc->sc_command | SEEQ_CMD_RX_INTACK); 1022 1023 /* Processes the received packets */ 1024 ea_rxint(sc); 1025 } 1026 1027 #if NRND > 0 1028 if (handled) 1029 rnd_add_uint32(&sc->rnd_source, status); 1030 #endif 1031 return handled; 1032 } 1033 1034 static void 1035 ea_txint(struct seeq8005_softc *sc) 1036 { 1037 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1038 bus_space_tag_t iot = sc->sc_iot; 1039 bus_space_handle_t ioh = sc->sc_ioh; 1040 u_int8_t txhdr[4]; 1041 u_int txstatus; 1042 1043 ea_readbuf(sc, txhdr, 0x0000, 4); 1044 1045 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1046 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1047 txstatus = txhdr[3]; 1048 1049 /* 1050 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1051 * one collision. On the 8004 we can find out exactly how many 1052 * collisions occurred. 1053 * 1054 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1055 * completed. 1056 * 1057 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1058 * occurred and the packet transmission was aborted. 1059 * This situation is untested as present. 1060 * 1061 * The SEEQ_TXSTAT_BABBLE is untested as it should only be set 1062 * when we deliberately transmit oversized packets (e.g. for 1063 * 802.1Q). 1064 */ 1065 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1066 switch (sc->sc_variant) { 1067 case SEEQ_8004: { 1068 int colls; 1069 1070 /* 1071 * The 8004 contains a 4 bit collision count 1072 * in the status register. 1073 */ 1074 1075 /* This appears to be broken on 80C04.AE */ 1076 /* ifp->if_collisions += 1077 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1078 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1079 1080 /* Use the TX Collision register */ 1081 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1082 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1083 ifp->if_collisions += colls; 1084 break; 1085 } 1086 case SEEQ_8005: 1087 /* We known there was at least 1 collision */ 1088 ifp->if_collisions++; 1089 break; 1090 } 1091 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1092 printf("seeq_intr: col16 %x\n", txstatus); 1093 ifp->if_collisions += 16; 1094 ifp->if_oerrors++; 1095 } 1096 1097 /* Have we completed transmission on the packet ? */ 1098 if (txstatus & SEEQ_PKTSTAT_DONE) { 1099 /* Clear watchdog timer. */ 1100 ifp->if_timer = 0; 1101 ifp->if_flags &= ~IFF_OACTIVE; 1102 1103 /* Update stats */ 1104 ifp->if_opackets++; 1105 1106 /* Tx next packet */ 1107 1108 eatxpacket(sc); 1109 } 1110 } 1111 1112 void 1113 ea_rxint(struct seeq8005_softc *sc) 1114 { 1115 bus_space_tag_t iot = sc->sc_iot; 1116 bus_space_handle_t ioh = sc->sc_ioh; 1117 u_int addr; 1118 int len; 1119 int ctrl; 1120 int ptr; 1121 int status; 1122 u_int8_t rxhdr[4]; 1123 struct ifnet *ifp; 1124 1125 ifp = &sc->sc_ethercom.ec_if; 1126 1127 1128 /* We start from the last rx pointer position */ 1129 addr = sc->sc_rx_ptr; 1130 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1131 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1132 1133 do { 1134 /* Read rx header */ 1135 ea_readbuf(sc, rxhdr, addr, 4); 1136 1137 /* Split the packet header */ 1138 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1139 ctrl = rxhdr[2]; 1140 status = rxhdr[3]; 1141 1142 DPRINTF(SEEQ_DEBUG_RX, 1143 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1144 addr, ptr, ctrl, status)); 1145 1146 /* Zero packet ptr ? then must be null header so exit */ 1147 if (ptr == 0) break; 1148 1149 /* Sanity-check the next-packet pointer and flags. */ 1150 if (__predict_false(ptr < sc->sc_tx_bufsize || 1151 (ctrl & SEEQ_PKTCMD_TX))) { 1152 ++ifp->if_ierrors; 1153 log(LOG_ERR, 1154 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1155 sc->sc_dev.dv_xname, addr, ptr); 1156 ea_init(ifp); 1157 return; 1158 } 1159 1160 /* Get packet length */ 1161 len = (ptr - addr) - 4; 1162 1163 if (len < 0) 1164 len += sc->sc_rx_bufsize; 1165 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1166 1167 /* Has the packet rx completed ? if not then exit */ 1168 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1169 break; 1170 1171 /* 1172 * Did we have any errors? then note error and go to 1173 * next packet 1174 */ 1175 if (__predict_false(status & 1176 (SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR | 1177 SEEQ_RXSTAT_SHORT_FRAME))) { 1178 ++ifp->if_ierrors; 1179 log(LOG_WARNING, 1180 "%s: rx packet error at %04x (err=%02x)\n", 1181 sc->sc_dev.dv_xname, addr, status & 0x0f); 1182 /* XXX shouldn't need to reset if it's genuine. */ 1183 ea_init(ifp); 1184 return; 1185 } 1186 /* 1187 * Is the packet too big? We allow slightly oversize packets 1188 * for vlan(4) and tcpdump purposes, but the rest of the world 1189 * wants incoming packets in a single mbuf cluster. 1190 */ 1191 if (__predict_false(len > MCLBYTES)) { 1192 ++ifp->if_ierrors; 1193 log(LOG_ERR, 1194 "%s: rx packet size error at %04x (len=%d)\n", 1195 sc->sc_dev.dv_xname, addr, len); 1196 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1197 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, 1198 sc->sc_config2); 1199 ea_init(ifp); 1200 return; 1201 } 1202 1203 ifp->if_ipackets++; 1204 /* Pass data up to upper levels. */ 1205 ea_read(sc, addr + 4, len); 1206 1207 addr = ptr; 1208 } while (len != 0); 1209 1210 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1211 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1212 1213 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1214 1215 /* Store new rx pointer */ 1216 sc->sc_rx_ptr = addr; 1217 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1218 1219 /* Make sure the receiver is on */ 1220 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1221 sc->sc_command | SEEQ_CMD_RX_ON); 1222 } 1223 1224 1225 /* 1226 * Pass a packet up to the higher levels. 1227 */ 1228 1229 static void 1230 ea_read(struct seeq8005_softc *sc, int addr, int len) 1231 { 1232 struct mbuf *m; 1233 struct ifnet *ifp; 1234 1235 ifp = &sc->sc_ethercom.ec_if; 1236 1237 /* Pull packet off interface. */ 1238 m = ea_get(sc, addr, len, ifp); 1239 if (m == 0) 1240 return; 1241 1242 #if NBPFILTER > 0 1243 /* 1244 * Check if there's a BPF listener on this interface. 1245 * If so, hand off the raw packet to bpf. 1246 */ 1247 if (ifp->if_bpf) 1248 bpf_mtap(ifp->if_bpf, m); 1249 #endif 1250 1251 (*ifp->if_input)(ifp, m); 1252 } 1253 1254 /* 1255 * Pull read data off a interface. Len is length of data, with local net 1256 * header stripped. We copy the data into mbufs. When full cluster sized 1257 * units are present we copy into clusters. 1258 */ 1259 1260 struct mbuf * 1261 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1262 { 1263 struct mbuf *top, **mp, *m; 1264 int len; 1265 u_int cp, epkt; 1266 1267 cp = addr; 1268 epkt = cp + totlen; 1269 1270 MGETHDR(m, M_DONTWAIT, MT_DATA); 1271 if (m == 0) 1272 return 0; 1273 m->m_pkthdr.rcvif = ifp; 1274 m->m_pkthdr.len = totlen; 1275 m->m_len = MHLEN; 1276 top = 0; 1277 mp = ⊤ 1278 1279 while (totlen > 0) { 1280 if (top) { 1281 MGET(m, M_DONTWAIT, MT_DATA); 1282 if (m == 0) { 1283 m_freem(top); 1284 return 0; 1285 } 1286 m->m_len = MLEN; 1287 } 1288 len = min(totlen, epkt - cp); 1289 if (len >= MINCLSIZE) { 1290 MCLGET(m, M_DONTWAIT); 1291 if (m->m_flags & M_EXT) 1292 m->m_len = len = min(len, MCLBYTES); 1293 else 1294 len = m->m_len; 1295 } else { 1296 /* 1297 * Place initial small packet/header at end of mbuf. 1298 */ 1299 if (len < m->m_len) { 1300 if (top == 0 && len + max_linkhdr <= m->m_len) 1301 m->m_data += max_linkhdr; 1302 m->m_len = len; 1303 } else 1304 len = m->m_len; 1305 } 1306 if (top == 0) { 1307 /* Make sure the payload is aligned */ 1308 caddr_t newdata = (caddr_t) 1309 ALIGN(m->m_data + sizeof(struct ether_header)) - 1310 sizeof(struct ether_header); 1311 len -= newdata - m->m_data; 1312 m->m_len = len; 1313 m->m_data = newdata; 1314 } 1315 ea_readbuf(sc, mtod(m, u_char *), 1316 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1317 len); 1318 cp += len; 1319 *mp = m; 1320 mp = &m->m_next; 1321 totlen -= len; 1322 if (cp == epkt) 1323 cp = addr; 1324 } 1325 1326 return top; 1327 } 1328 1329 /* 1330 * Process an ioctl request. Mostly boilerplate. 1331 */ 1332 static int 1333 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1334 { 1335 struct seeq8005_softc *sc = ifp->if_softc; 1336 int s, error = 0; 1337 1338 s = splnet(); 1339 switch (cmd) { 1340 1341 default: 1342 error = ether_ioctl(ifp, cmd, data); 1343 if (error == ENETRESET) { 1344 /* 1345 * Multicast list has changed; set the hardware filter 1346 * accordingly. 1347 */ 1348 ea_mc_reset(sc); 1349 error = 0; 1350 } 1351 break; 1352 } 1353 1354 splx(s); 1355 return error; 1356 } 1357 1358 /* Must be called at splnet() */ 1359 1360 static void 1361 ea_mc_reset(struct seeq8005_softc *sc) 1362 { 1363 1364 switch (sc->sc_variant) { 1365 case SEEQ_8004: 1366 ea_mc_reset_8004(sc); 1367 return; 1368 case SEEQ_8005: 1369 ea_mc_reset_8005(sc); 1370 return; 1371 } 1372 } 1373 1374 static void 1375 ea_mc_reset_8004(struct seeq8005_softc *sc) 1376 { 1377 struct ethercom *ec = &sc->sc_ethercom; 1378 struct ifnet *ifp = &ec->ec_if; 1379 struct ether_multi *enm; 1380 u_int32_t crc; 1381 int i; 1382 struct ether_multistep step; 1383 u_int8_t af[8]; 1384 1385 /* 1386 * Set up multicast address filter by passing all multicast addresses 1387 * through a crc generator, and then using bits 2 - 7 as an index 1388 * into the 64 bit logical address filter. The high order bits 1389 * selects the word, while the rest of the bits select the bit within 1390 * the word. 1391 */ 1392 1393 if (ifp->if_flags & IFF_PROMISC) { 1394 ifp->if_flags |= IFF_ALLMULTI; 1395 for (i = 0; i < 8; i++) 1396 af[i] = 0xff; 1397 return; 1398 } 1399 for (i = 0; i < 8; i++) 1400 af[i] = 0; 1401 ETHER_FIRST_MULTI(step, ec, enm); 1402 while (enm != NULL) { 1403 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1404 sizeof(enm->enm_addrlo)) != 0) { 1405 /* 1406 * We must listen to a range of multicast addresses. 1407 * For now, just accept all multicasts, rather than 1408 * trying to set only those filter bits needed to match 1409 * the range. (At this time, the only use of address 1410 * ranges is for IP multicast routing, for which the 1411 * range is big enough to require all bits set.) 1412 */ 1413 ifp->if_flags |= IFF_ALLMULTI; 1414 for (i = 0; i < 8; i++) 1415 af[i] = 0xff; 1416 break; 1417 } 1418 1419 crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1420 1421 /* Just want the 6 most significant bits. */ 1422 crc = (crc >> 2) & 0x3f; 1423 1424 /* Turn on the corresponding bit in the filter. */ 1425 af[crc >> 3] |= 1 << (crc & 0x7); 1426 1427 ETHER_NEXT_MULTI(step, enm); 1428 } 1429 ifp->if_flags &= ~IFF_ALLMULTI; 1430 1431 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1432 for (i = 0; i < 8; ++i) 1433 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1434 SEEQ_BUFWIN, af[i]); 1435 } 1436 1437 static void 1438 ea_mc_reset_8005(struct seeq8005_softc *sc) 1439 { 1440 struct ether_multi *enm; 1441 struct ether_multistep step; 1442 int naddr, maxaddrs; 1443 1444 naddr = 0; 1445 maxaddrs = 5; 1446 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1447 while (enm != NULL) { 1448 /* Have we got space? */ 1449 if (naddr >= maxaddrs || 1450 memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1451 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1452 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1453 return; 1454 } 1455 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1456 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1457 naddr++; 1458 ETHER_NEXT_MULTI(step, enm); 1459 } 1460 for (; naddr < maxaddrs; naddr++) 1461 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1462 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1463 sc->sc_config1); 1464 } 1465 1466 /* 1467 * Device timeout routine. 1468 */ 1469 1470 static void 1471 ea_watchdog(struct ifnet *ifp) 1472 { 1473 struct seeq8005_softc *sc = ifp->if_softc; 1474 1475 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1476 sc->sc_dev.dv_xname, 1477 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1478 ifp->if_oerrors++; 1479 1480 /* Kick the interface */ 1481 1482 ea_init(ifp); 1483 1484 ifp->if_timer = 0; 1485 } 1486 1487 /* End of if_ea.c */ 1488
Indexes created Tue Sep 30 17:09:57 GMT 2025