seeq8005.c revision 1.47
1 /* $NetBSD: seeq8005.c,v 1.47 2012/05/09 07:52:52 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45 /* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52 /* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56 /* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: seeq8005.c,v 1.47 2012/05/09 07:52:52 martin Exp $"); 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/endian.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 76 #include <net/if.h> 77 #include <net/if_dl.h> 78 #include <net/if_types.h> 79 #include <net/if_ether.h> 80 #include <net/if_media.h> 81 82 #include <net/bpf.h> 83 #include <net/bpfdesc.h> 84 85 #include <sys/rnd.h> 86 87 #include <sys/bus.h> 88 #include <sys/intr.h> 89 90 #include <dev/ic/seeq8005reg.h> 91 #include <dev/ic/seeq8005var.h> 92 93 /*#define SEEQ_DEBUG*/ 94 95 /* for debugging convenience */ 96 #ifdef SEEQ8005_DEBUG 97 #define SEEQ_DEBUG_MISC 1 98 #define SEEQ_DEBUG_TX 2 99 #define SEEQ_DEBUG_RX 4 100 #define SEEQ_DEBUG_PKT 8 101 #define SEEQ_DEBUG_TXINT 16 102 #define SEEQ_DEBUG_RXINT 32 103 int seeq8005_debug = 0; 104 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 105 #else 106 #define DPRINTF(f, x) 107 #endif 108 109 #define SEEQ_TX_BUFFER_SIZE 0x800 /* (> ETHER_MAX_LEN) */ 110 111 #define SEEQ_READ16(sc, iot, ioh, reg) \ 112 ((sc)->sc_flags & SF_8BIT ? \ 113 (bus_space_read_1((iot), (ioh), (reg)) | \ 114 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 115 (bus_space_read_2((iot), (ioh), (reg)))) 116 117 #define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 118 if ((sc)->sc_flags & SF_8BIT) { \ 119 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 120 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 121 } else \ 122 bus_space_write_2((iot), (ioh), (reg), (val)); \ 123 } while (/*CONSTCOND*/0) 124 125 /* 126 * prototypes 127 */ 128 129 static int ea_init(struct ifnet *); 130 static int ea_ioctl(struct ifnet *, u_long, void *); 131 static void ea_start(struct ifnet *); 132 static void ea_watchdog(struct ifnet *); 133 static void ea_chipreset(struct seeq8005_softc *); 134 static void ea_ramtest(struct seeq8005_softc *); 135 static int ea_stoptx(struct seeq8005_softc *); 136 static int ea_stoprx(struct seeq8005_softc *); 137 static void ea_stop(struct ifnet *, int); 138 static void ea_await_fifo_empty(struct seeq8005_softc *); 139 static void ea_await_fifo_full(struct seeq8005_softc *); 140 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 141 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 142 static void ea_select_buffer(struct seeq8005_softc *, int); 143 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 144 static void ea_read(struct seeq8005_softc *, int, int); 145 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 146 static void ea_txint(struct seeq8005_softc *); 147 static void ea_rxint(struct seeq8005_softc *); 148 static void eatxpacket(struct seeq8005_softc *); 149 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 150 static void ea_mc_reset(struct seeq8005_softc *); 151 static void ea_mc_reset_8004(struct seeq8005_softc *); 152 static void ea_mc_reset_8005(struct seeq8005_softc *); 153 static int ea_mediachange(struct ifnet *); 154 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 155 156 static u_char* padbuf = NULL; 157 158 159 /* 160 * Attach chip. 161 */ 162 163 void 164 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 165 int nmedia, int defmedia) 166 { 167 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 168 bus_space_tag_t iot = sc->sc_iot; 169 bus_space_handle_t ioh = sc->sc_ioh; 170 u_int id; 171 172 KASSERT(myaddr != NULL); 173 printf(" address %s", ether_sprintf(myaddr)); 174 175 /* Stop the board. */ 176 177 ea_chipreset(sc); 178 179 /* Work out data bus width. */ 180 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 181 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 182 /* Try 8-bit mode */ 183 sc->sc_flags |= SF_8BIT; 184 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 185 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 186 aprint_normal("\n"); 187 aprint_error_dev(&sc->sc_dev, "Cannot determine data bus width\n"); 188 return; 189 } 190 } 191 192 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 193 194 /* Get the product ID */ 195 196 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 197 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 198 199 switch (id & SEEQ_PRODUCTID_MASK) { 200 case SEEQ_PRODUCTID_8004: 201 sc->sc_variant = SEEQ_8004; 202 switch (id & SEEQ_PRODUCTID_REV_MASK) { 203 case SEEQ_PRODUCTID_REV_80C04: 204 printf(", SEEQ 80C04\n"); 205 break; 206 case SEEQ_PRODUCTID_REV_80C04A: 207 printf(", SEEQ 80C04A\n"); 208 break; 209 default: 210 /* Unknown SEEQ 8004 variants */ 211 printf(", SEEQ 8004 rev %x\n", 212 id & SEEQ_PRODUCTID_REV_MASK); 213 break; 214 } 215 break; 216 default: /* XXX */ 217 sc->sc_variant = SEEQ_8005; 218 printf(", SEEQ 8005\n"); 219 break; 220 } 221 222 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 223 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 224 225 /* 226 * Set up tx and rx buffers. 227 * 228 * We use approximately a quarter of the packet memory for TX 229 * buffers and the rest for RX buffers 230 */ 231 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 232 sc->sc_tx_bufs = 1; 233 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 234 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 235 sc->sc_enabled = 0; 236 237 /* Test the RAM */ 238 ea_ramtest(sc); 239 240 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 241 device_xname(&sc->sc_dev), sc->sc_buffersize >> 10, 242 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 243 244 if (padbuf == NULL) { 245 padbuf = malloc(ETHER_MIN_LEN - ETHER_CRC_LEN, M_DEVBUF, 246 M_ZERO | M_NOWAIT); 247 if (padbuf == NULL) { 248 aprint_error_dev(&sc->sc_dev, "can't allocate pad buffer\n"); 249 return; 250 } 251 } 252 253 /* Initialise ifnet structure. */ 254 255 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 256 ifp->if_softc = sc; 257 ifp->if_start = ea_start; 258 ifp->if_ioctl = ea_ioctl; 259 ifp->if_init = ea_init; 260 ifp->if_stop = ea_stop; 261 ifp->if_watchdog = ea_watchdog; 262 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 263 if (sc->sc_variant == SEEQ_8004) 264 ifp->if_flags |= IFF_SIMPLEX; 265 IFQ_SET_READY(&ifp->if_snd); 266 267 /* Initialize media goo. */ 268 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 269 if (media != NULL) { 270 int i; 271 272 for (i = 0; i < nmedia; i++) 273 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 274 ifmedia_set(&sc->sc_media, defmedia); 275 } else { 276 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 277 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 278 } 279 280 /* We can support 802.1Q VLAN-sized frames. */ 281 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 282 283 /* Now we can attach the interface. */ 284 285 if_attach(ifp); 286 ether_ifattach(ifp, myaddr); 287 288 printf("\n"); 289 290 /* After \n because it can print a line of its own. */ 291 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 292 RND_TYPE_NET, 0); 293 } 294 295 /* 296 * Media change callback. 297 */ 298 static int 299 ea_mediachange(struct ifnet *ifp) 300 { 301 struct seeq8005_softc *sc = ifp->if_softc; 302 303 if (sc->sc_mediachange) 304 return ((*sc->sc_mediachange)(sc)); 305 return (EINVAL); 306 } 307 308 /* 309 * Media status callback. 310 */ 311 static void 312 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 313 { 314 struct seeq8005_softc *sc = ifp->if_softc; 315 316 if (sc->sc_enabled == 0) { 317 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 318 ifmr->ifm_status = 0; 319 return; 320 } 321 322 if (sc->sc_mediastatus) 323 (*sc->sc_mediastatus)(sc, ifmr); 324 } 325 326 /* 327 * Test the RAM on the ethernet card. 328 */ 329 330 void 331 ea_ramtest(struct seeq8005_softc *sc) 332 { 333 bus_space_tag_t iot = sc->sc_iot; 334 bus_space_handle_t ioh = sc->sc_ioh; 335 int loop; 336 u_int sum = 0; 337 338 /* 339 * Test the buffer memory on the board. 340 * Write simple pattens to it and read them back. 341 */ 342 343 /* Set up the whole buffer RAM for writing */ 344 345 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 346 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 347 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 348 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 349 350 #define SEEQ_RAMTEST_LOOP(value) \ 351 do { \ 352 /* Set the write start address and write a pattern */ \ 353 ea_writebuf(sc, NULL, 0x0000, 0); \ 354 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 355 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 356 \ 357 /* Set the read start address and verify the pattern */ \ 358 ea_readbuf(sc, NULL, 0x0000, 0); \ 359 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 360 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 361 ++sum; \ 362 } while (/*CONSTCOND*/0) 363 364 SEEQ_RAMTEST_LOOP(loop); 365 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 366 SEEQ_RAMTEST_LOOP(0xaa55); 367 SEEQ_RAMTEST_LOOP(0x55aa); 368 369 /* Report */ 370 371 if (sum > 0) 372 aprint_error_dev(&sc->sc_dev, "buffer RAM failed self test, %d faults\n", sum); 373 } 374 375 376 /* 377 * Stop the tx interface. 378 * 379 * Returns 0 if the tx was already stopped or 1 if it was active 380 */ 381 382 static int 383 ea_stoptx(struct seeq8005_softc *sc) 384 { 385 bus_space_tag_t iot = sc->sc_iot; 386 bus_space_handle_t ioh = sc->sc_ioh; 387 int timeout; 388 int status; 389 390 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 391 392 sc->sc_enabled = 0; 393 394 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 395 if (!(status & SEEQ_STATUS_TX_ON)) 396 return 0; 397 398 /* Stop any tx and wait for confirmation */ 399 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 400 sc->sc_command | SEEQ_CMD_TX_OFF); 401 402 timeout = 20000; 403 do { 404 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 405 delay(1); 406 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 407 if (timeout == 0) 408 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 409 device_xname(&sc->sc_dev)); 410 411 /* Clear any pending tx interrupt */ 412 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 413 sc->sc_command | SEEQ_CMD_TX_INTACK); 414 return 1; 415 } 416 417 418 /* 419 * Stop the rx interface. 420 * 421 * Returns 0 if the tx was already stopped or 1 if it was active 422 */ 423 424 static int 425 ea_stoprx(struct seeq8005_softc *sc) 426 { 427 bus_space_tag_t iot = sc->sc_iot; 428 bus_space_handle_t ioh = sc->sc_ioh; 429 int timeout; 430 int status; 431 432 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 433 434 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 435 if (!(status & SEEQ_STATUS_RX_ON)) 436 return 0; 437 438 /* Stop any rx and wait for confirmation */ 439 440 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 441 sc->sc_command | SEEQ_CMD_RX_OFF); 442 443 timeout = 20000; 444 do { 445 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 446 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 447 if (timeout == 0) 448 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 449 device_xname(&sc->sc_dev)); 450 451 /* Clear any pending rx interrupt */ 452 453 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 454 sc->sc_command | SEEQ_CMD_RX_INTACK); 455 return 1; 456 } 457 458 459 /* 460 * Stop interface. 461 * Stop all IO and shut the interface down 462 */ 463 464 /* ARGSUSED */ 465 static void 466 ea_stop(struct ifnet *ifp, int disable) 467 { 468 struct seeq8005_softc *sc = ifp->if_softc; 469 bus_space_tag_t iot = sc->sc_iot; 470 bus_space_handle_t ioh = sc->sc_ioh; 471 472 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 473 474 /* Stop all IO */ 475 ea_stoptx(sc); 476 ea_stoprx(sc); 477 478 /* Disable rx and tx interrupts */ 479 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 480 481 /* Clear any pending interrupts */ 482 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 483 sc->sc_command | SEEQ_CMD_RX_INTACK | 484 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 485 SEEQ_CMD_BW_INTACK); 486 487 if (sc->sc_variant == SEEQ_8004) { 488 /* Put the chip to sleep */ 489 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 490 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 491 sc->sc_config3 | SEEQ_CFG3_SLEEP); 492 } 493 494 /* Cancel any watchdog timer */ 495 sc->sc_ethercom.ec_if.if_timer = 0; 496 } 497 498 499 /* 500 * Reset the chip 501 * Following this the software registers are reset 502 */ 503 504 static void 505 ea_chipreset(struct seeq8005_softc *sc) 506 { 507 bus_space_tag_t iot = sc->sc_iot; 508 bus_space_handle_t ioh = sc->sc_ioh; 509 510 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 511 512 /* Reset the controller. Min of 4us delay here */ 513 514 /* 515 * This can be called before we know whether the chip is in 8- or 516 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 517 * harmless in 8-bit mode, so we do that second. 518 */ 519 520 /* In 16-bit mode, this will munge the PreamSelect bit. */ 521 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 522 delay(4); 523 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 524 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 525 delay(4); 526 527 sc->sc_command = 0; 528 sc->sc_config1 = 0; 529 sc->sc_config2 = 0; 530 sc->sc_config3 = 0; 531 } 532 533 534 /* 535 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 536 * switching the FIFO from write to read. We also use it when changing 537 * the address for writes. 538 */ 539 static void 540 ea_await_fifo_empty(struct seeq8005_softc *sc) 541 { 542 bus_space_tag_t iot = sc->sc_iot; 543 bus_space_handle_t ioh = sc->sc_ioh; 544 int timeout; 545 546 timeout = 20000; 547 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 548 SEEQ_STATUS_FIFO_DIR) != 0) 549 return; /* FIFO is reading anyway. */ 550 while (--timeout > 0) 551 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 552 SEEQ_STATUS_FIFO_EMPTY) 553 return; 554 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", device_xname(&sc->sc_dev)); 555 } 556 557 /* 558 * Wait for the DMA FIFO to fill before reading from it. 559 */ 560 static void 561 ea_await_fifo_full(struct seeq8005_softc *sc) 562 { 563 bus_space_tag_t iot = sc->sc_iot; 564 bus_space_handle_t ioh = sc->sc_ioh; 565 int timeout; 566 567 timeout = 20000; 568 while (--timeout > 0) 569 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 570 SEEQ_STATUS_FIFO_FULL) 571 return; 572 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", device_xname(&sc->sc_dev)); 573 } 574 575 /* 576 * write to the buffer memory on the interface 577 * 578 * The buffer address is set to ADDR. 579 * If len != 0 then data is copied from the address starting at buf 580 * to the interface buffer. 581 * BUF must be usable as a u_int16_t *. 582 * If LEN is odd, it must be safe to overwrite one extra byte. 583 */ 584 585 static void 586 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 587 { 588 bus_space_tag_t iot = sc->sc_iot; 589 bus_space_handle_t ioh = sc->sc_ioh; 590 591 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 592 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 593 594 #ifdef DIAGNOSTIC 595 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 596 panic("%s: unaligned writebuf", device_xname(&sc->sc_dev)); 597 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 598 panic("%s: writebuf out of range", device_xname(&sc->sc_dev)); 599 #endif 600 601 if (addr != -1) { 602 ea_await_fifo_empty(sc); 603 604 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 605 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 606 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 607 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 608 } 609 610 if (len > 0) { 611 if (sc->sc_flags & SF_8BIT) 612 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 613 (u_int8_t *)buf, len); 614 else 615 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 616 /* LINTED: alignment checked above */ 617 (u_int16_t *)buf, len / 2); 618 } 619 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 620 /* Write the last byte */ 621 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, buf[len - 1]); 622 } 623 /* Leave FIFO to empty in the background */ 624 } 625 626 627 /* 628 * read from the buffer memory on the interface 629 * 630 * The buffer address is set to ADDR. 631 * If len != 0 then data is copied from the interface buffer to the 632 * address starting at buf. 633 * BUF must be usable as a u_int16_t *. 634 * If LEN is odd, it must be safe to overwrite one extra byte. 635 */ 636 637 static void 638 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 639 { 640 bus_space_tag_t iot = sc->sc_iot; 641 bus_space_handle_t ioh = sc->sc_ioh; 642 int runup; 643 644 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 645 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 646 647 #ifdef DIAGNOSTIC 648 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 649 panic("%s: unaligned readbuf", device_xname(&sc->sc_dev)); 650 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 651 panic("%s: readbuf out of range", device_xname(&sc->sc_dev)); 652 #endif 653 654 if (addr != -1) { 655 /* 656 * SEEQ 80C04 bug: 657 * Starting reading from certain addresses seems to cause 658 * us to get bogus results, so we avoid them. 659 */ 660 runup = 0; 661 if (sc->sc_variant == SEEQ_8004 && 662 ((addr & 0x00ff) == 0x00ea || 663 (addr & 0x00ff) == 0x00ee || 664 (addr & 0x00ff) == 0x00f0)) 665 runup = (addr & 0x00ff) - 0x00e8; 666 667 ea_await_fifo_empty(sc); 668 669 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 670 671 /* 672 * 80C04 bug workaround. I found this in the old arm32 "eb" 673 * driver. I've no idea what it does, but it seems to stop 674 * the chip mangling data so often. 675 */ 676 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 677 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 678 ea_await_fifo_empty(sc); 679 680 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 681 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 682 sc->sc_command | SEEQ_CMD_FIFO_READ); 683 684 ea_await_fifo_full(sc); 685 while (runup > 0) { 686 /* LINTED: Reading a volatile _does_ have an effect */ 687 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 688 runup -= 2; 689 } 690 } 691 692 if (len > 0) { 693 if (sc->sc_flags & SF_8BIT) 694 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 695 (u_int8_t *)buf, len); 696 else 697 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 698 /* LINTED: pointer alignment checked above */ 699 (u_int16_t *)buf, len / 2); 700 } 701 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 702 /* Read the last byte */ 703 buf[len - 1] = bus_space_read_2(iot, ioh, SEEQ_BUFWIN); 704 } 705 } 706 707 static void 708 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 709 { 710 711 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 712 sc->sc_config1 | bufcode); 713 } 714 715 /* Must be called at splnet */ 716 static void 717 ea_set_address(struct seeq8005_softc *sc, int which, const u_int8_t *ea) 718 { 719 int i; 720 721 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 722 for (i = 0; i < ETHER_ADDR_LEN; ++i) 723 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 724 ea[i]); 725 } 726 727 /* 728 * Initialize interface. 729 * 730 * This should leave the interface in a state for packet reception and 731 * transmission. 732 */ 733 734 static int 735 ea_init(struct ifnet *ifp) 736 { 737 struct seeq8005_softc *sc = ifp->if_softc; 738 bus_space_tag_t iot = sc->sc_iot; 739 bus_space_handle_t ioh = sc->sc_ioh; 740 int s; 741 742 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 743 744 s = splnet(); 745 746 /* First, reset the board. */ 747 748 ea_chipreset(sc); 749 750 /* Set up defaults for the registers */ 751 752 sc->sc_command = 0; 753 sc->sc_config1 = 0; 754 #if BYTE_ORDER == BIG_ENDIAN 755 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 756 #else 757 sc->sc_config2 = 0; 758 #endif 759 sc->sc_config3 = 0; 760 761 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 762 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 763 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 764 if (sc->sc_variant == SEEQ_8004) { 765 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 766 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 767 } 768 769 /* Write the station address - the receiver must be off */ 770 ea_set_address(sc, 0, (const u_int8_t *)CLLADDR(ifp->if_sadl)); 771 772 /* Split board memory into Rx and Tx. */ 773 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 774 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 775 776 if (sc->sc_variant == SEEQ_8004) { 777 /* Make the interface IFF_SIMPLEX. */ 778 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 779 /* Enable reception of long packets (for vlan(4)). */ 780 sc->sc_config2 |= SEEQ_CFG2_PASS_LONGSHORT; 781 } 782 783 /* Configure rx. */ 784 ea_mc_reset(sc); 785 if (ifp->if_flags & IFF_PROMISC) 786 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 787 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 788 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 789 else 790 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 791 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 792 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 793 794 /* Setup the Rx pointers */ 795 sc->sc_rx_ptr = sc->sc_tx_bufsize; 796 797 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 798 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 799 800 801 /* Place a NULL header at the beginning of the receive area */ 802 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 803 804 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 805 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 806 807 808 /* Configure TX. */ 809 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 810 811 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 812 813 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 814 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 815 816 /* Reset tx buffer pointers */ 817 sc->sc_tx_cur = 0; 818 sc->sc_tx_used = 0; 819 sc->sc_tx_next = 0; 820 821 /* Place a NULL header at the beginning of the transmit area */ 822 ea_writebuf(sc, NULL, 0x0000, 0); 823 824 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 825 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 826 827 sc->sc_command |= SEEQ_CMD_TX_INTEN; 828 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 829 830 /* Turn on Rx */ 831 sc->sc_command |= SEEQ_CMD_RX_INTEN; 832 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 833 sc->sc_command | SEEQ_CMD_RX_ON); 834 835 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 836 837 838 /* Set flags appropriately. */ 839 ifp->if_flags |= IFF_RUNNING; 840 ifp->if_flags &= ~IFF_OACTIVE; 841 sc->sc_enabled = 1; 842 843 /* And start output. */ 844 ea_start(ifp); 845 846 splx(s); 847 return 0; 848 } 849 850 /* 851 * Start output on interface. Get datagrams from the queue and output them, 852 * giving the receiver a chance between datagrams. Call only from splnet or 853 * interrupt level! 854 */ 855 856 static void 857 ea_start(struct ifnet *ifp) 858 { 859 struct seeq8005_softc *sc = ifp->if_softc; 860 int s; 861 862 s = splnet(); 863 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 864 865 /* 866 * Don't do anything if output is active. seeq8005intr() will call 867 * us (actually eatxpacket()) back when the card's ready for more 868 * frames. 869 */ 870 if (ifp->if_flags & IFF_OACTIVE) 871 return; 872 873 /* Mark interface as output active */ 874 875 ifp->if_flags |= IFF_OACTIVE; 876 877 /* tx packets */ 878 879 eatxpacket(sc); 880 splx(s); 881 } 882 883 884 /* 885 * Transfer a packet to the interface buffer and start transmission 886 * 887 * Called at splnet() 888 */ 889 890 void 891 eatxpacket(struct seeq8005_softc *sc) 892 { 893 bus_space_tag_t iot = sc->sc_iot; 894 bus_space_handle_t ioh = sc->sc_ioh; 895 struct mbuf *m0; 896 struct ifnet *ifp; 897 898 ifp = &sc->sc_ethercom.ec_if; 899 900 /* Dequeue the next packet. */ 901 IFQ_DEQUEUE(&ifp->if_snd, m0); 902 903 /* If there's nothing to send, return. */ 904 if (!m0) { 905 ifp->if_flags &= ~IFF_OACTIVE; 906 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 907 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 908 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 909 return; 910 } 911 912 /* Give the packet to the bpf, if any. */ 913 bpf_mtap(ifp, m0); 914 915 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 916 917 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 918 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 919 920 ea_writembuf(sc, m0, 0x0000); 921 m_freem(m0); 922 923 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 924 925 /* Now transmit the datagram. */ 926 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 927 sc->sc_command | SEEQ_CMD_TX_ON); 928 929 /* Make sure we notice if the chip goes silent on us. */ 930 ifp->if_timer = 5; 931 932 DPRINTF(SEEQ_DEBUG_TX, 933 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 934 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 935 } 936 937 /* 938 * Copy a packet from an mbuf to the transmit buffer on the card. 939 * 940 * Puts a valid Tx header at the start of the packet, and a null header at 941 * the end. 942 */ 943 static int 944 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 945 { 946 struct mbuf *m; 947 int len, nextpacket; 948 u_int8_t hdr[4]; 949 950 /* 951 * Copy the datagram to the packet buffer. 952 */ 953 len = 0; 954 for (m = m0; m; m = m->m_next) { 955 if (m->m_len == 0) 956 continue; 957 ea_writebuf(sc, mtod(m, u_char *), bufstart + 4 + len, 958 m->m_len); 959 len += m->m_len; 960 } 961 962 if (len < ETHER_MIN_LEN) { 963 ea_writebuf(sc, padbuf, bufstart + 4 + len, 964 ETHER_MIN_LEN - len); 965 len = ETHER_MIN_LEN; 966 } 967 968 /* Follow it with a NULL packet header */ 969 memset(hdr, 0, 4); 970 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 971 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 972 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 973 974 /* Ok we now have a packet len bytes long in our packet buffer */ 975 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 976 977 /* Write the packet header */ 978 nextpacket = len + 4; 979 hdr[0] = (nextpacket >> 8) & 0xff; 980 hdr[1] = nextpacket & 0xff; 981 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 982 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 983 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 984 ea_writebuf(sc, hdr, 0x0000, 4); 985 986 return len; 987 } 988 989 /* 990 * Ethernet controller interrupt. 991 */ 992 993 int 994 seeq8005intr(void *arg) 995 { 996 struct seeq8005_softc *sc = arg; 997 bus_space_tag_t iot = sc->sc_iot; 998 bus_space_handle_t ioh = sc->sc_ioh; 999 int status, handled; 1000 1001 handled = 0; 1002 1003 /* Get the controller status */ 1004 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 1005 1006 /* Tx interrupt ? */ 1007 if (status & SEEQ_STATUS_TX_INT) { 1008 handled = 1; 1009 1010 /* Acknowledge the interrupt */ 1011 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1012 sc->sc_command | SEEQ_CMD_TX_INTACK); 1013 1014 ea_txint(sc); 1015 } 1016 1017 1018 /* Rx interrupt ? */ 1019 if (status & SEEQ_STATUS_RX_INT) { 1020 handled = 1; 1021 1022 /* Acknowledge the interrupt */ 1023 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1024 sc->sc_command | SEEQ_CMD_RX_INTACK); 1025 1026 /* Processes the received packets */ 1027 ea_rxint(sc); 1028 } 1029 1030 if (handled) 1031 rnd_add_uint32(&sc->rnd_source, status); 1032 1033 return handled; 1034 } 1035 1036 static void 1037 ea_txint(struct seeq8005_softc *sc) 1038 { 1039 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1040 bus_space_tag_t iot = sc->sc_iot; 1041 bus_space_handle_t ioh = sc->sc_ioh; 1042 u_int8_t txhdr[4]; 1043 u_int txstatus; 1044 1045 ea_readbuf(sc, txhdr, 0x0000, 4); 1046 1047 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1048 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1049 txstatus = txhdr[3]; 1050 1051 /* 1052 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1053 * one collision. On the 8004 we can find out exactly how many 1054 * collisions occurred. 1055 * 1056 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1057 * completed. 1058 * 1059 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1060 * occurred and the packet transmission was aborted. 1061 * This situation is untested as present. 1062 * 1063 * The SEEQ_TXSTAT_BABBLE is untested as it should only be set 1064 * when we deliberately transmit oversized packets (e.g. for 1065 * 802.1Q). 1066 */ 1067 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1068 switch (sc->sc_variant) { 1069 case SEEQ_8004: { 1070 int colls; 1071 1072 /* 1073 * The 8004 contains a 4 bit collision count 1074 * in the status register. 1075 */ 1076 1077 /* This appears to be broken on 80C04.AE */ 1078 /* ifp->if_collisions += 1079 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1080 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1081 1082 /* Use the TX Collision register */ 1083 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1084 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1085 ifp->if_collisions += colls; 1086 break; 1087 } 1088 case SEEQ_8005: 1089 /* We known there was at least 1 collision */ 1090 ifp->if_collisions++; 1091 break; 1092 } 1093 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1094 printf("seeq_intr: col16 %x\n", txstatus); 1095 ifp->if_collisions += 16; 1096 ifp->if_oerrors++; 1097 } 1098 1099 /* Have we completed transmission on the packet ? */ 1100 if (txstatus & SEEQ_PKTSTAT_DONE) { 1101 /* Clear watchdog timer. */ 1102 ifp->if_timer = 0; 1103 ifp->if_flags &= ~IFF_OACTIVE; 1104 1105 /* Update stats */ 1106 ifp->if_opackets++; 1107 1108 /* Tx next packet */ 1109 1110 eatxpacket(sc); 1111 } 1112 } 1113 1114 void 1115 ea_rxint(struct seeq8005_softc *sc) 1116 { 1117 bus_space_tag_t iot = sc->sc_iot; 1118 bus_space_handle_t ioh = sc->sc_ioh; 1119 u_int addr; 1120 int len; 1121 int ctrl; 1122 int ptr; 1123 int status; 1124 u_int8_t rxhdr[4]; 1125 struct ifnet *ifp; 1126 1127 ifp = &sc->sc_ethercom.ec_if; 1128 1129 1130 /* We start from the last rx pointer position */ 1131 addr = sc->sc_rx_ptr; 1132 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1133 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1134 1135 do { 1136 /* Read rx header */ 1137 ea_readbuf(sc, rxhdr, addr, 4); 1138 1139 /* Split the packet header */ 1140 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1141 ctrl = rxhdr[2]; 1142 status = rxhdr[3]; 1143 1144 DPRINTF(SEEQ_DEBUG_RX, 1145 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1146 addr, ptr, ctrl, status)); 1147 1148 /* Zero packet ptr ? then must be null header so exit */ 1149 if (ptr == 0) break; 1150 1151 /* Sanity-check the next-packet pointer and flags. */ 1152 if (__predict_false(ptr < sc->sc_tx_bufsize || 1153 (ctrl & SEEQ_PKTCMD_TX))) { 1154 ++ifp->if_ierrors; 1155 log(LOG_ERR, 1156 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1157 device_xname(&sc->sc_dev), addr, ptr); 1158 ea_init(ifp); 1159 return; 1160 } 1161 1162 /* Get packet length */ 1163 len = (ptr - addr) - 4; 1164 1165 if (len < 0) 1166 len += sc->sc_rx_bufsize; 1167 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1168 1169 /* Has the packet rx completed ? if not then exit */ 1170 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1171 break; 1172 1173 /* 1174 * Did we have any errors? then note error and go to 1175 * next packet 1176 */ 1177 if (__predict_false(status & 1178 (SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR | 1179 SEEQ_RXSTAT_SHORT_FRAME))) { 1180 ++ifp->if_ierrors; 1181 log(LOG_WARNING, 1182 "%s: rx packet error at %04x (err=%02x)\n", 1183 device_xname(&sc->sc_dev), addr, status & 0x0f); 1184 /* XXX shouldn't need to reset if it's genuine. */ 1185 ea_init(ifp); 1186 return; 1187 } 1188 /* 1189 * Is the packet too big? We allow slightly oversize packets 1190 * for vlan(4) and tcpdump purposes, but the rest of the world 1191 * wants incoming packets in a single mbuf cluster. 1192 */ 1193 if (__predict_false(len > MCLBYTES)) { 1194 ++ifp->if_ierrors; 1195 log(LOG_ERR, 1196 "%s: rx packet size error at %04x (len=%d)\n", 1197 device_xname(&sc->sc_dev), addr, len); 1198 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1199 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, 1200 sc->sc_config2); 1201 ea_init(ifp); 1202 return; 1203 } 1204 1205 ifp->if_ipackets++; 1206 /* Pass data up to upper levels. */ 1207 ea_read(sc, addr + 4, len); 1208 1209 addr = ptr; 1210 } while (len != 0); 1211 1212 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1213 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1214 1215 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1216 1217 /* Store new rx pointer */ 1218 sc->sc_rx_ptr = addr; 1219 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1220 1221 /* Make sure the receiver is on */ 1222 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1223 sc->sc_command | SEEQ_CMD_RX_ON); 1224 } 1225 1226 1227 /* 1228 * Pass a packet up to the higher levels. 1229 */ 1230 1231 static void 1232 ea_read(struct seeq8005_softc *sc, int addr, int len) 1233 { 1234 struct mbuf *m; 1235 struct ifnet *ifp; 1236 1237 ifp = &sc->sc_ethercom.ec_if; 1238 1239 /* Pull packet off interface. */ 1240 m = ea_get(sc, addr, len, ifp); 1241 if (m == 0) 1242 return; 1243 1244 /* 1245 * Check if there's a BPF listener on this interface. 1246 * If so, hand off the raw packet to bpf. 1247 */ 1248 bpf_mtap(ifp, m); 1249 1250 (*ifp->if_input)(ifp, m); 1251 } 1252 1253 /* 1254 * Pull read data off a interface. Len is length of data, with local net 1255 * header stripped. We copy the data into mbufs. When full cluster sized 1256 * units are present we copy into clusters. 1257 */ 1258 1259 struct mbuf * 1260 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1261 { 1262 struct mbuf *top, **mp, *m; 1263 int len; 1264 u_int cp, epkt; 1265 1266 cp = addr; 1267 epkt = cp + totlen; 1268 1269 MGETHDR(m, M_DONTWAIT, MT_DATA); 1270 if (m == 0) 1271 return 0; 1272 m->m_pkthdr.rcvif = ifp; 1273 m->m_pkthdr.len = totlen; 1274 m->m_len = MHLEN; 1275 top = 0; 1276 mp = ⊤ 1277 1278 while (totlen > 0) { 1279 if (top) { 1280 MGET(m, M_DONTWAIT, MT_DATA); 1281 if (m == 0) { 1282 m_freem(top); 1283 return 0; 1284 } 1285 m->m_len = MLEN; 1286 } 1287 len = min(totlen, epkt - cp); 1288 if (len >= MINCLSIZE) { 1289 MCLGET(m, M_DONTWAIT); 1290 if (m->m_flags & M_EXT) 1291 m->m_len = len = min(len, MCLBYTES); 1292 else 1293 len = m->m_len; 1294 } else { 1295 /* 1296 * Place initial small packet/header at end of mbuf. 1297 */ 1298 if (len < m->m_len) { 1299 if (top == 0 && len + max_linkhdr <= m->m_len) 1300 m->m_data += max_linkhdr; 1301 m->m_len = len; 1302 } else 1303 len = m->m_len; 1304 } 1305 if (top == 0) { 1306 /* Make sure the payload is aligned */ 1307 char *newdata = (char *) 1308 ALIGN((char*)m->m_data + 1309 sizeof(struct ether_header)) - 1310 sizeof(struct ether_header); 1311 len -= newdata - m->m_data; 1312 m->m_len = len; 1313 m->m_data = newdata; 1314 } 1315 ea_readbuf(sc, mtod(m, u_char *), 1316 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1317 len); 1318 cp += len; 1319 *mp = m; 1320 mp = &m->m_next; 1321 totlen -= len; 1322 if (cp == epkt) 1323 cp = addr; 1324 } 1325 1326 return top; 1327 } 1328 1329 /* 1330 * Process an ioctl request. Mostly boilerplate. 1331 */ 1332 static int 1333 ea_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1334 { 1335 struct seeq8005_softc *sc = ifp->if_softc; 1336 int s, error = 0; 1337 1338 s = splnet(); 1339 switch (cmd) { 1340 1341 default: 1342 error = ether_ioctl(ifp, cmd, data); 1343 if (error == ENETRESET) { 1344 /* 1345 * Multicast list has changed; set the hardware filter 1346 * accordingly. 1347 */ 1348 if (ifp->if_flags & IFF_RUNNING) 1349 ea_mc_reset(sc); 1350 error = 0; 1351 } 1352 break; 1353 } 1354 1355 splx(s); 1356 return error; 1357 } 1358 1359 /* Must be called at splnet() */ 1360 1361 static void 1362 ea_mc_reset(struct seeq8005_softc *sc) 1363 { 1364 1365 switch (sc->sc_variant) { 1366 case SEEQ_8004: 1367 ea_mc_reset_8004(sc); 1368 return; 1369 case SEEQ_8005: 1370 ea_mc_reset_8005(sc); 1371 return; 1372 } 1373 } 1374 1375 static void 1376 ea_mc_reset_8004(struct seeq8005_softc *sc) 1377 { 1378 struct ethercom *ec = &sc->sc_ethercom; 1379 struct ifnet *ifp = &ec->ec_if; 1380 struct ether_multi *enm; 1381 u_int32_t crc; 1382 int i; 1383 struct ether_multistep step; 1384 u_int8_t af[8]; 1385 1386 /* 1387 * Set up multicast address filter by passing all multicast addresses 1388 * through a crc generator, and then using bits 2 - 7 as an index 1389 * into the 64 bit logical address filter. The high order bits 1390 * selects the word, while the rest of the bits select the bit within 1391 * the word. 1392 */ 1393 1394 if (ifp->if_flags & IFF_PROMISC) { 1395 ifp->if_flags |= IFF_ALLMULTI; 1396 for (i = 0; i < 8; i++) 1397 af[i] = 0xff; 1398 return; 1399 } 1400 for (i = 0; i < 8; i++) 1401 af[i] = 0; 1402 ETHER_FIRST_MULTI(step, ec, enm); 1403 while (enm != NULL) { 1404 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1405 sizeof(enm->enm_addrlo)) != 0) { 1406 /* 1407 * We must listen to a range of multicast addresses. 1408 * For now, just accept all multicasts, rather than 1409 * trying to set only those filter bits needed to match 1410 * the range. (At this time, the only use of address 1411 * ranges is for IP multicast routing, for which the 1412 * range is big enough to require all bits set.) 1413 */ 1414 ifp->if_flags |= IFF_ALLMULTI; 1415 for (i = 0; i < 8; i++) 1416 af[i] = 0xff; 1417 break; 1418 } 1419 1420 crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1421 1422 /* Just want the 6 most significant bits. */ 1423 crc = (crc >> 2) & 0x3f; 1424 1425 /* Turn on the corresponding bit in the filter. */ 1426 af[crc >> 3] |= 1 << (crc & 0x7); 1427 1428 ETHER_NEXT_MULTI(step, enm); 1429 } 1430 ifp->if_flags &= ~IFF_ALLMULTI; 1431 1432 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1433 for (i = 0; i < 8; ++i) 1434 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1435 SEEQ_BUFWIN, af[i]); 1436 } 1437 1438 static void 1439 ea_mc_reset_8005(struct seeq8005_softc *sc) 1440 { 1441 struct ether_multi *enm; 1442 struct ether_multistep step; 1443 int naddr, maxaddrs; 1444 1445 naddr = 0; 1446 maxaddrs = 5; 1447 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1448 while (enm != NULL) { 1449 /* Have we got space? */ 1450 if (naddr >= maxaddrs || 1451 memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1452 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1453 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1454 return; 1455 } 1456 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1457 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1458 naddr++; 1459 ETHER_NEXT_MULTI(step, enm); 1460 } 1461 for (; naddr < maxaddrs; naddr++) 1462 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1463 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1464 sc->sc_config1); 1465 } 1466 1467 /* 1468 * Device timeout routine. 1469 */ 1470 1471 static void 1472 ea_watchdog(struct ifnet *ifp) 1473 { 1474 struct seeq8005_softc *sc = ifp->if_softc; 1475 1476 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1477 device_xname(&sc->sc_dev), 1478 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1479 ifp->if_oerrors++; 1480 1481 /* Kick the interface */ 1482 1483 ea_init(ifp); 1484 1485 ifp->if_timer = 0; 1486 } 1487 1488 /* End of if_ea.c */ 1489
Indexes created Tue Sep 30 20:09:53 GMT 2025