seeq8005.c revision 1.6.2.3
1 /* $NetBSD: seeq8005.c,v 1.6.2.3 2000/11/22 16:03:30 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * seeq8005.c - SEEQ 8005 device driver 37 */ 38 /* 39 * This driver currently supports the following chip: 40 * SEEQ 8005 Advanced Ethernet Data Link Controller 41 */ 42 /* 43 * This driver is based on the arm32 ea(4) driver, hence the names of many 44 * of the functions. 45 */ 46 /* 47 * Bugs/possible improvements: 48 * - Does not currently support DMA 49 * - Does not currently support multicasts 50 * - Does not transmit multiple packets in one go 51 * - Does not support big-endian hosts 52 * - Does not support 8-bit busses 53 */ 54 55 #include "opt_inet.h" 56 #include "opt_ns.h" 57 58 #include <sys/types.h> 59 #include <sys/param.h> 60 61 __RCSID("$NetBSD: seeq8005.c,v 1.6.2.3 2000/11/22 16:03:30 bouyer Exp $"); 62 63 #include <sys/systm.h> 64 #include <sys/endian.h> 65 #include <sys/errno.h> 66 #include <sys/ioctl.h> 67 #include <sys/mbuf.h> 68 #include <sys/socket.h> 69 #include <sys/syslog.h> 70 #include <sys/device.h> 71 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_types.h> 75 #include <net/if_ether.h> 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/in_systm.h> 80 #include <netinet/in_var.h> 81 #include <netinet/ip.h> 82 #include <netinet/if_inarp.h> 83 #endif 84 85 #ifdef NS 86 #include <netns/ns.h> 87 #include <netns/ns_if.h> 88 #endif 89 90 #include "bpfilter.h" 91 #if NBPFILTER > 0 92 #include <net/bpf.h> 93 #include <net/bpfdesc.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/ic/seeq8005reg.h> 100 #include <dev/ic/seeq8005var.h> 101 102 #ifndef EA_TIMEOUT 103 #define EA_TIMEOUT 60 104 #endif 105 106 #define EA_TX_BUFFER_SIZE 0x4000 107 #define EA_RX_BUFFER_SIZE 0xC000 108 109 /*#define EA_TX_DEBUG*/ 110 /*#define EA_RX_DEBUG*/ 111 /*#define EA_DEBUG*/ 112 /*#define EA_PACKET_DEBUG*/ 113 114 /* for debugging convenience */ 115 #ifdef EA_DEBUG 116 #define dprintf(x) printf x 117 #else 118 #define dprintf(x) 119 #endif 120 121 /* 122 * prototypes 123 */ 124 125 static int ea_init(struct ifnet *); 126 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 127 static void ea_start(struct ifnet *); 128 static void ea_watchdog(struct ifnet *); 129 static void ea_chipreset(struct seeq8005_softc *); 130 static void ea_ramtest(struct seeq8005_softc *); 131 static int ea_stoptx(struct seeq8005_softc *); 132 static int ea_stoprx(struct seeq8005_softc *); 133 static void ea_stop(struct ifnet *, int); 134 static void ea_await_fifo_empty(struct seeq8005_softc *); 135 static void ea_await_fifo_full(struct seeq8005_softc *); 136 static void ea_writebuf(struct seeq8005_softc *, u_char *, u_int, size_t); 137 static void ea_readbuf(struct seeq8005_softc *, u_char *, u_int, size_t); 138 static void ea_select_buffer(struct seeq8005_softc *, int); 139 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 140 static void earead(struct seeq8005_softc *, int, int); 141 static struct mbuf *eaget(struct seeq8005_softc *, int, int, struct ifnet *); 142 static void eagetpackets(struct seeq8005_softc *); 143 static void eatxpacket(struct seeq8005_softc *); 144 static void ea_mc_reset(struct seeq8005_softc *); 145 146 147 #ifdef EA_PACKET_DEBUG 148 void ea_dump_buffer(struct seeq8005_softc *, int); 149 #endif 150 151 152 #ifdef EA_PACKET_DEBUG 153 /* 154 * Dump the interface buffer 155 */ 156 157 void 158 ea_dump_buffer(struct seeq8005_softc *sc, u_int offset) 159 { 160 bus_space_tag_t iot = sc->sc_iot; 161 bus_space_handle_t ioh = sc->sc_ioh; 162 u_int addr; 163 int loop, ctrl, ptr; 164 size_t size; 165 166 addr = offset; 167 168 do { 169 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 170 sc->sc_command | EA_CMD_FIFO_READ); 171 bus_space_write_2(iot, ioh, EA_8005_CONFIG1, 172 sc->sc_config1 | EA_BUFCODE_LOCAL_MEM); 173 bus_space_write_2(iot, ioh, EA_8005_DMA_ADDR, addr); 174 175 ptr = bus_space_read_2(iot, ioh, EA_8005_BUFWIN); 176 ctrl = bus_space_read_2(iot, ioh, EA_8005_BUFWIN); 177 ptr = ((ptr & 0xff) << 8) | ((ptr >> 8) & 0xff); 178 179 if (ptr == 0) break; 180 size = ptr - addr; 181 182 printf("addr=%04x size=%04x ", addr, size); 183 printf("cmd=%02x st=%02x\n", ctrl & 0xff, ctrl >> 8); 184 185 for (loop = 0; loop < size - 4; loop += 2) 186 printf("%04x ", 187 bus_space_read_2(iot, ioh, EA_8005_BUFWIN)); 188 printf("\n"); 189 addr = ptr; 190 } while (size != 0); 191 } 192 #endif 193 194 /* 195 * Attach chip. 196 */ 197 198 void 199 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr) 200 { 201 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 202 u_int id; 203 204 printf(" address %s", ether_sprintf(myaddr)); 205 206 /* Stop the board. */ 207 208 ea_chipreset(sc); 209 210 /* Get the product ID */ 211 212 ea_select_buffer(sc, EA_BUFCODE_PRODUCTID); 213 id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EA_8005_BUFWIN); 214 215 if ((id & 0xf0) == 0xa0) { 216 sc->sc_flags |= SEEQ8005_80C04; 217 printf(", SEEQ 80C04 rev %02x", id); 218 } else 219 printf(", SEEQ 8005"); 220 221 /* Initialise ifnet structure. */ 222 223 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 224 ifp->if_softc = sc; 225 ifp->if_start = ea_start; 226 ifp->if_ioctl = ea_ioctl; 227 ifp->if_init = ea_init; 228 ifp->if_stop = ea_stop; 229 ifp->if_watchdog = ea_watchdog; 230 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 231 232 /* Now we can attach the interface. */ 233 234 if_attach(ifp); 235 ether_ifattach(ifp, myaddr); 236 237 printf("\n"); 238 239 /* Test the RAM */ 240 ea_ramtest(sc); 241 } 242 243 244 /* 245 * Test the RAM on the ethernet card. 246 */ 247 248 void 249 ea_ramtest(struct seeq8005_softc *sc) 250 { 251 bus_space_tag_t iot = sc->sc_iot; 252 bus_space_handle_t ioh = sc->sc_ioh; 253 int loop; 254 u_int sum = 0; 255 256 /* dprintf(("ea_ramtest()\n"));*/ 257 258 /* 259 * Test the buffer memory on the board. 260 * Write simple pattens to it and read them back. 261 */ 262 263 /* Set up the whole buffer RAM for writing */ 264 265 ea_select_buffer(sc, EA_BUFCODE_TX_EAP); 266 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, (EA_BUFFER_SIZE >> 8) - 1); 267 bus_space_write_2(iot, ioh, EA_8005_TX_PTR, 0x0000); 268 bus_space_write_2(iot, ioh, EA_8005_RX_PTR, EA_BUFFER_SIZE - 2); 269 270 #define EA_RAMTEST_LOOP(value) \ 271 do { \ 272 /* Set the write start address and write a pattern */ \ 273 ea_writebuf(sc, NULL, 0x0000, 0); \ 274 for (loop = 0; loop < EA_BUFFER_SIZE; loop += 2) \ 275 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, (value)); \ 276 \ 277 /* Set the read start address and verify the pattern */ \ 278 ea_readbuf(sc, NULL, 0x0000, 0); \ 279 for (loop = 0; loop < EA_BUFFER_SIZE; loop += 2) \ 280 if (bus_space_read_2(iot, ioh, EA_8005_BUFWIN) != (value)) \ 281 ++sum; \ 282 if (sum != 0) \ 283 dprintf(("sum=%d\n", sum)); \ 284 } while (/*CONSTCOND*/0) 285 286 EA_RAMTEST_LOOP(loop); 287 EA_RAMTEST_LOOP(loop ^ (EA_BUFFER_SIZE - 1)); 288 EA_RAMTEST_LOOP(0xaa55); 289 EA_RAMTEST_LOOP(0x55aa); 290 291 /* Report */ 292 293 if (sum > 0) 294 printf("%s: buffer RAM failed self test, %d faults\n", 295 sc->sc_dev.dv_xname, sum); 296 } 297 298 299 /* 300 * Stop the tx interface. 301 * 302 * Returns 0 if the tx was already stopped or 1 if it was active 303 */ 304 305 static int 306 ea_stoptx(struct seeq8005_softc *sc) 307 { 308 bus_space_tag_t iot = sc->sc_iot; 309 bus_space_handle_t ioh = sc->sc_ioh; 310 int timeout; 311 int status; 312 313 dprintf(("ea_stoptx()\n")); 314 315 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 316 if (!(status & EA_STATUS_TX_ON)) 317 return 0; 318 319 /* Stop any tx and wait for confirmation */ 320 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 321 sc->sc_command | EA_CMD_TX_OFF); 322 323 timeout = 20000; 324 do { 325 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 326 } while ((status & EA_STATUS_TX_ON) && --timeout > 0); 327 if (timeout == 0) 328 dprintf(("ea_stoptx: timeout waiting for tx termination\n")); 329 330 /* Clear any pending tx interrupt */ 331 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 332 sc->sc_command | EA_CMD_TX_INTACK); 333 return 1; 334 } 335 336 337 /* 338 * Stop the rx interface. 339 * 340 * Returns 0 if the tx was already stopped or 1 if it was active 341 */ 342 343 static int 344 ea_stoprx(struct seeq8005_softc *sc) 345 { 346 bus_space_tag_t iot = sc->sc_iot; 347 bus_space_handle_t ioh = sc->sc_ioh; 348 int timeout; 349 int status; 350 351 dprintf(("ea_stoprx()\n")); 352 353 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 354 if (!(status & EA_STATUS_RX_ON)) 355 return 0; 356 357 /* Stop any rx and wait for confirmation */ 358 359 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 360 sc->sc_command | EA_CMD_RX_OFF); 361 362 timeout = 20000; 363 do { 364 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 365 } while ((status & EA_STATUS_RX_ON) && --timeout > 0); 366 if (timeout == 0) 367 dprintf(("ea_stoprx: timeout waiting for rx termination\n")); 368 369 /* Clear any pending rx interrupt */ 370 371 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 372 sc->sc_command | EA_CMD_RX_INTACK); 373 return 1; 374 } 375 376 377 /* 378 * Stop interface. 379 * Stop all IO and shut the interface down 380 */ 381 382 static void 383 ea_stop(struct ifnet *ifp, int disable) 384 { 385 struct seeq8005_softc *sc = ifp->if_softc; 386 bus_space_tag_t iot = sc->sc_iot; 387 bus_space_handle_t ioh = sc->sc_ioh; 388 389 dprintf(("ea_stop()\n")); 390 391 /* Stop all IO */ 392 ea_stoptx(sc); 393 ea_stoprx(sc); 394 395 /* Disable rx and tx interrupts */ 396 sc->sc_command &= (EA_CMD_RX_INTEN | EA_CMD_TX_INTEN); 397 398 /* Clear any pending interrupts */ 399 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 400 sc->sc_command | EA_CMD_RX_INTACK | 401 EA_CMD_TX_INTACK | EA_CMD_DMA_INTACK | 402 EA_CMD_BW_INTACK); 403 dprintf(("st=%08x", bus_space_read_2(iot, ioh, EA_8005_STATUS))); 404 405 /* Cancel any watchdog timer */ 406 sc->sc_ethercom.ec_if.if_timer = 0; 407 } 408 409 410 /* 411 * Reset the chip 412 * Following this the software registers are reset 413 */ 414 415 static void 416 ea_chipreset(struct seeq8005_softc *sc) 417 { 418 bus_space_tag_t iot = sc->sc_iot; 419 bus_space_handle_t ioh = sc->sc_ioh; 420 421 dprintf(("ea_chipreset()\n")); 422 423 /* Reset the controller. Min of 4us delay here */ 424 425 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, EA_CFG2_RESET); 426 delay(4); 427 428 sc->sc_command = 0; 429 sc->sc_config1 = 0; 430 sc->sc_config2 = 0; 431 } 432 433 434 /* 435 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 436 * switching the FIFO from write to read. We also use it when changing 437 * the address for writes. 438 */ 439 static void 440 ea_await_fifo_empty(struct seeq8005_softc *sc) 441 { 442 bus_space_tag_t iot = sc->sc_iot; 443 bus_space_handle_t ioh = sc->sc_ioh; 444 int timeout; 445 446 timeout = 20000; 447 if ((bus_space_read_2(iot, ioh, EA_8005_STATUS) & 448 EA_STATUS_FIFO_DIR) != 0) 449 return; /* FIFO is reading anyway. */ 450 while ((bus_space_read_2(iot, ioh, EA_8005_STATUS) & 451 EA_STATUS_FIFO_EMPTY) == 0 && 452 --timeout > 0) 453 continue; 454 } 455 456 /* 457 * Wait for the DMA FIFO to fill before reading from it. 458 */ 459 static void 460 ea_await_fifo_full(struct seeq8005_softc *sc) 461 { 462 bus_space_tag_t iot = sc->sc_iot; 463 bus_space_handle_t ioh = sc->sc_ioh; 464 int timeout; 465 466 timeout = 20000; 467 while ((bus_space_read_2(iot, ioh, EA_8005_STATUS) & 468 EA_STATUS_FIFO_FULL) == 0 && 469 --timeout > 0) 470 continue; 471 } 472 473 /* 474 * write to the buffer memory on the interface 475 * 476 * The buffer address is set to ADDR. 477 * If len != 0 then data is copied from the address starting at buf 478 * to the interface buffer. 479 * BUF must be usable as a u_int16_t *. 480 * If LEN is odd, it must be safe to overwrite one extra byte. 481 */ 482 483 static void 484 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len) 485 { 486 bus_space_tag_t iot = sc->sc_iot; 487 bus_space_handle_t ioh = sc->sc_ioh; 488 489 dprintf(("writebuf: st=%04x\n", 490 bus_space_read_2(iot, ioh, EA_8005_STATUS))); 491 492 #ifdef DIAGNOSTIC 493 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 494 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 495 #endif 496 if (__predict_false(addr >= EA_BUFFER_SIZE)) 497 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 498 499 /* Assume that copying too much is safe. */ 500 if (len % 2 != 0) 501 len++; 502 503 ea_await_fifo_empty(sc); 504 505 ea_select_buffer(sc, EA_BUFCODE_LOCAL_MEM); 506 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 507 sc->sc_command | EA_CMD_FIFO_WRITE); 508 bus_space_write_2(iot, ioh, EA_8005_DMA_ADDR, addr); 509 510 if (len > 0) 511 bus_space_write_multi_2(iot, ioh, EA_8005_BUFWIN, 512 (u_int16_t *)buf, len / 2); 513 /* Leave FIFO to empty in the background */ 514 } 515 516 517 /* 518 * read from the buffer memory on the interface 519 * 520 * The buffer address is set to ADDR. 521 * If len != 0 then data is copied from the interface buffer to the 522 * address starting at buf. 523 * BUF must be usable as a u_int16_t *. 524 * If LEN is odd, it must be safe to overwrite one extra byte. 525 */ 526 527 static void 528 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len) 529 { 530 531 bus_space_tag_t iot = sc->sc_iot; 532 bus_space_handle_t ioh = sc->sc_ioh; 533 534 dprintf(("readbuf: st=%04x addr=%04x len=%d\n", 535 bus_space_read_2(iot, ioh, EA_8005_STATUS), addr, len)); 536 537 #ifdef DIAGNOSTIC 538 if (!ALIGNED_POINTER(buf, u_int16_t)) 539 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 540 #endif 541 if (addr >= EA_BUFFER_SIZE) 542 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 543 544 /* Assume that copying too much is safe. */ 545 if (len % 2 != 0) 546 len++; 547 548 ea_await_fifo_empty(sc); 549 550 ea_select_buffer(sc, EA_BUFCODE_LOCAL_MEM); 551 bus_space_write_2(iot, ioh, EA_8005_DMA_ADDR, addr); 552 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 553 sc->sc_command | EA_CMD_FIFO_READ); 554 555 ea_await_fifo_full(sc); 556 557 if (len > 0) 558 bus_space_read_multi_2(iot, ioh, EA_8005_BUFWIN, 559 (u_int16_t *)buf, len / 2); 560 } 561 562 static void 563 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 564 { 565 566 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EA_8005_CONFIG1, 567 sc->sc_config1 | bufcode); 568 } 569 570 /* Must be called at splnet */ 571 static void 572 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 573 { 574 int i; 575 576 ea_select_buffer(sc, EA_BUFCODE_STATION_ADDR0 + which); 577 for (i = 0; i < ETHER_ADDR_LEN; ++i) 578 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EA_8005_BUFWIN, 579 ea[i]); 580 } 581 582 /* 583 * Initialize interface. 584 * 585 * This should leave the interface in a state for packet reception and 586 * transmission. 587 */ 588 589 static int 590 ea_init(struct ifnet *ifp) 591 { 592 struct seeq8005_softc *sc = ifp->if_softc; 593 bus_space_tag_t iot = sc->sc_iot; 594 bus_space_handle_t ioh = sc->sc_ioh; 595 int s; 596 597 dprintf(("ea_init()\n")); 598 599 s = splnet(); 600 601 /* First, reset the board. */ 602 603 ea_chipreset(sc); 604 605 /* Set up defaults for the registers */ 606 607 sc->sc_command = 0x00; 608 sc->sc_config1 = 0x00; /* XXX DMA settings? */ 609 #if BYTE_ORDER == BIG_ENDIAN 610 sc->sc_config2 = EA_CFG2_BYTESWAP 611 #else 612 sc->sc_config2 = 0; 613 #endif 614 615 bus_space_write_2(iot, ioh, EA_8005_COMMAND, sc->sc_command); 616 bus_space_write_2(iot, ioh, EA_8005_CONFIG1, sc->sc_config1); 617 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 618 619 /* Split board memory into Rx and Tx. */ 620 ea_select_buffer(sc, EA_BUFCODE_TX_EAP); 621 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 622 (EA_TX_BUFFER_SIZE >> 8) - 1); 623 624 /* Write the station address - the receiver must be off */ 625 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 626 627 /* Configure rx. */ 628 dprintf(("Configuring rx...\n")); 629 if (ifp->if_flags & IFF_PROMISC) 630 sc->sc_config1 = EA_CFG1_PROMISCUOUS; 631 else 632 sc->sc_config1 = EA_CFG1_BROADCAST; 633 sc->sc_config1 |= EA_CFG1_STATION_ADDR0; 634 bus_space_write_2(iot, ioh, EA_8005_CONFIG1, sc->sc_config1); 635 636 /* Setup the Rx pointers */ 637 sc->sc_rx_ptr = EA_TX_BUFFER_SIZE; 638 639 bus_space_write_2(iot, ioh, EA_8005_RX_PTR, sc->sc_rx_ptr); 640 bus_space_write_2(iot, ioh, EA_8005_RX_END, sc->sc_rx_ptr >> 8); 641 642 643 /* Place a NULL header at the beginning of the receive area */ 644 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 645 646 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 647 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 648 649 650 /* Turn on Rx */ 651 sc->sc_command |= EA_CMD_RX_INTEN; 652 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 653 sc->sc_command | EA_CMD_RX_ON); 654 655 656 /* Configure TX. */ 657 dprintf(("Configuring tx...\n")); 658 659 bus_space_write_2(iot, ioh, EA_8005_TX_PTR, 0x0000); 660 661 sc->sc_config2 |= EA_CFG2_OUTPUT; 662 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 663 664 665 /* Place a NULL header at the beginning of the transmit area */ 666 ea_writebuf(sc, NULL, 0x0000, 0); 667 668 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 669 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 670 671 sc->sc_command |= EA_CMD_TX_INTEN; 672 bus_space_write_2(iot, ioh, EA_8005_COMMAND, sc->sc_command); 673 674 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 675 676 677 /* Set flags appropriately. */ 678 ifp->if_flags |= IFF_RUNNING; 679 ifp->if_flags &= ~IFF_OACTIVE; 680 681 dprintf(("init: st=%04x\n", 682 bus_space_read_2(iot, ioh, EA_8005_STATUS))); 683 684 685 /* And start output. */ 686 ea_start(ifp); 687 688 splx(s); 689 return 0; 690 } 691 692 693 /* 694 * Start output on interface. Get datagrams from the queue and output them, 695 * giving the receiver a chance between datagrams. Call only from splnet or 696 * interrupt level! 697 */ 698 699 static void 700 ea_start(struct ifnet *ifp) 701 { 702 struct seeq8005_softc *sc = ifp->if_softc; 703 int s; 704 705 s = splnet(); 706 #ifdef EA_TX_DEBUG 707 dprintf(("ea_start()...\n")); 708 #endif 709 710 /* Don't do anything if output is active. */ 711 712 if (ifp->if_flags & IFF_OACTIVE) 713 return; 714 715 /* Mark interface as output active */ 716 717 ifp->if_flags |= IFF_OACTIVE; 718 719 /* tx packets */ 720 721 eatxpacket(sc); 722 splx(s); 723 } 724 725 726 /* 727 * Transfer a packet to the interface buffer and start transmission 728 * 729 * Called at splnet() 730 */ 731 732 void 733 eatxpacket(struct seeq8005_softc *sc) 734 { 735 bus_space_tag_t iot = sc->sc_iot; 736 bus_space_handle_t ioh = sc->sc_ioh; 737 struct mbuf *m, *m0; 738 struct ifnet *ifp; 739 int len, nextpacket; 740 u_int8_t hdr[4]; 741 742 ifp = &sc->sc_ethercom.ec_if; 743 744 /* Dequeue the next packet. */ 745 IF_DEQUEUE(&ifp->if_snd, m0); 746 747 /* If there's nothing to send, return. */ 748 if (!m0) { 749 ifp->if_flags &= ~IFF_OACTIVE; 750 sc->sc_config2 |= EA_CFG2_OUTPUT; 751 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 752 #ifdef EA_TX_DEBUG 753 dprintf(("tx finished\n")); 754 #endif 755 return; 756 } 757 758 #if NBPFILTER > 0 759 /* Give the packet to the bpf, if any. */ 760 if (ifp->if_bpf) 761 bpf_mtap(ifp->if_bpf, m0); 762 #endif 763 764 #ifdef EA_TX_DEBUG 765 dprintf(("Tx new packet\n")); 766 #endif 767 768 sc->sc_config2 &= ~EA_CFG2_OUTPUT; 769 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 770 771 /* 772 * Copy the frame to the start of the transmit area on the card, 773 * leaving four bytes for the transmit header. 774 */ 775 len = 0; 776 for (m = m0; m; m = m->m_next) { 777 if (m->m_len == 0) 778 continue; 779 ea_writebuf(sc, mtod(m, caddr_t), 4 + len, m->m_len); 780 len += m->m_len; 781 } 782 m_freem(m0); 783 784 785 /* If packet size is odd round up to the next 16 bit boundry */ 786 if (len % 2) 787 ++len; 788 789 len = max(len, ETHER_MIN_LEN); 790 791 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN)) 792 log(LOG_WARNING, "%s: oversize packet = %d bytes\n", 793 sc->sc_dev.dv_xname, len); 794 795 #if 0 /*def EA_TX_DEBUG*/ 796 dprintf(("ea: xfr pkt length=%d...\n", len)); 797 798 dprintf(("%s-->", ether_sprintf(sc->sc_pktbuf+6))); 799 dprintf(("%s\n", ether_sprintf(sc->sc_pktbuf))); 800 #endif 801 802 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS)));*/ 803 804 /* Follow it with a NULL packet header */ 805 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 806 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 807 808 809 /* Write the packet header */ 810 811 nextpacket = len + 4; 812 hdr[0] = (nextpacket >> 8) & 0xff; 813 hdr[1] = nextpacket & 0xff; 814 hdr[2] = EA_PKTHDR_TX | EA_PKTHDR_DATA_FOLLOWS | 815 EA_TXHDR_XMIT_SUCCESS_INT | EA_TXHDR_COLLISION_INT; 816 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 817 ea_writebuf(sc, hdr, 0x0000, 4); 818 819 bus_space_write_2(iot, ioh, EA_8005_TX_PTR, 0x0000); 820 821 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS)));*/ 822 823 #ifdef EA_PACKET_DEBUG 824 ea_dump_buffer(sc, 0); 825 #endif 826 827 828 /* Now transmit the datagram. */ 829 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS)));*/ 830 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 831 sc->sc_command | EA_CMD_TX_ON); 832 #ifdef EA_TX_DEBUG 833 dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS))); 834 dprintf(("tx: queued\n")); 835 #endif 836 } 837 838 839 /* 840 * Ethernet controller interrupt. 841 */ 842 843 int 844 seeq8005intr(void *arg) 845 { 846 struct seeq8005_softc *sc = arg; 847 bus_space_tag_t iot = sc->sc_iot; 848 bus_space_handle_t ioh = sc->sc_ioh; 849 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 850 int status, s, handled; 851 u_int8_t txhdr[4]; 852 u_int txstatus; 853 854 handled = 0; 855 dprintf(("eaintr: ")); 856 857 858 /* Get the controller status */ 859 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 860 dprintf(("st=%04x ", status)); 861 862 863 /* Tx interrupt ? */ 864 if (status & EA_STATUS_TX_INT) { 865 dprintf(("txint ")); 866 handled = 1; 867 868 /* Acknowledge the interrupt */ 869 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 870 sc->sc_command | EA_CMD_TX_INTACK); 871 872 ea_readbuf(sc, txhdr, 0x0000, 4); 873 874 #ifdef EA_TX_DEBUG 875 dprintf(("txstatus=%02x %02x %02x %02x\n", 876 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 877 #endif 878 txstatus = txhdr[3]; 879 880 /* 881 * Did it succeed ? Did we collide ? 882 * 883 * The exact proceedure here is not clear. We should get 884 * an interrupt on a sucessfull tx or on a collision. 885 * The done flag is set after successfull tx or 16 collisions 886 * We should thus get a interrupt for each of collision 887 * and the done bit should not be set. However it does appear 888 * to be set at the same time as the collision bit ... 889 * 890 * So we will count collisions and output errors and will 891 * assume that if the done bit is set the packet was 892 * transmitted. Stats may be wrong if 16 collisions occur on 893 * a packet as the done flag should be set but the packet 894 * may not have been transmitted. so the output count might 895 * not require incrementing if the 16 collisions flags is 896 * set. I don;t know abou this until it happens. 897 */ 898 899 if (txstatus & EA_TXHDR_COLLISION) 900 ifp->if_collisions++; 901 else if (txstatus & EA_TXHDR_ERROR_MASK) 902 ifp->if_oerrors++; 903 904 #if 0 905 if (txstatus & EA_TXHDR_ERROR_MASK) 906 log(LOG_WARNING, "tx packet error =%02x\n", txstatus); 907 #endif 908 909 if (txstatus & EA_PKTHDR_DONE) { 910 ifp->if_opackets++; 911 912 /* Tx next packet */ 913 914 s = splnet(); 915 eatxpacket(sc); 916 splx(s); 917 } 918 } 919 920 921 /* Rx interrupt ? */ 922 if (status & EA_STATUS_RX_INT) { 923 dprintf(("rxint ")); 924 handled = 1; 925 926 /* Acknowledge the interrupt */ 927 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 928 sc->sc_command | EA_CMD_RX_INTACK); 929 930 /* Install a watchdog timer needed atm to fixed rx lockups */ 931 ifp->if_timer = EA_TIMEOUT; 932 933 /* Processes the received packets */ 934 eagetpackets(sc); 935 936 937 #if 0 938 /* Make sure the receiver is on */ 939 if ((status & EA_STATUS_RX_ON) == 0) { 940 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 941 sc->sc_command | EA_CMD_RX_ON); 942 printf("rxintr: rx is off st=%04x\n",status); 943 } 944 #endif 945 } 946 947 #ifdef EA_DEBUG 948 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 949 dprintf(("st=%04x\n", status)); 950 #endif 951 952 return handled; 953 } 954 955 956 void 957 eagetpackets(struct seeq8005_softc *sc) 958 { 959 bus_space_tag_t iot = sc->sc_iot; 960 bus_space_handle_t ioh = sc->sc_ioh; 961 u_int addr; 962 int len; 963 int ctrl; 964 int ptr; 965 int pack; 966 int status; 967 u_int8_t rxhdr[4]; 968 struct ifnet *ifp; 969 970 ifp = &sc->sc_ethercom.ec_if; 971 972 973 /* We start from the last rx pointer position */ 974 addr = sc->sc_rx_ptr; 975 sc->sc_config2 &= ~EA_CFG2_OUTPUT; 976 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 977 978 do { 979 /* Read rx header */ 980 ea_readbuf(sc, rxhdr, addr, 4); 981 982 /* Split the packet header */ 983 ptr = (rxhdr[0] << 8) | rxhdr[1]; 984 ctrl = rxhdr[2]; 985 status = rxhdr[3]; 986 987 #ifdef EA_RX_DEBUG 988 dprintf(("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 989 addr, ptr, ctrl, status)); 990 #endif 991 992 993 /* Zero packet ptr ? then must be null header so exit */ 994 if (ptr == 0) break; 995 996 997 /* Get packet length */ 998 len = (ptr - addr) - 4; 999 1000 if (len < 0) 1001 len += EA_RX_BUFFER_SIZE; 1002 1003 #ifdef EA_RX_DEBUG 1004 dprintf(("len=%04x\n", len)); 1005 #endif 1006 1007 1008 /* Has the packet rx completed ? if not then exit */ 1009 if ((status & EA_PKTHDR_DONE) == 0) 1010 break; 1011 1012 /* 1013 * Did we have any errors? then note error and go to 1014 * next packet 1015 */ 1016 if (__predict_false(status & 0x0f)) { 1017 ++ifp->if_ierrors; 1018 log(LOG_WARNING, 1019 "%s: rx packet error (%02x) - dropping packet\n", 1020 sc->sc_dev.dv_xname, status & 0x0f); 1021 sc->sc_config2 |= EA_CFG2_OUTPUT; 1022 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, 1023 sc->sc_config2); 1024 ea_init(ifp); 1025 return; 1026 } 1027 1028 /* 1029 * Is the packet too big ? - this will probably be trapped 1030 * above as a receive error 1031 */ 1032 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1033 ++ifp->if_ierrors; 1034 log(LOG_WARNING, "%s: rx packet size error len=%d\n", 1035 sc->sc_dev.dv_xname, len); 1036 sc->sc_config2 |= EA_CFG2_OUTPUT; 1037 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, 1038 sc->sc_config2); 1039 ea_init(ifp); 1040 return; 1041 } 1042 1043 ifp->if_ipackets++; 1044 /* Pass data up to upper levels. */ 1045 earead(sc, addr + 4, len); 1046 1047 addr = ptr; 1048 ++pack; 1049 } while (len != 0); 1050 1051 sc->sc_config2 |= EA_CFG2_OUTPUT; 1052 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 1053 1054 #ifdef EA_RX_DEBUG 1055 dprintf(("new rx ptr=%04x\n", addr)); 1056 #endif 1057 1058 1059 /* Store new rx pointer */ 1060 sc->sc_rx_ptr = addr; 1061 bus_space_write_2(iot, ioh, EA_8005_RX_END, sc->sc_rx_ptr >> 8); 1062 1063 /* Make sure the receiver is on */ 1064 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 1065 sc->sc_command | EA_CMD_RX_ON); 1066 1067 } 1068 1069 1070 /* 1071 * Pass a packet up to the higher levels. 1072 */ 1073 1074 static void 1075 earead(struct seeq8005_softc *sc, int addr, int len) 1076 { 1077 struct mbuf *m; 1078 struct ifnet *ifp; 1079 1080 ifp = &sc->sc_ethercom.ec_if; 1081 1082 /* Pull packet off interface. */ 1083 m = eaget(sc, addr, len, ifp); 1084 if (m == 0) 1085 return; 1086 1087 #ifdef EA_RX_DEBUG 1088 dprintf(("%s-->", ether_sprintf(eh->ether_shost))); 1089 dprintf(("%s\n", ether_sprintf(eh->ether_dhost))); 1090 #endif 1091 1092 #if NBPFILTER > 0 1093 /* 1094 * Check if there's a BPF listener on this interface. 1095 * If so, hand off the raw packet to bpf. 1096 */ 1097 if (ifp->if_bpf) 1098 bpf_mtap(ifp->if_bpf, m); 1099 #endif 1100 1101 (*ifp->if_input)(ifp, m); 1102 } 1103 1104 /* 1105 * Pull read data off a interface. Len is length of data, with local net 1106 * header stripped. We copy the data into mbufs. When full cluster sized 1107 * units are present we copy into clusters. 1108 */ 1109 1110 struct mbuf * 1111 eaget(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1112 { 1113 struct mbuf *top, **mp, *m; 1114 int len; 1115 u_int cp, epkt; 1116 1117 cp = addr; 1118 epkt = cp + totlen; 1119 1120 MGETHDR(m, M_DONTWAIT, MT_DATA); 1121 if (m == 0) 1122 return 0; 1123 m->m_pkthdr.rcvif = ifp; 1124 m->m_pkthdr.len = totlen; 1125 m->m_len = MHLEN; 1126 top = 0; 1127 mp = ⊤ 1128 1129 while (totlen > 0) { 1130 if (top) { 1131 MGET(m, M_DONTWAIT, MT_DATA); 1132 if (m == 0) { 1133 m_freem(top); 1134 return 0; 1135 } 1136 m->m_len = MLEN; 1137 } 1138 len = min(totlen, epkt - cp); 1139 if (len >= MINCLSIZE) { 1140 MCLGET(m, M_DONTWAIT); 1141 if (m->m_flags & M_EXT) 1142 m->m_len = len = min(len, MCLBYTES); 1143 else 1144 len = m->m_len; 1145 } else { 1146 /* 1147 * Place initial small packet/header at end of mbuf. 1148 */ 1149 if (len < m->m_len) { 1150 if (top == 0 && len + max_linkhdr <= m->m_len) 1151 m->m_data += max_linkhdr; 1152 m->m_len = len; 1153 } else 1154 len = m->m_len; 1155 } 1156 if (top == 0) { 1157 /* Make sure the payload is aligned */ 1158 caddr_t newdata = (caddr_t) 1159 ALIGN(m->m_data + sizeof(struct ether_header)) - 1160 sizeof(struct ether_header); 1161 len -= newdata - m->m_data; 1162 m->m_len = len; 1163 m->m_data = newdata; 1164 } 1165 ea_readbuf(sc, mtod(m, u_char *), 1166 cp < EA_BUFFER_SIZE ? cp : cp - EA_RX_BUFFER_SIZE, 1167 len); 1168 cp += len; 1169 *mp = m; 1170 mp = &m->m_next; 1171 totlen -= len; 1172 if (cp == epkt) 1173 cp = addr; 1174 } 1175 1176 return top; 1177 } 1178 1179 /* 1180 * Process an ioctl request. Mostly boilerplate. 1181 */ 1182 static int 1183 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1184 { 1185 struct seeq8005_softc *sc = ifp->if_softc; 1186 int s, error = 0; 1187 1188 s = splnet(); 1189 switch (cmd) { 1190 1191 default: 1192 error = ether_ioctl(ifp, cmd, data); 1193 if (error == ENETRESET) { 1194 /* 1195 * Multicast list has changed; set the hardware filter 1196 * accordingly. 1197 */ 1198 ea_mc_reset(sc); 1199 error = 0; 1200 } 1201 break; 1202 } 1203 1204 splx(s); 1205 return error; 1206 } 1207 1208 /* Must be called at splnet() */ 1209 static void 1210 ea_mc_reset(struct seeq8005_softc *sc) 1211 { 1212 struct ether_multi *enm; 1213 struct ether_multistep step; 1214 int naddr, maxaddrs; 1215 1216 naddr = 0; 1217 maxaddrs = (sc->sc_flags & SEEQ8005_80C04) ? 5 : 0; 1218 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1219 while (enm != NULL) { 1220 /* Have we got space? */ 1221 if (naddr >= maxaddrs || 1222 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1223 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1224 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1225 return; 1226 } 1227 ea_set_address(sc, naddr, enm->enm_addrlo); 1228 sc->sc_config1 |= EA_CFG1_STATION_ADDR0 << naddr; 1229 naddr++; 1230 ETHER_NEXT_MULTI(step, enm); 1231 } 1232 for (; naddr < maxaddrs; naddr++) 1233 sc->sc_config1 &= ~(EA_CFG1_STATION_ADDR0 << naddr); 1234 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EA_8005_CONFIG1, 1235 sc->sc_config1); 1236 } 1237 1238 /* 1239 * Device timeout routine. 1240 * 1241 * Ok I am not sure exactly how the device timeout should work.... 1242 * Currently what will happens is that that the device timeout is only 1243 * set when a packet it received. This indicates we are on an active 1244 * network and thus we should expect more packets. If non arrive in 1245 * in the timeout period then we reinitialise as we may have jammed. 1246 * We zero the timeout at this point so that we don't end up with 1247 * an endless stream of timeouts if the network goes down. 1248 */ 1249 1250 static void 1251 ea_watchdog(struct ifnet *ifp) 1252 { 1253 struct seeq8005_softc *sc = ifp->if_softc; 1254 1255 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1256 ifp->if_oerrors++; 1257 dprintf(("ea_watchdog: ")); 1258 dprintf(("st=%04x\n", 1259 bus_space_read_2(sc->sc_iot, sc->sc_ioh, EA_8005_STATUS))); 1260 1261 /* Kick the interface */ 1262 1263 ea_init(ifp); 1264 1265 /* ifp->if_timer = EA_TIMEOUT;*/ 1266 ifp->if_timer = 0; 1267 } 1268 1269 /* End of if_ea.c */ 1270
Indexes created Wed Oct 22 00:09:40 GMT 2025