seeq8005.c revision 1.61
1 /* $NetBSD: seeq8005.c,v 1.61 2019/02/05 06:17:02 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45 /* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52 /* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56 /* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: seeq8005.c,v 1.61 2019/02/05 06:17:02 msaitoh Exp $"); 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/endian.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 76 #include <net/if.h> 77 #include <net/if_dl.h> 78 #include <net/if_types.h> 79 #include <net/if_ether.h> 80 #include <net/if_media.h> 81 #include <net/bpf.h> 82 83 #include <sys/rndsource.h> 84 85 #include <sys/bus.h> 86 #include <sys/intr.h> 87 88 #include <dev/ic/seeq8005reg.h> 89 #include <dev/ic/seeq8005var.h> 90 91 /*#define SEEQ_DEBUG*/ 92 93 /* for debugging convenience */ 94 #ifdef SEEQ8005_DEBUG 95 #define SEEQ_DEBUG_MISC 1 96 #define SEEQ_DEBUG_TX 2 97 #define SEEQ_DEBUG_RX 4 98 #define SEEQ_DEBUG_PKT 8 99 #define SEEQ_DEBUG_TXINT 16 100 #define SEEQ_DEBUG_RXINT 32 101 int seeq8005_debug = 0; 102 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 103 #else 104 #define DPRINTF(f, x) 105 #endif 106 107 #ifndef EA_TX_BUFFER_SIZE 108 #define EA_TX_BUFFER_SIZE 0x800 /* (> ETHER_MAX_LEN) */ 109 #endif 110 #ifndef EA_TX_BUFFER_COUNT 111 #define EA_TX_BUFFER_COUNT 1 /* (> 0) */ 112 #endif 113 114 #define SEEQ_READ16(sc, iot, ioh, reg) \ 115 ((sc)->sc_flags & SF_8BIT ? \ 116 (bus_space_read_1((iot), (ioh), (reg)) | \ 117 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 118 (bus_space_read_2((iot), (ioh), (reg)))) 119 120 #define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 121 if ((sc)->sc_flags & SF_8BIT) { \ 122 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 123 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 124 } else \ 125 bus_space_write_2((iot), (ioh), (reg), (val)); \ 126 } while (/*CONSTCOND*/0) 127 128 /* 129 * prototypes 130 */ 131 132 static int ea_init(struct ifnet *); 133 static int ea_ioctl(struct ifnet *, u_long, void *); 134 static void ea_start(struct ifnet *); 135 static void ea_watchdog(struct ifnet *); 136 static void ea_chipreset(struct seeq8005_softc *); 137 static void ea_ramtest(struct seeq8005_softc *); 138 static int ea_stoptx(struct seeq8005_softc *); 139 static int ea_stoprx(struct seeq8005_softc *); 140 static void ea_stop(struct ifnet *, int); 141 static void ea_await_fifo_empty(struct seeq8005_softc *); 142 static void ea_await_fifo_full(struct seeq8005_softc *); 143 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 145 static void ea_select_buffer(struct seeq8005_softc *, int); 146 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 147 static void ea_read(struct seeq8005_softc *, int, int); 148 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 149 static void ea_txint(struct seeq8005_softc *); 150 static void ea_rxint(struct seeq8005_softc *); 151 static void ea_txpacket(struct seeq8005_softc *); 152 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 153 static void ea_mc_reset(struct seeq8005_softc *); 154 static void ea_mc_reset_8004(struct seeq8005_softc *); 155 static void ea_mc_reset_8005(struct seeq8005_softc *); 156 static int ea_mediachange(struct ifnet *); 157 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 158 159 static u_char* padbuf = NULL; 160 161 162 /* 163 * Attach chip. 164 */ 165 166 void 167 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 168 int nmedia, int defmedia) 169 { 170 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 171 bus_space_tag_t iot = sc->sc_iot; 172 bus_space_handle_t ioh = sc->sc_ioh; 173 u_int id; 174 175 KASSERT(myaddr != NULL); 176 printf(" address %s", ether_sprintf(myaddr)); 177 178 /* Stop the board. */ 179 180 ea_chipreset(sc); 181 182 /* Work out data bus width. */ 183 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 184 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 185 /* Try 8-bit mode */ 186 sc->sc_flags |= SF_8BIT; 187 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 188 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 189 aprint_normal("\n"); 190 aprint_error_dev(sc->sc_dev, "Cannot determine data bus width\n"); 191 return; 192 } 193 } 194 195 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 196 197 /* Get the product ID */ 198 199 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 200 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 201 202 switch (id & SEEQ_PRODUCTID_MASK) { 203 case SEEQ_PRODUCTID_8004: 204 sc->sc_variant = SEEQ_8004; 205 switch (id & SEEQ_PRODUCTID_REV_MASK) { 206 case SEEQ_PRODUCTID_REV_80C04: 207 printf(", SEEQ 80C04\n"); 208 break; 209 case SEEQ_PRODUCTID_REV_80C04A: 210 printf(", SEEQ 80C04A\n"); 211 break; 212 default: 213 /* Unknown SEEQ 8004 variants */ 214 printf(", SEEQ 8004 rev %x\n", 215 id & SEEQ_PRODUCTID_REV_MASK); 216 break; 217 } 218 break; 219 default: /* XXX */ 220 sc->sc_variant = SEEQ_8005; 221 printf(", SEEQ 8005\n"); 222 break; 223 } 224 225 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 226 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 227 228 /* 229 * Set up tx and rx buffers. 230 * 231 * We set aside EA_TX_BUFFER_SIZE * EA_TX_BUFFER_COUNT for TX 232 * buffers and the rest for RX buffers 233 */ 234 sc->sc_tx_bufs = EA_TX_BUFFER_COUNT; 235 sc->sc_tx_bufsize = sc->sc_tx_bufs * EA_TX_BUFFER_SIZE; 236 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 237 sc->sc_enabled = 0; 238 239 /* Test the RAM */ 240 ea_ramtest(sc); 241 242 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 243 device_xname(sc->sc_dev), sc->sc_buffersize >> 10, 244 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 245 246 if (padbuf == NULL) { 247 padbuf = malloc(ETHER_MIN_LEN - ETHER_CRC_LEN, M_DEVBUF, 248 M_ZERO | M_NOWAIT); 249 if (padbuf == NULL) { 250 aprint_error_dev(sc->sc_dev, "can't allocate pad buffer\n"); 251 return; 252 } 253 } 254 255 /* Initialise ifnet structure. */ 256 257 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 258 ifp->if_softc = sc; 259 ifp->if_start = ea_start; 260 ifp->if_ioctl = ea_ioctl; 261 ifp->if_init = ea_init; 262 ifp->if_stop = ea_stop; 263 ifp->if_watchdog = ea_watchdog; 264 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST; 265 if (sc->sc_variant == SEEQ_8004) 266 ifp->if_flags |= IFF_SIMPLEX; 267 IFQ_SET_READY(&ifp->if_snd); 268 269 /* Initialize media goo. */ 270 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 271 if (media != NULL) { 272 int i; 273 274 for (i = 0; i < nmedia; i++) 275 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 276 ifmedia_set(&sc->sc_media, defmedia); 277 } else { 278 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 279 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 280 } 281 282 /* We can support 802.1Q VLAN-sized frames. */ 283 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 284 285 /* Now we can attach the interface. */ 286 287 if_attach(ifp); 288 ether_ifattach(ifp, myaddr); 289 290 printf("\n"); 291 292 /* After \n because it can print a line of its own. */ 293 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 294 RND_TYPE_NET, RND_FLAG_DEFAULT); 295 } 296 297 /* 298 * Media change callback. 299 */ 300 static int 301 ea_mediachange(struct ifnet *ifp) 302 { 303 struct seeq8005_softc *sc = ifp->if_softc; 304 305 if (sc->sc_mediachange) 306 return ((*sc->sc_mediachange)(sc)); 307 return (EINVAL); 308 } 309 310 /* 311 * Media status callback. 312 */ 313 static void 314 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 315 { 316 struct seeq8005_softc *sc = ifp->if_softc; 317 318 if (sc->sc_enabled == 0) { 319 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 320 ifmr->ifm_status = 0; 321 return; 322 } 323 324 if (sc->sc_mediastatus) 325 (*sc->sc_mediastatus)(sc, ifmr); 326 } 327 328 /* 329 * Test the RAM on the ethernet card. 330 */ 331 332 void 333 ea_ramtest(struct seeq8005_softc *sc) 334 { 335 bus_space_tag_t iot = sc->sc_iot; 336 bus_space_handle_t ioh = sc->sc_ioh; 337 int loop; 338 u_int sum = 0; 339 340 /* 341 * Test the buffer memory on the board. 342 * Write simple pattens to it and read them back. 343 */ 344 345 /* Set up the whole buffer RAM for writing */ 346 347 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 348 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 349 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 350 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 351 352 #define SEEQ_RAMTEST_LOOP(value) \ 353 do { \ 354 /* Set the write start address and write a pattern */ \ 355 ea_writebuf(sc, NULL, 0x0000, 0); \ 356 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 357 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 358 \ 359 /* Set the read start address and verify the pattern */ \ 360 ea_readbuf(sc, NULL, 0x0000, 0); \ 361 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 362 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 363 ++sum; \ 364 } while (/*CONSTCOND*/0) 365 366 SEEQ_RAMTEST_LOOP(loop); 367 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 368 SEEQ_RAMTEST_LOOP(0xaa55); 369 SEEQ_RAMTEST_LOOP(0x55aa); 370 371 /* Report */ 372 373 if (sum > 0) 374 aprint_error_dev(sc->sc_dev, "buffer RAM failed self test, %d faults\n", sum); 375 } 376 377 378 /* 379 * Stop the tx interface. 380 * 381 * Returns 0 if the tx was already stopped or 1 if it was active 382 */ 383 384 static int 385 ea_stoptx(struct seeq8005_softc *sc) 386 { 387 bus_space_tag_t iot = sc->sc_iot; 388 bus_space_handle_t ioh = sc->sc_ioh; 389 int timeout; 390 int status; 391 392 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 393 394 sc->sc_enabled = 0; 395 396 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 397 if (!(status & SEEQ_STATUS_TX_ON)) 398 return 0; 399 400 /* Stop any tx and wait for confirmation */ 401 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 402 sc->sc_command | SEEQ_CMD_TX_OFF); 403 404 timeout = 20000; 405 do { 406 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 407 delay(1); 408 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 409 if (timeout == 0) 410 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 411 device_xname(sc->sc_dev)); 412 413 /* Clear any pending tx interrupt */ 414 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 415 sc->sc_command | SEEQ_CMD_TX_INTACK); 416 return 1; 417 } 418 419 420 /* 421 * Stop the rx interface. 422 * 423 * Returns 0 if the tx was already stopped or 1 if it was active 424 */ 425 426 static int 427 ea_stoprx(struct seeq8005_softc *sc) 428 { 429 bus_space_tag_t iot = sc->sc_iot; 430 bus_space_handle_t ioh = sc->sc_ioh; 431 int timeout; 432 int status; 433 434 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 435 436 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 437 if (!(status & SEEQ_STATUS_RX_ON)) 438 return 0; 439 440 /* Stop any rx and wait for confirmation */ 441 442 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 443 sc->sc_command | SEEQ_CMD_RX_OFF); 444 445 timeout = 20000; 446 do { 447 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 448 delay(1); 449 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 450 if (timeout == 0) 451 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 452 device_xname(sc->sc_dev)); 453 454 /* Clear any pending rx interrupt */ 455 456 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 457 sc->sc_command | SEEQ_CMD_RX_INTACK); 458 return 1; 459 } 460 461 462 /* 463 * Stop interface. 464 * Stop all IO and shut the interface down 465 */ 466 467 /* ARGSUSED */ 468 static void 469 ea_stop(struct ifnet *ifp, int disable) 470 { 471 struct seeq8005_softc *sc = ifp->if_softc; 472 bus_space_tag_t iot = sc->sc_iot; 473 bus_space_handle_t ioh = sc->sc_ioh; 474 475 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 476 477 /* Stop all IO */ 478 ea_stoptx(sc); 479 ea_stoprx(sc); 480 481 /* Disable rx and tx interrupts */ 482 sc->sc_command &= ~(SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 483 484 /* Clear any pending interrupts */ 485 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 486 sc->sc_command | SEEQ_CMD_RX_INTACK | 487 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 488 SEEQ_CMD_BW_INTACK); 489 490 if (sc->sc_variant == SEEQ_8004) { 491 /* Put the chip to sleep */ 492 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 493 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 494 sc->sc_config3 | SEEQ_CFG3_SLEEP); 495 } 496 497 /* Cancel any watchdog timer */ 498 sc->sc_ethercom.ec_if.if_timer = 0; 499 } 500 501 502 /* 503 * Reset the chip 504 * Following this the software registers are reset 505 */ 506 507 static void 508 ea_chipreset(struct seeq8005_softc *sc) 509 { 510 bus_space_tag_t iot = sc->sc_iot; 511 bus_space_handle_t ioh = sc->sc_ioh; 512 513 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 514 515 /* Reset the controller. Min of 4us delay here */ 516 517 /* 518 * This can be called before we know whether the chip is in 8- or 519 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 520 * harmless in 8-bit mode, so we do that second. 521 */ 522 523 /* In 16-bit mode, this will munge the PreamSelect bit. */ 524 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 525 delay(4); 526 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 527 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 528 delay(4); 529 530 sc->sc_command = 0; 531 sc->sc_config1 = 0; 532 sc->sc_config2 = 0; 533 sc->sc_config3 = 0; 534 } 535 536 537 /* 538 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 539 * switching the FIFO from write to read. We also use it when changing 540 * the address for writes. 541 */ 542 static void 543 ea_await_fifo_empty(struct seeq8005_softc *sc) 544 { 545 bus_space_tag_t iot = sc->sc_iot; 546 bus_space_handle_t ioh = sc->sc_ioh; 547 int timeout; 548 549 timeout = 20000; 550 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 551 SEEQ_STATUS_FIFO_DIR) != 0) 552 return; /* FIFO is reading anyway. */ 553 while (--timeout > 0) 554 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 555 SEEQ_STATUS_FIFO_EMPTY) 556 return; 557 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", device_xname(sc->sc_dev)); 558 } 559 560 /* 561 * Wait for the DMA FIFO to fill before reading from it. 562 */ 563 static void 564 ea_await_fifo_full(struct seeq8005_softc *sc) 565 { 566 bus_space_tag_t iot = sc->sc_iot; 567 bus_space_handle_t ioh = sc->sc_ioh; 568 int timeout; 569 570 timeout = 20000; 571 while (--timeout > 0) 572 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 573 SEEQ_STATUS_FIFO_FULL) 574 return; 575 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", device_xname(sc->sc_dev)); 576 } 577 578 /* 579 * write to the buffer memory on the interface 580 * 581 * The buffer address is set to ADDR. 582 * If len != 0 then data is copied from the address starting at buf 583 * to the interface buffer. 584 * BUF must be usable as a u_int16_t *. 585 * If LEN is odd, it must be safe to overwrite one extra byte. 586 */ 587 588 static void 589 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 590 { 591 bus_space_tag_t iot = sc->sc_iot; 592 bus_space_handle_t ioh = sc->sc_ioh; 593 594 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 595 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 596 597 #ifdef DIAGNOSTIC 598 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 599 panic("%s: unaligned writebuf", device_xname(sc->sc_dev)); 600 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 601 panic("%s: writebuf out of range", device_xname(sc->sc_dev)); 602 #endif 603 604 if (addr != -1) { 605 ea_await_fifo_empty(sc); 606 607 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 608 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 609 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 610 611 ea_await_fifo_empty(sc); 612 613 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 614 } 615 616 if (len > 0) { 617 if (sc->sc_flags & SF_8BIT) 618 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 619 (u_int8_t *)buf, len); 620 else 621 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 622 /* LINTED: alignment checked above */ 623 (u_int16_t *)buf, len / 2); 624 } 625 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 626 /* Write the last byte */ 627 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, buf[len - 1]); 628 } 629 /* Leave FIFO to empty in the background */ 630 } 631 632 633 /* 634 * read from the buffer memory on the interface 635 * 636 * The buffer address is set to ADDR. 637 * If len != 0 then data is copied from the interface buffer to the 638 * address starting at buf. 639 * BUF must be usable as a u_int16_t *. 640 * If LEN is odd, it must be safe to overwrite one extra byte. 641 */ 642 643 static void 644 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 645 { 646 bus_space_tag_t iot = sc->sc_iot; 647 bus_space_handle_t ioh = sc->sc_ioh; 648 int runup; 649 650 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 651 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 652 653 #ifdef DIAGNOSTIC 654 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 655 panic("%s: unaligned readbuf", device_xname(sc->sc_dev)); 656 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 657 panic("%s: readbuf out of range", device_xname(sc->sc_dev)); 658 #endif 659 660 if (addr != -1) { 661 /* 662 * SEEQ 80C04 bug: 663 * Starting reading from certain addresses seems to cause 664 * us to get bogus results, so we avoid them. 665 */ 666 runup = 0; 667 if (sc->sc_variant == SEEQ_8004 && 668 ((addr & 0x00ff) == 0x00ea || 669 (addr & 0x00ff) == 0x00ee || 670 (addr & 0x00ff) == 0x00f0)) 671 runup = (addr & 0x00ff) - 0x00e8; 672 673 ea_await_fifo_empty(sc); 674 675 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 676 677 /* 678 * 80C04 bug workaround. I found this in the old arm32 "eb" 679 * driver. I've no idea what it does, but it seems to stop 680 * the chip mangling data so often. 681 */ 682 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 683 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 684 ea_await_fifo_empty(sc); 685 686 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 687 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 688 sc->sc_command | SEEQ_CMD_FIFO_READ); 689 690 ea_await_fifo_full(sc); 691 while (runup > 0) { 692 /* LINTED: Reading a volatile _does_ have an effect */ 693 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 694 runup -= 2; 695 } 696 } 697 698 if (len > 0) { 699 if (sc->sc_flags & SF_8BIT) 700 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 701 (u_int8_t *)buf, len); 702 else 703 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 704 /* LINTED: pointer alignment checked above */ 705 (u_int16_t *)buf, len / 2); 706 } 707 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 708 /* Read the last byte */ 709 buf[len - 1] = bus_space_read_2(iot, ioh, SEEQ_BUFWIN); 710 } 711 } 712 713 static void 714 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 715 { 716 717 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 718 sc->sc_config1 | bufcode); 719 } 720 721 /* Must be called at splnet */ 722 static void 723 ea_set_address(struct seeq8005_softc *sc, int which, const u_int8_t *ea) 724 { 725 int i; 726 727 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 728 for (i = 0; i < ETHER_ADDR_LEN; ++i) 729 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 730 ea[i]); 731 } 732 733 /* 734 * Initialize interface. 735 * 736 * This should leave the interface in a state for packet reception and 737 * transmission. 738 */ 739 740 static int 741 ea_init(struct ifnet *ifp) 742 { 743 struct seeq8005_softc *sc = ifp->if_softc; 744 bus_space_tag_t iot = sc->sc_iot; 745 bus_space_handle_t ioh = sc->sc_ioh; 746 int s; 747 748 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 749 750 s = splnet(); 751 752 /* First, reset the board. */ 753 754 ea_chipreset(sc); 755 756 /* Set up defaults for the registers */ 757 758 sc->sc_command = 0; 759 sc->sc_config1 = 0; 760 #if BYTE_ORDER == BIG_ENDIAN 761 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 762 #else 763 sc->sc_config2 = 0; 764 #endif 765 sc->sc_config3 = 0; 766 767 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 768 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 769 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 770 if (sc->sc_variant == SEEQ_8004) { 771 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 772 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 773 } 774 775 /* Write the station address - the receiver must be off */ 776 ea_set_address(sc, 0, (const u_int8_t *)CLLADDR(ifp->if_sadl)); 777 778 /* Split board memory into Rx and Tx. */ 779 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 780 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 781 782 if (sc->sc_variant == SEEQ_8004) { 783 /* Make the interface IFF_SIMPLEX. */ 784 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 785 /* Enable reception of long packets (for vlan(4)). */ 786 sc->sc_config2 |= SEEQ_CFG2_PASS_LONGSHORT; 787 } 788 789 /* Configure rx. */ 790 ea_mc_reset(sc); 791 if (ifp->if_flags & IFF_PROMISC) 792 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 793 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 794 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 795 else 796 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 797 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 798 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 799 800 /* Setup the Rx pointers */ 801 sc->sc_rx_ptr = sc->sc_tx_bufsize; 802 803 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 804 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 805 806 807 /* Place a NULL header at the beginning of the receive area */ 808 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 809 810 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 811 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 812 813 814 /* Configure TX. */ 815 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 816 817 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 818 819 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 820 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 821 822 /* Reset tx buffer pointers */ 823 sc->sc_tx_cur = 0; 824 sc->sc_tx_used = 0; 825 sc->sc_tx_next = 0; 826 827 /* Place a NULL header at the beginning of the transmit area */ 828 ea_writebuf(sc, NULL, 0x0000, 0); 829 830 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 831 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 832 833 sc->sc_command |= SEEQ_CMD_TX_INTEN; 834 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 835 836 /* Turn on Rx */ 837 sc->sc_command |= SEEQ_CMD_RX_INTEN; 838 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 839 sc->sc_command | SEEQ_CMD_RX_ON); 840 841 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 842 843 844 /* Set flags appropriately. */ 845 ifp->if_flags |= IFF_RUNNING; 846 ifp->if_flags &= ~IFF_OACTIVE; 847 sc->sc_enabled = 1; 848 849 /* And start output. */ 850 ea_start(ifp); 851 852 splx(s); 853 return 0; 854 } 855 856 /* 857 * Start output on interface. Get datagrams from the queue and output them, 858 * giving the receiver a chance between datagrams. Call only from splnet or 859 * interrupt level! 860 */ 861 862 static void 863 ea_start(struct ifnet *ifp) 864 { 865 struct seeq8005_softc *sc = ifp->if_softc; 866 int s; 867 868 s = splnet(); 869 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 870 871 /* 872 * Don't do anything if output is active. seeq8005intr() will call 873 * us (actually ea_txpacket()) back when the card's ready for more 874 * frames. 875 */ 876 if (ifp->if_flags & IFF_OACTIVE) { 877 splx(s); 878 return; 879 } 880 881 /* Mark interface as output active */ 882 883 ifp->if_flags |= IFF_OACTIVE; 884 885 /* tx packets */ 886 887 ea_txpacket(sc); 888 splx(s); 889 } 890 891 892 /* 893 * Transfer a packet to the interface buffer and start transmission 894 * 895 * Called at splnet() 896 */ 897 898 static void 899 ea_txpacket(struct seeq8005_softc *sc) 900 { 901 bus_space_tag_t iot = sc->sc_iot; 902 bus_space_handle_t ioh = sc->sc_ioh; 903 struct mbuf *m0; 904 struct ifnet *ifp; 905 906 ifp = &sc->sc_ethercom.ec_if; 907 908 /* Dequeue the next packet. */ 909 IFQ_DEQUEUE(&ifp->if_snd, m0); 910 911 /* If there's nothing to send, return. */ 912 if (m0 == NULL) { 913 ifp->if_flags &= ~IFF_OACTIVE; 914 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 915 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 916 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 917 return; 918 } 919 920 /* Give the packet to the bpf, if any. */ 921 bpf_mtap(ifp, m0, BPF_D_OUT); 922 923 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 924 925 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 926 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 927 928 ea_writembuf(sc, m0, 0x0000); 929 m_freem(m0); 930 931 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 932 933 /* Now transmit the datagram. */ 934 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 935 sc->sc_command | SEEQ_CMD_TX_ON); 936 937 /* Make sure we notice if the chip goes silent on us. */ 938 ifp->if_timer = 5; 939 940 DPRINTF(SEEQ_DEBUG_TX, 941 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 942 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 943 } 944 945 /* 946 * Copy a packet from an mbuf to the transmit buffer on the card. 947 * 948 * Puts a valid Tx header at the start of the packet, and a null header at 949 * the end. 950 */ 951 static int 952 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 953 { 954 struct mbuf *m; 955 int len, nextpacket; 956 u_int8_t hdr[4]; 957 958 /* 959 * Copy the datagram to the packet buffer. 960 */ 961 len = 0; 962 for (m = m0; m; m = m->m_next) { 963 if (m->m_len == 0) 964 continue; 965 ea_writebuf(sc, mtod(m, u_char *), bufstart + 4 + len, 966 m->m_len); 967 len += m->m_len; 968 } 969 970 if (len < ETHER_MIN_LEN) { 971 ea_writebuf(sc, padbuf, bufstart + 4 + len, 972 ETHER_MIN_LEN - len); 973 len = ETHER_MIN_LEN; 974 } 975 976 /* Follow it with a NULL packet header */ 977 memset(hdr, 0, 4); 978 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 979 980 /* Ok we now have a packet len bytes long in our packet buffer */ 981 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 982 983 /* Write the packet header */ 984 nextpacket = bufstart + len + 4; 985 hdr[0] = (nextpacket >> 8) & 0xff; 986 hdr[1] = nextpacket & 0xff; 987 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 988 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 989 hdr[3] = 0; /* Status byte -- will be updated by hardware. */ 990 ea_writebuf(sc, hdr, bufstart, 4); 991 992 return len; 993 } 994 995 /* 996 * Ethernet controller interrupt. 997 */ 998 999 int 1000 seeq8005intr(void *arg) 1001 { 1002 struct seeq8005_softc *sc = arg; 1003 bus_space_tag_t iot = sc->sc_iot; 1004 bus_space_handle_t ioh = sc->sc_ioh; 1005 int status, handled; 1006 1007 handled = 0; 1008 1009 /* Get the controller status */ 1010 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 1011 1012 /* Tx interrupt ? */ 1013 if (status & SEEQ_STATUS_TX_INT) { 1014 handled = 1; 1015 1016 /* Acknowledge the interrupt */ 1017 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1018 sc->sc_command | SEEQ_CMD_TX_INTACK); 1019 1020 ea_txint(sc); 1021 } 1022 1023 1024 /* Rx interrupt ? */ 1025 if (status & SEEQ_STATUS_RX_INT) { 1026 handled = 1; 1027 1028 /* Acknowledge the interrupt */ 1029 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1030 sc->sc_command | SEEQ_CMD_RX_INTACK); 1031 1032 /* Processes the received packets */ 1033 ea_rxint(sc); 1034 } 1035 1036 if (handled) 1037 rnd_add_uint32(&sc->rnd_source, status); 1038 1039 return handled; 1040 } 1041 1042 static void 1043 ea_txint(struct seeq8005_softc *sc) 1044 { 1045 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1046 bus_space_tag_t iot = sc->sc_iot; 1047 bus_space_handle_t ioh = sc->sc_ioh; 1048 u_int8_t txhdr[4]; 1049 u_int txstatus; 1050 1051 ea_readbuf(sc, txhdr, 0x0000, 4); 1052 1053 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1054 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1055 txstatus = txhdr[3]; 1056 1057 /* 1058 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1059 * one collision. On the 8004 we can find out exactly how many 1060 * collisions occurred. 1061 * 1062 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1063 * completed. 1064 * 1065 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1066 * occurred and the packet transmission was aborted. 1067 * This situation is untested as present. 1068 * 1069 * The SEEQ_TXSTAT_BABBLE is untested as it should only be set 1070 * when we deliberately transmit oversized packets (e.g. for 1071 * 802.1Q). 1072 */ 1073 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1074 switch (sc->sc_variant) { 1075 case SEEQ_8004: { 1076 int colls; 1077 1078 /* 1079 * The 8004 contains a 4 bit collision count 1080 * in the status register. 1081 */ 1082 1083 /* This appears to be broken on 80C04.AE */ 1084 /* ifp->if_collisions += 1085 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1086 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1087 1088 /* Use the TX Collision register */ 1089 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1090 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1091 ifp->if_collisions += colls; 1092 break; 1093 } 1094 case SEEQ_8005: 1095 /* We known there was at least 1 collision */ 1096 ifp->if_collisions++; 1097 break; 1098 } 1099 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1100 printf("seeq_intr: col16 %x\n", txstatus); 1101 ifp->if_collisions += 16; 1102 ifp->if_oerrors++; 1103 } 1104 1105 /* Have we completed transmission on the packet ? */ 1106 if (txstatus & SEEQ_PKTSTAT_DONE) { 1107 /* Clear watchdog timer. */ 1108 ifp->if_timer = 0; 1109 ifp->if_flags &= ~IFF_OACTIVE; 1110 1111 /* Update stats */ 1112 ifp->if_opackets++; 1113 1114 /* Tx next packet */ 1115 1116 ea_txpacket(sc); 1117 } 1118 } 1119 1120 static void 1121 ea_rxint(struct seeq8005_softc *sc) 1122 { 1123 bus_space_tag_t iot = sc->sc_iot; 1124 bus_space_handle_t ioh = sc->sc_ioh; 1125 u_int addr; 1126 int len; 1127 int ctrl; 1128 int ptr; 1129 int status; 1130 u_int8_t rxhdr[4]; 1131 struct ifnet *ifp; 1132 1133 ifp = &sc->sc_ethercom.ec_if; 1134 1135 1136 /* We start from the last rx pointer position */ 1137 addr = sc->sc_rx_ptr; 1138 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1139 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1140 1141 do { 1142 /* Read rx header */ 1143 ea_readbuf(sc, rxhdr, addr, 4); 1144 1145 /* Split the packet header */ 1146 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1147 ctrl = rxhdr[2]; 1148 status = rxhdr[3]; 1149 1150 DPRINTF(SEEQ_DEBUG_RX, 1151 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1152 addr, ptr, ctrl, status)); 1153 1154 /* Zero packet ptr ? then must be null header so exit */ 1155 if (ptr == 0) break; 1156 1157 /* Sanity-check the next-packet pointer and flags. */ 1158 if (__predict_false(ptr < sc->sc_tx_bufsize || 1159 (ctrl & SEEQ_PKTCMD_TX))) { 1160 ++ifp->if_ierrors; 1161 log(LOG_ERR, 1162 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1163 device_xname(sc->sc_dev), addr, ptr); 1164 ea_init(ifp); 1165 return; 1166 } 1167 1168 /* Get packet length */ 1169 len = (ptr - addr) - 4; 1170 1171 if (len < 0) 1172 len += sc->sc_rx_bufsize; 1173 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1174 1175 /* Has the packet rx completed ? if not then exit */ 1176 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1177 break; 1178 1179 /* 1180 * Did we have any errors? then note error and go to 1181 * next packet 1182 */ 1183 if (__predict_false(status & 1184 (SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR | 1185 SEEQ_RXSTAT_SHORT_FRAME))) { 1186 ++ifp->if_ierrors; 1187 log(LOG_WARNING, 1188 "%s: rx packet error at %04x (err=%02x)\n", 1189 device_xname(sc->sc_dev), addr, status & 0x0f); 1190 /* XXX shouldn't need to reset if it's genuine. */ 1191 ea_init(ifp); 1192 return; 1193 } 1194 /* 1195 * Is the packet too big? We allow slightly oversize packets 1196 * for vlan(4) and tcpdump purposes, but the rest of the world 1197 * wants incoming packets in a single mbuf cluster. 1198 */ 1199 if (__predict_false(len > MCLBYTES)) { 1200 ++ifp->if_ierrors; 1201 log(LOG_ERR, 1202 "%s: rx packet size error at %04x (len=%d)\n", 1203 device_xname(sc->sc_dev), addr, len); 1204 ea_init(ifp); 1205 return; 1206 } 1207 1208 /* Pass data up to upper levels. */ 1209 ea_read(sc, addr + 4, len); 1210 1211 addr = ptr; 1212 } while (len != 0); 1213 1214 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1215 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1216 1217 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1218 1219 /* Store new rx pointer */ 1220 sc->sc_rx_ptr = addr; 1221 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1222 1223 /* Make sure the receiver is on */ 1224 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1225 sc->sc_command | SEEQ_CMD_RX_ON); 1226 } 1227 1228 1229 /* 1230 * Pass a packet up to the higher levels. 1231 */ 1232 1233 static void 1234 ea_read(struct seeq8005_softc *sc, int addr, int len) 1235 { 1236 struct mbuf *m; 1237 struct ifnet *ifp; 1238 1239 ifp = &sc->sc_ethercom.ec_if; 1240 1241 /* Pull packet off interface. */ 1242 m = ea_get(sc, addr, len, ifp); 1243 if (m == NULL) 1244 return; 1245 1246 if_percpuq_enqueue(ifp->if_percpuq, m); 1247 } 1248 1249 /* 1250 * Pull read data off a interface. Len is length of data, with local net 1251 * header stripped. We copy the data into mbufs. When full cluster sized 1252 * units are present we copy into clusters. 1253 */ 1254 1255 struct mbuf * 1256 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1257 { 1258 struct mbuf *top, **mp, *m; 1259 int len; 1260 u_int cp, epkt; 1261 1262 cp = addr; 1263 epkt = cp + totlen; 1264 1265 MGETHDR(m, M_DONTWAIT, MT_DATA); 1266 if (m == NULL) 1267 return NULL; 1268 m_set_rcvif(m, ifp); 1269 m->m_pkthdr.len = totlen; 1270 m->m_len = MHLEN; 1271 top = NULL; 1272 mp = ⊤ 1273 1274 while (totlen > 0) { 1275 if (top) { 1276 MGET(m, M_DONTWAIT, MT_DATA); 1277 if (m == NULL) { 1278 m_freem(top); 1279 return NULL; 1280 } 1281 m->m_len = MLEN; 1282 } 1283 len = uimin(totlen, epkt - cp); 1284 if (len >= MINCLSIZE) { 1285 MCLGET(m, M_DONTWAIT); 1286 if (m->m_flags & M_EXT) 1287 m->m_len = len = uimin(len, MCLBYTES); 1288 else 1289 len = m->m_len; 1290 } else { 1291 /* 1292 * Place initial small packet/header at end of mbuf. 1293 */ 1294 if (len < m->m_len) { 1295 if (top == NULL && len + max_linkhdr <= m->m_len) 1296 m->m_data += max_linkhdr; 1297 m->m_len = len; 1298 } else 1299 len = m->m_len; 1300 } 1301 if (top == NULL) { 1302 /* Make sure the payload is aligned */ 1303 char *newdata = (char *) 1304 ALIGN((char*)m->m_data + 1305 sizeof(struct ether_header)) - 1306 sizeof(struct ether_header); 1307 len -= newdata - m->m_data; 1308 m->m_len = len; 1309 m->m_data = newdata; 1310 } 1311 ea_readbuf(sc, mtod(m, u_char *), 1312 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1313 len); 1314 cp += len; 1315 *mp = m; 1316 mp = &m->m_next; 1317 totlen -= len; 1318 if (cp == epkt) 1319 cp = addr; 1320 } 1321 1322 return top; 1323 } 1324 1325 /* 1326 * Process an ioctl request. Mostly boilerplate. 1327 */ 1328 static int 1329 ea_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1330 { 1331 struct seeq8005_softc *sc = ifp->if_softc; 1332 int s, error = 0; 1333 1334 s = splnet(); 1335 switch (cmd) { 1336 1337 default: 1338 error = ether_ioctl(ifp, cmd, data); 1339 if (error == ENETRESET) { 1340 /* 1341 * Multicast list has changed; set the hardware filter 1342 * accordingly. 1343 */ 1344 if (ifp->if_flags & IFF_RUNNING) 1345 ea_mc_reset(sc); 1346 error = 0; 1347 } 1348 break; 1349 } 1350 1351 splx(s); 1352 return error; 1353 } 1354 1355 /* Must be called at splnet() */ 1356 1357 static void 1358 ea_mc_reset(struct seeq8005_softc *sc) 1359 { 1360 1361 switch (sc->sc_variant) { 1362 case SEEQ_8004: 1363 ea_mc_reset_8004(sc); 1364 return; 1365 case SEEQ_8005: 1366 ea_mc_reset_8005(sc); 1367 return; 1368 } 1369 } 1370 1371 static void 1372 ea_mc_reset_8004(struct seeq8005_softc *sc) 1373 { 1374 struct ethercom *ec = &sc->sc_ethercom; 1375 struct ifnet *ifp = &ec->ec_if; 1376 struct ether_multi *enm; 1377 u_int32_t crc; 1378 int i; 1379 struct ether_multistep step; 1380 u_int8_t af[8]; 1381 1382 /* 1383 * Set up multicast address filter by passing all multicast addresses 1384 * through a crc generator, and then using bits 2 - 7 as an index 1385 * into the 64 bit logical address filter. The high order bits 1386 * selects the word, while the rest of the bits select the bit within 1387 * the word. 1388 */ 1389 1390 if (ifp->if_flags & IFF_PROMISC) { 1391 ifp->if_flags |= IFF_ALLMULTI; 1392 for (i = 0; i < 8; i++) 1393 af[i] = 0xff; 1394 return; 1395 } 1396 for (i = 0; i < 8; i++) 1397 af[i] = 0; 1398 ETHER_FIRST_MULTI(step, ec, enm); 1399 while (enm != NULL) { 1400 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1401 sizeof(enm->enm_addrlo)) != 0) { 1402 /* 1403 * We must listen to a range of multicast addresses. 1404 * For now, just accept all multicasts, rather than 1405 * trying to set only those filter bits needed to match 1406 * the range. (At this time, the only use of address 1407 * ranges is for IP multicast routing, for which the 1408 * range is big enough to require all bits set.) 1409 */ 1410 ifp->if_flags |= IFF_ALLMULTI; 1411 for (i = 0; i < 8; i++) 1412 af[i] = 0xff; 1413 break; 1414 } 1415 1416 crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1417 1418 /* Just want the 6 most significant bits. */ 1419 crc = (crc >> 2) & 0x3f; 1420 1421 /* Turn on the corresponding bit in the filter. */ 1422 af[crc >> 3] |= 1 << (crc & 0x7); 1423 1424 ETHER_NEXT_MULTI(step, enm); 1425 } 1426 ifp->if_flags &= ~IFF_ALLMULTI; 1427 1428 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1429 for (i = 0; i < 8; ++i) 1430 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1431 SEEQ_BUFWIN, af[i]); 1432 } 1433 1434 static void 1435 ea_mc_reset_8005(struct seeq8005_softc *sc) 1436 { 1437 struct ether_multi *enm; 1438 struct ether_multistep step; 1439 int naddr, maxaddrs; 1440 1441 naddr = 0; 1442 maxaddrs = 5; 1443 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1444 while (enm != NULL) { 1445 /* Have we got space? */ 1446 if (naddr >= maxaddrs || 1447 memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1448 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1449 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1450 return; 1451 } 1452 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1453 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1454 naddr++; 1455 ETHER_NEXT_MULTI(step, enm); 1456 } 1457 for (; naddr < maxaddrs; naddr++) 1458 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1459 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1460 sc->sc_config1); 1461 } 1462 1463 /* 1464 * Device timeout routine. 1465 */ 1466 1467 static void 1468 ea_watchdog(struct ifnet *ifp) 1469 { 1470 struct seeq8005_softc *sc = ifp->if_softc; 1471 1472 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1473 device_xname(sc->sc_dev), 1474 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1475 ifp->if_oerrors++; 1476 1477 /* Kick the interface */ 1478 1479 ea_init(ifp); 1480 1481 ifp->if_timer = 0; 1482 } 1483 1484 /* End of seeq8005.c */ 1485
Indexes created Tue Sep 30 11:09:46 GMT 2025