seeq8005.c revision 1.62
1 /* $NetBSD: seeq8005.c,v 1.62 2019/05/23 10:40:39 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45 /* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52 /* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56 /* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: seeq8005.c,v 1.62 2019/05/23 10:40:39 msaitoh Exp $"); 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/endian.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 76 #include <net/if.h> 77 #include <net/if_dl.h> 78 #include <net/if_types.h> 79 #include <net/if_ether.h> 80 #include <net/if_media.h> 81 #include <net/bpf.h> 82 83 #include <sys/rndsource.h> 84 85 #include <sys/bus.h> 86 #include <sys/intr.h> 87 88 #include <dev/ic/seeq8005reg.h> 89 #include <dev/ic/seeq8005var.h> 90 91 /*#define SEEQ_DEBUG*/ 92 93 /* for debugging convenience */ 94 #ifdef SEEQ8005_DEBUG 95 #define SEEQ_DEBUG_MISC 1 96 #define SEEQ_DEBUG_TX 2 97 #define SEEQ_DEBUG_RX 4 98 #define SEEQ_DEBUG_PKT 8 99 #define SEEQ_DEBUG_TXINT 16 100 #define SEEQ_DEBUG_RXINT 32 101 int seeq8005_debug = 0; 102 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 103 #else 104 #define DPRINTF(f, x) 105 #endif 106 107 #ifndef EA_TX_BUFFER_SIZE 108 #define EA_TX_BUFFER_SIZE 0x800 /* (> ETHER_MAX_LEN) */ 109 #endif 110 #ifndef EA_TX_BUFFER_COUNT 111 #define EA_TX_BUFFER_COUNT 1 /* (> 0) */ 112 #endif 113 114 #define SEEQ_READ16(sc, iot, ioh, reg) \ 115 ((sc)->sc_flags & SF_8BIT ? \ 116 (bus_space_read_1((iot), (ioh), (reg)) | \ 117 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 118 (bus_space_read_2((iot), (ioh), (reg)))) 119 120 #define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 121 if ((sc)->sc_flags & SF_8BIT) { \ 122 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 123 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 124 } else \ 125 bus_space_write_2((iot), (ioh), (reg), (val)); \ 126 } while (/*CONSTCOND*/0) 127 128 /* 129 * prototypes 130 */ 131 132 static int ea_init(struct ifnet *); 133 static int ea_ioctl(struct ifnet *, u_long, void *); 134 static void ea_start(struct ifnet *); 135 static void ea_watchdog(struct ifnet *); 136 static void ea_chipreset(struct seeq8005_softc *); 137 static void ea_ramtest(struct seeq8005_softc *); 138 static int ea_stoptx(struct seeq8005_softc *); 139 static int ea_stoprx(struct seeq8005_softc *); 140 static void ea_stop(struct ifnet *, int); 141 static void ea_await_fifo_empty(struct seeq8005_softc *); 142 static void ea_await_fifo_full(struct seeq8005_softc *); 143 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 145 static void ea_select_buffer(struct seeq8005_softc *, int); 146 static void ea_set_address(struct seeq8005_softc *, int, const uint8_t *); 147 static void ea_read(struct seeq8005_softc *, int, int); 148 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 149 static void ea_txint(struct seeq8005_softc *); 150 static void ea_rxint(struct seeq8005_softc *); 151 static void ea_txpacket(struct seeq8005_softc *); 152 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 153 static void ea_mc_reset(struct seeq8005_softc *); 154 static void ea_mc_reset_8004(struct seeq8005_softc *); 155 static void ea_mc_reset_8005(struct seeq8005_softc *); 156 static int ea_mediachange(struct ifnet *); 157 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 158 159 static u_char* padbuf = NULL; 160 161 162 /* 163 * Attach chip. 164 */ 165 166 void 167 seeq8005_attach(struct seeq8005_softc *sc, const uint8_t *myaddr, int *media, 168 int nmedia, int defmedia) 169 { 170 device_t dev = sc->sc_dev; 171 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 172 bus_space_tag_t iot = sc->sc_iot; 173 bus_space_handle_t ioh = sc->sc_ioh; 174 u_int id; 175 176 KASSERT(myaddr != NULL); 177 printf(" address %s", ether_sprintf(myaddr)); 178 179 /* Stop the board. */ 180 181 ea_chipreset(sc); 182 183 /* Work out data bus width. */ 184 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 185 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 186 /* Try 8-bit mode */ 187 sc->sc_flags |= SF_8BIT; 188 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 189 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 190 aprint_normal("\n"); 191 aprint_error_dev(dev, 192 "Cannot determine data bus width\n"); 193 return; 194 } 195 } 196 197 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 198 199 /* Get the product ID */ 200 201 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 202 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 203 204 switch (id & SEEQ_PRODUCTID_MASK) { 205 case SEEQ_PRODUCTID_8004: 206 sc->sc_variant = SEEQ_8004; 207 switch (id & SEEQ_PRODUCTID_REV_MASK) { 208 case SEEQ_PRODUCTID_REV_80C04: 209 printf(", SEEQ 80C04\n"); 210 break; 211 case SEEQ_PRODUCTID_REV_80C04A: 212 printf(", SEEQ 80C04A\n"); 213 break; 214 default: 215 /* Unknown SEEQ 8004 variants */ 216 printf(", SEEQ 8004 rev %x\n", 217 id & SEEQ_PRODUCTID_REV_MASK); 218 break; 219 } 220 break; 221 default: /* XXX */ 222 sc->sc_variant = SEEQ_8005; 223 printf(", SEEQ 8005\n"); 224 break; 225 } 226 227 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 228 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 229 230 /* 231 * Set up tx and rx buffers. 232 * 233 * We set aside EA_TX_BUFFER_SIZE * EA_TX_BUFFER_COUNT for TX 234 * buffers and the rest for RX buffers 235 */ 236 sc->sc_tx_bufs = EA_TX_BUFFER_COUNT; 237 sc->sc_tx_bufsize = sc->sc_tx_bufs * EA_TX_BUFFER_SIZE; 238 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 239 sc->sc_enabled = 0; 240 241 /* Test the RAM */ 242 ea_ramtest(sc); 243 244 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 245 device_xname(dev), sc->sc_buffersize >> 10, 246 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 247 248 if (padbuf == NULL) { 249 padbuf = malloc(ETHER_MIN_LEN - ETHER_CRC_LEN, M_DEVBUF, 250 M_ZERO | M_NOWAIT); 251 if (padbuf == NULL) { 252 aprint_error_dev(dev, "can't allocate pad buffer\n"); 253 return; 254 } 255 } 256 257 /* Initialise ifnet structure. */ 258 259 strlcpy(ifp->if_xname, device_xname(dev), IFNAMSIZ); 260 ifp->if_softc = sc; 261 ifp->if_start = ea_start; 262 ifp->if_ioctl = ea_ioctl; 263 ifp->if_init = ea_init; 264 ifp->if_stop = ea_stop; 265 ifp->if_watchdog = ea_watchdog; 266 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST; 267 if (sc->sc_variant == SEEQ_8004) 268 ifp->if_flags |= IFF_SIMPLEX; 269 IFQ_SET_READY(&ifp->if_snd); 270 271 /* Initialize media goo. */ 272 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 273 if (media != NULL) { 274 int i; 275 276 for (i = 0; i < nmedia; i++) 277 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 278 ifmedia_set(&sc->sc_media, defmedia); 279 } else { 280 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 281 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL); 282 } 283 284 /* We can support 802.1Q VLAN-sized frames. */ 285 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 286 287 /* Now we can attach the interface. */ 288 289 if_attach(ifp); 290 ether_ifattach(ifp, myaddr); 291 292 printf("\n"); 293 294 /* After \n because it can print a line of its own. */ 295 rnd_attach_source(&sc->rnd_source, device_xname(dev), 296 RND_TYPE_NET, RND_FLAG_DEFAULT); 297 } 298 299 /* 300 * Media change callback. 301 */ 302 static int 303 ea_mediachange(struct ifnet *ifp) 304 { 305 struct seeq8005_softc *sc = ifp->if_softc; 306 307 if (sc->sc_mediachange) 308 return (*sc->sc_mediachange)(sc); 309 return EINVAL; 310 } 311 312 /* 313 * Media status callback. 314 */ 315 static void 316 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 317 { 318 struct seeq8005_softc *sc = ifp->if_softc; 319 320 if (sc->sc_enabled == 0) { 321 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 322 ifmr->ifm_status = 0; 323 return; 324 } 325 326 if (sc->sc_mediastatus) 327 (*sc->sc_mediastatus)(sc, ifmr); 328 } 329 330 /* 331 * Test the RAM on the ethernet card. 332 */ 333 334 void 335 ea_ramtest(struct seeq8005_softc *sc) 336 { 337 bus_space_tag_t iot = sc->sc_iot; 338 bus_space_handle_t ioh = sc->sc_ioh; 339 int loop; 340 u_int sum = 0; 341 342 /* 343 * Test the buffer memory on the board. 344 * Write simple pattens to it and read them back. 345 */ 346 347 /* Set up the whole buffer RAM for writing */ 348 349 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 350 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 351 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 352 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 353 354 #define SEEQ_RAMTEST_LOOP(value) \ 355 do { \ 356 /* Set the write start address and write a pattern */ \ 357 ea_writebuf(sc, NULL, 0x0000, 0); \ 358 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 359 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 360 \ 361 /* Set the read start address and verify the pattern */ \ 362 ea_readbuf(sc, NULL, 0x0000, 0); \ 363 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 364 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 365 ++sum; \ 366 } while (/*CONSTCOND*/0) 367 368 SEEQ_RAMTEST_LOOP(loop); 369 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 370 SEEQ_RAMTEST_LOOP(0xaa55); 371 SEEQ_RAMTEST_LOOP(0x55aa); 372 373 /* Report */ 374 375 if (sum > 0) 376 aprint_error_dev(sc->sc_dev, 377 "buffer RAM failed self test, %d faults\n", sum); 378 } 379 380 381 /* 382 * Stop the tx interface. 383 * 384 * Returns 0 if the tx was already stopped or 1 if it was active 385 */ 386 387 static int 388 ea_stoptx(struct seeq8005_softc *sc) 389 { 390 bus_space_tag_t iot = sc->sc_iot; 391 bus_space_handle_t ioh = sc->sc_ioh; 392 int timeout; 393 int status; 394 395 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 396 397 sc->sc_enabled = 0; 398 399 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 400 if (!(status & SEEQ_STATUS_TX_ON)) 401 return 0; 402 403 /* Stop any tx and wait for confirmation */ 404 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 405 sc->sc_command | SEEQ_CMD_TX_OFF); 406 407 timeout = 20000; 408 do { 409 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 410 delay(1); 411 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 412 if (timeout == 0) 413 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 414 device_xname(sc->sc_dev)); 415 416 /* Clear any pending tx interrupt */ 417 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 418 sc->sc_command | SEEQ_CMD_TX_INTACK); 419 return 1; 420 } 421 422 423 /* 424 * Stop the rx interface. 425 * 426 * Returns 0 if the tx was already stopped or 1 if it was active 427 */ 428 429 static int 430 ea_stoprx(struct seeq8005_softc *sc) 431 { 432 bus_space_tag_t iot = sc->sc_iot; 433 bus_space_handle_t ioh = sc->sc_ioh; 434 int timeout; 435 int status; 436 437 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 438 439 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 440 if (!(status & SEEQ_STATUS_RX_ON)) 441 return 0; 442 443 /* Stop any rx and wait for confirmation */ 444 445 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 446 sc->sc_command | SEEQ_CMD_RX_OFF); 447 448 timeout = 20000; 449 do { 450 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 451 delay(1); 452 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 453 if (timeout == 0) 454 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 455 device_xname(sc->sc_dev)); 456 457 /* Clear any pending rx interrupt */ 458 459 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 460 sc->sc_command | SEEQ_CMD_RX_INTACK); 461 return 1; 462 } 463 464 465 /* 466 * Stop interface. 467 * Stop all IO and shut the interface down 468 */ 469 470 /* ARGSUSED */ 471 static void 472 ea_stop(struct ifnet *ifp, int disable) 473 { 474 struct seeq8005_softc *sc = ifp->if_softc; 475 bus_space_tag_t iot = sc->sc_iot; 476 bus_space_handle_t ioh = sc->sc_ioh; 477 478 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 479 480 /* Stop all IO */ 481 ea_stoptx(sc); 482 ea_stoprx(sc); 483 484 /* Disable rx and tx interrupts */ 485 sc->sc_command &= ~(SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 486 487 /* Clear any pending interrupts */ 488 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 489 sc->sc_command | SEEQ_CMD_RX_INTACK | SEEQ_CMD_TX_INTACK | 490 SEEQ_CMD_DMA_INTACK | SEEQ_CMD_BW_INTACK); 491 492 if (sc->sc_variant == SEEQ_8004) { 493 /* Put the chip to sleep */ 494 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 495 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 496 sc->sc_config3 | SEEQ_CFG3_SLEEP); 497 } 498 499 /* Cancel any watchdog timer */ 500 sc->sc_ethercom.ec_if.if_timer = 0; 501 } 502 503 504 /* 505 * Reset the chip 506 * Following this the software registers are reset 507 */ 508 509 static void 510 ea_chipreset(struct seeq8005_softc *sc) 511 { 512 bus_space_tag_t iot = sc->sc_iot; 513 bus_space_handle_t ioh = sc->sc_ioh; 514 515 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 516 517 /* Reset the controller. Min of 4us delay here */ 518 519 /* 520 * This can be called before we know whether the chip is in 8- or 521 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 522 * harmless in 8-bit mode, so we do that second. 523 */ 524 525 /* In 16-bit mode, this will munge the PreamSelect bit. */ 526 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 527 delay(4); 528 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 529 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 530 delay(4); 531 532 sc->sc_command = 0; 533 sc->sc_config1 = 0; 534 sc->sc_config2 = 0; 535 sc->sc_config3 = 0; 536 } 537 538 539 /* 540 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 541 * switching the FIFO from write to read. We also use it when changing 542 * the address for writes. 543 */ 544 static void 545 ea_await_fifo_empty(struct seeq8005_softc *sc) 546 { 547 bus_space_tag_t iot = sc->sc_iot; 548 bus_space_handle_t ioh = sc->sc_ioh; 549 int timeout; 550 551 timeout = 20000; 552 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 553 SEEQ_STATUS_FIFO_DIR) != 0) 554 return; /* FIFO is reading anyway. */ 555 while (--timeout > 0) 556 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 557 SEEQ_STATUS_FIFO_EMPTY) 558 return; 559 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", device_xname(sc->sc_dev)); 560 } 561 562 /* 563 * Wait for the DMA FIFO to fill before reading from it. 564 */ 565 static void 566 ea_await_fifo_full(struct seeq8005_softc *sc) 567 { 568 bus_space_tag_t iot = sc->sc_iot; 569 bus_space_handle_t ioh = sc->sc_ioh; 570 int timeout; 571 572 timeout = 20000; 573 while (--timeout > 0) 574 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 575 SEEQ_STATUS_FIFO_FULL) 576 return; 577 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", device_xname(sc->sc_dev)); 578 } 579 580 /* 581 * write to the buffer memory on the interface 582 * 583 * The buffer address is set to ADDR. 584 * If len != 0 then data is copied from the address starting at buf 585 * to the interface buffer. 586 * BUF must be usable as a uint16_t *. 587 * If LEN is odd, it must be safe to overwrite one extra byte. 588 */ 589 590 static void 591 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 592 { 593 bus_space_tag_t iot = sc->sc_iot; 594 bus_space_handle_t ioh = sc->sc_ioh; 595 596 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 597 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 598 599 #ifdef DIAGNOSTIC 600 if (__predict_false(!ALIGNED_POINTER(buf, uint16_t))) 601 panic("%s: unaligned writebuf", device_xname(sc->sc_dev)); 602 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 603 panic("%s: writebuf out of range", device_xname(sc->sc_dev)); 604 #endif 605 606 if (addr != -1) { 607 ea_await_fifo_empty(sc); 608 609 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 610 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 611 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 612 613 ea_await_fifo_empty(sc); 614 615 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 616 } 617 618 if (len > 0) { 619 if (sc->sc_flags & SF_8BIT) 620 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 621 (uint8_t *)buf, len); 622 else 623 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 624 /* LINTED: alignment checked above */ 625 (uint16_t *)buf, len / 2); 626 } 627 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 628 /* Write the last byte */ 629 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, buf[len - 1]); 630 } 631 /* Leave FIFO to empty in the background */ 632 } 633 634 635 /* 636 * read from the buffer memory on the interface 637 * 638 * The buffer address is set to ADDR. 639 * If len != 0 then data is copied from the interface buffer to the 640 * address starting at buf. 641 * BUF must be usable as a uint16_t *. 642 * If LEN is odd, it must be safe to overwrite one extra byte. 643 */ 644 645 static void 646 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 647 { 648 bus_space_tag_t iot = sc->sc_iot; 649 bus_space_handle_t ioh = sc->sc_ioh; 650 int runup; 651 652 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 653 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 654 655 #ifdef DIAGNOSTIC 656 if (__predict_false(!ALIGNED_POINTER(buf, uint16_t))) 657 panic("%s: unaligned readbuf", device_xname(sc->sc_dev)); 658 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 659 panic("%s: readbuf out of range", device_xname(sc->sc_dev)); 660 #endif 661 662 if (addr != -1) { 663 /* 664 * SEEQ 80C04 bug: 665 * Starting reading from certain addresses seems to cause 666 * us to get bogus results, so we avoid them. 667 */ 668 runup = 0; 669 if (sc->sc_variant == SEEQ_8004 && 670 ((addr & 0x00ff) == 0x00ea || 671 (addr & 0x00ff) == 0x00ee || 672 (addr & 0x00ff) == 0x00f0)) 673 runup = (addr & 0x00ff) - 0x00e8; 674 675 ea_await_fifo_empty(sc); 676 677 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 678 679 /* 680 * 80C04 bug workaround. I found this in the old arm32 "eb" 681 * driver. I've no idea what it does, but it seems to stop 682 * the chip mangling data so often. 683 */ 684 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 685 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 686 ea_await_fifo_empty(sc); 687 688 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 689 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 690 sc->sc_command | SEEQ_CMD_FIFO_READ); 691 692 ea_await_fifo_full(sc); 693 while (runup > 0) { 694 /* LINTED: Reading a volatile _does_ have an effect */ 695 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 696 runup -= 2; 697 } 698 } 699 700 if (len > 0) { 701 if (sc->sc_flags & SF_8BIT) 702 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 703 (uint8_t *)buf, len); 704 else 705 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 706 /* LINTED: pointer alignment checked above */ 707 (uint16_t *)buf, len / 2); 708 } 709 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 710 /* Read the last byte */ 711 buf[len - 1] = bus_space_read_2(iot, ioh, SEEQ_BUFWIN); 712 } 713 } 714 715 static void 716 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 717 { 718 719 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 720 sc->sc_config1 | bufcode); 721 } 722 723 /* Must be called at splnet */ 724 static void 725 ea_set_address(struct seeq8005_softc *sc, int which, const uint8_t *ea) 726 { 727 int i; 728 729 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 730 for (i = 0; i < ETHER_ADDR_LEN; ++i) 731 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, ea[i]); 732 } 733 734 /* 735 * Initialize interface. 736 * 737 * This should leave the interface in a state for packet reception and 738 * transmission. 739 */ 740 741 static int 742 ea_init(struct ifnet *ifp) 743 { 744 struct seeq8005_softc *sc = ifp->if_softc; 745 bus_space_tag_t iot = sc->sc_iot; 746 bus_space_handle_t ioh = sc->sc_ioh; 747 int s; 748 749 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 750 751 s = splnet(); 752 753 /* First, reset the board. */ 754 755 ea_chipreset(sc); 756 757 /* Set up defaults for the registers */ 758 759 sc->sc_command = 0; 760 sc->sc_config1 = 0; 761 #if BYTE_ORDER == BIG_ENDIAN 762 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 763 #else 764 sc->sc_config2 = 0; 765 #endif 766 sc->sc_config3 = 0; 767 768 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 769 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 770 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 771 if (sc->sc_variant == SEEQ_8004) { 772 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 773 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 774 } 775 776 /* Write the station address - the receiver must be off */ 777 ea_set_address(sc, 0, (const uint8_t *)CLLADDR(ifp->if_sadl)); 778 779 /* Split board memory into Rx and Tx. */ 780 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 781 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 782 783 if (sc->sc_variant == SEEQ_8004) { 784 /* Make the interface IFF_SIMPLEX. */ 785 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 786 /* Enable reception of long packets (for vlan(4)). */ 787 sc->sc_config2 |= SEEQ_CFG2_PASS_LONGSHORT; 788 } 789 790 /* Configure rx. */ 791 ea_mc_reset(sc); 792 if (ifp->if_flags & IFF_PROMISC) 793 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 794 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 795 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 796 else 797 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 798 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 799 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 800 801 /* Setup the Rx pointers */ 802 sc->sc_rx_ptr = sc->sc_tx_bufsize; 803 804 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 805 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 806 807 808 /* Place a NULL header at the beginning of the receive area */ 809 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 810 811 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 812 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 813 814 815 /* Configure TX. */ 816 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 817 818 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 819 820 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 821 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 822 823 /* Reset tx buffer pointers */ 824 sc->sc_tx_cur = 0; 825 sc->sc_tx_used = 0; 826 sc->sc_tx_next = 0; 827 828 /* Place a NULL header at the beginning of the transmit area */ 829 ea_writebuf(sc, NULL, 0x0000, 0); 830 831 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 832 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 833 834 sc->sc_command |= SEEQ_CMD_TX_INTEN; 835 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 836 837 /* Turn on Rx */ 838 sc->sc_command |= SEEQ_CMD_RX_INTEN; 839 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 840 sc->sc_command | SEEQ_CMD_RX_ON); 841 842 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 843 844 845 /* Set flags appropriately. */ 846 ifp->if_flags |= IFF_RUNNING; 847 ifp->if_flags &= ~IFF_OACTIVE; 848 sc->sc_enabled = 1; 849 850 /* And start output. */ 851 ea_start(ifp); 852 853 splx(s); 854 return 0; 855 } 856 857 /* 858 * Start output on interface. Get datagrams from the queue and output them, 859 * giving the receiver a chance between datagrams. Call only from splnet or 860 * interrupt level! 861 */ 862 863 static void 864 ea_start(struct ifnet *ifp) 865 { 866 struct seeq8005_softc *sc = ifp->if_softc; 867 int s; 868 869 s = splnet(); 870 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 871 872 /* 873 * Don't do anything if output is active. seeq8005intr() will call 874 * us (actually ea_txpacket()) back when the card's ready for more 875 * frames. 876 */ 877 if (ifp->if_flags & IFF_OACTIVE) { 878 splx(s); 879 return; 880 } 881 882 /* Mark interface as output active */ 883 884 ifp->if_flags |= IFF_OACTIVE; 885 886 /* tx packets */ 887 888 ea_txpacket(sc); 889 splx(s); 890 } 891 892 893 /* 894 * Transfer a packet to the interface buffer and start transmission 895 * 896 * Called at splnet() 897 */ 898 899 static void 900 ea_txpacket(struct seeq8005_softc *sc) 901 { 902 bus_space_tag_t iot = sc->sc_iot; 903 bus_space_handle_t ioh = sc->sc_ioh; 904 struct mbuf *m0; 905 struct ifnet *ifp; 906 907 ifp = &sc->sc_ethercom.ec_if; 908 909 /* Dequeue the next packet. */ 910 IFQ_DEQUEUE(&ifp->if_snd, m0); 911 912 /* If there's nothing to send, return. */ 913 if (m0 == NULL) { 914 ifp->if_flags &= ~IFF_OACTIVE; 915 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 916 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 917 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 918 return; 919 } 920 921 /* Give the packet to the bpf, if any. */ 922 bpf_mtap(ifp, m0, BPF_D_OUT); 923 924 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 925 926 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 927 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 928 929 ea_writembuf(sc, m0, 0x0000); 930 m_freem(m0); 931 932 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 933 934 /* Now transmit the datagram. */ 935 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 936 sc->sc_command | SEEQ_CMD_TX_ON); 937 938 /* Make sure we notice if the chip goes silent on us. */ 939 ifp->if_timer = 5; 940 941 DPRINTF(SEEQ_DEBUG_TX, 942 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 943 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 944 } 945 946 /* 947 * Copy a packet from an mbuf to the transmit buffer on the card. 948 * 949 * Puts a valid Tx header at the start of the packet, and a null header at 950 * the end. 951 */ 952 static int 953 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 954 { 955 struct mbuf *m; 956 int len, nextpacket; 957 uint8_t hdr[4]; 958 959 /* 960 * Copy the datagram to the packet buffer. 961 */ 962 len = 0; 963 for (m = m0; m; m = m->m_next) { 964 if (m->m_len == 0) 965 continue; 966 ea_writebuf(sc, mtod(m, u_char *), bufstart + 4 + len, 967 m->m_len); 968 len += m->m_len; 969 } 970 971 if (len < ETHER_MIN_LEN) { 972 ea_writebuf(sc, padbuf, bufstart + 4 + len, 973 ETHER_MIN_LEN - len); 974 len = ETHER_MIN_LEN; 975 } 976 977 /* Follow it with a NULL packet header */ 978 memset(hdr, 0, 4); 979 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 980 981 /* Ok we now have a packet len bytes long in our packet buffer */ 982 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 983 984 /* Write the packet header */ 985 nextpacket = bufstart + len + 4; 986 hdr[0] = (nextpacket >> 8) & 0xff; 987 hdr[1] = nextpacket & 0xff; 988 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 989 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 990 hdr[3] = 0; /* Status byte -- will be updated by hardware. */ 991 ea_writebuf(sc, hdr, bufstart, 4); 992 993 return len; 994 } 995 996 /* 997 * Ethernet controller interrupt. 998 */ 999 1000 int 1001 seeq8005intr(void *arg) 1002 { 1003 struct seeq8005_softc *sc = arg; 1004 bus_space_tag_t iot = sc->sc_iot; 1005 bus_space_handle_t ioh = sc->sc_ioh; 1006 int status, handled; 1007 1008 handled = 0; 1009 1010 /* Get the controller status */ 1011 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 1012 1013 /* Tx interrupt ? */ 1014 if (status & SEEQ_STATUS_TX_INT) { 1015 handled = 1; 1016 1017 /* Acknowledge the interrupt */ 1018 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1019 sc->sc_command | SEEQ_CMD_TX_INTACK); 1020 1021 ea_txint(sc); 1022 } 1023 1024 1025 /* Rx interrupt ? */ 1026 if (status & SEEQ_STATUS_RX_INT) { 1027 handled = 1; 1028 1029 /* Acknowledge the interrupt */ 1030 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1031 sc->sc_command | SEEQ_CMD_RX_INTACK); 1032 1033 /* Processes the received packets */ 1034 ea_rxint(sc); 1035 } 1036 1037 if (handled) 1038 rnd_add_uint32(&sc->rnd_source, status); 1039 1040 return handled; 1041 } 1042 1043 static void 1044 ea_txint(struct seeq8005_softc *sc) 1045 { 1046 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1047 bus_space_tag_t iot = sc->sc_iot; 1048 bus_space_handle_t ioh = sc->sc_ioh; 1049 uint8_t txhdr[4]; 1050 u_int txstatus; 1051 1052 ea_readbuf(sc, txhdr, 0x0000, 4); 1053 1054 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1055 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1056 txstatus = txhdr[3]; 1057 1058 /* 1059 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1060 * one collision. On the 8004 we can find out exactly how many 1061 * collisions occurred. 1062 * 1063 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1064 * completed. 1065 * 1066 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1067 * occurred and the packet transmission was aborted. 1068 * This situation is untested as present. 1069 * 1070 * The SEEQ_TXSTAT_BABBLE is untested as it should only be set 1071 * when we deliberately transmit oversized packets (e.g. for 1072 * 802.1Q). 1073 */ 1074 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1075 switch (sc->sc_variant) { 1076 case SEEQ_8004: { 1077 int colls; 1078 1079 /* 1080 * The 8004 contains a 4 bit collision count 1081 * in the status register. 1082 */ 1083 1084 /* This appears to be broken on 80C04.AE */ 1085 /* ifp->if_collisions += 1086 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1087 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1088 1089 /* Use the TX Collision register */ 1090 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1091 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1092 ifp->if_collisions += colls; 1093 break; 1094 } 1095 case SEEQ_8005: 1096 /* We known there was at least 1 collision */ 1097 ifp->if_collisions++; 1098 break; 1099 } 1100 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1101 printf("seeq_intr: col16 %x\n", txstatus); 1102 ifp->if_collisions += 16; 1103 ifp->if_oerrors++; 1104 } 1105 1106 /* Have we completed transmission on the packet ? */ 1107 if (txstatus & SEEQ_PKTSTAT_DONE) { 1108 /* Clear watchdog timer. */ 1109 ifp->if_timer = 0; 1110 ifp->if_flags &= ~IFF_OACTIVE; 1111 1112 /* Update stats */ 1113 ifp->if_opackets++; 1114 1115 /* Tx next packet */ 1116 1117 ea_txpacket(sc); 1118 } 1119 } 1120 1121 static void 1122 ea_rxint(struct seeq8005_softc *sc) 1123 { 1124 bus_space_tag_t iot = sc->sc_iot; 1125 bus_space_handle_t ioh = sc->sc_ioh; 1126 u_int addr; 1127 int len; 1128 int ctrl; 1129 int ptr; 1130 int status; 1131 uint8_t rxhdr[4]; 1132 struct ifnet *ifp; 1133 1134 ifp = &sc->sc_ethercom.ec_if; 1135 1136 1137 /* We start from the last rx pointer position */ 1138 addr = sc->sc_rx_ptr; 1139 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1140 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1141 1142 do { 1143 /* Read rx header */ 1144 ea_readbuf(sc, rxhdr, addr, 4); 1145 1146 /* Split the packet header */ 1147 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1148 ctrl = rxhdr[2]; 1149 status = rxhdr[3]; 1150 1151 DPRINTF(SEEQ_DEBUG_RX, 1152 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1153 addr, ptr, ctrl, status)); 1154 1155 /* Zero packet ptr ? then must be null header so exit */ 1156 if (ptr == 0) break; 1157 1158 /* Sanity-check the next-packet pointer and flags. */ 1159 if (__predict_false(ptr < sc->sc_tx_bufsize || 1160 (ctrl & SEEQ_PKTCMD_TX))) { 1161 ++ifp->if_ierrors; 1162 log(LOG_ERR, 1163 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1164 device_xname(sc->sc_dev), addr, ptr); 1165 ea_init(ifp); 1166 return; 1167 } 1168 1169 /* Get packet length */ 1170 len = (ptr - addr) - 4; 1171 1172 if (len < 0) 1173 len += sc->sc_rx_bufsize; 1174 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1175 1176 /* Has the packet rx completed ? if not then exit */ 1177 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1178 break; 1179 1180 /* 1181 * Did we have any errors? then note error and go to 1182 * next packet 1183 */ 1184 if (__predict_false(status & 1185 (SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR | 1186 SEEQ_RXSTAT_SHORT_FRAME))) { 1187 ++ifp->if_ierrors; 1188 log(LOG_WARNING, 1189 "%s: rx packet error at %04x (err=%02x)\n", 1190 device_xname(sc->sc_dev), addr, status & 0x0f); 1191 /* XXX shouldn't need to reset if it's genuine. */ 1192 ea_init(ifp); 1193 return; 1194 } 1195 /* 1196 * Is the packet too big? We allow slightly oversize packets 1197 * for vlan(4) and tcpdump purposes, but the rest of the world 1198 * wants incoming packets in a single mbuf cluster. 1199 */ 1200 if (__predict_false(len > MCLBYTES)) { 1201 ++ifp->if_ierrors; 1202 log(LOG_ERR, 1203 "%s: rx packet size error at %04x (len=%d)\n", 1204 device_xname(sc->sc_dev), addr, len); 1205 ea_init(ifp); 1206 return; 1207 } 1208 1209 /* Pass data up to upper levels. */ 1210 ea_read(sc, addr + 4, len); 1211 1212 addr = ptr; 1213 } while (len != 0); 1214 1215 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1216 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1217 1218 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1219 1220 /* Store new rx pointer */ 1221 sc->sc_rx_ptr = addr; 1222 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1223 1224 /* Make sure the receiver is on */ 1225 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1226 sc->sc_command | SEEQ_CMD_RX_ON); 1227 } 1228 1229 1230 /* 1231 * Pass a packet up to the higher levels. 1232 */ 1233 1234 static void 1235 ea_read(struct seeq8005_softc *sc, int addr, int len) 1236 { 1237 struct mbuf *m; 1238 struct ifnet *ifp; 1239 1240 ifp = &sc->sc_ethercom.ec_if; 1241 1242 /* Pull packet off interface. */ 1243 m = ea_get(sc, addr, len, ifp); 1244 if (m == NULL) 1245 return; 1246 1247 if_percpuq_enqueue(ifp->if_percpuq, m); 1248 } 1249 1250 /* 1251 * Pull read data off a interface. Len is length of data, with local net 1252 * header stripped. We copy the data into mbufs. When full cluster sized 1253 * units are present we copy into clusters. 1254 */ 1255 1256 struct mbuf * 1257 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1258 { 1259 struct mbuf *top, **mp, *m; 1260 int len; 1261 u_int cp, epkt; 1262 1263 cp = addr; 1264 epkt = cp + totlen; 1265 1266 MGETHDR(m, M_DONTWAIT, MT_DATA); 1267 if (m == NULL) 1268 return NULL; 1269 m_set_rcvif(m, ifp); 1270 m->m_pkthdr.len = totlen; 1271 m->m_len = MHLEN; 1272 top = NULL; 1273 mp = ⊤ 1274 1275 while (totlen > 0) { 1276 if (top) { 1277 MGET(m, M_DONTWAIT, MT_DATA); 1278 if (m == NULL) { 1279 m_freem(top); 1280 return NULL; 1281 } 1282 m->m_len = MLEN; 1283 } 1284 len = uimin(totlen, epkt - cp); 1285 if (len >= MINCLSIZE) { 1286 MCLGET(m, M_DONTWAIT); 1287 if (m->m_flags & M_EXT) 1288 m->m_len = len = uimin(len, MCLBYTES); 1289 else 1290 len = m->m_len; 1291 } else { 1292 /* 1293 * Place initial small packet/header at end of mbuf. 1294 */ 1295 if (len < m->m_len) { 1296 if (top == NULL && len + max_linkhdr <= m->m_len) 1297 m->m_data += max_linkhdr; 1298 m->m_len = len; 1299 } else 1300 len = m->m_len; 1301 } 1302 if (top == NULL) { 1303 /* Make sure the payload is aligned */ 1304 char *newdata = (char *) 1305 ALIGN((char*)m->m_data + 1306 sizeof(struct ether_header)) - 1307 sizeof(struct ether_header); 1308 len -= newdata - m->m_data; 1309 m->m_len = len; 1310 m->m_data = newdata; 1311 } 1312 ea_readbuf(sc, mtod(m, u_char *), 1313 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1314 len); 1315 cp += len; 1316 *mp = m; 1317 mp = &m->m_next; 1318 totlen -= len; 1319 if (cp == epkt) 1320 cp = addr; 1321 } 1322 1323 return top; 1324 } 1325 1326 /* 1327 * Process an ioctl request. Mostly boilerplate. 1328 */ 1329 static int 1330 ea_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1331 { 1332 struct seeq8005_softc *sc = ifp->if_softc; 1333 int s, error = 0; 1334 1335 s = splnet(); 1336 switch (cmd) { 1337 1338 default: 1339 error = ether_ioctl(ifp, cmd, data); 1340 if (error == ENETRESET) { 1341 /* 1342 * Multicast list has changed; set the hardware filter 1343 * accordingly. 1344 */ 1345 if (ifp->if_flags & IFF_RUNNING) 1346 ea_mc_reset(sc); 1347 error = 0; 1348 } 1349 break; 1350 } 1351 1352 splx(s); 1353 return error; 1354 } 1355 1356 /* Must be called at splnet() */ 1357 1358 static void 1359 ea_mc_reset(struct seeq8005_softc *sc) 1360 { 1361 1362 switch (sc->sc_variant) { 1363 case SEEQ_8004: 1364 ea_mc_reset_8004(sc); 1365 return; 1366 case SEEQ_8005: 1367 ea_mc_reset_8005(sc); 1368 return; 1369 } 1370 } 1371 1372 static void 1373 ea_mc_reset_8004(struct seeq8005_softc *sc) 1374 { 1375 struct ethercom *ec = &sc->sc_ethercom; 1376 struct ifnet *ifp = &ec->ec_if; 1377 struct ether_multi *enm; 1378 uint32_t crc; 1379 int i; 1380 struct ether_multistep step; 1381 uint8_t af[8]; 1382 1383 /* 1384 * Set up multicast address filter by passing all multicast addresses 1385 * through a crc generator, and then using bits 2 - 7 as an index 1386 * into the 64 bit logical address filter. The high order bits 1387 * selects the word, while the rest of the bits select the bit within 1388 * the word. 1389 */ 1390 1391 if (ifp->if_flags & IFF_PROMISC) { 1392 ifp->if_flags |= IFF_ALLMULTI; 1393 for (i = 0; i < 8; i++) 1394 af[i] = 0xff; 1395 return; 1396 } 1397 for (i = 0; i < 8; i++) 1398 af[i] = 0; 1399 ETHER_FIRST_MULTI(step, ec, enm); 1400 while (enm != NULL) { 1401 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1402 sizeof(enm->enm_addrlo)) != 0) { 1403 /* 1404 * We must listen to a range of multicast addresses. 1405 * For now, just accept all multicasts, rather than 1406 * trying to set only those filter bits needed to match 1407 * the range. (At this time, the only use of address 1408 * ranges is for IP multicast routing, for which the 1409 * range is big enough to require all bits set.) 1410 */ 1411 ifp->if_flags |= IFF_ALLMULTI; 1412 for (i = 0; i < 8; i++) 1413 af[i] = 0xff; 1414 break; 1415 } 1416 1417 crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1418 1419 /* Just want the 6 most significant bits. */ 1420 crc = (crc >> 2) & 0x3f; 1421 1422 /* Turn on the corresponding bit in the filter. */ 1423 af[crc >> 3] |= 1 << (crc & 0x7); 1424 1425 ETHER_NEXT_MULTI(step, enm); 1426 } 1427 ifp->if_flags &= ~IFF_ALLMULTI; 1428 1429 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1430 for (i = 0; i < 8; ++i) 1431 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1432 SEEQ_BUFWIN, af[i]); 1433 } 1434 1435 static void 1436 ea_mc_reset_8005(struct seeq8005_softc *sc) 1437 { 1438 struct ethercom *ec = &sc->sc_ethercom; 1439 struct ether_multi *enm; 1440 struct ether_multistep step; 1441 int naddr, maxaddrs; 1442 1443 naddr = 0; 1444 maxaddrs = 5; 1445 ETHER_FIRST_MULTI(step, ec, enm); 1446 while (enm != NULL) { 1447 /* Have we got space? */ 1448 if (naddr >= maxaddrs || 1449 memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1450 ec->ec_if.if_flags |= IFF_ALLMULTI; 1451 ea_ioctl(&ec->ec_if, SIOCSIFFLAGS, NULL); 1452 return; 1453 } 1454 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1455 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1456 naddr++; 1457 ETHER_NEXT_MULTI(step, enm); 1458 } 1459 for (; naddr < maxaddrs; naddr++) 1460 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1461 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1462 sc->sc_config1); 1463 } 1464 1465 /* 1466 * Device timeout routine. 1467 */ 1468 1469 static void 1470 ea_watchdog(struct ifnet *ifp) 1471 { 1472 struct seeq8005_softc *sc = ifp->if_softc; 1473 1474 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1475 device_xname(sc->sc_dev), 1476 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1477 ifp->if_oerrors++; 1478 1479 /* Kick the interface */ 1480 1481 ea_init(ifp); 1482 1483 ifp->if_timer = 0; 1484 } 1485 1486 /* End of seeq8005.c */ 1487
Indexes created Tue Sep 30 11:09:46 GMT 2025