seeq8005.c revision 1.64
1 /* $NetBSD: seeq8005.c,v 1.64 2019/05/28 07:41:48 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 /* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39 /* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45 /* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52 /* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56 /* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: seeq8005.c,v 1.64 2019/05/28 07:41:48 msaitoh Exp $"); 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/endian.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 76 #include <net/if.h> 77 #include <net/if_dl.h> 78 #include <net/if_types.h> 79 #include <net/if_ether.h> 80 #include <net/if_media.h> 81 #include <net/bpf.h> 82 83 #include <sys/rndsource.h> 84 85 #include <sys/bus.h> 86 #include <sys/intr.h> 87 88 #include <dev/ic/seeq8005reg.h> 89 #include <dev/ic/seeq8005var.h> 90 91 /*#define SEEQ_DEBUG*/ 92 93 /* for debugging convenience */ 94 #ifdef SEEQ8005_DEBUG 95 #define SEEQ_DEBUG_MISC 1 96 #define SEEQ_DEBUG_TX 2 97 #define SEEQ_DEBUG_RX 4 98 #define SEEQ_DEBUG_PKT 8 99 #define SEEQ_DEBUG_TXINT 16 100 #define SEEQ_DEBUG_RXINT 32 101 int seeq8005_debug = 0; 102 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 103 #else 104 #define DPRINTF(f, x) 105 #endif 106 107 #ifndef EA_TX_BUFFER_SIZE 108 #define EA_TX_BUFFER_SIZE 0x800 /* (> ETHER_MAX_LEN) */ 109 #endif 110 #ifndef EA_TX_BUFFER_COUNT 111 #define EA_TX_BUFFER_COUNT 1 /* (> 0) */ 112 #endif 113 114 #define SEEQ_READ16(sc, iot, ioh, reg) \ 115 ((sc)->sc_flags & SF_8BIT ? \ 116 (bus_space_read_1((iot), (ioh), (reg)) | \ 117 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 118 (bus_space_read_2((iot), (ioh), (reg)))) 119 120 #define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 121 if ((sc)->sc_flags & SF_8BIT) { \ 122 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 123 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 124 } else \ 125 bus_space_write_2((iot), (ioh), (reg), (val)); \ 126 } while (/*CONSTCOND*/0) 127 128 /* 129 * prototypes 130 */ 131 132 static int ea_init(struct ifnet *); 133 static int ea_ioctl(struct ifnet *, u_long, void *); 134 static void ea_start(struct ifnet *); 135 static void ea_watchdog(struct ifnet *); 136 static void ea_chipreset(struct seeq8005_softc *); 137 static void ea_ramtest(struct seeq8005_softc *); 138 static int ea_stoptx(struct seeq8005_softc *); 139 static int ea_stoprx(struct seeq8005_softc *); 140 static void ea_stop(struct ifnet *, int); 141 static void ea_await_fifo_empty(struct seeq8005_softc *); 142 static void ea_await_fifo_full(struct seeq8005_softc *); 143 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 144 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 145 static void ea_select_buffer(struct seeq8005_softc *, int); 146 static void ea_set_address(struct seeq8005_softc *, int, const uint8_t *); 147 static void ea_read(struct seeq8005_softc *, int, int); 148 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 149 static void ea_txint(struct seeq8005_softc *); 150 static void ea_rxint(struct seeq8005_softc *); 151 static void ea_txpacket(struct seeq8005_softc *); 152 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 153 static void ea_mc_reset(struct seeq8005_softc *); 154 static void ea_mc_reset_8004(struct seeq8005_softc *); 155 static void ea_mc_reset_8005(struct seeq8005_softc *); 156 static int ea_mediachange(struct ifnet *); 157 static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 158 159 static u_char* padbuf = NULL; 160 161 162 /* 163 * Attach chip. 164 */ 165 166 void 167 seeq8005_attach(struct seeq8005_softc *sc, const uint8_t *myaddr, int *media, 168 int nmedia, int defmedia) 169 { 170 device_t dev = sc->sc_dev; 171 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 172 bus_space_tag_t iot = sc->sc_iot; 173 bus_space_handle_t ioh = sc->sc_ioh; 174 u_int id; 175 176 KASSERT(myaddr != NULL); 177 printf(" address %s", ether_sprintf(myaddr)); 178 179 /* Stop the board. */ 180 181 ea_chipreset(sc); 182 183 /* Work out data bus width. */ 184 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 185 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 186 /* Try 8-bit mode */ 187 sc->sc_flags |= SF_8BIT; 188 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 189 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 190 aprint_normal("\n"); 191 aprint_error_dev(dev, 192 "Cannot determine data bus width\n"); 193 return; 194 } 195 } 196 197 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 198 199 /* Get the product ID */ 200 201 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 202 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 203 204 switch (id & SEEQ_PRODUCTID_MASK) { 205 case SEEQ_PRODUCTID_8004: 206 sc->sc_variant = SEEQ_8004; 207 switch (id & SEEQ_PRODUCTID_REV_MASK) { 208 case SEEQ_PRODUCTID_REV_80C04: 209 printf(", SEEQ 80C04\n"); 210 break; 211 case SEEQ_PRODUCTID_REV_80C04A: 212 printf(", SEEQ 80C04A\n"); 213 break; 214 default: 215 /* Unknown SEEQ 8004 variants */ 216 printf(", SEEQ 8004 rev %x\n", 217 id & SEEQ_PRODUCTID_REV_MASK); 218 break; 219 } 220 break; 221 default: /* XXX */ 222 sc->sc_variant = SEEQ_8005; 223 printf(", SEEQ 8005\n"); 224 break; 225 } 226 227 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 228 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 229 230 /* 231 * Set up tx and rx buffers. 232 * 233 * We set aside EA_TX_BUFFER_SIZE * EA_TX_BUFFER_COUNT for TX 234 * buffers and the rest for RX buffers 235 */ 236 sc->sc_tx_bufs = EA_TX_BUFFER_COUNT; 237 sc->sc_tx_bufsize = sc->sc_tx_bufs * EA_TX_BUFFER_SIZE; 238 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 239 sc->sc_enabled = 0; 240 241 /* Test the RAM */ 242 ea_ramtest(sc); 243 244 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 245 device_xname(dev), sc->sc_buffersize >> 10, 246 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 247 248 if (padbuf == NULL) { 249 padbuf = malloc(ETHER_MIN_LEN - ETHER_CRC_LEN, M_DEVBUF, 250 M_ZERO | M_NOWAIT); 251 if (padbuf == NULL) { 252 aprint_error_dev(dev, "can't allocate pad buffer\n"); 253 return; 254 } 255 } 256 257 /* Initialise ifnet structure. */ 258 259 strlcpy(ifp->if_xname, device_xname(dev), IFNAMSIZ); 260 ifp->if_softc = sc; 261 ifp->if_start = ea_start; 262 ifp->if_ioctl = ea_ioctl; 263 ifp->if_init = ea_init; 264 ifp->if_stop = ea_stop; 265 ifp->if_watchdog = ea_watchdog; 266 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST; 267 if (sc->sc_variant == SEEQ_8004) 268 ifp->if_flags |= IFF_SIMPLEX; 269 IFQ_SET_READY(&ifp->if_snd); 270 271 /* Initialize media goo. */ 272 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 273 if (media != NULL) { 274 int i; 275 276 for (i = 0; i < nmedia; i++) 277 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 278 ifmedia_set(&sc->sc_media, defmedia); 279 } else { 280 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 281 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL); 282 } 283 284 /* We can support 802.1Q VLAN-sized frames. */ 285 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 286 287 /* Now we can attach the interface. */ 288 289 if_attach(ifp); 290 ether_ifattach(ifp, myaddr); 291 292 printf("\n"); 293 294 /* After \n because it can print a line of its own. */ 295 rnd_attach_source(&sc->rnd_source, device_xname(dev), 296 RND_TYPE_NET, RND_FLAG_DEFAULT); 297 } 298 299 /* 300 * Media change callback. 301 */ 302 static int 303 ea_mediachange(struct ifnet *ifp) 304 { 305 struct seeq8005_softc *sc = ifp->if_softc; 306 307 if (sc->sc_mediachange) 308 return (*sc->sc_mediachange)(sc); 309 return EINVAL; 310 } 311 312 /* 313 * Media status callback. 314 */ 315 static void 316 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 317 { 318 struct seeq8005_softc *sc = ifp->if_softc; 319 320 if (sc->sc_enabled == 0) { 321 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 322 ifmr->ifm_status = 0; 323 return; 324 } 325 326 if (sc->sc_mediastatus) 327 (*sc->sc_mediastatus)(sc, ifmr); 328 } 329 330 /* 331 * Test the RAM on the ethernet card. 332 */ 333 334 void 335 ea_ramtest(struct seeq8005_softc *sc) 336 { 337 bus_space_tag_t iot = sc->sc_iot; 338 bus_space_handle_t ioh = sc->sc_ioh; 339 int loop; 340 u_int sum = 0; 341 342 /* 343 * Test the buffer memory on the board. 344 * Write simple pattens to it and read them back. 345 */ 346 347 /* Set up the whole buffer RAM for writing */ 348 349 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 350 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 351 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 352 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 353 354 #define SEEQ_RAMTEST_LOOP(value) \ 355 do { \ 356 /* Set the write start address and write a pattern */ \ 357 ea_writebuf(sc, NULL, 0x0000, 0); \ 358 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 359 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 360 \ 361 /* Set the read start address and verify the pattern */ \ 362 ea_readbuf(sc, NULL, 0x0000, 0); \ 363 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 364 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 365 ++sum; \ 366 } while (/*CONSTCOND*/0) 367 368 SEEQ_RAMTEST_LOOP(loop); 369 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 370 SEEQ_RAMTEST_LOOP(0xaa55); 371 SEEQ_RAMTEST_LOOP(0x55aa); 372 373 /* Report */ 374 375 if (sum > 0) 376 aprint_error_dev(sc->sc_dev, 377 "buffer RAM failed self test, %d faults\n", sum); 378 } 379 380 381 /* 382 * Stop the tx interface. 383 * 384 * Returns 0 if the tx was already stopped or 1 if it was active 385 */ 386 387 static int 388 ea_stoptx(struct seeq8005_softc *sc) 389 { 390 bus_space_tag_t iot = sc->sc_iot; 391 bus_space_handle_t ioh = sc->sc_ioh; 392 int timeout; 393 int status; 394 395 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 396 397 sc->sc_enabled = 0; 398 399 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 400 if (!(status & SEEQ_STATUS_TX_ON)) 401 return 0; 402 403 /* Stop any tx and wait for confirmation */ 404 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 405 sc->sc_command | SEEQ_CMD_TX_OFF); 406 407 timeout = 20000; 408 do { 409 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 410 delay(1); 411 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 412 if (timeout == 0) 413 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 414 device_xname(sc->sc_dev)); 415 416 /* Clear any pending tx interrupt */ 417 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 418 sc->sc_command | SEEQ_CMD_TX_INTACK); 419 return 1; 420 } 421 422 423 /* 424 * Stop the rx interface. 425 * 426 * Returns 0 if the tx was already stopped or 1 if it was active 427 */ 428 429 static int 430 ea_stoprx(struct seeq8005_softc *sc) 431 { 432 bus_space_tag_t iot = sc->sc_iot; 433 bus_space_handle_t ioh = sc->sc_ioh; 434 int timeout; 435 int status; 436 437 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 438 439 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 440 if (!(status & SEEQ_STATUS_RX_ON)) 441 return 0; 442 443 /* Stop any rx and wait for confirmation */ 444 445 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 446 sc->sc_command | SEEQ_CMD_RX_OFF); 447 448 timeout = 20000; 449 do { 450 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 451 delay(1); 452 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 453 if (timeout == 0) 454 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 455 device_xname(sc->sc_dev)); 456 457 /* Clear any pending rx interrupt */ 458 459 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 460 sc->sc_command | SEEQ_CMD_RX_INTACK); 461 return 1; 462 } 463 464 465 /* 466 * Stop interface. 467 * Stop all IO and shut the interface down 468 */ 469 470 /* ARGSUSED */ 471 static void 472 ea_stop(struct ifnet *ifp, int disable) 473 { 474 struct seeq8005_softc *sc = ifp->if_softc; 475 bus_space_tag_t iot = sc->sc_iot; 476 bus_space_handle_t ioh = sc->sc_ioh; 477 478 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 479 480 /* Stop all IO */ 481 ea_stoptx(sc); 482 ea_stoprx(sc); 483 484 /* Disable rx and tx interrupts */ 485 sc->sc_command &= ~(SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 486 487 /* Clear any pending interrupts */ 488 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 489 sc->sc_command | SEEQ_CMD_RX_INTACK | SEEQ_CMD_TX_INTACK | 490 SEEQ_CMD_DMA_INTACK | SEEQ_CMD_BW_INTACK); 491 492 if (sc->sc_variant == SEEQ_8004) { 493 /* Put the chip to sleep */ 494 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 495 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 496 sc->sc_config3 | SEEQ_CFG3_SLEEP); 497 } 498 499 /* Cancel any watchdog timer */ 500 sc->sc_ethercom.ec_if.if_timer = 0; 501 } 502 503 504 /* 505 * Reset the chip 506 * Following this the software registers are reset 507 */ 508 509 static void 510 ea_chipreset(struct seeq8005_softc *sc) 511 { 512 bus_space_tag_t iot = sc->sc_iot; 513 bus_space_handle_t ioh = sc->sc_ioh; 514 515 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 516 517 /* Reset the controller. Min of 4us delay here */ 518 519 /* 520 * This can be called before we know whether the chip is in 8- or 521 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 522 * harmless in 8-bit mode, so we do that second. 523 */ 524 525 /* In 16-bit mode, this will munge the PreamSelect bit. */ 526 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 527 delay(4); 528 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 529 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 530 delay(4); 531 532 sc->sc_command = 0; 533 sc->sc_config1 = 0; 534 sc->sc_config2 = 0; 535 sc->sc_config3 = 0; 536 } 537 538 539 /* 540 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 541 * switching the FIFO from write to read. We also use it when changing 542 * the address for writes. 543 */ 544 static void 545 ea_await_fifo_empty(struct seeq8005_softc *sc) 546 { 547 bus_space_tag_t iot = sc->sc_iot; 548 bus_space_handle_t ioh = sc->sc_ioh; 549 int timeout; 550 551 timeout = 20000; 552 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 553 SEEQ_STATUS_FIFO_DIR) != 0) 554 return; /* FIFO is reading anyway. */ 555 while (--timeout > 0) 556 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 557 SEEQ_STATUS_FIFO_EMPTY) 558 return; 559 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", 560 device_xname(sc->sc_dev)); 561 } 562 563 /* 564 * Wait for the DMA FIFO to fill before reading from it. 565 */ 566 static void 567 ea_await_fifo_full(struct seeq8005_softc *sc) 568 { 569 bus_space_tag_t iot = sc->sc_iot; 570 bus_space_handle_t ioh = sc->sc_ioh; 571 int timeout; 572 573 timeout = 20000; 574 while (--timeout > 0) 575 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 576 SEEQ_STATUS_FIFO_FULL) 577 return; 578 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", device_xname(sc->sc_dev)); 579 } 580 581 /* 582 * write to the buffer memory on the interface 583 * 584 * The buffer address is set to ADDR. 585 * If len != 0 then data is copied from the address starting at buf 586 * to the interface buffer. 587 * BUF must be usable as a uint16_t *. 588 * If LEN is odd, it must be safe to overwrite one extra byte. 589 */ 590 591 static void 592 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 593 { 594 bus_space_tag_t iot = sc->sc_iot; 595 bus_space_handle_t ioh = sc->sc_ioh; 596 597 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 598 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 599 600 #ifdef DIAGNOSTIC 601 if (__predict_false(!ALIGNED_POINTER(buf, uint16_t))) 602 panic("%s: unaligned writebuf", device_xname(sc->sc_dev)); 603 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 604 panic("%s: writebuf out of range", device_xname(sc->sc_dev)); 605 #endif 606 607 if (addr != -1) { 608 ea_await_fifo_empty(sc); 609 610 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 611 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 612 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 613 614 ea_await_fifo_empty(sc); 615 616 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 617 } 618 619 if (len > 0) { 620 if (sc->sc_flags & SF_8BIT) 621 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 622 (uint8_t *)buf, len); 623 else 624 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 625 /* LINTED: alignment checked above */ 626 (uint16_t *)buf, len / 2); 627 } 628 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 629 /* Write the last byte */ 630 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, buf[len - 1]); 631 } 632 /* Leave FIFO to empty in the background */ 633 } 634 635 636 /* 637 * read from the buffer memory on the interface 638 * 639 * The buffer address is set to ADDR. 640 * If len != 0 then data is copied from the interface buffer to the 641 * address starting at buf. 642 * BUF must be usable as a uint16_t *. 643 * If LEN is odd, it must be safe to overwrite one extra byte. 644 */ 645 646 static void 647 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 648 { 649 bus_space_tag_t iot = sc->sc_iot; 650 bus_space_handle_t ioh = sc->sc_ioh; 651 int runup; 652 653 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 654 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 655 656 #ifdef DIAGNOSTIC 657 if (__predict_false(!ALIGNED_POINTER(buf, uint16_t))) 658 panic("%s: unaligned readbuf", device_xname(sc->sc_dev)); 659 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 660 panic("%s: readbuf out of range", device_xname(sc->sc_dev)); 661 #endif 662 663 if (addr != -1) { 664 /* 665 * SEEQ 80C04 bug: 666 * Starting reading from certain addresses seems to cause 667 * us to get bogus results, so we avoid them. 668 */ 669 runup = 0; 670 if (sc->sc_variant == SEEQ_8004 && 671 ((addr & 0x00ff) == 0x00ea || 672 (addr & 0x00ff) == 0x00ee || 673 (addr & 0x00ff) == 0x00f0)) 674 runup = (addr & 0x00ff) - 0x00e8; 675 676 ea_await_fifo_empty(sc); 677 678 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 679 680 /* 681 * 80C04 bug workaround. I found this in the old arm32 "eb" 682 * driver. I've no idea what it does, but it seems to stop 683 * the chip mangling data so often. 684 */ 685 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 686 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 687 ea_await_fifo_empty(sc); 688 689 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 690 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 691 sc->sc_command | SEEQ_CMD_FIFO_READ); 692 693 ea_await_fifo_full(sc); 694 while (runup > 0) { 695 /* LINTED: Reading a volatile _does_ have an effect */ 696 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 697 runup -= 2; 698 } 699 } 700 701 if (len > 0) { 702 if (sc->sc_flags & SF_8BIT) 703 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 704 (uint8_t *)buf, len); 705 else 706 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 707 /* LINTED: pointer alignment checked above */ 708 (uint16_t *)buf, len / 2); 709 } 710 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 711 /* Read the last byte */ 712 buf[len - 1] = bus_space_read_2(iot, ioh, SEEQ_BUFWIN); 713 } 714 } 715 716 static void 717 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 718 { 719 720 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 721 sc->sc_config1 | bufcode); 722 } 723 724 /* Must be called at splnet */ 725 static void 726 ea_set_address(struct seeq8005_softc *sc, int which, const uint8_t *ea) 727 { 728 int i; 729 730 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 731 for (i = 0; i < ETHER_ADDR_LEN; ++i) 732 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, ea[i]); 733 } 734 735 /* 736 * Initialize interface. 737 * 738 * This should leave the interface in a state for packet reception and 739 * transmission. 740 */ 741 742 static int 743 ea_init(struct ifnet *ifp) 744 { 745 struct seeq8005_softc *sc = ifp->if_softc; 746 bus_space_tag_t iot = sc->sc_iot; 747 bus_space_handle_t ioh = sc->sc_ioh; 748 int s; 749 750 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 751 752 s = splnet(); 753 754 /* First, reset the board. */ 755 756 ea_chipreset(sc); 757 758 /* Set up defaults for the registers */ 759 760 sc->sc_command = 0; 761 sc->sc_config1 = 0; 762 #if BYTE_ORDER == BIG_ENDIAN 763 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 764 #else 765 sc->sc_config2 = 0; 766 #endif 767 sc->sc_config3 = 0; 768 769 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 770 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 771 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 772 if (sc->sc_variant == SEEQ_8004) { 773 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 774 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 775 } 776 777 /* Write the station address - the receiver must be off */ 778 ea_set_address(sc, 0, (const uint8_t *)CLLADDR(ifp->if_sadl)); 779 780 /* Split board memory into Rx and Tx. */ 781 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 782 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 783 784 if (sc->sc_variant == SEEQ_8004) { 785 /* Make the interface IFF_SIMPLEX. */ 786 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 787 /* Enable reception of long packets (for vlan(4)). */ 788 sc->sc_config2 |= SEEQ_CFG2_PASS_LONGSHORT; 789 } 790 791 /* Configure rx. */ 792 ea_mc_reset(sc); 793 if (ifp->if_flags & IFF_PROMISC) 794 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 795 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 796 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 797 else 798 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 799 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 800 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 801 802 /* Setup the Rx pointers */ 803 sc->sc_rx_ptr = sc->sc_tx_bufsize; 804 805 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 806 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 807 808 809 /* Place a NULL header at the beginning of the receive area */ 810 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 811 812 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 813 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 814 815 816 /* Configure TX. */ 817 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 818 819 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 820 821 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 822 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 823 824 /* Reset tx buffer pointers */ 825 sc->sc_tx_cur = 0; 826 sc->sc_tx_used = 0; 827 sc->sc_tx_next = 0; 828 829 /* Place a NULL header at the beginning of the transmit area */ 830 ea_writebuf(sc, NULL, 0x0000, 0); 831 832 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 833 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 834 835 sc->sc_command |= SEEQ_CMD_TX_INTEN; 836 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 837 838 /* Turn on Rx */ 839 sc->sc_command |= SEEQ_CMD_RX_INTEN; 840 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 841 sc->sc_command | SEEQ_CMD_RX_ON); 842 843 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 844 845 846 /* Set flags appropriately. */ 847 ifp->if_flags |= IFF_RUNNING; 848 ifp->if_flags &= ~IFF_OACTIVE; 849 sc->sc_enabled = 1; 850 851 /* And start output. */ 852 ea_start(ifp); 853 854 splx(s); 855 return 0; 856 } 857 858 /* 859 * Start output on interface. Get datagrams from the queue and output them, 860 * giving the receiver a chance between datagrams. Call only from splnet or 861 * interrupt level! 862 */ 863 864 static void 865 ea_start(struct ifnet *ifp) 866 { 867 struct seeq8005_softc *sc = ifp->if_softc; 868 int s; 869 870 s = splnet(); 871 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 872 873 /* 874 * Don't do anything if output is active. seeq8005intr() will call 875 * us (actually ea_txpacket()) back when the card's ready for more 876 * frames. 877 */ 878 if (ifp->if_flags & IFF_OACTIVE) { 879 splx(s); 880 return; 881 } 882 883 /* Mark interface as output active */ 884 885 ifp->if_flags |= IFF_OACTIVE; 886 887 /* tx packets */ 888 889 ea_txpacket(sc); 890 splx(s); 891 } 892 893 894 /* 895 * Transfer a packet to the interface buffer and start transmission 896 * 897 * Called at splnet() 898 */ 899 900 static void 901 ea_txpacket(struct seeq8005_softc *sc) 902 { 903 bus_space_tag_t iot = sc->sc_iot; 904 bus_space_handle_t ioh = sc->sc_ioh; 905 struct mbuf *m0; 906 struct ifnet *ifp; 907 908 ifp = &sc->sc_ethercom.ec_if; 909 910 /* Dequeue the next packet. */ 911 IFQ_DEQUEUE(&ifp->if_snd, m0); 912 913 /* If there's nothing to send, return. */ 914 if (m0 == NULL) { 915 ifp->if_flags &= ~IFF_OACTIVE; 916 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 917 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 918 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 919 return; 920 } 921 922 /* Give the packet to the bpf, if any. */ 923 bpf_mtap(ifp, m0, BPF_D_OUT); 924 925 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 926 927 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 928 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 929 930 ea_writembuf(sc, m0, 0x0000); 931 m_freem(m0); 932 933 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 934 935 /* Now transmit the datagram. */ 936 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 937 sc->sc_command | SEEQ_CMD_TX_ON); 938 939 /* Make sure we notice if the chip goes silent on us. */ 940 ifp->if_timer = 5; 941 942 DPRINTF(SEEQ_DEBUG_TX, 943 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 944 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 945 } 946 947 /* 948 * Copy a packet from an mbuf to the transmit buffer on the card. 949 * 950 * Puts a valid Tx header at the start of the packet, and a null header at 951 * the end. 952 */ 953 static int 954 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 955 { 956 struct mbuf *m; 957 int len, nextpacket; 958 uint8_t hdr[4]; 959 960 /* 961 * Copy the datagram to the packet buffer. 962 */ 963 len = 0; 964 for (m = m0; m; m = m->m_next) { 965 if (m->m_len == 0) 966 continue; 967 ea_writebuf(sc, mtod(m, u_char *), bufstart + 4 + len, 968 m->m_len); 969 len += m->m_len; 970 } 971 972 if (len < ETHER_MIN_LEN) { 973 ea_writebuf(sc, padbuf, bufstart + 4 + len, 974 ETHER_MIN_LEN - len); 975 len = ETHER_MIN_LEN; 976 } 977 978 /* Follow it with a NULL packet header */ 979 memset(hdr, 0, 4); 980 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 981 982 /* Ok we now have a packet len bytes long in our packet buffer */ 983 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 984 985 /* Write the packet header */ 986 nextpacket = bufstart + len + 4; 987 hdr[0] = (nextpacket >> 8) & 0xff; 988 hdr[1] = nextpacket & 0xff; 989 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 990 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 991 hdr[3] = 0; /* Status byte -- will be updated by hardware. */ 992 ea_writebuf(sc, hdr, bufstart, 4); 993 994 return len; 995 } 996 997 /* 998 * Ethernet controller interrupt. 999 */ 1000 1001 int 1002 seeq8005intr(void *arg) 1003 { 1004 struct seeq8005_softc *sc = arg; 1005 bus_space_tag_t iot = sc->sc_iot; 1006 bus_space_handle_t ioh = sc->sc_ioh; 1007 int status, handled; 1008 1009 handled = 0; 1010 1011 /* Get the controller status */ 1012 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 1013 1014 /* Tx interrupt ? */ 1015 if (status & SEEQ_STATUS_TX_INT) { 1016 handled = 1; 1017 1018 /* Acknowledge the interrupt */ 1019 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1020 sc->sc_command | SEEQ_CMD_TX_INTACK); 1021 1022 ea_txint(sc); 1023 } 1024 1025 1026 /* Rx interrupt ? */ 1027 if (status & SEEQ_STATUS_RX_INT) { 1028 handled = 1; 1029 1030 /* Acknowledge the interrupt */ 1031 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1032 sc->sc_command | SEEQ_CMD_RX_INTACK); 1033 1034 /* Processes the received packets */ 1035 ea_rxint(sc); 1036 } 1037 1038 if (handled) 1039 rnd_add_uint32(&sc->rnd_source, status); 1040 1041 return handled; 1042 } 1043 1044 static void 1045 ea_txint(struct seeq8005_softc *sc) 1046 { 1047 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1048 bus_space_tag_t iot = sc->sc_iot; 1049 bus_space_handle_t ioh = sc->sc_ioh; 1050 uint8_t txhdr[4]; 1051 u_int txstatus; 1052 1053 ea_readbuf(sc, txhdr, 0x0000, 4); 1054 1055 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1056 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1057 txstatus = txhdr[3]; 1058 1059 /* 1060 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1061 * one collision. On the 8004 we can find out exactly how many 1062 * collisions occurred. 1063 * 1064 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1065 * completed. 1066 * 1067 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1068 * occurred and the packet transmission was aborted. 1069 * This situation is untested as present. 1070 * 1071 * The SEEQ_TXSTAT_BABBLE is untested as it should only be set 1072 * when we deliberately transmit oversized packets (e.g. for 1073 * 802.1Q). 1074 */ 1075 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1076 switch (sc->sc_variant) { 1077 case SEEQ_8004: { 1078 int colls; 1079 1080 /* 1081 * The 8004 contains a 4 bit collision count 1082 * in the status register. 1083 */ 1084 1085 /* This appears to be broken on 80C04.AE */ 1086 /* ifp->if_collisions += 1087 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1088 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1089 1090 /* Use the TX Collision register */ 1091 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1092 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1093 ifp->if_collisions += colls; 1094 break; 1095 } 1096 case SEEQ_8005: 1097 /* We known there was at least 1 collision */ 1098 ifp->if_collisions++; 1099 break; 1100 } 1101 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1102 printf("seeq_intr: col16 %x\n", txstatus); 1103 ifp->if_collisions += 16; 1104 ifp->if_oerrors++; 1105 } 1106 1107 /* Have we completed transmission on the packet ? */ 1108 if (txstatus & SEEQ_PKTSTAT_DONE) { 1109 /* Clear watchdog timer. */ 1110 ifp->if_timer = 0; 1111 ifp->if_flags &= ~IFF_OACTIVE; 1112 1113 /* Update stats */ 1114 ifp->if_opackets++; 1115 1116 /* Tx next packet */ 1117 1118 ea_txpacket(sc); 1119 } 1120 } 1121 1122 static void 1123 ea_rxint(struct seeq8005_softc *sc) 1124 { 1125 bus_space_tag_t iot = sc->sc_iot; 1126 bus_space_handle_t ioh = sc->sc_ioh; 1127 u_int addr; 1128 int len; 1129 int ctrl; 1130 int ptr; 1131 int status; 1132 uint8_t rxhdr[4]; 1133 struct ifnet *ifp; 1134 1135 ifp = &sc->sc_ethercom.ec_if; 1136 1137 1138 /* We start from the last rx pointer position */ 1139 addr = sc->sc_rx_ptr; 1140 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1141 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1142 1143 do { 1144 /* Read rx header */ 1145 ea_readbuf(sc, rxhdr, addr, 4); 1146 1147 /* Split the packet header */ 1148 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1149 ctrl = rxhdr[2]; 1150 status = rxhdr[3]; 1151 1152 DPRINTF(SEEQ_DEBUG_RX, 1153 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1154 addr, ptr, ctrl, status)); 1155 1156 /* Zero packet ptr ? then must be null header so exit */ 1157 if (ptr == 0) break; 1158 1159 /* Sanity-check the next-packet pointer and flags. */ 1160 if (__predict_false(ptr < sc->sc_tx_bufsize || 1161 (ctrl & SEEQ_PKTCMD_TX))) { 1162 ++ifp->if_ierrors; 1163 log(LOG_ERR, 1164 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1165 device_xname(sc->sc_dev), addr, ptr); 1166 ea_init(ifp); 1167 return; 1168 } 1169 1170 /* Get packet length */ 1171 len = (ptr - addr) - 4; 1172 1173 if (len < 0) 1174 len += sc->sc_rx_bufsize; 1175 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1176 1177 /* Has the packet rx completed ? if not then exit */ 1178 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1179 break; 1180 1181 /* 1182 * Did we have any errors? then note error and go to 1183 * next packet 1184 */ 1185 if (__predict_false(status & 1186 (SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR | 1187 SEEQ_RXSTAT_SHORT_FRAME))) { 1188 ++ifp->if_ierrors; 1189 log(LOG_WARNING, 1190 "%s: rx packet error at %04x (err=%02x)\n", 1191 device_xname(sc->sc_dev), addr, status & 0x0f); 1192 /* XXX shouldn't need to reset if it's genuine. */ 1193 ea_init(ifp); 1194 return; 1195 } 1196 /* 1197 * Is the packet too big? We allow slightly oversize packets 1198 * for vlan(4) and tcpdump purposes, but the rest of the world 1199 * wants incoming packets in a single mbuf cluster. 1200 */ 1201 if (__predict_false(len > MCLBYTES)) { 1202 ++ifp->if_ierrors; 1203 log(LOG_ERR, 1204 "%s: rx packet size error at %04x (len=%d)\n", 1205 device_xname(sc->sc_dev), addr, len); 1206 ea_init(ifp); 1207 return; 1208 } 1209 1210 /* Pass data up to upper levels. */ 1211 ea_read(sc, addr + 4, len); 1212 1213 addr = ptr; 1214 } while (len != 0); 1215 1216 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1217 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1218 1219 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1220 1221 /* Store new rx pointer */ 1222 sc->sc_rx_ptr = addr; 1223 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1224 1225 /* Make sure the receiver is on */ 1226 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1227 sc->sc_command | SEEQ_CMD_RX_ON); 1228 } 1229 1230 1231 /* 1232 * Pass a packet up to the higher levels. 1233 */ 1234 1235 static void 1236 ea_read(struct seeq8005_softc *sc, int addr, int len) 1237 { 1238 struct mbuf *m; 1239 struct ifnet *ifp; 1240 1241 ifp = &sc->sc_ethercom.ec_if; 1242 1243 /* Pull packet off interface. */ 1244 m = ea_get(sc, addr, len, ifp); 1245 if (m == NULL) 1246 return; 1247 1248 if_percpuq_enqueue(ifp->if_percpuq, m); 1249 } 1250 1251 /* 1252 * Pull read data off a interface. Len is length of data, with local net 1253 * header stripped. We copy the data into mbufs. When full cluster sized 1254 * units are present we copy into clusters. 1255 */ 1256 1257 struct mbuf * 1258 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1259 { 1260 struct mbuf *top, **mp, *m; 1261 int len; 1262 u_int cp, epkt; 1263 1264 cp = addr; 1265 epkt = cp + totlen; 1266 1267 MGETHDR(m, M_DONTWAIT, MT_DATA); 1268 if (m == NULL) 1269 return NULL; 1270 m_set_rcvif(m, ifp); 1271 m->m_pkthdr.len = totlen; 1272 m->m_len = MHLEN; 1273 top = NULL; 1274 mp = ⊤ 1275 1276 while (totlen > 0) { 1277 if (top) { 1278 MGET(m, M_DONTWAIT, MT_DATA); 1279 if (m == NULL) { 1280 m_freem(top); 1281 return NULL; 1282 } 1283 m->m_len = MLEN; 1284 } 1285 len = uimin(totlen, epkt - cp); 1286 if (len >= MINCLSIZE) { 1287 MCLGET(m, M_DONTWAIT); 1288 if (m->m_flags & M_EXT) 1289 m->m_len = len = uimin(len, MCLBYTES); 1290 else 1291 len = m->m_len; 1292 } else { 1293 /* 1294 * Place initial small packet/header at end of mbuf. 1295 */ 1296 if (len < m->m_len) { 1297 if (top == NULL && len + max_linkhdr <= m->m_len) 1298 m->m_data += max_linkhdr; 1299 m->m_len = len; 1300 } else 1301 len = m->m_len; 1302 } 1303 if (top == NULL) { 1304 /* Make sure the payload is aligned */ 1305 char *newdata = (char *) 1306 ALIGN((char*)m->m_data + 1307 sizeof(struct ether_header)) - 1308 sizeof(struct ether_header); 1309 len -= newdata - m->m_data; 1310 m->m_len = len; 1311 m->m_data = newdata; 1312 } 1313 ea_readbuf(sc, mtod(m, u_char *), 1314 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1315 len); 1316 cp += len; 1317 *mp = m; 1318 mp = &m->m_next; 1319 totlen -= len; 1320 if (cp == epkt) 1321 cp = addr; 1322 } 1323 1324 return top; 1325 } 1326 1327 /* 1328 * Process an ioctl request. Mostly boilerplate. 1329 */ 1330 static int 1331 ea_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1332 { 1333 struct seeq8005_softc *sc = ifp->if_softc; 1334 int s, error = 0; 1335 1336 s = splnet(); 1337 switch (cmd) { 1338 1339 default: 1340 error = ether_ioctl(ifp, cmd, data); 1341 if (error == ENETRESET) { 1342 /* 1343 * Multicast list has changed; set the hardware filter 1344 * accordingly. 1345 */ 1346 if (ifp->if_flags & IFF_RUNNING) 1347 ea_mc_reset(sc); 1348 error = 0; 1349 } 1350 break; 1351 } 1352 1353 splx(s); 1354 return error; 1355 } 1356 1357 /* Must be called at splnet() */ 1358 1359 static void 1360 ea_mc_reset(struct seeq8005_softc *sc) 1361 { 1362 1363 switch (sc->sc_variant) { 1364 case SEEQ_8004: 1365 ea_mc_reset_8004(sc); 1366 return; 1367 case SEEQ_8005: 1368 ea_mc_reset_8005(sc); 1369 return; 1370 } 1371 } 1372 1373 static void 1374 ea_mc_reset_8004(struct seeq8005_softc *sc) 1375 { 1376 struct ethercom *ec = &sc->sc_ethercom; 1377 struct ifnet *ifp = &ec->ec_if; 1378 struct ether_multi *enm; 1379 uint32_t crc; 1380 int i; 1381 struct ether_multistep step; 1382 uint8_t af[8]; 1383 1384 /* 1385 * Set up multicast address filter by passing all multicast addresses 1386 * through a crc generator, and then using bits 2 - 7 as an index 1387 * into the 64 bit logical address filter. The high order bits 1388 * selects the word, while the rest of the bits select the bit within 1389 * the word. 1390 */ 1391 1392 if (ifp->if_flags & IFF_PROMISC) { 1393 ifp->if_flags |= IFF_ALLMULTI; 1394 for (i = 0; i < 8; i++) 1395 af[i] = 0xff; 1396 return; 1397 } 1398 for (i = 0; i < 8; i++) 1399 af[i] = 0; 1400 1401 ETHER_LOCK(ec); 1402 ETHER_FIRST_MULTI(step, ec, enm); 1403 while (enm != NULL) { 1404 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1405 sizeof(enm->enm_addrlo)) != 0) { 1406 /* 1407 * We must listen to a range of multicast addresses. 1408 * For now, just accept all multicasts, rather than 1409 * trying to set only those filter bits needed to match 1410 * the range. (At this time, the only use of address 1411 * ranges is for IP multicast routing, for which the 1412 * range is big enough to require all bits set.) 1413 */ 1414 ifp->if_flags |= IFF_ALLMULTI; 1415 for (i = 0; i < 8; i++) 1416 af[i] = 0xff; 1417 break; 1418 } 1419 1420 crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1421 1422 /* Just want the 6 most significant bits. */ 1423 crc = (crc >> 2) & 0x3f; 1424 1425 /* Turn on the corresponding bit in the filter. */ 1426 af[crc >> 3] |= 1 << (crc & 0x7); 1427 1428 ETHER_NEXT_MULTI(step, enm); 1429 } 1430 ETHER_UNLOCK(ec); 1431 ifp->if_flags &= ~IFF_ALLMULTI; 1432 1433 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1434 for (i = 0; i < 8; ++i) 1435 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1436 SEEQ_BUFWIN, af[i]); 1437 } 1438 1439 static void 1440 ea_mc_reset_8005(struct seeq8005_softc *sc) 1441 { 1442 struct ethercom *ec = &sc->sc_ethercom; 1443 struct ether_multi *enm; 1444 struct ether_multistep step; 1445 int naddr, maxaddrs; 1446 1447 naddr = 0; 1448 maxaddrs = 5; 1449 ETHER_LOCK(ec); 1450 ETHER_FIRST_MULTI(step, ec, enm); 1451 while (enm != NULL) { 1452 /* Have we got space? */ 1453 if (naddr >= maxaddrs || 1454 memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1455 ec->ec_if.if_flags |= IFF_ALLMULTI; 1456 ETHER_UNLOCK(ec); 1457 ea_ioctl(&ec->ec_if, SIOCSIFFLAGS, NULL); 1458 return; 1459 } 1460 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1461 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1462 naddr++; 1463 ETHER_NEXT_MULTI(step, enm); 1464 } 1465 ETHER_UNLOCK(ec); 1466 1467 for (; naddr < maxaddrs; naddr++) 1468 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1469 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1470 sc->sc_config1); 1471 } 1472 1473 /* 1474 * Device timeout routine. 1475 */ 1476 1477 static void 1478 ea_watchdog(struct ifnet *ifp) 1479 { 1480 struct seeq8005_softc *sc = ifp->if_softc; 1481 1482 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1483 device_xname(sc->sc_dev), 1484 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1485 ifp->if_oerrors++; 1486 1487 /* Kick the interface */ 1488 1489 ea_init(ifp); 1490 1491 ifp->if_timer = 0; 1492 } 1493 1494 /* End of seeq8005.c */ 1495
Indexes created Mon Sep 29 21:09:56 GMT 2025